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* configs: Don't use SPI_FLASH_BAR as defaultVignesh R2019-02-0791-90/+6
| | | | | | | | | | | | | | | Now that new SPI NOR layer uses stateless 4 byte opcodes by default, don't enable SPI_FLASH_BAR. For SPI controllers that cannot support 4-byte addressing, (stm32_qspi.c, fsl_qspi.c, mtk_qspi.c, ich.c, renesas_rpc_spi.c) add an imply clause to enable SPI_FLASH_BAR so as to not break functionality. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
* configs: Remove SF_DUAL_FLASHVignesh R2019-02-0717-108/+0
| | | | | | | | | | | SF_DUAL_FLASH claims to enable support for SF_DUAL_STACKED_FLASH and SF_DUAL_PARALLEL_FLASH. But, in current U-Boot code, grepping for above enums yield no user and therefore support seems to be incomplete. Remove these configs so as to avoid confusion. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
* spl: Kconfig: Enable SPI_FLASH_TINY by default for SPLVignesh R2019-02-071-0/+1
| | | | | | | | | | | | | | | SPL only needs to be able to read from SPI Flash to load next stage and does not really need write/erase etc. Therefore in order to reduce SPI Flash code size in SPL, enable SPI_FLASH_TINY, that only supports reading from SPI flash, as default. Note: Since, SPI_FLASH_TINY does not support SPI_FLASH_BAR, SPI_FLASH_TINY is not enabled for boards with SPI controllers that cannot support 4 byte addressing. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
* mtd: spi: Add lightweight SPI flash stack for SPLVignesh R2019-02-076-264/+1126
| | | | | | | | | | | | | | | | | Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
* mtd: spi: Remove unused filesVignesh R2019-02-072-1548/+0
| | | | | | | | | | | | spi_flash and spi_flash_ids are no longer needed after SPI NOR migration. Remove them. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
* mtd: spi: Switch to new SPI NOR frameworkVignesh R2019-02-079-365/+113
| | | | | | | | | | | | | Switch spi_flash_* interfaces to call into new SPI NOR framework via MTD layer. Fix up sf_dataflash to work in legacy way. And update sandbox to use new interfaces/definitions Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
* mtd: spi: sf_probe: Add "jedec, spi-nor" compatible stringVignesh R2019-02-071-0/+1
| | | | | | | | | | | | | Linux uses "jedec,spi-nor" as compatible string for JEDEC compatible SPI Flash device nodes. Therefore make U-Boot also to look for the same compatible string so that we can use Linux DTS files as is. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
* mtd: spi: spi-nor-core: Add back U-Boot specific featuresVignesh R2019-02-072-3/+168
| | | | | | | | | For legacy reasons, we will have to keep around U-Boot specific SPI_FLASH_BAR and SPI_TX_BYTE. Add them back to the new framework Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
* mtd: spi: spi-nor-core: Add SFDP supportVignesh R2019-02-073-7/+649
| | | | | | | | | | | | Sync Serial Flash Discoverable Parameters (SFDP) parsing support from Linux. This allows auto detection and configuration of Flash parameters. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
* mtd: spi: spi-nor-core: Add 4 Byte addressing supportVignesh R2019-02-071-0/+141
| | | | | | | | | | | | | | Sync changes from Linux SPI NOR framework to add 4 byte addressing support. This is required in order to support flashes like MT35x that no longer support legacy Bank Address Register(BAR) way of accessing >16MB region. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
* mtd: spi: spi-nor-core: Add SPI MEM supportVignesh R2019-02-071-4/+93
| | | | | | | | | | | | | | | | | Many SPI controllers have special MMIO interfaces which provide accelerated read/write access but require knowledge of flash parameters to make use of it. Recent spi-mem layer provides a way to support such controllers. Therefore, add spi-mem support to spi-nor-core as a way to support SPI controllers with MMIO interface. SPI MEM layer takes care of translating spi_mem_ops to spi_xfer()s in case of legacy SPI controllers. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
* mtd: spi: Port SPI NOR framework from LinuxVignesh R2019-02-073-0/+2158
| | | | | | | | | | | | | | | | | Current U-Boot SPI NOR support (sf layer) is quite outdated as it does not support 4 byte addressing opcodes, SFDP table parsing and different types of quad mode enable sequences. Many newer flashes no longer support BANK registers used by sf layer to a access >16MB of flash address space. So, sync SPI NOR framework from Linux v4.19 that supports all the above features. Start with basic sync up that brings in basic framework subsequent commits will bring in more features. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
* sh: bitops: add hweight*() macrosVignesh R2019-02-071-0/+4
| | | | | | | Add hweight*() macros required for moving to new SF layer Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* spi: Add non DM version of SPI_MEMVignesh R2019-02-073-2/+108
| | | | | | | | | | | | Add non DM version of SPI_MEM to support easy migration to new SPI NOR framework. This can be removed once DM_SPI conversion is complete. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
* spi: spi-mem: Claim SPI bus before spi mem accessVignesh R2019-02-071-5/+8
| | | | | | | | | | | | | | It is necessary to call spi_claim_bus() before starting any SPI transactions and this restriction would also apply when calling spi-mem operations. Therefore claim and release bus before requesting transfer via exec_op. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
* spi: spi-mem: Extend spi_mem_adjust_op_size() to honor max xfer sizeVignesh R2019-02-071-0/+19
| | | | | | | | | | | | Extend spi_mem_adjust_op_size() to take spi->max_write_size and spi->max_read_size into account. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
* spi: spi-mem: Allow use of spi_mem_exec_op for all SPI modesVignesh R2019-02-071-9/+0
| | | | | | | | | | | | SPI controllers support all types of SPI modes including dual/quad bus widths. Therefore remove constraint wrt SPI mode from spi-mem layer. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
* bitops: Fix GENMASK definition for SandboxVignesh R2019-02-071-0/+5
| | | | | | | | | | | | | | | | | | | In arch/sandbox/include/asm/types.h we have Therefore for 32 bit Sandbox build BITS_PER_LONG turns out to be 32 as CONFIG_PHYS64 is not set This messes up the current logic of GENMASK macro due to mismatch b/w size of unsigned long (64 bit) and that of BITS_PER_LONG. Fix this by using CONFIG_SANDBOX_BITS_PER_LONG which is set to 64/32 based on the host machine on which its being compiled. Without this patch: GENMASK(14,0) => 0x7fffffffffff After this patch: GENMASK(14,0) => 0x7fff Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* configs: Move CONFIG_SPI_FLASH into defconfigsVignesh R2019-02-0732-9/+24
| | | | | | | | | Completely move CONFIG_SPI_FLASH from remaining board header files to defconfigs Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
* Merge tag 'for-master-20190201' of git://git.denx.de/u-boot-rockchipTom Rini2019-02-02109-6775/+7516
|\ | | | | | | | | | | | | | | u-boot-rockchip changes for 2019.04-rc1: * support for Chromebook Bob * full pinctrl driver using DTS properties * documentation improvements * I2S support for some Rockchip SoCs
| * rockchip: rk3399: spl: ensure that debug_uart_init is calledPhilipp Tomsich2019-02-011-2/+2
| | | | | | | | | | | | | | | | | | | | With the latest changes to add support for the Chromebook Bob, initialisation through debug_uart_init() did no longer get called for other targets. Fix this, by moving debug_uart_init() out of the Bob-specific Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: rk3399-puma: enable SPL_ATF_NO_PLATFORM_PARAMPhilipp Tomsich2019-02-011-0/+1
| | | | | | | | | | | | | | | | As we're working on the next update of our ATF (and U-Boot and the ATF are out-of-sync), let's temporarily enable SPL_ATF_NO_PLATFORM_PARAM to reduce compatibility issues. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * pinctrl: Kconfig: fix missing include of rockchip/KconfigPhilipp Tomsich2019-02-011-0/+1
| | | | | | | | | | | | | | | | After the merge of the new, generic pinctrl-code, the include for rockchip/Kconfig was missing. Add it here, so we can select the pinctrl-driver for SPL. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * pinctrl: Kconfig: sort includes alphabeticallyPhilipp Tomsich2019-02-011-5/+5
| | | | | | | | | | | | | | | | To make adding new subdirectories easier, let's enforce alphabetical ordering of the includes of Kconfig files in the respective subdirectories. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: Add MAINTAINER entry for chromebook_speedyPhilipp Tomsich2019-02-011-0/+7
| | | | | | | | | | | | | | | | | | | | | | This adds a MAINTAINER entry for chromebook_speedy. Without this, we get the following warnings from the maintainers check: WARNING: no status info for 'chromebook_minnie' WARNING: no maintainers for 'chromebook_minnie' Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: Add support for chromebook_bobSimon Glass2019-02-0110-3/+215
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bob is a 10-inch chromebook produced by Asus. It has two USB 3.0 type-C ports, 4GB of SDRAM, WiFi and a 1280x800 display. It uses its USB ports for both power and external display. It includes a Chrome OS EC (Cortex-M3) to provide access to the keyboard and battery functions. Support so far includes only: - UART - SDRAM - MMC, SD card - Cros EC (but not keyboard) Not included: - Keyboard - Display - Sound - USB - TPM Bob is quite similar to Kevin, the Samsung Chromebook Plus, but support for this is not provided in this series. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: gru: Add extra device-tree settingsSimon Glass2019-02-013-4/+19
| | | | | | | | | | | | | | | | Add some U-Boot-specific settings. These should really go in the *u-boot.dtsi file, but it seems that rk3399 does not use that yet. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: Implement spl_gpio in the GPIO driverSimon Glass2019-02-012-0/+69
| | | | | | | | | | | | | | | | | | Allow rockchip boards to use GPIOs before driver model is ready. This is really only useful for setting GPIOs to enable the early debug console, if needed on some platforms. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: Move pull-up/down enum into a common fileSimon Glass2019-02-012-7/+7
| | | | | | | | | | | | | | | | | | | | | | At present this enum is only available to rk3288. Move it so that other rockchip SoCs can access it. It is needed for the SPL GPIO driver for rk3999 in a later patch. Also adjust the enum name to lower case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: rk3399: Add ROCKCHIP_DEVICE_SETTINGS to set envSimon Glass2019-02-011-0/+5
| | | | | | | | | | | | | | | | | | Some boards use different stdio environment variables from the default. Provide a #define for this which can be set before including the header file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: Tidy up board include-file orderingSimon Glass2019-02-017-13/+13
| | | | | | | | | | | | | | These board files have inconsistent #include ordering. Fix them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: clk: Add mention of four new clocksSimon Glass2019-02-011-0/+12
| | | | | | | | | | | | | | | | These clocks are needed to get MMC running. We don't actually support setting them yet. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: Add settings for Samsung LPDDR3 4GB SDRAM 1866MHzSimon Glass2019-02-011-0/+1542
| | | | | | | | | | | | | | This memory is used on Bob. Add settings for this, taken from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: Allow booting from SPISimon Glass2019-02-011-0/+3
| | | | | | | | | | | | | | | | The u-boot,spl-boot-device property only allows MMC at present. Add SPI as well for boards that boot from SPI flash. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: Clarify docs on SPI writingSimon Glass2019-02-011-1/+1
| | | | | | | | | | | | | | | | | | We use every second block when creating a SPI image, so update the text to say this explicitly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: evb_rk3399: Tidy up the READMESimon Glass2019-02-011-12/+21
| | | | | | | | | | | | | | | | | | | | | | | | Add mention of a prerequisite needed to build the image. Also adjust the English wording in a few places. Ideally this should move to using binman to produce images, and avoid the manual steps. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: Adjust rk3399 device tree to be closer to linuxSimon Glass2019-02-011-61/+371
| | | | | | | | | | | | | | | | | | | | | | | | This file has changed upstream, with some additions and changes. Move the U-Boot version towards this. Some USB changes seem to be incompatible with how the bindings work on rockchip in U-Boot. Testing is needed to make sure that USB still works correct, and adjust the code (not device tree) if not. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: Bring in device tree files for rk3399-gruSimon Glass2019-02-015-0/+1757
| | | | | | | | | | | | | | Bring in these files from Linux v4.20. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: Drop note about supporting other SoCsSimon Glass2019-02-011-8/+1
| | | | | | | | | | | | | | | | | | Quite a wide range of Rockchip SoCs are supported in mainline U-Boot now, so drop the comment about needing to add more. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: Add mention of other boardsSimon Glass2019-02-011-2/+42
| | | | | | | | | | | | | | | | | | | | At present some Rockchip SoCs and boards are not mentioned in the README. So that people can see which SoCs are supported, expand the list to include everything. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * gpio: Add a simple GPIO API for SPLSimon Glass2019-02-011-0/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | In space-constrained environments or before driver model is available, it is sometimes necessary to set GPIO values. Add an SPL API for this, to allow early board code to change GPIOs. The caller must provide the register address, so that the drivers can be fairly generic. This API can be implemented by GPIO drivers, behind a suitable guard, like #ifdef CONFIG_SPL_BUILD. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * gpio: Use more command-specific enums valuesSimon Glass2019-02-011-14/+23
| | | | | | | | | | | | | | | | | | At present this file uses GPIO_OUTPUT and GPIO_INPUT as its sub-command values. These are pretty generic names. Add a 'C' suffix to avoid possible conflicts. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * clk: Improve debug message in clk_set_default_rates()Simon Glass2019-02-011-2/+2
| | | | | | | | | | | | | | | | | | It is helpful to print the clock number as well as the index, so that this can be looked up in the binding file. Update the debug() statement to do this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * lib: Allow using display_buffer() in SPLSimon Glass2019-02-011-1/+3
| | | | | | | | | | | | | | | | | | At present this function uses printf() format strings that are not supported in SPL, so the output just consists of %llx strings on 64-bit. machines. Fix this by adding a special case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * ARM: dts: rk322x: Correct the uart2 default pin configurationDavid Wu2019-02-011-2/+9
| | | | | | | | | | | | | | | | | | | | To match the iomux setting of uart2 at SPL, correct the uart2 default pin configuration, if not changed, the evb-rk3229 can't output the log message. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * pinctrl: rockchip: Clean the unused rockchip pinctrl driversDavid Wu2019-02-019-6387/+0
| | | | | | | | | | | | | | | | | | | | | | If we used the pinctrl-rockchip driver, these code is not needed, so remove them. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: defconfig: Clean the unused pinctrl configDavid Wu2019-02-0129-43/+20
| | | | | | | | | | | | | | | | | | If we used the pinctrl-rockchip driver, these config is not needed, so remove them. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * pinctrl: rockchip: Add common rockchip pinctrl driverDavid Wu2019-02-0115-100/+2531
| | | | | | | | | | | | | | | | | | | | Use this driver to fit all Rockchip SOCs and to support the desired pinctrl configuration via DTS. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rk3288: chrome: defconfig: Enable FDT for new pinctrl driverDavid Wu2019-02-013-6/+0
| | | | | | | | | | | | | | | | The FDT is requested for new pinctrl driver, disable SPL_OF_PLATDATA and enable SPL_OF_LIBFDT to make FDT be built in. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * ARM: rockchip: Remove the pinctrl request at rk3288-board-splDavid Wu2019-02-011-79/+0
| | | | | | | | | | | | | | | | | | | | If we use the new pinctrl driver, the pinctrl setup will be done by device probe. Remove the pinctrl setup at rk3288-board-spl. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
generated by cgit (git 2.34.1) at 2024-11-19 04:52:25 +0000