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| * arm: sunxi: add initial H616 DTSI and headersJernej Skrabec2021-01-255-0/+938
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit introduces H616 DTSI file and dt-bindings headers needed for device tree files. Files are taken from v3 Linux H616 support submission[1], as the H616 .dtsi file is not merged upstream yet. [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2021-January/632082.html Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * sunxi: Add H616 FEL supportJernej Skrabec2021-01-251-1/+4
| | | | | | | | | | | | | | | | H616 uses different address for reset. Add it. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * sunxi: Add support for H616 SoCJernej Skrabec2021-01-256-1/+35
| | | | | | | | | | | | | | | | | | | | | | H616 is very similar to H6 so most of the infrastructure can be reused. However, two big differences are that it doesn't have functional SRAM A2 which is usually used for TF-A and it doesn't have ARISC co-processor. It also needs bigger SPL size - 48 KiB. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * mmc: sunxi: Refactor mod clock register offsetAndre Przywara2021-01-251-61/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far the only difference between the various Allwinner MMC controller we are concerned about is the mod clock register offset. This is actually not directly related to the MMC controller IP, but an integration choice, dependent on the SoC this appears in. To avoid becoming trapped with some compatible fallback strings, let's remove the whole struct sunxi_mmc_variant, and replace this with a SoC based choice, which we can derive from the CONFIG_MACH_SUNx_y symbols. This will later simplify H616 support. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * sunxi: Add H616 DRAM supportJernej Skrabec2021-01-257-0/+1325
| | | | | | | | | | | | | | | | | | | | | | | | | | Allwinner H616 supports many types of DRAM. Most notably it supports LPDDR4. However, all commercially available boards at this time use only DDR3, so this commit adds only DDR3 support. Controller and MBUS are very similar to H6 but PHY is completely unknown. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * sunxi: add support for R_I2C on H616Jernej Skrabec2021-01-252-0/+5
| | | | | | | | | | | | | | | | | | | | This port is needed for communication with PMIC. SPL uses it to set DRAM voltage on H616 boards. Reviewed-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * sunxi: add support for H616 uart0Jernej Skrabec2021-01-252-0/+5
| | | | | | | | | | | | | | | | | | This port is used for debug terminal on all known H616 boards. Reviewed-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * sunxi: introduce support for H616 clocksJernej Skrabec2021-01-252-3/+23
| | | | | | | | | | | | | | | | | | | | H616 has mostly the same clocks as H6 with some small differences. Just reuse H6 clocks for H616 and handle differences with macros. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * sunxi: support loading with SPL > 32KBAndre Przywara2021-01-252-3/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | H616 supports and needs bigger SPL than 32 KiB, mostly due to big DRAM driver and need for PMIC configuration, which pulls several drivers which are not needed otherwise. spl_mmc_get_uboot_raw_sector() will now compare pre-configured size with that, reported in SPL header. If size in header is bigger, it will use that value instead. In the process of function rework, also add missing function argument. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Samuel Holland <samuel@sholland.org>
| * sunxi: Add support for I2C on H6 like SoCsJernej Skrabec2021-01-253-1/+31
| | | | | | | | | | | | | | | | | | | | I2C support, especially R_I2C port, will be needed in future. Upcoming support for H616 will need R_I2C to adjust DRAM voltage. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * sunxi: prcm: Add memory map for H6 like SoCsJernej Skrabec2021-01-253-238/+303
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There was no need to have prcm definitions for H6 and similar SoCs till now. However, support R_I2C will be needed soon in SPL. Move old definitions to prcm_sun6i.h and add new ones in prcm_sun50i.h. One of those files will be selected in common prcm.h based on defined macros. This commit doesn't do any functional change. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * i2c: mvtwsi: sunxi: update macroJernej Skrabec2021-01-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | While currently none of the newer Allwinner SoCs currently has I2C support implemented in U-Boot, this will change soon. mvtwsi driver is good as it is for them except one macro. Update it to be ready once I2C support lands for those SoCs. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * mmc: sunxi: Replace H6 ifdefs with H6 gen macroJernej Skrabec2021-01-252-7/+7
| | | | | | | | | | | | | | | | | | | | It turns out that several SoCs share same mmc configuration as H6. In order to lower ifdef clutter replace H6 specific macro with common one. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * sunxi: Introduce common symbol for H6 like SoCsJernej Skrabec2021-01-2510-17/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | It turns out that there are at least 2 other SoCs which have basically the same memory map, similar clocks and other features as H6. It's very likely that we'll see more such SoCs in the future. In order to ease porting to new SoCs and lower ifdef clutter, introduce common symbol for them. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * sunxi: Add support for AXP305 PMICJernej Skrabec2021-01-257-4/+129
| | | | | | | | | | | | | | | | | | | | This PMIC can be found on H616 boards and it's very similar to AXP805 and AXP806. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * sunxi: Properly check for SATAPWR and MACPWRAndre Przywara2021-01-251-12/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The #ifdef CONFIG_xxxPWR conditionals were not working as expected, as string Kconfig symbols are always "defined" from the preprocessor's perspective. This lead to unnecessary calls to the GPIO routines, but also always added a half a second delay to wait for a SATA disk to power up. Many thanks to Peter for pointing this out! Fix this by properly comparing the Kconfig symbols against the empty string. strcmp() would be nicer for this, but GCC does not optimise this away, probably due to our standalone compiler switches. Reported-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Samuel Holland <samuel@sholland.org> # Orange Pi WinPlus Tested-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
| * sunxi: Add support for Orange Pi 3Andre Heider2021-01-254-0/+363
| | | | | | | | | | | | | | | | | | | | | | | | | | | | dts file is taken from Linux 5.11-rc1 tag. The Bluetooth controller of this device ships with a default address, use the new CONFIG_FIXUP_BDADDR option to fix it up. Signed-off-by: Andre Heider <a.heider@gmail.com> Acked-by: Maxime Ripard <mripard@kernel.org> [Updated OrangePi 3 DT, rebase and config update] Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * sunxi: Add support for Tanix TX6Jernej Skrabec2021-01-254-1/+142
| | | | | | | | | | | | | | | | | | | | | | | | This commit adds support for Tanix TX6 TV box, based on H6. It's low end H6 board, with 3 GiB of RAM, eMMC, fast ethernet, USB, IR and other peripherals. DT file is taken from Linux 5.11-rc1 release. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * ARM: dts: sunxi: h6: Update DT filesJernej Skrabec2021-01-257-73/+794
| | | | | | | | | | | | | | | | Updated H6 DT files are based on Linux 5.11-rc1 release. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * net: sun8i-emac: Allow all RGMII PHY modesAndre Przywara2021-01-251-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far all GBit users of the sun8i-emac driver were using the "rgmii" PHY mode, even though this turns out to be wrong. It just worked because the PHY driver doesn't do the proper setup (yet). In fact for most boards the "rgmii-id" or "rgmii-txid" PHY modes are the correct ones. To allow the DTs to describe the phy-mode correctly, and to stay compatible with Linux, at least allow those other RGMII modes in the driver. This avoids breakage if mainline DTs will be synced with U-Boot. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* | Merge tag 'mips-pull-2021-01-24' of ↵Tom Rini2021-01-2561-72/+4477
|\ \ | |/ |/| | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-mips - MIPS: add support for Mediatek MT7620 SoCs
| * MAINTAINERS: add maintainer for MediaTek MIPS platformWeijie Gao2021-01-241-0/+23
| | | | | | | | | | | | | | | | Update maintainer for MediaTek MIPS platform Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * reset: reset-mtmips: add DM_FLAG_PRE_RELOC flagWeijie Gao2021-01-241-0/+1
| | | | | | | | | | | | | | | | | | Add DM_FLAG_PRE_RELOC flag for reset-mtmips to make sure this driver can be probed before relocation even if u-boot,dm-pre-reloc is not present in the dts. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * mmc: mtk-sd: assign plat->cfg.f_max with a correct valueWeijie Gao2021-01-241-0/+2
| | | | | | | | | | | | | | | | | | | | | | Currently this driver does not set the value of plat->cfg.f_max, which results in that MMC framework will always run at the lowest frequency. This patch sets plat->cfg.f_max to the maximum allowed frequency, which equals to the source clock frequency. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * mmc: mtk-sd: add pad control settings for MediaTek MT7620/MT76x8 SoCsWeijie Gao2021-01-241-3/+118
| | | | | | | | | | | | | | | | | | | | | | The driver is missing pad control settings (pad delay and pad conf) for the mt7620 and mt76x8. Although mt76x8 still works well, mt7620 will encounter CRC error on data transfers. This patch adds default pad control settings for mt7620_compat. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * mmc: mtk-sd: fix sclk cycles shift valueWeijie Gao2021-01-241-9/+4
| | | | | | | | | | | | | | | | | | | | | | It turns out that the sclk cycles used by mt7620/mt7628 is the same as other chips (20 bits, 1048576), not 65536. This patch removes sclk_cycle_shift from dev_comp, and uses a macro with a value 20 instead. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * net: add ethernet driver for MediaTek MT7620 SoCWeijie Gao2021-01-243-0/+1235
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds ethernet driver for MediaTek MT7620 SoC. The MT7620 SoC has a built-in ethernet (Frame Engine) and a built-in 7-port switch and two xMII interfaces (can be MII/RMII/RGMII). The port 0-3 of the switch connects to intergrited FE PHYs. Port 4 can be configured to connect to either the intergrited FE PHY, or the xMII. Port 5 always connects to the xMII. Port 6 is the CPU port. This driver supports MT7530 giga switch connects to port 5. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * phy: add USB PHY driver for MediaTek MT7620 SoCWeijie Gao2021-01-243-0/+118
| | | | | | | | | | | | | | This patch adds USB PHY driver for MediaTek MT7620 SoC Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * spi: add spi controller support for MediaTek MT7620 SoCWeijie Gao2021-01-243-0/+289
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds spi controller support for MediaTek MT7620 SoC. The SPI controller supports two chip selects. These two chip selects are implemented as two separate register groups, but they share the same bus (DI/DO/CLK), only CS pins are dedicated for each register group. Appearently these two register groups cannot operates simulataneously so they are implemented as one controller. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * gpio: add GPIO controller driver for MediaTek MT7620 SoCWeijie Gao2021-01-243-0/+155
| | | | | | | | | | | | | | | | This patch adds GPIO controller driver for MediaTek MT7620 SoC Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * watchdog: add watchdog driver for MediaTek MT7620 SoCWeijie Gao2021-01-243-0/+150
| | | | | | | | | | | | | | | | This patch adds watchdog support for the Mediatek MT7620 SoC Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * pinctrl: mtmips: add support for MediaTek MT7620 SoCWeijie Gao2021-01-243-0/+210
| | | | | | | | | | | | | | | | This patch adds pinctrl support for MediaTek MT7620 SoC. The MT7620 SoC supports only pinmux. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * reset: mtmips: add reset controller support for MediaTek MT7620 SoCWeijie Gao2021-01-241-0/+35
| | | | | | | | | | | | | | | | This patch adds reset controller bits definition header file for MediaTek MT7620 SoC Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * clk: add clock driver for MediaTek MT7620 SoCWeijie Gao2021-01-243-0/+200
| | | | | | | | | | | | | | | | | | This patch adds a clock driver for MediaTek MT7620 SoC. This driver provides clock gate control as well as getting clock frequency for CPU/SYS/XTAL and some peripherals. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * serial: add uart driver for MediaTek MT7620 SoCWeijie Gao2021-01-243-0/+267
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds uart support for MediaTek MT7620 and earlier SoCs. The UART used by MT7620 is incompatible with the ns16550a driver. All registers of this UART have different addresses. A special 16-bit register for Divisor Latch is used to set the baudrate instead of the original two 8-bit registers (DLL and DLM). The driver supports of-platdata which is useful for tiny SPL. Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * configs: mtmips: refresh for mt7628 based boardsWeijie Gao2021-01-244-0/+4
| | | | | | | | | | | | | | | | | | Since mt7620 is added into Kconfig, the CONFIG_SOC_MT7628=y which is omitted by default must be added back, otherwise make xxx_defconfig for these boards will be configured for mt7620 platform. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * mips: mtmips: add two reference boards for mt7620Weijie Gao2021-01-2410-0/+380
| | | | | | | | | | | | | | | | | | | | | | The mt7620_rfb board supports integrated 10/100M PHYs plus two external giga PHYs. It also has 8MB SPI-NOR, mini PCI-e x1 slot, SDHC and USB. The mt7620_mt7530_rfb boards supports an external MT7530 giga switch and a 16MB SPI-NOR flash. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * mips: mtmips: add support for MediaTek MT7620 SoCWeijie Gao2021-01-2414-0/+1163
| | | | | | | | | | | | | | | | This patch adds support for MediaTek MT7620 SoC. All files are dedicated for u-boot. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * mips: mtmips: add support to initialize SDRAMWeijie Gao2021-01-242-0/+63
| | | | | | | | | | | | | | This patch adds support for mtmips SoCs to initialize the SDRAM. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * mips: enable _machine_restart for splWeijie Gao2021-01-241-1/+1
| | | | | | | | | | | | | | | | | | | | The sysreset driver has a config CONFIG_SPL_SYSRESET for the spl stage. Change CONFIG_SYSRESET to CONFIG_IS_ENABLED(SYSRESET) will give spl a chance to use _machine_restart instead of the sysreset driver. Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * mips: mtmips: fix dram size detection in dram_initWeijie Gao2021-01-241-3/+2
| | | | | | | | | | | | | | | | | | | | | | CONFIG_SYS_SDRAM_BASE points to cached memory, i.e. KSEG0, which is not suitable for detecting memory size. Replace CONFIG_SYS_SDRAM_BASE with KSEG1, and make dram_init() always do memory size detection in any stage. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * mips: mtmips: select SYSRESET for mt7628 onlyWeijie Gao2021-01-242-1/+1
| | | | | | | | | | | | | | | | Currently only mt7628 needs the sysreset driver, do not select it for mt7620. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * mips: mtmips: move mt7628 related Kconfig into mt7628 subdirectoryWeijie Gao2021-01-242-52/+54
| | | | | | | | | | | | | | | | | | | | | | This patch is a preparation for add a new soc fot mtmips. Move all mt7628 related Kconfig (boards and UART selection) into mt7628 subdirectory and make sure the top directory of mtmips contains only selection for SoCs. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * mips: dts: switch to board defines for dtb for mtmipsWeijie Gao2021-01-241-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Previous the dts files for gardena-smart-gateway-mt7688 and linkit-smart-7688 are set to be built when mtmips is selected. This can lead to a compilation error if another soc is added to this arch with different dtsi files. So it's better to build the dtb only if their board is selected. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
* | Merge tag 'u-boot-imx-20210125' of ↵Tom Rini2021-01-2590-2347/+10029
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx Changes for 2020.04 ------------------- - new board: Phytec phyCORE-i.MX8MP i.MX8MN Beacon EmbeddedWorks devkit - Fixes: several nanbcb fixes fix for imx8mm_beacon - further switch to distro boot commands - DM: DM Ether for MX6UL CI: https://gitlab.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/6013
| * | ARM: imx: add i.MX8MN lpddr4 image cfg fileMarek Vasut2021-01-231-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add cfg file for i.MX8MN LPDDR4 Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: Add support for i.MX8MN Beacon EmbeddedWorks devkit.Adam Ford2021-01-2315-0/+2771
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Beacon EmbeddedWorks is releasing a devkit based on the i.MX8M Nano SoC consisting of baseboard + SOM. The kit is based on the same design as the Beacon dev kit with the i.MX8M Mini. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
| * | arm: dart6ul: fix ddr size macroMarc Ferland2021-01-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | The previous macro was off by one bit and so we were getting a ddr size which was twice the real size. This commit refactors the macro so it returns the right size in _bytes_ and modifies the printf call so the size is still printed in MiB. Signed-off-by: Marc Ferland <ferlandm@amotus.ca>
| * | spi: imx: Use clock framework if enabledMarek Vasut2021-01-231-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | In case the clock framework is enabled, enable the SPI controller clock and obtain max frequency from the clock framework. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Stefano Babic <sbabic@denx.de>
| * | spi: imx: Define register bits in the driverMarek Vasut2021-01-237-200/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CSPI/ECSPI register bits do not differ between newer SoCs, instead of having multiple copies of the same thing for each iMX SoC, define the bits in the driver. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Stefano Babic <sbabic@denx.de>
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