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| * | | ARM: dts: at91: sama7g5ek: add pinctrl for sdmmc1 and flx3Eugen Hristev2021-01-072-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | Add pinctrl for sdmmc1 and flx3. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * | | ARM: dts: at91: sama7g5: add pinctrl nodeEugen Hristev2021-01-072-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | Add pioA pinctrl node. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * | | ARM: dts: sama7g5: add pit64b supportClaudiu Beznea2021-01-072-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | Add DT bindings for PIT64B driver. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | ARM: dts: sama7g5: enable autobootClaudiu Beznea2021-01-071-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | Enable autoboot. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | configs: sama7g5: use PIT64BClaudiu Beznea2021-01-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Use PIT64B driver. ATMEL_PIT is not available for SAMA7G5. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | ARM: dts: sama7g5: add CPU bindingsClaudiu Beznea2021-01-071-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | Add CPU DT bindings. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | configs: sama7g5: enable CONFIG_CPUClaudiu Beznea2021-01-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Enable CONFIG_CPU. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | ARM: dts: sama7g5: switch to PMC bindingsClaudiu Beznea2021-01-072-13/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Get rid of software defined MCK and switch to PMC bindings for IPs currently present in device tree. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | ARM: dts: sama7g5: add PMC bindingsClaudiu Beznea2021-01-072-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | Add DT bindings for PMC driver. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | ARM: dts: sama7g5: add slow clock bindingsClaudiu Beznea2021-01-071-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Add DT bindings for slow clock driver. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | ARM: dts: sama7g5: add u-boot,dm-pre-reloc bindings for xtalsClaudiu Beznea2021-01-071-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Add dm-pre-reloc DT binding property for cristals. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | ARM: dts: sama7g5: add slow rc and main rc oscillatorsClaudiu Beznea2021-01-072-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | Add slow rc and main rc oscillators to dtsi. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | ARM: dts: sama7g5: move clock frequencies for xtals in board fileClaudiu Beznea2021-01-072-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | Move clock frequencies for crystals on board specific files. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | configs: sama7g5ek: enable pll driverClaudiu Beznea2021-01-071-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Enable PLL driver for SAMA7G5. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | configs: sama7g5ek: set malloc pool to 68KClaudiu Beznea2021-01-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Set malloc pool to 68K for sama7g5ek. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | board: atmel: sama7g5ek: add SYS_MALLOC_F_LEN to SYS_INIT_SP_ADDRClaudiu Beznea2021-01-071-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Heap base address is computed based on SYS_INIT_SP_ADDR by subtracting the SYS_MALLOC_F_LEN value in board_init_f_init_reserve(). Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | board: atmel: sama7g5ek: add initial support for sama7g5ekEugen Hristev2021-01-0710-0/+285
| | | | | | | | | | | | | | | | | | | | | | | | Add initial support for sama7g5 evaluation kit board. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * | | ARM: dts: sama7g5: add initial DT for sama7g5 SoCEugen Hristev2021-01-071-0/+65
| | | | | | | | | | | | | | | | | | | | | | | | Add initial basic devicetree for sama7g5 SoC Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * | | arm: at91: configs: Enable CONFIG_SYS_NAND_USE_FLASH_BBT on all boardsNicolas Ferre2021-01-0750-50/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As highlighted by Stefan in the commit e074d0f79b2e ("arm: at91: gardena-smart-gateway-at91sam: Enable CONFIG_SYS_NAND_USE_FLASH_BBT") it's important to use BBT when Linux enables it. We use it for a long time on all our boards. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: Stefan Roese <sr@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Tom Rini <trini@konsulko.com> Acked-by: Alexander Dahl <ada@thorsis.com>
* | | | Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiTom Rini2021-01-1118-163/+508
|\ \ \ \ | |_|/ / |/| | | | | | | | | | | | | | | | | | | | | | | - Pinecube board support - 64-bit FEL support - mkimage support for eGON images (superseding mksunxiboot) - Bluetooth BD address generation - some fixes
| * | | sunxi: board: add a config option to fixup a Bluetooth addressAndre Heider2021-01-112-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some Bluetooth controllers, like the BCM4345C5 of the Orange Pi 3, ship with the controller default address. Add a config option to fix it up so it can function properly. Signed-off-by: Andre Heider <a.heider@gmail.com> Tested-by: Ondrej Jirman <megous@megous.com> Acked-by: Maxime Ripard <mripard@kernel.org> [rebased] Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | sunxi: board: extract creating a unique sid into a helper functionAndre Heider2021-01-111-47/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor setup_environment() so we can use the created sid for a Bluetooth address too. Signed-off-by: Andre Heider <a.heider@gmail.com> Acked-by: Maxime Ripard <mripard@kernel.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> [rebased] Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | sunxi: dram: h6: Improve DDR3 config detectionJernej Skrabec2021-01-111-44/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It turns out that in rare cases, current analytical approach to detect correct DRAM bus width and rank on H6 doesn't work. On some TV boxes with DDR3, incorrect DRAM configuration triggers write leveling error which immediately stops initialization process. Exact reason why this error appears isn't known. However, if correct configuration is used, initalization works without problem. In order to fix this issue, simply try another configuration when any kind of error appears during initialization, not just those related to rank and bus width. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Tested-by: Thomas Graichen <thomas.graichen@googlemail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | sunxi: board: Move USB ethernet initialization to board_late_init()Andy Shevchenko2021-01-112-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the sake of consistency (*) and order of initialization, i.e. after we have got the ethernet address, interrupt and timer initialized, try to initialize USB ethernet gadget. *) for example, zynqmp uses same order. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | sunxi: Add arm64 FEL supportAndre Przywara2021-01-114-2/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far we did not support the BootROM based FEL USB debug mode on the 64-bit builds for Allwinner SoCs: The BootROM is using AArch32, but the SPL runs in AArch64. Returning back to AArch32 was not working as expected, since the RMR reset into 32-bit mode always starts execution in the BootROM, but not in the FEL routine. After some debug and research and with help via IRC, the CPU hotplug mechanism emerged as a solution: If a certain R_CPUCFG register contains some magic, the BootROM will immediately branch to an address stored in some other register. This works well for our purposes. Enable the FEL feature by providing early AArch32 code to first save the FEL state, *before* initially entering AArch64. If we eventually determine that we should return to FEL, we reset back into AArch32, and use the CPU hotplug mechanism to run some small AArch32 code snippet that restores the initially saved FEL state. That allows the normal AArch64 SPL build to be loaded via the sunxi-fel tool, with it returning into FEL mode, so that other payloads can be transferred via FEL as well. Tested on A64, H5 and H6. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Priit Laes <plaes@plaes.org> (on Olimex A64-Olinuxino)
| * | | sunxi: Fix is_boot0_magic macroAndre Przywara2021-01-111-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The is_boot0_magic macro is missing parentheses around the macro argument, breaking any usage with a more complex argument. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | sunxi: Use mkimage for SPL boot image generationAndre Przywara2021-01-111-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch the SPL boot image generation from using mksunxiboot to the new sunxi_egon format of mkimage. Verified to create identical results for all 152 Allwinner boards. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Samuel Holland <samuel@sholland.org>
| * | | tools: mkimage: Add Allwinner eGON supportAndre Przywara2021-01-115-0/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far we used the separate mksunxiboot tool for generating a bootable image for Allwinner SPLs, probably just for historical reasons. Use the mkimage framework to generate a so called eGON image the Allwinner BROM expects. The new image type is called "sunxi_egon", to differentiate it from the (still to be implemented) secure boot TOC0 image. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | sunxi: Factor out eGON BROM header descriptionAndre Przywara2021-01-112-64/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To be able to easily share the Allwinner eGON BROM header structure between the tools and the SPL code, move the struct definition into a separate header file. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Samuel Holland <samuel@sholland.org>
| * | | sunxi: add PineCube boardIcenowy Zheng2021-01-113-0/+21
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PineCube is an IP camera development kit released by Pine64. It comes with the following compoents: - A mainboard with Sochip S3 SoC, a 16MByte SPI Flash, AXP209 PMIC, a power-only microUSB connector, a USB Type-A connector, a 10/100Mbps Ethernet port and FPC connectors for camera and daughter board. - An OV5640-based camera module which is connected to the parallel CSI bus of the mainboard. - A daughterboard with several buttons, a SD slot, some IR LEDs, a microphone and a speaker connector. As the device tree is synchronized in a previous commit, just add it to Makefile, create a new MAINTAINER item and provide a defconfig. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | Merge branch 'next'Tom Rini2021-01-111517-8689/+16853
|\ \ \ | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com>
| * \ \ Merge tag 'xilinx-for-v2021.04' of ↵Tom Rini2021-01-0625-80/+540
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2021.04 arm64: - DT updates microblaze: - Add support for NOR device support spi: - Fix unaligned data write issue nand: - Minor code change xilinx: - Fru fix in limit calculation - Fill git repo link for all Xilinx boards video: - Add support for seps525 spi display tools: - Minor Vitis file support cmd/common - Minor code indentation fixes serial: - Uartlite debug uart initialization fix
| | * | | xilinx: Fill git repository for Xilinx boardsMichal Simek2021-01-054-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All Xilinx SoCs have repository location filled already but boards are covered by different fragment which is missing this link. The patch is extending description with adding proper link to the same repository. Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | | video: Call video_sync in video_clear()Michal Simek2021-01-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a need to call sync when anybody asking for clearing display. For example via cls command. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| | * | | video: seps525: Add seps525 SPI driverMichal Simek2021-01-054-0/+336
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the WiseChip Semiconductor Inc. (UG-6028GDEBF02) display using the SEPS525 (Syncoam) LCD Controller. Syncoam Seps525 PM-Oled is RGB 160x128 display. This driver has been tested through zynq-spi driver. ZynqMP> load mmc 1 100000 rainbow.bmp 61562 bytes read in 20 ms (2.9 MiB/s) ZynqMP> bmp info 100000 Image size : 160 x 128 Bits per pixel: 24 Compression : 0 ZynqMP> bmp display 100000 ZynqMP> setenv stdout vidconsole Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| | * | | video: seps525: Add dt binding descriptionVikhyat Goyal2021-01-052-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added dt binding for seps525 display driver. Signed-off-by: Vikhyat Goyal <vikhyat.goyal@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| | * | | video: Introduce video_sync operationMichal Simek2021-01-052-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some drivers like LCD connected via SPI requires explicit sync function which copy framebuffer content over SPI to controller to display. This hook doesn't exist yet that's why introduce it via video operations. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| | * | | video: Let video_sync to return error valueMichal Simek2021-01-054-19/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is preparation for follow up one to support cases where synchronization can fail. Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| | * | | video: Fix video sync kernel-doc formatMichal Simek2021-01-051-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Place description below function parameters to make kernel-doc stript happy. Also rename dev to vid to be aligned with function parameters. Fixes: 1acafc73bfc7 ("dm: video: Add a video uclass") Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| | * | | fru: ops: avoid out of bounds accessHeinrich Schuchardt2021-01-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Building xilinx_zynq_virt_defconfig fails on origin/next as reported by GCC 10.2 (as provided by Debian Bullseye): CC board/xilinx/common/fru_ops.o board/xilinx/common/fru_ops.c: In function ‘fru_capture’: board/xilinx/common/fru_ops.c:173:8: error: array subscript 284 is outside array bounds of ‘struct fru_table[1]’ [-Werror=array-bounds] 173 | limit = data + sizeof(struct fru_board_data); | ~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ board/xilinx/common/fru_ops.c:17:18: note: while referencing ‘fru_data’ 17 | struct fru_table fru_data __section(.data); | ^~~~~~~~ When using sizeof(struct fru_board_data) to find the end of the structure you should add it to the start of the structure. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | | zynq: mtd: nand: remove superfluous ifHeinrich Schuchardt2021-01-051-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This sort of code does not make much sense: if (ondie_ecc_enabled) { if (ondie_ecc_enabled) { Remove the inner if. The problem was indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | | arm64: zynqmp: Add Ethernet node for zcu1285 revAHarini Katakam2021-01-051-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add ethernet node gem1 to zcu1285 RevB. GMII to RGMII converter sits between MAC and external phy connected over GMII to MAC and RGMMI to external phy Signed-off-by: Harini Katakam <harini.katakam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | | arm64: zynqmp: Add ethernet node for zcu1275 revBSiva Durga Prasad Paladugu2021-01-051-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add ethernet node gem1 to zcu1275 RevB. GMII to RGMII converter sits between MAC and external phy connected over GMII to MAC and RGMMI to external phy. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | | spi: zynqmp_gqspi: Fix unaligned data writes issueT Karthik Reddy2021-01-041-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When unaligned 3 bytes data write operation is performed, 3rd byte is being over written by 1st byte of 3 bytes data. This patch fixes it. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | | microblaze: Add nor device to distro bootT Karthik Reddy2021-01-041-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add parallel nor device to distroboot for microblaze. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | | microblaze: Set script_offset_nor env variableT Karthik Reddy2021-01-041-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set script_offset_nor env variable using CONFIG_BOOT_SCRIPT_OFFSET and nor flash start address to keep bootscript offset configurable. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | | arm64: zynqmp: Sync DT with Linux kernelMichal Simek2021-01-041-33/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All changes are recorded in lore.kernel.org. Here are links to that patches for the record. Link: https://lore.kernel.org/r/f59a63d8cb941592de6d2dee8afa6f120b2e40c8.1601379794.git.michal.simek@xilinx.com Link: https://lore.kernel.org/r/68f20a2b2bb0feee80bc3348619c2ee98aa69963.1598263539.git.michal.simek@xilinx.com Link: https://lore.kernel.org/r/f767fe007e446a2299fda9905e75b723c650a424.1605021644.git.michal.simek@xilinx.com Link: https://lore.kernel.org/r/cc294ae1a79ef845af6809ddb4049f0c0f5bb87a.1598259551.git.michal.simek@xilinx.com Link: https://lore.kernel.org/r/20200629081744.13916-1-krzk@kernel.org And there are other minor changes (just moving things around). Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | | serial: uartlite: Fix uninitialized ret in debug uartliteAshok Reddy Soma2021-01-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Endianness detection is checked against uninitialized ret variable. Assign ret with read value from status register to fix this. Fixes: 31a359f87eaa ("serial: uartlite: Add support to work with any endianness") Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | | common: usb_storage: Fix code indentationMichal Simek2021-01-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reported by smatch like: common/usb_storage.c:430 us_one_transfer() warn: inconsistent indenting Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | | cmd: load: Fix code indentationMichal Simek2021-01-041-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reported by smatch like: cmd/load.c:228 read_record() warn: inconsistent indenting Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
generated by cgit (git 2.34.1) at 2025-09-30 01:37:37 +0000