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* Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2018-11-2734-111/+117
|\ | | | | | | - Introduce CONFIG_SPL_DM_USB
| * usb: storage: s/CONFIG_BLK/CONFIG_IS_ENABLED(BLK)/Sven Schwermer2018-11-261-14/+14
| | | | | | | | | | | | | | | | | | This fixes link issues when building the SPL without USB driver model but with USB storage support. CONFIG_BLK can be enabled and disabled independently for SPL and non-SPL builds. We leverage that existing functionality here. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
| * usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/Sven Schwermer2018-11-2629-92/+92
| | | | | | | | | | | | | | | | This allows to disable the USB driver model in SPL because it checks the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for regular non-SPL builds. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
| * usb: Remove CMD_USB dependency for common codeSven Schwermer2018-11-262-2/+2
| | | | | | | | | | | | | | | | Common USB code is built whenever USB is enabled (in non-SPL builds). The USB uclass is built whenever (SPL_)DM_USB is enabled. Both need to be independent from CMD_USB. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
| * usb: am335x_evm: Disable CONFIG_SPL_DM_USBSven Schwermer2018-11-261-1/+2
| | | | | | | | | | | | | | This configuration doesn't use USB in the SPL, so we need to disable driver model for USB in the SPL. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
| * usb: Introduce CONFIG_SPL_DM_USBSven Schwermer2018-11-263-2/+7
| | | | | | | | | | | | | | | | This allows building the SPL without driver model for USB. Since CONFIG_SPL_DM_USB is enabled if and only if CONFIG_DM_USB was enabled before, this patch does not change the build behaviour. Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
* | Merge branch '2018-11-26-master-imports'Tom Rini2018-11-2625-74/+455
|\ \ | | | | | | | | | | | | - chiliboard updates - misc TI platform updates
| * | ARM: chiliboard: remove dead !CONFIG_DM_SERIAL codeMarcin Niestroj2018-11-261-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | DM_SERIAL is selected by TARGET_CHILIBOARD, so there is no reason to keep code that will not be built. Remove it. Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | ARM: chiliboard: move towards driver model and device-tree bootMarcin Niestroj2018-11-262-55/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch mostly enables DM drivers in board defconfig and all their dependencies. Additionally we remove ethernet platform data, as all details are in device-tree now. Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | ARM: dts: am335x-chiliboard: add /chosen/stdout-pathMarcin Niestroj2018-11-261-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | Add that node path in u-boot overlay dtsi file for now to keep am335x-chiliboard.dts in sync with Linux. Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | ARM: dts: am335x-chili*: add chiliSOM and chiliboard DTS filesMarcin Niestroj2018-11-263-1/+380
| | | | | | | | | | | | | | | | | | | | | | | | Import chiliSOM and chiliboard dts files from Linux v4.19. They will be used after transition to driver model and device-tree based boot. Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | configs: Remove CONFIG_MARVELLChris Packham2018-11-264-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | This option is defined by a few boards but doesn't guard any code. Remove it from the boards and config_whitelist.txt. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * | ARM: vexpress_*_defconfig: Enable CMD_UBI supportOtavio Salvador2018-11-267-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allow for convenient use of QEMU machine to test loading of UBI filesystem. There are a couple of changes made together of this which are required: 1) The malloc must be at least 512 KiB to allow the use of UBI filesystem. We are going to enable it in a next patch. 2) MTD_DEVICE must be enabled, otherwise we get missing symbols during the build Following configs were change: - vexpress_aemv8a_dram_defconfig - vexpress_aemv8a_juno_defconfig - vexpress_aemv8a_semi_defconfig - vexpress_ca15_tc2_defconfig - vexpress_ca5x2_defconfig - vexpress_ca9x4_defconfig Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Liviu Dudau <liviu.dudau@arm.com>
| * | board: da8xxevm: Fix Environmental CRC errorAdam Ford2018-11-261-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the spi_flash_probe_bus_cs() was previously called, it was called using 0's for two values where CONFIG_ENV_SPI_MAX_HZ and CONFIG_ENV_SPI_MODE are now used. When changed this caused the environment to fail the CRC check and the default was used. This patch defines both of these values back 0. Fixes: 25a17652c9c2 ("fix: env: Fix the SPI flash device setup for DM mode") Signed-off-by: Adam Ford <aford173@gmail.com>
| * | ARM: armv7: Add early stack for erratum workaroundsAndrew F. Davis2018-11-261-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some erratum workarounds call into C code before the stack is setup, this can lead to values pushed onto the stack being lost, firewall exceptions, and other undefined behavior. Setup a temporary stack to allow these functions to work correctly. Signed-off-by: Andrew F. Davis <afd@ti.com> Acked-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com>
| * | tools/file2include: don't use malloc.h for mallocJonathan Gray2018-11-261-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | stdlib.h is the header for malloc since at least c89/c90. Previously this would fail to build on OpenBSD and fallback to the wrong header: In file included from u-boot/tools/file2include.c:21: u-boot/include/malloc.h:875:5: error: function-like macro 'CONFIG_IS_ENABLED' is not defined Signed-off-by: Jonathan Gray <jsg@jsg.id.au> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * | arm: ti: boot: Fix U-Boot environment partition addressSam Protsenko2018-11-261-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recent removal of obsolete partition led to shifting of starting address of "reserved" partition (which reflects U-Boot environment). Fix its start address to keep it in sync with ENV_OFFSET and DFU environment. This patch also provides fixed start address for "reserved" partition, so that we can track when it's shifted next time. While at it, move it before "misc" partition to keep all Android partitions together. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Acked-By: Praneeth Bajjuri <praneeth@ti.com>
| * | armv7r: K3: Allow SPL to run only on core 0Lokesh Vutla2018-11-263-1/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on the MCU R5 efuse settings, R5F cores in MCU domain either work in split mode or in lock step mode. If efuse settings are in lockstep mode: ROM release R5 cores and SPL continues to run on the R5 core is lockstep mode. If efuse settings are in split mode: ROM releases both the R5 cores simultaneously and allow SPL to run on both the cores. In this case it is bootloader's responsibility to detect core 1 and park it. Else both the core will be running bootloader independently which might result in an unexpected behaviour. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | add default-option to bootmenuFrank Wunderlich2018-11-261-0/+5
|/ / | | | | | | | | | | with this patch the selected Entry in bootmenu can be set by environment-var bootmenu_default=<number> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini2018-11-262-2/+10
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| * | dm: video: correctly set the cursor positionHeinrich Schuchardt2018-11-172-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The terminal escape sequence ESC [ <x> ; <y> H is used to set the cursor position. According to the ECMA 48 standard the upper left corner in the escape sequences is [1, 1]. The video uclass uses [0, 0] as upper left corner. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2018-11-265-14/+47
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| * | | sun8i_emac: add support for setting EMAC TX/RX delayIcenowy Zheng2018-11-231-3/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some boards have the EMAC TX/RX lanes wired with a different length with the clock lane, which can be workarounded by setting a TX/RX delay in the EMAC. This kind of delays are already defined in the newest device tree binding of dwmac-sun8i, which has already entered linux-next. Add support for setting these delays. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | | sunxi: Fix memory 2-rank initialization for a33 cpuMichael Trimarchi2018-11-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we initialize the memory we need to autodetect rank and size but this can happen only if we send the proper reset to both memory module including cke signal. For this reason we need initialize the physical on both channel because we need to presume that both are connected. This way let the CLKE to be activated at the right time with the memory reset coming from the cpu Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
| * | | sunxi-mmc: use new mode on both controllers on A64Vasily Khoruzhick2018-11-222-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using new mode improves stability of eMMC and SD cards. Without it SPL fails to load u-boot from SD on Pinebook. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # Amarula A64-Relic Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | | sunxi-mmc: don't double clock for new mode unconditionallyVasily Khoruzhick2018-11-221-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Comment in Linux driver says that clock needs to be doubled only if we use DDR modes, moreover divider has to be set accordingly. U-boot driver doesn't declare support for any DDR modes and doesn't set internal clock divider in CLKCR, so it doubles clock unconditionally when new mode is used. Some cards can't handle that and as result SPL fails to load u-boot. Fixes: de9b1771c3b ("mmc: sunxi: Support new mode") Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # Amarula A64-Relic
| * | | sunxi-mmc: introduce new MMC_SUNXI_HAS_MODE_SWITCH optionVasily Khoruzhick2018-11-223-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allwinner A64 has new mode but doesn't have a mode switch in CCM, and CCM_MMC_CTRL_MODE_SEL_NEW is not defined, so compilation fails if MMC_SUNXI_HAS_NEW_MODE is enabled Introduce new MMC_SUNXI_HAS_MODE_SWITCH option to be able to ifdef usage of CCM_MMC_CTRL_MODE_SEL_NEW Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> [jagan: update commit message] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # Amarula A64-Relic
* | | | Merge git://git.denx.de/u-boot-riscvTom Rini2018-11-2640-368/+1269
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| * | | riscv: cache: Implement i/dcache [status, enable, disable]Rick Chen2018-11-269-10/+146
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
| * | | riscv: dts: Add ae350_32.dts for RV32IRick Chen2018-11-263-1/+458
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add ae350_32.dts for 32 bit. And also rename ae350.dts to ae350_64.dts for 64 bit. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
| * | | configs: ax25-ae350: Separate ax25-ae350 for RV32/64I.Rick Chen2018-11-262-1/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Separate ax25-ae350 from one to two for 32 and 64 bit individually. And also select different dts for 32 and 64 bit. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
| * | | riscv: dts: Sync to Linux Kernel ae350 dts.Rick Chen2018-11-261-15/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use same dts to boot U-Boot and Kernel. Following are the change notes : 1 Remove early printk bootargs. 2 Timer frequency are changed to 60MHz. 3 Add dma, snd, lcd, virtio nodes which are used in kernel drivers. They does not been used by U-Boot. 4 Change spi irq from 3 to 4. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
| * | | riscv: qemu: clear kernel-start/-end in device tree as workaround for BBLLukas Auer2018-11-262-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | QEMU specifies the location of Linux (supplied with the -kernel argument) in the device tree using the riscv,kernel-start and riscv,kernel-end properties. We currently rely on the SBI implementation of BBL to run Linux and therefore embed Linux as payload in BBL. This causes an issue, because BBL detects the kernel properties in the device tree and ignores the Linux payload as a result. Work around this issue by clearing the kernel properties in the device tree before booting Linux. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | | riscv: qemu: detect and boot the kernel passed by QEMULukas Auer2018-11-263-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | QEMU embeds the location of the kernel image in the device tree. Store this address in the environment as variable kernel_start. It is used in the board-local distro boot command QEMU to boot the kernel with the U-Boot device tree. The QEMU boot command is added as the first boot target device. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alexander Graf <agraf@suse.de>
| * | | dm: core: add missing prototype for ofnode_read_u64Lukas Auer2018-11-261-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | riscv: qemu: enable distro bootLukas Auer2018-11-263-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable distro boot on the qemu-riscv32/64 boards. Supported boot target devices are VirtIO and DHCP. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alexander Graf <agraf@suse.de>
| * | | distro_bootcmd: add VirtIO distro boot commandLukas Auer2018-11-262-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a boot command to distro boot to support disks connected over the VirtIO bus. The boot command uses the shared block environment. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alexander Graf <agraf@suse.de>
| * | | riscv: align bootm implementation with that of other architecturesLukas Auer2018-11-261-27/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The bootm implementation of RISC-V diverges from that of other architectures. Update it to match the implementation of other architectures. The ARM implementation is used as a reference. This adds the following features and changes to RISC-V. * Add support for the BOOTM_STATE_OS_FAKE_GO command * Call the remove function on devices with the removal flag set before booting Linux * Force disconnect USB devices from the host before booting Linux * Print and add bootstage information to the device tree before booting Linux Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | | riscv: qemu: support booting LinuxLukas Auer2018-11-263-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support booting Linux (as payload of BBL) from FIT images. For this, the default CONFIG_SYS_BOOTM_LEN is increased to 16 MB, and the environment variables fdt_high and initrd_high are set to mark the device tree and initrd as in-place. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | | riscv: qemu: use device tree passed by prior boot stageLukas Auer2018-11-263-13/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | QEMU provides a device tree, which is passed to U-Boot using register a1. We are now able to directly select the device tree with the configuration CONFIG_OF_PRIOR_STAGE. Replace the hard-coded address in qemu-riscv with it. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
| * | | riscv: save hart ID and device tree passed by prior boot stageLukas Auer2018-11-262-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Store the hart ID and device tree passed by the prior boot stage (in a0 and a1) in registers s0 and s1. Replace one use of s1 in start.S to avoid overwriting it. The device tree is also stored in memory to make it available to U-Boot with the configuration CONFIG_OF_PRIOR_STAGE. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
| * | | riscv: do not blindly modify the mstatus CSRLukas Auer2018-11-261-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mstatus CSR includes WPRI (writes preserve values, reads ignore values) fields and must therefore not be set to zero without preserving these fields. It is not apparent why mstatus is set to zero here since it is not required for U-Boot to run. Remove it. This instruction and others encode zero as an immediate. RISC-V has the zero register for this purpose. Replace the immediates with the zero register. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
| * | | riscv: remove unused labels in start.SLukas Auer2018-11-261-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The labels nmi_vector, trap_vector and handle_reset in start.S are not used for RISC-V. Remove them. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | | Drop CONFIG_INIT_CRITICALBin Meng2018-11-265-73/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This is now deprecated and no board is using it. Drop it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
| * | | riscv: align mtvec on a 4-byte boundaryLukas Auer2018-11-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The machine trap-vector base address (mtvec) must be aligned on a 4-byte boundary. Add the necessary align directive to trap_entry. This patch also removes the global directive for trap_entry, which is not required. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | | riscv: fix inconsistent use of spaces and tabs in start.SLukas Auer2018-11-261-161/+161
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | start.S uses both tabs and spaces after instructions. Fix this by only using tabs after instructions. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
| * | | riscv: implement the invalidate_icache_* functionsLukas Auer2018-11-261-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
| * | | riscv: hang on unhandled exceptionsLukas Auer2018-11-261-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hang on unhandled exceptions to prevent execution in a faulty state. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
| * | | riscv: treat undefined exception codes as reservedLukas Auer2018-11-261-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Undefined exception codes currently lead to an out-of-bounds array access. Prevent this by treating undefined exception codes as "reserved". Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
| * | | riscv: complete the list of exception codesLukas Auer2018-11-261-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only the first four exception codes are defined. Add the missing exception codes from the definition in RISC-V Privileged Architecture Version 1.10. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
generated by cgit (git 2.34.1) at 2025-05-02 18:41:52 +0000