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* board: fsl: lx2160a: implement board_fix_fdtPankaj Bansal2019-09-123-0/+70
| | | | | | | | | | | | | lx2160a rev1 and rev2 SoC has different pcie controller. The pcie controller device tree node fields "compatible" and registers names needs to be updated accordingly This change in device tree is handled as part of fdt fixups. These changes would only be applied if the soc revision is not rev1. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: fsl-layerscape: Update I2C clock dividerChuanhua Han2019-09-121-0/+4
| | | | | | | | | | | By default, i2c input clock is programmed at platform clk / 2 in u-boot, but this is not correct for all the platforms, Update I2C clock divider's default values as per SoC (LS1012A, LS1028A, LX2160A and LS1088A). Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* watchdog: sp805_wdt: add expire_now methodThomas Schaefer2019-09-121-1/+9
| | | | | | | | | Add sp805_wdt_expire_now function. expire_now method is required by U_BOOT_DRIVER. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: ls1028a: configure PMU's PCTBENR to enable WDTThomas Schaefer2019-09-121-2/+4
| | | | | | | | | | The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* arm: dts: ls1028a-qds: define the MDIO MUXAlex Marginean2019-09-121-3/+53
| | | | | | | | | | | Add the device-tree structure describing the MUX in board dts. QDS board has an on-board RGMII PHY and 4 slots for extension cards. All these can be accessed over MDIO through a MDIO MUX controlled over I2C. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* board/lx2160a: Fix MC firmware loading for SD bootPankaj Bansal2019-09-121-6/+6
| | | | | | | | | | | During boot, u-boot reads MC, DPL, DPC firmware from SD card and copies to DDR. Update DDR addresses to which these firmwares are copied as per memory map of these firmwares on SD-card so that isolation between the regions of various firmwares is maintained to avoid geting overwritten. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* configs/ls1012ardb,lx2160ardb,ls1028ardb: add esdhc hs200 configYinbo Zhu2019-09-123-0/+6
| | | | | | | | | | Enable CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK and CONFIG_MMC_HS200_SUPPORT config for ls1012ardb, ls1012ardb, lx2160ardb in defconfig file Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* mmc: fsl_esdhc: Add emmc hs200 supportYinbo Zhu2019-09-122-15/+23
| | | | | | | | | | Add eMMC hs200 mode for ls1028a, ls1012a, lx2160a. This increases eMMC performance. Tuning procedure is currently not supported. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* dts: armv8: add emmc hs200 support for ls1028ardbYinbo Zhu2019-09-121-0/+1
| | | | | | | Add emmc hs200 support for ls1028ardb Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* dts: armv8: add emmc hs200 support for lx2160ardbYinbo Zhu2019-09-121-0/+1
| | | | | | | Add emmc hs200 support for lx2160ardb Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* dts: armv8: add emmc hs200 support for ls1012ardbYinbo Zhu2019-09-121-0/+4
| | | | | | | Add emmc hs200 support for ls1012ardb Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* mmc: Kconfig: Add FSL_ESDHC_USE_PERIPHERAL_CLK optionYinbo Zhu2019-09-121-1/+9
| | | | | | | | | | | | | | | NXP fsl_esdhc controller supports two reference clocks: platform clock and peripheral clock Peripheral clock can provide higher clock frequency which is required to be used for tuning of SD UHS mode and eMMC HS200/HS400 modes. Peripheral clock is enabled by default by defining config option FSL_ESDHC_USE_PERIPHERAL_CLK if eMMC HS200/HS400 modes are supported. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* fsl-layerscape: Add fsl_esdhc peripheral clock supportYinbo Zhu2019-09-124-19/+78
| | | | | | | | | Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86Tom Rini2019-09-1013-51/+189
|\ | | | | | | | | | | | | - Tangier ACPI table fixes - Support getting high memory size on QEMU x86 - Show UEFI images involved in crash for x86 - EFI loader conventional memory map fix
| * x86: tangier: Use spaces over TABs in ASL codeAndy Shevchenko2019-09-101-13/+13
| | | | | | | | | | | | | | For sake of consistency use spaces over TABs in ASL code. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: tangier: Fix off-by-one error when preparing CSRTAndy Shevchenko2019-09-101-1/+1
| | | | | | | | | | | | | | | | | | | | Intel iDMA 32-bit controller has 17 bits for the maximum block size value. Due to nature of the binary number representation the maximum value is 2^17 - 1. The original code misses the latter part in equation. Fixes: 5e99fde34a77 ("x86: tangier: Populate CSRT for shared DMA controller") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: tangier: Reserve PCI ECAM in motherboard resourcesAndy Shevchenko2019-09-104-1/+30
| | | | | | | | | | | | | | | | | | Per PCI firmware specification the ACPI has to reserve the memory which is defined as PCI ECAM. Fixes: 39665beed6f7 ("x86: tangier: Enable ACPI support for Intel Tangier") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: acpi: Annotate struct acpi_table_header with __packedAndy Shevchenko2019-09-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GCC 9.2 starts complaining about possible pointer misalignment of pointers to the unpacked (alignment=4) structures in the packed (alignment=1) ones: CC arch/x86/cpu/tangier/acpi.o arch/x86/cpu/tangier/acpi.c: In function ‘acpi_create_fadt’: arch/x86/cpu/tangier/acpi.c:22:37: warning: taking address of packed member of ‘struct acpi_fadt’ may result in an unaligned pointer value [-Waddress-of-packed-member] 22 | struct acpi_table_header *header = &(fadt->header); CC arch/x86/lib/acpi_table.o arch/x86/lib/acpi_table.c: In function ‘acpi_create_spcr’: arch/x86/lib/acpi_table.c:366:37: warning: taking address of packed member of ‘struct acpi_spcr’ may result in an unaligned pointer value [-Waddress-of-packed-member] 366 | struct acpi_table_header *header = &(spcr->header); Fix the potential issues by annotating embedded structures with __packed even though they are packed naturally. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: add GCC version number in the commit message] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: efi_loader: Use efi_add_conventional_memory_map()Park, Aiden2019-09-101-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | Use efi_add_conventional_memory_map() to configure EFI conventional memory properly with ram_top value. This will give 32-bit mode U-Boot proper conventional memory regions even if e820 has an entry which is greater than 32-bit address space. Signed-off-by: Aiden Park <aiden.park@intel.com> Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> [bmeng: fixed some typos in the commit message] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: show UEFI images involved in crashHeinrich Schuchardt2019-09-101-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a crash occurs, show the loaded UEFI images to facilitate analysis. This is an example output: => bootefi 0x1000000 Found 0 disks Hello world of bugs! Invalid Opcode (Undefined Opcode) EIP: 0010:[<06ceb06e>] EFLAGS: 00010206 Original EIP :[<fec9906e>] EAX: 00000000 EBX: 06cec000 ECX: 00000fd0 EDX: 00000001 ESI: 06ced18a EDI: 07d0fe10 EBP: 07fe27a0 ESP: 07d0fde0 DS: 0018 ES: 0018 FS: 0020 GS: 0018 SS: 0018 CR0: 00000033 CR2: 00000000 CR3: 00000000 CR4: 00000000 DR0: 00000000 DR1: 00000000 DR2: 00000000 DR3: 00000000 DR6: ffff0ff0 DR7: 00000400 Stack: 0x07d0fde8 : 0x00000000 0x07d0fde4 : 0x06ced040 --->0x07d0fde0 : 0x07fe27a0 0x07d0fddc : 0x00010206 0x07d0fdd8 : 0x00000010 0x07d0fdd4 : 0x06ceb06e UEFI image [0x06cea000:0x06cf0fff] pc=0x106e '/bug-i386.efi' ### ERROR ### Please RESET the board ### With the additional information provided by this patch we know that the problem occurred 0x106e after the load address of bug-i386.efi. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * doc: slimbootloader: Update Linux booting steps on QEMUPark, Aiden2019-09-101-0/+22
| | | | | | | | | | | | | | | | Add steps to test Linux booting on QEMU with Yocto image. Signed-off-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: qemu: Report high memory in the E820 tableBin Meng2019-09-101-19/+40
| | | | | | | | | | | | | | | | Now that we are able to get the size of high memory from QEMU, report its memory range as usable ram. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Aiden Park <aiden.park@intel.com>
| * x86: qemu: Support getting high memory sizeBin Meng2019-09-102-2/+36
| | | | | | | | | | | | | | | | At present only size of memory that is below 4GiB is retrieved from QEMU. Add a function that gets size of memory that is above 4GiB. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Aiden Park <aiden.park@intel.com>
| * x86: qemu: Extract getting memory size to a separate routineBin Meng2019-09-102-2/+14
| | | | | | | | | | | | | | | | This extracts getting memory size logic in dram_init() to a separate routine qemu_get_low_memory_size(). No functional changes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Aiden Park <aiden.park@intel.com>
| * x86: Drop weak version board_get_usable_ram_top()Bin Meng2019-09-101-6/+0
| | | | | | | | | | | | | | | | | | | | | | Every x86 platform provides board_get_usable_ram_top(), hence there is no need to provide a weak version board_get_usable_ram_top(), not to mention there is another weak version board_get_usable_ram_top() in common/board_f.c. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Aiden Park <aiden.park@intel.com>
| * x86: acpi: Slightly reduce binary size of ACPI tables for TangierAndy Shevchenko2019-09-102-3/+3
| | | | | | | | | | | | | | | | | | | | Using ACPI predefined macros, such as Zero or One, will reduce a binary size of resulting ACPI tables. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: manually fixed the conflicts when applying] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * tools: Add ifwitool to .gitignoreAndy Shevchenko2019-09-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Follow up fix to the commit 56bf4f863075 ("x86: Add ifwitool for Intel Integrated Firmware Image") in order to ignore created binary. Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | Merge tag 'u-boot-amlogic-20190910' of ↵Tom Rini2019-09-101-0/+3
|\ \ | |/ |/| | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - Add support for dis_u2_susphy_quirk in the xhci-dwc3 driver to fix boot when a device is plugged only in the OTG capable port for libretech-ac and libretech-cc
| * usb: xhci-dwc3: Add support for dis_u2_susphy_quirkNeil Armstrong2019-09-101-0/+3
|/ | | | | | | | | | | | | | | | | | | | This quirk is necessary for the Amlogic GXL SoCs otherwise the Port 2 PHY doesn't get out of suspend and U-Boot resets the board after: XHCI timeout on event type 33... cannot recover. BUG: failure at drivers/usb/host/xhci-ring.c:474/xhci_wait_for_event()! BUG! This quirk is also handled in the dwc3 core code, but until the xhci-dwc3 driver uses the dwc3 core, the quirk must be handled here to fix USB support on the Amlogic libretech-cc and libretech-ac board when a device is only plugged in the OTG port. Cc: Yuri Frolov <crashing.kernel@gmail.com> Cc: Bin Meng <bmeng.cn@gmail.com> Fixes: dc9cdf859e ("usb: dwc3: Add DWC3 controller driver support") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* arm: ti: Add missing "=" from previous fixTom Rini2019-09-091-1/+1
| | | | | | | | | | | While the original patch to fix a regression in distro boot for mmc on these platforms had the correct syntax, I broke the change while applying. Add back in the missing "=" here so that the syntax is correct. Reported-by: Andre Heider <a.heider@gmail.com> Fixes: 27e0f3bcf075 ("arm: ti: Fix regression in distro boot for mmc") Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge tag 'mmc-9-6-2019' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmcTom Rini2019-09-0823-66/+289
|\ | | | | | | | | | | | | | | | | | | | | Bug fixes to mmc_spi Add Aspeed SD driver Fix dw_mmc timeout calculation Fix timeout values passed to mmc_wait_dat0 sdhci dt caps/mask update [trini: Fix evb-ast2500_defconfig CONFIG_MMC line] Signed-off-by: Tom Rini <trini@konsulko.com>
| * mmc: sdhci: Add support for dt caps & caps maskT Karthik Reddy2019-09-061-9/+14
| | | | | | | | | | | | | | | | | | | | | | | | The sdhci capabilities registers can be incorrect. The sdhci-caps-mask and sdhci-caps dt properties specify which bits of the registers are incorrect and what their values should be. This patch makes the sdhci driver use those properties to correct the caps. Also use "dev_read_u64_default" instead of "dev_read_u32_array" for caps mask. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * dm: core: Add functions to read 64-bit dt propertiesT Karthik Reddy2019-09-064-2/+45
| | | | | | | | | | | | | | | | | | This patch adds functions dev_read_u64_default & dev_read_u64 to read unsigned 64-bit values from devicetree. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * dm: mmc_spi: Fix NULL pointer dereference in mmc_spi_bind()Bin Meng2019-09-051-15/+20
| | | | | | | | | | | | | | | | | | The mmc_spi driver's priv is not available in its bind phase(). Use platdata instead. Fixes: 05e35d429745 ("mmc: mmc_spi: Re-write driver using DM framework") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
| * mmc: dw_mmc: fix timeout calculate methodKever Yang2019-09-051-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two cases not been considered: - use uint for timeout, it will overflow when size bigger than 512KB for it *8*1000 at the beginning, but we may use size up to 32MB; The 'timeout' will overflow if size bigger than 51.2MB after this fix, which should be enough for U-Boot; - The timeout is using clock speed for data rate, but the device may not have such high speed, eg. clock is 52MHz while the device write speed may be less than 10MB/s, and we may use up to 150MHz clock. Fix them in this patch, the max timeout is about 6500 when size is 32MB after fix. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * ARM: dts: ast2500: Add SDHCI nodesEddie James2019-09-052-0/+30
| | | | | | | | | | | | | | Add nodes for the Aspeed SD controllers with their necessary properties. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Eddie James <eajames@linux.ibm.com>
| * configs: AST2500 EVB: Enable SD controllerEddie James2019-09-051-0/+8
| | | | | | | | | | | | | | | | Enable the MMC subsystem and the Aspeed SD controller. Also enable the use of the device tree for probing the controller. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
| * mmc: Add Aspeed SD controller driverEddie James2019-09-054-1/+104
| | | | | | | | | | | | | | Add support for the Aspeed SD host controller engine. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
| * clk: aspeed: Add support for SD clockEddie James2019-09-053-0/+32
| | | | | | | | | | | | | | Add code to enable the SD clock on the ast2500 SoC. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Eddie James <eajames@linux.ibm.com>
| * mmc: Rename timeout parameters for clarificationSam Protsenko2019-09-056-32/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's quite hard to figure out time units for various function that have timeout parameters. This leads to possible errors when one forgets to convert ms to us, for example. Let's rename those parameters correspondingly to 'timeout_us' and 'timeout_ms' to prevent such issues further. While at it, add time units info as comments to struct mmc fields. This commit doesn't change the behavior, only renames parameters names. Buildman should report no changes at all. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Igor Opaniuk <igor.opaniuk@gmail.com>
| * mmc: Fix timeout values passed to mmc_wait_dat0()Sam Protsenko2019-09-051-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mmc_wait_dat0() expects timeout argument to be in usec units. But some overlying functions operate on timeout in msec units. Convert timeout from msec to usec when passing it to mmc_wait_dat0(). This fixes 'avb' commands on BeagleBoard X15, because next chain was failing: get_partition() -> mmc_switch_part() -> __mmc_switch() -> mmc_wait_dat0() when passing incorrect timeout from __mmc_switch() to mmc_wait_dat0(). Fixes: bb98b8c5c06a ("mmc: During a switch, poll on dat0 if available and check the final status") Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Eugeniu Rosca <rosca.eugeniu@gmail.com> Tested-by: Eugeniu Rosca <rosca.eugeniu@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Tested-by: Igor Opaniuk <igor.opaniuk@gmail.com> Reviewed-by: Igor Opaniuk <igor.opaniuk@gmail.com>
| * dm: mmc: remove unused U_BOOT_DRIVER(mmc)Andy Yan2019-09-051-4/+0
| | | | | | | | | | | | | | | | When look through the code, I found this bare metal drives is not used, so remove it. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2019-09-0713-86/+177
|\ \ | | | | | | | | | - Initial DM conversion
| * | sh: r2dplus: Switch to DM PCI driverMarek Vasut2019-09-024-20/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add DT entry for the DM PCI driver, update board configs and drop ad-hoc board init code for the PCI bus. Instead, let the DM PCI driver initialize and operate the hardware. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | pci: sh7751: Convert to DM and DT probingMarek Vasut2019-09-021-58/+106
| | | | | | | | | | | | | | | | | | | | | | | | Convert the SH7751 PCI driver to DM and add DT probing. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Bin Meng <bmeng.cn@gmail.com>
| * | sh: r2dplus: Enable OF controlMarek Vasut2019-09-025-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable OF control for SH4 R2Dplus board. This is necessary, because the PCI uclass is designed in a way that makes it depend on DT and disallows instanciating devices without DT (e.g. with platdata). Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | sh: r2dplus: Enable DMMarek Vasut2019-09-021-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable driver model support for SH4 R2Dplus board. Thus far, no drivers are bound via the DM. The PCI drivers have yet to be converted to DM_PCI. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | sh: Fix OF_SEPARATE supportMarek Vasut2019-09-022-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the OF_SEPARATE is enabled, the DT is appended past the _end symbol. The current code however clears BSS very early, which overwrites the DT blob with zeroes. Moreover, the early code relocates U-Boot into RAM to the correct location, but does not relocate the DT. This patch adds code to relocate the DT and avoids clearing BSS too early, thus addressing both problems with OF_SEPARATE on SH. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | sh: tmu: Fix SH4 TCNT0 offsetMarek Vasut2019-09-021-1/+1
| | | | | | | | | | | | | | | | | | | | | Fix the offset of TCNT0 register, which is 0xc on SH4. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | dm: core: Decouple DM from DTMarek Vasut2019-09-023-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some of the DM functions depend on OF_CONTROL, which is incorrect. DM and DT are orthogonal. Add macro guards around such functions to avoid compiling them in when DM is enabled, while OF_CONTROL is not. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Simon Glass <sjg@chromium.org>
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