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| * Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 ↵Tom Rini2019-12-18223-706/+12370
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into next - Various x86 common codes updated for TPL/SPL - I2C designware driver updated for PCI - ICH SPI driver updated to support Apollo Lake - Add Intel FSP2 base support - Intel Apollo Lake platform specific drivers support - Add a new board Google Chromebook Coral
| | * x86: Add chromebook_coralSimon Glass2019-12-1511-0/+1296
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for coral which is a range of Apollo Lake-based Chromebook released in 2017. This also includes reef released in 2016, since it is based on the same SoC. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: apl: Add FSP supportSimon Glass2019-12-153-0/+877
| | | | | | | | | | | | | | | | | | | | | | | | The memory and silicon init parts of the FSP need support code to work. Add this for Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: apl: Add FSP structuresSimon Glass2019-12-154-0/+440
| | | | | | | | | | | | | | | | | | | | | | | | These are mostly specific to a particular SoC. Add the definitions for Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: apl: Add Kconfig and MakefileSimon Glass2019-12-153-0/+98
| | | | | | | | | | | | | | | | | | | | | Add basic plumbing to allow Apollo Lake support to be used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: apl: Add P2SB driverSimon Glass2019-12-152-0/+167
| | | | | | | | | | | | | | | | | | | | | | | | Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports various child devices. It supposed both device tree and of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: apl: Add SPL/TPL initSimon Glass2019-12-152-0/+272
| | | | | | | | | | | | | | | | | | | | | | | | Add code to init the system both in TPL and SPL. Each phase has its own procedure. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: apl: Add a CPU driverSimon Glass2019-12-155-0/+81
| | | | | | | | | | | | | | | | | | | | | Add a bare-bones CPU driver so that CPUs can be probed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: apl: Add SPL loadersSimon Glass2019-12-152-0/+180
| | | | | | | | | | | | | | | | | | | | | | | | Add loaders for SPL and TPL so that the next stage can be loaded from memory-mapped SPI or, failing that, the Fast SPI driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * spl: Add methods to find the position/size of next phaseSimon Glass2019-12-152-1/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Binman supports writing the position and size of U-Boot proper and SPL into the previous phase of U-Boot. This allows the next phase to be easily located and loaded. Add functions to return these useful values, along with symbols to allow TPL to load SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: apl: Add PUNIT driverSimon Glass2019-12-152-0/+97
| | | | | | | | | | | | | | | | | | | | | | | | Add a driver for the Apollo Lake P-unit (power unit). It is modelled as a syscon driver since it only needs to be probed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: apl: Add PCH driverSimon Glass2019-12-153-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | Add a driver for the Apollo Lake Platform Controller Hub. It does not have any functionality and is just a placeholder for now. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: apl: Add LPC driverSimon Glass2019-12-153-0/+205
| | | | | | | | | | | | | | | | | | | | | | | | | | | This driver the LPC and provides a few functions to set up LPC features. These should probably use ioctls() or perhaps, better, have specific uclass methods. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: apl: Add ITSS driverSimon Glass2019-12-153-0/+258
| | | | | | | | | | | | | | | | | | | | | | | | | | | This driver models some sort of interrupt thingy but there are so many abreviations that I cannot find out what it stands for. Possibly something to do with interrupts. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: apl: Add hostbridge driverSimon Glass2019-12-152-0/+180
| | | | | | | | | | | | | | | | | | | | | | | | This driver models the hostbridge as a northbridge. It simply sets up the graphics BAR. It supports of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: apl: Add systemagent driverSimon Glass2019-12-153-0/+62
| | | | | | | | | | | | | | | | | | | | | | | | This driver handles communication with the systemagent which needs to be told when U-Boot has completed its init. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * i2c: designware: Add Apollo Lake supportSimon Glass2019-12-151-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | For Apollo Lake we need to take the I2C bus controller out of reset before using this. Add this functionality to the driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: apl: Add pinctrl driverSimon Glass2019-12-154-3/+691
| | | | | | | | | | | | | | | | | | | | | | | | Add a driver for the Apollo Lake pinctrl. This mostly makes use of the common Intel pinctrl support. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: apl: Add UART driverSimon Glass2019-12-153-0/+154
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add a driver for the Apollo Lake UART. It uses the standard ns16550 device but also sets up the input clock with LPSS and supports configuration via of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: apl: Add PMC driverSimon Glass2019-12-154-0/+296
| | | | | | | | | | | | | | | | | | | | | | | | Add a driver for the Apollo Lake SoC. It supports the basic operations and can use device tree or of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: apl: Add basic IO addressesSimon Glass2019-12-151-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | Add some fixed IO and mmap addresses for use in the device tree and with some early-init code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: Move qemu CPU fixup function into its own fileSimon Glass2019-12-154-68/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function is specific to qemu so it seems best to keep it separate from the generic code. Move it out to a new file and update the condition to use if() instead of #ifdef Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: Add a generic Intel GPIO driverSimon Glass2019-12-154-0/+226
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add a GPIO driver which uses the pinctrl driver to access the pad information. This driver relies on the GPIO nodes being subnodes to the pinctrl device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: Add a generic Intel pinctrl driverSimon Glass2019-12-158-0/+1385
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recent Intel SoCs share a pinctrl mechanism with many common elements. Add an implementation of this core functionality, allowing SoC-specific drivers to avoid adding common code. As well as a pinctrl driver this provides a GPIO driver based on the same code. Once other SoCs use this driver we may consider moving more properties to the device tree (e.g. the community info and pad definitions). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: Add low-power subsystem (lpss) supportSimon Glass2019-12-153-0/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | This subsystem is present on various Intel SoCs. Add very basic support for taking an lpss device out of reset. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: Enable pinctrl in SPL and TPLSimon Glass2019-12-152-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | If these phases are used we typically want to enable pinctrl in then, so that pad setup and GPIO access are possible. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * mtd: spi: Export spi_flash_std_probe()Simon Glass2019-12-152-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With of-platdata we need to create drivers for particular chips, or at least drivers that are separate from the standard code, since C structures are created by dtoc which are private to that driver. To avoid duplicating the probing code, export this probe function for use by these drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * spi: ich: Add Apollo Lake supportSimon Glass2019-12-152-5/+15
| | | | | | | | | | | | | | | | | | | | | | | | Add support for Apollo Lake to the ICH driver. This involves adjusting the mmio address and skipping setting of the bbar. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * spi: ich: Add TPL supportSimon Glass2019-12-151-4/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | In TPL we want to reduce code size and support running with CONFIG_PCI disabled. Add special code to handle this using a fixed BAR programmed into the SPI on boot. Also cache the SPI flash to speed up boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * spi: ich: Add support for get_mmap() methodSimon Glass2019-12-151-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | Add this method so that the memory-mapped location of the SPI flash can be queried. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * spi: ich: Support hardware sequencingSimon Glass2019-12-152-3/+245
| | | | | | | | | | | | | | | | | | | | | | | | Apollo Lake (APL) only supports hardware sequencing. Add support for this into the SPI driver, as an option. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * spi: ich: Support of-platdata for fast-spiSimon Glass2019-12-151-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | The Intel Fast SPI interface is similar to ICH. Add of-platdata support for this using the "intel,fast-spi" compatible string. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * spi: ich: Correct max-size bug in ich_spi_adjust_size()Simon Glass2019-12-151-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | This incorrectly shortens read operations if there is a maximum write size but no maximum read size. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * dm: doc: Add a note about of-platdata and header filesSimon Glass2019-12-151-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | We don't want to include dt-structs.h in header files, so add a note about that. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * spi: ich: Add mmio_base to struct ich_spi_platdataSimon Glass2019-12-152-19/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | It is useful to store the mmio base in platdata. It reduces the amount of casting needed. Update the code and move the struct to the C file at the same time, as we will need to use with of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * spi: ich: Various small tidy-upsSimon Glass2019-12-151-9/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use debug() instead of printf() to reduce code size and change a bool return value to the use the 'bool' type. Also drop the global data declaration since it not actually used. Finally, set the log category. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * spi: ich: Fix header orderSimon Glass2019-12-151-2/+2
| | | | | | | | | | | | | | | | | | | | | Move the header files into the right order. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * spi: ich: Convert to livetreeSimon Glass2019-12-151-17/+5
| | | | | | | | | | | | | | | | | | | | | | | | Use dev_get_driver_data() to obtain the device type. It has the same effect and is shorter. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * spi: ich: Move the protection/lockdown code into a functionSimon Glass2019-12-152-20/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reduce the size of the probe function but putting this code into its own function. Also remove the assumption that the PCH is always a parent of the SPI controller, as this is not the case APL platforms. Use driver model to find the PCH instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * spi: ich: Move init function just above probe()Simon Glass2019-12-151-61/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | It is annoying to have some of the init code in a different part of the file. Move ich_init_controller() to just above probe() to keep things together. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: spi: Don't enable SPI_FLASH_BAR by defaultSimon Glass2019-12-151-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We don't normally need this on x86 unless the size of SPI flash devices is larger than 16MB. This can be enabled by particular SoCs as needed, since it adds to code size. Drop the default enabling of this option on x86. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * spi: Correct operations check in dm_spi_xfer()Simon Glass2019-12-153-10/+6
| | | | | | | | | | | | | | | | | | | | | | | | At present we have to have an xfer() method even if it does nothing. This is not correct, so fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: Make MSR_PKG_POWER_SKU commonSimon Glass2019-12-153-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | This is used on several boards so add it to the common file. Also add a useful power-limit value while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: Separate out U-Boot and device tree in ROM imageSimon Glass2019-12-151-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present binman does not support updating a device tree that is part of U-Boot (i.e u-boot.bin). Separate the entries into two so that we can get updated entry information. This makes binman_entry_find() work correctly. Do the same for SPL tool. In both cases, group the two parts into a section so that SPL symbols get the correct total size. It may be possible for binman to handle this automatically at some point, by ignoring u-boot.bin and always creating it from u-boot-nodtb.bin and u-boot.dtb Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: Don't repeat microcode in U-Boot if not neededSimon Glass2019-12-151-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | At present if SPL sets up the microcode then it is still included in U-Boot as well. This is wasteful as microcode is large. Adjust the logic in the image to prevent this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: Add an fdtmap and image-headerSimon Glass2019-12-151-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add these entries to the ROM so that we can list the contents of an image with 'binman ls'. The image-header is not essential but does speed up access. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: Add an option to control the position of SPLSimon Glass2019-12-152-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For Apollo Lake SPL is run from CAR (cache-as-RAM) which is in a different location from where SPL must be placed in ROM. In other words, although SPL runs before SDRAM is set up, it is not execute-in-place (XIP). Add a Kconfig option for the ROM position. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: Add an option to control the position of U-BootSimon Glass2019-12-155-18/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The existing work-around for positioning U-Boot in the ROM when it actually runs from RAM still exists and there is not obvious way to change this. Add a proper Kconfig option to handle this case. This also adds a new bool property to indicate whether CONFIG_SYS_TEXT_BASE exists. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: Update .dtsi file for FSP2Simon Glass2019-12-151-1/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Include the IFWI section and the FSP-M binary. The FSP-T binary is not currently used, as CAR is set up manually. Also drop the FSP binary as this relates only to FSP1. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: Update the fsp command for FSP2Simon Glass2019-12-151-21/+44
| | | | | | | | | | | | | | | | | | | | | | | | The current 'fsp' command only works with FSP1. Update it to handle FSP2 as well. Convert everything to hex which is what U-Boot uses. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit (git 2.34.1) at 2024-10-01 05:00:54 +0000