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* Merge tag 'u-boot-atmel-fixes-2021.01-b' of ↵Tom Rini2020-12-116-19/+29
|\ | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-atmel Second set of u-boot-atmel fixes for 2021.01 cycle This set includes very important fixes for: MMC booting on several boards, drive strength on sam9x60ek mmc lines, compile issues for timer.c old driver, removal of unwanted access to sam9x60 bit for oscillator bypass mode, and eeproms read on sama5d2_icp.
| * ARM: dts: at91: sama5d2_icp: fix i2c eeprom compatibleEugen Hristev2020-12-111-3/+3
| | | | | | | | | | | | | | | | The correct compatible for this eeproms is microchip,24aa02e48 The previous compatible string was working up to U-boot 2020.04. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Tested-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
| * clk: at91: sam9x60: remove the parsing of atmel, main-osc-bypassClaudiu Beznea2020-12-071-4/+1
| | | | | | | | | | | | | | | | | | Remove the parsing of atmel,main-osc-bypass DT property as the SAM9X60 have no support for crystal oscillator bypass. Setting this bit might affect the device functionality. Fixes: a64862284f65 ("clk: at91: sam9x60: add support compatible with CCF") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * ARM: mach-at91: fix timer.o compile conditionEugen Hristev2020-11-261-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | The AT91 architecture now has two possible timer blocks, the old PIT timer and the new PIT64B. The timer.c file has an old non DM driver that works for platforms that do not use the ATMEL_PIT_TIMER DM-based driver. Update the Makefile to select this old driver in case neither of the ATMEL_PIT_TIMER and the MCHP_PIT64B_TIMER are selected. Suggested-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * ARM: at91: armv7: sama7g5 uses CCF clock driverNicolas Ferre2020-11-262-4/+7
| | | | | | | | | | | | | | | | | | | | SAMA7G5 uses CCF driver under drivers/clk/at91/ and not the custom older at91 clock.c driver. Remove it from the compilation list and adapt cpu.c arch_cpu_init() to avoid calling at91_clock_init() which is wrong anyway. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * ARM: dts: at91: sam9x60: enable slewrate/high drive for sdhci0 pinoutEugen Hristev2020-11-261-6/+12
| | | | | | | | | | | | | | Align the pin setup for sdhci0 with linux kernel. This means to have slew rate enable and high drive strength. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * mmc: atmel-sdhci: fix the clk_enable call in case of no opsEugen Hristev2020-11-261-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the clock driver does not offer a clk_enable ops, then the system will return -ENOSYS. The clk_enable works with CCF (common clock framework). Some clocks in some cases (like the generic clock for some products: sama5d2) do not have the clk_enable primitive, and in this case probing of the driver will fail. This patch changes the behavior to return an error in case there is really an error, and not a missing primitive. If the clock driver does not have an enable primitive, most likely clocks are always enabled or enabled in the set_rate primitives. Fixes: 81f16438d4 ("mmc: atmel-sdhci: enable the required generic clock") Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini2020-12-1186-292/+2434
|\ \ | | | | | | | | | | | | | | | - Add lx2162 soc, lx2162qds support. - Bug-fixes related ls102x-usb, ifc, bootcmd, secure-boot header, - rgmii, vid, fdt, env variable, pci for Layerscape products
| * | configs: lx2162aqds: Enable gpio driver in defconfigHui Song2020-12-103-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | make lx2162aqds platform to enable gpio driver. Signed-off-by: Hui Song <hui.song_1@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | arm: ls102xa: select USB PHY erratum's only if USB is enabledAleksandar Gerasimovski2020-12-101-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The USB support is not by default enabled on all designs, so it does not make seance to have USB specific erratum's enabled on such a designs. On our internal Hitachi-Powergrids design not using the USB controller there is a crash when accessing those specific memory locations selected by the erratum flags. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | drivers: ifc: add define for IFC_CSPRn TE bitAleksandar Gerasimovski2020-12-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | To drive TE pin high is supported IFC configuration that can be used on some designs. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | powerpc: mpc85xx: Allow boards to override CONFIG_USB_MAX_CONTROLLER_COUNTChris Packham2020-12-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | If the board isn't strapped to enable USB1 then attempting to access it will result in a hang. Avoid this by allowing boards to define CONFIG_USB_MAX_CONTROLLER_COUNT. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | armv8: fsl-layerscape: Fix automatic setting of bootmcd with TF-AAlban Bedel2020-12-101-23/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When booting from TF-A there is a logic that attempt to detect if the default environment is used, if this is the case it then set the `bootcmd` and `mcinitcmd` depending of the device we booted from. This detection logic is dubious as it access internals of the env implementation and it doesn't always work correctly. First of all it detect any valid environment as not being the default, so after running `env default -a && saveenv` the board doesn't boot anymore as `bootcmd` is then empty. But it also fails in some other ways, for example it always detect a default environment when redundant env is enabled on MMC, so in that case `bootcmd` is overwritten on every boot. Instead of increasing the complexity of the detection just check if `bootcmd` and `mcinitcmd` are set in the environment and set them if they are not. Signed-off-by: Alban Bedel <alban.bedel@aerq.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | net: pfe_eth: read PFE ESBC header flash with spi_flash_read APIBiwen Li2020-12-104-10/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Read PFE ESBC header flash with spi_flash_read API - logs as follows, Net: SF: Detected s25fs512s with page size 256 Bytes, erase size 256 KiB, total 64 MiB "Synchronous Abort" handler, esr 0x96000210 elr: 000000008206db44 lr : 0000000082004ea0 (reloc) elr: 00000000b7ba6b44 lr : 00000000b7b3dea0 x0 : 00000000b79407e8 x1 : 0000000040640000 x2 : 0000000000000050 x3 : 0000000000000000 x4 : 000000000000000a x5 : 0000000000000050 x6 : 0000000000000366 x7 : 00000000b7942308 x8 : 00000000b76407c0 x9 : 0000000000000008 x10: 0000000000000044 x11: 00000000b7634d1c x12: 000000000000004f x13: 0000000000000044 x14: 00000000b7634d98 x15: 00000000b76407c0 x16: 0000000000000000 x17: 0000000000000000 x18: 00000000b7636dd8 x19: 0000000000000000 x20: 00000000b79407d0 x21: 00000000b79407e8 x22: 0000000040640000 x23: 00000000b7634e58 x24: 0000000000000000 x25: 0000000003800000 x26: 00000000b7bdd000 x27: 0000000000000000 x28: 0000000000000000 x29: 00000000b7634d10 Code: d2800003 eb03005f 54000101 d65f03c0 (f8636826) Resetting CPU ... Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | lx2160a: Fix address for secure boot headersManish Tomar2020-12-101-1/+1
| | | | | | | | | | | | | | | | | | | | | Update kernel_size_sd variable with correct value for lx2160a. Signed-off-by: Manish Tomar <manish.tomar@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | ls1043a: Fix address for secure boot headersManish Tomar2020-12-101-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Update kernelheader_addr and kernelheader_addr variables with correct values for ls1043a. Signed-off-by: Manish Tomar <manish.tomar@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | layerscape: fdt.c: Check for NULL return value from fdt_getprop()Priyanka Singh2020-12-101-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Check for NULL return value from fdt_getprop() in fdt_fixup_remove_jr() Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com> [Fixed checkpatch errors/warnings] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | board: freescale: powerpc: add support for all RGMII modesMadalin Bucur2020-12-108-10/+55
| | | | | | | | | | | | | | | | | | | | | Make sure all RGMII internal delay modes are covered. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | armv8: ls1043/ls1046aqds: add support for all RGMII modesMadalin Bucur2020-12-102-0/+4
| | | | | | | | | | | | | | | | | | | | | Make sure all RGMII internal delay modes are covered. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | board: freescale: vid.c: Initialize variable 'i2caddress'Priyanka Singh2020-12-101-1/+1
| | | | | | | | | | | | | | | | | | | | | Initialize variable 'i2caddress' in adjust_vdd() to zero Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | include/configs: ls1012aqds: add default environment variableBiwen Li2020-12-101-0/+62
| | | | | | | | | | | | | | | | | | | | | This adds default environment variable for ls1012aqds Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | board/freescale/common: fix a bug that failed to read/write eeprom on ls1021atsnBiwen Li2020-12-101-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | Fix a bug that failed to read/write eeprom on ls1021atsn Signed-off-by: Biwen Li <biwen.li@nxp.com> Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | pci: layerscape: fix a dead loop issueHou Zhiqiang2020-12-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes: commit 8ec619f8fd84 ("pci: layerscape: Fixup PCIe EP mode DT nodes for LX2160A rev2") This added the PCIe EP nodes fixup of LX2160A, but it didn't update the condition value when there isn't a property 'apio-wins'. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [Fixed checkpatch error] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | configs: lx2162aqds: enable eMMC HS400 mode supportYangbo Lu2020-12-103-0/+3
| | | | | | | | | | | | | | | | | | | | | Enable eMMC HS400 mode support on LX2162AQDS. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | configs: lx2162aqds: enable CONFIG_BOARD_EARLY_INIT_RYangbo Lu2020-12-103-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable CONFIG_BOARD_EARLY_INIT_R for SDHC adapter card identification and configuration. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | configs: lx2162a: Enable OPTEE supportRuchika Gupta2020-12-101-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable support to compile OPTEE driver, access AVB TA and RPMB API's access via RPC from OPTEE for lx2162 Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | armv8: lx2162aqds: Add support for LX2162AQDS platformMeenakshi Aggarwal2020-12-1028-150/+1935
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add base support for LX2162AQDS board. LX2162AQDS board supports LX2162A family SoCs. This patch add basic support of platform. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Signed-off-by: hui.song <hui.song_1@nxp.com> Signed-off-by: Manish Tomar <manish.tomar@nxp.com> Signed-off-by: Vikas Singh <vikas.singh@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | armv8: lx2162a: Add Soc changes to support LX2162AMeenakshi Aggarwal2020-12-1021-42/+171
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | drivers/net/phy: Add CORTINA_NO_FW_UPLOAD to KconfigMeenakshi Aggarwal2020-12-109-6/+18
| | | | | | | | | | | | | | | | | | | | | | | | Move CORTINA_NO_FW_UPLOAD to Kconfig file so that it can be controlled via defconfig files. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | pci: ls_pcie_g4: Add size check for config resourceWasim Khan2020-12-101-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | resource "config" is required to have minimum 4KB space to access all config space of PCI Express EP. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | pci: layerscape: Add size check for config resourceWasim Khan2020-12-101-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | resource "config" is required to have minimum 8KB space as per hardware documentation. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | arm: dts: ls1028a: add label to pcie nodes in dtsWasim Khan2020-12-101-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Add label to pcie nodes in dts so that these nodes are easy to refer. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | arm: dts: ls1043a: add label to pcie nodes in dtsWasim Khan2020-12-101-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | Add label to pcie nodes in dts so that these nodes are easy to refer. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | arm: dts: ls1012a: add label to pcie nodes in dtsWasim Khan2020-12-101-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Add label to pcie nodes in dts so that these nodes are easy to refer. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | arm: dts: ls1088a: add label to pcie nodes in dtsWasim Khan2020-12-101-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Add label to pcie nodes in dts so that these nodes are easy to refer. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | arm: dts: ls2080a: add label to pcie nodes in dtsWasim Khan2020-12-101-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | Add label to pcie nodes in dts so that these nodes are easy to refer. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | arm: dts: ls1046a: add label to pcie nodes in dtsWasim Khan2020-12-101-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | Add label to pcie nodes in dts so that these nodes are easy to refer. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | arm: dts: lx2160a: add label to pcie nodes in dtsWasim Khan2020-12-101-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add label to pcie nodes in dts so that these nodes are easy to refer. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | pci: ls_pcie_g4: Print pcie controller number starting from 1Wasim Khan2020-12-101-4/+7
| | | | | | | | | | | | | | | | | | Print pcie controller number starting from 1 Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
| * | pci: layerscape: Update print of pcie controllerWasim Khan2020-12-102-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | Print pcie controller number starting from 1 Signed-off-by: Wasim Khan <wasim.khan@nxp.com> [Trimmed subject] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | configs: lx2160a: Enable CONFIG_PCIE_LAYERSCAPE_GEN4Wasim Khan2020-12-105-0/+5
|/ / | | | | | | | | | | | | | | LX2160A-Rev1 uses PCIe layerscape Gen4 controller. Enable CONFIG_PCIE_LAYERSCAPE_GEN4 for lx2160a. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | Merge tag 'u-boot-stm32-20201209' of ↵Tom Rini2020-12-0940-41/+77
|\ \ | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-stm - Manage CONFIG_ENV_EXT4_DEVICE_AND_PART in stm32mp1 board - Update ARM STI and ARM STM STM32MP Arch maintainers emails - Enable internal pull-ups for SDMMC1 on DHCOM SoM
| * | ARM: dts: stm32: Add USB OTG ID pin on DH AV96Marek Vasut2020-12-091-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add USB OTG ID pin mux and switch the USB OTG port from peripheral to OTG mode. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| * | ARM: dts: stm32: Enable SDMMC3 on DH DRC02Marek Vasut2020-12-091-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DH DRC02 board has an on-board microSD slot, add DT properties to enable the slot. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| * | ARM: dts: stm32: Disable SDMMC1 CKIN feedback clockMarek Vasut2020-12-091-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The STM32MP1 DHCOM SoM can be built with either bus voltage level shifter or without one on the SDMMC1 interface. Because the SDMMC1 interface is limited to 50 MHz and hence SD high-speed anyway, disable the SD feedback clock to permit operation of the same U-Boot image on both SoM with and without voltage level shifter. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| * | ARM: dts: stm32: Enable internal pull-ups for SDMMC1 on DHCOM SoMMarek Vasut2020-12-091-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The default state of SD bus and clock line is logical HI. SD card IO is open-drain and pulls the bus lines LO. Always enable the SD bus pull ups to guarantee this behavior on DHCOM SoM. Note that on SoMs with SD bus voltage level shifter, the pull ups are built into the level shifter, however that has no negative impact. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| * | .mailmap: map Patrick Delaunay and my email addressPatrice Chotard2020-12-091-0/+2
| | | | | | | | | | | | | | | | | | | | | Add our new email address dedicated for upstream activities. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | treewide: Update email address Patrick Delaunay and Patrice ChotardPatrice Chotard2020-12-0934-34/+34
| | | | | | | | | | | | | | | | | | | | | | | | Update Patrick and my email address with the one dedicated to upstream activities. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | MAINTAINERS: Update ARM STI and ARM STM STM32MP Arch maintainers emailsPatrice Chotard2020-12-091-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Update Patrick and my email address with the one dedicated to upstream activities. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | add check for ignored CONFIG_ENV_EXT4_DEVICE_AND_PART definitionManuel Reis2020-12-091-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check whether user has explicitly defined device and partition where environment file will be located before using 'auto' i.e. bootable partition Voids the need to set such partition as bootable to work with the 'dev:auto' tuple Signed-off-by: Manuel Reis <mluis.reis@gmail.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Tested-by: Michael Opdenacker <michael.opdenacker@bootlin.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
generated by cgit (git 2.34.1) at 2024-10-03 22:51:06 +0000