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* efi_selftest: correct block device unit testHeinrich Schuchardt2018-08-201-1/+1
| | | | | | | | The UEFI specification mandates that the create flag is only used in conjunction with both the read and the write flag. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de>
* efi_loader: document runtime functionsHeinrich Schuchardt2018-08-201-4/+149
| | | | | | | Add comments for runtime service functions. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de>
* efi_loader: update runtime services table crc32Heinrich Schuchardt2018-08-203-12/+18
| | | | | | | | | | The crc32 of the runtime services table must be updated after detaching. efi_update_table_header_crc32() must be __efi_runtime. So move it to efi_runtime.c Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de>
* lib: crc32: mark function crc32() as __efi_runtimeHeinrich Schuchardt2018-08-201-12/+14
| | | | | | | | | | | | The function crc32() is needed by the EFI subsystem at runtime. So it has to be linked into the runtime section together with all dependencies. Eliminate empty defines local and ZEXPORT. Mark variables as static which are not exported. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de>
* efi_loader: avoid NULL dereference in efi_get_memory_map()Heinrich Schuchardt2018-08-201-1/+3
| | | | | | | | | We should only dereference parameter memory_map_size after checking that it is valid. Fixes: 8e835554b36b ("efi_loader: check parameters of GetMemoryMap") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de>
* efi_loader: fix a parameter check at CreateEvent()AKASHI Takahiro2018-08-201-1/+2
| | | | | | | | | | | | | | | | | | | The commit 21b3edfc9644 ("efi_loader: check parameters of CreateEvent") enforces a strict parameter check at CreateEvent(). On the other hand, UEFI specification version 2.7, section 7.1, says: The EVT_NOTIFY_WAIT and EVT_NOTIFY_SIGNAL flags are exclusive. If neither flag is specified, the caller does not require any notification concerning the event and the NotifyTpl, NotifyFunction, and NotifyContext parameters are ignored. So the check should be mitigated so as to comply with the specification. Without this patch, EDK2's Shell.efi won't be started. Fixes: 21b3edfc9644 ("efi_loader: check parameters of CreateEvent") Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de>
* riscv: Include bss subsections in linker scriptAlexander Graf2018-08-201-1/+1
| | | | | | | | | When we build with -fdata-sections we may end up with bss subsections. Our linker script explicitly lists only a single consecutive bss section though. Adapt the statement to also include subsections. Signed-off-by: Alexander Graf <agraf@suse.de>
* x86: Enable -fdata-sections alwaysAlexander Graf2018-08-201-3/+1
| | | | | | | | | | | We left -fdata-sections disabled for x86_64 before because we encountered random bugs that were at that time inexplicable. Turns out this really was just side effects of missing .bss* statements in the linker scripts. With those fixed, we can enable data sections for all targets. Signed-off-by: Alexander Graf <agraf@suse.de>
* x86: Include bss subsections in linker scriptAlexander Graf2018-08-204-4/+4
| | | | | | | | | | | When we build with -fdata-sections we may end up with bss subsections. Our linker script explicitly lists only a single consecutive bss section though. Adapt the statement to also include subsections. This fixes booting efi-x86_app_defconfig. Signed-off-by: Alexander Graf <agraf@suse.de>
* efi_loader: relocate pointer to tablesHeinrich Schuchardt2018-08-201-1/+8
| | | | | | | | | | | When applying a virtual memory map we have to update the pointer to the list of configuration tables. Fixes: 4182a129ef73 ("efi_loader: allocate configuration table array") Reported-by: Mark Kettenis <mark.kettenis@xs4all.nl> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Tested-by: Mark Kettenis <kettenis@openbsd.org> Signed-off-by: Alexander Graf <agraf@suse.de>
* Revert "efi_loader: efi_allocate_pages is too restrictive"Stephen Warren2018-08-201-1/+1
| | | | | | | | | | | | | | | | | | This reverts commit aa909462d01866354f4cd4534db5f571c2cf1fbb. This change caused "dhcp filename" to crash the system on p2371-2180 (Jetson TX1), for example when running test/py. Reverting this change isn't optimal, but at least restores TX1 to a working state. In the future, we should: a) Fix whatever problem causes the crash with this patch applied. This needs further discussion, so isn't something we can immediately do. b) Undo the revert; re-apply the original patch to efi_allocate_pages. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Alexander Graf <agraf@suse.de>
* sandbox: Move BSS after EFI sectionsAlexander Graf2018-08-201-3/+2
| | | | | | | | | | | Something went wrong when writing the sandbox linker scripts and so we ended up with a .bss section marker right before the efi runtime sections. That obviously is a terrible idea, as it may result in overwriting efi runtime code and data. So let's move the .bss identifier behind the efi sections. Signed-off-by: Alexander Graf <agraf@suse.de>
* Convert CONFIG_SYS_I2C_DAVINCI to KconfigAdam Ford2018-08-1721-6/+20
| | | | | | | This converts the following to Kconfig: CONFIG_SYS_I2C_DAVINCI Signed-off-by: Adam Ford <aford173@gmail.com>
* Removed unused references to CONFIG_SERIALxAdam Ford2018-08-1736-43/+6
| | | | | | | | | After creating CONS_INDEX and migrating a bunch of boards to it, there are a bunch of defined references to CONFIG_SERIALx which are not referenced in any C code or #ifdef, so they can now be removed Signed-off-by: Adam Ford <aford173@gmail.com>
* Convert CONFIG_TWL4030_LED et al to KconfigAdam Ford2018-08-1727-16/+23
| | | | | | | | | | | This converts the following to Kconfig: CONFIG_TWL4030_LED CONFIG_TWL4030_INPUT This also removes dead references to: CONFIG_TWL4030_KEYPAD Signed-off-by: Adam Ford <aford173@gmail.com>
* Convert CONFIG_VIDEO_OMAP3 to KconfigAdam Ford2018-08-1712-6/+11
| | | | | | | This converts the following to Kconfig: CONFIG_VIDEO_OMAP3 Signed-off-by: Adam Ford <aford173@gmail.com>
* Convert CONFIG_MISC_INIT_R to KconfigAdam Ford2018-08-17447-235/+326
| | | | | | | | | This converts the following to Kconfig: CONFIG_MISC_INIT_R Signed-off-by: Adam Ford <aford173@gmail.com> [trini: Update the defaults logic slightly] Signed-off-by: Tom Rini <trini@konsulko.com>
* Migrate bootlimit to KconfigAlex Kiernan2018-08-1737-6/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | Migrate boards which set bootlimit in the environment to Kconfig. We exclude gurnard_defconfig which includes a bootlimit=, but doesn't set CONFIG_BOOTCOUNT_LIMIT, so we'd fail to include a bootlimit setting if we migrated it. display5_defconfig and display5_factory_defconfig share a SYS_CONFIG_NAME, but only display5_defconfig enables CONFIG_BOOTCOUNT_LIMIT, so we fail to set bootlimit= in display5_factory_defconfig. This is okay because the display5_factory_defconfig doesn't need to have it set, as it is only meant to prepare the board in the factory. Environment changes for all modified configs as seen from buildman: boards.cfg is up to date. Nothing to do. Summary of 3 commits for 32 boards (8 threads, 1 job per thread) 01: Merge git://git.denx.de/u-boot-x86 arm: + draco etamin rastaban pxm2 display5 thuban rut 02: Add BOOTCOUNT_BOOTLIMIT to set reboot limit 03: Migrate bootlimit to Kconfig - display5_factory: bootlimit=3 Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
* Add BOOTCOUNT_BOOTLIMIT to set reboot limitAlex Kiernan2018-08-172-0/+11
| | | | | | Add ability to set environment bootlimit from Kconfig Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
* Convert CONFIG_MII et al to KconfigAdam Ford2018-08-17882-630/+714
| | | | | | | | | | This converts the following to Kconfig: CONFIG_MII CONFIG_DRIVER_TI_EMAC Signed-off-by: Adam Ford <aford173@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* dts: Fix typo in OF_LIVE Kconfig helpMichal Simek2018-08-171-1/+1
| | | | | | Fix typo in Kconfig description. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* kconfig: fix typo 'parition'Simon Goldschmidt2018-08-172-2/+2
| | | | | | | | Replaced misspelled words "parition"/"paritioning" (missing 't') in two Kconfig files by correct words "partition"/"partitioning" Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2018-08-175-1/+202
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| * ARM: rmobile: Enable USB PHY on Gen2Marek Vasut2018-08-141-0/+2
| | | | | | | | | | | | | | | | Enable support for USB PHY on the R-Car Gen2. This allows for both of the USB host ports to be used on such boards. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * phy: rcar: Add R-Car Gen2 PHY driverMarek Vasut2018-08-143-0/+199
| | | | | | | | | | | | | | | | Add a PHY driver for the R-Car Gen2 which allows configuring the mux connected to the EHCI controllers and USBHS controller. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * phy: Fix off-by-one error when parsing DT PHY bindingsMarek Vasut2018-08-141-1/+1
| | | | | | | | | | | | | | | | | | The code fails to copy the last PHY phandle argument, so it is missing from the adjusted phandle args and the consumer cannot use it to determine what the PHY should do. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2018-08-1735-627/+800
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| * | arm: socfpga: Fix SYSMGR_FPGAINTF_EMACx bit maskLey Foon Tan2018-08-151-3/+3
| | | | | | | | | | | | | | | | | | Bitmask for EMAC should be bit-0, EMAC1 bit-8 and EMAC2 bit-16. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | ARM: socfpga: clk: Convert to clock frameworkMarek Vasut2018-08-132-218/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use clock framework functions to fetch clock information now that there is a clock driver for Arria10, instead of custom coded register parsing. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | mmc: socfpga: Add clock framework supportMarek Vasut2018-08-131-9/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for fetching the clock frequency both using the legacy method in case clock framework is disabled as well as via the clock framework if it is enabled. This allows for migration to the clock framework on platforms which supports it while not breaking legacy platforms. That said, the legacy method must be removed eventually. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | clk: socfpga: Add initial Arria10 clock driverMarek Vasut2018-08-133-0/+371
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add clock driver for the Arria10, which allows reading the clock frequency from all the clock described in the DT. The driver also allows enabling and disabling the clock. Reconfiguring frequency is not supported thus far. Since the DT bindings for the SoCFPGA clock are massively misdesigned and the handoff DT adds additional incorrectly described entries to the DT, the driver contains workarounds which attempt to rectify all of those problems. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | ARM: dts: socfpga: Add u-boot,dm-pre-reloc to necessary clock nodesMarek Vasut2018-08-133-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the pre-reloc DT markers to clock nodes needed in SPL and early U-Boot stages. This is required to let the Arria10 clock driver start early and provide clock information for UART and SDMMC. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | ARM: socfpga: clk: Drop unused variables on Arria10Marek Vasut2018-08-131-17/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The variables removed in this patch are never used, they are only ever assigned and then waste precious memory. Drop both the assignment and the variables. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | ARM: socfpga: clk: Make L4SP and MMC clock calculation Gen5 onlyMarek Vasut2018-08-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The L4SP and MMC clock precalculation is specific to Gen5, it is not needed on Arria10/Stratix10. Isolate it to Gen5 until there is a proper clock driver for Gen5, at which point this will go away completely. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | ARM: socfpga: clk: Obtain handoff base clock via DMMarek Vasut2018-08-132-12/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bind fixed clock driver to the base clock instantiated in the handoff DT and use DM clock framework to get their clock rate. This replaces the ad-hoc DT parsing present thus far. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | ARM: socfpga: Enable DM ethernet on A10Marek Vasut2018-08-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable DM ethernet framework on Arria10, so that the designware GMAC can be probed from DT as it should be. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | ARM: socfpga: Remove adhoc ethernet reset and configurationMarek Vasut2018-08-133-50/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove ad-hoc ethernet syscon registers configuration and reset support. Reset is now handled by the reset framework and the syscon registers are set in the dwmac_socfpga.c driver. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | ARM: socfpga: Zap unused reset codeMarek Vasut2018-08-132-126/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove code from the reset manager that is never called. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | net: designware: socfpga: Add Arria10 extrasMarek Vasut2018-08-133-0/+152
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add wrapper around the designware MAC driver to handle the SoCFPGA specific configuration bits. On Arria10, this is configuration of syscon phy_intf. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
| * | ARM: socfpga: Zap all the UART handling complexityMarek Vasut2018-08-135-149/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The UART reset handling is now done via reset framework using the SoCFPGA reset driver. The UART console assignment is done using the DM and console framework. Nuke all this comlexity, since it is just duplicating the same functionality, badly. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
| * | ARM: socfpga: Enable DM I2C framework on A10Marek Vasut2018-08-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the DM I2C framework on Arria10, so that the DM capable Designware I2C driver can handle the reset via DM reset framework. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | ARM: socfpga: Enable DM reset framework on A10Marek Vasut2018-08-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the DM reset framework and DM reset driver on Arria10 both in U-Boot and in SPL. This lets U-Boot parse reset control from DT. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | ARM: dts: socfpga: Add i2c alias to A10 SoCDKMarek Vasut2018-08-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A10 SoCDK is missing the I2C bus alias, so DM I2C cannot assign the I2C bus a bus number. Add the missing alias. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | ARM: dts: socfpga: Add missing I2C resetsMarek Vasut2018-08-131-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The I2Cx resets are missing from DT, so the reset manager cannot control them. Add the missing DT reset entries. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | ARM: dts: socfpga: Fix Arria10 GMAC resetsMarek Vasut2018-08-131-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the GMAC0,1 OCP resets, which must also be ungated for those GMACs to work and add GMAC2 reset and OCP resets which were missing altogether. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | ARM: dts: socfpga: Add missing UART resetsMarek Vasut2018-08-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The UART0 and UART1 resets are missing from DT, so the reset manager cannot control them. Add the missing DT reset entries. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | ARM: dts: socfpga: Flag reset manager on A10 as pre-relocMarek Vasut2018-08-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Altera reset manager block must be available very early on, since it controls ie. UART resets. Flag it as pre-reloc. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | ARM: socfpga: Register the FPGA on A10 in SPL againMarek Vasut2018-08-131-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The restructuring of the SPL dropped registration of the FPGA in SPL, readd it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Fixes: c859f2a77d98 ("arm: socfpga: Restructure the SPL file")
| * | arm: socfpga: gen5: combine some init code for SPL and U-BootSimon Goldschmidt2018-08-133-39/+22
| | | | | | | | | | | | | | | | | | | | | | | | Some of the code for low level system initialization in SPL's board_init_f() and U-Boot's arch_early_init_r() is the same, so let's combine it into a single function called from both. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * | arm: socfpga: fix device trees to work with DM serialSimon Goldschmidt2018-08-1311-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | Device trees need to have the serial console device available before relocation and require a stdout-path in chosen at least for SPL to have a console. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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