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* Drop global data sdhc_adapter for powerpcYangbo Lu2020-07-272-4/+1
| | | | | | | | | | The sdhc_adapter of global data has not been used, and we do not have to use it as global data even we may need it in the future. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: ls1028ardb: add xspi parameter to qixis commandYuantian Tang2020-07-272-2/+15
| | | | | | | | Add xspi boot source to qixis command to let the soc boot from flex-nor flash chip. Signed-off-by: Yuantian Tang <andy.tang@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: ls1012a: RGMII ports require internal delayChaitanya Sakinam2020-07-272-2/+2
| | | | | | | | | | The correct setting for the RGMII ports on LS1012ARDB is to enable delay on both Rx and Tx so the interface mode used should be PHY_INTERFACE_MODE_RGMII_ID Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com> Signed-off-by: Anji J <anji.jagarlmudi@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* include/configs: ls1012a: Remove fdt_high env variableUdit Agarwal2020-07-275-5/+5
| | | | | | | | | Remove "fdt_high" environment variable to use the bootm_size to safely contain a kernel, device tree and initrd for relocation. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* config: lx2160/2a: enable dspiZhao Qiang2020-07-271-0/+3
| | | | | | | | Enable dspi in lx2160aqds tfa defconfig Enable CONFIG_SPI_FLASH_SST/EON in config file. Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: dts: fsl-lx2160a: add flash node under dspi to qds dtsZhao Qiang2020-07-271-0/+99
| | | | | | | Add flash node under dspi into fsl-lx2160a-qds.dtsi Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* crypto/fsl: fix unaligned accessMichael Walle2020-07-271-14/+13
| | | | | | | | | | | | | | | | | | | | On aarch64 running with dcache off, will result in an unaligned access exception: => dcache off => hash sha1 $kernel_addr_r 100 "Synchronous Abort" handler, esr 0x96000061 elr: 00000000960317d8 lr : 00000000960316a4 (reloc) elr: 00000000fbd787d8 lr : 00000000fbd786a4 [..] The compiler emits a "stur x1, [x0, #12]". x1 is might just be 32 bit aligned pointer. Remove the unused u64 element from the union to drop the minimal alignment to 32 bit. Also remove the union, because it is no more needed. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* I2C: ls1043a, ls1046a: enable SYS_I2C_MXCBiwen Li2020-07-273-5/+3
| | | | | | | | | This enables SYS_I2C_MXC to fix a bug that failed to boot from sd card with image u-boot-with-spl-pbl.bin Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: layerscape: rework spin tableMichael Walle2020-07-271-60/+23
| | | | | | | | | | | | | | | | | | | | There are two issues: (1) The spin table doesn't convert the endianness of the jump address. Although there is code for it, the result isn't used at all (x0). (2) If something goes wrong, the function returns. But that doesn't make sense at all. Use the actual converted jump address as destination to fix. If there is an error, jump to a trap loop. And rearrange the code exception level switching code to make it smaller and clearer. This reduces the size of the spin table code section from 696 bytes to 424 bytes. If CONFIG_ARMV8_SWITCH_TO_EL1 the code size reduced from 696 bytes to 632 bytes. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: layerscape: relocate spin table if EFI_LOADER is enabledMichael Walle2020-07-271-0/+36
| | | | | | | | | | | On ARM64, a 64kb region is reserved for the runtime services code. Unfortunately, this code overlaps with the spin table code, which also needs to be reserved. Thus now that the code is relocatable, allocate a new page from EFI, copy the spin table code into it, update any pointers to the old region and the start the secondary CPUs. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: layerscape: clean exported symbols in spintable.SMichael Walle2020-07-274-21/+24
| | | | | | | | | | | Add a new variable secondary_boot_code_start, which holds a pointer to the start of the spin table code. This will help to relocate the code section. While at it, move the size variable from the end to the beginning so there is a common section for the variables. Remove any other symbols. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: layerscape: drop first .ltorg directive in spintable.SMichael Walle2020-07-271-2/+0
| | | | | | | | Now that the spin table is in a separate module, this is no longer necessary. Drop it. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: layerscape: make wake_secondary_core_n() staticMichael Walle2020-07-271-1/+1
| | | | | | | This function is not used outside the module. Make it static. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: layerscape: simplify get_spin_tbl_addr() callsMichael Walle2020-07-271-8/+7
| | | | | | | | There is no need to cast around. Assign the address to the local variable and use it. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: layerscape: remove determine_mp_bootpg()Michael Walle2020-07-272-6/+0
| | | | | | | Only the PowerPC architecture needs this function. Remove it. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: layerscape: fix alignment for spin tableMichael Walle2020-07-271-2/+2
| | | | | | | | Fix the alignment so it will match the comments. The spin table has to be 8 byte aligned, so ".align 3" is enough. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: layerscape: load function pointer using ADRMichael Walle2020-07-271-3/+3
| | | | | | | | | Don't use LDR to load a pointer to a function. This will generate a literal which cannot be relocated. Use ADR which is PC-relative and therefore can easily be relocated. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: layerscape: move spin table into own moduleMichael Walle2020-07-273-150/+161
| | | | | | | | | | | Move it out of lowlevel.S into spintable.S. On layerscape, the secondary CPUs are brought up in main u-boot. This will make it possible to only compile the spin table code for the main u-boot and omit it in SPL. This saves about 720 bytes in the SPL. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: layerscape: properly use CPU_RELEASE_ADDRMichael Walle2020-07-278-9/+18
| | | | | | | | | | | | The generic armv8 code already has support to bring up the secondary cores. Thus, don't hardcode the jump in the layerscape lowlevel_init to the spin table code; instead just return early and let the common armv8 code handle the jump. This way we can actually use the CPU_RELEASE_ADDR feature. Signed-off-by: Michael Walle <michael@walle.cc> [Rebased, Removed kontron_sl28.h change as file does not exist] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: layerscape: pretty print info about SMP coresMichael Walle2020-07-271-4/+5
| | | | | | | | Make the print of the starting address a debug output and pretty print the info about online cores. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: layerscape: fix spin-table supportMichael Walle2020-07-272-11/+5
| | | | | | | | | | | | | | | | | | | Spin tables are broken with bootefi. This is because - in contrast to the booti call chain - there is no call to smp_kick_all_cpus(). Due to this missing call the secondary CPUs are never released from their "wait for interrupt state", see secondary_boot_func() in lowlevel.S. Originally, this "wait for interrupt" is there to make sure, the spin table is cleared before the secondary cores read it for the first time. But the boot flow for the layerscape architecture is different from that. The CPUs are release from their BootROM _after_ U-Boot's spin-table is cleared, see fsl_layerscape_wake_seconday_cores() in mp.c. Thus, there is no need to wait for this interrupt and no need for kicking all cores on cpu_release. An atomic 64bit write to the spin-table and a "sev" is sufficient. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* net: pfe_eth: Use spi_flash_read API to access flash memoryKuldeep Singh2020-07-272-2/+48
| | | | | | | | | | Current PFE firmware access spi-nor memory directly. New spi-mem framework does not support direct memory access. So, let's use spi_flash_read API to access memory instead of directly using it. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* dm: armv8: gpio: include <asm/arch/gpio.h> for fsl-layerscapehui.song2020-07-271-6/+2
| | | | | | | Enable the gpio feature on fsl-layerscape platform. Signed-off-by: hui.song <hui.song_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: gpio: add gpio featurehui.song2020-07-271-0/+22
| | | | | | | add one struct mpc8xxx_gpio_plat to enable gpio feature. Signed-off-by: hui.song <hui.song_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* configs: ls1088ardb: Add support for usb boot targetEra Tiwari2020-07-271-0/+1
| | | | | | | | | | | LS1088A-RDB has MMC, SCSI, DHCP as boot targets, but the USB support was missing. Add support for USB as Boot_targets_devices. Signed-off-by: Era Tiwari <era.tiwari@nxp.com> Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: ls1028a: move FSL_LAYERSCAPE to kconfigMichael Walle2020-07-272-1/+1
| | | | | | | | | | CONFIG_FSL_LAYERSCAPE is available in kconfig. There is no need to define it per board; the ls1028a_common.h is really board dependent and only fits to the NXP eval boards. Instead select CONFIG_FSL_LAYERSCAPE when ARCH_LS1028A is selected. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* fsl_dspi: Introduce DT bindings for CS-SCK and SCK-CS delaysVladimir Oltean2020-07-273-1/+58
| | | | | | | | | | | | | | Communication with some SPI slaves just won't cut it if these delays (before the beginning, and after the end of a transfer) are not added to the Chip Select signal. These are a straight copy from Linux: Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt drivers/spi/spi-fsl-dspi.c Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscvTom Rini2020-07-2420-51/+178
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Fix SiFive HiFive Unleashed board booting failure problem. - Enable SiFive fu540 PWM driver. - Support SiFive fu540: SPI boot. - Update OpenSBI used for RISC-V CI testing. - Revert "riscv: Allow use of reset drivers". - Revert "Revert "riscv: sifive: fu540: Add gpio-restart support"". - sysreset: syscon: - Don't assume default value for offset and mask property. - Support value property. - qemu: Add syscon reboot and poweroff support. - Fix SIFIVE debug serial dependency. - Fix linking error when building u-boot-spl with no SMP support. - AE350 use fdtdec_get_addr_size_auto_noparent to parse smc reg. - Make memory node available to SPL in hifive-unleashed-a00-u-boot.dtsi - SiFive fu540 avoid using hardcoded ram base and size.
| * ram: sifive: Avoid using hardcoded ram base and sizeBin Meng2020-07-241-15/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | At present the SiFive FU540 RAM driver uses hard-coded memory base address and size to initialize the DDR controller. This may not be true when this driver is used on another board based on FU540. Update the driver to read the memory information from DT and use that during the initialization. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Leo Liang <ycliang@andestech.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
| * riscv: dts: hifive-unleashed-a00: Make memory node available to SPLBin Meng2020-07-241-0/+4
| | | | | | | | | | | | | | | | Make memory node available to SPL in prepration to updates to SiFive DDR RAM driver to read memory information from DT. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
| * riscv: ae350: Use fdtdec_get_addr_size_auto_noparent to parse smc regRick Chen2020-07-241-1/+2
| | | | | | | | | | | | | | | | | | | | | | Use fdtdec_get_addr_size_auto_noparent to read the "reg" property instead of fdtdec_get_addr. This will increase the compatibility of dtb parsing. Signed-off-by: Rick Chen <rick@andestech.com> Acked-by: Leo Liang <ycliang@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Leo Liang <ycliang@andestech.com>
| * riscv: Fix linking error when building u-boot-spl with no SMP supportLeo Yu-Chi Liang2020-07-241-0/+2
| | | | | | | | | | | | | | | | | | | | Switch off SMP support when building u-boot-spl would cause linking error as follow: undefined reference to 'secondary hart relocate' and 'smp_call_function'. Add macro to wrap up proper code region that needs SMP configuration on. Signed-off by: Leo Liang <ycliang@andestech.com> Cc: rick@andestech.com Reviewed-by: Bin Meng <bin.meng@windriver.com>
| * serial: Fix SIFIVE debug serial dependencyMichal Simek2020-07-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The commit 4cc24aeaf420 ("serial: Add missing Kconfig dependencies for debug consoles") has added incorrect dependency for SIFIVE debug uart which should depend on SIFIVE driver instead of PL01x. Fixes: 4cc24aeaf420 ("serial: Add missing Kconfig dependencies for debug consoles") Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Leo Liang <ycliang@andestech.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
| * riscv: qemu: Add syscon reboot and poweroff supportBin Meng2020-07-241-0/+4
| | | | | | | | | | | | | | This adds syscon reboot and poweroff support to QEMU RISC-V. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
| * sysreset: syscon: Support value propertyBin Meng2020-07-241-5/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | Per the DT binding, <mask> and <value> property can have either one or both, and if <value> is missing, <mask> should be used, which is what current U-Boot sysreset_syscon driver supports. This adds support to the <value> property to the driver, and <mask> semantics is updated to really be a mask to the value if both exist. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
| * sysreset: syscon: Don't assume default value for offset and mask propertyBin Meng2020-07-241-2/+12
| | | | | | | | | | | | | | | | | | | | Per the DT binding, <offset> is a required property. Let's abort the probe if it is missing. For the <mask> property, current codes assume a default value of zero, which is not correct either. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
| * Revert "Revert "riscv: sifive: fu540: Add gpio-restart support""Bin Meng2020-07-241-0/+2
| | | | | | | | | | | | | | | | | | This reverts commit 23da3c682a84a2ad67a67287979dd4f5259ff607. Now the build failure of sifive_fu540_defconfig board has been fixed, revert this "revert patch". Signed-off-by: Bin Meng <bin.meng@windriver.com>
| * Revert "riscv: Allow use of reset drivers"Bin Meng2020-07-241-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 958a3f464c7f8ef7e10db9feb663e9e80445ce2f. A more appropriate change below is already in mainline. Commit fd31e4fd184f ("riscv: Do not build reset.c if SYSRESET is on") Revert this patch, so that U-Boot can be built successfully for SiFive Fu540 board. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Liang <ycliang@andestech.com>
| * azure: gitlab: travis: Update OpenSBI used for RISC-V testingBin Meng2020-07-243-12/+12
| | | | | | | | | | | | | | | | Change to use OpenSBI release v0.8 generic platform images for QEMU RISC-V CI testing for azure, gitlab and travis-ci. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * sifive: fu540: Enable SF distro bootcmdJagan Teki2020-07-241-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable SPI flash(SF) distro boot command in Sifive FU540. This distro boot will read the boot script at specific location at the flash and start sourcing the same. Included the SF device at the last of the target devices list since all the rest of the devices on the list have more possibility to boot the distribution due to the size of the SPI flash is concern. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
| * sifive: fu540: Add boot flash script offset, sizeJagan Teki2020-07-241-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | HiFive-Unleashed-A00 has SPI flash with 32MiB size. So, let's use the script offset at the end of 4K. This way it cannot overlap any offsets being used by software components in flash layout. So, SF distrocmd will pick the script at desired script address and run. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
| * sifive: fu540: Mark the default env as SPI flashJagan Teki2020-07-241-0/+1
| | | | | | | | | | | | | | | | | | | | Mark the default U-Boot environment as SPI flash since this is an on board flash device. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
| * env: Enable SPI flash env for SiFive FU540Jagan Teki2020-07-241-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPI flash device on HiFive Unleashed has 32MiB Size. This patch adds SPI flash environment after U-Boot proper partition with a size of 128KiB. SPI flash partition layout(32MiB): 0 - 34 : reserved for GPT header 35 - 39 : unused 40 - 2087 : loader1 (SPL, FSBL) 2088 - 10279 : loader2 (U-Boot proper, U-Boot) 10280 - 10535 : environment 10536 - 65494 : rootfs 65528 - 65536 : distro script Note: the loader1 must start from 40th sector even though there are 6 free sectors prior since 40th sector is nearest flash sector boundary.  Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
| * sifive: fu540: Add Booting from SPIJagan Teki2020-07-243-0/+57
| | | | | | | | | | | | | | | | Add booting from SPI for SiFive Unleashed board. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
| * sifive: fu540: Add runtime boot mode detectionJagan Teki2020-07-241-6/+19
| | | | | | | | | | | | | | | | | | Add support to detect boot mode at runtime for SiFive FU540 boards. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
| * riscv: sifive: fu540: Enable SiFive PWM driverPragnesh Patel2020-07-241-0/+2
| | | | | | | | | | | | | | | | This patch enables SiFive PWM driver for the SiFive Unleashed board. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
| * riscv: Make SiFive HiFive Unleashed board boot againBin Meng2020-07-243-10/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 40686c394e53 ("riscv: Clean up IPI initialization code") caused U-Boot failed to boot on SiFive HiFive Unleashed board. The codes inside arch_cpu_init_dm() may call U-Boot timer APIs before the call to riscv_init_ipi(). At that time the timer register base (e.g.: the SiFive CLINT device in this case) is unknown yet. It might be the name riscv_init_ipi() that misleads people to only consider it is related to IPI, but in fact the timer capability is provided by the same SiFive CLINT device that provides the IPI. Timer capability is needed for both UP and SMP. Considering that the original refactor does have benefits, that it makes the IPI code more similar to U-Boot initialization idioms. It also removes some quite ugly macros. Let's do the minimal revert instead of a complete revert, plus a fixes to arch_cpu_init_dm() to consider the SPL case. Fixes: 40686c394e53 ("riscv: Clean up IPI initialization code") Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Tested-by: Leo Liang <ycliang@andestech.com>
* | Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm"Tom Rini2020-07-24319-2506/+656
|/ | | | | | | | | | This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dmTom Rini2020-07-23319-656/+2506
|\ | | | | | | | | | | | | | | binman support for FIT new UCLASS_SOC patman switch 'test' command minor fdt fixes patman usability improvements
| * treewide: convert devfdt_get_addr() to dev_read_addr()Masahiro Yamada2020-07-20120-125/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
generated by cgit (git 2.34.1) at 2024-11-19 02:24:07 +0000