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| * | arm: mvebu: AXP: Add possiblity to configure PEX detection pulse widthStefan Roese2017-03-291-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tests have shown that on some boards the default width of the configuration pulse for the PEX link detection might lead to non-established PCIe links (link down). Especially under certain conditions (higher temperature) and with specific PCIe devices (in the case on the theadorable board its a Atheros PCIe WLAN device). To enable a board-specific detection pulse width this weak array "serdes_pex_pulse_width[4]" is introduced which can be overwritten if needed by a board-specific version. If the board code does not provide a non-weak version of this variable, the default value will be used. So nothing is changed from the current setup on the supported board. Many thanks to Adam from Marvell for all his insights here and his suggestion about testing with a changed detection pulse width. Signed-off-by: Stefan Roese <sr@denx.de> Suggested-by: Adam Shobash <adams@marvell.com> Cc: Adam Shobash <adams@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | arm64: a37xx: Remove DM_I2C_COMPAT from the board configKonstantin Porotchkin2017-03-292-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove DM_I2C_COMPAT from the board configurations for Armada 37xx platform boards for supressing the buid tim warning. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | arm64: a37xx: Disable DB configurations on ESPRESSOBin boardKonstantin Porotchkin2017-03-291-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bypass XHCI and AHCi board configuration flow on ESPRESSOBin community board. The community board does not have i2c expander and USB VBUS is always on, so the scan for AHCi and USB devices can be faster without unneded configurations. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | arm64: mvebu: Add default config for ESPRESSOBin boardKonstantin Porotchkin2017-03-291-0/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial default configuration for Marvell ESPRESSOBin community board based on Aramda-3720 SoC Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | arm64: dts: Add device tree for ESPRESSOBin boardKonstantin Porotchkin2017-03-292-0/+136
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initial DTS file for Marvell ESPRESSOBin comunity board based on Armada-3720 SoC. The Marvell ESPRESSOBin is a tiny board made by Globalscale and available on KickStarter site. It has dual core Armv8 Marvell SoC (Armada-3720) with 512MB/1GB/2GB DDR3 RAM, mini-PCIe 2.0 slot, single SATA-3 port, USB 2.0 and USB 3.0 interfaces, Gigabit Ethernet switch with 3 ports, micro-SD socket and two 46-pin GPIO connectors. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | mvebu: a37xx: Add init for ESPRESSBin Topaz switchKonstantin Porotchkin2017-03-291-0/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the board-specific network init function for ESPRESSOBin community board, setting the on-board Topaz switch port to forward mode and allow network connection through any of the available Etherenet ports. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | mvebu: neta: a37xx: Add fixed link support to neta driverKonstantin Porotchkin2017-03-291-27/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for fixed link to NETA driver. This feature requreed for proper support of SFP modules and onboard connected devices like Ethernet switches Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Terry Zhou <bjzhou@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | mvebu: neta: Add support for board init functionKonstantin Porotchkin2017-03-291-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add ability to use board-specific initialization flow to NETA driver (for instance Ethernet switch bring-up) Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | arm64: a37xx: Handle pin controls in early board initKonstantin Porotchkin2017-03-291-1/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the default pin control values in a board-specific function on early board init stage. This fix allows the NETA driver to work in RGMII mode until the full-featured pin control driver gets introduced. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | arm64: a37xx: dts: Add pin control nodes to DTKonstantin Porotchkin2017-03-291-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pin control nodes for North and South bridges to Armada-37xx DT Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | arm64: a37xx: Enable bubt command support on A3720-DBKonstantin Porotchkin2017-03-291-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable mvebu bubt command support on A3720 DB Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | arm64: a37xx: Enable Marvell ETH PHY supportKonstantin Porotchkin2017-03-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable support for Marvell Ethernet PHYs on A37xx platforms Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | arm64: mvebu: Rename the db-88f3720 to armada-37xx platformKonstantin Porotchkin2017-03-296-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modify the file names and deifinitions relater to Marvell db-77f3720 board support. Convert these names to more generic armada-37xx platform for future addition of more boards based on the same SoC family. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | mvebu: usb: xhci: Add VBUS regulator supply to the host driverKonstantin Porotchkin2017-03-293-1/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The USB device should linked to VBUS regulator through "vbus-supply" DTS property. This patch adds handling for "vbus-supply" property inside the USB device entry for turning on the VBUS regulator upon the host adapter probe. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * | arm64: mvebu: Add default configuraton for MACCHIATOBin boardKonstantin Porotchkin2017-03-291-0/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add default configuration for MACHHIATOBin community board based on Aramda-8040 SoC. Change-Id: Ic6b562065c0929ec338492452f765115c15a6188 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | arm64: mvebu: dts: Add DTS file for MACCHIATOBin boardRabeeh Khoury2017-03-292-0/+294
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added A8040 dts file for community board MACCHIATIBin. The patch includes the following features: AP - Serial console (connected to onboard FTDI usb to serial) CP0 - PCIe x4, SATA, I2C and 10G KR (connected to Marvell 3310 10G copper / SFP+ phy) CP1 - Boot SPI, USB3 host, 2xSATA, 10G KR (connected to Marvell 3310 10G copper / SFP+ phy), SGMII connected to onboard 1512 1Gbps copper phy, and additional SGMII connected to SFP (default 1Gbps can be configured to 2.5Gbps). Network interface naming - egiga0 - CP0 KR egiga1 - CP1 KR egiga2 - CP1 RJ45 1Gbps connector (recommended for TFTP boot) egiga3 - CP1 SFP default 1Gbps and can be modified to 2.5Gbps Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | mvebu: pcie: Add support for GPIO reset for PCIe deviceKonstantin Porotchkin2017-03-292-0/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for "marvell,reset-gpio" property to mvebu DW PCIe driver. This option is valid when CONFIG_DM_GPIO=y Change-Id: Ic17c500449050c2fbb700731f1a9ca8b83298986 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | arm64: mvebu: dts: Add i2c1 pin definitions to CPMKonstantin Porotchkin2017-03-291-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add i2c-1 pin mappings to CP0(master) DTSI file Change-Id: I0c6e6de8a557393f518f7df8e6daa6dfce1788b0 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | arm64: mvebu: gpio: Add GPIO nodes to A8K family devicesKonstantin Porotchkin2017-03-295-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add GPIO nodes to AP-806 and CP-110-master DTSI files. Change-Id: I05958698d460cb721b7d8683d34f74a5ea32532c Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | dtoc: make ScanTree recurse into subnodesPhilipp Tomsich2017-03-291-1/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, dtoc could only process the top-level nodes which led to device nodes in hierarchical trees to be ignored. E.g. the mmc0 node in the following example would be ignored, as only the soc node was processed: / { soc { mmc0 { /* ... */ }; }; }; This introduces a recursive helper method ScanNode, which is used by ScanTree to recursively parse the entire tree hierarchy. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | drivers: ti_qspi: use syscon to get the address ctrl_mod_mmap registerJean-Jacques Hiblot2017-03-291-5/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We used to get the address of the optionnal ctrl_mod_mmap register as the third memory range of the "reg" property. the linux driver moved to use a syscon instead. In order to keep the DTS as close as possible to that of linux, we move to using a syscon as well. If SYSCON is not supported, the driver reverts to the old way of getting the address from the 3rd memory range Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
| * | regmap: use fdt address translationJean-Jacques Hiblot2017-03-291-6/+8
| | | | | | | | | | | | | | | | | | | | | In the DTS, the addresses are defined relative to the parent bus. We need to translate them to get the address as seen by the CPU core. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
| * | dm: core: Fix Handling of global_data moving in SPLLokesh Vutla2017-03-291-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 2f11cd9121658 ("dm: core: Handle global_data moving in SPL") handles relocation of GD in SPL if spl_init() is called before board_init_r(). So, uclass_root.next need not be initialized always and accessing uclass_root.next->prev gives an abort. Update the uclass_root only if it is available. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | mmc: xenon_sdhci: Add missing host->max_clk to Xenon SDHCI driverStefan Roese2017-03-291-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Xenon SDHCI driver just missed the integration of this patch: git ID 6d0e34bf mmc: sdhci: Distinguish between base clock and maximum peripheral frequency With this patch applied, the SDHCI subsystem complains now with this warning while probing: sdhci_setup_cfg: Hardware doesn't specify base clock frequency This patch fixes this issue, by providing the missing host->max_clk variable to the SDHCI subsystem. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Hu Ziji <huziji@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Konstantin Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Cc: Jaehoon Chung <jh80.chung@samsung.com>
| * | mmc: drop unnecessary send_status requestXu Ziyuan2017-03-291-4/+0
| | | | | | | | | | | | | | | | | | | | | It's redundant to send cmd13 after cmd9 whose response is not R1b. The card devices will not be busy w/ cmd9. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
| * | mmc: sdhci: only flush cache for data commandKevin Liu2017-03-291-2/+4
| | | | | | | | | | | | | | | | | | No need to flush cache for command without data. Signed-off-by: Kevin Liu <kevinliu@asrmicro.com>
| * | mmc: tangier: Add Intel Tangier eMMC/SDHCI driverFelipe Balbi2017-03-293-0/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds Intel Tangier eMMC/SDHCI driver. Intel Tangier SoC contains a hybrid of PCI and non-PCI devices. SDHCI controller is one of the devices which are *not* on a PCI and, hence, cannot be enumerated by standard PCI means. This driver, allows for SDHCI controller on Tangier SoC to work in U-Boot. Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | mmc: pci: Add CONFIG_MMC_PCIFelipe Balbi2017-03-2910-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We don't want pci_mmc to compile every time x86 compiles, only when there's a platform that needs it. For that reason, we're adding a new CONFIG_MMC_PCI which platforms can choose to enable. Suggested-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* | | Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2017-04-0442-133/+691
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| * | | pcie-layerscape: Fixup iommu-map property of pci nodeBharat Bhushan2017-03-281-0/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixup iommu-map property on pci node to have a valid mapping of requester-id to stream-id. The requester-id to stream-id mapping is based on PCI-LUT table initialization. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | pcie-layerscape: Initialize pci-lut for NXP chasis-2 socsBharat Bhushan2017-03-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Layerscape Chasis-2 also uses same PCIe controller as Chasis-3 and have similar PCI-Lut. Signed-off-by: Bharat Bhushan <bharat.bhushan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: fsl-lsch2: Use Chassis-2 streamid definition for ls1012aBharat Bhushan2017-03-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1012A is Chassis-2 type SOC and shares same streamid definition. This patch adds using streamids for ls1012a Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: fsl-lsch2: Use Chassis-2 streamid definition for ls1046aBharat Bhushan2017-03-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1046A is Chassis-2 type SOC and shares same streamid definition, this patch adds using streamids for LS1046A. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | arvm8: pcie-layerscape: Define stream-ids for Layerscape Chassis-2Bharat Bhushan2017-03-282-0/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Layerscape Chassis-2 have PCIe device, some platform devices and DPAA1 devices which will use stream-ids for iommu level isolation as they are behind SMMU. This patch defines the stream-ids for Chassis-2 devices. DPAA1 is reserved for future use. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: fsl-lsch3: Rewrite comment for stream IDsBharat Bhushan2017-03-281-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS2080a, LS1088a and LS2088a SOCs are based on Chassis-3 and shared same stream-id partitioning. This patch rewords the definition to support all these SOCs. Also have changes in description about iommu-map property updates in PCI node. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: fsl-lsch3: rename ls2080a_stream_id.h to stream_id_lsch3.hBharat Bhushan2017-03-282-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The stream ID allocation for Chasis 3.0 devices can be shared among LS1088, LS2088 and LS2080. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | fsl-layerscape/ls104xardb: enable PPA support for eMMC/SD and NAND bootHou Zhiqiang2017-03-284-0/+4
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: Kconfig: fsl-ppa: support load PPA from eMMC/SD and NAND FlashHou Zhiqiang2017-03-281-0/+15
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | fsl: PPA: add support PPA image loading from NAND and SDHou Zhiqiang2017-03-281-1/+142
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | mtd: nand: remove nand size print from nand_init functionHou Zhiqiang2017-03-283-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add nand_size() function to move the nand size print into initr_nand(). Remove nand size print from nand_init() to allow other function to call nand_init() without printing nand size. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | mtd: nand: add initialization flagHou Zhiqiang2017-03-281-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initialization flag to avoid initializing NAND Flash multiple times, otherwise it will calculate a wrong total size. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8/fsl-layerscape: fdt: Skip checking USB clock on LS1012AYingxi Yu2017-03-281-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USB requires 100MHz clock. On LS1012A, a dedicated 100MHz is provided instead of SYSCLK (125MHz). Skipping checking SYSCLK for FDT fixup. Signed-off-by: Yingxi Yu <yingxi.yu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: ls1043a/ls1046aqds: fix the offsets of MTD partitions on NOR flashWenbin Song2017-03-282-12/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the offsets of MTD partitions on Nor flash on ls1043ardb, ls1043aqds and ls1046aqds boards. Delete the rcw, uboot env and fman partitions. Add user partitions for general usage. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | board: freescale: ls2080a/ls2088a: Enable PPASantan Kumar2017-03-285-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable PPA on LS2080A, LS2088A boards: -LS2080ARDB, LS2080AQDS -LS2088ARDB, LS2088AQDS Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | pci: layerscape: Fixup device tree node for ls2088aHou Zhiqiang2017-03-281-11/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS2088A and its variants have different PCIe node than LS2080A. The compatible string is updated accordingly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | pci: layerscape: add LS2088A series SoC pcie supportHou Zhiqiang2017-03-283-0/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | tools: plbimage support generate rcw fileyuan linyu2017-03-281-21/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | some system will not generate pbl format u-boot, but require rcw. Signed-off-by: yuan linyu <Linyu.Yuan@alcatel-sbell.com.cn> Reviewed-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: fsl-lsch3: Conditionally apply workaround for erratum a0009203Ashish kumar2017-03-282-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This i2c errata only applies to LS2080A and its variants, namely LS2080A, LS2085A and LS2088A. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: dts: fsl-ls1012a: Change number of CS in SPI nodeSuresh Gupta2017-03-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1012A has only one chip select for QSPI flash. Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | spi: fsl_qspi: Add support for single chip selectSuresh Gupta2017-03-281-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SOC’s like LS1012A has only one chip select signal for QSPI flash. Avoid scanning other flash. Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
generated by cgit (git 2.34.1) at 2024-11-19 03:05:06 +0000