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* Prepare v2020.04Tom Rini2020-04-131-1/+1
| | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xxTom Rini2020-04-121-6/+7
|\ | | | | | | | | - Fixes DDR initialization failure on PowerPC boards like P3041DS, P4080DS
| * Revert "mpc85xx: ddr: Always start DDR RAM in Self Refresh mode"Biwen Li2020-04-101-6/+7
| | | | | | | | | | | | | | | | | | This reverts commit 2a5d5d27edfbdb0e02a7fcf05569f92c02ae44ee. The commit breaks uboot boot (hang in ddr init) on many PowerPC boards like P3041DS, P4080DS Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* | Merge tag 'dm-pull9apr20' of git://git.denx.de/u-boot-dmTom Rini2020-04-101-7/+11
|\ \ | | | | | | | | | Fixes segfault in 'dm drivers' command
| * | dm: dump.c: Refactor dm_dump_drivers printsOvidiu Panait2020-04-091-7/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor the printing sequence in dm_dump_drivers to make it more clear. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Cc: Sean Anderson <seanga2@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | dm: dump.c: Fix segfault when entry->of_match is NULLOvidiu Panait2020-04-091-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, dm drivers command produces a segfault: => dm drivers Driver Compatible -------------------------------- Segmentation fault (core dumped) This is caused by a NULL pointer dereference of entry->of_match. Add a check to prevent this. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Cc: Sean Anderson <seanga2@gmail.com> Cc: Simon Glass <sjg@chromium.org>
* | | Merge tag 'mips-fixes-for-2020.04' of git://git.denx.de/u-boot-mipsTom Rini2020-04-0910-69/+114
|\ \ \ | |_|/ |/| | | | | | | | | | | - doc: fix code examples in qemu-mips.rst - mips: vcoreiii: fix memtest and cache coherency issues - cmd/go: fix cache coherency issues on MIPS
| * | mips: cmd: go: Flush cache before jumping to app/imageStefan Roese2020-04-092-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It has been noticed on MT7628/88 platforms, that booting the RAM image does not work reliably. Sometimes it works and sometimes not. Debugging showed that this "might" be a cache related issue as very strange errors occurred (e.g. output corrupted etc). This patch adds a cache flush for the complete SDRAM area to the go cmd before jumping to the entry point for the MIPS architecture. The complete area is flushed as we don't know at this point, how big the area of the "application" really is. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Tested-by: Mauro Condarelli <mc5686@mclink.it> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Mauro Condarelli <mc5686@mclink.it> Cc: Weijie Gao <weijie.gao@mediatek.com>
| * | mips: vcoreiii: Fix cache coherency issuesLars Povlsen2020-04-094-18/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes an stability issue seen on some vcoreiii targets, which was root caused to a cache inconsistency situation. The inconsistency was caused by having kuseg pointing to NOR area but used as a stack/gd/heap area during initialization, while only relatively late remapping the RAM area into kuseg position. The fix is to initialize the DDR right after the TLB setup, and then remapping it into position before gd/stack/heap usage. Reported-by: Ramin Seyed-Moussavi <ramin.moussavi@yacoub.de> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
| * | mips: vcoreiii: Ajust CONFIG_SYS_MEMTEST_ENDLars Povlsen2020-04-091-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch ajust CONFIG_SYS_MEMTEST_END for vcoreiii-based systems to avoid overwriting the relocated u-boot. The former setting was too agressive with networking etc. enabled on some platforms. Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
| * | doc: board: qemu-mips.rst: fix code examplesHeinrich Schuchardt2020-04-091-48/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Code sections should be syntax highlighted as bash. Comment lines in code should start with a hash sign ('#') but code lines should not. Most commands can be executed as normal users. Prepend those commands requiring elevated authorization with 'sudo'. dd does not have a parameter cout. sfdisk does not have a -C parameter on Debian Buster. Provide the necessary input to sfdisk. Creating a partition of length zero makes no sense. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * | MIPS: allow override of get_tbclk()Alex Nemirovsky2020-04-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Allow SoC or board layers with reconfigurable cpu clocks capabilties to do implementation specific lookups and service get_tbclk() requests. Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
| * | MIPS: allow override of flush_dcache_range()Alex Nemirovsky2020-04-091-1/+1
| |/ | | | | | | | | | | | | Useful in custom HW designs which have a need to flush dcache range in a completely non standard way. Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
* | usb: Keep async schedule running only across mass storage xfersMarek Vasut2020-04-096-14/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than keeping the asynchronous schedule running always, keep it running only across USB mass storage transfers for now, as it seems that keeping it running all the time interferes with certain control transfers during device enumeration. Note that running the async schedule all the time should not be an issue, especially on EHCI HCD, as that one implements most of the transfers using async schedule. Note that we have usb_disable_asynch(), which however is utterly broken. The usb_disable_asynch() blocks the USB core from doing async transfers by setting a global flag. The async schedule should however be disabled per USB controller. Moreover, setting a global flag does not prevent the controller from using the async schedule, which e.g. the EHCI HCD does. This patch implements additional callback to the controller, which permits it to lock the async schedule and keep it running across multiple transfers. Once the schedule is unlocked, it must also be disabled. This thus prevents the async schedule from running outside of the USB mass storage transfers. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Lukasz Majewski <lukma@denx.de> Cc: Tom Rini <trini@konsulko.com> Tested-by: Tom Rini <trini@konsulko.com> [omap3_beagle, previously failing]
* | imx: Fix imx8m FIT script issueYe Li2020-04-091-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The FIT config node has reversed ATF and u-boot: ATF is set to 'firmware' but u-boot is set to 'loadables'. This script can work previously because spl fit driver wrongly appends fdt to all loadable images. With the issue fixed in commit 9d15d1d1c24f ("Revert "common: spl_fit: Default to IH_OS_U_BOOT if FIT_IMAGE_TINY enabled"") the u-boot in 'loadables' does not have fdt appended and fails to work. So correct the script by moving u-boot to 'firmware' and ATF to 'loadables'. Signed-off-by: Ye Li <ye.li@nxp.com> Reported-by: Matt Porter <mporter@konsulko.com> Tested-by: Matt Porter <mporter@konsulko.com>
* | cmd: Add test and fix bugs for dm driversSean Anderson2020-04-093-3/+21
|/ | | | | | | | | | Add a test for the dm drivers command. Also fix a null pointer dereference revealed by said test. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge tag 'u-boot-imx-20200408' of ↵Tom Rini2020-04-084-61/+84
|\ | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx Fixes for 2020.04 ----------------- - mx7dsabre: Fix ramdisk_addr* for distro boot - Toradex boards Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/671988124
| * mx7dsabre: Fix ramdisk_addr* for distro bootJan Kiszka2020-04-071-2/+2
| | | | | | | | | | | | Overlapped with fdt_addr*, thus corrupted the latter when using both. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
| * ARM: dts: imx8qxp-colibri: dm-pre-proper for pd_dma nodesIgor Opaniuk2020-04-071-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | pd_dma_* nodes should be accessible during pre-relocation stage of U-Boot proper for properly handling power domains. This fixes the issue with permanent failing of invocation of power_domain_get_by_index() in the common code of DM power domain uclass (drivers/power/domain/power-domain-uclass.c). Fixes: f0cc4eae9a ("core: device: use dev_power_domain_on") Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
| * ARM: dts: imx8qm-apalis: dm-pre-proper for pd_dma nodesIgor Opaniuk2020-04-071-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | pd_dma_* nodes should be accessible during pre-relocation stage of U-Boot proper for properly handling power domains. This fixes the issue with permanent failing of invocation of power_domain_get_by_index() in the common code of DM power domain uclass (drivers/power/domain/power-domain-uclass.c). Fixes: f0cc4eae9a ("core: device: use dev_power_domain_on") Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
| * ARM: dts: imx8qxp-colibri: replace dm-spl with dm-pre-properIgor Opaniuk2020-04-071-28/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For non-SPL/TPL setups dm-spl, dm-tpl, dm-pre-proper, dm-pre-reloc are handled equally, forcing the nodes with these properties to be accessible and device being probed before pre-relocation of U-Boot proper (drivers/core/util.c): bool ofnode_pre_reloc(ofnode node) { /* for SPL and TPL the remaining nodes after the fdtgrep 1st pass * had property dm-pre-reloc or u-boot,dm-spl/tpl. * They are removed in final dtb (fdtgrep 2nd pass) */ return true; if (ofnode_read_bool(node, "u-boot,dm-pre-reloc")) return true; if (ofnode_read_bool(node, "u-boot,dm-pre-proper")) return true; /* * In regular builds individual spl and tpl handling both * count as handled pre-relocation for later second init. */ if (ofnode_read_bool(node, "u-boot,dm-spl") || ofnode_read_bool(node, "u-boot,dm-tpl")) return true; return false; } Howewer, to avoid confusion in future, replace dm-spl `%s/dm-spl/dm-pre-proper/g` properties to dm-pre-proper to explicitly state that they are handled during pre-relocation stage of U-Boot proper. Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
| * ARM: dts: imx8qm-apalis: replace dm-spl with dm-pre-properIgor Opaniuk2020-04-071-31/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For non-SPL/TPL setups dm-spl, dm-tpl, dm-pre-proper, dm-pre-reloc are handled equally, forcing the nodes with these properties to be accessible and device being probed before pre-relocation of U-Boot proper (drivers/core/util.c): bool ofnode_pre_reloc(ofnode node) { /* for SPL and TPL the remaining nodes after the fdtgrep 1st pass * had property dm-pre-reloc or u-boot,dm-spl/tpl. * They are removed in final dtb (fdtgrep 2nd pass) */ return true; if (ofnode_read_bool(node, "u-boot,dm-pre-reloc")) return true; if (ofnode_read_bool(node, "u-boot,dm-pre-proper")) return true; /* * In regular builds individual spl and tpl handling both * count as handled pre-relocation for later second init. */ if (ofnode_read_bool(node, "u-boot,dm-spl") || ofnode_read_bool(node, "u-boot,dm-tpl")) return true; return false; } Howewer, to avoid confusion in future, replace dm-spl `%s/dm-spl/dm-pre-proper/g` properties to dm-pre-proper to explicitly state that they are handled during pre-relocation stage of U-Boot proper. Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
| * colibri_imx6: set gpr1 ENET_CLK_SELIgor Opaniuk2020-04-071-0/+3
|/ | | | | | | | This fixes the issue when PHY auto negotiation never completes. Fixes: 431cd76dd8("colibri_imx6: migrate to DM_ETH") Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
* Prepare v2020.04-rc5Tom Rini2020-04-061-1/+1
| | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* clk: socfpga: Read the clock parent's register base in probe functionChee Hong Ang2020-04-051-22/+18
| | | | | | | | | | | | | This commit (82de42fa14682d408da935adfb0f935354c5008f) calls child's ofdata_to_platdata() method before the parent is probed in dm core. This has caused the driver no longer able to get the correct parent clock's register base in the ofdata_to_platdata() method because the parent clocks will only be probed after the child's ofdata_to_platdata(). To resolve this, the clock parent's register base will only be retrieved by the child in probe() method instead of ofdata_to_platdata(). Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* ARM: dts: stm32: Temporarily drop cd-gpios from AV96 DTMarek Vasut2020-04-051-1/+0
| | | | | | | | | | | | | | | The card-detect GPIO and any other GPIO access currently doesn't work in U-Boot SPL on any STM32 platform and crashes the SPL. To work around this problem on AV96 right before release, remove the cd-gpios from DT. This patch must be reverted right after release, once the proper fix for the GPIO driver, "gpio: stm32: support gpio ops in SPL", is applied. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Tom Rini <trini@konsulko.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
* Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2020-04-041-0/+4
|\ | | | | | | - net: sh_eth: Init the hardware before PHY access
| * net: sh_eth: Init the hardware before PHY accessMarek Vasut2020-04-041-0/+4
| | | | | | | | | | | | | | | | | | | | To access the PHY, the MAC registers must be initialized. Call the init function in probe() to make it so, otherwise the PHY ID readout returns all zeroes. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86Tom Rini2020-04-044-55/+124
|\ \ | | | | | | | | | | | | | | | - verdin-imx8mm board reST documentation update - Intel Edison board ACPI table I2C/USB minor updates - Fix a regression of ns16550 serial driver that breaks Intel Edison
| * | serial: ns16550: Fix ordering of getting base addressBin Meng2020-04-041-17/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
| * | x86: acpi: Describe USB 3 host controller found on Intel TangierAndy Shevchenko2020-04-041-0/+47
| | | | | | | | | | | | | | | | | | | | | | | | USB 3 host controller may be described in ACPI to allow users alter the properties or other features. Describe it for Intel Tangier SoC. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: acpi: Add I²C timings to Intel Merrifield platformAndy Shevchenko2020-04-041-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | There is established way to provide I²C timings, or actually counters, to the OS via ACPI. Fill them for Intel Merrifield platform. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | doc: board: verdin-imx8mm: use mainline TF-AIgor Opaniuk2020-04-041-20/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Update build steps where mainline Trusted Firmware A is used. 2. Fix BL31_BASE to the proper one according to the SoC reference manual. Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: acpi: Refactor XSDT handling in acpi_add_table()Andy Shevchenko2020-04-041-18/+19
| |/ | | | | | | | | | | | | | | | | | | | | There is no need to have an assignment to NULL for XSDT pointer. Therefore, no need to assign it when rsdt_address is not set. Because of above changes we may decrease indentation level as well. While here, drop unnecessary parentheses. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-tegraTom Rini2020-04-0341-1420/+757
|\ \ | | | | | | | | | | | | | | | - Add support for Jetson Nano, plus miscellaneous other fixes found during Nano bringup. - Add Igor's update_uboot wrapper patches.
| * | ARM: tegra: Add NVIDIA Jetson Nano Developer Kit supportTom Warren2020-04-0210-1/+495
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Jetson Nano Developer Kit is a Tegra X1-based development board. It is similar to Jetson TX1 but it is not pin compatible. It features 4GB of LPDDR4, a SPI NOR flash for early boot firmware and an SD card slot used for storage. HDMI 2.0 or DP 1.2 are available for display, four USB ports (3 USB 2.0 and 1 USB 3.0) can be used to attach a variety of peripherals and a PCI Ethernet controller provides onboard network connectivity. NVMe support has also been added. Env save is at the end of QSPI (4MB-8K). A 40-pin header on the board can be used to extend the capabilities and exposed interfaces of the Jetson Nano. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Tested-by: Peter Robinson <pbrobinson@gmail.com>
| * | mtd: spi: Add Macronix MX25U3235F deviceTom Warren2020-04-021-0/+1
| | | | | | | | | | | | | | | | | | | | | Add Macronix MX25U3235F flash device description. This is a 4MiB part. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | t210: Adjust ramdisk_addr_r/fdt_addr_r to allow for large kernelsTom Warren2020-04-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The L4T kernel is 32MB+, and can overwrite the ramdisk/fdt loaded from extlinux.conf. Adjust the load addresses to fix this for now. Using the calculated_env addresses table from T186 U-Boot is a better fix, but it isn't working correctly on T210 U-Boot right now, so this will do until I can fix it. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | qspi: t210: Use dev_read calls to get FDT data like base, freqTom Warren2020-04-021-8/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This Tegra QSPI driver hadn't been brought up to date with how DM drivers are fetching data from the FDT now, and was pulling in bogus data for base, max freq, etc. Fixed ofdata_to_platdata to work the same way it does in the tegra114 SPI driver, using dev_read_ functions. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | qspi: t210: Fix QSPI clock and tap delaysTom Warren2020-04-021-9/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When claim_bus was setting the clock, it reset the QSPI controller, which wipes out any tap delays set by previous bootloaders (nvtboot, CBoot for example on Nano). Instead of doing that in claim_bus, which gets called a lot, moved clock setting to probe(), and set tap delays there, too. Also updated clock to 80MHz to match CBoot. Now QSPI env save works reliably again. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | qspi: t210: Fix claim_bus's use of the wrong bus/deviceTom Warren2020-04-021-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | claim_bus() is passed a udevice *dev, which is the bus device's parent. In this driver, claim_bus assumed it was the bus, which caused the 'priv' info pointer to be wrong, and periph_id was incorrect. This in turn caused the periph clock call to assign the wrong clock (PLLM instead of PLLP0), which caused a kernel warning. I only saw the 'bad' periph_id when enabling DEBUG due to an assert. Not sure how QSPI was working w/this errant clock, but it was moot as QSPI wasn't active unless you probed it, and that wasn't happening until I posted a patch to enable env save to QSPI for Nano (coming soon). Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | mmc: t210: Fix 'bad' SD-card clock when doing 400KHz card detectTom Warren2020-04-022-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the HW team, for some reason the normal clock select code picks what appears to be a perfectly valid 375KHz SD card clock, based on the CAR clock source and SDMMC1 controller register settings (CAR = 408MHz PLLP0 divided by 68 for 6MHz, then a SD Clock Control register divisor of 16 = 375KHz). But the resulting SD card clock, as measured by the HW team, is 700KHz, which is out-of-spec. So the WAR is to use the values given in the TRM PLLP table to generate a 400KHz SD-clock (CAR clock of 24.7MHz, SD Clock Control divisor of 62) only for SDMMC1 on T210 when the requested clock is <= 400KHz. Note that as far as I can tell, the other requests for clocks in the Tegra MMC driver result in valid SD clocks. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | mmc: t210: Add autocal and tap/trim updates for SDMMC1/3Tom Warren2020-04-022-12/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per the T210 TRM, when running at 3.3v, the SDMMC1 tap/trim and autocal values need to be set to condition the signals correctly before talking to the SD-card. This is the same as what's being done in CBoot, but it gets reset when the SDMMC1 HW is soft-reset during SD driver init, so needs to be repeated here. Also set autocal and tap/trim for SDMMC3, although no T210 boards use it for SD-card at this time. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | tegra: Enable CONFIG_BOOTP_PREFER_SERVERIP for all Jetson boardsTom Warren2020-04-026-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | This allows the user to set $serverip in the environment before executing a DHCP request. If they do, U-Boot will use that IP rather than using the IP in the DHCP response. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: p2771-0000: enable PIE relocationVishruth2020-04-022-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot is configured to build as position independent executable. Enable relocation of RELA section required to work with different load addresses. Signed-off-by: Vishruth <vishruthj@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Peter Robinson <probinson@gmail.com>
| * | i2c: t210: Add VI_I2C clock source supportTom Warren2020-04-021-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Fix VI_I2C clock source type. Will be needed by VI_I2C driver. Also added use of INTERNAL_ID macro in two places, needed to keep the id returned to 8 bits. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | t210: pinmux: Remove pinmux/GPIO init from T210 boardsTom Warren2020-04-0210-1339/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T210 CBoot is now doing the full pinmux and GPIO init, based on the DTB tables. Remove pinmux/GPIO init tables & code from all T210-based builds below: p2371-2180 aka TX1 p2371-0000 e2220-1170 p2571 Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
| * | t210: do not enable PLLE and UPHY PLL HW PWRSEQJC Kuo2020-04-026-44/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit removes the programming sequence that enables PLLE and UPHY PLL hardware power sequencers. Per TRM, boot software should enable PLLE and UPHY PLLs in software controlled power-on state and should power down PLL before jumping into kernel or the next stage boot software. Adds call to board_cleanup_before_linux to facilitate this. Signed-off-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: p2371-2180: add I2C nodes to DTStephen Warren2020-04-021-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | This adds to the DT the I2C controllers that connect to the board ID EEPROM, etc. With this change, you can now probe all I2C devices on a TX1 board. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
| * | colibri_t30: add update_uboot wrapperIgor Opaniuk2020-04-021-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add universal update_uboot wrapper that helps to update U-Boot image on internal storage. Create an proper tegra image: $ cbootimage -s tegra30 colibri_t30.img.cfg colibri_t30.img Flash in U-boot shell: > tftpboot ${loadaddr} ${board_name}/${board_name}.img > run update_uboot Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
generated by cgit (git 2.34.1) at 2024-10-06 19:19:16 +0000