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* arm: Re-sync ARCH_MX5 / MX51 / MX53 CONFIG optionsTom Rini2017-04-3017-65/+51
| | | | | | | A few boards had not been fully re-synced with CONFIG_ARCH_MX5 / CONFIG_MX51 / CONFIG_MX53 being in Kconfig. Do so now. Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge tag 'xilinx-fixes-for-v2017.05' of git://www.denx.de/git/u-boot-microblazeTom Rini2017-04-272-1/+1
|\ | | | | | | | | | | | | Xilinx fixes for v2017.05 - Fix usbotg on Miami board - Cleanup zc1751 defconfig
| * arm64: zynqmp: Sync defconfig with KconfigMichal Simek2017-04-271-1/+0
| | | | | | | | | | | | | | Remove option which depends on MMC controller which is disabled for dc2. Savedefconfig is removing it because of new dependencies. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * zynq-topic-miami.dts: Add usbotg0 alias to make USB actually workMike Looijmans2017-04-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Fixes the following problem: zynq-uboot> run dfu_ram Setting bus to 1 g_dnl_register: failed!, error: -19 The cause appears to be that the USB framework is looking for a usbotg aliases, so add the alias to point to our USB device. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ext4: Fix comparision of unsigned expression with < 0Lokesh Vutla2017-04-272-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In file ext4fs.c funtion ext4fs_read_file() compares an unsigned expression with < 0 like below lbaint_t blknr; blknr = read_allocated_block(&(node->inode), i); if (blknr < 0) return -1; blknr is of type ulong/uint64_t. read_allocated_block() returns long int. So comparing blknr with < 0 will always be false. Instead declare blknr as long int. Similarly ext4/dev.c does a similar comparison. Drop the redundant comparison. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | MAINTAINERS: Update for Keystone2 secure devicesLokesh Vutla2017-04-271-0/+3
| | | | | | | | | | | | | | | | | | | | Update Keystone2 secure device configs under "TI SYSTEM SECURITY". Without this buildman keeps complaining about the status of these boards. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Andrew F. Davis <afd@ti.com>
* | arm/lib/bootm.c: keep ARM v7M in thumb mode during boot_jump_linux()Patrice Chotard2017-04-271-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On ARM v7M, the processor will return to ARM mode when executing a blx instruction with bit 0 of the address == 0. Always set it to 1 to stay in thumb mode. Tested on STM32f746-disco board Similar commit: f99993c10882f7dc8ec35993d5febe59aac01e6a Author: Matt Porter <mporter@konsulko.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | ARM: omap2+: rename config to ARCH_OMAP2PLUS and consolidate KconfigMasahiro Yamada2017-04-2787-232/+298
| | | | | | | | | | | | | | | | | | | | | | | | In Linux, CONFIG_ARCH_OMAP2PLUS is used for OMAP2 or later SoCs. Rename CONFIG_ARCH_OMAP2 to CONFIG_ARCH_OMAP2PLUS to follow this naming. Move the OMAP2+ board/SoC choice down to mach-omap2/Kconfig to slim down the arch/arm/Kconfig level. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | add Kconfig for fsuuid commandJosua Mayer2017-04-271-0/+5
| | | | | | | | | | | | | | | | CONFIG_CMD_FS_UUID was neither whitelisted, nor was it declared in Kconfig. Now it can be enabled in .config and defconfig as expected. Signed-off-by: Josua Mayer <josua.mayer97@gmail.com>
* | Kconfig: Enable FIT support by default for TI platformsAndrew F. Davis2017-04-2737-36/+2
| | | | | | | | | | | | | | | | Almost all TI defconfigs enable this already, add this as a default and remove the explicit assignment. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | travisci: Add support for ARCAlexey Brodkin2017-04-271-0/+8
| | | | | | | | | | | | | | | | | | | | | | Finally adding support for ARC boards in TravisCI. To build for ARC boards we need to install Synopsys prebuilt toolchain which we do here. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | board: dra71: Fix selection of OPPsLokesh Vutla2017-04-271-6/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per the DM[1] Dated June 2016–Revised February 2017, Table 5-3, DRA71 supports the following OPPs for various voltage domains: VDD_MPU: OPP_NOM VDD_CORE: OPP_NOM VDD_GPU: OPP_NOM VDD_DSPEVE: OPP_NOM, OPP_HIGH VDD_IVA: OPP_NOM, OPP_HIGH This patch add support for selection of the above OPPs instead of using OPP_NOM for all voltage domains. [1] http://www.ti.com/lit/ds/symlink/dra718.pdf Reported-by: Vishal Mahaveer <vishalm@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | pinctrl: Kconfig: sort pinctrl config options to prevent future clutterPhilipp Tomsich2017-04-2723-105/+117
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This originally started out as "pinctrl: Kconfig: reorder to keep Rockchip options together" and tried to keep the Rockchip-related config options together. However, we now rewrite all chip-specific driver selections to start with CONFIG_PINCTRL_ (with the inadvertent changes to related Makefiles) and sort those alphabetically. And as this already means touching most of the file, we also reformat the help text to not exceed 80 characters (but make full use of those 80 characters). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: mkimage: remove (left-over) assignment w/o effect [coverity]Philipp Tomsich2017-04-271-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | An assignment (of a value to itself) was left over (after removing and addition from the line) from moving the common padding code into rkcommon_vrec_header. This change removes this to avoid a spurious warning in static code analysis (i.e. Coverity). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reported-by: Coverity (CID: 161418) Reviewed-by: Tom Rini <trini@konsulko.com>
* | clean-up: Remove uselsess mentions of CONFIG_COMMAND_HISTORYAlexey Brodkin2017-04-279-10/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These were reminders that somehow slipped through the cracks or were erroneously introduced after previous clean-ups. Getting rid of then once again. Hopefully for good now :) Where missing and appropriate replace with CONFIG_CMDLINE_EDITING which really enables shell history as of now. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Peter Griffin <peter.griffin@linaro.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Steve Rae <steve.rae@raedomain.com> Cc: Jon Mason <jon.mason@broadcom.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* | arm: Warn that starting with v2018.01 gcc-6 or later is requiredTom Rini2017-04-271-1/+11
| | | | | | | | | | | | | | | | | | | | There are more and more cases where if we do not use gcc-6.0 or later we run into problems where our binaries are too large for the targets. Given the prevalence of gcc-6.0 or later toolchains at this point in time, we give notice now that starting with v2018.01 we will require gcc-6 (or later) for ARM. Signed-off-by: Tom Rini <trini@konsulko.com>
* | dm: sandbox: pwm: Add a basic pwm testSimon Glass2017-04-279-0/+131
| | | | | | | | | | | | | | | | | | | | | | Unfortunately a test for the PWM uclass was not included when it was submitted. This was noticed when trying to add more functionality: http://patchwork.ozlabs.org/patch/748172/ Add a simple test to get us started. Signed-off-by: Simon Glass <sjg@chromium.org>
* | configs: keystone2: Standardise U-boot promptLokesh Vutla2017-04-275-5/+0
| | | | | | | | | | | | | | | | Standardise U-Boot prompt on all keystone2 platforms instead of platform specific prompt. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | OMAP3: Correct name of omap34xx_gpios when using DM_GPIOAdam Ford2017-04-271-1/+1
| | | | | | | | | | | | | | | | The name of the gpio bank under DM_GPIO appear to be a copy-paste error. This changes the name of the gpio bank from am33xx_gpios to omap34xx_gpios. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | omap3: i2c: correct registerAdam Ford2017-04-271-1/+13
|/ | | | | | | | | The register names and offset were not correct as per the TRM for OMAP3530 and OMAP3630. Correct the naing and offsets per the documentation Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* Merge git://git.denx.de/u-boot-sunxiTom Rini2017-04-2599-404/+1793
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| * sunxi: fix the default value of CONS_INDEX on non-A23/A33 SUN8IIcenowy Zheng2017-04-251-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only A23/A33 in SUN8I want a default value of CONS_INDEX of 5, for other chips the default value is 1 like other Allwinner SoCs. Fix this default value. The original wrong value has lead to wrong console on H3 Orange Pi boards. Fixes: 7095f8641863 ("sunxi: Convert CONS_INDEX to Kconfig") Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: Fix arm64 fdtfile variableAndreas Färber2017-04-241-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently $fdtfile is constructed from CONFIG_DEFAULT_TREE, containing the filename. However on arm64 that file is located in an allwinner subdirectory. To avoid the need for users/distros symlinking the .dtb files, prepend the vendor directory for ARM64. This aligns Pine64 with other boards such as Raspberry Pi 3. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * sunxi: add support for Lichee Pi ZeroIcenowy Zheng2017-04-214-0/+102
| | | | | | | | | | | | | | | | | | | | | | | | Lichee Pi Zero is a development board with a V3s SoC, which features 64MiB DRAM co-packaged within the SoC, a TF slot, a SPI NOR slot (not soldered in production batch), a 40-pin RGB LCD connector and some extra pins available as 2.54mm pins or stamp holes. Add support for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: add DTSI file for V3sIcenowy Zheng2017-04-213-0/+469
| | | | | | | | | | | | | | | | | | | | | | As we have now V3s support in board code, the V3s DTSI file should also be added. Add also some CCU include headers to satisfy the DTSI file. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: add basic V3s supportIcenowy Zheng2017-04-216-2/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Basic U-Boot support is now present for V3s. Some memory addresses are changed specially for V3s, as the original address map cannot fit into a so small DRAM. As the DRAM controller code needs a big refactor, the SPL support is disabled in this version. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: Add clock support for DE2/HDMI/TCON on newer SoCsJernej Skrabec2017-04-204-1/+103
| | | | | | | | | | | | | | | | This is needed for HDMI, which will be added later. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: video: Convert lcdc to use struct display_timingJernej Skrabec2017-04-203-38/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Video driver for older Allwinner SoCs uses cfb console framework which in turn uses struct ctfb_res_modes to hold timing informations. However, DM video framework uses different structure - struct display_timing. It makes more sense to convert lcdc to use new timing structure because all new drivers should use DM video framework and older drivers might be rewritten to use new framework too. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: video: Split out TCON codeJernej Skrabec2017-04-206-285/+362
| | | | | | | | | | | | | | | | | | TCON unit has similar layout and functionality also on newer SoCs. This commit splits out TCON code for easier reuse later. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: Add support for Bananapi M2 UltraChen-Yu Tsai2017-04-205-0/+275
| | | | | | | | | | | | | | | | | | | | | | The Bananapi M2 Ultra is the first publicly available development board featuring the R40 SoC. This patch add barebone dtsi/dts files for the R40 and Bananapi M2 Ultra, as well as a defconfig for it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: Add PSCI support for R40Chen-Yu Tsai2017-04-202-3/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The R40's CPU controls are a combination of sun6i and sun7i. All controls are in the CPUCFG block, and it seems the R40 does not have a PRCM block. The core reset, power gating and clamp controls are grouped like sun6i. Last, the R40 does not have a secure SRAM block. This patch adds a PSCI implementation for CPU bring-up and hotplug for the R40. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: Fix CPUCFG address for R40Chen-Yu Tsai2017-04-201-2/+4
| | | | | | | | | | | | | | | | The R40 has the CPUCFG block at the same address as the A20. Fix it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: Enable SPL for R40Chen-Yu Tsai2017-04-201-0/+1
| | | | | | | | | | | | | | | | Now that we can do DRAM initialization for the R40, we can enable SPL support for it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: Use H3/A64 DRAM initialization code for R40Chen-Yu Tsai2017-04-206-18/+133
| | | | | | | | | | | | | | | | | | | | The R40 seems to have a variant of the memory controller found in the H3 and A64 SoCs. Adapt the code for use on the R40. The changes are based on released DRAM code and comparing register dumps from boot0. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * gpio: sunxi: Add compatible string for R40 PIOChen-Yu Tsai2017-04-201-0/+1
| | | | | | | | | | | | | | | | | | The PIO on the R40 SoC is mostly compatible with the A20. Only a few pin functions for mmc2 were added to the PC pingroup, to support 8 bit eMMCs. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: Provide defaults for R40 DRAM settingsChen-Yu Tsai2017-04-201-0/+3
| | | | | | | | | | | | | | | | | | These values were taken from the Banana Pi M2 Ultra fex file found in the released vendor BSP. This is the only publicly available R40 device at the time of this writing. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: Set PLL lock enable bits for R40Chen-Yu Tsai2017-04-202-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | According to the BSP released by Banana Pi, the R40 (sun8iw11p1) has an extra "PLL lock control" register in the CCU, which controls whether the individual PLL lock status bits in each PLL's control register work or not. This patch enables it for all the PLLs. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: Add mmc[1-3] pinmux settings for R40Chen-Yu Tsai2017-04-201-2/+15
| | | | | | | | | | | | | | | | The PIO is generally compatible with the A20, except that it routes the full 8 bits and eMMC reset pins for mmc2. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: Fix watchdog reset function for R40Chen-Yu Tsai2017-04-203-7/+8
| | | | | | | | | | | | | | | | The watchdog found on the R40 SoC is the older variant found on the A20. Add the proper "#if defines" to make it work. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: Enable AXP221s in I2C mode with the R40 SoCChen-Yu Tsai2017-04-203-7/+18
| | | | | | | | | | | | | | | | | | | | The R40 SoC uses the AXP221s in I2C mode to supply power. Some regulator's common usages have changed, and also the recommended voltage for existing usages have changed. Update the defaults to match. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: Add initial support for R40Chen-Yu Tsai2017-04-204-8/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The R40 is the successor to the A20. It is a hybrid of the A20, A33 and the H3. The R40's PIO controller is compatible with the A20, Reuse the A20 UART and I2C muxing code by adding the R40's macro. The display pipeline is the newer DE 2.0 variant. Block enabling video on R40 for now. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: Split up long Kconfig linesChen-Yu Tsai2017-04-201-5/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we have some lines in board/sunxi/Kconfig that are very long. These line either provide default values for a set of SoCs, or limit some option to a subset of sunxi SoCs. Fortunately Kconfig makes it easy to split them. The Kconfig language document states If multiple dependencies are defined, they are connected with '&&'. This means we can split existing dependencies at "&&" symbols. This applies to both the "depends on" lines and "if" expressions. This patch splits them up to one symbol per line. This will make it easier to add, remove, or modify one item at a time. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: Convert CONS_INDEX to KconfigMylène Josserand2017-04-2022-24/+12
| | | | | | | | | | | | | | | | | | | | | | Convert the CONS_INDEX configuration to Kconfig. Update sunxi's defconfigs to remove SYS_EXTRA_OPTIONS variable not needed anymore. Default value is 1 except for sun5i (equals 2) and sun8i (equals 5). Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> [Maxime: Added a depends on ARCH_SUNXI to avoid build breakages] Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: Convert CONFIG_MACPWR to KconfigMylène Josserand2017-04-2013-14/+22
| | | | | | | | | | | | | | | | Convert the CONFIG_MACPWR to Kconfig and update all the sunxi defconfigs that used it in SYS_EXTRA_OPTIONS. Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: Convert CONFIG_SATAPWR to KconfigMylène Josserand2017-04-2016-17/+27
| | | | | | | | | | | | | | | | | | Convert the CONFIG_SATAPWR into kconfig. Thanks to that, many SYS_EXTRA_OPTIONS can be removed from some defconfigs. Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: Convert CONFIG_RGMII to KconfigMylène Josserand2017-04-2015-14/+30
| | | | | | | | | | | | | | | | | | Convert CONFIG_RGMII to Kconfig. Thanks to that, it is possible to update defconfig files of SYS_EXTRA_OPTIONS accordingly and remove it when it is possible. Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: Convert SUNXI_EMAC to KconfigMylène Josserand2017-04-209-8/+18
| | | | | | | | | | | | | | | | | | Convert the SUNXI_EMAC config to Kconfig. Remove it from SYS_EXTRA_OPTIONS from many sunxi defconfig and renamed it into SUN4I_EMAC to not confuse it with SUN8I_EMAC. Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: mk802_defconfig: Remove SYS_EXTRA_OPTIONSMylène Josserand2017-04-201-1/+0
| | | | | | | | | | | | | | | | | | The USB_EHCI configuration is already set in this defconfig using kconfig's config. This configuration in SYS_EXTRA_OPTIONS must be removed and so the SYS_EXTRA_OPTIONS. Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: icnova-a20-swac_defconfig: Remove CMD_BMP fromMylène Josserand2017-04-201-1/+0
| | | | | | | | | | | | | | | | This configuration is not necessary in a defconfig file so it is removed from the SYS_EXTRA_OPTIONS. Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: icnova-a20-swac_defconfig: Remove AXP209_POWERMylène Josserand2017-04-201-1/+1
| | | | | | | | | | | | | | | | | | Remove the AXP209_POWER option from SYS_EXTRA_OPTIONS. As this configuration already exists on Kconfig, we just need to remove it from defconfig. Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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