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* efi: Add a serial driverSimon Glass2015-08-053-0/+167
| | | | | | | | | Add a serial driver which makes use of EFI's console in/out service. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested on Intel Crown Bay and QEMU Tested-by: Bin Meng <bmeng.cn@gmail.com>
* Add a way to skip relocationSimon Glass2015-08-052-0/+10
| | | | | | | | | | | When running U-Boot as an EFI application we cannot relocate since we do not have relocation information. U-Boot has already been relocated to a suitable address. Add a global_data flag to control skipping relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Update README to explain booting Ubuntu on MinnowmaxSimon Glass2015-08-051-0/+278
| | | | | | | | | | | | | | | | The steps required to boot a Linux distribution from U-Boot on x86 are not very complicated, but it is a good idea to have these written down in an accessible place. Document how to examine the boot media from U-Boot, how to load a kernel, load a ramdisk, set the kernel boot arguments and start the kernel. With these instructions Ubuntu boots mostly normally on Minnowmax. Note that the TSC timer does not operate correctly and gives warnings in the boot log. I expect that ACPI support will solve this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: minnowmax: Drop the old PCI settingsSimon Glass2015-08-051-12/+0
| | | | | | | | These are now in the device tree so we don't need to use the CONFIG options. Drop them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: dts: Fix typo in intel,irq-router.txtSimon Glass2015-08-051-2/+2
| | | | | | | Fix a small typo in this binding file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Drop CONFIG_DCACHE_RAM_MRC_VAR_SIZE from header fileSimon Glass2015-08-051-1/+0
| | | | | | | This is provided in Kconfig so we don't need it here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move CONFIG_X86_SERIAL to KconfigSimon Glass2015-08-057-10/+11
| | | | | | | Move this config option to Kconfig and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move Chrome OS options to defconfigSimon Glass2015-08-053-3/+6
| | | | | | | Drop these from the header file and use Kconfig instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: Add a return value comment to device_get_child()Simon Glass2015-08-051-1/+3
| | | | | | | At present this function does not specify its return value. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: Indicate prefetchable memory allocate when debuggingSimon Glass2015-08-051-2/+3
| | | | | | | | | | At present the PCI output displays 'Mem' when it allocates memory for a PCI device, whether it is prefetchable or not. There is a distinction since the memory comes from separate pools. Use 'Prf' instead of 'Mem' when allocating prefetchable memory. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: Add a constant for an invalid interruptSimon Glass2015-08-052-1/+4
| | | | | | | Rather than using 0xff in the code, add a constant. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* efi: Display the correct initcall pre-relocation valuesSimon Glass2015-08-051-0/+4
| | | | | | | | | | | | With EFI the start address of U-Boot is specified differently. We could consider just setting GD_FLG_RELOC and then setting up reloc_off. But that flag has other implementations and we are not able to use U-Boot relocation which this flag implies. Instead, just add a special case for EFI. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* efi: Avoid using non-existent text baseBen Stoltz2015-08-051-3/+4
| | | | | | | | | | | | | When U-Boot runs as an EFI application is does not have a definition of CONFIG_SYS_TEXT_BASE. U-Boot is a relocatable application and the relocation is done by EFI. U-Boot can be loaded at any address. This is similar to how sandbox works. Adjust the early board init to deal with this. Signed-off-by: Ben Stoltz <stoltz@google.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* efi: Add start-up library codeSimon Glass2015-08-0510-64/+887
| | | | | | | | | | | When running as an EFI application, U-Boot must request memory from EFI, and provide access to the boot services U-Boot needs. Add library code to perform these tasks. This includes efi_main() which is the entry point from EFI. U-Boot is built as a shared library. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Allow use of global_data with EFISimon Glass2015-08-051-0/+7
| | | | | | | | | | | | | | | On x86 the global_data pointer is provided through a somewhat-bizarre and x86-specific mechanism: the F segment register is set to a pointer to the start of global_data, so that accesses can use this build-in register. When running as an EFI application we don't want to mess with the Global Descriptor Table (GDT) and there is little advantage (in terms of code size) to doing so. Allow global_data to be a simple variable in this case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: Fix up code for CONFIG_PCI_ENUM_ONLYSimon Glass2015-08-051-1/+3
| | | | | | | | This option is not used by any board but appears to still be useful, at least for testing. With recent commits it does not build, so fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: Use debug() instead of DEBUGF() in pci_auto.cSimon Glass2015-08-051-25/+23
| | | | | | | | | This file does not need its own way of doing debug(). Clean it up to use the new way. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Tidy up a few minor issues with interruptsSimon Glass2015-08-051-5/+4
| | | | | | | | Fix a typo, remove an unused field and make sure to use existing #define constants instead of open-coded values. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add some missing global_data declarations in files that use gdSimon Glass2015-08-056-0/+12
| | | | | | | Some files use global_data but don't declare it. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Tidy up the 64-bit calling codeSimon Glass2015-08-051-2/+2
| | | | | | | | The GDT works but technically the length is incorrect. Fix this and add a comment. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Drop unused copy_fdt_to_ram()Simon Glass2015-08-052-19/+0
| | | | | | | | This is now handled by generic U-Boot code so we do not need an x86 version. It is no-longer called, so remove it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Tidy up global_data flagsSimon Glass2015-08-052-7/+11
| | | | | | | | | | These flags now overlap some global ones. Adjust the x86-specific flags to avoid this. Since this requires a change to the start.S code, add a way for tools to find the 32-bit cold reset entry point. Previously this was at a fixed offset. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Reserve the top 16 flag bits for architecture-specific useSimon Glass2015-08-051-1/+1
| | | | | | | | | Add a convention that the generic global_data only occupy the bottom 16 bits of the flags word, so that there is less chance of a conflict. At present the x86 flags conflict. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Use CR0 constants in CPU initSimon Glass2015-08-051-1/+1
| | | | | | | We should use these constants where possible. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add various minor tidy-ups to the 32-bit startup codeSimon Glass2015-08-051-20/+26
| | | | | | | | Fix a typo, improve some comments and add a little more detail in some cases. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Bring in __aligned_u64 and friends to linux/types.hSimon Glass2015-08-051-1/+5
| | | | | | | | These will be used for efi.h both for U-Boot running as an EFI application and as a payload. They come from Linux 4.1. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Allow objcopy to work without filling gaps with 0xffSimon Glass2015-08-052-3/+7
| | | | | | | | | This is currently done for all targets, since 0xff is the default erased value for most flash devices. In some cases this is not what we want (e.g. for EFI images) so provide a command to do a vanilla objcopy. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* elf: Add a few definitions for 64-bit relocationSimon Glass2015-08-051-0/+26
| | | | | | | Provide the types necessary to relocate 64-bit images. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: serial: Correct logic in serial_find_console_or_panic()Simon Glass2015-08-051-1/+1
| | | | | | | | | | | | | In a final attempt to find a console UART this function uses the first first available serial device. However the check for a valid device is inverted. This code is only executed when there is in fact no serial UART, but at present it can fail to reach the panic_str() call in this case, and start trying to use a non-existent UART. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: core: Check for empty list in uclass_find_device()Simon Glass2015-08-051-0/+2
| | | | | | | | This function needs to check the list has entries before traversing it. Fix this bug. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Support removing default assembler flagsSimon Glass2015-08-051-1/+2
| | | | | | | | | | The CFLAGS_REMOVE_<file> feature allows default C compiler flags to be removed for particular files. Add the same feature for assembler, using AFLAGS_REMOVE_<file>. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* common: command add '\n' for debug msgPeng Fan2015-08-051-1/+1
| | | | | | | | | | Add '\n' for debug msg. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Tom Rini <trini@konsulko.com> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* lib: fdt: fix indent of #ifdef..#endif conditionalMasahiro Yamada2015-08-051-1/+1
| | | | | | | | Match the depth of indentation between #ifdef and #endif for better readability. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
* common: Print nothing in the __weak checkboard()Bin Meng2015-08-051-1/+0
| | | | | | | Do not print confusing "Board: Unknown" during boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* gitignore: Add defconfig and fdtgrepBin Meng2015-08-052-0/+2
| | | | | | | Ignore defconfig and tools/fdtgrep. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: bayleybay: Configure PCI IRQBin Meng2015-08-054-0/+74
| | | | | | | | Add PCI IRQ routing information in the board device tree and enable writing PIRQ routing table and MP table. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add Intel Bayley Bay board supportBin Meng2015-08-0510-1/+283
| | | | | | | | Intel Bayley Bay board is a BayTrail based board. Add this board with existing baytrail fsp support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add microcode for BayTrail-I B0 steppingBin Meng2015-08-051-0/+4244
| | | | | | | | This commit adds the microcode blob for BayTrail-I B0 stepping, CPUID signature 30671h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: baytrail: Update UPD setting for FSP Gold4 releaseBin Meng2015-08-051-1/+2
| | | | | | | | BayTrail FSP Gold4 release adds one UPD parameter to control IGD enable/disable. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: minnowmax: Remove smsc47x superio codesBin Meng2015-08-052-14/+0
| | | | | | | | | On Intel BayTrail SoC, there is a legacy UART (I/O 0x3f8) integrated into the SoC which is enabled by the FSP. Remove the smsc47x superio initialization codes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Sanity test on vesa parameters before setting up kernel screen_infoBin Meng2015-08-051-0/+4
| | | | | | | | We should not set up kernel screen_info when the vesa parameters are insane, otherwise kernel will panic. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: qemu: Add MP initializationBin Meng2015-08-054-0/+21
| | | | | | | | | Add a cpu1 node to the device tree and enable the MP initialization on QEMU targets (i440fx and q35). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: Add a 'pause' instruction in __udelay() for QEMU targetMiao Yan2015-08-051-0/+8
| | | | | | | | | | | | | | | | When running SMP configuration on QEMU (tcg mode, no kvm), there is a busy loop in start_aps(), calling udelay(), that waits for APs to show up online. However, there is a chance that VCPU1 will be timeout waiting, IOW the secondary VCPUs haven't started their execution yet. This patch adds a 'pause' instruction in __udelay() only for QEMU target, to give other VCPUs a chance to run. When QEMU sees the 'pause' instruction, it will yeild the execution to other CPUs. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* doc: dm: Update pci-info.txt for pci supportBin Meng2015-08-051-3/+3
| | | | | | | Correct two typos and mention how pci bus will be probed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: pci: Allow scan bridge child devices before relocationBin Meng2015-08-051-4/+0
| | | | | | | | | On some platforms pci devices behind bridge need to be probed (eg: a pci uart on recent x86 chipset) before relocation. Remove such limitation so that dm pci can be used before relocation. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-08-0434-432/+1185
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| * armv8/ls2085ardb: Add USB support for ls2085ardbNikhil Badola2015-08-031-0/+13
| | | | | | | | | | | | | | Add USB XHCI support for ls2085rdb platform Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085aqds: Add USB support for ls2085aqdsNikhil Badola2015-08-031-0/+13
| | | | | | | | | | | | | | Add USB XHCI support for ls2085qds platform Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/lsch3/config: Define USB XHCI controller base address for LS2085ANikhil Badola2015-08-031-0/+3
| | | | | | | | | | | | | | | | Define base address of both usb xhci controllers in lsch3 config in the format (IMMR + offset) for LS2085A Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/lsch3/config: Define CONFIG_SYS_CACHELINE_SIZE for LS2085ANikhil Badola2015-08-031-0/+1
| | | | | | | | | | | | | | | | Define CONFIG_SYS_CACHELINE_SIZE for LS2085A which is required by USB XHCI stack for alignment Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
generated by cgit (git 2.34.1) at 2024-11-13 11:31:10 +0000