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* rockchip: rk3368: enable stimer for rk3368Kever Yang2019-07-203-1/+50
| | | | | | | Add stimer_init() for spl/tpl so that we able to switch to use arch timer. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: rk3368: move sgrf init to spl as arch_cpu_init()Kever Yang2019-07-203-70/+80
| | | | | | | The SoC related init will move to SPL and keep TPL clean, so that we can reuse the common TPL board file. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: remove rk_timerKever Yang2019-07-202-43/+0
| | | | | | | We have convert all SoC to use DM timer or ARM arch/generic timer, we can remove this rk_timer now. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: remove no use header file in board codeKever Yang2019-07-202-2/+0
| | | | | | The timer.h is no use any more, remove it from the board files. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: rk3128: use ARM arch timer instead of rk_timerKever Yang2019-07-203-12/+4
| | | | | | | | We prefer to use ARM arch timer instead of rockchip timer, so that we are using the same timer for SPL, U-Boot and Kernel, which will make things simple and easy to track to boot time. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: rk3288: use ARM arch timer instead of rk_timerKever Yang2019-07-204-8/+58
| | | | | | | | We prefer to use ARM arch timer instead of rockchip timer, so that we are using the same timer for SPL, U-Boot and Kernel, which will make things simple and easy to track to boot time. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: rk3036: use ARM arch timer instead of rk_timerKever Yang2019-07-203-7/+31
| | | | | | | | We prefer to use ARM arch timer instead of rockchip timer, so that we are using the same timer for SPL, U-Boot and Kernel, which will make things simple and easy to track the boot time. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: rk3036: sdram: use udelay instead of rockchip_udelayKever Yang2019-07-201-10/+9
| | | | | | | Use system api for udelay instead of vendor defined api, and rockchip_udelay() will be removed. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: rk322x: use ARM arch timer instead of rk_timerKever Yang2019-07-205-7/+66
| | | | | | | | We prefer to use ARM arch timer instead of rockchip timer, so that we are using the same timer for SPL, U-Boot and Kernel, which will make things simple and easy to track to boot time. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: rk322x: sdram: use udelay instead of rockchip_udelayKever Yang2019-07-201-15/+14
| | | | | | | Use system api for udelay instead of vendor defined api, and rockchip_udelay() will be removed. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: board: rk3288: remove board_boot_order()Kever Yang2019-07-205-43/+0
| | | | | | | Prefer to use dts config instead, remove all board_boot_order() for rk3288 boards. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: rk3288: dts: enable spl-boot-orderKever Yang2019-07-202-1/+8
| | | | | | | We share the same default SPL boot order for all rk3288 boards, use dts instead of hard code in board file. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: spl-boot-order: update dependency to OF_LIBFDTKever Yang2019-07-201-1/+1
| | | | | | | | The fdt interfaces are actuall depends on OF_LIBFDT instead of OF_CONTROL, some boards may enable OF_CONTROL while disable OF_LIBFDT. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: popmetal-rk3288: add -u-boot.dtsiKever Yang2019-07-202-26/+46
| | | | | | Move U-Boot relate dts node/property into -u-boot.dtsi Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: miqi-rk3288: add -u-boot.dtsiKever Yang2019-07-202-18/+38
| | | | | | Move U-Boot relate dts node/property into -u-boot.dtsi Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: rk3288-firefly: sync sdmmc pinctrl from mainlineKever Yang2019-07-202-6/+26
| | | | | | | | The rk3288-firefly board have different setting for sdmmc io, sync then from kernel mainline: 6fbc7275c7a9 Linux 5.2-rc7 Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: firefly-rk3288: add -u-boot.dtsiKever Yang2019-07-202-23/+54
| | | | | | Move U-Boot relate dts node/property into -u-boot.dtsi Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: rk3288: update u-boot raw image size for all boardsKever Yang2019-07-202-1/+2
| | | | | | | | Some rk3288 boards are using raw image of u-boot.bin, and now it's much bigger than default 200KB, update CONFIG_SYS_MONITOR_LEN to 600KB. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: fennec-rk3288: add -u-boot.dtsiKever Yang2019-07-202-25/+54
| | | | | | Move U-Boot relate dts node/property into -u-boot.dtsi Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: evb-rk3288: add -u-boot.dtsiKever Yang2019-07-202-25/+46
| | | | | | Move U-Boot relate dts node/property into -u-boot.dtsi Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: rk3288: enable TPL for evb-rk3288Kever Yang2019-07-202-6/+4
| | | | | | | Enable TPL for evb-rk3288 so that we can have a free size limited SPL. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: rk3288: add default TPL_LDSCRIPT value in KconfigKever Yang2019-07-202-1/+3
| | | | | | | We share the same TPL_LDSCRIPT for all rk3288 board, add default value in Kconfig. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: rk3288: move configure_l2ctlr back to rk3288Kever Yang2019-07-202-22/+22
| | | | | | | The configure_l2ctlr() is used only by rk3288, do not need to locate in sys_proto.h Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: rk3288: add arch_cpu_init in splKever Yang2019-07-203-3/+10
| | | | | | | | | Add arch_cpu_init() in SPL for soc related init, and move configure_l2ctlr() into it. The arch_cpu_init() only need to run once, so no need to run in TPL. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: rk3368: default enable SPL LIBCOMMON and LIBGENERICKever Yang2019-07-203-4/+6
| | | | | | | | We needs SPL LIBCOMMON and LIBGENERIC for all boards, so we can enable them by default and no need to define in each board. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: rk322x: default enable SPL LIBCOMMON and LIBGENERICKever Yang2019-07-202-2/+6
| | | | | | | | We needs SPL LIBCOMMON and LIBGENERIC for all boards, so we can enable them by default and no need to define in each board. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: rk3328: default enable SPL LIBCOMMON and LIBGENERICKever Yang2019-07-203-4/+6
| | | | | | | | We needs SPL LIBCOMMON and LIBGENERIC for all boards, so we can enable them by default and no need to define in each board. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: rk3399: default enable SPL LIBCOMMON and LIBGENERICKever Yang2019-07-2013-24/+6
| | | | | | | | We needs SPL LIBCOMMON and LIBGENERIC for all boards, so we can enable them by default and no need to define in each board. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: rk3368: use defaule value for SYS_MALLOC_F_LENKever Yang2019-07-204-3/+3
| | | | | | | There is no difference in rk3368 board use for SYS_MALLOC_F_LEN, so we can use default value. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: rk3328: use defaule value for SYS_MALLOC_F_LENKever Yang2019-07-202-2/+1
| | | | | | | There is no difference in rk3328 board use for SYS_MALLOC_F_LEN, so we can use default value. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: rk3399: use default value for SYS_MALLOC_F_LENKever Yang2019-07-2013-13/+1
| | | | | | | There is no difference in rk3399 board use for SYS_MALLOC_F_LEN, so we can use default value. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: rk3288: use default value for SYS_MALLOC_F_LENKever Yang2019-07-2013-13/+1
| | | | | | | There is no difference in rk3288 board use for SYS_MALLOC_F_LEN, so we can use default value. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: rk322x: use defconfig for SYS_MALLOC_F_LENKever Yang2019-07-202-2/+1
| | | | | | | There is no difference in rk322x board use for SYS_MALLOC_F_LEN, so we can use default value. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: Kconfig: move ROCKCHIP_BOOT_MODE_REG to soc KconfigKever Yang2019-07-2010-8/+27
| | | | | | | | Rockchip SoCs have different ROCKCHIP_BOOT_MODE_REG value, move it to SoC's own Kconfig, and add address for rk3128 and rk3328 so that all SoCs have available address. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: Kconfig: move rk3399 config into its KconfigKever Yang2019-07-202-16/+12
| | | | | | | Each SoC have its config setting and its Kconfig, move the specific setting to its own Kconfig file. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: Kconfig: move rk3368 config into its KconfigKever Yang2019-07-202-13/+9
| | | | | | | Each SoC have its config setting and its Kconfig, move the specific setting to its own Kconfig file. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: Kconfig: move rk3288 config into its KconfigKever Yang2019-07-202-13/+9
| | | | | | | Each SoC have its config setting and its Kconfig, move the specific setting to its own Kconfig file. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: Kconfig: move rk322x config into its KconfigKever Yang2019-07-202-13/+10
| | | | | | | Each SoC have its config setting and its Kconfig, move the specific setting to its own Kconfig file. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: fixup board choice in KconfigKever Yang2019-07-203-0/+15
| | | | | | | Kconfig for board target select is choice option, fixup for rk3036, rk3288 and rv1108. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: remove redundant pinctrl header includingKever Yang2019-07-202-2/+0
| | | | | | No code is using this header file, remove it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: rk3288: remove pinctrl init in spl_board_initKever Yang2019-07-202-28/+0
| | | | | | | The pinctrl will default init the io while driver is probe with new pinctrl driver. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: rk3188: remove pinctrl init in spl_board_initKever Yang2019-07-202-32/+0
| | | | | | | The pinctrl will default init the io while driver is probe with new pinctrl driver. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: rk3399: remove pinctrl init in spl_board_initKever Yang2019-07-201-8/+0
| | | | | | | The pinctrl will default init the io while driver is probe with new pinctrl driver. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: dts: rk3399: rock-pi-4: Use LPDDR4-100 dtsiJagan Teki2019-07-201-0/+2
| | | | | | | | | | | | | | | | | Use LPDDR4-100 sdram timings dtsi for RockPI-4 board. All these timings are processed during TPL stage of rock-pi-4 board, bootchain. This make TPL would replace rockchip in house rkbin in current bootchain. Bootchain after and before this change: TPL -> SPL -> U-Boot proper rkbin -> SPL -> U-Boot proper Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
* rockchip: dts: rk3399: nanopi-neo4: Use DDR3-1866 dtsiJagan Teki2019-07-201-0/+1
| | | | | | | | | | | | | | | | | | | | | Use DDR3-1866 2GB ddr timings dtsi for 1GB NanoPi Neo4 board. Since sdram rk3399 support dynamic stride and rank detection it can able to detect 1GB ddr eventough the timings are meant for dual channel, 2GB size. Bootchain after and before this change are: TPL -> SPL -> U-Boot proper rkbin -> SPL -> U-Boot proper This certainly fix the second channel data training initialization since we have dynamic rank, stride where second channel capabilities are clear or memset to 0. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
* rockchip: dts: rk3399: rockpro64: Use LPDDR4-100 dtsiJagan Teki2019-07-211-0/+1
| | | | | | | | | | | | | | | | | Use LPDDR4-100 sdram timings dtsi for Rockpro64 board. All these timings are processed during TPL stage of rockpro64 board, bootchain. This make TPL would replace rockchip in house rkbin in current bootchain. Bootchain after and before this change: TPL -> SPL -> U-Boot proper rkbin -> SPL -> U-Boot proper Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
* rockchip: dts: rk3399: Add LPDDR4-100 timingsJagan Teki2019-07-211-0/+1537
| | | | | | | | | | | | Add sdram timings for LPDDR4-100 via rk3399-sdram-lpddr4-100.dtsi file. all timings are dumped from rkbin/bin/rk33/rk3399_ddr_800MHz_v1.20.bin Associated LPDDR4 board -u-boot.dtsi can include this to make these timings available during SPL or TPL stages. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
* configs: rock-pi-4: Enable LPDDR4 supportJagan Teki2019-07-211-0/+1
| | | | | | | | | | Due to foot-print issues, we have LPDDR4 code can be marked as CONFIG_RAM_RK3399_LPDDR4. So, enable it for Rock-PI-4 board. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
* configs: rockpro64: Enable LPDDR4 supportJagan Teki2019-07-211-0/+1
| | | | | | | | | | Due to foot-print issues, we have LPDDR4 code can be marked as CONFIG_RAM_RK3399_LPDDR4. So, enable it for Rockpro64 board. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
* ram: rk3399: Add lpddr4 set rate supportJagan Teki2019-07-201-12/+661
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unlike rest of dram type chips, LPDDR4 initialization start with at board selected frequency (say 50MHz) and then it switches into 400MHz and 800MHz simultaneously to make the proper sequence work on each channel with associated training. The lpddr4 set rate sequnce will follow by setting lpddr4 - dq out - ca odt - MR3 - MR12 - MR14 registers sets in sequential order. Here is sameple log about LPDDR4-100 init sequence in Rockpro64: Channel 0: LPDDR4, 50MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Channel 1: LPDDR4, 50MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB 256B stride channel 0 training pass channel 1 training pass change freq to 400 MHz 0, 1 channel 0 training pass channel 1 training pass change freq to 800 MHz 1, 0 This patch add support to this init sequence via lpddr4 set rate by taking sdram timing parameters from 400, 800 .inc files. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> (Fix travis error, use one ret instead of ret[2] in set_ctrl) Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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