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| * | | arm: dts: ls1021a: add gpio nodeBiwen Li2021-02-081-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add gpio node for SoC LS1021A Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | gpio: mpc8xxx_gpio: Fix for litte endianBiwen Li2021-02-084-39/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Update gpio driver to use same logic for big-endian and little-endian Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | configs: T1042: Drop the CONFIG_VIDEOHou Zhiqiang2021-02-0810-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Drop the CONFIG_VIDEO to fix the following build warning. ===================== WARNING ====================== This board does not use CONFIG_DM_VIDEO Please update the board to use CONFIG_DM_VIDEO before the v2019.07 release. UPD include/generated/dt.h Failure to update by the deadline may result in board removal. See doc/driver-model/migration.rst for more info. UPD include/generated/timestamp_autogenerated.h ==================================================== Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | mpc8xxx: fsl_pamu: Update data type in config_pamuPriyanka Jain2021-02-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update data type of '1' to '1ull' in below assignment size = 1ull << sizebit; to fix incorrect assignment issue. e.g: when sizebit was 31, 0x80000000 got sign extended to 0xffffffff_80000000 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reported-by: Dean Saridakis <dean.saridakis@baesystems.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | armv7: ls102xa: Enable I-Cache to speed up the boot timeHou Zhiqiang2021-02-081-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the I-Cache to speed up the boot time, especailly for the NOR boot, currently it takes about 15 seconds from power up to the U-Boot prompt, and with the I-Cache enabled it only takes around 2.5 seconds. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | board/km: move km i2c deblock declarations to a km/common.hAleksandar Gerasimovski2021-02-083-10/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cleanup, move the declarations to keymile/common.h instead declaring them per-board config.h Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | pci: kconfig: layerscape: Change LX2162A PCIe node compatible stringHou Zhiqiang2021-02-081-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LX2162A is not like LX2160A which has different PCIe controller in rev1 and rev2 silicon. It supports only one configuration of PCIe controller, which is same as LS2088A. So update PCIe compatible string same as LS2088A. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Tested-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | pci: layerscape: Remove the shadow SVR definitionsHou Zhiqiang2021-02-084-42/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves the SVR definitions to a new svr.h for Layerscape armv7 and armv8 platforms respectively, so that the PCIe driver can reuse them. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | spi: fsl_qspi: apply the same settings for LS1088 as LS208xMathew McBride2021-02-081-9/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LS1088 requires the same QUADSPI_QURIK_BASE_INTERNAL workaround as the LS208x and also has a 64 byte TX buffer. With the previous settings SPI-NAND reads over AHB were corrupted. Fixes: 91afd36f3802 ("spi: Transform the FSL QuadSPI driver to use the SPI MEM API") Signed-off-by: Mathew McBride <matt@traverse.com.au> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | spi: fsl_qspi: Ensure width is respected in spi-mem operationsMathew McBride2021-02-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adapted from kernel commit b0177aca7aea From: Michael Walle <michael@walle.cc> Make use of a core helper to ensure the desired width is respected when calling spi-mem operators. Otherwise only the SPI controller will be matched with the flash chip, which might lead to wrong widths. Also consider the width specified by the user in the device tree. Fixes: 91afd36f38 ("spi: Add a driver for the Freescale/NXP QuadSPI controller") Signed-off-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20200114154613.8195-1-michael@walle.cc Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Mathew McBride <matt@traverse.com.au> [adapt for U-Boot] Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | mem: spi-mem: add declaration for spi_mem_default_supports_opMathew McBride2021-02-081-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | spi_mem_default_supports_op is used internally by controller drivers to verify operation semantics are correct. It is used internally inside spi-mem but has not (in U-Boot) been declared in spi-mem.h for external use. Signed-off-by: Mathew McBride <matt@traverse.com.au> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | PowerPC: keymile: Add support for kmcent2 boardNiel Fourie2021-02-0814-0/+1320
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add basic support for the Hitachi Power Grids kmcent2 board, based on the NXP QorIQ T1040 SoC. Signed-off-by: Valentin Longchamp <valentin.longchamp@hitachi-powergrids.com> Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Niel Fourie <lusus@denx.de> Cc: Holger Brunck <holger.brunck@hitachi-powergrids.com> Cc: Heiko Schocher <hs@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> [Fixed blank line at EOF errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | keymile: common: update to set_env_hex(), fix "pram" radixNiel Fourie2021-02-081-16/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace instances of sprintf()/set_env() for setting hexadecimal values with set_env_hex(). In set_km_env() the "pram" variable was set to an hexadecimal value, while initr_mem() expects an unsigned decimal, so use set_env_ulong() instead. Signed-off-by: Niel Fourie <lusus@denx.de> Cc: Holger Brunck <holger.brunck@hitachi-powergrids.com> Cc: Heiko Schocher <hs@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | PowerPC: dts: Pulled in kmcent2 dts files from Linux 5.10Niel Fourie2021-02-0817-0/+1580
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pulled in the kmcent2.dts and all its dependents from Linux 5.10, commit 2c85ebc57b3e upstream. Replaced the license text with SPDX License Identifiers. Signed-off-by: Niel Fourie <lusus@denx.de> Cc: Holger Brunck <holger.brunck@hitachi-powergrids.com> Cc: Heiko Schocher <hs@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | board/km/common: fix pnvramaddr and varaddrAleksandar Gerasimovski2021-02-081-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Take into account SDRAM_BASE address when calculating pnvramaddr and varaddr offsets. Up to now Keymile designs had SDRAM_BASE equal to zero and the offsets where calculated correctly, this fix is for the upcoming designs that have SDRAM_BASE different then zero. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | keymile: common: qrio: print QRIO id and revision numberAleksandar Gerasimovski2021-02-082-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add show_qrio function to print chip id and revision information. There are already multiple QRIO chip versions available and the upcoming designs may want to show used version. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | board: keymile: common: fix qrio compilation for armAleksandar Gerasimovski2021-02-081-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is fixing qrio driver compilation for ARM architecture: - It includes asm/io.h for in_/out_ access - It use correct names for set/clear_bits as defined in linux/bitops.h Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | armv8: lx2: SVR_SOC_VER: Mask CAN_FD and security bitWasim Khan2021-02-081-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Multiple LX2(LX2160A/LX2162A SoC) personality variants exists based on CAN-FD and security bit in SVR. Currenly SVR_SOC_VER mask only security bit. Update SVR_SOC_VER to mask CAN_FD and security bit for LX2 products. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | armv8: ls1028a: fix stream id allocationNipun Gupta2021-02-081-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When A-050382 errata is enabled, ECAM and EDMA have conflicting stream id 40. This patch fixes the same. Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com> Reviewed-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | board: sl28: add SATA supportMichael Walle2021-02-087-11/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable SATA support. Although not supported by the usual SATA pins on the SMARC baseboard connector, SATA mode is supported on a PCIe lane. This way one can use a mSATA card in a Mini PCI slot. We need to invert the received data because in this mode the polarity of the SerDes lane is swapped. Provide a fixup in board_early_init_f() for the SPL. board_early_init_f() is then not common between SPL and u-boot proper anymore, thus common.c is removed, as it just contained said function. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | board: sl28: add network variant 2 supportMichael Walle2021-02-085-3/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Although this variant has two external network ports, they are not (yet) supported by the bootloader because they are connected via an internal network switch. Otherwise its the same as the other variants. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | board: sl28: add network variant 1 supportMichael Walle2021-02-085-3/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This variant has one network port connected via RGMII and doesn't have any TSN capabilities out-of-the-box. Instead it has all four SerDes lanes available for customer use. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | board: sl28: move ethernet aliases to variant specific dtsiMichael Walle2021-02-083-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The variants differ in their network configuration. Move the first two network aliases to the proper variant device tree includes. This is in prepartion for variant 1 and 2 support which has a different network port mapping. The network aliases for the two internal ports will stay in the common dtsi because they are present on all board variants. This might leave a hole if there is no ethernet1 alias. This is intended. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | net: eqos: Reduce the MDIO wait timeYe Li2021-02-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current MDIO wait time is too long, which introduce long delay when PHY negotiation register checking. Reduce it to 10us Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Fugang Duan <Fugang.duan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | armv8: dts: fsl-lx2162a: add dspi node into qds dtsZhao Qiang2021-02-081-0/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add dspi node into lx2162aqds device tree Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | armv8: lx2162aqds: disable non existing pcie controllersWasim Khan2021-02-081-12/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | disable non existing pcie controllers on lx2162aqds Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | configs: ls1088aqds: add COMMON_ENV to fix distrobootBiwen Li2021-02-081-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add COMMON_ENV(kernelheader_addr_r, fdtheader_addr_r, kernel_addr_r, fdt_addr_r, load_addr) to fix a bug that failed to boot to ubuntu Failed log as follows, ## Executing script at 80000000 load - load binary file from a filesystemUsage: load <interface> [<dev[:part]> [<addr> [<filename> [bytes [pos]]]]] - Load binary file filename from partition part on device type interface instance dev to address addr in memory. bytes gives the size to load in bytes. If bytes is 0 or omitted, the file is read until the end. pos gives the file byte position to start reading from. If pos is 0 or omitted, the file is read from the start. ... Bad Linux ARM64 Image magic! SCRIPT FAILED: continuing... Signed-off-by: Biwen Li <biwen.li@nxp.com> [Updated description] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | net: memac_phy: add a timeout to MDIO operationsIoana Ciornei2021-02-081-18/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have encountered circumstances when a board design does not include pull-up resistors on the external MDIO buses which are not used. This leads to the MDIO data line not being pulled-up, thus the MDIO controller will always see the line as busy. Without a timeout in the MDIO bus driver, the execution is stuck in an infinite loop when any access is initiated on that external bus. Add a timeout in the driver so that we are protected in this circumstance. This is similar to what is being done in the Linux xgmac_mdio driver. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Madalin Bucur <madalin.bucur@oss.nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | board: kontron: disable flash unlock allMichael Walle2021-02-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Although the status register is protected by the hardware write protection, there is a hardware jumper to disable that hardware write protection. Thus if a user would set this jumper any u-boot start would disable the write protection altogether. Circumvent that by not disabling the write protection in the first place. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | | mtd: spi-nor: add unlock all config optionMichael Walle2021-02-082-4/+15
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide an explicit configuration option to disable default "unlock all" of any flash chip which supports locking. It doesn't make sense to automatically unprotect the entire flash on each u-boot startup if the block protection bits are actually used. Traditionally, the unlock was there to be able to write to flash devices which powered-up with the block protection bits set. Over time this feature creeped into all flash devices which support locking. For a more detailed description and discussion see: https://lore.kernel.org/linux-mtd/20201203162959.29589-8-michael@walle.cc/ Keep things simple in u-boot and just provide a configration option to disable this behavior which can be set per board. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | | Merge git://git.denx.de/u-boot-shTom Rini2021-02-0817-134/+2247
|\ \ \ | | | | | | | | | | | | - Beacon EmbeddedWorks RZG2H/N Dev Kit support
| * | | ARM: rmobile: Add Beacon EmbeddedWorks RZG2H Dev KitAdam Ford2021-02-077-1/+190
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Beacon EmbeddedWorks kit is based on the R8A774E1 SoC also known as the RZ/G2H. The kit consists of a SOM + Baseboard and supports microSD, eMMC, Ethernet, a couple celular radios, two CAN interfaces, Bluetooth and WiFi. It shares much of the same design as the RZ/G2M and RZ/G2N dev kits. Signed-off-by: Adam Ford <aford173@gmail.com>
| * | | ARM: rmobile: Add Beacon EmbeddedWorks RZG2N Dev KitAdam Ford2021-02-077-1/+179
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Beacon EmbeddedWorks kit is based on the R8A774B1 SoC also known as the RZ/G2N. The kit consists of a SOM + Baseboard and supports microSD, eMMC, Ethernet, a couple celular radios, two CAN interfaces, Bluetooth and WiFi. It shares much of the same design as the RZ/G2M dev kit. Signed-off-by: Adam Ford <aford173@gmail.com>
| * | | arm: dts: r8a774b1: Import DTS queued for Linux 5.12-rc1Adam Ford2021-02-071-2/+74
| | | | | | | | | | | | | | | | | | | | | | | | Update the RZ/G2N dtsi from Renesas repo destined to become 5.12-rc1. Signed-off-by: Adam Ford <aford173@gmail.com>
| * | | arm: dts: r8a774e1: Import DTS queued for Linux 5.12-rc1Adam Ford2021-02-071-27/+1347
| | | | | | | | | | | | | | | | | | | | | | | | Update the RZ/G2H dtsi from Renesas repo destined to become 5.12-rc1. Signed-off-by: Adam Ford <aford173@gmail.com>
| * | | arm: dts: r8a774a1: Import DTS queued for Linux 5.12-rc1Adam Ford2021-02-074-104/+445
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the RZ/G2M dtsi and r8a774a1-beacon-rzg2m-kit kit from Renesas repo destined to become 5.12-rc1. Signed-off-by: Adam Ford <aford173@gmail.com>
| * | | dt-bindings: Sync versaclock.h with upcoming 5.12-rc1Adam Ford2021-02-071-0/+13
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | The versaclock doesn't have a driver yet, but there are a bunch of device tree updates for the Beacon RZ/G2 boards that won't compile without these. A driver is coming, so sync the bindings for now Signed-off-by: Adam Ford <aford173@gmail.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2021-02-0812-99/+188
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| * | fastboot: reinit partition after storing GPT or MBRRoman Stratiienko2021-02-071-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | In case MMC has MBR system and fastboot writes GPT, MMC is still recognized as MBR. Invoke part_init() to purge cached data and update information about partition table type. Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
| * | fastboot: add command to select the eMMC boot configurationPatrick Delaunay2021-02-074-0/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add command oem bootbus which executes the command ``mmc bootbus <id> <arg>`` on the current fastboot mmc device (<i> = CONFIG_FASTBOOT_FLASH_MMC_DEV) to set the eMMC boot configuration on first update, with <arg> = boot_bus_width reset_boot_bus_width boot_mode $> fastboot oem bootbus:<boot_bus_width> <reset_boot_bus_width> <boot_mode> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| * | fastboot: add command to select the default emmc hwpart for bootPatrick Delaunay2021-02-074-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add fastboot command oem partconf which executes the command ``mmc partconf <id> <arg> 0`` on the current <id> mmc device to configure the eMMC boot partition with <arg>: boot_ack boot_partition, so the command is: $> fastboot oem partconf:<boot_ack> <boot_partition> The partition_access argument is forced to 0 (userdata) Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> [lukma - Kconfig adjustments after merging this patch]
| * | fastboot: mmc: extend flash/erase for both emmc hwpart 1 and 2Patrick Delaunay2021-02-075-27/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the code and the configs for eMMC boot and userdata partitions acces - FASTBOOT_MMC_BOOT_SUPPORT: boot partition 1 and 2 (erase/write) - FASTBOOT_MMC_BOOT1_NAME: boot partition 1, default name="mmc0boot0" - FASTBOOT_MMC_BOOT2_NAME: boot partition 2, default name="mmc0boot1" This patch also removes the unnecessary dependency with ARCH_MEDIATEK and EFI_PARTITION. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| * | fastboot: mmc: Add CONFIG_FASTBOOT_MMC_USER_SUPPORTPatrick Delaunay2021-02-075-8/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Split userdata and boot partition support for eMMC update and correct the description (update is supported). The new configuration CONFIG_FASTBOOT_MMC_USER_SUPPORT allows to activate support of userdata partition update, based on target name=CONFIG_FASTBOOT_MMC_USER_NAME This patch also removes the unnecessary dependency with ARCH_MEDIATEK and EFI_PARTITION. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| * | fastboot: Implement generic fastboot_set_reboot_flagRoman Kovalivskyi2021-02-071-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is possible to implement fastboot_set_reboot_flag in a generic way if BCB commands are turned on for a target. Using bcb_set_reboot_reason allows to do this by simply passing string with correct reboot reason that should be handled during next boot process. If BCB are turned off, then bcb_set_reboot_reason would simply return error, so it won't introduce any new behaviour for such targets. Signed-off-by: Roman Kovalivskyi <roman.kovalivskyi@globallogic.com>
| * | Revert "fastboot: Add default fastboot_set_reboot_flag implementation"Roman Kovalivskyi2021-02-074-65/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 0ebf9842e56c5b8cb7cb1f990bb452cc14af6225. Current generic implementation of fastboot_set_reboot_flag is somewhat messy and requires some additional configuration option to be enabled besides CMD_BCB, so it reverts that implementtion in order to bring a new cleaner one. Next commit introduces new generic implementation of fastboot_set_reboot_flag. Signed-off-by: Roman Kovalivskyi <roman.kovalivskyi@globallogic.com>
| * | dfu: dfu_sf: use correct print codeHeinrich Schuchardt2021-02-071-1/+1
| | | | | | | | | | | | | | | | | | For printing unsigned int %u has to be used. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* | | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86Tom Rini2021-02-068-76/+328
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | - introduces some standard sysinfo options as a source, e.g. to read strapping pins to determine the board revision - allows the U-Boot version number to be included - allows the version number to be provided programmatically, e.g. to support the build system adding information after U-Boot is built
| * | smbios: Allow a few values to come from sysinfoSimon Glass2021-02-062-3/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While static configuration is useful it cannot cover every case. Sometimes board revisions are encoded in resistor straps and must be read at runtime. The easiest way to provide this information is via sysinfo, since the board can then provide a driver to read whatever is needed. Add some standard sysinfo options for this, and use them to obtain the required information. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: coral: Add sysinfo opsSimon Glass2021-02-061-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These ops are missing at present which is not permitted. Add an empty operation struct. Note: If the uclass requires operations then the drivers should provide them. Otherwise, checking for missing operations must be done in every uclass operation, so it adds to code size. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | sysinfo: Move #ifdef so that operations are always definedSimon Glass2021-02-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present the struct is not available unless SYSINFO is enabled. This is annoying since code it is not possible to use compile-time checks like CONFIG_IS_ENABLED(SYSINFO) with this header. Fix it by moving the #ifdef. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit (git 2.34.1) at 2025-09-26 19:26:37 +0000