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* arm: renesas: Add config option for R8A774C0 SoCLad Prabhakar2020-10-201-0/+3
| | | | | | | Add config support for RZ/G2E (a.k.a R8A774C0) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
* arm: renesas: Add config option for R8A774E1 SoCBiju Das2020-10-201-0/+3
| | | | | | | Add config support for RZ/G2H(a.k.a R8A774E1) SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
* arm: renesas: Add config option for R8A774B1 SoCBiju Das2020-10-201-1/+4
| | | | | | | | | Add config support for RZ/G2N(a.k.a R8A774B1) SoC. Also fixed the alignment issue on R8A774A1 config. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
* clk: renesas: r8a774a1-cpg-mssr: Add R8A774A1 RPC clockBiju Das2020-10-201-0/+4
| | | | | | | Add RPC entry into the R8A774A1 clock driver tables. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
* spi: renesas_rpc_spi: Add R-Car Gen3 and RZ/G2 fallback compatibility stringBiju Das2020-10-201-1/+2
| | | | | | | | Add fallback compatibility string for R-Car Gen3 and RZ/G2. Also sorted the compatible string as per SoC ID. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
* Merge tag 'u-boot-atmel-2021.01-b' of ↵Tom Rini2020-10-1914-206/+729
|\ | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-atmel Second set of u-boot-atmel features for 2021.01 cycle: This feature set brings the rework of the clock tree for sam9x60 SoC. This makes the clock tree fully compatible with Common Clock Framework and allows full clock configuration in U-Boot. This means that the sam9x60 boards can boot now using U-Boot. This also includes the definitions for sam9x60 SiPs and a divisor fix for the clock on sama7g5 SoC.
| * clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristicsEugen Hristev2020-10-191-2/+2
| | | | | | | | | | | | | | | | | | This SoC has the 5th divisor for the mck0 master clock. Adapt the characteristics accordingly. Reported-by: Mihai Sain <mihai.sain@microchip.com> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * clk: at91: clk-master: add 5th divisor for mck masterEugen Hristev2020-10-192-2/+2
| | | | | | | | | | | | | | | | | | | | | | clk-master can have 5 divisors with a field width of 3 bits on some products. Change the mask and number of divisors accordingly. Reported-by: Mihai Sain <mihai.sain@microchip.com> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * ARM: at91: Add chip ID for SAM9X60 SiPNicolas Ferre2020-10-192-0/+9
| | | | | | | | | | | | SAM9X60 SiP (System in Package) are added for SoC identification. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
| * ARM: dts: sam9x60: use alphabetical orderClaudiu Beznea2020-10-191-14/+13
| | | | | | | | | | | | Use alphabetical order for entries in sam9x60ek-u-boot.dtsi Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * configs: sam9x60ek: update defconfigs for CCFClaudiu Beznea2020-10-193-3/+9
| | | | | | | | | | | | | | Update defconfigs for using common clock framework compatible clocks. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * ARM: dts: sam9x60: use CCF compatibles for PMCClaudiu Beznea2020-10-193-164/+33
| | | | | | | | | | | | | | Use CCF compatible for PMC. With this, the board/SoC will be able to boot. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * ARM: dts: sam9x60: use slow clock CCF compatible bindingsClaudiu Beznea2020-10-192-47/+20
| | | | | | | | | | | | | | | | Use slow clock CCF compatible DT bindings. This will not break the above functionality as the SoC is not booting with current PMC bindings. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * ARM: dts: sam9x60: use u-boot,dm-pre-relocClaudiu Beznea2020-10-191-0/+8
| | | | | | | | | | | | Use u-boot,dm-pre-reloc for slow xtal and main xtal. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * ARM: dts: sam9x60ek: add clock frequencies to board fileClaudiu Beznea2020-10-192-2/+10
| | | | | | | | | | | | | | Slow Xtal and Main Xtal are board specific. Add their proper frequency to board file. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * clk: at91: sam9x60: add support compatible with CCFClaudiu Beznea2020-10-192-0/+650
| | | | | | | | | | | | Add SAM9X60 clock support compatible with CCF. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * board: atmel: sam9x60ek: add SYS_MALLOC_F_LEN to SYS_INIT_SP_ADDRClaudiu Beznea2020-10-191-1/+2
| | | | | | | | | | | | | | | | Heap base address is computed based on SYS_INIT_SP_ADDR by subtracting the SYS_MALLOC_F_LEN value in board_init_f_init_reserve(). Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
* | Merge tag 'video-for-2021.01' of ↵Tom Rini2020-10-18136-138/+283
|\ \ | |/ |/| | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-video - add dw-mipi-dsi phy timings and Tx escape clock configuration - fix pwm backlight duty cycle calculation - migrate CONFIG_VIDEO_BMP_* and CONFIG_BMP_* to Kconfig
| * configs: migrate CONFIG_BMP_16/24/32BPP to defconfigsPatrick Delaunay2020-10-18103-63/+122
| | | | | | | | | | | | | | | | Done with: ./tools/moveconfig.py BMP_16BPP BMP_24BPP BMP_32BPP Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * configs: migrate CONFIG_VIDEO_BMP_RLE8 to defconfigsPatrick Delaunay2020-10-18119-43/+88
| | | | | | | | | | | | | | | | Done with: ./tools/moveconfig.py VIDEO_BMP_RLE8 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * configs: migrate CONFIG_VIDEO_BMP_GZIP to defconfigsPatrick Delaunay2020-10-1823-14/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Done with: ./tools/moveconfig.py VIDEO_BMP_GZIP The 3 suspicious migration because CMD_BMP and SPLASH_SCREEN are not activated in these defconfigs: - trats_defconfig - s5pc210_universal_defconfig - trats2_defconfig Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * video: backlight: fix pwm's duty cycle calculationDario Binacchi2020-10-182-7/+7
| | | | | | | | | | | | | | | | For levels equal to the maximum value, the duty cycle must be equal to the period. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
| * video: backlight: fix pwm data structure descriptionDario Binacchi2020-10-181-1/+1
| | | | | | | | | | | | | | The description of the 'max_level' field was incorrectly assigned to the 'min_level' field. Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * video: dw-mipi-dsi: permit configuring the escape clock rateNeil Armstrong2020-10-182-4/+17
| | | | | | | | | | | | | | | | | | | | | | | | The Amlogic D-PHY in the Amlogic AXG SoC Family does support a frequency higher than 10MHz for the TX Escape Clock, thus make the target rate configurable. This is based on the Linux commit [1] and adapted to the U-Boot driver. [1] a328ca7e4af3 ("drm/bridge: dw-mipi-dsi: permit configuring the escape clock rate") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * video: dw-mipi-dsi: driver-specific configuration of phy timingsNeil Armstrong2020-10-182-6/+27
|/ | | | | | | | | | | | | | | | The timing values for dw-dsi are often dependent on the used display and according to Philippe Cornu will most likely also depend on the used phy technology in the soc-specific implementation. To solve this and allow specific implementations to define them as needed add a new get_timing callback to phy_ops and call this from the dphy_timing function to retrieve the necessary values for the specific mode. This is based on the Linux commit [1] and adapted to the U-Boot driver. [1] 25ed8aeb9c39 ("drm/bridge/synopsys: dsi: driver-specific configuration of phy timings") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* test: Fix sandbox tests failing to buildSean Anderson2020-10-172-2/+2
| | | | | | | | syslog_test.h is in test/log/, not include/ Fixes: 52d3df7fef ("log: Allow LOG_DEBUG to always enable log output") Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini2020-10-168-7/+93
|\ | | | | | | | | | | - Fix Octeon SPI driver for Octeon TX2 - Fix and enhance Octeon watchdog driver - Misc minor enhancements to Octeon TX/TX2
| * arm: octeontx: Add CMD_WDTStefan Roese2020-10-164-0/+4
| | | | | | | | | | | | | | | | | | Enable WDT command for Octeon TX/TX2 boards. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Suneel Garapati <sgarapati@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
| * watchdog: octeontx_wdt: Add support for start and stopSuneel Garapati2020-10-161-5/+83
| | | | | | | | | | | | | | | | | | | | | | | | This patch enhances the Octeon TX/TX2 watchdog driver to fully enable the WDT. With this changes, the "wdt" command is now also supported on these platforms. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Suneel Garapati <sgarapati@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
| * arm: octeontx: Select CLKStefan Roese2020-10-161-0/+2
| | | | | | | | | | | | | | | | | | | | Clock support is needed for all Octeon TX/TX2 boards. This patch selects CONFIG_CLK so that it is available. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Suneel Garapati <sgarapati@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
| * mmc: octeontx_hsmmc.c: Remove test debug messageStefan Roese2020-10-161-1/+0
| | | | | | | | | | | | | | | | | | | | Remove a left-over debug test message from the Octeon TX / TX2 MMC driver. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Suneel Garapati <sgarapati@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
| * spi: octeon_spi: Use a fixed 100MHz input clock on Octeon TX2Stefan Roese2020-10-161-1/+4
| | | | | | | | | | | | | | | | | | | | | | Octeon TX2 sets the TB100_EN bit in the config register. We need to use a fixed 100MHz clock for this as well to work properly. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Suneel Garapati <sgarapati@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Jagan Teki <jagan@amarulasolutions.com>
* | Merge branch '2020-10-15-further-cleanup_dev_xxx'Tom Rini2020-10-1626-94/+74
|\ \ | |/ |/| | | - Bring in the next round of dev_xxx cleanup patches.
| * dm: Don't undefine dev_xxx macrosSean Anderson2020-10-161-20/+0
| | | | | | | | | | | | | | | | Now that linux/compat.h does not define these macros, we do not need to undefine them. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * linux/compat.h: Remove redefinition of dev_xxx macrosSean Anderson2020-10-161-28/+0
| | | | | | | | | | | | | | All users of these functions now include dm/device_compat.h directly. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * usb: dwc3: Include device_compat.h in dwc3-octeon-glue.cTom Rini2020-10-161-0/+1
| | | | | | | | | | | | Necessary for dev_xxx. Signed-off-by: Tom Rini <trini@konsulko.com>
| * clk: at91: Include device_compat.h in compat.cTom Rini2020-10-161-0/+1
| | | | | | | | | | | | Necessary for dev_xxx. Signed-off-by: Tom Rini <trini@konsulko.com>
| * arm: fsl-layerscape: Include device_compat.h in soc.cTom Rini2020-10-161-0/+1
| | | | | | | | | | | | Necessary for dev_xxx. Signed-off-by: Tom Rini <trini@konsulko.com>
| * usb: musb-new: mt85xx: Fix not calling dev_err with a deviceSean Anderson2020-10-161-3/+4
| | | | | | | | | | | | | | This driver doesn't use DM (in the correct places), so we use a device and not a udevice. We also need to include device_compat.h Signed-off-by: Sean Anderson <seanga2@gmail.com>
| * usb: musb-new: Include device_compat.hSean Anderson2020-10-165-1/+11
| | | | | | | | | | | | | | This was included, but was ifdef'd out. We also need dm.h for struct udevice. Signed-off-by: Sean Anderson <seanga2@gmail.com>
| * usb: xhci: Include device_compat.hSean Anderson2020-10-162-5/+7
| | | | | | | | | | | | This header is necessary for the dev_xxx macros. Signed-off-by: Sean Anderson <seanga2@gmail.com>
| * timer: Include device_compat.hSean Anderson2020-10-161-2/+3
| | | | | | | | | | | | | | Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * tee: optee: Include device_compat.hSean Anderson2020-10-161-0/+1
| | | | | | | | | | | | | | Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * spi: fsl_qspi: Include device_compat.hSean Anderson2020-10-161-4/+5
| | | | | | | | | | | | Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
| * spi: nxp_fspi: Include device_compat.hSean Anderson2020-10-161-3/+4
| | | | | | | | | | | | Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
| * ram: imxrt: Include device_compat.hSean Anderson2020-10-151-0/+1
| | | | | | | | | | | | Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
| * phy: Include device_compat.hSean Anderson2020-10-151-1/+1
| | | | | | | | | | | | Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
| * net: ldpaa_eth: Include device_compat.hSean Anderson2020-10-151-7/+7
| | | | | | | | | | | | Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
| * mtd: mxs_nand: Fix not calling dev_xxx with a deviceSean Anderson2020-10-151-13/+15
| | | | | | | | | | | | This includes device_compat.h, and fixes several calls to dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
| * firmware: scmi: Include device_compat.hSean Anderson2020-10-153-0/+3
| | | | | | | | | | | | | | This header is necessary for the dev_xxx macros. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
generated by cgit (git 2.34.1) at 2024-09-17 21:11:17 +0000