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| * | spi: nxp_fspi: Fix error reportingAdam Ford2021-02-261-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the i.MX8M Mini, ret = clk_set_rate() sets ret to the value of the rate the clock was able to set. When checking for errors, it only checks that it is not NULL. Since positive numbers are not errors, only check for negative numbers when handling errors. Fixes: 383fded70c4f ("spi: nxp_fspi: new driver for the FlexSPI controller") Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | mtd: spi-nor-ids: Add support of flash protection to w25q128Su Baocheng2021-02-261-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The NOR flash w25q128 denoted by JEDEC ID 0xef4018 actually represents various models. From Winbond's website, I could only find 3 types of them: W25Q128JV-IQ/JQ datasheet:https://www.winbond.com/resource-files/ w25q128jv%20revg%2004082019%20plus.pdf W25Q128FV (SPI Mode) datasheet: https://www.winbond.com/resource-files/ w25q128fv%20rev.m%2005132016%20kms.pdf W25Q128BV datesheet: https://www.winbond.com/resource-files/ w25q128bv_revh_100313_wo_automotive.pdf According to the datasheets, all of these 3 types support BP(0,1,2) and TB bits in the status register (SR), so it could reuse the flash protection logic for ST Micro. So it should be safe to add the SPI_NOR_HAS_LOCK and SPI_NOR_HAS_TB flags to the w25q128 entry of spi_nor_ids table. Signed-off-by: Su Baocheng <baocheng.su@siemens.com> [jagan: remove comments in spi-nor-ids.c] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | mtd: spi-nor.h: Change spaces to tabsBin Meng2021-02-261-10/+10
| | | | | | | | | | | | | | | | | | | | | U-Boot coding convention prefers tabs over spaces. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | mtd: spi-nor-ids: Add Gigadevice GD25LQ64CAlper Nebi Yasak2021-02-261-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add GD25LQ24C 64Mbit chip to spi-nor id table. This chip is used on rk3399-gru-kevin: => sf probe SF: Detected gd25lq64c with page size 256 Bytes, erase size 4 KiB, total 8 MiB => sf erase 0x600000 0x200000 SF: 2097152 bytes @ 0x600000 Erased: OK => sf test 0x700000 0x1000 SPI flash test: 0 erase: 52 ticks, 76 KiB/s 0.608 Mbps 1 check: 5 ticks, 800 KiB/s 6.400 Mbps 2 write: 14 ticks, 285 KiB/s 2.280 Mbps 3 read: 3 ticks, 1333 KiB/s 10.664 Mbps Test passed 0 erase: 52 ticks, 76 KiB/s 0.608 Mbps 1 check: 5 ticks, 800 KiB/s 6.400 Mbps 2 write: 14 ticks, 285 KiB/s 2.280 Mbps 3 read: 3 ticks, 1333 KiB/s 10.664 Mbps The values are the same as in Linux, except adjusted for the U-Boot definition of INFO(). Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | spi: imx: Implement set_speedMarek Vasut2021-02-261-1/+4
| |/ | | | | | | | | | | | | | | | | The set_speed() callback should configure the bus speed, make it so. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | Merge tag 'u-boot-stm32-20210226' of ↵Tom Rini2021-02-264-80/+13
|\ \ | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-stm - Add USB host boot support in stm32mp1 config - Enable uefi related commands for STMicroelectronics STM32MP15 boards - Remove duplicate uart nodes in stm32mp15 device tree
| * | configs: stm32mp1: enable uefi related commandsIlias Apalodimas2021-02-262-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The board can boot with UEFI. With the latest changes in U-Boot's EFI subsystem we also have support for EFI runtime variables, without SetVariable support. We can also store the EFI variables in a file on the ESP partition and preserve them across reboots. The env and efidebug commands are missing in order to configure EFI variables and the efibootmgr though. Since U-Boot's default config enables other EFI related commands (e.g bootefi), let's add the env related and efidebug commands and allow users to do that Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| * | arm: dts: stm32mp15: remove duplicate uart nodesPatrick Delaunay2021-02-261-80/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove duplicated uart nodes introduced with commit 62f95af92a3f ("ARM: dts: stm32mp1: DT alignment with Linux kernel v5.9-rc4"), because the uart nodes wasn't correctly ordered in alphabetic order. Only cosmetic: the generated device tree don't change. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
| * | ARM: stm32: Add USB host boot supportMarek Vasut2021-02-261-0/+7
| |/ | | | | | | | | | | | | | | | | | | Add support for booting from USB pen drive, since USB host port is available on the STM32MP1. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
* | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini2021-02-2622-53/+123
|\ \ | | | | | | | | | | | | | | | | | | | | | - turris_mox: Enhancements, mostlly defconfig changes (Pali) - pci-aardvark: Set Max Payload Size and Max Read Request Size to 512 bytes (Pali) - pci_mvebu: Minor cleanup and refactoring (Marek) - Upgrade A38x DDR3 training to version 14.0.0 (Marek)
| * | ddr: marvell: a38x: fix comment in conditional macroMarek Behún2021-02-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code was processed with unifdef utility to omit portions not relevant to A38x and DDR3. This removes usage of many macros, including A70X0, A80X0 and A3900. It seems that the unifdef utility did not remove the macros from #else comment. Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | ddr: marvell: a38x: bump version to 14.0.0Marek Behún2021-02-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bump version of a38x DDR3 trianing to version 14.0.0 to reflect the version in the mv-ddr-devel branch of upstream repository https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git. There is a new version numbering system, where after 18.12.0 came 1.0.0, 2.0.0, and so on until 14.0.0. So 14.0.0 is newer than 18.12.0. Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | ddr: marvell: a38x: enum mv_ddr_twin_die: change orderheaterC2021-02-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 56db5d1464b44df10a02b99e615ebd6f6a35c428 upstream. @pali suggested this change In commit 6285efb ("mv_ddr: add support for twin-die combined memory device") was added support for twin-die combined memory device and default value for explicitly uninitialized structure members is zero, s also twin_die_combined is initialized to zero. Which means COMBINED value. As prior this commit there was no support for twin-die combined memory device, default value for twin_die_combined should be NOT_COMBINED. This change change order of enum mv_ddr_twin_die to ensure that NOT_COMBINED has value zero. Signed-off-by: heaterC <airyguy@gmx.de> Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | ddr: marvell: a38x: import code change from upstreamMarek Behún2021-02-261-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 2bdd12dd68b1f8e27a03a3443ae49a09a14c18e4 upstream. The commit mentioned above changes non-DDR3 stuff in upstream, but it also changes code in ddr3_training.c. Import this change to remain consistent with upstream. Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | ddr: marvell: a38x: fix memory cs size functionMoti Buskila2021-02-262-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit c8b301463d508c807a33f7b7eaea98bbda4aa35e upstream. The funtion returnd cs size in byte instead of MB, that cause calculation error since the caller was expected to get u32 and when he got above 4G it refers it as 0. The fix was to get the cs memory size from function as in MB and then multiply it by 1MB. Signed-off-by: Moti Buskila <motib@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | ddr: marvell: a38x: import header change from upstreamMarek Behún2021-02-261-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit d653b305d0b3da9727c49124683f1a6d95d5c9a5 upstream. The commit mentioned above changes non-DDR3 stuff in upstream, but it also changes header ddr_topology_def.h. Import this header change to remain consistent with upstream. Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | ddr: marvell: a38x: disable WL phase correction stage in case of bus_width=16bitMoti Buskila2021-02-261-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 20c89a28548cdab11f88d2ec8936344af0686a1e upstream. WL phase correcion stage is failing while using bus_width of 16bit, not to be fix this stage is un-necessary when working with bus_width of 16 bit. Signed-off-by: Moti Buskila <motib@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | ddr: marvell: a38x: add support for twin-die combined memory deviceMoti Buskila2021-02-269-1/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 6285efb8a118940877522c4c07bd7c64569b4f5f upstream. the twin-die combined memory device should be treatened as X8 device and not as X16 one Signed-off-by: Moti Buskila <motib@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> [ - the default value for twin_die_combined is set to NOT_COMBINED for all boards, as this was default behaviour prior this change ] Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | ddr: marvell: a38x: add 16Gbit memory devices supportMoti Buskila2021-02-262-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | commit 994509eb4fe6771d92cd06314c37895098ac48fa upstream. Signed-off-by: Moti Buskila <motib@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | ddr: marvell: a38x: allow board specific ODT configurationBaruch Siach2021-02-262-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 2d3b9437cf38c06c4330e0de07f29476197f5e04 upstream. The ODT enable heuristic based on active chip-selects is not always correct. Some board might use two chip-selects, but have only one ODT line connected. Allow board specific mv_ddr_topology_map to directly set the ODT configuration register value. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Moti Buskila <motib@marvell.com> Reviewed-by: Nadav Haklai <Nadav.Haklai@cavium.com> Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com> Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | ddr: marvell: a38x: import header change from upstreamMarek Behún2021-02-261-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 3908e20c6c520339e9bddb566823ae5e065d5218 upstream. The commit mentioned above changes non-DDR3 stuff in upstream, but it also changes header ddr_topology_def.h. Import this header change to remain consistent with upstream. Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | ddr: marvell: a38x: fix memory size calculation using 32bit bus widthMoti Buskila2021-02-263-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit ab9240402a70cc02496683971779e75eff410ab4 upstream. - function mv_ddr_spd_die_capacity_user_get() has a bug, since it insert a user memory enum to it, instead of SPD memory enum (which are different) - fix: remove mv_ddr_spd_die_capacity_user_get() function. - memory size with 64 and 32 bit already calculated correctly at mv_ddr_mem_sz_per_cs_get() function Signed-off-by: Moti Buskila <motib@marvell.com> Reviewed-by: Stefan Chulski <Stefan.Chulski@cavium.com> Reviewed-by: Alex Leibovich <alexl@marvell.com> Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com> Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | ddr: marvell: a38x: fix 32bitMoti Buskila2021-02-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 0b5adedd4ced9b8f528faad1957d4d69e95759ef upstream. Signed-off-by: Moti Buskila <motib@marvell.com> Reviewed-by: Alex Leibovich <alexl@marvell.com> Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com> Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | ddr: marvell: a38x: import header change from upstreamMarek Behún2021-02-261-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 6c705ebc0d70f67ed7cae83ad1978c3305ef25be upstream. The commit mentioned above changes non-DDR3 stuff in upstream, but it also changes header mv_ddr_topology.h. Import this header change to remain consistent with upstream. Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | ddr: marvell: a38x: add ddr 32bit ECC supportAlex Leibovich2021-02-263-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 61a8910998d7b553e80f600ebe8147a8b98f0945 upstream. Required changes made for 32bit ddr support. An update is made to the topology map, according to bus_act_mask, set in the dram_port.c Signed-off-by: Alex Leibovich <alexl@marvell.com> Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com> Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | ddr: marvell: a38x: add ddr32 supportAlex Leibovich2021-02-261-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 32800667b375ebd1f82120da0f3479b1cf52d96d upstream. Required changes made for 32bit ddr support. An update is made to the topology map, according to bus_act_mask, set in the dram_port.c Signed-off-by: Alex Leibovich <alexl@marvell.com> Reviewed-by: Nadav Haklai <Nadav.Haklai@cavium.com> Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com> Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | ddr: marvell: a38x: import header change from upstreamMarek Behún2021-02-261-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit a165037ec26f301be75e1fabc263643683e85255 upstream. The commit mentioned above changes non-DDR3 stuff in upstream, but it also changes header ddr_topology_def.h. Import this header change to remain consistent with upstream. Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | ddr: marvell: a38x: fix write leveling suplementary algoMoti Buskila2021-02-261-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit ce62bef8fac559e27245259882e45f19cdc293ad upstream. - fix JIRA A7K8K-5056 - remove TEST_PATTERN write at the load patern stage earlier to WL SUP stage - the WL SUP stage already writes this pattern to the memory, if the pattern exist at the memory then the algorithm will fail, since it think that there are no phase to correct Signed-off-by: Moti Buskila <motib@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
| * | ARM: dts: armada-385-turris-omnia: rename node in -u-boot.dtsi fileMarek Behún2021-02-261-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPI NOR flash node name in main device tree for Turris Omnia is called `spi-nor@0`. Rename node spi-flash@0 in Turris Omnia's -u-boot.dtsi file to spi-nor@0 so that U-Boot does not try to probe the same SPI NOR device multiple times. Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Pali Rohár <pali@kernel.org>
| * | pci: pci_mvebu: set local dev to number 1Marek Behún2021-02-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux displays the real PCIe card connected to a mvebu PCIe slot as device 0, not 1. This is done by setting local dev number to 1, so that the local "Marvell Memory controller" device is on address 1. Let's do it also in U-Boot. With this commit the pci command in U-Boot prints something like: => pci Scanning PCI devices on bus 0 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 00.00.00 0x168c 0x003c Network controller 0x80 Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de>
| * | pci: pci_mvebu: refactor validation of addresses for config accessMarek Behún2021-02-261-28/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor validation of bdf parameter in mvebu_pcie_read/write_config functions. We can simplify the code by putting the validation into separate function. Also there are always only two devices visible on local bus: * on slot configured by function mvebu_pcie_set_local_dev_nr() (by default this register is set to 0) there is a "Marvell Memory controller", which isn't useful in root complex mode, * on all other slots the real PCIe card connected to the PCIe slot. We can simplify the code even more by simply allowing access only to the real PCIe card. Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de>
| * | pci: pci_mvebu: debug rd/wr config as other drivers doMarek Behún2021-02-261-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Other drivers (aardvark, intel_fpga) print "(addr,size,val)" when debugging is enabled. Print size for pci_mvebu as well. Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de>
| * | pci: pci_mvebu: cosmetic fixMarek Behún2021-02-261-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Write bdf address in a same way in mvebu_pcie_read/write_config. Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de>
| * | pci: pci_mvebu: use dev_seq instead of static variableMarek Behún2021-02-261-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI uclass maps PCI bus numbers to the seq member of struct udevice. Use dev_seq(dev) as the bus number in mvebu_pcie_probe instead of an incrementing a static variable. Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de>
| * | arm: mvebu: turris_mox: Enable NVMe supportMarek Behún2021-02-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | NVMe drives can be connected to Turris MOX via MOX B and MOX G extensions. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
| * | arm: mvebu: turris_mox: Enable CONFIG_USB_XHCI_PCIPali Rohár2021-02-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | USB devices can be connected to Turris MOX also via MOX F extension which contains VL805 PCIe based USB 3.0 controller. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
| * | arm: mvebu: turris_mox: Enable CONFIG_PCI_PNPPali Rohár2021-02-261-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | PCIe devices do not work in U-Boot without proper initialization and configuration of PCI config space like the PCI_BASE_ADDRESS_0 register. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
| * | arm: a37xx: pci: Set Max Payload Size and Max Read Request Size to 512 bytesPali Rohár2021-02-261-0/+8
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix usage of VL805 XHCI PCIe controller when it is connected via PCIe to Armada 3720 SOC. Without this U-Boot crashes when trying to access enumerated USB devices connected to this XHCI PCIe controller. This should be done according to the PCIe Link Initialization sequence, as defined in Marvell Armada 3720 Functional Specification. Linux has this code too. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
* | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-samsungTom Rini2021-02-2612-162/+29
|\ \
| * | samsung: origen: change maintainerMinkyu Kang2021-02-231-1/+1
| | | | | | | | | | | | Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | samsung: espresso7420: change maintainerMinkyu Kang2021-02-231-1/+1
| | | | | | | | | | | | Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | samsung: smdkv310: change maintainerMinkyu Kang2021-02-231-1/+1
| | | | | | | | | | | | | | | | | | | | | change maintainer to Jaehoon Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | samsung: smdk5420: change maintainerMinkyu Kang2021-02-231-1/+1
| | | | | | | | | | | | | | | | | | | | | change maintainer to Jaehoon Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | samsung: smdk5250: change maintainerMinkyu Kang2021-02-231-2/+2
| | | | | | | | | | | | | | | | | | | | | change maintainer to Jaehoon Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | samsung: goni: change maintainerMinkyu Kang2021-02-231-1/+1
| | | | | | | | | | | | | | | | | | | | | change maintainer to Jaehoon Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | serial: s5p: Allow independent selectionMark Kettenis2021-02-232-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently support for the Samsung serial port driver is part of CONFIG_S5P which controls selection of several drivers for the S5P family. Give it its own config option such that we can use it on other SoCs as well. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Patrick Wildt <patrick@blueri.se> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | power: pmic: remove pmic_max8997/8 filesJaehoon Chung2021-02-233-141/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove pmic_max8997/8 files about no-DM. There are already existed max8997/8 as driver-model. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | board: samsung: covert to driver model about power_key_pressedJaehoon Chung2021-02-231-13/+14
| | | | | | | | | | | | | | | | | | | | | | | | Convert to driver model about power_key_pressed. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscvTom Rini2021-02-262-0/+3
|\ \ \ | |_|/ |/| |
| * | riscv: k210: Enable QSPI for spi3Sean Anderson2021-02-251-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | This device has four IOs connected to the SPI flash. Add the appropriate bindings. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Leo Liang <ycliang@andestech.com>
generated by cgit (git 2.34.1) at 2025-10-02 20:15:18 +0000