diff options
Diffstat (limited to 'include')
171 files changed, 3478 insertions, 1705 deletions
diff --git a/include/ahci.h b/include/ahci.h index 33171b7ffd..cc36d81f98 100644 --- a/include/ahci.h +++ b/include/ahci.h @@ -234,18 +234,18 @@ int ahci_init(void __iomem *base); int ahci_reset(void __iomem *base); /** - * achi_init_one_dm() - set up a single AHCI port + * ahci_init_one_dm() - set up a single AHCI port * * @dev: Controller to init */ -int achi_init_one_dm(struct udevice *dev); +int ahci_init_one_dm(struct udevice *dev); /** - * achi_start_ports_dm() - start all AHCI ports for a controller + * ahci_start_ports_dm() - start all AHCI ports for a controller * * @dev: Controller containing ports to start */ -int achi_start_ports_dm(struct udevice *dev); +int ahci_start_ports_dm(struct udevice *dev); /** * ahci_init_dm() - init AHCI for a controller, finding all ports diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 944f58195c..73e036d6fd 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -36,7 +36,7 @@ typedef struct global_data { #if defined(CONFIG_LCD) || defined(CONFIG_VIDEO) unsigned long fb_base; /* Base address of framebuffer mem */ #endif -#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) +#if defined(CONFIG_POST) unsigned long post_log_word; /* Record POST activities */ unsigned long post_log_res; /* success of POST test */ unsigned long post_init_f_time; /* When post_init_f started */ @@ -114,6 +114,11 @@ typedef struct global_data { struct bootstage_data *bootstage; /* Bootstage information */ struct bootstage_data *new_bootstage; /* Relocated bootstage info */ #endif +#ifdef CONFIG_LOG + int log_drop_count; /* Number of dropped log messages */ + int default_log_level; /* For devices with no filters */ + struct list_head log_head; /* List of struct log_device */ +#endif } gd_t; #endif @@ -141,5 +146,6 @@ typedef struct global_data { #define GD_FLG_RECORD 0x01000 /* Record console */ #define GD_FLG_ENV_DEFAULT 0x02000 /* Default variable flag */ #define GD_FLG_SPL_EARLY_INIT 0x04000 /* Early SPL init is done */ +#define GD_FLG_LOG_READY 0x08000 /* Log system is ready for use */ #endif /* __ASM_GENERIC_GBL_DATA_H */ diff --git a/include/binman_sym.h b/include/binman_sym.h new file mode 100644 index 0000000000..87d03d5294 --- /dev/null +++ b/include/binman_sym.h @@ -0,0 +1,93 @@ +/* + * Symbol access for symbols set up by binman as part of the build. + * + * This allows C code to access the position of a particular part of the image + * assembled by binman. + * + * Copyright (c) 2017 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __BINMAN_SYM_H +#define __BINMAN_SYM_H + +#define BINMAN_SYM_MISSING (-1UL) + +#ifdef CONFIG_BINMAN + +/** + * binman_symname() - Internal fnuction to get a binman symbol name + * + * @entry_name: Name of the entry to look for (e.g. 'u_boot_spl') + * @_prop_name: Property value to get from that entry (e.g. 'pos') + * @returns name of the symbol for that entry and property + */ +#define binman_symname(_entry_name, _prop_name) \ + _binman_ ## _entry_name ## _prop_ ## _prop_name + +/** + * binman_sym_declare() - Declare a symbol that will be used at run-time + * + * @_type: Type f the symbol (e.g. unsigned long) + * @entry_name: Name of the entry to look for (e.g. 'u_boot_spl') + * @_prop_name: Property value to get from that entry (e.g. 'pos') + */ +#define binman_sym_declare(_type, _entry_name, _prop_name) \ + _type binman_symname(_entry_name, _prop_name) \ + __attribute__((aligned(4), unused, section(".binman_sym"))) + +/** + * binman_sym_extern() - Declare a extern symbol that will be used at run-time + * + * @_type: Type f the symbol (e.g. unsigned long) + * @entry_name: Name of the entry to look for (e.g. 'u_boot_spl') + * @_prop_name: Property value to get from that entry (e.g. 'pos') + */ +#define binman_sym_extern(_type, _entry_name, _prop_name) \ + extern _type binman_symname(_entry_name, _prop_name) \ + __attribute__((aligned(4), unused, section(".binman_sym"))) + +/** + * binman_sym_declare_optional() - Declare an optional symbol + * + * If this symbol cannot be provided by binman, an error will not be generated. + * Instead the image will be assigned the value BINMAN_SYM_MISSING. + * + * @_type: Type f the symbol (e.g. unsigned long) + * @entry_name: Name of the entry to look for (e.g. 'u_boot_spl') + * @_prop_name: Property value to get from that entry (e.g. 'pos') + */ +#define binman_sym_declare_optional(_type, _entry_name, _prop_name) \ + _type binman_symname(_entry_name, _prop_name) \ + __attribute__((aligned(4), weak, unused, \ + section(".binman_sym"))) + +/** + * binman_sym() - Access a previously declared symbol + * + * This is used to get the value of a symbol. E.g.: + * + * ulong address = binman_sym(ulong, u_boot_spl, pos); + * + * @_type: Type f the symbol (e.g. unsigned long) + * @entry_name: Name of the entry to look for (e.g. 'u_boot_spl') + * @_prop_name: Property value to get from that entry (e.g. 'pos') + * @returns value of that property (filled in by binman) + */ +#define binman_sym(_type, _entry_name, _prop_name) \ + (*(_type *)&binman_symname(_entry_name, _prop_name)) + +#else /* !BINMAN */ + +#define binman_sym_declare(_type, _entry_name, _prop_name) + +#define binman_sym_declare_optional(_type, _entry_name, _prop_name) + +#define binman_sym_extern(_type, _entry_name, _prop_name) + +#define binman_sym(_type, _entry_name, _prop_name) BINMAN_SYM_MISSING + +#endif /* BINMAN */ + +#endif diff --git a/include/charset.h b/include/charset.h index 37a3278499..2662c2f7c9 100644 --- a/include/charset.h +++ b/include/charset.h @@ -9,6 +9,8 @@ #ifndef __CHARSET_H_ #define __CHARSET_H_ +#include <linux/types.h> + #define MAX_UTF8_PER_UTF16 3 /** @@ -62,4 +64,17 @@ uint16_t *utf16_strdup(const uint16_t *s); */ uint8_t *utf16_to_utf8(uint8_t *dest, const uint16_t *src, size_t size); +/** + * utf8_to_utf16() - Convert an utf8 string to utf16 + * + * Converts up to 'size' characters of the utf16 string 'src' to utf8 + * written to the 'dest' buffer. Stops at 0x00. + * + * @dest the destination buffer to write the utf8 characters + * @src the source utf16 string + * @size maximum number of utf16 characters to convert + * @return the pointer to the first unwritten byte in 'dest' + */ +uint16_t *utf8_to_utf16(uint16_t *dest, const uint8_t *src, size_t size); + #endif /* __CHARSET_H_ */ diff --git a/include/common.h b/include/common.h index e14e1daa88..436200044f 100644 --- a/include/common.h +++ b/include/common.h @@ -45,51 +45,7 @@ typedef volatile unsigned char vu_char; #define CONFIG_SYS_SUPPORT_64BIT_DATA #endif -#ifdef DEBUG -#define _DEBUG 1 -#else -#define _DEBUG 0 -#endif - -#ifdef CONFIG_SPL_BUILD -#define _SPL_BUILD 1 -#else -#define _SPL_BUILD 0 -#endif - -/* - * Output a debug text when condition "cond" is met. The "cond" should be - * computed by a preprocessor in the best case, allowing for the best - * optimization. - */ -#define debug_cond(cond, fmt, args...) \ - do { \ - if (cond) \ - printf(pr_fmt(fmt), ##args); \ - } while (0) - -/* Show a message if DEBUG is defined in a file */ -#define debug(fmt, args...) \ - debug_cond(_DEBUG, fmt, ##args) - -/* Show a message if not in SPL */ -#define warn_non_spl(fmt, args...) \ - debug_cond(!_SPL_BUILD, fmt, ##args) - -/* - * An assertion is run-time check done in debug mode only. If DEBUG is not - * defined then it is skipped. If DEBUG is defined and the assertion fails, - * then it calls panic*( which may or may not reset/halt U-Boot (see - * CONFIG_PANIC_HANG), It is hoped that all failing assertions are found - * before release, and after release it is hoped that they don't matter. But - * in any case these failing assertions cannot be fixed with a reset (which - * may just do the same assertion again). - */ -void __assert_fail(const char *assertion, const char *file, unsigned line, - const char *function); -#define assert(x) \ - ({ if (!(x) && _DEBUG) \ - __assert_fail(#x, __FILE__, __LINE__, __func__); }) +#include <log.h> typedef void (interrupt_handler_t)(void *); @@ -201,6 +157,7 @@ int last_stage_init(void); extern ulong monitor_flash_len; int mac_read_from_eeprom(void); extern u8 __dtb_dt_begin[]; /* embedded device tree blob */ +extern u8 __dtb_dt_spl_begin[]; /* embedded device tree blob for SPL/TPL */ int set_cpu_clk_info(void); int mdm_init(void); int print_cpuinfo(void); diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index e0d0034ed3..5c469a23fa 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -91,6 +91,10 @@ #define BOOTEFI_NAME "bootaa64.efi" #elif defined(CONFIG_ARM) #define BOOTEFI_NAME "bootarm.efi" +#elif defined(CONFIG_X86_RUN_32BIT) +#define BOOTEFI_NAME "bootia32.efi" +#elif defined(CONFIG_X86_RUN_64BIT) +#define BOOTEFI_NAME "bootx64.efi" #endif #endif diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index b6715418fc..bd1a7b2679 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -395,9 +395,6 @@ /* * SATA */ -#define CONFIG_LIBATA -#define CONFIG_FSL_SATA - #define CONFIG_SYS_SATA_MAX_DEVICE 2 #define CONFIG_SATA1 #define CONFIG_SYS_SATA1_OFFSET 0x18000 diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index d06d4a2817..c88aa95632 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -67,7 +67,6 @@ /* The CF card interface on the back of the board */ #define CONFIG_COMPACT_FLASH #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ -#define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */ #define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */ #endif @@ -139,7 +138,6 @@ #ifdef CONFIG_SATA_SIL3114 #define CONFIG_SYS_SATA_MAX_DEVICE 4 -#define CONFIG_LIBATA #define CONFIG_LBA48 #endif diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 264aa90cb3..3cc1a4717b 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -420,9 +420,6 @@ extern int board_pci_host_broken(void); /* * SATA */ -#define CONFIG_LIBATA -#define CONFIG_FSL_SATA - #define CONFIG_SYS_SATA_MAX_DEVICE 2 #define CONFIG_SATA1 #define CONFIG_SYS_SATA1_OFFSET 0x18000 diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index beec38f934..656180f91a 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -434,9 +434,6 @@ /* * SATA */ -#define CONFIG_LIBATA -#define CONFIG_FSL_SATA - #define CONFIG_SYS_SATA_MAX_DEVICE 2 #define CONFIG_SATA1 #define CONFIG_SYS_SATA1_OFFSET 0x18000 diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 3319a6f958..7587225bda 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -508,9 +508,6 @@ #endif /* CONFIG_PCI */ /* SATA */ -#define CONFIG_LIBATA -#define CONFIG_FSL_SATA - #define CONFIG_SYS_SATA_MAX_DEVICE 2 #define CONFIG_SATA1 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 2aea8928ee..bec8a09b5f 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -282,10 +282,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SCSI_AHCI #ifdef CONFIG_SCSI_AHCI -#define CONFIG_LIBATA #define CONFIG_SATA_ULI5288 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 #define CONFIG_SYS_SCSI_MAX_LUN 1 diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index b277cdb1c6..ebc2e3aad4 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -469,10 +469,8 @@ #endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SCSI_AHCI #ifdef CONFIG_SCSI_AHCI -#define CONFIG_LIBATA #define CONFIG_SATA_ULI5288 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 #define CONFIG_SYS_SCSI_MAX_LUN 1 diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index e7b59a3d65..bd14bc0607 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -281,10 +281,7 @@ #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ #endif -#define CONFIG_SCSI_AHCI - #ifdef CONFIG_SCSI_AHCI -#define CONFIG_LIBATA #define CONFIG_SATA_ULI5288 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 #define CONFIG_SYS_SCSI_MAX_LUN 1 diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 298fe5a63d..567111798b 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -373,10 +373,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SCSI_AHCI - #ifdef CONFIG_SCSI_AHCI -#define CONFIG_LIBATA #define CONFIG_SATA_ULI5288 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 #define CONFIG_SYS_SCSI_MAX_LUN 1 diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index cbc15ae4c5..72b6e3ad6d 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -634,9 +634,7 @@ extern unsigned long get_sdram_size(void); #endif /* CONFIG_TSEC_ENET */ /* SATA */ -#define CONFIG_FSL_SATA #define CONFIG_FSL_SATA_V2 -#define CONFIG_LIBATA #ifdef CONFIG_FSL_SATA #define CONFIG_SYS_SATA_MAX_DEVICE 2 diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 4756a7102d..30e20bc6e4 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -482,8 +482,6 @@ #endif /* SATA */ -#define CONFIG_LIBATA -#define CONFIG_FSL_SATA #define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_SATA_MAX_DEVICE 2 diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 600823798c..917e5d5a06 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -527,9 +527,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_FSL_SATA_V2 #ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_FSL_SATA -#define CONFIG_LIBATA - #define CONFIG_SYS_SATA_MAX_DEVICE 2 #define CONFIG_SATA1 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index f192181c08..117def9dc2 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h @@ -12,9 +12,7 @@ #define CONFIG_PCIE3 -#define CONFIG_SATA_SIL #define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_LIBATA #define CONFIG_LBA48 #define CONFIG_SYS_SRIO diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 259e8a01f3..ed6df53916 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -615,8 +615,6 @@ unsigned long get_board_ddr_clk(void); */ #define CONFIG_FSL_SATA_V2 #ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_LIBATA -#define CONFIG_FSL_SATA #define CONFIG_SYS_SATA_MAX_DEVICE 1 #define CONFIG_SATA1 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index c694e50c2c..bc5c0d2e68 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -500,9 +500,6 @@ unsigned long get_board_ddr_clk(void); /* SATA */ #define CONFIG_FSL_SATA_V2 #ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_LIBATA -#define CONFIG_FSL_SATA - #define CONFIG_SYS_SATA_MAX_DEVICE 2 #define CONFIG_SATA1 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 2dbeffdd2a..2b9c77f7c8 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -614,9 +614,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg /* SATA */ #define CONFIG_FSL_SATA_V2 #ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_LIBATA -#define CONFIG_FSL_SATA - #define CONFIG_SYS_SATA_MAX_DEVICE 1 #define CONFIG_SATA1 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR @@ -634,6 +631,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #ifdef CONFIG_USB_EHCI_HCD #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_EHCI_DESC_BIG_ENDIAN #endif #endif diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 41926f76e6..43fcc6f5dd 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -678,8 +678,6 @@ unsigned long get_board_ddr_clk(void); * SATA */ #ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_LIBATA -#define CONFIG_FSL_SATA #define CONFIG_SYS_SATA_MAX_DEVICE 2 #define CONFIG_SATA1 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index d2ddb17fce..e1c57de2af 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -628,8 +628,6 @@ unsigned long get_board_ddr_clk(void); * SATA */ #ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_LIBATA -#define CONFIG_FSL_SATA #define CONFIG_SYS_SATA_MAX_DEVICE 2 #define CONFIG_SATA1 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index 885dc776eb..099e9e1d94 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -468,9 +468,6 @@ unsigned long get_board_ddr_clk(void); /* SATA */ #ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_LIBATA -#define CONFIG_FSL_SATA - #define CONFIG_SYS_SATA_MAX_DEVICE 2 #define CONFIG_SATA1 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 625130aafc..98f8f4f10c 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -240,9 +240,6 @@ /* SATA */ #ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_LIBATA -#define CONFIG_FSL_SATA - #define CONFIG_SYS_SATA_MAX_DEVICE 2 #define CONFIG_SATA1 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR @@ -635,9 +632,6 @@ unsigned long get_board_ddr_clk(void); /* SATA */ #ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_LIBATA -#define CONFIG_FSL_SATA - #define CONFIG_SYS_SATA_MAX_DEVICE 2 #define CONFIG_SATA1 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h index 902abc48ce..e8b1a74c64 100644 --- a/include/configs/UCP1020.h +++ b/include/configs/UCP1020.h @@ -118,9 +118,7 @@ #define CONFIG_ENV_OVERWRITE -#define CONFIG_SATA_SIL #define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_LIBATA #define CONFIG_LBA48 #define CONFIG_SYS_CLK_FREQ 66666666 diff --git a/include/configs/adp-ae3xx.h b/include/configs/adp-ae3xx.h index 6946029333..5644a6153b 100644 --- a/include/configs/adp-ae3xx.h +++ b/include/configs/adp-ae3xx.h @@ -91,7 +91,6 @@ /* * SD (MMC) controller */ -#define CONFIG_FTSDC010 #define CONFIG_FTSDC010_NUMBER 1 #define CONFIG_FTSDC010_SDIO diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h index fad4d308e0..f2de384631 100644 --- a/include/configs/adp-ag101p.h +++ b/include/configs/adp-ag101p.h @@ -97,7 +97,6 @@ /* * SD (MMC) controller */ -#define CONFIG_FTSDC010 #define CONFIG_FTSDC010_NUMBER 1 #define CONFIG_FTSDC010_SDIO diff --git a/include/configs/advantech_dms-ba16.h b/include/configs/advantech_dms-ba16.h index 09f470c6b5..f370fe5b78 100644 --- a/include/configs/advantech_dms-ba16.h +++ b/include/configs/advantech_dms-ba16.h @@ -39,12 +39,10 @@ #define CONFIG_MXC_OCOTP /* SATA Configs */ -#define CONFIG_DWC_AHSATA #define CONFIG_SYS_SATA_MAX_DEVICE 1 #define CONFIG_DWC_AHSATA_PORT_ID 0 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR #define CONFIG_LBA48 -#define CONFIG_LIBATA /* MMC Configs */ #define CONFIG_FSL_ESDHC diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 5ad0366730..856c546fc1 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -255,7 +255,7 @@ /* USB Device Firmware Update support */ #ifndef CONFIG_SPL_BUILD #define DFUARGS \ - "dfu_alt_info_emmc=rawemmc raw 0 3751936\0" \ + DFU_ALT_INFO_EMMC \ DFU_ALT_INFO_MMC \ DFU_ALT_INFO_RAM \ DFU_ALT_INFO_NAND diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index dc05bea05e..28618a579c 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -96,8 +96,6 @@ #define CONFIG_OMAP_USB3PHY1_HOST /* SATA */ -#define CONFIG_LIBATA -#define CONFIG_SCSI_AHCI #define CONFIG_SCSI_AHCI_PLAT #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 #define CONFIG_SYS_SCSI_MAX_LUN 1 diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 5a51f3c556..c4e93562b5 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -70,12 +70,10 @@ * SATA Configs */ #ifdef CONFIG_CMD_SATA -#define CONFIG_DWC_AHSATA #define CONFIG_SYS_SATA_MAX_DEVICE 1 #define CONFIG_DWC_AHSATA_PORT_ID 0 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR #define CONFIG_LBA48 -#define CONFIG_LIBATA #endif /* Network */ diff --git a/include/configs/boston.h b/include/configs/boston.h index ee4e4a37ea..fdd5ef5632 100644 --- a/include/configs/boston.h +++ b/include/configs/boston.h @@ -34,7 +34,7 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100000) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x08000000) #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0) #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x10000000) diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index 2e8993d7d4..b50535f9b0 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -81,12 +81,10 @@ #define CONFIG_IMX_HDMI /* SATA */ -#define CONFIG_DWC_AHSATA #define CONFIG_SYS_SATA_MAX_DEVICE 1 #define CONFIG_DWC_AHSATA_PORT_ID 0 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR #define CONFIG_LBA48 -#define CONFIG_LIBATA /* Ethernet */ #define CONFIG_FEC_MXC diff --git a/include/configs/cl-som-am57x.h b/include/configs/cl-som-am57x.h index a3b40ab196..6935b06d5c 100644 --- a/include/configs/cl-som-am57x.h +++ b/include/configs/cl-som-am57x.h @@ -62,8 +62,6 @@ #ifndef CONFIG_SPL_BUILD /* SATA */ -#define CONFIG_LIBATA -#define CONFIG_SCSI_AHCI #define CONFIG_SCSI_AHCI_PLAT #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 #define CONFIG_SYS_SCSI_MAX_LUN 1 diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index da3233e965..5195610233 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -209,9 +209,7 @@ /* SATA */ #define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_LIBATA #define CONFIG_LBA48 -#define CONFIG_DWC_AHSATA #define CONFIG_DWC_AHSATA_PORT_ID 0 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR diff --git a/include/configs/cm_t54.h b/include/configs/cm_t54.h index 9152c71717..1351eb85f2 100644 --- a/include/configs/cm_t54.h +++ b/include/configs/cm_t54.h @@ -47,8 +47,6 @@ #define CONFIG_SPL_SATA_BOOT_DEVICE 0 #define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1 -#define CONFIG_LIBATA -#define CONFIG_SCSI_AHCI #define CONFIG_SCSI_AHCI_PLAT #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 #define CONFIG_SYS_SCSI_MAX_LUN 1 diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h index 37c8be48ac..4312ddd4fc 100644 --- a/include/configs/controlcenterd.h +++ b/include/configs/controlcenterd.h @@ -245,10 +245,8 @@ /* * SATA */ -#define CONFIG_LIBATA #define CONFIG_LBA48 -#define CONFIG_FSL_SATA #define CONFIG_SYS_SATA_MAX_DEVICE 2 #define CONFIG_SATA1 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR diff --git a/include/configs/controlcenterdc.h b/include/configs/controlcenterdc.h index 715e9ed9c9..a882fa650b 100644 --- a/include/configs/controlcenterdc.h +++ b/include/configs/controlcenterdc.h @@ -48,8 +48,6 @@ /* * SATA/SCSI/AHCI configuration */ -#define CONFIG_LIBATA -#define CONFIG_SCSI_AHCI #define CONFIG_SCSI_AHCI_PLAT #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 #define CONFIG_SYS_SCSI_MAX_LUN 1 diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 0dbf149725..d0e8bfbed7 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -541,9 +541,6 @@ /* SATA */ #ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_LIBATA -#define CONFIG_FSL_SATA - #define CONFIG_SYS_SATA_MAX_DEVICE 2 #define CONFIG_SATA1 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h index 1b20d85acf..4fea53bf79 100644 --- a/include/configs/cyrus.h +++ b/include/configs/cyrus.h @@ -376,9 +376,6 @@ /* SATA */ #ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_LIBATA -#define CONFIG_FSL_SATA - #define CONFIG_SYS_SATA_MAX_DEVICE 2 #define CONFIG_SATA1 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h index 44fd968d3b..32f93f2f46 100644 --- a/include/configs/db-88f6820-gp.h +++ b/include/configs/db-88f6820-gp.h @@ -44,8 +44,6 @@ /* * SATA/SCSI/AHCI configuration */ -#define CONFIG_LIBATA -#define CONFIG_SCSI_AHCI #define CONFIG_SCSI_AHCI_PLAT #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 #define CONFIG_SYS_SCSI_MAX_LUN 1 diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index 4a5be6188f..3dcc28710b 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -49,8 +49,6 @@ /* SATA support */ #define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA_MV -#define CONFIG_LIBATA #define CONFIG_LBA48 /* Additional FS support/configuration */ diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 11a01d476f..fb49997ebd 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -84,12 +84,10 @@ /* SATA Configs */ #ifdef CONFIG_CMD_SATA -#define CONFIG_DWC_AHSATA #define CONFIG_SYS_SATA_MAX_DEVICE 1 #define CONFIG_DWC_AHSATA_PORT_ID 0 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR #define CONFIG_LBA48 -#define CONFIG_LIBATA #endif /* SPI Flash Configs */ diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index f84c1f0146..f777d576dd 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -148,8 +148,6 @@ #define CONFIG_OMAP_USB2PHY2_HOST /* SATA */ -#define CONFIG_LIBATA -#define CONFIG_SCSI_AHCI #define CONFIG_SCSI_AHCI_PLAT #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 #define CONFIG_SYS_SCSI_MAX_LUN 1 diff --git a/include/configs/draak.h b/include/configs/draak.h new file mode 100644 index 0000000000..392ba4a6ba --- /dev/null +++ b/include/configs/draak.h @@ -0,0 +1,47 @@ +/* + * include/configs/draak.h + * This file is Draak board configuration. + * + * Copyright (C) 2015 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DRAAK_H +#define __DRAAK_H + +#undef DEBUG + +#include "rcar-gen3-common.h" + +/* Ethernet RAVB */ +#define CONFIG_NET_MULTI +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI + +/* Board Clock */ +/* XTAL_CLK : 33.33MHz */ +#define CONFIG_SYS_CLK_FREQ 33333333u + +/* Generic Timer Definitions (use in assembler source) */ +#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) +#define CONFIG_SYS_MMC_ENV_DEV 1 +#define CONFIG_SYS_MMC_ENV_PART 2 + +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_MTD +#define CONFIG_FLASH_SHOW_PROGRESS 45 +#define CONFIG_MTD_DEVICE +#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CONFIG_CMD_CACHE + +#endif /* __DRAAK_H */ diff --git a/include/configs/eagle.h b/include/configs/eagle.h new file mode 100644 index 0000000000..2ef0c7a777 --- /dev/null +++ b/include/configs/eagle.h @@ -0,0 +1,29 @@ +/* + * include/configs/eagle.h + * This file is Eagle board configuration. + * + * Copyright (C) 2015 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __EAGLE_H +#define __EAGLE_H + +#undef DEBUG + +#include "rcar-gen3-common.h" + +/* Ethernet RAVB */ +#define CONFIG_NET_MULTI +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI + +/* Board Clock */ +/* XTAL_CLK : 33.33MHz */ +#define CONFIG_SYS_CLK_FREQ 33333333u + +/* Generic Timer Definitions (use in assembler source) */ +#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ + +#endif /* __EAGLE_H */ diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index 17d23839b8..2b7a5d7c5c 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -140,7 +140,6 @@ #define __io #define CONFIG_IDE_PREINIT /* ED Mini V has an IDE-compatible SATA connector for port 1 */ -#define CONFIG_MVSATA_IDE #define CONFIG_MVSATA_IDE_USE_PORT1 /* Needs byte-swapping for ATA data register */ #define CONFIG_IDE_SWAP_IO diff --git a/include/configs/efi-x86.h b/include/configs/efi-x86.h index 43935bf4b4..b027615139 100644 --- a/include/configs/efi-x86.h +++ b/include/configs/efi-x86.h @@ -11,8 +11,6 @@ #undef CONFIG_TPM_TIS_BASE_ADDRESS -#undef CONFIG_SCSI_AHCI - #define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ "stdout=vga,serial\0" \ "stderr=vga,serial\0" diff --git a/include/configs/evb_px5.h b/include/configs/evb_px5.h index d008539eb1..4160187d50 100644 --- a/include/configs/evb_px5.h +++ b/include/configs/evb_px5.h @@ -9,8 +9,6 @@ #include <configs/rk3368_common.h> -#define CONFIG_ENV_SIZE 0x2000 - #define CONFIG_CONSOLE_SCROLL_LINES 10 #endif diff --git a/include/configs/evb_rk3128.h b/include/configs/evb_rk3128.h new file mode 100644 index 0000000000..a34153aac5 --- /dev/null +++ b/include/configs/evb_rk3128.h @@ -0,0 +1,15 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __EVB_RK3128_H +#define __EVB_RK3128_H + +#include <configs/rk3128_common.h> + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#endif diff --git a/include/configs/galileo.h b/include/configs/galileo.h index 00c5434125..cf798d07e7 100644 --- a/include/configs/galileo.h +++ b/include/configs/galileo.h @@ -22,9 +22,6 @@ "stdout=serial\0" \ "stderr=serial\0" -/* SATA is not supported in Quark SoC */ -#undef CONFIG_SCSI_AHCI - /* 10/100M Ethernet support */ #define CONFIG_DESIGNWARE_ETH #define CONFIG_DW_ALTDESCRIPTOR diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 33f5101c14..1454577dbf 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -51,12 +51,10 @@ /* SATA Configs */ #ifdef CONFIG_CMD_SATA -#define CONFIG_DWC_AHSATA #define CONFIG_SYS_SATA_MAX_DEVICE 1 #define CONFIG_DWC_AHSATA_PORT_ID 0 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR #define CONFIG_LBA48 -#define CONFIG_LIBATA #endif /* MMC Configs */ diff --git a/include/configs/geekbox.h b/include/configs/geekbox.h index 7a707cb2a0..bb2ef9a31b 100644 --- a/include/configs/geekbox.h +++ b/include/configs/geekbox.h @@ -9,8 +9,6 @@ #include <configs/rk3368_common.h> -#define CONFIG_ENV_SIZE 0x2000 - #define CONFIG_CONSOLE_SCROLL_LINES 10 #endif diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 05c88b3ef8..068962d613 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -102,12 +102,10 @@ * SATA Configs */ #ifdef CONFIG_CMD_SATA - #define CONFIG_DWC_AHSATA #define CONFIG_SYS_SATA_MAX_DEVICE 1 #define CONFIG_DWC_AHSATA_PORT_ID 0 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR #define CONFIG_LBA48 - #define CONFIG_LIBATA #endif /* diff --git a/include/configs/highbank.h b/include/configs/highbank.h index b2b2c2500a..a5a524008b 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -33,8 +33,6 @@ #define CONFIG_SYS_BOOTCOUNT_ADDR 0xfff3cf0c #define CONFIG_MISC_INIT_R -#define CONFIG_LIBATA -#define CONFIG_SCSI_AHCI #define CONFIG_SCSI_AHCI_PLAT #define CONFIG_SYS_SCSI_MAX_SCSI_ID 5 #define CONFIG_SYS_SCSI_MAX_LUN 1 diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h index 86c1d385cf..0c45e066d8 100644 --- a/include/configs/imx6-engicam.h +++ b/include/configs/imx6-engicam.h @@ -215,17 +215,6 @@ # endif # include "imx6_spl.h" -# ifdef CONFIG_SPL_BUILD -# if defined(CONFIG_TARGET_MX6Q_ICORE_RQS) || defined(CONFIG_TARGET_MX6UL_ISIOT) -# define CONFIG_SYS_FSL_USDHC_NUM 2 -# else -# define CONFIG_SYS_FSL_USDHC_NUM 1 -# endif - -# define CONFIG_SYS_FSL_ESDHC_ADDR 0 -# undef CONFIG_DM_GPIO -# undef CONFIG_DM_MMC -# endif #endif #endif /* __IMX6_ENGICAM_CONFIG_H */ diff --git a/include/configs/khadas-vim.h b/include/configs/khadas-vim.h new file mode 100644 index 0000000000..9d99bc5dc7 --- /dev/null +++ b/include/configs/khadas-vim.h @@ -0,0 +1,21 @@ +/* + * Configuration for Khadas VIM + * + * Copyright (C) 2017 Baylibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MISC_INIT_R + +#define CONFIG_PHY_ADDR 8 + +#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-khadas-vim.dtb\0" + +#include <configs/meson-gxbb-common.h> + +#endif /* __CONFIG_H */ diff --git a/include/configs/libretech-cc.h b/include/configs/libretech-cc.h new file mode 100644 index 0000000000..ffaca2648b --- /dev/null +++ b/include/configs/libretech-cc.h @@ -0,0 +1,21 @@ +/* + * Configuration for LibreTech CC + * + * Copyright (C) 2017 Baylibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MISC_INIT_R + +#define CONFIG_PHY_ADDR 8 + +#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-libretech-cc.dtb\0" + +#include <configs/meson-gxbb-common.h> + +#endif /* __CONFIG_H */ diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index d2fa50a8be..db920bc5cc 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -65,7 +65,7 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_ENV_SIZE 0x40000 /* 256KB */ -#define CONFIG_ENV_OFFSET 0x200000 /* 2MB */ +#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ #define CONFIG_ENV_SECT_SIZE 0x40000 #endif @@ -87,6 +87,14 @@ #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 +#include <config_distro_defaults.h> +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) +#include <config_distro_bootcmd.h> +#endif + /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ @@ -94,10 +102,11 @@ "kernel_addr=0x100000\0" \ "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ - "kernel_start=0xa00000\0" \ + "kernel_start=0x1000000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ +#undef CONFIG_BOOTCOMMAND #define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\ "$kernel_start $kernel_size && "\ "bootm $kernel_load" @@ -105,7 +114,6 @@ /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ #define CONFIG_SYS_LONGHELP -#define CONFIG_CMDLINE_EDITING 1 #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_MAXARGS 64 /* max command args */ diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h index efb4c00cd9..297c057292 100644 --- a/include/configs/ls1012afrdm.h +++ b/include/configs/ls1012afrdm.h @@ -20,16 +20,55 @@ #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END 0x9fffffff +#ifndef CONFIG_SPL_BUILD +#undef BOOT_TARGET_DEVICES +#define BOOT_TARGET_DEVICES(func) \ + func(USB, usb, 0) +#endif + #undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "verify=no\0" \ - "loadaddr=0x80100000\0" \ - "kernel_addr=0x100000\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "kernel_start=0xa00000\0" \ - "kernel_load=0x96000000\0" \ - "kernel_size=0x2800000\0" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=no\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "fdt_addr=0x00f00000\0" \ + "kernel_addr=0x01000000\0" \ + "scriptaddr=0x80000000\0" \ + "fdtheader_addr_r=0x80100000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "kernel_addr_r=0x96000000\0" \ + "fdt_addr_r=0x90000000\0" \ + "load_addr=0x96000000\0" \ + "kernel_size=0x2800000\0" \ + "console=ttyS0,115200\0" \ + BOOTENV \ + "boot_scripts=ls1012afrdm_boot.scr\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "scan_dev_for_boot=" \ + "echo Scanning ${devtype} " \ + "${devnum}:${distro_bootpart}...; " \ + "for prefix in ${boot_prefixes}; do " \ + "run scan_dev_for_scripts; " \ + "done;" \ + "\0" \ + "installer=load usb 0:2 $load_addr " \ + "/flex_installer_arm64.itb; " \ + "bootm $load_addr#$board\0" \ + "qspi_bootcmd=echo Trying load from qspi..;" \ + "sf probe && sf read $load_addr " \ + "$kernel_addr $kernel_size && bootm $load_addr#$board\0" + +#undef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run qspi_bootcmd" #define CONFIG_CMD_MEMINFO #define CONFIG_CMD_MEMTEST diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index d15054709e..af5f37cca3 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -125,8 +125,6 @@ #endif /* SATA */ -#define CONFIG_LIBATA -#define CONFIG_SCSI_AHCI #define CONFIG_SCSI_AHCI_PLAT #define CONFIG_SYS_SATA AHCI_BASE_ADDR diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index 794117062f..ab139b00dd 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -24,14 +24,21 @@ * I2C IO expander */ -#define I2C_MUX_IO1_ADDR 0x24 -#define __SW_BOOT_MASK 0xFC -#define __SW_BOOT_EMU 0x10 -#define __SW_BOOT_BANK1 0x00 -#define __SW_BOOT_BANK2 0x01 -#define __SW_REV_MASK 0x07 -#define __SW_REV_A 0xF8 -#define __SW_REV_B 0xF0 +#define I2C_MUX_IO_ADDR 0x24 +#define I2C_MUX_IO_0 0 +#define I2C_MUX_IO_1 1 +#define SW_BOOT_MASK 0x03 +#define SW_BOOT_EMU 0x02 +#define SW_BOOT_BANK1 0x00 +#define SW_BOOT_BANK2 0x01 +#define SW_REV_MASK 0xF8 +#define SW_REV_A 0xF8 +#define SW_REV_B 0xF0 +#define SW_REV_C 0xE8 +#define SW_REV_C1 0xE0 +#define SW_REV_C2 0xD8 +#define SW_REV_D 0xD0 +#define SW_REV_E 0xC8 /* MMC */ #ifdef CONFIG_MMC @@ -40,8 +47,6 @@ #endif /* SATA */ -#define CONFIG_LIBATA -#define CONFIG_SCSI_AHCI #define CONFIG_SCSI_AHCI_PLAT #define CONFIG_SYS_SATA AHCI_BASE_ADDR @@ -60,6 +65,49 @@ #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END 0x9fffffff +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=no\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "fdt_addr=0x00f00000\0" \ + "kernel_addr=0x01000000\0" \ + "scriptaddr=0x80000000\0" \ + "fdtheader_addr_r=0x80100000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "kernel_addr_r=0x81000000\0" \ + "fdt_addr_r=0x90000000\0" \ + "load_addr=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "console=ttyS0,115200\0" \ + BOOTENV \ + "boot_scripts=ls1012ardb_boot.scr\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "scan_dev_for_boot=" \ + "echo Scanning ${devtype} " \ + "${devnum}:${distro_bootpart}...; " \ + "for prefix in ${boot_prefixes}; do " \ + "run scan_dev_for_scripts; " \ + "done;" \ + "\0" \ + "installer=load mmc 0:2 $load_addr " \ + "/flex_installer_arm64.itb; " \ + "bootm $load_addr#$board\0" \ + "qspi_bootcmd=echo Trying load from qspi..;" \ + "sf probe && sf read $load_addr " \ + "$kernel_addr $kernel_size && bootm $load_addr#$board\0" + +#undef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run qspi_bootcmd" #include <asm/fsl_secure_boot.h> diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 46bf55f891..4a63efc5ef 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -127,8 +127,6 @@ #define CONFIG_FSL_ESDHC /* SATA */ -#define CONFIG_LIBATA -#define CONFIG_SCSI_AHCI #define CONFIG_SCSI_AHCI_PLAT #ifndef PCI_DEVICE_ID_FREESCALE_AHCI #define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440 diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 5be61ad7b6..3db7ef12b0 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -420,16 +420,22 @@ "initrd_high=0xffffffff\0" \ "fdt_high=0xffffffff\0" \ "fdt_addr=0x64f00000\0" \ - "kernel_addr=0x65000000\0" \ + "kernel_addr=0x61000000\0" \ + "kernelheader_addr=0x60800000\0" \ "scriptaddr=0x80000000\0" \ "scripthdraddr=0x80080000\0" \ "fdtheader_addr_r=0x80100000\0" \ "kernelheader_addr_r=0x80200000\0" \ "kernel_addr_r=0x81000000\0" \ + "kernelheader_size=0x40000\0" \ "fdt_addr_r=0x90000000\0" \ "ramdisk_addr_r=0xa0000000\0" \ "load_addr=0xa0000000\0" \ "kernel_size=0x2800000\0" \ + "kernel_addr_sd=0x8000\0" \ + "kernel_size_sd=0x14000\0" \ + "kernelhdr_addr_sd=0x4000\0" \ + "kernelhdr_size_sd=0x10\0" \ BOOTENV \ "boot_scripts=ls1021atwr_boot.scr\0" \ "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \ @@ -460,26 +466,35 @@ "source ${scriptaddr}\0" \ "qspi_bootcmd=echo Trying load from qspi..;" \ "sf probe && sf read $load_addr " \ - "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \ + "$kernel_addr $kernel_size; env exists secureboot " \ + "&& sf read $kernelheader_addr_r $kernelheader_addr " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ + "bootm $load_addr#$board\0" \ "nor_bootcmd=echo Trying load from nor..;" \ "cp.b $kernel_addr $load_addr " \ - "$kernel_size && bootm $load_addr#$board\0" \ + "$kernel_size; env exists secureboot " \ + "&& cp.b $kernelheader_addr $kernelheader_addr_r " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ + "bootm $load_addr#$board\0" \ "sd_bootcmd=echo Trying load from SD ..;" \ "mmcinfo && mmc read $load_addr " \ "$kernel_addr_sd $kernel_size_sd && " \ + "env exists secureboot && mmc read $kernelheader_addr_r " \ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ "bootm $load_addr#$board\0" #endif #undef CONFIG_BOOTCOMMAND #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot" \ - "&& esbc_halt; run qspi_bootcmd;" +#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd" \ + "env exists secureboot && esbc_halt" #elif defined(CONFIG_SD_BOOT) -#define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot" \ - "&& esbc_halt; run sd_bootcmd;" +#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;" #else -#define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot" \ - "&& esbc_halt; run nor_bootcmd;" +#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd;" \ + "env exists secureboot && esbc_halt;" #endif /* diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index a4cd09aa90..67b5ea715e 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -252,7 +252,7 @@ "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ "fdt_addr=0x64f00000\0" \ - "kernel_addr=0x65000000\0" \ + "kernel_addr=0x61000000\0" \ "scriptaddr=0x80000000\0" \ "scripthdraddr=0x80080000\0" \ "fdtheader_addr_r=0x80100000\0" \ @@ -260,9 +260,13 @@ "kernel_addr_r=0x81000000\0" \ "fdt_addr_r=0x90000000\0" \ "load_addr=0xa0000000\0" \ + "kernelheader_addr=0x60800000\0" \ "kernel_size=0x2800000\0" \ + "kernelheader_size=0x40000\0" \ "kernel_addr_sd=0x8000\0" \ "kernel_size_sd=0x14000\0" \ + "kernelhdr_addr_sd=0x4000\0" \ + "kernelhdr_size_sd=0x10\0" \ "console=ttyS0,115200\0" \ "boot_os=y\0" \ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ @@ -295,26 +299,35 @@ "source ${scriptaddr}\0" \ "qspi_bootcmd=echo Trying load from qspi..;" \ "sf probe && sf read $load_addr " \ - "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \ + "$kernel_addr $kernel_size; env exists secureboot " \ + "&& sf read $kernelheader_addr_r $kernelheader_addr " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ + "bootm $load_addr#$board\0" \ "nor_bootcmd=echo Trying load from nor..;" \ "cp.b $kernel_addr $load_addr " \ - "$kernel_size && bootm $load_addr#$board\0" \ + "$kernel_size; env exists secureboot " \ + "&& cp.b $kernelheader_addr $kernelheader_addr_r " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ + "bootm $load_addr#$board\0" \ "sd_bootcmd=echo Trying load from SD ..;" \ "mmcinfo; mmc read $load_addr " \ "$kernel_addr_sd $kernel_size_sd && " \ + "env exists secureboot && mmc read $kernelheader_addr_r " \ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ "bootm $load_addr#$board\0" #undef CONFIG_BOOTCOMMAND #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot" \ - "&& esbc_halt; run qspi_bootcmd;" +#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ + "env exists secureboot && esbc_halt;" #elif defined(CONFIG_SD_BOOT) -#define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot" \ - "&& esbc_halt; run sd_bootcmd;" +#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;" #else -#define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot" \ - "&& esbc_halt; run nor_bootcmd;" +#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \ + "env exists secureboot && esbc_halt;" #endif #endif diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 8cc2abb2b6..a7f78f46ae 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -94,8 +94,6 @@ unsigned long get_board_ddr_clk(void); #endif /* SATA */ -#define CONFIG_LIBATA -#define CONFIG_SCSI_AHCI #define CONFIG_SCSI_AHCI_PLAT /* EEPROM */ diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index b4b4d5e178..34f82281c8 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -286,8 +286,6 @@ /* SATA */ #ifndef SPL_NO_SATA -#define CONFIG_LIBATA -#define CONFIG_SCSI_AHCI #ifndef CONFIG_CMD_EXT2 #define CONFIG_CMD_EXT2 #endif diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 11f2a28743..e208f7d2de 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -225,10 +225,14 @@ "fdt_addr_r=0x90000000\0" \ "ramdisk_addr_r=0xa0000000\0" \ "kernel_start=0x1000000\0" \ + "kernelheader_start=0x800000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ + "kernelheader_size=0x40000\0" \ "kernel_addr_sd=0x8000\0" \ "kernel_size_sd=0x14000\0" \ + "kernelhdr_addr_sd=0x4000\0" \ + "kernelhdr_size_sd=0x10\0" \ "console=ttyS0,115200\0" \ CONFIG_MTDPARTS_DEFAULT "\0" \ BOOTENV \ @@ -261,10 +265,16 @@ "source ${scriptaddr}\0" \ "qspi_bootcmd=echo Trying load from qspi..;" \ "sf probe && sf read $load_addr " \ - "$kernel_start $kernel_size && bootm $load_addr#$board\0" \ + "$kernel_start $kernel_size; env exists secureboot " \ + "&& sf read $kernelheader_addr_r $kernelheader_start " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ + "bootm $load_addr#$board\0" \ "sd_bootcmd=echo Trying load from SD ..;" \ "mmcinfo; mmc read $load_addr " \ "$kernel_addr_sd $kernel_size_sd && " \ + "env exists secureboot && mmc read $kernelheader_addr_r " \ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ "bootm $load_addr#$board\0" #endif diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index 1713e2c031..c3b0f4d47e 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -137,8 +137,6 @@ unsigned long get_board_ddr_clk(void); #endif /* SATA */ -#define CONFIG_LIBATA -#define CONFIG_SCSI_AHCI #define CONFIG_SCSI_AHCI_PLAT /* EEPROM */ @@ -178,12 +176,13 @@ unsigned long get_board_ddr_clk(void); CSOR_NOR_TRHZ_80) #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TAVDS(0x6) | \ FTIM0_NOR_TEAHC(0x5)) #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1a) | \ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ - FTIM2_NOR_TCH(0x4) | \ +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \ + FTIM2_NOR_TCH(0x8) | \ FTIM2_NOR_TWPH(0xe) | \ FTIM2_NOR_TWP(0x1c)) #define CONFIG_SYS_NOR_FTIM3 0 diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index d001b80270..784894f0b7 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -211,8 +211,6 @@ /* SATA */ #ifndef SPL_NO_SATA -#define CONFIG_LIBATA -#define CONFIG_SCSI_AHCI #define CONFIG_SCSI_AHCI_PLAT #define CONFIG_SYS_SATA AHCI_BASE_ADDR @@ -226,11 +224,11 @@ #ifndef SPL_NO_MISC #undef CONFIG_BOOTCOMMAND #if defined(CONFIG_QSPI_BOOT) -#define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot" \ - "&& esbc_halt; run qspi_bootcmd;" +#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ + "env exists secureboot && esbc_halt;;" #elif defined(CONFIG_SD_BOOT) -#define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot" \ - "&& esbc_halt; run sd_bootcmd;" +#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;" #endif #endif diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 6b71d47c5a..0cd2f3c2bc 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -144,9 +144,6 @@ unsigned long long get_qixis_addr(void); #if defined(CONFIG_FSL_MC_ENET) #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) #endif - -#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ - /* Command line configuration */ #define CONFIG_CMD_GREPENV #define CONFIG_CMD_CACHE @@ -156,8 +153,6 @@ unsigned long long get_qixis_addr(void); /* SATA */ #ifdef CONFIG_SCSI -#define CONFIG_LIBATA -#define CONFIG_SCSI_AHCI #define CONFIG_SCSI_AHCI_PLAT #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index 310e8fd59f..e7e3afefd9 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -335,6 +335,26 @@ unsigned long get_board_ddr_clk(void); QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) /* Initial environment variables */ +#ifdef CONFIG_SECURE_BOOT +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "loadaddr=0x90100000\0" \ + "kernel_addr=0x100000\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xa0000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x1000000\0" \ + "kernel_load=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x100000;" \ + "sf read 0xa0700000 0x700000 0x4000; esbc_validate 0xa0700000;" \ + "sf read 0xa0e00000 0xe00000 0x100000;" \ + "sf read 0xa0740000 0x740000 0x4000;esbc_validate 0xa0740000;" \ + "fsl_mc start mc 0xa0a00000 0xa0e00000\0" \ + "mcmemsize=0x70000000 \0" +#else /* if !(CONFIG_SECURE_BOOT) */ #if defined(CONFIG_QSPI_BOOT) #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -385,6 +405,7 @@ unsigned long get_board_ddr_clk(void); "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \ "mcmemsize=0x70000000 \0" #endif +#endif /* CONFIG_SECURE_BOOT */ #ifdef CONFIG_FSL_MC_ENET #define CONFIG_FSL_MEMAC diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index e6bf2b8d87..1438bec1af 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -11,6 +11,8 @@ #define CONFIG_DISPLAY_BOARDINFO_LATE +#define CONFIG_MISC_INIT_R + #if defined(CONFIG_QSPI_BOOT) #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ @@ -95,6 +97,7 @@ #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } #endif #endif +#define CONFIG_NAND_FSL_IFC #define CONFIG_SYS_NAND_MAX_ECCPOS 256 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 @@ -132,6 +135,7 @@ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) @@ -261,13 +265,23 @@ #define MC_INIT_CMD \ "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ "sf read 0x80100000 0xE00000 0x100000;" \ - "fsl_mc start mc 0x80000000 0x80100000\0" \ + "env exists secureboot && " \ + "sf read 0x80700000 0x700000 0x40000 && " \ + "sf read 0x80740000 0x740000 0x40000 && " \ + "esbc_validate 0x80700000 && " \ + "esbc_validate 0x80740000 ;" \ + "fsl_mc start mc 0x80000000 0x80100000\0" \ "mcmemsize=0x70000000\0" #elif defined(CONFIG_SD_BOOT) #define MC_INIT_CMD \ "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ "mmc read 0x80100000 0x7000 0x800;" \ - "fsl_mc start mc 0x80000000 0x80100000\0" \ + "env exists secureboot && " \ + "mmc read 0x80700000 0x3800 0x10 && " \ + "mmc read 0x80740000 0x3A00 0x10 && " \ + "esbc_validate 0x80700000 && " \ + "esbc_validate 0x80740000 ;" \ + "fsl_mc start mc 0x80000000 0x80100000\0" \ "mcmemsize=0x70000000\0" #endif @@ -282,6 +296,7 @@ "fdt_addr=0x64f00000\0" \ "kernel_addr=0x1000000\0" \ "kernel_addr_sd=0x8000\0" \ + "kernelhdr_addr_sd=0x4000\0" \ "kernel_start=0x580100000\0" \ "kernelheader_start=0x580800000\0" \ "scriptaddr=0x80000000\0" \ @@ -295,6 +310,7 @@ "load_addr=0xa0000000\0" \ "kernel_size=0x2800000\0" \ "kernel_size_sd=0x14000\0" \ + "kernelhdr_size_sd=0x10\0" \ MC_INIT_CMD \ BOOTENV \ "boot_scripts=ls1088ardb_boot.scr\0" \ @@ -331,29 +347,41 @@ "bootm $load_addr#ls1088ardb\0" \ "qspi_bootcmd=echo Trying load from qspi..;" \ "sf probe && sf read $load_addr " \ - "$kernel_addr $kernel_size &&" \ + "$kernel_addr $kernel_size ; env exists secureboot " \ + "&& sf read $kernelheader_addr_r $kernelheader_addr " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ "bootm $load_addr#$BOARD\0" \ - "sd_bootcmd=echo Trying load from sd card..;" \ + "sd_bootcmd=echo Trying load from sd card..;" \ "mmcinfo; mmc read $load_addr " \ "$kernel_addr_sd $kernel_size_sd ;" \ + "env exists secureboot && mmc read $kernelheader_addr_r "\ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ "bootm $load_addr#$BOARD\0" #undef CONFIG_BOOTCOMMAND #if defined(CONFIG_QSPI_BOOT) /* Try to boot an on-QSPI kernel first, then do normal distro boot */ #define CONFIG_BOOTCOMMAND \ - "env exists mcinitcmd && run mcinitcmd && " \ - "sf read 0x80200000 0xd00000 0x100000;" \ - " fsl_mc apply dpl 0x80200000;" \ - "run distro_bootcmd;run qspi_bootcmd" + "sf read 0x80200000 0xd00000 0x100000;" \ + "env exists mcinitcmd && env exists secureboot " \ + " && sf read 0x80780000 0x780000 0x100000 " \ + "&& esbc_validate 0x80780000;env exists mcinitcmd " \ + "&& fsl_mc apply dpl 0x80200000;" \ + "run distro_bootcmd;run qspi_bootcmd;" \ + "env exists secureboot && esbc_halt;" + /* Try to boot an on-SD kernel first, then do normal distro boot */ #elif defined(CONFIG_SD_BOOT) #define CONFIG_BOOTCOMMAND \ - "env exists mcinitcmd && run mcinitcmd ;" \ - "&& env exists mcinitcmd && mmcinfo; " \ - "mmc read 0x88000000 0x6800 0x800; " \ - "&& fsl_mc apply dpl 0x88000000;" \ - "run distro_bootcmd;run sd_bootcmd" + "env exists mcinitcmd && mmcinfo; " \ + "mmc read 0x80200000 0x6800 0x800; " \ + "env exists mcinitcmd && env exists secureboot " \ + " && mmc read 0x80780000 0x3800 0x10 " \ + "&& esbc_validate 0x80780000;env exists mcinitcmd " \ + "&& fsl_mc apply dpl 0x80200000;" \ + "run distro_bootcmd;run sd_bootcmd;" \ + "env exists secureboot && esbc_halt;" #endif /* MAC/PHY configuration */ diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index f8978693a4..576785e4b6 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -237,7 +237,7 @@ unsigned long long get_qixis_addr(void); #endif #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 -#define CONFIG_SYS_MONITOR_LEN (640 * 1024) +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index f1968cc533..815d8adc92 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -46,8 +46,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ /* SATA */ -#define CONFIG_LIBATA -#define CONFIG_SCSI_AHCI #define CONFIG_SCSI_AHCI_PLAT #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 650db2f594..6f3301c2fd 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -64,8 +64,6 @@ unsigned long get_board_sys_clk(void); #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ /* SATA */ -#define CONFIG_LIBATA -#define CONFIG_SCSI_AHCI #define CONFIG_SCSI_AHCI_PLAT #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h index 29eb59a3cb..50379c7b21 100644 --- a/include/configs/m53evk.h +++ b/include/configs/m53evk.h @@ -141,12 +141,10 @@ * SATA */ #ifdef CONFIG_CMD_SATA -#define CONFIG_DWC_AHSATA #define CONFIG_SYS_SATA_MAX_DEVICE 1 #define CONFIG_DWC_AHSATA_PORT_ID 0 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR #define CONFIG_LBA48 -#define CONFIG_LIBATA #endif /* diff --git a/include/configs/meson-gxbb-common.h b/include/configs/meson-gxbb-common.h index d88d42de9a..c2b306ad2e 100644 --- a/include/configs/meson-gxbb-common.h +++ b/include/configs/meson-gxbb-common.h @@ -10,7 +10,7 @@ #define CONFIG_CPU_ARMV8 #define CONFIG_REMAKE_ELF -#define CONFIG_NR_DRAM_BANKS 2 +#define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SYS_MAXARGS 32 #define CONFIG_SYS_MALLOC_LEN (32 << 20) diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h index 1b2e0d71b4..af16b9454a 100644 --- a/include/configs/mvebu_armada-37xx.h +++ b/include/configs/mvebu_armada-37xx.h @@ -96,9 +96,7 @@ /* * SATA/SCSI/AHCI configuration */ -#define CONFIG_SCSI_AHCI #define CONFIG_SCSI_AHCI_PLAT -#define CONFIG_LIBATA #define CONFIG_LBA48 #define CONFIG_SYS_64BIT_LBA diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h index fd60a9bfd4..7f143164c3 100644 --- a/include/configs/mvebu_armada-8k.h +++ b/include/configs/mvebu_armada-8k.h @@ -73,11 +73,6 @@ #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE -/* Environment in SPI NOR flash */ -#ifdef CONFIG_MVEBU_SPI_BOOT -/* Environment in NAND flash */ -#endif - #define CONFIG_ENV_OFFSET 0x180000 /* as Marvell U-Boot version */ #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ @@ -101,9 +96,7 @@ /* * SATA/SCSI/AHCI configuration */ -#define CONFIG_SCSI_AHCI #define CONFIG_SCSI_AHCI_PLAT -#define CONFIG_LIBATA #define CONFIG_LBA48 #define CONFIG_SYS_64BIT_LBA diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index e973b35698..323aa3d907 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -182,12 +182,10 @@ #define CONFIG_SYS_MMC_ENV_DEV 0 #ifdef CONFIG_CMD_SATA - #define CONFIG_DWC_AHSATA #define CONFIG_SYS_SATA_MAX_DEVICE 1 #define CONFIG_DWC_AHSATA_PORT_ID 0 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR #define CONFIG_LBA48 - #define CONFIG_LIBATA #endif /* Framebuffer and LCD */ diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h new file mode 100644 index 0000000000..92dd845c70 --- /dev/null +++ b/include/configs/mx53ppd.h @@ -0,0 +1,248 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Jason Liu <r64343@freescale.com> + * + * Configuration settings for Freescale MX53 low cost board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/imx-regs.h> + +#define CONSOLE_DEV "ttymxc0" + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#define CONFIG_SYS_FSL_CLK + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + +#define CONFIG_HW_WATCHDOG +#define CONFIG_IMX_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT_MSECS 8000 + +#define CONFIG_MISC_INIT_R +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_MXC_GPIO +#define CONFIG_REVISION_TAG + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_NUM 2 + +#define CONFIG_SUPPORT_RAW_INITRD /* bootz raw initrd support */ + +/* Eth Configs */ +#define CONFIG_MII + +#define CONFIG_FEC_MXC +#define IMX_FEC_BASE FEC_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1F + +/* USB Configs */ +#define CONFIG_USB_EHCI_MX5 +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_MCS7830 +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_MXC_USB_PORT 1 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + +#define CONFIG_SYS_RTC_BUS_NUM 2 +#define CONFIG_SYS_I2C_RTC_ADDR 0x30 + +/* I2C Configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ + +/* PMIC Controller */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_DIALOG_POWER +#define CONFIG_POWER_FSL +#define CONFIG_POWER_FSL_MC13892 +#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 +#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Command definition */ +#define CONFIG_SUPPORT_RAW_INITRD + +#define CONFIG_ETHPRIME "FEC0" + +#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */ +#define CONFIG_SYS_TEXT_BASE 0x77800000 + +#define PPD_CONFIG_NFS \ + "nfsserver=192.168.252.95\0" \ + "gatewayip=192.168.252.95\0" \ + "netmask=255.255.255.0\0" \ + "ipaddr=192.168.252.99\0" \ + "kernsize=0x2000\0" \ + "use_dhcp=0\0" \ + "nfsroot=/opt/springdale/rd\0" \ + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \ + "${kern_ipconf} nfsroot=${nfsserver}:${nfsroot},v3,tcp rw\0" \ + "choose_ip=if test $use_dhcp = 1; then set kern_ipconf ip=dhcp; " \ + "set getcmd dhcp; else set kern_ipconf " \ + "ip=${ipaddr}:${nfsserver}:${gatewayip}:${netmask}::eth0:off; " \ + "set getcmd tftp; fi\0" \ + "nfs=run choose_ip setargs bootargs_nfs; ${getcmd} ${loadaddr} " \ + "${nfsserver}:${image}; bootm ${loadaddr}\0" \ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + PPD_CONFIG_NFS \ + "bootlimit=10\0" \ + "image=/boot/fitImage\0" \ + "fdt_high=0xffffffff\0" \ + "dev=mmc\0" \ + "devnum=0\0" \ + "rootdev=mmcblk0p\0" \ + "quiet=quiet loglevel=0\0" \ + "console=" CONSOLE_DEV "\0" \ + "lvds=ldb\0" \ + "setargs=setenv bootargs ${lvds} jtag=on mem=2G " \ + "vt.global_cursor_default=0 bootcause=${bootcause} ${quiet} " \ + "console=${console} ${rtc_status}\0" \ + "bootargs_emmc=setenv bootargs root=/dev/${rootdev}${partnum} ro " \ + "rootwait ${bootargs}\0" \ + "doquiet=if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \ + "then setenv quiet; fi\0" \ + "hasfirstboot=ext2load ${dev} ${devnum}:${partnum} 0x7000A000 " \ + "/boot/bootcause/firstboot\0" \ + "swappartitions=setexpr partnum 3 - ${partnum}\0" \ + "failbootcmd=" \ + "ppd_lcd_enable; " \ + "msg=\"Monitor failed to start. " \ + "Try again, or contact GE Service for support.\"; " \ + "echo $msg; " \ + "setenv stdout vga; " \ + "echo \"\n\n\n\n \" $msg; " \ + "setenv stdout serial; " \ + "mw.b 0x7000A000 0xbc; " \ + "mw.b 0x7000A001 0x00; " \ + "ext4write ${dev} ${devnum}:5 0x7000A000 /boot/failures 2\0" \ + "altbootcmd=" \ + "run doquiet; " \ + "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \ + "run hasfirstboot || setenv partnum 0; " \ + "if test ${partnum} != 0; then " \ + "setenv bootcause REVERT; " \ + "run swappartitions loadimage doboot; " \ + "fi; " \ + "run failbootcmd\0" \ + "loadimage=" \ + "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \ + "doboot=" \ + "echo Booting from ${dev}:${devnum}:${partnum} ...; " \ + "run setargs; " \ + "run bootargs_emmc; " \ + "bootm ${loadaddr}\0" \ + "tryboot=" \ + "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \ + "run loadimage || run swappartitions && run loadimage || " \ + "setenv partnum 0 && echo MISSING IMAGE;" \ + "run doboot; " \ + "run failbootcmd\0" \ + "video-mode=" \ + "lcd:800x480-24@60,monitor=lcd\0" \ + +#define CONFIG_MMCBOOTCOMMAND \ + "if mmc dev ${devnum}; then " \ + "run doquiet; " \ + "run tryboot; " \ + "fi; " \ + +#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND + +#define CONFIG_ARP_TIMEOUT 200UL + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + +#define CONFIG_SYS_MAXARGS 48 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0x70000000 +#define CONFIG_SYS_MEMTEST_END 0x70010000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_CMDLINE_EDITING + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) +#define PHYS_SDRAM_2 CSD1_BASE_ADDR +#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) +#define PHYS_SDRAM_SIZE (gd->ram_size) + +#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_CMD_FUSE +#define CONFIG_FSL_IIM + +#define CONFIG_SYS_I2C_SPEED 100000 + +/* I2C1 */ +#define CONFIG_SYS_NUM_I2C_BUSES 9 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \ + } + +#define CONFIG_BCH + +#define CONFIG_BOOTCOUNT_LIMIT + +/* Backlight Control */ +#define CONFIG_PWM_IMX +#define CONFIG_IMX6_PWM_PER_CLK 66666000 + +/* Framebuffer and LCD */ +#ifdef CONFIG_VIDEO + #define CONFIG_VIDEO_IPUV3 +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index 6b42b2b3c1..d649172d5f 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -23,12 +23,10 @@ /* SATA Configuration */ #ifdef CONFIG_CMD_SATA -#define CONFIG_DWC_AHSATA #define CONFIG_SYS_SATA_MAX_DEVICE 1 #define CONFIG_DWC_AHSATA_PORT_ID 0 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR #define CONFIG_LBA48 -#define CONFIG_LIBATA #endif /* Ethernet Configuration */ diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 5ef78a75ab..f4c9c28397 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -57,9 +57,9 @@ "videomode=video=ctfb:x:800,y:480,depth:24,pclk:29850,le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0\0" \ "mmcdev=2\0" \ "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ + "finduuid=part uuid mmc 2:2 uuid\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ + "root=PARTUUID=${uuid} rootwait rw\0" \ "loadbootscript=" \ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ @@ -67,6 +67,7 @@ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ + "run finduuid; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index b847906310..8e0d6df93d 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -49,12 +49,10 @@ * SATA Configs */ #ifdef CONFIG_CMD_SATA -#define CONFIG_DWC_AHSATA #define CONFIG_SYS_SATA_MAX_DEVICE 1 #define CONFIG_DWC_AHSATA_PORT_ID 0 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR #define CONFIG_LBA48 -#define CONFIG_LIBATA #endif #define CONFIG_FEC_MXC diff --git a/include/configs/novena.h b/include/configs/novena.h index dd0e637062..f82b6a44d2 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -108,12 +108,10 @@ /* SATA Configs */ #ifdef CONFIG_CMD_SATA -#define CONFIG_DWC_AHSATA #define CONFIG_SYS_SATA_MAX_DEVICE 1 #define CONFIG_DWC_AHSATA_PORT_ID 0 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR #define CONFIG_LBA48 -#define CONFIG_LIBATA #endif /* UART */ diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index df50325ab6..42f2153637 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -86,8 +86,49 @@ /* Environment */ #define CONFIG_PREBOOT "usb start" +#if !defined(CONFIG_SPL_BUILD) + +#include <config_distro_defaults.h> + +#define MEM_LAYOUT_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV + +#if defined(CONFIG_NAND) +#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=" \ + "run nandboot\0" + +#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ + #devtypel #instance " " +#endif /* CONFIG_NAND */ + +#define BOOTENV_DEV_UIMAGE_MMC(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=" \ + "setenv mmcdev " #instance"; " \ + "run mmcboot\0" + +#define BOOTENV_DEV_NAME_UIMAGE_MMC(devtypeu, devtypel, instance) \ + #devtypel #instance " " + +#define BOOTENV_DEV_ZIMAGE_MMC(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=" \ + "setenv mmcdev " #instance"; " \ + "run mmcbootz\0" + +#define BOOTENV_DEV_NAME_ZIMAGE_MMC(devtypeu, devtypel, instance) \ + #devtypel #instance " " + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(ZIMAGE_MMC, zimage_mmc, 0) \ + func(UIMAGE_MMC, uimage_mmc, 0) \ + func(NAND, nand, 0) + +#include <config_distro_bootcmd.h> + #define CONFIG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ + MEM_LAYOUT_ENV_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "bootenv=uEnv.txt\0" \ @@ -107,40 +148,39 @@ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ "importbootenv=echo Importing environment from mmc ...; " \ "env import -t ${loadaddr} ${filesize}\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source ${loadaddr}\0" \ + "mmcbootenv=" \ + "mmc dev ${mmcdev}; " \ + "if mmc rescan && run loadbootenv; then " \ + "run importbootenv; " \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...; " \ + "run uenvcmd; " \ + "fi; " \ + "fi\0" \ "loaduimage=setenv bootfile uImage; " \ "fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ "loadzimage=setenv bootfile zImage; " \ "fatload mmc ${mmcdev} ${loadaddr} zImage\0" \ - "loaddtb=fatload mmc ${mmcdev} ${fdtaddr} " CONFIG_DEFAULT_FDT_FILE "\0" \ - "mmcboot=echo Booting ${bootfile} from mmc ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr} - ${fdtaddr}\0" \ - "mmcbootz=echo Booting ${bootfile} from mmc ...; " \ - "run mmcargs; " \ - "bootz ${loadaddr} - ${fdtaddr}\0" \ + "loaddtb=fatload mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \ + "mmcboot=run mmcbootenv; " \ + "if run loaduimage && run loaddtb; then " \ + "echo Booting ${bootfile} from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr} - ${fdtaddr}; " \ + "fi\0" \ + "mmcbootz=run mmcbootenv; " \ + "if run loadzimage && run loaddtb; then " \ + "echo Booting ${bootfile} from mmc ...; " \ + "run mmcargs; " \ + "bootz ${loadaddr} - ${fdtaddr};" \ + "fi\0" \ "nandboot=echo Booting uImage from nand ...; " \ "run nandargs; " \ "nand read ${loadaddr} kernel; " \ "nand read ${fdtaddr} dtb; " \ - "bootm ${loadaddr} - ${fdtaddr}\0" + "bootm ${loadaddr} - ${fdtaddr}\0" \ + BOOTENV -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootenv; then " \ - "run importbootenv; " \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...; " \ - "run uenvcmd; " \ - "fi; " \ - "else " \ - "if run loadzimage && run loaddtb; then " \ - "run mmcbootz; fi; " \ - "if run loaduimage && run loaddtb; then " \ - "run mmcboot; fi; " \ - "run nandboot; " \ - "fi; " \ - "else run nandboot; fi" +#endif /* !CONFIG_SPL_BUILD */ #endif /* __CONFIG_H */ diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 3ecfb58918..b095814cda 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -93,7 +93,6 @@ #define CONFIG_PREBOOT \ "setenv preboot;" \ - "nand unlock;" \ "saveenv;" #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -192,7 +191,6 @@ "tftpboot $loadaddr zImage;" \ "bootz $loadaddr\0" \ "nandbootcommon=echo 'Booting kernel from NAND...';" \ - "nand unlock;" \ "run nandargs;" \ "run common_bootargs;" \ "run dump_bootargs;" \ diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 38d7412099..38a0055297 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -61,8 +61,6 @@ #define CONSOLEDEV "ttyO2" -#define CONFIG_LIBATA -#define CONFIG_SCSI_AHCI #define CONFIG_SCSI_AHCI_PLAT #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 #define CONFIG_SYS_SCSI_MAX_LUN 1 diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h index 55e716a22a..051416eab8 100644 --- a/include/configs/ot1200.h +++ b/include/configs/ot1200.h @@ -59,12 +59,10 @@ * SATA Configs */ #ifdef CONFIG_CMD_SATA -#define CONFIG_DWC_AHSATA #define CONFIG_SYS_SATA_MAX_DEVICE 1 #define CONFIG_DWC_AHSATA_PORT_ID 0 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR #define CONFIG_LBA48 -#define CONFIG_LIBATA #endif /* SPL */ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 1b665b2c15..07c192aecc 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -244,9 +244,7 @@ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_SATA_SIL #define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_LIBATA #define CONFIG_LBA48 #if defined(CONFIG_TARGET_P2020RDB) @@ -782,6 +780,7 @@ #ifdef CONFIG_USB_EHCI_HCD #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_DESC_BIG_ENDIAN #endif #endif diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index e9692048d1..d2302636ac 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -50,9 +50,7 @@ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_SATA_SIL3114 #define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_LIBATA #define CONFIG_LBA48 #ifndef __ASSEMBLY__ diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 75658fd489..f821b67c72 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -47,6 +47,13 @@ #define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M #define DFU_DEFAULT_POLL_TIMEOUT 300 +#define CONFIG_DFU_ENV_SETTINGS \ + "dfu_alt_info=uboot raw 0x2 0x400 mmcpart 1;" \ + "boot part 0 1;" \ + "/zImage ext4 0 1;" \ + "/imx6ul-pico-hobbit.dtb ext4 0 1;" \ + "rootfs part 0 2\0" \ + #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -58,14 +65,19 @@ "fdt_addr=0x83000000\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ "mmcautodetect=yes\0" \ - "dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \ + CONFIG_DFU_ENV_SETTINGS \ + "finduuid=part uuid mmc 0:2 uuid\0" \ + "partitions=" \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=boot,size=16MiB;name=rootfs,size=0,uuid=${uuid_gpt_rootfs}\0" \ + "setup_emmc=gpt write mmc 0 $partitions; reset;\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "root=PARTUUID=${uuid} rootwait rw\0" \ + "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ + "run finduuid; " \ "run mmcargs; " \ "if run loadfdt; then " \ "bootz ${loadaddr} - ${fdt_addr}; " \ @@ -144,6 +156,5 @@ #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_SYS_MMC_ENV_PART 0 -#define CONFIG_MMCROOT "/dev/mmcblk0p2" #endif /* __PICO_IMX6UL_CONFIG_H */ diff --git a/include/configs/puma_rk3399.h b/include/configs/puma_rk3399.h index 39d0786266..6523a7c34a 100644 --- a/include/configs/puma_rk3399.h +++ b/include/configs/puma_rk3399.h @@ -9,14 +9,6 @@ #include <configs/rk3399_common.h> -/* - * SPL @ 32kB for ~130kB - * ENV @ 240KB for 8kB - * FIT payload (ATF, U-Boot, FDT) @ 256kB - */ -#undef CONFIG_ENV_OFFSET -#define CONFIG_ENV_OFFSET (240 * 1024) - #if defined(CONFIG_ENV_IS_IN_MMC) #define CONFIG_SYS_MMC_ENV_DEV 1 #elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) diff --git a/include/configs/qemu-arm.h b/include/configs/qemu-arm.h index 4376a24787..c8852cef34 100644 --- a/include/configs/qemu-arm.h +++ b/include/configs/qemu-arm.h @@ -31,8 +31,6 @@ /* For block devices, QEMU emulates an ICH9 AHCI controller over PCI */ #define CONFIG_SYS_SCSI_MAX_SCSI_ID 6 -#define CONFIG_SCSI_AHCI -#define CONFIG_LIBATA /* Environment options */ #define CONFIG_ENV_SIZE SZ_64K diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 6deed0dcd7..30a98b8ada 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -31,6 +31,11 @@ #define CONFIG_ARCH_CPU_INIT +/* Generic Interrupt Controller Definitions */ +#define CONFIG_GICV2 +#define GICD_BASE 0xF1010000 +#define GICC_BASE 0xF1020000 + /* console */ #define CONFIG_SYS_CBSIZE 2048 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE @@ -39,34 +44,20 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400 } /* MEMORY */ +#if defined(CONFIG_R8A77970) +#define CONFIG_SYS_TEXT_BASE 0x58280000 +#else #define CONFIG_SYS_TEXT_BASE 0x50000000 +#endif #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE #define DRAM_RSV_SIZE 0x08000000 -#if defined(CONFIG_R8A7795) #define CONFIG_NR_DRAM_BANKS 4 -#define PHYS_SDRAM_1 (0x40000000 + DRAM_RSV_SIZE) -#define PHYS_SDRAM_1_SIZE (0x40000000u - DRAM_RSV_SIZE) -#define PHYS_SDRAM_2 0x500000000 -#define PHYS_SDRAM_2_SIZE 0x40000000u -#define PHYS_SDRAM_3 0x600000000 -#define PHYS_SDRAM_3_SIZE 0x40000000u -#define PHYS_SDRAM_4 0x700000000 -#define PHYS_SDRAM_4_SIZE 0x40000000u -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE -#elif defined(CONFIG_R8A7796) -#define CONFIG_NR_DRAM_BANKS 2 -#define PHYS_SDRAM_1 (0x40000000 + DRAM_RSV_SIZE) -#define PHYS_SDRAM_1_SIZE (0x80000000u - DRAM_RSV_SIZE) -#define PHYS_SDRAM_2 0x0600000000 -#define PHYS_SDRAM_2_SIZE 0x80000000u -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE -#endif +#define CONFIG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) +#define CONFIG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) #define CONFIG_SYS_LOAD_ADDR 0x48080000 #define CONFIG_VERY_BIG_RAM -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_SDRAM_SIZE +#define CONFIG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) #define CONFIG_SYS_MONITOR_BASE 0x00000000 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index 4ed8f5a6c7..3a2bf339b1 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -25,7 +25,7 @@ #define CONFIG_SYS_INIT_SP_ADDR 0x60100000 #define CONFIG_SYS_LOAD_ADDR 0x60800800 #define CONFIG_SPL_STACK 0x10081fff -#define CONFIG_SPL_TEXT_BASE 0x10081004 +#define CONFIG_SPL_TEXT_BASE 0x10081000 #define CONFIG_ROCKCHIP_MAX_INIT_SIZE (4 << 10) #define CONFIG_ROCKCHIP_CHIP_TAG "RK30" diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h new file mode 100644 index 0000000000..e915a562b9 --- /dev/null +++ b/include/configs/rk3128_common.h @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_RK3128_COMMON_H +#define __CONFIG_RK3128_COMMON_H + +#include "rockchip-common.h" + +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_MALLOC_LEN (32 << 20) +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) +#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */ +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) + +#define CONFIG_SYS_NS16550_MEM32 + +#define CONFIG_SYS_TEXT_BASE 0x60000000 +#define CONFIG_SYS_INIT_SP_ADDR 0x60100000 +#define CONFIG_SYS_LOAD_ADDR 0x60800800 + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + +/* MMC/SD IP block */ +#define CONFIG_BOUNCE_BUFFER + +#define CONFIG_SUPPORT_VFAT +#define CONFIG_FS_EXT4 + +/* RAW SD card / eMMC locations. */ +#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10) + +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CONFIG_NR_DRAM_BANKS 2 +#define SDRAM_MAX_SIZE 0x80000000 + +#define CONFIG_SPI_FLASH +#define CONFIG_SPI +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 + +#ifndef CONFIG_SPL_BUILD + +/* usb mass storage */ +#define CONFIG_USB_FUNCTION_MASS_STORAGE + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x60500000\0" \ + "pxefile_addr_r=0x60600000\0" \ + "fdt_addr_r=0x61f00000\0" \ + "kernel_addr_r=0x62000000\0" \ + "ramdisk_addr_r=0x64000000\0" + +#include <config_distro_bootcmd.h> +#define CONFIG_EXTRA_ENV_SETTINGS \ + ENV_MEM_LAYOUT_SETTINGS \ + "partitions=" PARTS_DEFAULT \ + BOOTENV + +#endif + +#endif diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index cfa5364710..0cb0762345 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -36,23 +36,11 @@ #define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x8000 - 0x800) #define CONFIG_ROCKCHIP_CHIP_TAG "RK31" -#ifdef CONFIG_TPL_BUILD -#define CONFIG_SPL_TEXT_BASE 0x10080804 -/* tpl size 1kb - 4byte RK31 header */ -#define CONFIG_SPL_MAX_SIZE (0x400 - 0x4) -#elif defined(CONFIG_SPL_BUILD) -/* spl size 32kb sram - 2kb bootrom - 1kb spl */ -#define CONFIG_SPL_MAX_SIZE (0x8000 - 0xC00) -#define CONFIG_SPL_TEXT_BASE 0x10080C00 +#define CONFIG_SPL_TEXT_BASE 0x10080800 +/* spl size 32kb sram - 2kb bootrom */ +#define CONFIG_SPL_MAX_SIZE (0x8000 - 0x800) #define CONFIG_SPL_FRAMEWORK 1 -#define CONFIG_SPL_CLK 1 -#define CONFIG_SPL_PINCTRL 1 -#define CONFIG_SPL_REGMAP 1 -#define CONFIG_SPL_SYSCON 1 -#define CONFIG_SPL_RAM 1 -#define CONFIG_SPL_DRIVERS_MISC_SUPPORT 1 #define CONFIG_ROCKCHIP_SERIAL 1 -#endif #define CONFIG_SPL_STACK 0x10087fff diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 2b8f618f72..e2f070fd1c 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -34,7 +34,7 @@ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TPL_BOOTROM_SUPPORT) # define CONFIG_SPL_TEXT_BASE 0x0 #else -# define CONFIG_SPL_TEXT_BASE 0xff704004 +# define CONFIG_SPL_TEXT_BASE 0xff704000 #endif /* MMC/SD IP block */ diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h index 35d948ae29..f465d35330 100644 --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h @@ -52,21 +52,13 @@ #define PARTS_DEFAULT \ "uuid_disk=${uuid_gpt_disk};" \ "name=loader1,start=32K,size=4000K,uuid=${uuid_gpt_loader1};" \ - "name=reserved1,size=64K,uuid=${uuid_gpt_reserved1};" \ - "name=reserved2,size=4M,uuid=${uuid_gpt_reserved2};" \ - "name=loader2,size=4MB,uuid=${uuid_gpt_loader2};" \ - "name=atf,size=4M,uuid=${uuid_gpt_atf};" \ + "name=loader2,start=8MB,size=4MB,uuid=${uuid_gpt_loader2};" \ + "name=trust,size=4M,uuid=${uuid_gpt_atf};" \ "name=boot,size=112M,bootable,uuid=${uuid_gpt_boot};" \ "name=rootfs,size=-,uuid="ROOT_UUID #endif -/* - * Rockchip SoCs use fixed ENV 32KB@(4MB-32KB) - */ -#define CONFIG_ENV_OFFSET (SZ_4M - SZ_32K) -#define CONFIG_ENV_SIZE SZ_32K - #define CONFIG_DISPLAY_BOARDINFO_LATE #endif /* _ROCKCHIP_COMMON_H_ */ diff --git a/include/configs/rpi.h b/include/configs/rpi.h index c499b45b32..cab8661779 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -76,7 +76,7 @@ #endif /* Console UART */ -#ifdef CONFIG_BCM2837 +#if defined (CONFIG_BCM2837) || defined(CONFIG_TARGET_RPI_0_W) #define CONFIG_BCM283X_MU_SERIAL #else #define CONFIG_PL01X_SERIAL diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h index 5ee45594a3..549839d4d6 100644 --- a/include/configs/rv1108_common.h +++ b/include/configs/rv1108_common.h @@ -9,7 +9,6 @@ #include <asm/arch/hardware.h> #include "rockchip-common.h" -#define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h index 77a12de963..33624e6c4e 100644 --- a/include/configs/salvator-x.h +++ b/include/configs/salvator-x.h @@ -12,74 +12,22 @@ #undef DEBUG -#define CONFIG_RCAR_BOARD_STRING "Salvator-X" - #include "rcar-gen3-common.h" -/* SCIF */ -#define CONFIG_CONS_SCIF2 -#define CONFIG_CONS_INDEX 2 -#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ - -/* [A] Hyper Flash */ -/* use to RPC(SPI Multi I/O Bus Controller) */ - /* Ethernet RAVB */ #define CONFIG_BITBANGMII #define CONFIG_BITBANGMII_MULTI /* Board Clock */ /* XTAL_CLK : 33.33MHz */ -#define RCAR_XTAL_CLK 33333333u -#define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK -/* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */ -/* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz */ -#define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) -#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2) -#define CONFIG_S3D2_CLK_FREQ (266666666u/2) -#define CONFIG_S3D4_CLK_FREQ (266666666u/4) +#define CONFIG_SYS_CLK_FREQ 33333333u /* Generic Timer Definitions (use in assembler source) */ #define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ -/* Generic Interrupt Controller Definitions */ -#define CONFIG_GICV2 -#define GICD_BASE 0xF1010000 -#define GICC_BASE 0xF1020000 - -/* i2c */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SH -#define CONFIG_SYS_I2C_SLAVE 0x60 -#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 1 -#define CONFIG_SYS_I2C_SH_SPEED0 400000 -#define CONFIG_SH_I2C_DATA_HIGH 4 -#define CONFIG_SH_I2C_DATA_LOW 5 -#define CONFIG_SH_I2C_CLOCK 10000000 - -#define CONFIG_SYS_I2C_POWERIC_ADDR 0x30 - -/* USB */ -#ifdef CONFIG_R8A7795 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 -#else -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#endif - -/* SDHI */ -#define CONFIG_SH_SDHI_FREQ 200000000 - /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) #define CONFIG_SYS_MMC_ENV_DEV 1 #define CONFIG_SYS_MMC_ENV_PART 2 -/* Module stop status bits */ -/* MFIS, SCIF1 */ -#define CONFIG_SMSTP2_ENA 0x00002040 -/* SCIF2 */ -#define CONFIG_SMSTP3_ENA 0x00000400 -/* INTC-AP, IRQC */ -#define CONFIG_SMSTP4_ENA 0x00000180 - #endif /* __SALVATOR_X_H */ diff --git a/include/configs/sama5d2_ptc.h b/include/configs/sama5d2_ptc.h deleted file mode 100644 index c52dcd4e8f..0000000000 --- a/include/configs/sama5d2_ptc.h +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Configuration settings for the SAMA5D2 PTC Engineering board. - * - * Copyright (C) 2016 Atmel - * Wenyou Yang <wenyou.yang@atmel.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "at91-sama5_common.h" - -/* serial console */ -#define CONFIG_ATMEL_USART -#define CONFIG_USART_BASE 0xf801c000 -#define CONFIG_USART_ID 24 - -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 - -#define CONFIG_SYS_TIMER_COUNTER 0xf804803c - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x210000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -#undef CONFIG_AT91_GPIO -#define CONFIG_ATMEL_PIO4 - -/* SDRAM */ -#define CONFIG_NR_DRAM_BANKS 1 - -/* SerialFlash */ -#ifdef CONFIG_CMD_SF -#define CONFIG_ATMEL_SPI -#define CONFIG_SPI_FLASH_ATMEL -#define CONFIG_SF_DEFAULT_BUS 0 -#define CONFIG_SF_DEFAULT_CS 0 -#define CONFIG_SF_DEFAULT_SPEED 30000000 -#endif - -/* NAND flash */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_ATMEL -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x80000000 -/* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -/* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ONFI_DETECTION -/* PMECC & PMERRLOC */ -#define CONFIG_ATMEL_NAND_HWECC -#define CONFIG_ATMEL_NAND_HW_PMECC -#endif - -/* USB device */ - -/* Ethernet Hardware */ -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_MACB_SEARCH_PHY - -#ifdef CONFIG_NAND_BOOT -#undef CONFIG_ENV_OFFSET -#undef CONFIG_ENV_OFFSET_REDUND -#undef CONFIG_BOOTCOMMAND -/* u-boot env in nand flash */ -#define CONFIG_ENV_OFFSET 0x200000 -#define CONFIG_ENV_OFFSET_REDUND 0x400000 -#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0xb80000 0x80000;" \ - "nand read 0x22000000 0x600000 0x600000;" \ - "bootz 0x22000000 - 0x21000000" -#endif - -/* SPL */ -#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_TEXT_BASE 0x200000 -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 - -#define CONFIG_SYS_MONITOR_LEN (512 << 10) - -#ifdef CONFIG_SPI_BOOT -#define CONFIG_SPL_SPI_LOAD -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 - -#elif CONFIG_NAND_BOOT -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_BASE -#endif -#define CONFIG_PMECC_CAP 8 -#define CONFIG_PMECC_SECTOR_SIZE 512 -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000 -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_OOBSIZE 224 -#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000 -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 -#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER - -#endif diff --git a/include/configs/sama5d2_ptc_ek.h b/include/configs/sama5d2_ptc_ek.h new file mode 100644 index 0000000000..d99eaee18f --- /dev/null +++ b/include/configs/sama5d2_ptc_ek.h @@ -0,0 +1,46 @@ +/* + * Configuration file for the SAMA5D2 PTC EK Board. + * + * Copyright (C) 2017 Microchip Technology Inc. + * Wenyou Yang <wenyou.yang@microchip.com> + * Ludovic Desroches <ludovic.desroches@microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "at91-sama5_common.h" + +#undef CONFIG_SYS_AT91_MAIN_CLOCK +#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ + +#define CONFIG_MISC_INIT_R + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x20000000 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +/* NAND Flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE BIT(21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE BIT(22) +#define CONFIG_SYS_NAND_ONFI_DETECTION +/* PMECC & PMERRLOC */ +#define CONFIG_ATMEL_NAND_HWECC +#define CONFIG_ATMEL_NAND_HW_PMECC +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index a0097fdbd9..817c9d920d 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -300,8 +300,6 @@ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#undef CONFIG_SCSI_AHCI - #ifdef CONFIG_SCSI_AHCI #define CONFIG_SATA_ULI5288 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 8a7debbceb..66e7c4fc8b 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -142,7 +142,6 @@ #ifdef CONFIG_NAND_DENALI #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_NAND_DENALI_ECC_SIZE 512 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS #endif @@ -294,7 +293,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); /* SPL NAND boot support */ #ifdef CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 #endif diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 4391a8cbc8..3855c564f9 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -34,6 +34,7 @@ #ifdef CONFIG_ARM64 #define CONFIG_BUILD_TARGET "u-boot.itb" +#define CONFIG_SYS_BOOTM_LEN (32 << 20) #endif /* Serial & console */ @@ -113,8 +114,6 @@ #define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */ #ifdef CONFIG_AHCI -#define CONFIG_LIBATA -#define CONFIG_SCSI_AHCI #define CONFIG_SCSI_AHCI_PLAT #define CONFIG_SUNXI_AHCI #define CONFIG_SYS_64BIT_LBA @@ -493,6 +492,20 @@ extern int soft_i2c_gpio_scl; #define SUNXI_MTDPARTS_DEFAULT #endif +#define PARTS_DEFAULT \ + "name=loader1,start=8k,size=32k,uuid=${uuid_gpt_loader1};" \ + "name=loader2,size=984k,uuid=${uuid_gpt_loader2};" \ + "name=esp,size=128M,bootable,uuid=${uuid_gpt_esp};" \ + "name=system,size=-,uuid=${uuid_gpt_system};" + +#define UUID_GPT_ESP "c12a7328-f81f-11d2-ba4b-00a0c93ec93b" + +#ifdef CONFIG_ARM64 +#define UUID_GPT_SYSTEM "b921b045-1df0-41c3-af44-4c6f280d3fae" +#else +#define UUID_GPT_SYSTEM "69dad710-2ce4-4e3c-b16c-21a1d49abed3" +#endif + #define CONSOLE_ENV_SETTINGS \ CONSOLE_STDIN_SETTINGS \ CONSOLE_STDOUT_SETTINGS @@ -511,6 +524,9 @@ extern int soft_i2c_gpio_scl; "console=ttyS0,115200\0" \ SUNXI_MTDIDS_DEFAULT \ SUNXI_MTDPARTS_DEFAULT \ + "uuid_gpt_esp=" UUID_GPT_ESP "\0" \ + "uuid_gpt_system=" UUID_GPT_SYSTEM "\0" \ + "partitions=" PARTS_DEFAULT "\0" \ BOOTCMD_SUNXI_COMPAT \ BOOTENV diff --git a/include/configs/syzygy_hub.h b/include/configs/syzygy_hub.h new file mode 100644 index 0000000000..4147b45ef0 --- /dev/null +++ b/include/configs/syzygy_hub.h @@ -0,0 +1,72 @@ +/* + * (C) Copyright 2012 Xilinx + * (C) Copyright 2017 Opal Kelly Inc. + * + * Configuration settings for the SYZYGY Hub development board + * See zynq-common.h for Zynq common configs + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_SYZYGY_HUB_H +#define __CONFIG_SYZYGY_HUB_H + +#define CONFIG_ZYNQ_I2C1 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x57 +#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0xFA + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fit_image=fit.itb\0" \ + "bitstream_image=download.bit\0" \ + "loadbit_addr=0x1000000\0" \ + "load_addr=0x2000000\0" \ + "fit_size=0x800000\0" \ + "flash_off=0x100000\0" \ + "nor_flash_off=0xE2100000\0" \ + "fdt_high=0x20000000\0" \ + "initrd_high=0x20000000\0" \ + "loadbootenv_addr=0x2000000\0" \ + "fdt_addr_r=0x1f00000\0" \ + "pxefile_addr_r=0x2000000\0" \ + "kernel_addr_r=0x2000000\0" \ + "scriptaddr=0x3000000\0" \ + "ramdisk_addr_r=0x3100000\0" \ + "bootenv=uEnv.txt\0" \ + "bootenv_dev=mmc\0" \ + "loadbootenv=load ${bootenv_dev} 0 ${loadbootenv_addr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from ${bootenv_dev} ...; " \ + "env import -t ${loadbootenv_addr} $filesize\0" \ + "bootenv_existence_test=test -e ${bootenv_dev} 0 /${bootenv}\0" \ + "setbootenv=if env run bootenv_existence_test; then " \ + "if env run loadbootenv; then " \ + "env run importbootenv; " \ + "fi; " \ + "fi; \0" \ + "sd_loadbootenv=set bootenv_dev mmc && " \ + "run setbootenv \0" \ + "usb_loadbootenv=set bootenv_dev usb && usb start && run setbootenv\0" \ + "preboot=if test $modeboot = sdboot; then " \ + "run sd_loadbootenv; " \ + "echo Checking if uenvcmd is set ...; " \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...; " \ + "run uenvcmd; " \ + "fi; " \ + "fi; \0" \ + "sdboot=echo Copying FPGA Bitstream from SD to RAM... && " \ + "load mmc 0 ${loadbit_addr} ${bitstream_image} && " \ + "echo Programming FPGA... && " \ + "fpga loadb 0 ${loadbit_addr} ${filesize} && " \ + "echo Copying FIT from SD to RAM... && " \ + "load mmc 0 ${load_addr} ${fit_image} && " \ + "bootm ${load_addr}\0" \ + "jtagboot=echo TFTPing FIT to RAM... && " \ + "tftpboot ${load_addr} ${fit_image} && " \ + "bootm ${load_addr}\0" \ + DFU_ALT_INFO \ + BOOTENV + +#include <configs/zynq-common.h> + +#endif /* __CONFIG_SYZYGY_HUB_H */ diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index 4938f43985..5a69708e30 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -209,9 +209,6 @@ /* SATA */ #ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_LIBATA -#define CONFIG_FSL_SATA - #define CONFIG_SYS_SATA_MAX_DEVICE 2 #define CONFIG_SATA1 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index 849d4a6aec..3a3bab0fea 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -78,12 +78,10 @@ /* SATA */ #ifdef CONFIG_CMD_SATA -#define CONFIG_DWC_AHSATA #define CONFIG_SYS_SATA_MAX_DEVICE 1 #define CONFIG_DWC_AHSATA_PORT_ID 0 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR #define CONFIG_LBA48 -#define CONFIG_LIBATA #endif /* USB */ diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h index a7001e76aa..6e95aa1626 100644 --- a/include/configs/theadorable.h +++ b/include/configs/theadorable.h @@ -65,8 +65,6 @@ /* SATA support */ #define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_SATA_MV -#define CONFIG_LIBATA #define CONFIG_LBA48 /* Additional FS support/configuration */ diff --git a/include/configs/turris_omnia.h b/include/configs/turris_omnia.h index d2c3e57570..3dbd2cacba 100644 --- a/include/configs/turris_omnia.h +++ b/include/configs/turris_omnia.h @@ -53,8 +53,6 @@ /* * SATA/SCSI/AHCI configuration */ -#define CONFIG_LIBATA -#define CONFIG_SCSI_AHCI #define CONFIG_SCSI_AHCI_PLAT #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 #define CONFIG_SYS_SCSI_MAX_LUN 1 diff --git a/include/configs/udoo.h b/include/configs/udoo.h index bcce41db8a..989014a177 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -25,12 +25,10 @@ /* SATA Configs */ #ifdef CONFIG_CMD_SATA -#define CONFIG_DWC_AHSATA #define CONFIG_SYS_SATA_MAX_DEVICE 1 #define CONFIG_DWC_AHSATA_PORT_ID 0 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR #define CONFIG_LBA48 -#define CONFIG_LIBATA #endif /* Network support */ diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h index b54e63c2a2..dfd6436b3c 100644 --- a/include/configs/ulcb.h +++ b/include/configs/ulcb.h @@ -12,96 +12,22 @@ #undef DEBUG -#define CONFIG_RCAR_BOARD_STRING "ULCB" - #include "rcar-gen3-common.h" -/* M3 ULCB has 2 banks, each with 1 GiB of RAM */ -#if defined(CONFIG_R8A7796) -#undef PHYS_SDRAM_1_SIZE -#undef PHYS_SDRAM_2_SIZE -#define PHYS_SDRAM_1_SIZE (0x40000000u - DRAM_RSV_SIZE) -#define PHYS_SDRAM_2_SIZE 0x40000000u -#endif - -/* SCIF */ -#define CONFIG_CONS_SCIF2 -#define CONFIG_CONS_INDEX 2 -#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ - -/* [A] Hyper Flash */ -/* use to RPC(SPI Multi I/O Bus Controller) */ - /* Ethernet RAVB */ -#define CONFIG_PHY_MICREL #define CONFIG_BITBANGMII #define CONFIG_BITBANGMII_MULTI /* Board Clock */ /* XTAL_CLK : 33.33MHz */ -#define RCAR_XTAL_CLK 33333333u -#define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK -/* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */ -/* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz */ -#define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) -#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2) -#define CONFIG_S3D2_CLK_FREQ (266666666u/2) -#define CONFIG_S3D4_CLK_FREQ (266666666u/4) +#define CONFIG_SYS_CLK_FREQ 33333333u /* Generic Timer Definitions (use in assembler source) */ #define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ -/* Generic Interrupt Controller Definitions */ -#define CONFIG_GICV2 -#define GICD_BASE 0xF1010000 -#define GICC_BASE 0xF1020000 - -/* CPLD SPI */ -#define CONFIG_CMD_SPI -#define CONFIG_SOFT_SPI -#define SPI_DELAY udelay(0) -#define SPI_SDA(val) ulcb_softspi_sda(val) -#define SPI_SCL(val) ulcb_softspi_scl(val) -#define SPI_READ ulcb_softspi_read() -#ifndef __ASSEMBLY__ -void ulcb_softspi_sda(int); -void ulcb_softspi_scl(int); -unsigned char ulcb_softspi_read(void); -#endif - -/* i2c */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SH -#define CONFIG_SYS_I2C_SLAVE 0x60 -#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 1 -#define CONFIG_SYS_I2C_SH_SPEED0 400000 -#define CONFIG_SH_I2C_DATA_HIGH 4 -#define CONFIG_SH_I2C_DATA_LOW 5 -#define CONFIG_SH_I2C_CLOCK 10000000 - -#define CONFIG_SYS_I2C_POWERIC_ADDR 0x30 - -/* USB */ -#ifdef CONFIG_R8A7795 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 -#else -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#endif - -/* SDHI */ -#define CONFIG_SH_SDHI_FREQ 200000000 - /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) #define CONFIG_SYS_MMC_ENV_DEV 1 #define CONFIG_SYS_MMC_ENV_PART 2 -/* Module stop status bits */ -/* MFIS, SCIF1 */ -#define CONFIG_SMSTP2_ENA 0x00002040 -/* SCIF2 */ -#define CONFIG_SMSTP3_ENA 0x00000400 -/* INTC-AP, IRQC */ -#define CONFIG_SMSTP4_ENA 0x00000180 - #endif /* __ULCB_H */ diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 6f4d67ea8a..453f3db9eb 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -71,13 +71,8 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_ONFI_DETECTION - -#define CONFIG_NAND_DENALI_ECC_SIZE 1024 - #define CONFIG_SYS_NAND_REGS_BASE 0x68100000 #define CONFIG_SYS_NAND_DATA_BASE 0x68000000 - -#define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 /* SD/MMC */ diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 97d193ba49..e42bfc51f8 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -26,12 +26,10 @@ /* SATA Configs */ #ifdef CONFIG_CMD_SATA -#define CONFIG_DWC_AHSATA #define CONFIG_SYS_SATA_MAX_DEVICE 1 #define CONFIG_DWC_AHSATA_PORT_ID 0 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR #define CONFIG_LBA48 -#define CONFIG_LIBATA #endif #define CONFIG_SYS_MEMTEST_START 0x10000000 diff --git a/include/configs/wb45n.h b/include/configs/wb45n.h new file mode 100644 index 0000000000..8989d55f53 --- /dev/null +++ b/include/configs/wb45n.h @@ -0,0 +1,161 @@ +/* + * Configuation settings for the WB45N CPU Module. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H__ +#define __CONFIG_H__ + +#include <asm/hardware.h> + +#define CONFIG_SYS_TEXT_BASE 0x23f00000 + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* general purpose I/O */ +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ +#define CONFIG_AT91_GPIO + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 MB */ + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) + +/* NAND flash */ +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 + +/* PMECC & PMERRLOC */ +#define CONFIG_ATMEL_NAND_HWECC 1 +#define CONFIG_ATMEL_NAND_HW_PMECC 1 +#define CONFIG_PMECC_CAP 4 +#define CONFIG_PMECC_SECTOR_SIZE 512 + +#define CONFIG_MTD_DEVICE +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_PARTITIONS +#define CONFIG_RBTREE +#define CONFIG_LZO + +/* Ethernet */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_MACB_SEARCH_PHY +#define CONFIG_ETHADDR C0:EE:40:00:00:00 +#define CONFIG_ENV_OVERWRITE 1 + +/* System */ +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END 0x23e00000 + +#ifdef CONFIG_SYS_USE_NANDFLASH +/* bootstrap + u-boot + env + linux in nandflash */ +#define CONFIG_ENV_OFFSET 0xa0000 +#define CONFIG_ENV_OFFSET_REDUND 0xc0000 +#define CONFIG_ENV_SIZE 0x20000 /* 1 block = 128 kB */ + +#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xe0000 0x280000; " \ + "run _mtd; bootm" + +#define MTDIDS_DEFAULT "nand0=atmel_nand" +#define MTDPARTS_DEFAULT "mtdparts=atmel_nand:" \ + "128K(at91bs)," \ + "512K(u-boot)," \ + "128K(u-boot-env)," \ + "128K(redund-env)," \ + "2560K(kernel-a)," \ + "2560K(kernel-b)," \ + "38912K(rootfs-a)," \ + "38912K(rootfs-b)," \ + "46208K(user)," \ + "512K(logs)" + +#else +#error No boot method selected, please select 'CONFIG_SYS_USE_NANDFLASH' +#endif + +#define CONFIG_BOOTARGS "console=ttyS0,115200 earlyprintk " \ + "rw noinitrd mem=64M " \ + "rootfstype=ubifs root=ubi0:rootfs ubi.mtd=6" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "_mtd=mtdparts default; setenv bootargs ${bootargs} ${mtdparts}\0" \ + "autoload=no\0" \ + "autostart=no\0" \ + "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ + "\0" + +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000) + +/* SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x300000 +#define CONFIG_SPL_MAX_SIZE 0x6000 +#define CONFIG_SPL_STACK 0x308000 + +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SYS_MONITOR_LEN (512 << 10) + +#define CONFIG_SYS_MASTER_CLOCK 132096000 +#define CONFIG_SYS_AT91_PLLA 0x20c73f03 +#define CONFIG_SYS_MCKR 0x1301 +#define CONFIG_SYS_MCKR_CSS 0x1302 + +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 +#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER + +#endif /* __CONFIG_H__ */ diff --git a/include/configs/wb50n.h b/include/configs/wb50n.h new file mode 100644 index 0000000000..4ab81c864b --- /dev/null +++ b/include/configs/wb50n.h @@ -0,0 +1,139 @@ +/* + * Configuation settings for the WB50N CPU Module. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/hardware.h> + +#define CONFIG_SYS_TEXT_BASE 0x23f00000 + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ + +#define CONFIG_ARCH_CPU_INIT + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#define CONFIG_IMAGE_FORMAT_LEGACY + +/* general purpose I/O */ +#define CONFIG_AT91_GPIO + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_DBGU + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_INIT_SP_ADDR 0x310000 +#else +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) +#endif + +#define CONFIG_SYS_MEMTEST_START 0x21000000 +#define CONFIG_SYS_MEMTEST_END 0x22000000 +#define CONFIG_SYS_ALT_MEMTEST + +/* NAND flash */ +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ONFI_DETECTION +/* PMECC & PMERRLOC */ +#define CONFIG_ATMEL_NAND_HWECC +#define CONFIG_ATMEL_NAND_HW_PMECC +#define CONFIG_PMECC_CAP 8 +#define CONFIG_PMECC_SECTOR_SIZE 512 + +/* Ethernet Hardware */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_MACB_SEARCH_PHY +#define CONFIG_RGMII +#define CONFIG_ETHADDR C0:EE:40:00:00:00 +#define CONFIG_ENV_OVERWRITE 1 + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autoload=no\0" \ + "autostart=no\0" + +/* bootstrap + u-boot + env in nandflash */ +#define CONFIG_ENV_OFFSET 0xA0000 +#define CONFIG_ENV_OFFSET_REDUND 0xC0000 +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_BOOTCOMMAND \ + "nand read 0x22000000 0x000e0000 0x500000; " \ + "bootm" + +#define CONFIG_BOOTARGS \ + "rw rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs" + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) + +/* SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x300000 +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SYS_MONITOR_LEN (512 << 10) + +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 +#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER + +#endif diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 6422852010..064c546403 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -28,10 +28,7 @@ #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* SATA AHCI storage */ - -#define CONFIG_SCSI_AHCI #ifdef CONFIG_SCSI_AHCI -#define CONFIG_LIBATA #define CONFIG_LBA48 #define CONFIG_SYS_64BIT_LBA diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 8526ba0e88..9997fd0959 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -42,7 +42,6 @@ /* Serial setup */ #define CONFIG_ARM_DCC #define CONFIG_CPU_ARMV8 -#define CONFIG_ZYNQ_SERIAL #define CONFIG_CONS_INDEX 0 #define CONFIG_SYS_BAUDRATE_TABLE \ @@ -127,6 +126,7 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_LONGHELP #define CONFIG_CMDLINE_EDITING +#define CONFIG_PANIC_HANG #define CONFIG_SYS_MAXARGS 64 /* Ethernet driver */ @@ -158,8 +158,6 @@ #endif #ifdef CONFIG_SATA_CEVA -#define CONFIG_LIBATA -#define CONFIG_SCSI_AHCI #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 #define CONFIG_SYS_SCSI_MAX_LUN 1 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ @@ -236,6 +234,15 @@ #define CONFIG_SPL_FRAMEWORK +#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT) +# define CONFIG_SPL_SPI_LOAD +# define CONFIG_SYS_SPI_KERNEL_OFFS 0x80000 +# define CONFIG_SYS_SPI_ARGS_OFFS 0xa0000 +# define CONFIG_SYS_SPI_ARGS_SIZE 0xa0000 + +# define CONFIG_SYS_SPI_U_BOOT_OFFS 0x170000 +#endif + /* u-boot is like dtb */ #define CONFIG_SPL_FS_LOAD_ARGS_NAME "u-boot.bin" #define CONFIG_SYS_SPL_ARGS_ADDR 0x8000000 @@ -260,14 +267,14 @@ # define CONFIG_SPL_ENV_SUPPORT # define CONFIG_SPL_HASH_SUPPORT # define CONFIG_ENV_MAX_ENTRIES 10 +#endif -# define CONFIG_SYS_SPL_MALLOC_START 0x20000000 -# define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20000000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 #ifdef CONFIG_SPL_SYS_MALLOC_SIMPLE # error "Disable CONFIG_SPL_SYS_MALLOC_SIMPLE. Full malloc needs to be used" #endif -#endif #define CONFIG_BOARD_EARLY_INIT_F diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index b9599c73a6..b10cb3f572 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -33,7 +33,6 @@ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} #define CONFIG_ARM_DCC -#define CONFIG_ZYNQ_SERIAL /* Ethernet driver */ #if defined(CONFIG_ZYNQ_GEM) @@ -157,12 +156,6 @@ /* Environment */ #ifndef CONFIG_ENV_IS_NOWHERE -# ifdef CONFIG_MTD_NOR_FLASH -/* Environment in NOR flash */ -# elif defined(CONFIG_ZYNQ_QSPI) -/* Environment in Serial Flash */ -# endif - # define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE # define CONFIG_ENV_OFFSET 0xE0000 #endif @@ -293,16 +286,11 @@ GENERATED_GBL_DATA_SIZE) /* Enable the PL to be downloaded */ -#define CONFIG_FPGA -#define CONFIG_FPGA_XILINX #define CONFIG_FPGA_ZYNQPL /* FIT support */ #define CONFIG_IMAGE_FORMAT_LEGACY /* enable also legacy image format */ -/* FDT support */ -#define CONFIG_DISPLAY_BOARDINFO_LATE - /* Extend size of kernel image for uncompression */ #define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) @@ -325,7 +313,6 @@ /* Disable dcache for SPL just for sure */ #ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_DCACHE_OFF -#undef CONFIG_FPGA #endif /* Address in RAM where the parameters must be copied by SPL. */ @@ -357,12 +344,9 @@ /* 3 * 64kB blocks of OCM - one is on the top because of bootrom */ #define CONFIG_SPL_MAX_SIZE 0x30000 -/* The highest 64k OCM address */ -#define OCM_HIGH_ADDR 0xffff0000 - /* On the top of OCM space */ -#define CONFIG_SYS_SPL_MALLOC_START OCM_HIGH_ADDR -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x2000 +#define CONFIG_SYS_SPL_MALLOC_START CONFIG_SPL_STACK_R_ADDR +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x2000000 /* * SPL stack position - and stack goes down diff --git a/include/configs/zynq_cse.h b/include/configs/zynq_cse.h new file mode 100644 index 0000000000..dd65b52343 --- /dev/null +++ b/include/configs/zynq_cse.h @@ -0,0 +1,53 @@ +/* + * (C) Copyright 2013 - 2017 Xilinx. + * + * Configuration settings for the Xilinx Zynq CSE board. + * See zynq-common.h for Zynq common configs + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQ_CSE_H +#define __CONFIG_ZYNQ_CSE_H + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_SYS_ICACHE_OFF + +#include <configs/zynq-common.h> + +/* Undef unneeded configs */ +#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_BOARD_LATE_INIT +#undef CONFIG_BOOTCOMMAND +#undef CONFIG_ENV_SIZE +#undef CONFIG_CMDLINE_EDITING +#undef CONFIG_AUTO_COMPLETE +#undef CONFIG_ZLIB +#undef CONFIG_GZIP + +#undef CONFIG_SYS_LONGHELP + +#undef CONFIG_SYS_CBSIZE +#undef CONFIG_BOOTM_VXWORKS +#undef CONFIG_BOOTM_LINUX + +#define CONFIG_SYS_CBSIZE 1024 + +#define CONFIG_ENV_SIZE 400 +#undef CONFIG_SYS_INIT_RAM_ADDR +#undef CONFIG_SYS_INIT_RAM_SIZE +#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFDE000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#undef CONFIG_SPL_BSS_START_ADDR +#undef CONFIG_SPL_BSS_MAX_SIZE +#define CONFIG_SPL_BSS_START_ADDR 0x20000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x8000 + +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN 0x1000 + +#define CONFIG_SYS_SDRAM_BASE 0xfffc0000 +#define CONFIG_SYS_SDRAM_SIZE 0x40000 + +#endif /* __CONFIG_ZYNQ_CSE_H */ diff --git a/include/dt-bindings/clock/r8a77970-cpg-mssr.h b/include/dt-bindings/clock/r8a77970-cpg-mssr.h new file mode 100644 index 0000000000..4146395595 --- /dev/null +++ b/include/dt-bindings/clock/r8a77970-cpg-mssr.h @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2016 Renesas Electronics Corp. + * Copyright (C) 2017 Cogent Embedded, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* r8a77970 CPG Core Clocks */ +#define R8A77970_CLK_Z2 0 +#define R8A77970_CLK_ZR 1 +#define R8A77970_CLK_ZTR 2 +#define R8A77970_CLK_ZTRD2 3 +#define R8A77970_CLK_ZT 4 +#define R8A77970_CLK_ZX 5 +#define R8A77970_CLK_S1D1 6 +#define R8A77970_CLK_S1D2 7 +#define R8A77970_CLK_S1D4 8 +#define R8A77970_CLK_S2D1 9 +#define R8A77970_CLK_S2D2 10 +#define R8A77970_CLK_S2D4 11 +#define R8A77970_CLK_LB 12 +#define R8A77970_CLK_CL 13 +#define R8A77970_CLK_ZB3 14 +#define R8A77970_CLK_ZB3D2 15 +#define R8A77970_CLK_DDR 16 +#define R8A77970_CLK_CR 17 +#define R8A77970_CLK_CRD2 18 +#define R8A77970_CLK_SD0H 19 +#define R8A77970_CLK_SD0 20 +#define R8A77970_CLK_RPC 21 +#define R8A77970_CLK_RPCD2 22 +#define R8A77970_CLK_MSO 23 +#define R8A77970_CLK_CANFD 24 +#define R8A77970_CLK_CSI0 25 +#define R8A77970_CLK_FRAY 26 +#define R8A77970_CLK_CP 27 +#define R8A77970_CLK_CPEX 28 +#define R8A77970_CLK_R 29 +#define R8A77970_CLK_OSC 30 + +#endif /* __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r8a77995-cpg-mssr.h b/include/dt-bindings/clock/r8a77995-cpg-mssr.h new file mode 100644 index 0000000000..4e8ae3dee5 --- /dev/null +++ b/include/dt-bindings/clock/r8a77995-cpg-mssr.h @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2017 Glider bvba + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* r8a77995 CPG Core Clocks */ +#define R8A77995_CLK_Z2 0 +#define R8A77995_CLK_ZG 1 +#define R8A77995_CLK_ZTR 2 +#define R8A77995_CLK_ZT 3 +#define R8A77995_CLK_ZX 4 +#define R8A77995_CLK_S0D1 5 +#define R8A77995_CLK_S1D1 6 +#define R8A77995_CLK_S1D2 7 +#define R8A77995_CLK_S1D4 8 +#define R8A77995_CLK_S2D1 9 +#define R8A77995_CLK_S2D2 10 +#define R8A77995_CLK_S2D4 11 +#define R8A77995_CLK_S3D1 12 +#define R8A77995_CLK_S3D2 13 +#define R8A77995_CLK_S3D4 14 +#define R8A77995_CLK_S1D4C 15 +#define R8A77995_CLK_S3D1C 16 +#define R8A77995_CLK_S3D2C 17 +#define R8A77995_CLK_S3D4C 18 +#define R8A77995_CLK_LB 19 +#define R8A77995_CLK_CL 20 +#define R8A77995_CLK_ZB3 21 +#define R8A77995_CLK_ZB3D2 22 +#define R8A77995_CLK_CR 23 +#define R8A77995_CLK_CRD2 24 +#define R8A77995_CLK_SD0H 25 +#define R8A77995_CLK_SD0 26 +#define R8A77995_CLK_SSP2 27 +#define R8A77995_CLK_SSP1 28 +#define R8A77995_CLK_RPC 29 +#define R8A77995_CLK_RPCD2 30 +#define R8A77995_CLK_ZA2 31 +#define R8A77995_CLK_ZA8 32 +#define R8A77995_CLK_Z2D 33 +#define R8A77995_CLK_CANFD 34 +#define R8A77995_CLK_MSO 35 +#define R8A77995_CLK_R 36 +#define R8A77995_CLK_OSC 37 +#define R8A77995_CLK_LV0 38 +#define R8A77995_CLK_LV1 39 +#define R8A77995_CLK_CP 40 + +#endif /* __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/rk3128-cru.h b/include/dt-bindings/clock/rk3128-cru.h new file mode 100644 index 0000000000..476268a78b --- /dev/null +++ b/include/dt-bindings/clock/rk3128-cru.h @@ -0,0 +1,190 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_GPLL 3 +#define ARMCLK 4 + +/* sclk gates (special clocks) */ +#define SCLK_GPU 64 +#define SCLK_SPI 65 +#define SCLK_SDMMC 68 +#define SCLK_SDIO 69 +#define SCLK_EMMC 71 +#define SCLK_NANDC 76 +#define SCLK_UART0 77 +#define SCLK_UART1 78 +#define SCLK_UART2 79 +#define SCLK_I2S 82 +#define SCLK_SPDIF 83 +#define SCLK_TIMER0 85 +#define SCLK_TIMER1 86 +#define SCLK_TIMER2 87 +#define SCLK_TIMER3 88 +#define SCLK_SARADC 91 +#define SCLK_OTGPHY0 93 +#define SCLK_LCDC 100 +#define SCLK_HDMI 109 +#define SCLK_HEVC 111 +#define SCLK_I2S_OUT 113 +#define SCLK_SDMMC_DRV 114 +#define SCLK_SDIO_DRV 115 +#define SCLK_EMMC_DRV 117 +#define SCLK_SDMMC_SAMPLE 118 +#define SCLK_SDIO_SAMPLE 119 +#define SCLK_EMMC_SAMPLE 121 +#define SCLK_PVTM_CORE 123 +#define SCLK_PVTM_GPU 124 +#define SCLK_PVTM_VIDEO 125 +#define SCLK_MAC 151 +#define SCLK_MACREF 152 +#define SCLK_SFC 160 + +#define DCLK_LCDC 190 + +/* aclk gates */ +#define ACLK_DMAC2 194 +#define ACLK_VIO0 197 +#define ACLK_VIO1 203 +#define ACLK_VCODEC 208 +#define ACLK_CPU 209 +#define ACLK_PERI 210 + +/* pclk gates */ +#define PCLK_SARADC 318 +#define PCLK_GPIO0 320 +#define PCLK_GPIO1 321 +#define PCLK_GPIO2 322 +#define PCLK_GPIO3 323 +#define PCLK_GRF 329 +#define PCLK_I2C0 332 +#define PCLK_I2C1 333 +#define PCLK_I2C2 334 +#define PCLK_I2C3 335 +#define PCLK_SPI 338 +#define PCLK_UART0 341 +#define PCLK_UART1 342 +#define PCLK_UART2 343 +#define PCLK_PWM 350 +#define PCLK_TIMER 353 +#define PCLK_HDMI 360 +#define PCLK_CPU 362 +#define PCLK_PERI 363 +#define PCLK_DDRUPCTL 364 +#define PCLK_WDT 368 + +/* hclk gates */ +#define HCLK_OTG0 449 +#define HCLK_OTG1 450 +#define HCLK_NANDC 453 +#define HCLK_SDMMC 456 +#define HCLK_SDIO 457 +#define HCLK_EMMC 459 +#define HCLK_I2S 462 +#define HCLK_LCDC 465 +#define HCLK_ROM 467 +#define HCLK_VIO_BUS 472 +#define HCLK_VCODEC 476 +#define HCLK_CPU 477 +#define HCLK_PERI 478 + +#define CLK_NR_CLKS (HCLK_PERI + 1) + +/* soft-reset indices */ +#define SRST_CORE0 0 +#define SRST_CORE1 1 +#define SRST_CORE0_DBG 4 +#define SRST_CORE1_DBG 5 +#define SRST_CORE0_POR 8 +#define SRST_CORE1_POR 9 +#define SRST_L2C 12 +#define SRST_TOPDBG 13 +#define SRST_STRC_SYS_A 14 +#define SRST_PD_CORE_NIU 15 + +#define SRST_TIMER2 16 +#define SRST_CPUSYS_H 17 +#define SRST_AHB2APB_H 19 +#define SRST_TIMER3 20 +#define SRST_INTMEM 21 +#define SRST_ROM 22 +#define SRST_PERI_NIU 23 +#define SRST_I2S 24 +#define SRST_DDR_PLL 25 +#define SRST_GPU_DLL 26 +#define SRST_TIMER0 27 +#define SRST_TIMER1 28 +#define SRST_CORE_DLL 29 +#define SRST_EFUSE_P 30 +#define SRST_ACODEC_P 31 + +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_UART0 39 +#define SRST_UART1 40 +#define SRST_UART2 41 +#define SRST_I2C0 43 +#define SRST_I2C1 44 +#define SRST_I2C2 45 +#define SRST_SFC 47 + +#define SRST_PWM0 48 +#define SRST_DAP 51 +#define SRST_DAP_SYS 52 +#define SRST_GRF 55 +#define SRST_PERIPHSYS_A 57 +#define SRST_PERIPHSYS_H 58 +#define SRST_PERIPHSYS_P 59 +#define SRST_CPU_PERI 61 +#define SRST_EMEM_PERI 62 +#define SRST_USB_PERI 63 + +#define SRST_DMA2 64 +#define SRST_MAC 66 +#define SRST_NANDC 68 +#define SRST_USBOTG0 69 +#define SRST_OTGC0 71 +#define SRST_USBOTG1 72 +#define SRST_OTGC1 74 +#define SRST_DDRMSCH 79 + +#define SRST_MMC0 81 +#define SRST_SDIO 82 +#define SRST_EMMC 83 +#define SRST_SPI0 84 +#define SRST_WDT 86 +#define SRST_SARADC 87 +#define SRST_DDRPHY 88 +#define SRST_DDRPHY_P 89 +#define SRST_DDRCTRL 90 +#define SRST_DDRCTRL_P 91 + +#define SRST_HDMI_P 96 +#define SRST_VIO_BUS_H 99 +#define SRST_UTMI0 103 +#define SRST_UTMI1 104 +#define SRST_USBPOR 105 + +#define SRST_VCODEC_A 112 +#define SRST_VCODEC_H 113 +#define SRST_VIO1_A 114 +#define SRST_HEVC 115 +#define SRST_VCODEC_NIU_A 116 +#define SRST_LCDC1_A 117 +#define SRST_LCDC1_H 118 +#define SRST_LCDC1_D 119 +#define SRST_GPU 120 +#define SRST_GPU_NIU_A 122 + +#define SRST_DBG_P 131 + +#endif diff --git a/include/dt-bindings/clock/snps,hsdk-cgu.h b/include/dt-bindings/clock/snps,hsdk-cgu.h new file mode 100644 index 0000000000..813ab71531 --- /dev/null +++ b/include/dt-bindings/clock/snps,hsdk-cgu.h @@ -0,0 +1,40 @@ +/* + * Synopsys HSDK SDP CGU clock driver dts bindings + * + * Copyright (C) 2017 Synopsys + * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __DT_BINDINGS_CLK_HSDK_CGU_H_ +#define __DT_BINDINGS_CLK_HSDK_CGU_H_ + +#define CLK_ARC_PLL 0 +#define CLK_ARC 1 +#define CLK_DDR_PLL 2 +#define CLK_SYS_PLL 3 +#define CLK_SYS_APB 4 +#define CLK_SYS_AXI 5 +#define CLK_SYS_ETH 6 +#define CLK_SYS_USB 7 +#define CLK_SYS_SDIO 8 +#define CLK_SYS_HDMI 9 +#define CLK_SYS_GFX_CORE 10 +#define CLK_SYS_GFX_DMA 11 +#define CLK_SYS_GFX_CFG 12 +#define CLK_SYS_DMAC_CORE 13 +#define CLK_SYS_DMAC_CFG 14 +#define CLK_SYS_SDIO_REF 15 +#define CLK_SYS_SPI_REF 16 +#define CLK_SYS_I2C_REF 17 +#define CLK_SYS_UART_REF 18 +#define CLK_SYS_EBI_REF 19 +#define CLK_TUN_PLL 20 +#define CLK_TUN 21 +#define CLK_HDMI_PLL 22 +#define CLK_HDMI 23 + +#endif /* __DT_BINDINGS_CLK_HSDK_CGU_H_ */ diff --git a/include/dt-bindings/gpio/uniphier-gpio.h b/include/dt-bindings/gpio/uniphier-gpio.h new file mode 100644 index 0000000000..9f0ad174f6 --- /dev/null +++ b/include/dt-bindings/gpio/uniphier-gpio.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2017 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + */ + +#ifndef _DT_BINDINGS_GPIO_UNIPHIER_H +#define _DT_BINDINGS_GPIO_UNIPHIER_H + +#define UNIPHIER_GPIO_LINES_PER_BANK 8 + +#define UNIPHIER_GPIO_IRQ_OFFSET ((UNIPHIER_GPIO_LINES_PER_BANK) * 15) + +#define UNIPHIER_GPIO_PORT(bank, line) \ + ((UNIPHIER_GPIO_LINES_PER_BANK) * (bank) + (line)) + +#define UNIPHIER_GPIO_IRQ(n) ((UNIPHIER_GPIO_IRQ_OFFSET) + (n)) + +#endif /* _DT_BINDINGS_GPIO_UNIPHIER_H */ diff --git a/include/dt-bindings/mfd/stm32f7-rcc.h b/include/dt-bindings/mfd/stm32f7-rcc.h index e36cc69959..44c0914493 100644 --- a/include/dt-bindings/mfd/stm32f7-rcc.h +++ b/include/dt-bindings/mfd/stm32f7-rcc.h @@ -90,6 +90,7 @@ #define STM32F7_RCC_APB2_TIM8 1 #define STM32F7_RCC_APB2_USART1 4 #define STM32F7_RCC_APB2_USART6 5 +#define STM32F7_RCC_APB2_SDMMC2 7 #define STM32F7_RCC_APB2_ADC1 8 #define STM32F7_RCC_APB2_ADC2 9 #define STM32F7_RCC_APB2_ADC3 10 diff --git a/include/dt-bindings/pinctrl/pinctrl-zynqmp.h b/include/dt-bindings/pinctrl/pinctrl-zynqmp.h new file mode 100644 index 0000000000..e1b81fe5ef --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-zynqmp.h @@ -0,0 +1,30 @@ +/* + * MIO pin configuration defines for Xilinx ZynqMP + * + * Copyright (C) 2017 Xilinx, Inc. + * Author: Chirag Parekh <chirag.parekh@xilinx.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H +#define _DT_BINDINGS_PINCTRL_ZYNQMP_H + +/* Bit value for IO standards */ +#define IO_STANDARD_LVCMOS33 0 +#define IO_STANDARD_LVCMOS18 1 + +/* Bit values for Slew Rates */ +#define SLEW_RATE_FAST 0 +#define SLEW_RATE_SLOW 1 + +/* Bit values for Pin inputs */ +#define PIN_INPUT_TYPE_CMOS 0 +#define PIN_INPUT_TYPE_SCHMITT 1 + +#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ diff --git a/include/dt-bindings/power/r8a77970-sysc.h b/include/dt-bindings/power/r8a77970-sysc.h new file mode 100644 index 0000000000..bf54779d16 --- /dev/null +++ b/include/dt-bindings/power/r8a77970-sysc.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2017 Cogent Embedded Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __DT_BINDINGS_POWER_R8A77970_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A77970_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A77970_PD_CA53_CPU0 5 +#define R8A77970_PD_CA53_CPU1 6 +#define R8A77970_PD_CR7 13 +#define R8A77970_PD_CA53_SCU 21 +#define R8A77970_PD_A2IR0 23 +#define R8A77970_PD_A3IR 24 +#define R8A77970_PD_A2IR1 27 +#define R8A77970_PD_A2IR2 28 +#define R8A77970_PD_A2IR3 29 +#define R8A77970_PD_A2SC0 30 +#define R8A77970_PD_A2SC1 31 + +/* Always-on power area */ +#define R8A77970_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A77970_SYSC_H__ */ diff --git a/include/dt-bindings/power/r8a77995-sysc.h b/include/dt-bindings/power/r8a77995-sysc.h new file mode 100644 index 0000000000..09d0ed575b --- /dev/null +++ b/include/dt-bindings/power/r8a77995-sysc.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2017 Glider bvba + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + */ +#ifndef __DT_BINDINGS_POWER_R8A77995_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A77995_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A77995_PD_CA53_CPU0 5 +#define R8A77995_PD_CA53_SCU 21 + +/* Always-on power area */ +#define R8A77995_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A77995_SYSC_H__ */ diff --git a/include/efi.h b/include/efi.h index dc8edc8743..2f0be9c86c 100644 --- a/include/efi.h +++ b/include/efi.h @@ -227,9 +227,9 @@ struct efi_time_cap { }; enum efi_locate_search_type { - all_handles, - by_register_notify, - by_protocol + ALL_HANDLES, + BY_REGISTER_NOTIFY, + BY_PROTOCOL }; struct efi_open_protocol_info_entry { diff --git a/include/efi_api.h b/include/efi_api.h index fcd7483ab2..584016dc30 100644 --- a/include/efi_api.h +++ b/include/efi_api.h @@ -28,8 +28,7 @@ enum efi_timer_delay { EFI_TIMER_RELATIVE = 2 }; -#define UINTN size_t -typedef long INTN; +#define efi_uintn_t size_t typedef uint16_t *efi_string_t; #define EVT_TIMER 0x80000000 @@ -49,20 +48,22 @@ struct efi_event; /* EFI Boot Services table */ struct efi_boot_services { struct efi_table_hdr hdr; - efi_status_t (EFIAPI *raise_tpl)(UINTN new_tpl); - void (EFIAPI *restore_tpl)(UINTN old_tpl); + efi_status_t (EFIAPI *raise_tpl)(efi_uintn_t new_tpl); + void (EFIAPI *restore_tpl)(efi_uintn_t old_tpl); - efi_status_t (EFIAPI *allocate_pages)(int, int, unsigned long, + efi_status_t (EFIAPI *allocate_pages)(int, int, efi_uintn_t, efi_physical_addr_t *); - efi_status_t (EFIAPI *free_pages)(efi_physical_addr_t, unsigned long); - efi_status_t (EFIAPI *get_memory_map)(unsigned long *memory_map_size, - struct efi_mem_desc *desc, unsigned long *key, - unsigned long *desc_size, u32 *desc_version); - efi_status_t (EFIAPI *allocate_pool)(int, unsigned long, void **); + efi_status_t (EFIAPI *free_pages)(efi_physical_addr_t, efi_uintn_t); + efi_status_t (EFIAPI *get_memory_map)(efi_uintn_t *memory_map_size, + struct efi_mem_desc *desc, + efi_uintn_t *key, + efi_uintn_t *desc_size, + u32 *desc_version); + efi_status_t (EFIAPI *allocate_pool)(int, efi_uintn_t, void **); efi_status_t (EFIAPI *free_pool)(void *); efi_status_t (EFIAPI *create_event)(uint32_t type, - UINTN notify_tpl, + efi_uintn_t notify_tpl, void (EFIAPI *notify_function) ( struct efi_event *event, void *context), @@ -70,8 +71,9 @@ struct efi_boot_services { efi_status_t (EFIAPI *set_timer)(struct efi_event *event, enum efi_timer_delay type, uint64_t trigger_time); - efi_status_t (EFIAPI *wait_for_event)(unsigned long number_of_events, - struct efi_event **event, size_t *index); + efi_status_t (EFIAPI *wait_for_event)(efi_uintn_t number_of_events, + struct efi_event **event, + efi_uintn_t *index); efi_status_t (EFIAPI *signal_event)(struct efi_event *event); efi_status_t (EFIAPI *close_event)(struct efi_event *event); efi_status_t (EFIAPI *check_event)(struct efi_event *event); @@ -94,7 +96,7 @@ struct efi_boot_services { efi_status_t (EFIAPI *locate_handle)( enum efi_locate_search_type search_type, const efi_guid_t *protocol, void *search_key, - unsigned long *buffer_size, efi_handle_t *buffer); + efi_uintn_t *buffer_size, efi_handle_t *buffer); efi_status_t (EFIAPI *locate_device_path)(const efi_guid_t *protocol, struct efi_device_path **device_path, efi_handle_t *device); @@ -141,14 +143,14 @@ struct efi_boot_services { efi_status_t(EFIAPI *open_protocol_information)(efi_handle_t handle, const efi_guid_t *protocol, struct efi_open_protocol_info_entry **entry_buffer, - unsigned long *entry_count); + efi_uintn_t *entry_count); efi_status_t (EFIAPI *protocols_per_handle)(efi_handle_t handle, efi_guid_t ***protocol_buffer, - unsigned long *protocols_buffer_count); + efi_uintn_t *protocols_buffer_count); efi_status_t (EFIAPI *locate_handle_buffer) ( enum efi_locate_search_type search_type, const efi_guid_t *protocol, void *search_key, - unsigned long *no_handles, efi_handle_t **buffer); + efi_uintn_t *no_handles, efi_handle_t **buffer); efi_status_t (EFIAPI *locate_protocol)(const efi_guid_t *protocol, void *registration, void **protocol_interface); efi_status_t (EFIAPI *install_multiple_protocol_interfaces)( @@ -249,7 +251,7 @@ struct efi_system_table { struct efi_simple_text_output_protocol *std_err; struct efi_runtime_services *runtime; struct efi_boot_services *boottime; - unsigned long nr_tables; + efi_uintn_t nr_tables; struct efi_configuration_table *tables; }; @@ -583,14 +585,14 @@ struct efi_gop_mode struct efi_gop { efi_status_t (EFIAPI *query_mode)(struct efi_gop *this, u32 mode_number, - unsigned long *size_of_info, + efi_uintn_t *size_of_info, struct efi_gop_mode_info **info); efi_status_t (EFIAPI *set_mode)(struct efi_gop *this, u32 mode_number); efi_status_t (EFIAPI *blt)(struct efi_gop *this, void *buffer, - unsigned long operation, unsigned long sx, - unsigned long sy, unsigned long dx, - unsigned long dy, unsigned long width, - unsigned long height, unsigned long delta); + u32 operation, efi_uintn_t sx, + efi_uintn_t sy, efi_uintn_t dx, + efi_uintn_t dy, efi_uintn_t width, + efi_uintn_t height, efi_uintn_t delta); struct efi_gop_mode *mode; }; diff --git a/include/efi_loader.h b/include/efi_loader.h index 1b92edbd77..6185055e78 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -6,6 +6,9 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#ifndef _EFI_LOADER_H +#define _EFI_LOADER_H 1 + #include <common.h> #include <part_efi.h> #include <efi_api.h> @@ -75,9 +78,9 @@ const char *__efi_nesting_dec(void); extern struct efi_runtime_services efi_runtime_services; extern struct efi_system_table systab; -extern const struct efi_simple_text_output_protocol efi_con_out; +extern struct efi_simple_text_output_protocol efi_con_out; extern struct efi_simple_input_interface efi_con_in; -extern const struct efi_console_control_protocol efi_console_control; +extern struct efi_console_control_protocol efi_console_control; extern const struct efi_device_path_to_text_protocol efi_device_path_to_text; uint16_t *efi_dp_str(struct efi_device_path *dp); @@ -98,6 +101,8 @@ extern unsigned int __efi_runtime_rel_start, __efi_runtime_rel_stop; * interface (usually a struct with callback functions), this struct maps the * protocol GUID to the respective protocol interface */ struct efi_handler { + /* Link to the list of protocols of a handle */ + struct list_head link; const efi_guid_t *guid; void *protocol_interface; }; @@ -112,20 +117,12 @@ struct efi_handler { struct efi_object { /* Every UEFI object is part of a global object list */ struct list_head link; - /* We support up to 16 "protocols" an object can be accessed through */ - struct efi_handler protocols[16]; + /* The list of protocols */ + struct list_head protocols; /* The object spawner can either use this for data or as identifier */ void *handle; }; -#define EFI_PROTOCOL_OBJECT(_guid, _protocol) (struct efi_object){ \ - .protocols = {{ \ - .guid = &(_guid), \ - .protocol_interface = (void *)(_protocol), \ - }}, \ - .handle = (void *)(_protocol), \ -} - /** * struct efi_event * @@ -141,7 +138,7 @@ struct efi_object { */ struct efi_event { uint32_t type; - UINTN notify_tpl; + efi_uintn_t notify_tpl; void (EFIAPI *notify_function)(struct efi_event *event, void *context); void *notify_context; u64 trigger_next; @@ -163,6 +160,8 @@ int efi_disk_register(void); int efi_gop_register(void); /* Called by bootefi to make the network interface available */ int efi_net_register(void); +/* Called by bootefi to make the watchdog available */ +int efi_watchdog_register(void); /* Called by bootefi to make SMBIOS tables available */ void efi_smbios_register(void); @@ -171,6 +170,8 @@ efi_fs_from_path(struct efi_device_path *fp); /* Called by networking code to memorize the dhcp ack package */ void efi_net_set_dhcp_ack(void *pkt, int len); +/* Called by efi_set_watchdog_timer to reset the timer */ +efi_status_t efi_set_watchdog(unsigned long timeout); /* Called from places to check whether a timer expired */ void efi_timer_check(void); @@ -185,8 +186,28 @@ void efi_restore_gd(void); void efi_runtime_relocate(ulong offset, struct efi_mem_desc *map); /* Call this to set the current device name */ void efi_set_bootdev(const char *dev, const char *devnr, const char *path); +/* Add a new object to the object list. */ +void efi_add_handle(struct efi_object *obj); +/* Create handle */ +efi_status_t efi_create_handle(void **handle); +/* Delete handle */ +void efi_delete_handle(struct efi_object *obj); +/* Call this to validate a handle and find the EFI object for it */ +struct efi_object *efi_search_obj(const void *handle); +/* Find a protocol on a handle */ +efi_status_t efi_search_protocol(const void *handle, + const efi_guid_t *protocol_guid, + struct efi_handler **handler); +/* Install new protocol on a handle */ +efi_status_t efi_add_protocol(const void *handle, const efi_guid_t *protocol, + void *protocol_interface); +/* Delete protocol from a handle */ +efi_status_t efi_remove_protocol(const void *handle, const efi_guid_t *protocol, + void *protocol_interface); +/* Delete all protocols from a handle */ +efi_status_t efi_remove_all_protocols(const void *handle); /* Call this to create an event */ -efi_status_t efi_create_event(uint32_t type, UINTN notify_tpl, +efi_status_t efi_create_event(uint32_t type, efi_uintn_t notify_tpl, void (EFIAPI *notify_function) ( struct efi_event *event, void *context), @@ -208,20 +229,20 @@ struct efi_file_handle *efi_file_from_path(struct efi_device_path *fp); /* Generic EFI memory allocator, call this to get memory */ void *efi_alloc(uint64_t len, int memory_type); /* More specific EFI memory allocator, called by EFI payloads */ -efi_status_t efi_allocate_pages(int type, int memory_type, unsigned long pages, +efi_status_t efi_allocate_pages(int type, int memory_type, efi_uintn_t pages, uint64_t *memory); /* EFI memory free function. */ -efi_status_t efi_free_pages(uint64_t memory, unsigned long pages); +efi_status_t efi_free_pages(uint64_t memory, efi_uintn_t pages); /* EFI memory allocator for small allocations */ -efi_status_t efi_allocate_pool(int pool_type, unsigned long size, +efi_status_t efi_allocate_pool(int pool_type, efi_uintn_t size, void **buffer); /* EFI pool memory free function. */ efi_status_t efi_free_pool(void *buffer); /* Returns the EFI memory map */ -efi_status_t efi_get_memory_map(unsigned long *memory_map_size, +efi_status_t efi_get_memory_map(efi_uintn_t *memory_map_size, struct efi_mem_desc *memory_map, - unsigned long *map_key, - unsigned long *descriptor_size, + efi_uintn_t *map_key, + efi_uintn_t *descriptor_size, uint32_t *descriptor_version); /* Adds a range into the EFI memory map */ uint64_t efi_add_memory_map(uint64_t start, uint64_t pages, int memory_type, @@ -230,9 +251,11 @@ uint64_t efi_add_memory_map(uint64_t start, uint64_t pages, int memory_type, int efi_memory_init(void); /* Adds new or overrides configuration table entry to the system table */ efi_status_t efi_install_configuration_table(const efi_guid_t *guid, void *table); -void efi_setup_loaded_image(struct efi_loaded_image *info, struct efi_object *obj, - struct efi_device_path *device_path, - struct efi_device_path *file_path); +/* Sets up a loaded image */ +efi_status_t efi_setup_loaded_image( + struct efi_loaded_image *info, struct efi_object *obj, + struct efi_device_path *device_path, + struct efi_device_path *file_path); efi_status_t efi_load_image_from_path(struct efi_device_path *file_path, void **buffer); @@ -243,7 +266,8 @@ extern void *efi_bounce_buffer; struct efi_device_path *efi_dp_next(const struct efi_device_path *dp); -int efi_dp_match(struct efi_device_path *a, struct efi_device_path *b); +int efi_dp_match(const struct efi_device_path *a, + const struct efi_device_path *b); struct efi_object *efi_dp_find_obj(struct efi_device_path *dp, struct efi_device_path **rem); unsigned efi_dp_size(const struct efi_device_path *dp); @@ -341,4 +365,6 @@ static inline void efi_set_bootdev(const char *dev, const char *devnr, const char *path) { } static inline void efi_net_set_dhcp_ack(void *pkt, int len) { } -#endif +#endif /* CONFIG_EFI_LOADER && !CONFIG_SPL_BUILD */ + +#endif /* _EFI_LOADER_H */ diff --git a/include/efi_selftest.h b/include/efi_selftest.h index 7ec42a0406..be5ba4bfa9 100644 --- a/include/efi_selftest.h +++ b/include/efi_selftest.h @@ -12,6 +12,7 @@ #include <common.h> #include <efi.h> #include <efi_api.h> +#include <efi_loader.h> #include <linker_lists.h> #define EFI_ST_SUCCESS 0 @@ -27,6 +28,15 @@ efi_st_printf(__VA_ARGS__)) \ /* + * Prints a TODO message. + * + * @... format string followed by fields to print + */ +#define efi_st_todo(...) \ + (efi_st_printf("%s(%u):\nTODO: ", __FILE__, __LINE__), \ + efi_st_printf(__VA_ARGS__)) \ + +/* * A test may be setup and executed at boottime, * it may be setup at boottime and executed at runtime, * or it may be setup and executed at runtime. @@ -72,6 +82,15 @@ void efi_st_printf(const char *fmt, ...) int efi_st_memcmp(const void *buf1, const void *buf2, size_t length); /* + * Compare an u16 string to a char string. + * + * @buf1: u16 string + * @buf2: char string + * @return: 0 if both buffers contain the same bytes + */ +int efi_st_strcmp_16_8(const u16 *buf1, const char *buf2); + +/* * Reads an Unicode character from the input device. * * @return: Unicode character @@ -88,6 +107,7 @@ u16 efi_st_get_key(void); * @setup: set up the unit test * @teardown: tear down the unit test * @execute: execute the unit test + * @on_request: test is only executed on request */ struct efi_unit_test { const char *name; @@ -96,6 +116,7 @@ struct efi_unit_test { const struct efi_system_table *systable); int (*execute)(void); int (*teardown)(void); + bool on_request; }; /* Declare a new EFI unit test */ diff --git a/include/fdt_support.h b/include/fdt_support.h index 2bca4d7889..e0f908636c 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -133,6 +133,24 @@ void fdt_fixup_crypto_node(void *blob, int sec_rev); static inline void fdt_fixup_crypto_node(void *blob, int sec_rev) {} #endif +/** + * Record information about a processed loadable in /fit-images (creating + * /fit-images if necessary). + * + * @param blob FDT blob to update + * @param index index of this loadable + * @param name name of the loadable + * @param load_addr address the loadable was loaded to + * @param size number of bytes loaded + * @param entry_point entry point (if specified, otherwise pass -1) + * @param type type (if specified, otherwise pass NULL) + * @param os os-type (if specified, otherwise pass NULL) + * @return 0 if ok, or -1 or -FDT_ERR_... on error + */ +int fdt_record_loadable(void *blob, u32 index, const char *name, + uintptr_t load_addr, u32 size, uintptr_t entry_point, + const char *type, const char *os); + #ifdef CONFIG_PCI #include <pci.h> int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose); diff --git a/include/fdtdec.h b/include/fdtdec.h index 1ba02be8e1..0fb3e07212 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -159,6 +159,8 @@ enum fdt_compat_id { COMPAT_ALTERA_SOCFPGA_F2SDR0, /* SoCFPGA fpga2SDRAM0 bridge */ COMPAT_ALTERA_SOCFPGA_F2SDR1, /* SoCFPGA fpga2SDRAM1 bridge */ COMPAT_ALTERA_SOCFPGA_F2SDR2, /* SoCFPGA fpga2SDRAM2 bridge */ + COMPAT_ALTERA_SOCFPGA_FPGA0, /* SOCFPGA FPGA manager */ + COMPAT_ALTERA_SOCFPGA_NOC, /* SOCFPGA Arria 10 NOC */ COMPAT_COUNT, }; diff --git a/include/fpga.h b/include/fpga.h index d768fb1417..4d6da790b7 100644 --- a/include/fpga.h +++ b/include/fpga.h @@ -54,6 +54,7 @@ void fpga_init(void); int fpga_add(fpga_type devtype, void *desc); int fpga_count(void); const fpga_desc *const fpga_get_desc(int devnum); +int fpga_is_partial_data(int devnum, size_t img_len); int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype); int fpga_fsload(int devnum, const void *buf, size_t size, diff --git a/include/fsl-mc/fsl_dpbp.h b/include/fsl-mc/fsl_dpbp.h index b1ad46ee45..5401e861f0 100644 --- a/include/fsl-mc/fsl_dpbp.h +++ b/include/fsl-mc/fsl_dpbp.h @@ -1,8 +1,8 @@ /* * Freescale Layerscape MC I/O wrapper * - * Copyright (C) 2013-2015 Freescale Semiconductor, Inc. - * Author: German Rivera <German.Rivera@freescale.com> + * Copyright (C) 2013-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -14,19 +14,21 @@ #define __FSL_DPBP_H /* DPBP Version */ -#define DPBP_VER_MAJOR 2 -#define DPBP_VER_MINOR 2 +#define DPBP_VER_MAJOR 3 +#define DPBP_VER_MINOR 3 /* Command IDs */ -#define DPBP_CMDID_CLOSE 0x800 -#define DPBP_CMDID_OPEN 0x804 -#define DPBP_CMDID_CREATE 0x904 -#define DPBP_CMDID_DESTROY 0x900 - -#define DPBP_CMDID_ENABLE 0x002 -#define DPBP_CMDID_DISABLE 0x003 -#define DPBP_CMDID_GET_ATTR 0x004 -#define DPBP_CMDID_RESET 0x005 +#define DPBP_CMDID_CLOSE 0x8001 +#define DPBP_CMDID_OPEN 0x8041 +#define DPBP_CMDID_CREATE 0x9041 +#define DPBP_CMDID_DESTROY 0x9841 +#define DPBP_CMDID_GET_API_VERSION 0xa041 + +#define DPBP_CMDID_ENABLE 0x0021 +#define DPBP_CMDID_DISABLE 0x0031 +#define DPBP_CMDID_GET_ATTR 0x0041 +#define DPBP_CMDID_RESET 0x0051 +#define DPBP_CMDID_IS_ENABLED 0x0061 /* cmd, param, offset, width, type, arg_name */ #define DPBP_CMD_OPEN(cmd, dpbp_id) \ @@ -37,8 +39,6 @@ do { \ MC_RSP_OP(cmd, 0, 16, 16, uint16_t, attr->bpid); \ MC_RSP_OP(cmd, 0, 32, 32, int, attr->id);\ - MC_RSP_OP(cmd, 1, 0, 16, uint16_t, attr->version.major);\ - MC_RSP_OP(cmd, 1, 16, 16, uint16_t, attr->version.minor);\ } while (0) /* Data Path Buffer Pool API @@ -114,9 +114,10 @@ struct dpbp_cfg { * Return: '0' on Success; Error code otherwise. */ int dpbp_create(struct fsl_mc_io *mc_io, + uint16_t dprc_token, uint32_t cmd_flags, const struct dpbp_cfg *cfg, - uint16_t *token); + uint32_t *obj_id); /** * dpbp_destroy() - Destroy the DPBP object and release all its resources. @@ -127,8 +128,9 @@ int dpbp_create(struct fsl_mc_io *mc_io, * Return: '0' on Success; error code otherwise. */ int dpbp_destroy(struct fsl_mc_io *mc_io, + uint16_t dprc_token, uint32_t cmd_flags, - uint16_t token); + uint32_t obj_id); /** * dpbp_enable() - Enable the DPBP. @@ -189,16 +191,7 @@ int dpbp_reset(struct fsl_mc_io *mc_io, * acquire/release operations on buffers */ struct dpbp_attr { - int id; - /** - * struct version - Structure representing DPBP version - * @major: DPBP major version - * @minor: DPBP minor version - */ - struct { - uint16_t major; - uint16_t minor; - } version; + uint32_t id; uint16_t bpid; }; @@ -217,6 +210,21 @@ int dpbp_get_attributes(struct fsl_mc_io *mc_io, uint16_t token, struct dpbp_attr *attr); +/** + * dpbp_get_api_version - Retrieve DPBP Major and Minor version info. + * + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @major_ver: DPBP major version + * @minor_ver: DPBP minor version + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_get_api_version(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 *major_ver, + u16 *minor_ver); + /** @} */ #endif /* __FSL_DPBP_H */ diff --git a/include/fsl-mc/fsl_dpio.h b/include/fsl-mc/fsl_dpio.h index d8c458fb4f..86251e222f 100644 --- a/include/fsl-mc/fsl_dpio.h +++ b/include/fsl-mc/fsl_dpio.h @@ -1,5 +1,6 @@ /* - * Copyright (C) 2013-2015 Freescale Semiconductor + * Copyright (C) 2013-2016 Freescale Semiconductor + * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -8,19 +9,20 @@ #define _FSL_DPIO_H /* DPIO Version */ -#define DPIO_VER_MAJOR 3 +#define DPIO_VER_MAJOR 4 #define DPIO_VER_MINOR 2 /* Command IDs */ -#define DPIO_CMDID_CLOSE 0x800 -#define DPIO_CMDID_OPEN 0x803 -#define DPIO_CMDID_CREATE 0x903 -#define DPIO_CMDID_DESTROY 0x900 +#define DPIO_CMDID_CLOSE 0x8001 +#define DPIO_CMDID_OPEN 0x8031 +#define DPIO_CMDID_CREATE 0x9031 +#define DPIO_CMDID_DESTROY 0x9831 +#define DPIO_CMDID_GET_API_VERSION 0xa031 -#define DPIO_CMDID_ENABLE 0x002 -#define DPIO_CMDID_DISABLE 0x003 -#define DPIO_CMDID_GET_ATTR 0x004 -#define DPIO_CMDID_RESET 0x005 +#define DPIO_CMDID_ENABLE 0x0021 +#define DPIO_CMDID_DISABLE 0x0031 +#define DPIO_CMDID_GET_ATTR 0x0041 +#define DPIO_CMDID_RESET 0x0051 /* cmd, param, offset, width, type, arg_name */ #define DPIO_CMD_OPEN(cmd, dpio_id) \ @@ -43,8 +45,6 @@ do { \ MC_RSP_OP(cmd, 0, 56, 4, enum dpio_channel_mode, attr->channel_mode);\ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, attr->qbman_portal_ce_offset);\ MC_RSP_OP(cmd, 2, 0, 64, uint64_t, attr->qbman_portal_ci_offset);\ - MC_RSP_OP(cmd, 3, 0, 16, uint16_t, attr->version.major);\ - MC_RSP_OP(cmd, 3, 16, 16, uint16_t, attr->version.minor);\ MC_RSP_OP(cmd, 3, 32, 32, uint32_t, attr->qbman_version);\ } while (0) @@ -73,7 +73,7 @@ struct fsl_mc_io; */ int dpio_open(struct fsl_mc_io *mc_io, uint32_t cmd_flags, - int dpio_id, + uint32_t dpio_id, uint16_t *token); /** @@ -114,9 +114,10 @@ struct dpio_cfg { /** * dpio_create() - Create the DPIO object. * @mc_io: Pointer to MC portal's I/O object + * @token: Authentication token. * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' * @cfg: Configuration structure - * @token: Returned token; use in subsequent API calls + * @obj_id: Returned obj_id; use in subsequent API calls * * Create the DPIO object, allocate required resources and * perform required initialization. @@ -134,21 +135,24 @@ struct dpio_cfg { * Return: '0' on Success; Error code otherwise. */ int dpio_create(struct fsl_mc_io *mc_io, + uint16_t token, uint32_t cmd_flags, const struct dpio_cfg *cfg, - uint16_t *token); + uint32_t *obj_id); /** * dpio_destroy() - Destroy the DPIO object and release all its resources. * @mc_io: Pointer to MC portal's I/O object + * @token: Authentication token. * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPIO object + * @obj_id: Object ID of DPIO * * Return: '0' on Success; Error code otherwise */ int dpio_destroy(struct fsl_mc_io *mc_io, + uint16_t token, uint32_t cmd_flags, - uint16_t token); + uint32_t obj_id); /** * dpio_enable() - Enable the DPIO, allow I/O portal operations. @@ -199,16 +203,7 @@ int dpio_reset(struct fsl_mc_io *mc_io, * @qbman_version: QBMAN version */ struct dpio_attr { - int id; - /** - * struct version - DPIO version - * @major: DPIO major version - * @minor: DPIO minor version - */ - struct { - uint16_t major; - uint16_t minor; - } version; + uint32_t id; uint64_t qbman_portal_ce_offset; uint64_t qbman_portal_ci_offset; uint16_t qbman_portal_id; @@ -231,4 +226,19 @@ int dpio_get_attributes(struct fsl_mc_io *mc_io, uint16_t token, struct dpio_attr *attr); +/** + * dpio_get_api_version - Retrieve DPIO Major and Minor version info. + * + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @major_ver: DPIO major version + * @minor_ver: DPIO minor version + * + * Return: '0' on Success; Error code otherwise. + */ +int dpio_get_api_version(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 *major_ver, + u16 *minor_ver); + #endif /* _FSL_DPIO_H */ diff --git a/include/fsl-mc/fsl_dpmac.h b/include/fsl-mc/fsl_dpmac.h index 296f3aed24..36a5cca69c 100644 --- a/include/fsl-mc/fsl_dpmac.h +++ b/include/fsl-mc/fsl_dpmac.h @@ -1,7 +1,8 @@ /* * Freescale Layerscape MC I/O wrapper * - * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * Author: Prabhakar Kushwaha <prabhakar@freescale.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -11,27 +12,28 @@ #define __FSL_DPMAC_H /* DPMAC Version */ -#define DPMAC_VER_MAJOR 3 +#define DPMAC_VER_MAJOR 4 #define DPMAC_VER_MINOR 2 /* Command IDs */ -#define DPMAC_CMDID_CLOSE 0x800 -#define DPMAC_CMDID_OPEN 0x80c -#define DPMAC_CMDID_CREATE 0x90c -#define DPMAC_CMDID_DESTROY 0x900 +#define DPMAC_CMDID_CLOSE 0x8001 +#define DPMAC_CMDID_OPEN 0x80c1 +#define DPMAC_CMDID_CREATE 0x90c1 +#define DPMAC_CMDID_DESTROY 0x98c1 +#define DPMAC_CMDID_GET_API_VERSION 0xa0c1 -#define DPMAC_CMDID_GET_ATTR 0x004 -#define DPMAC_CMDID_RESET 0x005 +#define DPMAC_CMDID_GET_ATTR 0x0041 +#define DPMAC_CMDID_RESET 0x0051 -#define DPMAC_CMDID_MDIO_READ 0x0c0 -#define DPMAC_CMDID_MDIO_WRITE 0x0c1 -#define DPMAC_CMDID_GET_LINK_CFG 0x0c2 -#define DPMAC_CMDID_SET_LINK_STATE 0x0c3 -#define DPMAC_CMDID_GET_COUNTER 0x0c4 +#define DPMAC_CMDID_MDIO_READ 0x0c01 +#define DPMAC_CMDID_MDIO_WRITE 0x0c11 +#define DPMAC_CMDID_GET_LINK_CFG 0x0c21 +#define DPMAC_CMDID_SET_LINK_STATE 0x0c31 +#define DPMAC_CMDID_GET_COUNTER 0x0c41 /* cmd, param, offset, width, type, arg_name */ #define DPMAC_CMD_CREATE(cmd, cfg) \ - MC_CMD_OP(cmd, 0, 0, 32, int, cfg->mac_id) + MC_CMD_OP(cmd, 0, 0, 16, uint16_t, cfg->mac_id) /* cmd, param, offset, width, type, arg_name */ #define DPMAC_CMD_OPEN(cmd, dpmac_id) \ @@ -42,8 +44,6 @@ do { \ MC_RSP_OP(cmd, 0, 0, 32, int, attr->phy_id);\ MC_RSP_OP(cmd, 0, 32, 32, int, attr->id);\ - MC_RSP_OP(cmd, 1, 0, 16, uint16_t, attr->version.major);\ - MC_RSP_OP(cmd, 1, 16, 16, uint16_t, attr->version.minor);\ MC_RSP_OP(cmd, 1, 32, 8, enum dpmac_link_type, attr->link_type);\ MC_RSP_OP(cmd, 1, 40, 8, enum dpmac_eth_if, attr->eth_if);\ MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->max_rate);\ @@ -85,7 +85,7 @@ do { \ /* cmd, param, offset, width, type, arg_name */ #define DPMAC_CMD_GET_COUNTER(cmd, type) \ - MC_CMD_OP(cmd, 0, 0, 8, enum dpmac_counter, type) + MC_CMD_OP(cmd, 1, 0, 64, enum dpmac_counter, type) /* cmd, param, offset, width, type, arg_name */ #define DPMAC_RSP_GET_COUNTER(cmd, counter) \ @@ -187,9 +187,10 @@ struct dpmac_cfg { /** * dpmac_create() - Create the DPMAC object. * @mc_io: Pointer to MC portal's I/O object + * @token: Authentication token. * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' * @cfg: Configuration structure - * @token: Returned token; use in subsequent API calls + * @obj_id: Returned obj_id; use in subsequent API calls * * Create the DPMAC object, allocate required resources and * perform required initialization. @@ -206,21 +207,24 @@ struct dpmac_cfg { * Return: '0' on Success; Error code otherwise. */ int dpmac_create(struct fsl_mc_io *mc_io, + uint16_t token, uint32_t cmd_flags, const struct dpmac_cfg *cfg, - uint16_t *token); + uint32_t *obj_id); /** * dpmac_destroy() - Destroy the DPMAC object and release all its resources. * @mc_io: Pointer to MC portal's I/O object + * @token: Authentication token. * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPMAC object + * @obj_id: DPMAC object id * * Return: '0' on Success; error code otherwise. */ int dpmac_destroy(struct fsl_mc_io *mc_io, + uint16_t token, uint32_t cmd_flags, - uint16_t token); + uint32_t obj_id); /* DPMAC IRQ Index and Events */ @@ -246,15 +250,6 @@ struct dpmac_attr { enum dpmac_link_type link_type; enum dpmac_eth_if eth_if; uint32_t max_rate; - /** - * struct version - Structure representing DPMAC version - * @major: DPMAC major version - * @minor: DPMAC minor version - */ - struct { - uint16_t major; - uint16_t minor; - } version; }; /** @@ -464,5 +459,19 @@ int dpmac_get_counter(struct fsl_mc_io *mc_io, uint16_t token, enum dpmac_counter type, uint64_t *counter); +/** + * dpmac_get_api_version - Retrieve DPMAC Major and Minor version info. + * + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @major_ver: DPMAC major version + * @minor_ver: DPMAC minor version + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_get_api_version(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t *major_ver, + uint16_t *minor_ver); #endif /* __FSL_DPMAC_H */ diff --git a/include/fsl-mc/fsl_dpni.h b/include/fsl-mc/fsl_dpni.h index f396dc304f..5b80b6f8e0 100644 --- a/include/fsl-mc/fsl_dpni.h +++ b/include/fsl-mc/fsl_dpni.h @@ -1,5 +1,6 @@ /* - * Copyright (C) 2013-2015 Freescale Semiconductor + * Copyright (C) 2013-2016 Freescale Semiconductor + * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -7,134 +8,80 @@ #define _FSL_DPNI_H /* DPNI Version */ -#define DPNI_VER_MAJOR 6 -#define DPNI_VER_MINOR 0 +#define DPNI_VER_MAJOR 7 +#define DPNI_VER_MINOR 3 /* Command IDs */ -#define DPNI_CMDID_OPEN 0x801 -#define DPNI_CMDID_CLOSE 0x800 -#define DPNI_CMDID_CREATE 0x901 -#define DPNI_CMDID_DESTROY 0x900 - -#define DPNI_CMDID_ENABLE 0x002 -#define DPNI_CMDID_DISABLE 0x003 -#define DPNI_CMDID_GET_ATTR 0x004 -#define DPNI_CMDID_RESET 0x005 - -#define DPNI_CMDID_SET_POOLS 0x200 -#define DPNI_CMDID_GET_RX_BUFFER_LAYOUT 0x201 -#define DPNI_CMDID_SET_RX_BUFFER_LAYOUT 0x202 -#define DPNI_CMDID_GET_TX_BUFFER_LAYOUT 0x203 -#define DPNI_CMDID_SET_TX_BUFFER_LAYOUT 0x204 -#define DPNI_CMDID_SET_TX_CONF_BUFFER_LAYOUT 0x205 -#define DPNI_CMDID_GET_TX_CONF_BUFFER_LAYOUT 0x206 -#define DPNI_CMDID_SET_ERRORS_BEHAVIOR 0x20B - -#define DPNI_CMDID_GET_QDID 0x210 -#define DPNI_CMDID_GET_TX_DATA_OFFSET 0x212 -#define DPNI_CMDID_GET_COUNTER 0x213 -#define DPNI_CMDID_SET_COUNTER 0x214 -#define DPNI_CMDID_GET_LINK_STATE 0x215 -#define DPNI_CMDID_SET_LINK_CFG 0x21A - -#define DPNI_CMDID_SET_PRIM_MAC 0x224 -#define DPNI_CMDID_GET_PRIM_MAC 0x225 -#define DPNI_CMDID_ADD_MAC_ADDR 0x226 -#define DPNI_CMDID_REMOVE_MAC_ADDR 0x227 - -#define DPNI_CMDID_SET_TX_FLOW 0x236 -#define DPNI_CMDID_GET_TX_FLOW 0x237 -#define DPNI_CMDID_SET_RX_FLOW 0x238 -#define DPNI_CMDID_GET_RX_FLOW 0x239 -#define DPNI_CMDID_SET_TX_CONF 0x257 -#define DPNI_CMDID_GET_TX_CONF 0x258 +#define DPNI_CMDID_OPEN 0x8011 +#define DPNI_CMDID_CLOSE 0x8001 +#define DPNI_CMDID_CREATE 0x9011 +#define DPNI_CMDID_DESTROY 0x9811 +#define DPNI_CMDID_GET_API_VERSION 0xa011 + +#define DPNI_CMDID_ENABLE 0x0021 +#define DPNI_CMDID_DISABLE 0x0031 +#define DPNI_CMDID_GET_ATTR 0x0041 +#define DPNI_CMDID_RESET 0x0051 + +#define DPNI_CMDID_SET_POOLS 0x2002 +#define DPNI_CMDID_SET_BUFFER_LAYOUT 0x2651 +#define DPNI_CMDID_GET_BUFFER_LAYOUT 0x2641 +#define DPNI_CMDID_SET_ERRORS_BEHAVIOR 0x20B1 + +#define DPNI_CMDID_GET_QDID 0x2101 +#define DPNI_CMDID_GET_TX_DATA_OFFSET 0x2121 +#define DPNI_CMDID_GET_LINK_STATE 0x2151 +#define DPNI_CMDID_SET_LINK_CFG 0x21A1 + +#define DPNI_CMDID_SET_PRIM_MAC 0x2241 +#define DPNI_CMDID_GET_PRIM_MAC 0x2251 +#define DPNI_CMDID_ADD_MAC_ADDR 0x2261 +#define DPNI_CMDID_REMOVE_MAC_ADDR 0x2271 + +#define DPNI_CMDID_GET_STATISTICS 0x25D1 +#define DPNI_CMDID_RESET_STATISTICS 0x25E1 +#define DPNI_CMDID_GET_QUEUE 0x25F1 +#define DPNI_CMDID_SET_QUEUE 0x2601 +#define DPNI_CMDID_SET_TX_CONFIRMATION_MODE 0x2661 /* cmd, param, offset, width, type, arg_name */ #define DPNI_CMD_OPEN(cmd, dpni_id) \ MC_CMD_OP(cmd, 0, 0, 32, int, dpni_id) -#define DPNI_PREP_EXTENDED_CFG(ext, cfg) \ +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_PREP_CFG(param, cfg) \ do { \ - MC_PREP_OP(ext, 0, 0, 16, uint16_t, cfg->tc_cfg[0].max_dist); \ - MC_PREP_OP(ext, 0, 16, 16, uint16_t, cfg->tc_cfg[0].max_fs_entries); \ - MC_PREP_OP(ext, 0, 32, 16, uint16_t, cfg->tc_cfg[1].max_dist); \ - MC_PREP_OP(ext, 0, 48, 16, uint16_t, cfg->tc_cfg[1].max_fs_entries); \ - MC_PREP_OP(ext, 1, 0, 16, uint16_t, cfg->tc_cfg[2].max_dist); \ - MC_PREP_OP(ext, 1, 16, 16, uint16_t, cfg->tc_cfg[2].max_fs_entries); \ - MC_PREP_OP(ext, 1, 32, 16, uint16_t, cfg->tc_cfg[3].max_dist); \ - MC_PREP_OP(ext, 1, 48, 16, uint16_t, cfg->tc_cfg[3].max_fs_entries); \ - MC_PREP_OP(ext, 2, 0, 16, uint16_t, cfg->tc_cfg[4].max_dist); \ - MC_PREP_OP(ext, 2, 16, 16, uint16_t, cfg->tc_cfg[4].max_fs_entries); \ - MC_PREP_OP(ext, 2, 32, 16, uint16_t, cfg->tc_cfg[5].max_dist); \ - MC_PREP_OP(ext, 2, 48, 16, uint16_t, cfg->tc_cfg[5].max_fs_entries); \ - MC_PREP_OP(ext, 3, 0, 16, uint16_t, cfg->tc_cfg[6].max_dist); \ - MC_PREP_OP(ext, 3, 16, 16, uint16_t, cfg->tc_cfg[6].max_fs_entries); \ - MC_PREP_OP(ext, 3, 32, 16, uint16_t, cfg->tc_cfg[7].max_dist); \ - MC_PREP_OP(ext, 3, 48, 16, uint16_t, cfg->tc_cfg[7].max_fs_entries); \ - MC_PREP_OP(ext, 4, 0, 16, uint16_t, \ - cfg->ipr_cfg.max_open_frames_ipv4); \ - MC_PREP_OP(ext, 4, 16, 16, uint16_t, \ - cfg->ipr_cfg.max_open_frames_ipv6); \ - MC_PREP_OP(ext, 4, 32, 16, uint16_t, \ - cfg->ipr_cfg.max_reass_frm_size); \ - MC_PREP_OP(ext, 5, 0, 16, uint16_t, \ - cfg->ipr_cfg.min_frag_size_ipv4); \ - MC_PREP_OP(ext, 5, 16, 16, uint16_t, \ - cfg->ipr_cfg.min_frag_size_ipv6); \ + MC_PREP_OP(param, 0, 0, 32, uint16_t, cfg->adv.options); \ + MC_PREP_OP(param, 0, 32, 8, uint16_t, cfg->adv.num_queues); \ + MC_PREP_OP(param, 0, 40, 8, uint16_t, cfg->adv.num_tcs); \ + MC_PREP_OP(param, 0, 48, 8, uint16_t, cfg->adv.mac_entries); \ + MC_PREP_OP(param, 1, 0, 8, uint16_t, cfg->adv.vlan_entries); \ + MC_PREP_OP(param, 1, 16, 8, uint16_t, cfg->adv.qos_entries); \ + MC_PREP_OP(param, 1, 32, 16, uint16_t, cfg->adv.fs_entries); \ } while (0) -#define DPNI_EXT_EXTENDED_CFG(ext, cfg) \ +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_EXT_CFG(param, cfg) \ do { \ - MC_EXT_OP(ext, 0, 0, 16, uint16_t, cfg->tc_cfg[0].max_dist); \ - MC_EXT_OP(ext, 0, 16, 16, uint16_t, cfg->tc_cfg[0].max_fs_entries); \ - MC_EXT_OP(ext, 0, 32, 16, uint16_t, cfg->tc_cfg[1].max_dist); \ - MC_EXT_OP(ext, 0, 48, 16, uint16_t, cfg->tc_cfg[1].max_fs_entries); \ - MC_EXT_OP(ext, 1, 0, 16, uint16_t, cfg->tc_cfg[2].max_dist); \ - MC_EXT_OP(ext, 1, 16, 16, uint16_t, cfg->tc_cfg[2].max_fs_entries); \ - MC_EXT_OP(ext, 1, 32, 16, uint16_t, cfg->tc_cfg[3].max_dist); \ - MC_EXT_OP(ext, 1, 48, 16, uint16_t, cfg->tc_cfg[3].max_fs_entries); \ - MC_EXT_OP(ext, 2, 0, 16, uint16_t, cfg->tc_cfg[4].max_dist); \ - MC_EXT_OP(ext, 2, 16, 16, uint16_t, cfg->tc_cfg[4].max_fs_entries); \ - MC_EXT_OP(ext, 2, 32, 16, uint16_t, cfg->tc_cfg[5].max_dist); \ - MC_EXT_OP(ext, 2, 48, 16, uint16_t, cfg->tc_cfg[5].max_fs_entries); \ - MC_EXT_OP(ext, 3, 0, 16, uint16_t, cfg->tc_cfg[6].max_dist); \ - MC_EXT_OP(ext, 3, 16, 16, uint16_t, cfg->tc_cfg[6].max_fs_entries); \ - MC_EXT_OP(ext, 3, 32, 16, uint16_t, cfg->tc_cfg[7].max_dist); \ - MC_EXT_OP(ext, 3, 48, 16, uint16_t, cfg->tc_cfg[7].max_fs_entries); \ - MC_EXT_OP(ext, 4, 0, 16, uint16_t, \ - cfg->ipr_cfg.max_open_frames_ipv4); \ - MC_EXT_OP(ext, 4, 16, 16, uint16_t, \ - cfg->ipr_cfg.max_open_frames_ipv6); \ - MC_EXT_OP(ext, 4, 32, 16, uint16_t, \ - cfg->ipr_cfg.max_reass_frm_size); \ - MC_EXT_OP(ext, 5, 0, 16, uint16_t, \ - cfg->ipr_cfg.min_frag_size_ipv4); \ - MC_EXT_OP(ext, 5, 16, 16, uint16_t, \ - cfg->ipr_cfg.min_frag_size_ipv6); \ + MC_EXT_OP(param, 0, 0, 32, uint16_t, cfg->adv.options); \ + MC_EXT_OP(param, 0, 32, 8, uint16_t, cfg->adv.num_queues); \ + MC_EXT_OP(param, 0, 40, 8, uint16_t, cfg->adv.num_tcs); \ + MC_EXT_OP(param, 0, 48, 8, uint16_t, cfg->adv.mac_entries); \ + MC_EXT_OP(param, 1, 0, 8, uint16_t, cfg->adv.vlan_entries); \ + MC_EXT_OP(param, 1, 16, 8, uint16_t, cfg->adv.qos_entries); \ + MC_EXT_OP(param, 1, 32, 16, uint16_t, cfg->adv.fs_entries); \ } while (0) /* cmd, param, offset, width, type, arg_name */ #define DPNI_CMD_CREATE(cmd, cfg) \ do { \ - MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->adv.max_tcs); \ - MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->adv.max_senders); \ - MC_CMD_OP(cmd, 0, 16, 8, uint8_t, cfg->mac_addr[5]); \ - MC_CMD_OP(cmd, 0, 24, 8, uint8_t, cfg->mac_addr[4]); \ - MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->mac_addr[3]); \ - MC_CMD_OP(cmd, 0, 40, 8, uint8_t, cfg->mac_addr[2]); \ - MC_CMD_OP(cmd, 0, 48, 8, uint8_t, cfg->mac_addr[1]); \ - MC_CMD_OP(cmd, 0, 56, 8, uint8_t, cfg->mac_addr[0]); \ - MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->adv.options); \ - MC_CMD_OP(cmd, 2, 0, 8, uint8_t, cfg->adv.max_unicast_filters); \ - MC_CMD_OP(cmd, 2, 8, 8, uint8_t, cfg->adv.max_multicast_filters); \ - MC_CMD_OP(cmd, 2, 16, 8, uint8_t, cfg->adv.max_vlan_filters); \ - MC_CMD_OP(cmd, 2, 24, 8, uint8_t, cfg->adv.max_qos_entries); \ - MC_CMD_OP(cmd, 2, 32, 8, uint8_t, cfg->adv.max_qos_key_size); \ - MC_CMD_OP(cmd, 2, 48, 8, uint8_t, cfg->adv.max_dist_key_size); \ - MC_CMD_OP(cmd, 2, 56, 8, enum net_prot, cfg->adv.start_hdr); \ - MC_CMD_OP(cmd, 4, 48, 8, uint8_t, cfg->adv.max_policers); \ - MC_CMD_OP(cmd, 4, 56, 8, uint8_t, cfg->adv.max_congestion_ctrl); \ - MC_CMD_OP(cmd, 5, 0, 64, uint64_t, cfg->adv.ext_cfg_iova); \ + MC_CMD_OP(cmd, 0, 0, 32, uint32_t, cfg->adv.options); \ + MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->adv.num_queues); \ + MC_CMD_OP(cmd, 0, 40, 8, uint8_t, cfg->adv.num_tcs); \ + MC_CMD_OP(cmd, 0, 48, 8, uint8_t, cfg->adv.mac_entries); \ + MC_CMD_OP(cmd, 1, 0, 8, uint8_t, cfg->adv.vlan_entries); \ + MC_CMD_OP(cmd, 1, 16, 8, uint8_t, cfg->adv.qos_entries); \ + MC_CMD_OP(cmd, 1, 32, 16, uint8_t, cfg->adv.fs_entries); \ } while (0) /* cmd, param, offset, width, type, arg_name */ @@ -168,27 +115,18 @@ do { \ } while (0) /* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_GET_ATTR(cmd, attr) \ - MC_CMD_OP(cmd, 6, 0, 64, uint64_t, attr->ext_cfg_iova) - -/* cmd, param, offset, width, type, arg_name */ #define DPNI_RSP_GET_ATTR(cmd, attr) \ do { \ - MC_RSP_OP(cmd, 0, 0, 32, int, attr->id);\ - MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->max_tcs); \ - MC_RSP_OP(cmd, 0, 40, 8, uint8_t, attr->max_senders); \ - MC_RSP_OP(cmd, 0, 48, 8, enum net_prot, attr->start_hdr); \ - MC_RSP_OP(cmd, 1, 0, 32, uint32_t, attr->options); \ - MC_RSP_OP(cmd, 2, 0, 8, uint8_t, attr->max_unicast_filters); \ - MC_RSP_OP(cmd, 2, 8, 8, uint8_t, attr->max_multicast_filters);\ - MC_RSP_OP(cmd, 2, 16, 8, uint8_t, attr->max_vlan_filters); \ - MC_RSP_OP(cmd, 2, 24, 8, uint8_t, attr->max_qos_entries); \ - MC_RSP_OP(cmd, 2, 32, 8, uint8_t, attr->max_qos_key_size); \ - MC_RSP_OP(cmd, 2, 40, 8, uint8_t, attr->max_dist_key_size); \ - MC_RSP_OP(cmd, 4, 48, 8, uint8_t, attr->max_policers); \ - MC_RSP_OP(cmd, 4, 56, 8, uint8_t, attr->max_congestion_ctrl); \ - MC_RSP_OP(cmd, 5, 32, 16, uint16_t, attr->version.major);\ - MC_RSP_OP(cmd, 5, 48, 16, uint16_t, attr->version.minor);\ + MC_RSP_OP(cmd, 0, 0, 32, int, attr->options);\ + MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->max_num_queues); \ + MC_RSP_OP(cmd, 0, 40, 8, uint8_t, attr->max_num_tcs); \ + MC_RSP_OP(cmd, 0, 48, 8, uint8_t, attr->max_mac_entries); \ + MC_RSP_OP(cmd, 1, 0, 8, uint8_t, attr->max_vlan_entries); \ + MC_RSP_OP(cmd, 1, 16, 8, uint8_t, attr->max_qos_entries); \ + MC_RSP_OP(cmd, 1, 32, 16, uint16_t, attr->max_fs_entries); \ + MC_RSP_OP(cmd, 2, 0, 8, uint8_t, attr->max_qos_key_size); \ + MC_RSP_OP(cmd, 2, 8, 8, uint8_t, attr->max_fs_key_size); \ + MC_RSP_OP(cmd, 2, 16, 16, uint16_t, attr->wriop_version); \ } while (0) /* cmd, param, offset, width, type, arg_name */ @@ -200,78 +138,17 @@ do { \ } while (0) /* cmd, param, offset, width, type, arg_name */ -#define DPNI_RSP_GET_RX_BUFFER_LAYOUT(cmd, layout) \ -do { \ - MC_RSP_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \ - MC_RSP_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \ - MC_RSP_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \ - MC_RSP_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \ - MC_RSP_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \ - MC_RSP_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \ - MC_RSP_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_SET_RX_BUFFER_LAYOUT(cmd, layout) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \ - MC_CMD_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \ - MC_CMD_OP(cmd, 0, 32, 32, uint32_t, layout->options); \ - MC_CMD_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \ - MC_CMD_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \ - MC_CMD_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \ - MC_CMD_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \ - MC_CMD_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_RSP_GET_TX_BUFFER_LAYOUT(cmd, layout) \ -do { \ - MC_RSP_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \ - MC_RSP_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \ - MC_RSP_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \ - MC_RSP_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \ - MC_RSP_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \ - MC_RSP_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \ - MC_RSP_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_SET_TX_BUFFER_LAYOUT(cmd, layout) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \ - MC_CMD_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \ - MC_CMD_OP(cmd, 0, 32, 32, uint32_t, layout->options); \ - MC_CMD_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \ - MC_CMD_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \ - MC_CMD_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \ - MC_CMD_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \ - MC_CMD_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_RSP_GET_TX_CONF_BUFFER_LAYOUT(cmd, layout) \ -do { \ - MC_RSP_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \ - MC_RSP_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \ - MC_RSP_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \ - MC_RSP_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \ - MC_RSP_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \ - MC_RSP_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \ - MC_RSP_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_SET_TX_CONF_BUFFER_LAYOUT(cmd, layout) \ +#define DPNI_CMD_SET_BUFFER_LAYOUT(cmd, layout, queue) \ do { \ - MC_CMD_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \ - MC_CMD_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \ - MC_CMD_OP(cmd, 0, 32, 32, uint32_t, layout->options); \ - MC_CMD_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \ - MC_CMD_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \ - MC_CMD_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \ - MC_CMD_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \ - MC_CMD_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \ + MC_CMD_OP(cmd, 0, 0, 8, enum dpni_queue_type, queue); \ + MC_CMD_OP(cmd, 1, 0, 16, uint16_t, layout->private_data_size); \ + MC_CMD_OP(cmd, 1, 16, 16, uint16_t, layout->data_align); \ + MC_CMD_OP(cmd, 0, 32, 16, uint16_t, layout->options); \ + MC_CMD_OP(cmd, 0, 48, 1, int, layout->pass_timestamp); \ + MC_CMD_OP(cmd, 0, 49, 1, int, layout->pass_parser_result); \ + MC_CMD_OP(cmd, 0, 50, 1, int, layout->pass_frame_status); \ + MC_CMD_OP(cmd, 1, 32, 16, uint16_t, layout->data_head_room); \ + MC_CMD_OP(cmd, 1, 48, 16, uint16_t, layout->data_tail_room); \ } while (0) /* cmd, param, offset, width, type, arg_name */ @@ -283,21 +160,6 @@ do { \ MC_RSP_OP(cmd, 0, 0, 16, uint16_t, data_offset) /* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_GET_COUNTER(cmd, counter) \ - MC_CMD_OP(cmd, 0, 0, 16, enum dpni_counter, counter) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_RSP_GET_COUNTER(cmd, value) \ - MC_RSP_OP(cmd, 1, 0, 64, uint64_t, value) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_SET_COUNTER(cmd, counter, value) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 16, enum dpni_counter, counter); \ - MC_CMD_OP(cmd, 1, 0, 64, uint64_t, value); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ #define DPNI_CMD_SET_LINK_CFG(cmd, cfg) \ do { \ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->rate);\ @@ -358,129 +220,54 @@ do { \ MC_CMD_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \ } while (0) -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_SET_TX_FLOW(cmd, flow_id, cfg) \ +#define DPNI_CMD_GET_QUEUE(cmd, type, tc, index) \ do { \ - MC_CMD_OP(cmd, 0, 43, 1, int, cfg->l3_chksum_gen);\ - MC_CMD_OP(cmd, 0, 44, 1, int, cfg->l4_chksum_gen);\ - MC_CMD_OP(cmd, 0, 45, 1, int, cfg->use_common_tx_conf_queue);\ - MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id);\ - MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->options);\ + MC_CMD_OP(cmd, 0, 0, 8, enum dpni_queue_type, type); \ + MC_CMD_OP(cmd, 0, 8, 8, uint8_t, tc); \ + MC_CMD_OP(cmd, 0, 16, 8, uint8_t, index); \ } while (0) -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_RSP_SET_TX_FLOW(cmd, flow_id) \ - MC_RSP_OP(cmd, 0, 48, 16, uint16_t, flow_id) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_GET_TX_FLOW(cmd, flow_id) \ - MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_RSP_GET_TX_FLOW(cmd, attr) \ +#define DPNI_RSP_GET_QUEUE(cmd, queue) \ do { \ - MC_RSP_OP(cmd, 0, 43, 1, int, attr->l3_chksum_gen);\ - MC_RSP_OP(cmd, 0, 44, 1, int, attr->l4_chksum_gen);\ - MC_RSP_OP(cmd, 0, 45, 1, int, attr->use_common_tx_conf_queue);\ + MC_RSP_OP(cmd, 1, 0, 32, uint32_t, (queue)->destination.id); \ + MC_RSP_OP(cmd, 1, 56, 4, enum dpni_dest, (queue)->destination.type); \ + MC_RSP_OP(cmd, 1, 62, 1, char, (queue)->destination.stash_ctrl); \ + MC_RSP_OP(cmd, 1, 63, 1, char, (queue)->destination.hold_active); \ + MC_RSP_OP(cmd, 2, 0, 64, uint64_t, (queue)->flc); \ + MC_RSP_OP(cmd, 3, 0, 64, uint64_t, (queue)->user_context); \ + MC_RSP_OP(cmd, 4, 0, 32, uint32_t, (queue)->fqid); \ + MC_RSP_OP(cmd, 4, 32, 16, uint16_t, (queue)->qdbin); \ } while (0) -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_SET_RX_FLOW(cmd, tc_id, flow_id, cfg) \ +#define DPNI_CMD_SET_QUEUE(cmd, type, tc, index, queue) \ do { \ - MC_CMD_OP(cmd, 0, 0, 32, int, cfg->dest_cfg.dest_id); \ - MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->dest_cfg.priority);\ - MC_CMD_OP(cmd, 0, 40, 2, enum dpni_dest, cfg->dest_cfg.dest_type);\ - MC_CMD_OP(cmd, 0, 42, 1, int, cfg->order_preservation_en);\ - MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id); \ - MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->user_ctx); \ - MC_CMD_OP(cmd, 2, 16, 8, uint8_t, tc_id); \ - MC_CMD_OP(cmd, 2, 32, 32, uint32_t, cfg->options); \ - MC_CMD_OP(cmd, 3, 0, 4, enum dpni_flc_type, cfg->flc_cfg.flc_type); \ - MC_CMD_OP(cmd, 3, 4, 4, enum dpni_stash_size, \ - cfg->flc_cfg.frame_data_size);\ - MC_CMD_OP(cmd, 3, 8, 4, enum dpni_stash_size, \ - cfg->flc_cfg.flow_context_size);\ - MC_CMD_OP(cmd, 3, 32, 32, uint32_t, cfg->flc_cfg.options);\ - MC_CMD_OP(cmd, 4, 0, 64, uint64_t, cfg->flc_cfg.flow_context);\ - MC_CMD_OP(cmd, 5, 0, 32, uint32_t, cfg->tail_drop_threshold); \ + MC_CMD_OP(cmd, 0, 0, 8, enum dpni_queue_type, type); \ + MC_CMD_OP(cmd, 0, 8, 8, uint8_t, tc); \ + MC_CMD_OP(cmd, 0, 16, 8, uint8_t, index); \ + MC_CMD_OP(cmd, 0, 24, 8, uint8_t, (queue)->options); \ + MC_CMD_OP(cmd, 1, 0, 32, uint32_t, (queue)->destination.id); \ + MC_CMD_OP(cmd, 1, 56, 4, enum dpni_dest, (queue)->destination.type); \ + MC_CMD_OP(cmd, 1, 62, 1, char, (queue)->destination.stash_ctrl); \ + MC_CMD_OP(cmd, 1, 63, 1, char, (queue)->destination.hold_active); \ + MC_CMD_OP(cmd, 1, 0, 32, uint32_t, (queue)->destination.id); \ + MC_CMD_OP(cmd, 2, 0, 64, uint64_t, (queue)->flc); \ + MC_CMD_OP(cmd, 3, 0, 64, uint64_t, (queue)->user_context); \ } while (0) -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_GET_RX_FLOW(cmd, tc_id, flow_id) \ -do { \ - MC_CMD_OP(cmd, 0, 16, 8, uint8_t, tc_id); \ - MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id); \ -} while (0) +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_CMD_GET_STATISTICS(cmd, page) \ + MC_CMD_OP(cmd, 0, 0, 8, uint8_t, page) /* cmd, param, offset, width, type, arg_name */ -#define DPNI_RSP_GET_RX_FLOW(cmd, attr) \ +#define DPNI_RSP_GET_STATISTICS(cmd, stat) \ do { \ - MC_RSP_OP(cmd, 0, 0, 32, int, attr->dest_cfg.dest_id); \ - MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->dest_cfg.priority);\ - MC_RSP_OP(cmd, 0, 40, 2, enum dpni_dest, attr->dest_cfg.dest_type); \ - MC_RSP_OP(cmd, 0, 42, 1, int, attr->order_preservation_en);\ - MC_RSP_OP(cmd, 1, 0, 64, uint64_t, attr->user_ctx); \ - MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->tail_drop_threshold); \ - MC_RSP_OP(cmd, 2, 32, 32, uint32_t, attr->fqid); \ - MC_RSP_OP(cmd, 3, 0, 4, enum dpni_flc_type, attr->flc_cfg.flc_type); \ - MC_RSP_OP(cmd, 3, 4, 4, enum dpni_stash_size, \ - attr->flc_cfg.frame_data_size);\ - MC_RSP_OP(cmd, 3, 8, 4, enum dpni_stash_size, \ - attr->flc_cfg.flow_context_size);\ - MC_RSP_OP(cmd, 3, 32, 32, uint32_t, attr->flc_cfg.options);\ - MC_RSP_OP(cmd, 4, 0, 64, uint64_t, attr->flc_cfg.flow_context);\ -} while (0) - -#define DPNI_CMD_SET_TX_CONF(cmd, flow_id, cfg) \ -do { \ - MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->queue_cfg.dest_cfg.priority); \ - MC_CMD_OP(cmd, 0, 40, 2, enum dpni_dest, \ - cfg->queue_cfg.dest_cfg.dest_type); \ - MC_CMD_OP(cmd, 0, 42, 1, int, cfg->errors_only); \ - MC_CMD_OP(cmd, 0, 46, 1, int, cfg->queue_cfg.order_preservation_en); \ - MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id); \ - MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->queue_cfg.user_ctx); \ - MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->queue_cfg.options); \ - MC_CMD_OP(cmd, 2, 32, 32, int, cfg->queue_cfg.dest_cfg.dest_id); \ - MC_CMD_OP(cmd, 3, 0, 32, uint32_t, \ - cfg->queue_cfg.tail_drop_threshold); \ - MC_CMD_OP(cmd, 4, 0, 4, enum dpni_flc_type, \ - cfg->queue_cfg.flc_cfg.flc_type); \ - MC_CMD_OP(cmd, 4, 4, 4, enum dpni_stash_size, \ - cfg->queue_cfg.flc_cfg.frame_data_size); \ - MC_CMD_OP(cmd, 4, 8, 4, enum dpni_stash_size, \ - cfg->queue_cfg.flc_cfg.flow_context_size); \ - MC_CMD_OP(cmd, 4, 32, 32, uint32_t, cfg->queue_cfg.flc_cfg.options); \ - MC_CMD_OP(cmd, 5, 0, 64, uint64_t, \ - cfg->queue_cfg.flc_cfg.flow_context); \ -} while (0) - -#define DPNI_CMD_GET_TX_CONF(cmd, flow_id) \ - MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id) - -#define DPNI_RSP_GET_TX_CONF(cmd, attr) \ -do { \ - MC_RSP_OP(cmd, 0, 32, 8, uint8_t, \ - attr->queue_attr.dest_cfg.priority); \ - MC_RSP_OP(cmd, 0, 40, 2, enum dpni_dest, \ - attr->queue_attr.dest_cfg.dest_type); \ - MC_RSP_OP(cmd, 0, 42, 1, int, attr->errors_only); \ - MC_RSP_OP(cmd, 0, 46, 1, int, \ - attr->queue_attr.order_preservation_en); \ - MC_RSP_OP(cmd, 1, 0, 64, uint64_t, attr->queue_attr.user_ctx); \ - MC_RSP_OP(cmd, 2, 32, 32, int, attr->queue_attr.dest_cfg.dest_id); \ - MC_RSP_OP(cmd, 3, 0, 32, uint32_t, \ - attr->queue_attr.tail_drop_threshold); \ - MC_RSP_OP(cmd, 3, 32, 32, uint32_t, attr->queue_attr.fqid); \ - MC_RSP_OP(cmd, 4, 0, 4, enum dpni_flc_type, \ - attr->queue_attr.flc_cfg.flc_type); \ - MC_RSP_OP(cmd, 4, 4, 4, enum dpni_stash_size, \ - attr->queue_attr.flc_cfg.frame_data_size); \ - MC_RSP_OP(cmd, 4, 8, 4, enum dpni_stash_size, \ - attr->queue_attr.flc_cfg.flow_context_size); \ - MC_RSP_OP(cmd, 4, 32, 32, uint32_t, attr->queue_attr.flc_cfg.options); \ - MC_RSP_OP(cmd, 5, 0, 64, uint64_t, \ - attr->queue_attr.flc_cfg.flow_context); \ + MC_RSP_OP(cmd, 0, 0, 64, uint64_t, (stat)->counter0); \ + MC_RSP_OP(cmd, 1, 0, 64, uint64_t, (stat)->counter1); \ + MC_RSP_OP(cmd, 2, 0, 64, uint64_t, (stat)->counter2); \ + MC_RSP_OP(cmd, 3, 0, 64, uint64_t, (stat)->counter3); \ + MC_RSP_OP(cmd, 4, 0, 64, uint64_t, (stat)->counter4); \ + MC_RSP_OP(cmd, 5, 0, 64, uint64_t, (stat)->counter5); \ + MC_RSP_OP(cmd, 6, 0, 64, uint64_t, (stat)->counter6); \ } while (0) enum net_prot { @@ -645,6 +432,33 @@ int dpni_close(struct fsl_mc_io *mc_io, #define DPNI_OPT_FS_MASK_SUPPORT 0x00040000 /** + * enum dpni_queue_type - Identifies a type of queue targeted by the command + * @DPNI_QUEUE_RX: Rx queue + * @DPNI_QUEUE_TX: Tx queue + * @DPNI_QUEUE_TX_CONFIRM: Tx confirmation queue + * @DPNI_QUEUE_RX_ERR: Rx error queue + */ +enum dpni_queue_type { + DPNI_QUEUE_RX, + DPNI_QUEUE_TX, + DPNI_QUEUE_TX_CONFIRM, + DPNI_QUEUE_RX_ERR, +}; + +struct dpni_cfg { + uint8_t mac_addr[6]; + struct { + uint32_t options; + uint16_t fs_entries; + uint8_t num_queues; + uint8_t num_tcs; + uint8_t mac_entries; + uint8_t vlan_entries; + uint8_t qos_entries; + } adv; +}; + +/** * struct dpni_extended_cfg - Structure representing extended DPNI configuration * @tc_cfg: TCs configuration * @ipr_cfg: IP reassembly configuration @@ -685,78 +499,21 @@ struct dpni_extended_cfg { }; /** - * dpni_prepare_extended_cfg() - function prepare extended parameters - * @cfg: extended structure - * @ext_cfg_buf: Zeroed 256 bytes of memory before mapping it to DMA + * dpni_prepare_cfg() - function prepare parameters + * @cfg: cfg structure + * @cfg_buf: Zeroed 256 bytes of memory before mapping it to DMA * * This function has to be called before dpni_create() */ -int dpni_prepare_extended_cfg(const struct dpni_extended_cfg *cfg, - uint8_t *ext_cfg_buf); - -/** - * struct dpni_cfg - Structure representing DPNI configuration - * @mac_addr: Primary MAC address - * @adv: Advanced parameters; default is all zeros; - * use this structure to change default settings - */ -struct dpni_cfg { - uint8_t mac_addr[6]; - /** - * struct adv - Advanced parameters - * @options: Mask of available options; use 'DPNI_OPT_<X>' values - * @start_hdr: Selects the packet starting header for parsing; - * 'NET_PROT_NONE' is treated as default: 'NET_PROT_ETH' - * @max_senders: Maximum number of different senders; used as the number - * of dedicated Tx flows; Non-power-of-2 values are rounded - * up to the next power-of-2 value as hardware demands it; - * '0' will be treated as '1' - * @max_tcs: Maximum number of traffic classes (for both Tx and Rx); - * '0' will e treated as '1' - * @max_unicast_filters: Maximum number of unicast filters; - * '0' is treated as '16' - * @max_multicast_filters: Maximum number of multicast filters; - * '0' is treated as '64' - * @max_qos_entries: if 'max_tcs > 1', declares the maximum entries in - * the QoS table; '0' is treated as '64' - * @max_qos_key_size: Maximum key size for the QoS look-up; - * '0' is treated as '24' which is enough for IPv4 - * 5-tuple - * @max_dist_key_size: Maximum key size for the distribution; - * '0' is treated as '24' which is enough for IPv4 5-tuple - * @max_policers: Maximum number of policers; - * should be between '0' and max_tcs - * @max_congestion_ctrl: Maximum number of congestion control groups - * (CGs); covers early drop and congestion notification - * requirements; - * should be between '0' and ('max_tcs' + 'max_senders') - * @ext_cfg_iova: I/O virtual address of 256 bytes DMA-able memory - * filled with the extended configuration by calling - * dpni_prepare_extended_cfg() - */ - struct { - uint32_t options; - enum net_prot start_hdr; - uint8_t max_senders; - uint8_t max_tcs; - uint8_t max_unicast_filters; - uint8_t max_multicast_filters; - uint8_t max_vlan_filters; - uint8_t max_qos_entries; - uint8_t max_qos_key_size; - uint8_t max_dist_key_size; - uint8_t max_policers; - uint8_t max_congestion_ctrl; - uint64_t ext_cfg_iova; - } adv; -}; - +int dpni_prepare_cfg(const struct dpni_cfg *cfg, + uint8_t *cfg_buf); /** * dpni_create() - Create the DPNI object * @mc_io: Pointer to MC portal's I/O object + * @token: Authentication token. * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' * @cfg: Configuration structure - * @token: Returned token; use in subsequent API calls + * @obj_id: Returned obj_id; use in subsequent API calls * * Create the DPNI object, allocate required resources and * perform required initialization. @@ -774,21 +531,24 @@ struct dpni_cfg { * Return: '0' on Success; Error code otherwise. */ int dpni_create(struct fsl_mc_io *mc_io, + uint16_t token, uint32_t cmd_flags, const struct dpni_cfg *cfg, - uint16_t *token); + uint32_t *obj_id); /** * dpni_destroy() - Destroy the DPNI object and release all its resources. * @mc_io: Pointer to MC portal's I/O object + * @token: Authentication token. * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object + * @obj_id: Returned obj_id; use in subsequent API calls * * Return: '0' on Success; error code otherwise. */ int dpni_destroy(struct fsl_mc_io *mc_io, + uint16_t token, uint32_t cmd_flags, - uint16_t token); + uint32_t obj_id); /** * struct dpni_pools_cfg - Structure representing buffer pools configuration @@ -867,49 +627,32 @@ int dpni_reset(struct fsl_mc_io *mc_io, /** * struct dpni_attr - Structure representing DPNI attributes - * @id: DPNI object ID - * @version: DPNI version - * @start_hdr: Indicates the packet starting header for parsing * @options: Mask of available options; reflects the value as was given in * object's creation - * @max_senders: Maximum number of different senders; used as the number - * of dedicated Tx flows; - * @max_tcs: Maximum number of traffic classes (for both Tx and Rx) + * @max_num_queues: Number of queues available (for both Tx and Rx) + * @max_num_tcs: Maximum number of traffic classes (for both Tx and Rx) + * @max_mac_entries: Maximum number of traffic classes (for both Tx and Rx) * @max_unicast_filters: Maximum number of unicast filters * @max_multicast_filters: Maximum number of multicast filters - * @max_vlan_filters: Maximum number of VLAN filters + * @max_vlan_entries: Maximum number of VLAN filters * @max_qos_entries: if 'max_tcs > 1', declares the maximum entries in QoS table + * @max_fs_entries: declares the maximum entries in flow steering table * @max_qos_key_size: Maximum key size for the QoS look-up - * @max_dist_key_size: Maximum key size for the distribution look-up - * @max_policers: Maximum number of policers; - * @max_congestion_ctrl: Maximum number of congestion control groups (CGs); - * @ext_cfg_iova: I/O virtual address of 256 bytes DMA-able memory; - * call dpni_extract_extended_cfg() to extract the extended configuration + * @max_fs_key_size: Maximum key size for the flow steering + * @wriop_version: Indicates revision of WRIOP hardware block */ struct dpni_attr { - int id; - /** - * struct version - DPNI version - * @major: DPNI major version - * @minor: DPNI minor version - */ - struct { - uint16_t major; - uint16_t minor; - } version; - enum net_prot start_hdr; + uint32_t id; uint32_t options; - uint8_t max_senders; - uint8_t max_tcs; - uint8_t max_unicast_filters; - uint8_t max_multicast_filters; - uint8_t max_vlan_filters; + uint8_t max_num_queues; + uint8_t max_num_tcs; + uint8_t max_mac_entries; + uint8_t max_vlan_entries; uint8_t max_qos_entries; + uint16_t max_fs_entries; uint8_t max_qos_key_size; - uint8_t max_dist_key_size; - uint8_t max_policers; - uint8_t max_congestion_ctrl; - uint64_t ext_cfg_iova; + uint8_t max_fs_key_size; + uint16_t wriop_version; }; /** @@ -927,14 +670,14 @@ int dpni_get_attributes(struct fsl_mc_io *mc_io, struct dpni_attr *attr); /** - * dpni_extract_extended_cfg() - extract the extended parameters - * @cfg: extended structure - * @ext_cfg_buf: 256 bytes of DMA-able memory + * dpni_extract_cfg() - extract the parameters + * @cfg: cfg structure + * @cfg_buf: 256 bytes of DMA-able memory * * This function has to be called after dpni_get_attributes() */ -int dpni_extract_extended_cfg(struct dpni_extended_cfg *cfg, - const uint8_t *ext_cfg_buf); +int dpni_extract_cfg(struct dpni_cfg *cfg, + const uint8_t *cfg_buf); /** * DPNI errors @@ -1037,7 +780,7 @@ int dpni_set_errors_behavior(struct fsl_mc_io *mc_io, * @data_tail_room: Data tail room */ struct dpni_buffer_layout { - uint32_t options; + uint16_t options; int pass_timestamp; int pass_parser_result; int pass_frame_status; @@ -1048,96 +791,38 @@ struct dpni_buffer_layout { }; /** - * dpni_get_rx_buffer_layout() - Retrieve Rx buffer layout attributes. + * dpni_get_buffer_layout() - Retrieve buffer layout attributes. * @mc_io: Pointer to MC portal's I/O object * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' * @token: Token of DPNI object * @layout: Returns buffer layout attributes + * @type: DPNI queue type * * Return: '0' on Success; Error code otherwise. */ -int dpni_get_rx_buffer_layout(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpni_buffer_layout *layout); +int dpni_get_buffer_layout(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + const struct dpni_buffer_layout *layout, + enum dpni_queue_type type); /** - * dpni_set_rx_buffer_layout() - Set Rx buffer layout configuration. + * dpni_set_buffer_layout() - Set buffer layout configuration. * @mc_io: Pointer to MC portal's I/O object * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' * @token: Token of DPNI object * @layout: Buffer layout configuration + * @type: DPNI queue type * * Return: '0' on Success; Error code otherwise. * * @warning Allowed only when DPNI is disabled */ -int dpni_set_rx_buffer_layout(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const struct dpni_buffer_layout *layout); - -/** - * dpni_get_tx_buffer_layout() - Retrieve Tx buffer layout attributes. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @layout: Returns buffer layout attributes - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_get_tx_buffer_layout(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpni_buffer_layout *layout); - -/** - * dpni_set_tx_buffer_layout() - Set Tx buffer layout configuration. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @layout: Buffer layout configuration - * - * Return: '0' on Success; Error code otherwise. - * - * @warning Allowed only when DPNI is disabled - */ -int dpni_set_tx_buffer_layout(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const struct dpni_buffer_layout *layout); - -/** - * dpni_get_tx_conf_buffer_layout() - Retrieve Tx confirmation buffer layout - * attributes. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @layout: Returns buffer layout attributes - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_get_tx_conf_buffer_layout(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpni_buffer_layout *layout); - -/** - * dpni_set_tx_conf_buffer_layout() - Set Tx confirmation buffer layout - * configuration. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @layout: Buffer layout configuration - * - * Return: '0' on Success; Error code otherwise. - * - * @warning Allowed only when DPNI is disabled - */ -int dpni_set_tx_conf_buffer_layout(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const struct dpni_buffer_layout *layout); +int dpni_set_buffer_layout(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + const struct dpni_buffer_layout *layout, + enum dpni_queue_type type); /** * dpni_get_qdid() - Get the Queuing Destination ID (QDID) that should be used @@ -1169,68 +854,6 @@ int dpni_get_tx_data_offset(struct fsl_mc_io *mc_io, uint16_t token, uint16_t *data_offset); -/** - * enum dpni_counter - DPNI counter types - * @DPNI_CNT_ING_FRAME: Counts ingress frames - * @DPNI_CNT_ING_BYTE: Counts ingress bytes - * @DPNI_CNT_ING_FRAME_DROP: Counts ingress frames dropped due to explicit - * 'drop' setting - * @DPNI_CNT_ING_FRAME_DISCARD: Counts ingress frames discarded due to errors - * @DPNI_CNT_ING_MCAST_FRAME: Counts ingress multicast frames - * @DPNI_CNT_ING_MCAST_BYTE: Counts ingress multicast bytes - * @DPNI_CNT_ING_BCAST_FRAME: Counts ingress broadcast frames - * @DPNI_CNT_ING_BCAST_BYTES: Counts ingress broadcast bytes - * @DPNI_CNT_EGR_FRAME: Counts egress frames - * @DPNI_CNT_EGR_BYTE: Counts egress bytes - * @DPNI_CNT_EGR_FRAME_DISCARD: Counts egress frames discarded due to errors - */ -enum dpni_counter { - DPNI_CNT_ING_FRAME = 0x0, - DPNI_CNT_ING_BYTE = 0x1, - DPNI_CNT_ING_FRAME_DROP = 0x2, - DPNI_CNT_ING_FRAME_DISCARD = 0x3, - DPNI_CNT_ING_MCAST_FRAME = 0x4, - DPNI_CNT_ING_MCAST_BYTE = 0x5, - DPNI_CNT_ING_BCAST_FRAME = 0x6, - DPNI_CNT_ING_BCAST_BYTES = 0x7, - DPNI_CNT_EGR_FRAME = 0x8, - DPNI_CNT_EGR_BYTE = 0x9, - DPNI_CNT_EGR_FRAME_DISCARD = 0xa -}; - -/** - * dpni_get_counter() - Read a specific DPNI counter - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @counter: The requested counter - * @value: Returned counter's current value - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_get_counter(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - enum dpni_counter counter, - uint64_t *value); - -/** - * dpni_set_counter() - Set (or clear) a specific DPNI counter - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @counter: The requested counter - * @value: New counter value; typically pass '0' for resetting - * the counter. - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_set_counter(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - enum dpni_counter counter, - uint64_t value); - /* Enable auto-negotiation */ #define DPNI_LINK_OPT_AUTONEG 0x0000000000000001ULL /* Enable half-duplex mode */ @@ -1506,183 +1129,199 @@ struct dpni_queue_attr { #define DPNI_TX_FLOW_OPT_L4_CHKSUM_GEN 0x00000020 /** - * struct dpni_tx_flow_cfg - Structure representing Tx flow configuration - * @options: Flags representing the suggested modifications to the Tx flow; - * Use any combination 'DPNI_TX_FLOW_OPT_<X>' flags - * @use_common_tx_conf_queue: Set to '1' to use the common (default) Tx - * confirmation and error queue; Set to '0' to use the private - * Tx confirmation and error queue; valid only if - * 'DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED' wasn't set at DPNI creation - * and 'DPNI_TX_FLOW_OPT_TX_CONF_ERROR' is contained in 'options' - * @l3_chksum_gen: Set to '1' to enable L3 checksum generation; '0' to disable; - * valid only if 'DPNI_TX_FLOW_OPT_L3_CHKSUM_GEN' is contained in 'options' - * @l4_chksum_gen: Set to '1' to enable L4 checksum generation; '0' to disable; - * valid only if 'DPNI_TX_FLOW_OPT_L4_CHKSUM_GEN' is contained in 'options' - */ -struct dpni_tx_flow_cfg { - uint32_t options; - int use_common_tx_conf_queue; - int l3_chksum_gen; - int l4_chksum_gen; -}; - -/** - * dpni_set_tx_flow() - Set Tx flow configuration + * dpni_get_api_version - Retrieve DPNI Major and Minor version info. + * * @mc_io: Pointer to MC portal's I/O object * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @flow_id: Provides (or returns) the sender's flow ID; - * for each new sender set (*flow_id) to 'DPNI_NEW_FLOW_ID' to generate - * a new flow_id; this ID should be used as the QDBIN argument - * in enqueue operations - * @cfg: Tx flow configuration + * @major_ver: DPNI major version + * @minor_ver: DPNI minor version * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_set_tx_flow(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - uint16_t *flow_id, - const struct dpni_tx_flow_cfg *cfg); - -/** - * struct dpni_tx_flow_attr - Structure representing Tx flow attributes - * @use_common_tx_conf_queue: '1' if using common (default) Tx confirmation and - * error queue; '0' if using private Tx confirmation and error queue - * @l3_chksum_gen: '1' if L3 checksum generation is enabled; '0' if disabled - * @l4_chksum_gen: '1' if L4 checksum generation is enabled; '0' if disabled - */ -struct dpni_tx_flow_attr { - int use_common_tx_conf_queue; - int l3_chksum_gen; - int l4_chksum_gen; + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_api_version(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 *major_ver, + u16 *minor_ver); + +/** + * enum dpni_confirmation_mode - Defines DPNI options supported for Tx + * confirmation + * @DPNI_CONF_AFFINE: For each Tx queue set associated with a sender there is + * an affine Tx Confirmation queue + * @DPNI_CONF_SINGLE: All Tx queues are associated with a single Tx + * confirmation queue + * @DPNI_CONF_DISABLE: Tx frames are not confirmed. This must be associated + * with proper FD set-up to have buffers release to a Buffer Pool, otherwise + * buffers will be leaked. + */ +enum dpni_confirmation_mode { + DPNI_CONF_AFFINE, + DPNI_CONF_SINGLE, + DPNI_CONF_DISABLE, }; -/** - * dpni_get_tx_flow() - Get Tx flow attributes - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @flow_id: The sender's flow ID, as returned by the - * dpni_set_tx_flow() function - * @attr: Returned Tx flow attributes - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_get_tx_flow(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - uint16_t flow_id, - struct dpni_tx_flow_attr *attr); +struct dpni_tx_confirmation_mode { + uint32_t pad; + uint8_t confirmation_mode; +}; /** - * struct dpni_tx_conf_cfg - Structure representing Tx conf configuration - * @errors_only: Set to '1' to report back only error frames; - * Set to '0' to confirm transmission/error for all transmitted frames; - * @queue_cfg: Queue configuration + * struct dpni_queue - Queue structure + * @fqid: FQID used for enqueueing to and/or configuration of this specific FQ + * @qdbin: Queueing bin, used to enqueue using QDID, DQBIN, QPRI. Only relevant + * for Tx queues. + * @flc: FLC value for traffic dequeued from this queue. + * @user_context: User data, presented to the user along with any frames + * from this queue. Not relevant for Tx queues. */ -struct dpni_tx_conf_cfg { - int errors_only; - struct dpni_queue_cfg queue_cfg; +struct dpni_queue { + /** + * struct destination - Destination structure + * @id: ID of the destination, only relevant if DEST_TYPE is > 0. + * Identifies either a DPIO or a DPCON object. Not relevant for Tx + * queues. + * @type: May be one of the following: + * 0 - No destination, queue can be manually queried, but won't + * push traffic or notifications to a DPIO; + * 1 - The destination is DPIO. When traffic becomes available in + * the queue a FQDAN (FQ data available notification) will be + * generated to selected DPIO; + * 2 - The destination is a DPCON. The queue is associated with a + * DPCON object for purpose of scheduling between multiple + * queues. The DPCON may be independently configured to + * generate notifications. Not relevant for Tx queues. + * @hold_active: Hold active + */ + struct { + uint32_t id; + enum dpni_dest type; + char hold_active; + char stash_ctrl; + } destination; + uint8_t options; + uint32_t fqid; + uint16_t qdbin; + uint64_t flc; + uint64_t user_context; }; /** - * dpni_set_tx_conf() - Set Tx confirmation and error queue configuration - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @flow_id: The sender's flow ID, as returned by the - * dpni_set_tx_flow() function; - * use 'DPNI_COMMON_TX_CONF' for common tx-conf - * @cfg: Queue configuration + * dpni_set_queue() - Set queue parameters + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @type: Type of queue + * @tc: Traffic class, in range 0 to NUM_TCS - 1 + * @index: Selects the specific queue out of the set allocated for the same + * TC. Value must be in range 0 to NUM_QUEUES - 1 + * @queue: Queue structure * - * If either 'DPNI_OPT_TX_CONF_DISABLED' or - * 'DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED' were selected at DPNI creation, - * this function can ONLY be used with 'flow_id == DPNI_COMMON_TX_CONF'; - * i.e. only serve the common tx-conf-err queue; - * if 'DPNI_OPT_TX_CONF_DISABLED' was selected, only error frames are reported - * back - successfully transmitted frames are not confirmed. Otherwise, all - * transmitted frames are sent for confirmation. + * Return: '0' on Success; Error code otherwise. + */ +int dpni_set_queue(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + enum dpni_queue_type type, + uint8_t tc, + uint8_t index, + const struct dpni_queue *queue); + +/** + * dpni_get_queue() - Get queue parameters + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @type: Type of queue + * @tc: Traffic class, in range 0 to NUM_TCS - 1 + * @index: Selects the specific queue out of the set allocated for the same + * TC. Value must be in range 0 to NUM_QUEUES - 1 + * @queue: Queue structure * - * Return: '0' on Success; Error code otherwise. + * Return: '0' on Success; Error code otherwise. */ -int dpni_set_tx_conf(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - uint16_t flow_id, - const struct dpni_tx_conf_cfg *cfg); +int dpni_get_queue(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + enum dpni_queue_type type, + uint8_t tc, + uint8_t index, + struct dpni_queue *queue); /** - * struct dpni_tx_conf_attr - Structure representing Tx conf attributes - * @errors_only: '1' if only error frames are reported back; '0' if all - * transmitted frames are confirmed - * @queue_attr: Queue attributes + * dpni_set_tx_confirmation_mode() - Set TX conf mode + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @mode: DPNI confirmation mode type + * + * Return: '0' on Success; Error code otherwise. */ -struct dpni_tx_conf_attr { - int errors_only; - struct dpni_queue_attr queue_attr; +int dpni_set_tx_confirmation_mode(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + enum dpni_confirmation_mode mode); +struct dpni_statistics { + /** + * Page_0 statistics structure + * @ingress_all_frames: Ingress frame count + * @ingress_all_bytes: Ingress byte count + * @ingress_multicast_frames: Ingress multicast frame count + * @ingress_multicast_bytes: Ingress multicast byte count + * @ingress_broadcast_frames: Ingress broadcast frame count + * @ingress_broadcast_bytes: Ingress broadcast byte count + * + * Page_1 statistics structure + * @egress_all_frames: Egress frame count + * @egress_all_bytes: Egress byte count + * @egress_multicast_frames: Egress multicast frame count + * @egress_multicast_bytes: Egress multicast byte count + * @egress_broadcast_frames: Egress broadcast frame count + * @egress_broadcast_bytes: Egress broadcast byte count + * + * Page_2 statistics structure + * @ingress_filtered_frames: Ingress filtered frame count + * @ingress_discarded_frames: Ingress discarded frame count + * @ingress_nobuffer_discards: Ingress discarded frame count due to + * lack of buffers. + * @egress_discarded_frames: Egress discarded frame count + * @egress_confirmed_frames: Egress confirmed frame count + */ + + uint64_t counter0; + uint64_t counter1; + uint64_t counter2; + uint64_t counter3; + uint64_t counter4; + uint64_t counter5; + uint64_t counter6; }; /** - * dpni_get_tx_conf() - Get Tx confirmation and error queue attributes + * dpni_get_statistics() - Get DPNI statistics * @mc_io: Pointer to MC portal's I/O object * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' * @token: Token of DPNI object - * @flow_id: The sender's flow ID, as returned by the - * dpni_set_tx_flow() function; - * use 'DPNI_COMMON_TX_CONF' for common tx-conf - * @attr: Returned tx-conf attributes - * - * If either 'DPNI_OPT_TX_CONF_DISABLED' or - * 'DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED' were selected at DPNI creation, - * this function can ONLY be used with 'flow_id == DPNI_COMMON_TX_CONF'; - * i.e. only serve the common tx-conf-err queue; + * @page: Selects the statistics page to retrieve, see DPNI_GET_STATISTICS + * output. Pages are numbered 0 to 2. + * @stat: Structure containing the statistics * * Return: '0' on Success; Error code otherwise. */ -int dpni_get_tx_conf(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - uint16_t flow_id, - struct dpni_tx_conf_attr *attr); -/** - * dpni_set_rx_flow() - Set Rx flow configuration - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @tc_id: Traffic class selection (0-7); - * use 'DPNI_ALL_TCS' to set all TCs and all flows - * @flow_id: Rx flow id within the traffic class; use - * 'DPNI_ALL_TC_FLOWS' to set all flows within - * this tc_id; ignored if tc_id is set to - * 'DPNI_ALL_TCS'; - * @cfg: Rx flow configuration - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_set_rx_flow(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - uint8_t tc_id, - uint16_t flow_id, - const struct dpni_queue_cfg *cfg); +int dpni_get_statistics(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + uint8_t page, + struct dpni_statistics *stat); /** - * dpni_get_rx_flow() - Get Rx flow attributes + * dpni_reset_statistics() - Clears DPNI statistics * @mc_io: Pointer to MC portal's I/O object * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' * @token: Token of DPNI object - * @tc_id: Traffic class selection (0-7) - * @flow_id: Rx flow id within the traffic class - * @attr: Returned Rx flow attributes * * Return: '0' on Success; Error code otherwise. */ -int dpni_get_rx_flow(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - uint8_t tc_id, - uint16_t flow_id, - struct dpni_queue_attr *attr); - +int dpni_reset_statistics(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token); #endif /* _FSL_DPNI_H */ diff --git a/include/fsl-mc/fsl_dprc.h b/include/fsl-mc/fsl_dprc.h index 535c789c95..8ad01d4f51 100644 --- a/include/fsl-mc/fsl_dprc.h +++ b/include/fsl-mc/fsl_dprc.h @@ -1,8 +1,8 @@ /* * Freescale Layerscape MC I/O wrapper * - * Copyright (C) 2013-2015 Freescale Semiconductor, Inc. - * Author: German Rivera <German.Rivera@freescale.com> + * Copyright (C) 2013-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -10,29 +10,30 @@ #define _FSL_DPRC_H /* DPRC Version */ -#define DPRC_VER_MAJOR 5 +#define DPRC_VER_MAJOR 6 #define DPRC_VER_MINOR 1 /* Command IDs */ -#define DPRC_CMDID_CLOSE 0x800 -#define DPRC_CMDID_OPEN 0x805 -#define DPRC_CMDID_CREATE 0x905 - -#define DPRC_CMDID_GET_ATTR 0x004 -#define DPRC_CMDID_RESET_CONT 0x005 - -#define DPRC_CMDID_CREATE_CONT 0x151 -#define DPRC_CMDID_DESTROY_CONT 0x152 -#define DPRC_CMDID_GET_CONT_ID 0x830 -#define DPRC_CMDID_GET_OBJ_COUNT 0x159 -#define DPRC_CMDID_GET_OBJ 0x15A -#define DPRC_CMDID_GET_RES_COUNT 0x15B -#define DPRC_CMDID_GET_RES_IDS 0x15C -#define DPRC_CMDID_GET_OBJ_REG 0x15E - -#define DPRC_CMDID_CONNECT 0x167 -#define DPRC_CMDID_DISCONNECT 0x168 -#define DPRC_CMDID_GET_CONNECTION 0x16C +#define DPRC_CMDID_CLOSE 0x8001 +#define DPRC_CMDID_OPEN 0x8051 +#define DPRC_CMDID_CREATE 0x9051 + +#define DPRC_CMDID_GET_ATTR 0x0041 +#define DPRC_CMDID_RESET_CONT 0x0051 +#define DPRC_CMDID_GET_API_VERSION 0xa051 + +#define DPRC_CMDID_CREATE_CONT 0x1511 +#define DPRC_CMDID_DESTROY_CONT 0x1521 +#define DPRC_CMDID_GET_CONT_ID 0x8301 +#define DPRC_CMDID_GET_OBJ_COUNT 0x1591 +#define DPRC_CMDID_GET_OBJ 0x15A1 +#define DPRC_CMDID_GET_RES_COUNT 0x15B1 +#define DPRC_CMDID_GET_RES_IDS 0x15C1 +#define DPRC_CMDID_GET_OBJ_REG 0x15E1 + +#define DPRC_CMDID_CONNECT 0x1671 +#define DPRC_CMDID_DISCONNECT 0x1681 +#define DPRC_CMDID_GET_CONNECTION 0x16C1 /* cmd, param, offset, width, type, arg_name */ #define DPRC_RSP_GET_CONTAINER_ID(cmd, container_id) \ @@ -88,8 +89,6 @@ do { \ MC_RSP_OP(cmd, 0, 32, 16, uint16_t, attr->icid); \ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, attr->options);\ MC_RSP_OP(cmd, 1, 32, 32, int, attr->portal_id); \ - MC_RSP_OP(cmd, 2, 0, 16, uint16_t, attr->version.major);\ - MC_RSP_OP(cmd, 2, 16, 16, uint16_t, attr->version.minor);\ } while (0) /* cmd, param, offset, width, type, arg_name */ @@ -345,9 +344,9 @@ do { \ #define DPRC_CMD_CONNECT(cmd, endpoint1, endpoint2, cfg) \ do { \ MC_CMD_OP(cmd, 0, 0, 32, int, endpoint1->id); \ - MC_CMD_OP(cmd, 0, 32, 16, uint16_t, endpoint1->if_id); \ + MC_CMD_OP(cmd, 0, 32, 32, int, endpoint1->if_id); \ MC_CMD_OP(cmd, 1, 0, 32, int, endpoint2->id); \ - MC_CMD_OP(cmd, 1, 32, 16, uint16_t, endpoint2->if_id); \ + MC_CMD_OP(cmd, 1, 32, 32, int, endpoint2->if_id); \ MC_CMD_OP(cmd, 2, 0, 8, char, endpoint1->type[0]); \ MC_CMD_OP(cmd, 2, 8, 8, char, endpoint1->type[1]); \ MC_CMD_OP(cmd, 2, 16, 8, char, endpoint1->type[2]); \ @@ -410,8 +409,8 @@ do { \ /* cmd, param, offset, width, type, arg_name */ #define DPRC_CMD_GET_CONNECTION(cmd, endpoint1) \ do { \ - MC_CMD_OP(cmd, 0, 0, 32, int, endpoint1->id); \ - MC_CMD_OP(cmd, 0, 32, 16, uint16_t, endpoint1->if_id); \ + MC_CMD_OP(cmd, 0, 0, 32, int, endpoint1->id); \ + MC_CMD_OP(cmd, 0, 32, 32, int, endpoint1->if_id); \ MC_CMD_OP(cmd, 1, 0, 8, char, endpoint1->type[0]); \ MC_CMD_OP(cmd, 1, 8, 8, char, endpoint1->type[1]); \ MC_CMD_OP(cmd, 1, 16, 8, char, endpoint1->type[2]); \ @@ -657,15 +656,6 @@ struct dprc_attributes { uint16_t icid; int portal_id; uint64_t options; - /** - * struct version - DPRC version - * @major: DPRC major version - * @minor: DPRC minor version - */ - struct { - uint16_t major; - uint16_t minor; - } version; }; /** @@ -950,4 +940,19 @@ int dprc_get_connection(struct fsl_mc_io *mc_io, struct dprc_endpoint *endpoint2, int *state); +/** + * dprc_get_api_version - Retrieve DPRC Major and Minor version info. + * + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @major_ver: DPRC major version + * @minor_ver: DPRC minor version + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_get_api_version(struct fsl_mc_io *mc_io, + u32 cmd_flags, + u16 *major_ver, + u16 *minor_ver); + #endif /* _FSL_DPRC_H */ diff --git a/include/fsl-mc/fsl_mc_cmd.h b/include/fsl-mc/fsl_mc_cmd.h index f3d1498cc0..1ec67b5491 100644 --- a/include/fsl-mc/fsl_mc_cmd.h +++ b/include/fsl-mc/fsl_mc_cmd.h @@ -1,4 +1,5 @@ -/* Copyright 2013-2015 Freescale Semiconductor Inc. +/* Copyright 2013-2016 Freescale Semiconductor Inc. + * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -24,6 +25,15 @@ struct mc_command { uint64_t params[MC_CMD_NUM_OF_PARAMS]; }; +struct mc_rsp_create { + __le32 object_id; +}; + +struct mc_rsp_api_ver { + __le16 major_ver; + __le16 minor_ver; +}; + enum mc_cmd_status { MC_CMD_STATUS_OK = 0x0, /*!< Completed successfully */ MC_CMD_STATUS_READY = 0x1, /*!< Ready to be processed */ @@ -51,15 +61,15 @@ enum mc_cmd_status { #define MC_CMD_FLAG_INTR_DIS 0x01000000 -#define MC_CMD_HDR_CMDID_O 52 /* Command ID field offset */ -#define MC_CMD_HDR_CMDID_S 12 /* Command ID field size */ +#define MC_CMD_HDR_CMDID_O 48 /* Command ID field offset */ +#define MC_CMD_HDR_CMDID_S 16 /* Command ID field size */ #define MC_CMD_HDR_STATUS_O 16 /* Status field offset */ -#define MC_CMD_HDR_TOKEN_O 38 /* Token field offset */ -#define MC_CMD_HDR_TOKEN_S 10 /* Token field size */ +#define MC_CMD_HDR_TOKEN_O 32 /* Token field offset */ +#define MC_CMD_HDR_TOKEN_S 16 /* Token field size */ #define MC_CMD_HDR_STATUS_S 8 /* Status field size*/ #define MC_CMD_HDR_FLAGS_O 0 /* Flags field offset */ #define MC_CMD_HDR_FLAGS_S 32 /* Flags field size*/ -#define MC_CMD_HDR_FLAGS_MASK 0xFF00FF00 /* Command flags mask */ +#define MC_CMD_HDR_FLAGS_MASK 0x0000FFFF /* Command flags mask */ #define MC_CMD_HDR_READ_STATUS(_hdr) \ ((enum mc_cmd_status)mc_dec((_hdr), \ @@ -80,11 +90,19 @@ enum mc_cmd_status { #define MC_RSP_OP(_cmd, _param, _offset, _width, _type, _arg) \ (_arg = (_type)mc_dec(_cmd.params[_param], (_offset), (_width))) +/* cmd, param, offset, width, type, arg_name */ +#define MC_CMD_READ_OBJ_ID(cmd, obj_id) \ + MC_RSP_OP(cmd, 0, 0, 32, uint32_t, obj_id) + +/* cmd, param, offset, width, type, arg_name */ +#define CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, object_id) \ + MC_CMD_OP(cmd, 0, 0, 32, uint32_t, object_id) + static inline uint64_t mc_encode_cmd_header(uint16_t cmd_id, uint32_t cmd_flags, uint16_t token) { - uint64_t hdr; + uint64_t hdr = 0; hdr = mc_enc(MC_CMD_HDR_CMDID_O, MC_CMD_HDR_CMDID_S, cmd_id); hdr |= mc_enc(MC_CMD_HDR_FLAGS_O, MC_CMD_HDR_FLAGS_S, @@ -144,4 +162,22 @@ static inline enum mc_cmd_status mc_read_response( return status; } +/** + * mc_read_version - read version of the given cmd + * + * @cmd: pointer to a filled command + * @major_version: major version value for the given cmd + * @minor_version: minor version value for the given cmd + */ +static inline void mc_cmd_read_api_version(struct mc_command *cmd, + u16 *major_ver, + u16 *minor_ver) +{ + struct mc_rsp_api_ver *rsp_params; + + rsp_params = (struct mc_rsp_api_ver *)cmd->params; + *major_ver = le16_to_cpu(rsp_params->major_ver); + *minor_ver = le16_to_cpu(rsp_params->minor_ver); +} + #endif /* __FSL_MC_CMD_H */ diff --git a/include/fsl-mc/fsl_mc_private.h b/include/fsl-mc/fsl_mc_private.h index 17e0611964..2932d9d561 100644 --- a/include/fsl-mc/fsl_mc_private.h +++ b/include/fsl-mc/fsl_mc_private.h @@ -1,5 +1,6 @@ /* - * Copyright (C) 2014 Freescale Semiconductor + * Copyright (C) 2014-2016 Freescale Semiconductor + * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -29,6 +30,7 @@ extern struct fsl_mc_io *dflt_mc_io; * @struct dpbp_attr: DPBP attribute */ struct fsl_dpbp_obj { + uint32_t dpbp_id; uint16_t dpbp_handle; struct dpbp_attr dpbp_attr; }; @@ -41,7 +43,7 @@ extern struct fsl_dpbp_obj *dflt_dpbp; * @struct qbman_swp *sw_portal: SW portal object */ struct fsl_dpio_obj { - int dpio_id; + uint32_t dpio_id; uint16_t dpio_handle; struct qbman_swp *sw_portal; /** SW portal object */ }; @@ -56,7 +58,7 @@ extern struct fsl_dpio_obj *dflt_dpio; * @struct dpni_buffer_layout: DPNI buffer layout */ struct fsl_dpni_obj { - int dpni_id; + uint32_t dpni_id; uint16_t dpni_handle; struct dpni_attr dpni_attrs; struct dpni_buffer_layout buf_layout; diff --git a/include/image.h b/include/image.h index 127cfc5148..a128a623e5 100644 --- a/include/image.h +++ b/include/image.h @@ -152,6 +152,7 @@ enum { IH_OS_OSE, /* OSE */ IH_OS_PLAN9, /* Plan 9 */ IH_OS_OPENRTOS, /* OpenRTOS */ + IH_OS_ARM_TRUSTED_FIRMWARE, /* ARM Trusted Firmware */ IH_OS_COUNT, }; @@ -886,6 +887,7 @@ int bootz_setup(ulong image, ulong *start, ulong *end); /* image node */ #define FIT_DATA_PROP "data" +#define FIT_DATA_POSITION_PROP "data-position" #define FIT_DATA_OFFSET_PROP "data-offset" #define FIT_DATA_SIZE_PROP "data-size" #define FIT_TIMESTAMP_PROP "timestamp" @@ -967,6 +969,8 @@ int fit_image_get_entry(const void *fit, int noffset, ulong *entry); int fit_image_get_data(const void *fit, int noffset, const void **data, size_t *size); int fit_image_get_data_offset(const void *fit, int noffset, int *data_offset); +int fit_image_get_data_position(const void *fit, int noffset, + int *data_position); int fit_image_get_data_size(const void *fit, int noffset, int *data_size); int fit_image_hash_get_algo(const void *fit, int noffset, char **algo); diff --git a/include/linux/bitops.h b/include/linux/bitops.h index 576b15dc53..a47f6d17bb 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -5,9 +5,16 @@ #include <asm-generic/bitsperlong.h> #include <linux/compiler.h> +#ifdef __KERNEL__ #define BIT(nr) (1UL << (nr)) +#define BIT_ULL(nr) (1ULL << (nr)) #define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) #define BIT_WORD(nr) ((nr) / BITS_PER_LONG) +#define BIT_ULL_MASK(nr) (1ULL << ((nr) % BITS_PER_LONG_LONG)) +#define BIT_ULL_WORD(nr) ((nr) / BITS_PER_LONG_LONG) +#define BITS_PER_BYTE 8 +#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long)) +#endif /* * Create a contiguous bitmask starting at bit position @l and ending at diff --git a/include/linux/mtd/fsl_upm.h b/include/linux/mtd/fsl_upm.h index 0a949bca0d..a023860e7b 100644 --- a/include/linux/mtd/fsl_upm.h +++ b/include/linux/mtd/fsl_upm.h @@ -10,7 +10,7 @@ #ifndef __LINUX_MTD_NAND_FSL_UPM #define __LINUX_MTD_NAND_FSL_UPM -#include <linux/mtd/nand.h> +#include <linux/mtd/rawnand.h> #define FSL_UPM_WAIT_RUN_PATTERN 0x1 #define FSL_UPM_WAIT_WRITE_BYTE 0x2 diff --git a/include/linux/mtd/fsmc_nand.h b/include/linux/mtd/fsmc_nand.h index f0f77270af..bc3db030d0 100644 --- a/include/linux/mtd/fsmc_nand.h +++ b/include/linux/mtd/fsmc_nand.h @@ -8,7 +8,7 @@ #ifndef __FSMC_NAND_H__ #define __FSMC_NAND_H__ -#include <linux/mtd/nand.h> +#include <linux/mtd/rawnand.h> struct fsmc_regs { u32 ctrl; /* 0x00 */ diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 4bde251322..ba4cbba949 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -103,6 +103,36 @@ struct mtd_oob_ops { #else #define MTD_MAX_ECCPOS_ENTRIES_LARGE 680 #endif +/** + * struct mtd_oob_region - oob region definition + * @offset: region offset + * @length: region length + * + * This structure describes a region of the OOB area, and is used + * to retrieve ECC or free bytes sections. + * Each section is defined by an offset within the OOB area and a + * length. + */ +struct mtd_oob_region { + u32 offset; + u32 length; +}; + +/* + * struct mtd_ooblayout_ops - NAND OOB layout operations + * @ecc: function returning an ECC region in the OOB area. + * Should return -ERANGE if %section exceeds the total number of + * ECC sections. + * @free: function returning a free region in the OOB area. + * Should return -ERANGE if %section exceeds the total number of + * free sections. + */ +struct mtd_ooblayout_ops { + int (*ecc)(struct mtd_info *mtd, int section, + struct mtd_oob_region *oobecc); + int (*free)(struct mtd_info *mtd, int section, + struct mtd_oob_region *oobfree); +}; /* * Internal ECC layout control structure. For historical reasons, there is a @@ -179,6 +209,9 @@ struct mtd_info { #endif int index; + /* OOB layout description */ + const struct mtd_ooblayout_ops *ooblayout; + /* ECC layout structure pointer - read only! */ struct nand_ecclayout *ecclayout; @@ -278,6 +311,30 @@ struct mtd_info { int usecount; }; +int mtd_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *oobecc); +int mtd_ooblayout_find_eccregion(struct mtd_info *mtd, int eccbyte, + int *section, + struct mtd_oob_region *oobregion); +int mtd_ooblayout_get_eccbytes(struct mtd_info *mtd, u8 *eccbuf, + const u8 *oobbuf, int start, int nbytes); +int mtd_ooblayout_set_eccbytes(struct mtd_info *mtd, const u8 *eccbuf, + u8 *oobbuf, int start, int nbytes); +int mtd_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *oobfree); +int mtd_ooblayout_get_databytes(struct mtd_info *mtd, u8 *databuf, + const u8 *oobbuf, int start, int nbytes); +int mtd_ooblayout_set_databytes(struct mtd_info *mtd, const u8 *databuf, + u8 *oobbuf, int start, int nbytes); +int mtd_ooblayout_count_freebytes(struct mtd_info *mtd); +int mtd_ooblayout_count_eccbytes(struct mtd_info *mtd); + +static inline void mtd_set_ooblayout(struct mtd_info *mtd, + const struct mtd_ooblayout_ops *ooblayout) +{ + mtd->ooblayout = ooblayout; +} + static inline int mtd_oobavail(struct mtd_info *mtd, struct mtd_oob_ops *ops) { return ops->mode == MTD_OPS_AUTO_OOB ? mtd->oobavail : mtd->oobsize; diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/rawnand.h index d55807b2e2..6c3e838d80 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/rawnand.h @@ -1,6 +1,4 @@ /* - * linux/include/linux/mtd/nand.h - * * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> * Steven J. Hill <sjhill@realitydiluted.com> * Thomas Gleixner <tglx@linutronix.de> @@ -13,8 +11,8 @@ * Changelog: * See git changelog. */ -#ifndef __LINUX_MTD_NAND_H -#define __LINUX_MTD_NAND_H +#ifndef __LINUX_MTD_RAWNAND_H +#define __LINUX_MTD_RAWNAND_H #include <config.h> @@ -22,26 +20,27 @@ #include <linux/mtd/mtd.h> #include <linux/mtd/flashchip.h> #include <linux/mtd/bbm.h> +#include <asm/cache.h> struct mtd_info; struct nand_flash_dev; struct device_node; /* Scan and identify a NAND device */ -extern int nand_scan(struct mtd_info *mtd, int max_chips); +int nand_scan(struct mtd_info *mtd, int max_chips); /* * Separate phases of nand_scan(), allowing board driver to intervene * and override command or ECC setup according to flash type. */ -extern int nand_scan_ident(struct mtd_info *mtd, int max_chips, +int nand_scan_ident(struct mtd_info *mtd, int max_chips, struct nand_flash_dev *table); -extern int nand_scan_tail(struct mtd_info *mtd); +int nand_scan_tail(struct mtd_info *mtd); /* Free resources held by the NAND device */ -extern void nand_release(struct mtd_info *mtd); +void nand_release(struct mtd_info *mtd); /* Internal helper for board drivers which need to override command function */ -extern void nand_wait_ready(struct mtd_info *mtd); +void nand_wait_ready(struct mtd_info *mtd); /* * This constant declares the max. oobsize / page, which @@ -124,6 +123,8 @@ extern void nand_wait_ready(struct mtd_info *mtd); #define NAND_STATUS_READY 0x40 #define NAND_STATUS_WP 0x80 +#define NAND_DATA_IFACE_CHECK_ONLY -1 + /* * Constants for ECC_MODES */ @@ -153,6 +154,13 @@ typedef enum { * pages and you want to rely on the default implementation. */ #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) +#define NAND_ECC_MAXIMIZE BIT(1) +/* + * If your controller already sends the required NAND commands when + * reading or writing a page, then the framework is not supposed to + * send READ0 and SEQIN/PAGEPROG respectively. + */ +#define NAND_ECC_CUSTOM_PAGE_ACCESS BIT(2) /* Bit mask for flags passed to do_nand_read_ecc */ #define NAND_GET_DEVICE 0x80 @@ -195,12 +203,16 @@ typedef enum { */ #define NAND_NEED_SCRAMBLING 0x00002000 +/* Device needs 3rd row address cycle */ +#define NAND_ROW_ADDR_3 0x00004000 + /* Options valid for Samsung large page devices */ #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG /* Macros to identify the above */ #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) +#define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE) /* Non chip related options */ /* This option skips the bbt scan during initialization. */ @@ -478,6 +490,44 @@ struct nand_hw_control { }; /** + * struct nand_ecc_step_info - ECC step information of ECC engine + * @stepsize: data bytes per ECC step + * @strengths: array of supported strengths + * @nstrengths: number of supported strengths + */ +struct nand_ecc_step_info { + int stepsize; + const int *strengths; + int nstrengths; +}; + +/** + * struct nand_ecc_caps - capability of ECC engine + * @stepinfos: array of ECC step information + * @nstepinfos: number of ECC step information + * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step + */ +struct nand_ecc_caps { + const struct nand_ecc_step_info *stepinfos; + int nstepinfos; + int (*calc_ecc_bytes)(int step_size, int strength); +}; + +/* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */ +#define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \ +static const int __name##_strengths[] = { __VA_ARGS__ }; \ +static const struct nand_ecc_step_info __name##_stepinfo = { \ + .stepsize = __step, \ + .strengths = __name##_strengths, \ + .nstrengths = ARRAY_SIZE(__name##_strengths), \ +}; \ +static const struct nand_ecc_caps __name = { \ + .stepinfos = &__name##_stepinfo, \ + .nstepinfos = 1, \ + .calc_ecc_bytes = __calc, \ +} + +/** * struct nand_ecc_ctrl - Control structure for ECC * @mode: ECC mode * @steps: number of ECC steps per page @@ -567,6 +617,11 @@ struct nand_ecc_ctrl { int page); }; +static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc) +{ + return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS); +} + /** * struct nand_buffers - buffer structure for read/write * @ecccalc: buffer pointer for calculated ECC, size is oobsize. @@ -584,6 +639,131 @@ struct nand_buffers { }; /** + * struct nand_sdr_timings - SDR NAND chip timings + * + * This struct defines the timing requirements of a SDR NAND chip. + * These information can be found in every NAND datasheets and the timings + * meaning are described in the ONFI specifications: + * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing + * Parameters) + * + * All these timings are expressed in picoseconds. + * + * @tBERS_max: Block erase time + * @tCCS_min: Change column setup time + * @tPROG_max: Page program time + * @tR_max: Page read time + * @tALH_min: ALE hold time + * @tADL_min: ALE to data loading time + * @tALS_min: ALE setup time + * @tAR_min: ALE to RE# delay + * @tCEA_max: CE# access time + * @tCEH_min: CE# high hold time + * @tCH_min: CE# hold time + * @tCHZ_max: CE# high to output hi-Z + * @tCLH_min: CLE hold time + * @tCLR_min: CLE to RE# delay + * @tCLS_min: CLE setup time + * @tCOH_min: CE# high to output hold + * @tCS_min: CE# setup time + * @tDH_min: Data hold time + * @tDS_min: Data setup time + * @tFEAT_max: Busy time for Set Features and Get Features + * @tIR_min: Output hi-Z to RE# low + * @tITC_max: Interface and Timing Mode Change time + * @tRC_min: RE# cycle time + * @tREA_max: RE# access time + * @tREH_min: RE# high hold time + * @tRHOH_min: RE# high to output hold + * @tRHW_min: RE# high to WE# low + * @tRHZ_max: RE# high to output hi-Z + * @tRLOH_min: RE# low to output hold + * @tRP_min: RE# pulse width + * @tRR_min: Ready to RE# low (data only) + * @tRST_max: Device reset time, measured from the falling edge of R/B# to the + * rising edge of R/B#. + * @tWB_max: WE# high to SR[6] low + * @tWC_min: WE# cycle time + * @tWH_min: WE# high hold time + * @tWHR_min: WE# high to RE# low + * @tWP_min: WE# pulse width + * @tWW_min: WP# transition to WE# low + */ +struct nand_sdr_timings { + u64 tBERS_max; + u32 tCCS_min; + u64 tPROG_max; + u64 tR_max; + u32 tALH_min; + u32 tADL_min; + u32 tALS_min; + u32 tAR_min; + u32 tCEA_max; + u32 tCEH_min; + u32 tCH_min; + u32 tCHZ_max; + u32 tCLH_min; + u32 tCLR_min; + u32 tCLS_min; + u32 tCOH_min; + u32 tCS_min; + u32 tDH_min; + u32 tDS_min; + u32 tFEAT_max; + u32 tIR_min; + u32 tITC_max; + u32 tRC_min; + u32 tREA_max; + u32 tREH_min; + u32 tRHOH_min; + u32 tRHW_min; + u32 tRHZ_max; + u32 tRLOH_min; + u32 tRP_min; + u32 tRR_min; + u64 tRST_max; + u32 tWB_max; + u32 tWC_min; + u32 tWH_min; + u32 tWHR_min; + u32 tWP_min; + u32 tWW_min; +}; + +/** + * enum nand_data_interface_type - NAND interface timing type + * @NAND_SDR_IFACE: Single Data Rate interface + */ +enum nand_data_interface_type { + NAND_SDR_IFACE, +}; + +/** + * struct nand_data_interface - NAND interface timing + * @type: type of the timing + * @timings: The timing, type according to @type + */ +struct nand_data_interface { + enum nand_data_interface_type type; + union { + struct nand_sdr_timings sdr; + } timings; +}; + +/** + * nand_get_sdr_timings - get SDR timing from data interface + * @conf: The data interface + */ +static inline const struct nand_sdr_timings * +nand_get_sdr_timings(const struct nand_data_interface *conf) +{ + if (conf->type != NAND_SDR_IFACE) + return ERR_PTR(-EINVAL); + + return &conf->timings.sdr; +} + +/** * struct nand_chip - NAND Private Flash Chip Data * @mtd: MTD device registered to the MTD framework * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the @@ -614,6 +794,7 @@ struct nand_buffers { * setting the read-retry mode. Mostly needed for MLC NAND. * @ecc: [BOARDSPECIFIC] ECC control structure * @buffers: buffer structure for read/write + * @buf_align: minimum buffer alignment required by a platform * @hwcontrol: platform-specific hardware control structure * @erase: [REPLACEABLE] erase function * @scan_bbt: [REPLACEABLE] function to scan bad block table @@ -646,10 +827,9 @@ struct nand_buffers { * also from the datasheet. It is the recommended ECC step * size, if known; if unknown, set to zero. * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is - * either deduced from the datasheet if the NAND - * chip is not ONFI compliant or set to 0 if it is - * (an ONFI chip is always configured in mode 0 - * after a NAND reset) + * set to the actually used ONFI mode if the chip is + * ONFI compliant or deduced from the datasheet if + * the NAND chip is not ONFI compliant. * @numchips: [INTERN] number of physical chips * @chipsize: [INTERN] the size of one chip for multichip arrays * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 @@ -669,6 +849,10 @@ struct nand_buffers { * @read_retries: [INTERN] the number of read retry modes supported * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand + * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If + * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this + * means the configuration should not be applied but + * only checked. * @bbt: [INTERN] bad block table pointer * @bbt_td: [REPLACEABLE] bad block table descriptor for flash * lookup. @@ -679,9 +863,6 @@ struct nand_buffers { * structure which is shared among multiple independent * devices. * @priv: [OPTIONAL] pointer to private chip data - * @errstat: [OPTIONAL] hardware specific function to perform - * additional error status checks (determine if errors are - * correctable). * @write_page: [REPLACEABLE] High-level page write function */ @@ -707,16 +888,17 @@ struct nand_chip { int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); int (*erase)(struct mtd_info *mtd, int page); int (*scan_bbt)(struct mtd_info *mtd); - int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, - int status, int page); int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, uint32_t offset, int data_len, const uint8_t *buf, - int oob_required, int page, int cached, int raw); + int oob_required, int page, int raw); int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip, int feature_addr, uint8_t *subfeature_para); int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip, int feature_addr, uint8_t *subfeature_para); int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode); + int (*setup_data_interface)(struct mtd_info *mtd, int chipnr, + const struct nand_data_interface *conf); + int chip_delay; unsigned int options; @@ -741,11 +923,11 @@ struct nand_chip { int onfi_version; int jedec_version; -#ifdef CONFIG_SYS_NAND_ONFI_DETECTION struct nand_onfi_params onfi_params; -#endif struct nand_jedec_params jedec_params; + struct nand_data_interface *data_interface; + int read_retries; flstate_t state; @@ -756,6 +938,7 @@ struct nand_chip { struct nand_ecc_ctrl ecc; struct nand_buffers *buffers; + unsigned long buf_align; struct nand_hw_control hwcontrol; uint8_t *bbt; @@ -900,13 +1083,13 @@ struct nand_manufacturers { extern struct nand_flash_dev nand_flash_ids[]; extern struct nand_manufacturers nand_manuf_ids[]; -extern int nand_default_bbt(struct mtd_info *mtd); -extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); -extern int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs); -extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); -extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, +int nand_default_bbt(struct mtd_info *mtd); +int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); +int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs); +int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); +int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, int allowbbt); -extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, +int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, uint8_t *buf); /* @@ -1001,8 +1184,28 @@ static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) return ONFI_TIMING_MODE_UNKNOWN; return le16_to_cpu(chip->onfi_params.src_sync_timing_mode); } +#else +static inline int onfi_feature(struct nand_chip *chip) +{ + return 0; +} + +static inline int onfi_get_async_timing_mode(struct nand_chip *chip) +{ + return ONFI_TIMING_MODE_UNKNOWN; +} + +static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) +{ + return ONFI_TIMING_MODE_UNKNOWN; +} #endif +int onfi_init_data_interface(struct nand_chip *chip, + struct nand_data_interface *iface, + enum nand_data_interface_type type, + int timing_mode); + /* * Check if it is a SLC nand. * The !nand_is_slc() can be used to check the MLC/TLC nand chips. @@ -1045,60 +1248,25 @@ void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len); void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len); uint8_t nand_read_byte(struct mtd_info *mtd); -/* - * struct nand_sdr_timings - SDR NAND chip timings - * - * This struct defines the timing requirements of a SDR NAND chip. - * These informations can be found in every NAND datasheets and the timings - * meaning are described in the ONFI specifications: - * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing - * Parameters) - * - * All these timings are expressed in picoseconds. - */ - -struct nand_sdr_timings { - u32 tALH_min; - u32 tADL_min; - u32 tALS_min; - u32 tAR_min; - u32 tCEA_max; - u32 tCEH_min; - u32 tCH_min; - u32 tCHZ_max; - u32 tCLH_min; - u32 tCLR_min; - u32 tCLS_min; - u32 tCOH_min; - u32 tCS_min; - u32 tDH_min; - u32 tDS_min; - u32 tFEAT_max; - u32 tIR_min; - u32 tITC_max; - u32 tRC_min; - u32 tREA_max; - u32 tREH_min; - u32 tRHOH_min; - u32 tRHW_min; - u32 tRHZ_max; - u32 tRLOH_min; - u32 tRP_min; - u32 tRR_min; - u64 tRST_max; - u32 tWB_max; - u32 tWC_min; - u32 tWH_min; - u32 tWHR_min; - u32 tWP_min; - u32 tWW_min; -}; - /* get timing characteristics from ONFI timing mode. */ const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode); +/* get data interface from ONFI timing mode 0, used after reset. */ +const struct nand_data_interface *nand_get_default_data_interface(void); int nand_check_erased_ecc_chunk(void *data, int datalen, void *ecc, int ecclen, void *extraoob, int extraooblen, int threshold); -#endif /* __LINUX_MTD_NAND_H */ + +int nand_check_ecc_caps(struct nand_chip *chip, + const struct nand_ecc_caps *caps, int oobavail); + +int nand_match_ecc_req(struct nand_chip *chip, + const struct nand_ecc_caps *caps, int oobavail); + +int nand_maximize_ecc(struct nand_chip *chip, + const struct nand_ecc_caps *caps, int oobavail); + +/* Reset and initialize a NAND device */ +int nand_reset(struct nand_chip *chip, int chipnr); +#endif /* __LINUX_MTD_RAWNAND_H */ diff --git a/include/log.h b/include/log.h new file mode 100644 index 0000000000..8083b64831 --- /dev/null +++ b/include/log.h @@ -0,0 +1,304 @@ +/* + * Logging support + * + * Copyright (c) 2017 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LOG_H +#define __LOG_H + +#include <dm/uclass-id.h> +#include <linux/list.h> + +/** Log levels supported, ranging from most to least important */ +enum log_level_t { + LOGL_EMERG = 0, /*U-Boot is unstable */ + LOGL_ALERT, /* Action must be taken immediately */ + LOGL_CRIT, /* Critical conditions */ + LOGL_ERR, /* Error that prevents something from working */ + LOGL_WARNING, /* Warning may prevent optimial operation */ + LOGL_NOTICE, /* Normal but significant condition, printf() */ + LOGL_INFO, /* General information message */ + LOGL_DEBUG, /* Basic debug-level message */ + LOGL_DEBUG_CONTENT, /* Debug message showing full message content */ + LOGL_DEBUG_IO, /* Debug message showing hardware I/O access */ + + LOGL_COUNT, + LOGL_FIRST = LOGL_EMERG, + LOGL_MAX = LOGL_DEBUG, +}; + +/** + * Log categories supported. Most of these correspond to uclasses (i.e. + * enum uclass_id) but there are also some more generic categories + */ +enum log_category_t { + LOGC_FIRST = 0, /* First part mirrors UCLASS_... */ + + LOGC_NONE = UCLASS_COUNT, + LOGC_ARCH, + LOGC_BOARD, + LOGC_CORE, + LOGC_DT, + + LOGC_COUNT, + LOGC_END, +}; + +/* Helper to cast a uclass ID to a log category */ +static inline int log_uc_cat(enum uclass_id id) +{ + return (enum log_category_t)id; +} + +/** + * _log() - Internal function to emit a new log record + * + * @cat: Category of log record (indicating which subsystem generated it) + * @level: Level of log record (indicating its severity) + * @file: File name of file where log record was generated + * @line: Line number in file where log record was generated + * @func: Function where log record was generated + * @fmt: printf() format string for log record + * @...: Optional parameters, according to the format string @fmt + * @return 0 if log record was emitted, -ve on error + */ +int _log(enum log_category_t cat, enum log_level_t level, const char *file, + int line, const char *func, const char *fmt, ...); + +/* Define this at the top of a file to add a prefix to debug messages */ +#ifndef pr_fmt +#define pr_fmt(fmt) fmt +#endif + +/* Use a default category if this file does not supply one */ +#ifndef LOG_CATEGORY +#define LOG_CATEGORY LOGC_NONE +#endif + +/* + * This header may be including when CONFIG_LOG is disabled, in which case + * CONFIG_LOG_MAX_LEVEL is not defined. Add a check for this. + */ +#if CONFIG_IS_ENABLED(LOG) +#define _LOG_MAX_LEVEL CONFIG_VAL(LOG_MAX_LEVEL) +#else +#define _LOG_MAX_LEVEL LOGL_INFO +#endif + +/* Emit a log record if the level is less that the maximum */ +#define log(_cat, _level, _fmt, _args...) ({ \ + int _l = _level; \ + if (_l <= _LOG_MAX_LEVEL) \ + _log((enum log_category_t)(_cat), _l, __FILE__, __LINE__, \ + __func__, \ + pr_fmt(_fmt), ##_args); \ + }) + +#ifdef DEBUG +#define _DEBUG 1 +#else +#define _DEBUG 0 +#endif + +#ifdef CONFIG_SPL_BUILD +#define _SPL_BUILD 1 +#else +#define _SPL_BUILD 0 +#endif + +#if !_DEBUG && CONFIG_IS_ENABLED(LOG) + +#define debug_cond(cond, fmt, args...) \ + do { \ + if (1) \ + log(LOG_CATEGORY, LOGL_DEBUG, fmt, ##args); \ + } while (0) + +#else /* _DEBUG */ + +/* + * Output a debug text when condition "cond" is met. The "cond" should be + * computed by a preprocessor in the best case, allowing for the best + * optimization. + */ +#define debug_cond(cond, fmt, args...) \ + do { \ + if (cond) \ + printf(pr_fmt(fmt), ##args); \ + } while (0) + +#endif /* _DEBUG */ + +/* Show a message if DEBUG is defined in a file */ +#define debug(fmt, args...) \ + debug_cond(_DEBUG, fmt, ##args) + +/* Show a message if not in SPL */ +#define warn_non_spl(fmt, args...) \ + debug_cond(!_SPL_BUILD, fmt, ##args) + +/* + * An assertion is run-time check done in debug mode only. If DEBUG is not + * defined then it is skipped. If DEBUG is defined and the assertion fails, + * then it calls panic*( which may or may not reset/halt U-Boot (see + * CONFIG_PANIC_HANG), It is hoped that all failing assertions are found + * before release, and after release it is hoped that they don't matter. But + * in any case these failing assertions cannot be fixed with a reset (which + * may just do the same assertion again). + */ +void __assert_fail(const char *assertion, const char *file, unsigned int line, + const char *function); +#define assert(x) \ + ({ if (!(x) && _DEBUG) \ + __assert_fail(#x, __FILE__, __LINE__, __func__); }) + +/** + * struct log_rec - a single log record + * + * Holds information about a single record in the log + * + * Members marked as 'not allocated' are stored as pointers and the caller is + * responsible for making sure that the data pointed to is not overwritten. + * Memebers marked as 'allocated' are allocated (e.g. via strdup()) by the log + * system. + * + * @cat: Category, representing a uclass or part of U-Boot + * @level: Severity level, less severe is higher + * @file: Name of file where the log record was generated (not allocated) + * @line: Line number where the log record was generated + * @func: Function where the log record was generated (not allocated) + * @msg: Log message (allocated) + */ +struct log_rec { + enum log_category_t cat; + enum log_level_t level; + const char *file; + int line; + const char *func; + const char *msg; +}; + +struct log_device; + +/** + * struct log_driver - a driver which accepts and processes log records + * + * @name: Name of driver + */ +struct log_driver { + const char *name; + /** + * emit() - emit a log record + * + * Called by the log system to pass a log record to a particular driver + * for processing. The filter is checked before calling this function. + */ + int (*emit)(struct log_device *ldev, struct log_rec *rec); +}; + +/** + * struct log_device - an instance of a log driver + * + * Since drivers are set up at build-time we need to have a separate device for + * the run-time aspects of drivers (currently just a list of filters to apply + * to records send to this device). + * + * @next_filter_num: Seqence number of next filter filter added (0=no filters + * yet). This increments with each new filter on the device, but never + * decrements + * @drv: Pointer to driver for this device + * @filter_head: List of filters for this device + * @sibling_node: Next device in the list of all devices + */ +struct log_device { + int next_filter_num; + struct log_driver *drv; + struct list_head filter_head; + struct list_head sibling_node; +}; + +enum { + LOGF_MAX_CATEGORIES = 5, /* maximum categories per filter */ +}; + +enum log_filter_flags { + LOGFF_HAS_CAT = 1 << 0, /* Filter has a category list */ +}; + +/** + * struct log_filter - criterial to filter out log messages + * + * @filter_num: Sequence number of this filter. This is returned when adding a + * new filter, and must be provided when removing a previously added + * filter. + * @flags: Flags for this filter (LOGFF_...) + * @cat_list: List of categories to allow (terminated by LOGC_none). If empty + * then all categories are permitted. Up to LOGF_MAX_CATEGORIES entries + * can be provided + * @max_level: Maximum log level to allow + * @file_list: List of files to allow, separated by comma. If NULL then all + * files are permitted + * @sibling_node: Next filter in the list of filters for this log device + */ +struct log_filter { + int filter_num; + int flags; + enum log_category_t cat_list[LOGF_MAX_CATEGORIES]; + enum log_level_t max_level; + const char *file_list; + struct list_head sibling_node; +}; + +#define LOG_DRIVER(_name) \ + ll_entry_declare(struct log_driver, _name, log_driver) + +/* Handle the 'log test' command */ +int do_log_test(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]); + +/** + * log_add_filter() - Add a new filter to a log device + * + * @drv_name: Driver name to add the filter to (since each driver only has a + * single device) + * @cat_list: List of categories to allow (terminated by LOGC_none). If empty + * then all categories are permitted. Up to LOGF_MAX_CATEGORIES entries + * can be provided + * @max_level: Maximum log level to allow + * @file_list: List of files to allow, separated by comma. If NULL then all + * files are permitted + * @return the sequence number of the new filter (>=0) if the filter was added, + * or a -ve value on error + */ +int log_add_filter(const char *drv_name, enum log_category_t cat_list[], + enum log_level_t max_level, const char *file_list); + +/** + * log_remove_filter() - Remove a filter from a log device + * + * @drv_name: Driver name to remove the filter from (since each driver only has + * a single device) + * @filter_num: Filter number to remove (as returned by log_add_filter()) + * @return 0 if the filter was removed, -ENOENT if either the driver or the + * filter number was not found + */ +int log_remove_filter(const char *drv_name, int filter_num); + +#if CONFIG_IS_ENABLED(LOG) +/** + * log_init() - Set up the log system ready for use + * + * @return 0 if OK, -ENOMEM if out of memory + */ +int log_init(void); +#else +static inline int log_init(void) +{ + return 0; +} +#endif + +#endif diff --git a/include/logbuff.h b/include/logbuff.h deleted file mode 100644 index 625feb9f95..0000000000 --- a/include/logbuff.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * (C) Copyright 2002-2007 - * Detlev Zundel, dzu@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _LOGBUFF_H -#define _LOGBUFF_H - -#ifdef CONFIG_LOGBUFFER - -#define LOGBUFF_MAGIC 0xc0de4ced /* Forced by code, eh! */ -#define LOGBUFF_LEN (16384) /* Must be 16k right now */ -#define LOGBUFF_MASK (LOGBUFF_LEN-1) -#define LOGBUFF_OVERHEAD (4096) /* Logbuffer overhead for extra info */ -#define LOGBUFF_RESERVE (LOGBUFF_LEN+LOGBUFF_OVERHEAD) - -/* The mapping used here has to be the same as in setup_ext_logbuff () - in linux/kernel/printk */ - -typedef struct { - union { - struct { - unsigned long tag; - unsigned long start; - unsigned long con; - unsigned long end; - unsigned long chars; - } v2; - struct { - unsigned long dummy; - unsigned long tag; - unsigned long start; - unsigned long size; - unsigned long chars; - } v1; - }; - unsigned char buf[0]; -} logbuff_t; - -int drv_logbuff_init (void); -void logbuff_init_ptrs (void); -void logbuff_log(char *msg); -void logbuff_reset (void); -unsigned long logbuffer_base (void); - -#endif /* CONFIG_LOGBUFFER */ - -#endif /* _LOGBUFF_H */ diff --git a/include/msc01.h b/include/msc01.h index 37cf963f13..7ee243bec3 100644 --- a/include/msc01.h +++ b/include/msc01.h @@ -1,6 +1,6 @@ /* * Copyright (C) 2013 Imagination Technologies - * Author: Paul Burton <paul.burton@imgtec.com> + * Author: Paul Burton <paul.burton@mips.com> * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/include/nand.h b/include/nand.h index c1c1d8cce6..cead563553 100644 --- a/include/nand.h +++ b/include/nand.h @@ -32,7 +32,7 @@ unsigned long nand_size(void); #include <linux/compat.h> #include <linux/mtd/mtd.h> -#include <linux/mtd/nand.h> +#include <linux/mtd/rawnand.h> int nand_mtd_to_devnum(struct mtd_info *mtd); diff --git a/include/os.h b/include/os.h index 2bf4bdb1b8..049b248c5b 100644 --- a/include/os.h +++ b/include/os.h @@ -241,6 +241,26 @@ const char *os_dirent_get_typename(enum os_dirent_t type); int os_get_filesize(const char *fname, loff_t *size); /** + * Write a character to the controlling OS terminal + * + * This bypasses the U-Boot console support and writes directly to the OS + * stdout file descriptor. + * + * @param ch Character to write + */ +void os_putc(int ch); + +/** + * Write a string to the controlling OS terminal + * + * This bypasses the U-Boot console support and writes directly to the OS + * stdout file descriptor. + * + * @param str String to write (note that \n is not appended) + */ +void os_puts(const char *str); + +/** * Write the sandbox RAM buffer to a existing file * * @param fname Filename to write memory to (simple binary format) diff --git a/include/part_efi.h b/include/part_efi.h index 31e6bc6e14..4c8f6cc473 100644 --- a/include/part_efi.h +++ b/include/part_efi.h @@ -27,7 +27,7 @@ #define GPT_HEADER_SIGNATURE 0x5452415020494645ULL #define GPT_HEADER_REVISION_V1 0x00010000 #define GPT_PRIMARY_PARTITION_TABLE_LBA 1ULL -#define GPT_ENTRY_NUMBERS 128 +#define GPT_ENTRY_NUMBERS CONFIG_EFI_PARTITION_ENTRIES_NUMBERS #define GPT_ENTRY_SIZE 128 #define PARTITION_SYSTEM_GUID \ diff --git a/include/pci_msc01.h b/include/pci_msc01.h index 54945a7a8f..066c6622da 100644 --- a/include/pci_msc01.h +++ b/include/pci_msc01.h @@ -1,6 +1,6 @@ /* * Copyright (C) 2013 Imagination Technologies - * Author: Paul Burton <paul.burton@imgtec.com> + * Author: Paul Burton <paul.burton@mips.com> * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/include/post.h b/include/post.h index d5278111e8..b41a6c8127 100644 --- a/include/post.h +++ b/include/post.h @@ -15,7 +15,7 @@ #include <common.h> #include <asm/io.h> -#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) +#if defined(CONFIG_POST) #ifndef CONFIG_POST_EXTERNAL_WORD_FUNCS #ifdef CONFIG_SYS_POST_WORD_ADDR @@ -58,7 +58,7 @@ extern ulong post_word_load(void); extern void post_word_store(ulong value); #endif /* CONFIG_POST_EXTERNAL_WORD_FUNCS */ -#endif /* defined (CONFIG_POST) || defined(CONFIG_LOGBUFFER) */ +#endif /* defined (CONFIG_POST) */ #endif /* __ASSEMBLY__ */ #ifdef CONFIG_POST diff --git a/include/power/sandbox_pmic.h b/include/power/sandbox_pmic.h index 7fdbfb9fc6..c5e6fda2ea 100644 --- a/include/power/sandbox_pmic.h +++ b/include/power/sandbox_pmic.h @@ -13,7 +13,7 @@ #define SANDBOX_BUCK_DRIVER "sandbox_buck" #define SANDBOX_OF_BUCK_PREFIX "buck" -#define SANDBOX_BUCK_COUNT 2 +#define SANDBOX_BUCK_COUNT 3 #define SANDBOX_LDO_COUNT 2 /* * Sandbox PMIC registers: @@ -109,6 +109,9 @@ enum { #define SANDBOX_BUCK1_PLATNAME "SUPPLY_1.2V" #define SANDBOX_BUCK2_DEVNAME "buck2" #define SANDBOX_BUCK2_PLATNAME "SUPPLY_3.3V" +/* BUCK3: for testing fallback regulator prefix matching during bind */ +#define SANDBOX_BUCK3_DEVNAME "no_match_by_nodename" +#define SANDBOX_BUCK3_PLATNAME "buck_SUPPLY_1.5V" /* LDO names */ #define SANDBOX_LDO1_DEVNAME "ldo1" #define SANDBOX_LDO1_PLATNAME "VDD_EMMC_1.8V" diff --git a/include/power/tps65910_pmic.h b/include/power/tps65910_pmic.h new file mode 100644 index 0000000000..e8d9ffaa9f --- /dev/null +++ b/include/power/tps65910_pmic.h @@ -0,0 +1,130 @@ +/* + * Copyright (C) EETS GmbH, 2017, Felix Brack <f.brack@eets.ch> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __TPS65910_PMIC_H_ +#define __TPS65910_PMIC_H_ + +#define TPS65910_I2C_SEL_MASK (0x1 << 4) +#define TPS65910_VDD_SR_MASK (0x1 << 7) +#define TPS65910_GAIN_SEL_MASK (0x3 << 6) +#define TPS65910_VDD_SEL_MASK 0x7f +#define TPS65910_VDD_SEL_MIN 3 +#define TPS65910_VDD_SEL_MAX 75 +#define TPS65910_SEL_MASK (0x3 << 2) +#define TPS65910_SUPPLY_STATE_MASK 0x3 +#define TPS65910_SUPPLY_STATE_OFF 0x0 +#define TPS65910_SUPPLY_STATE_ON 0x1 + +/* i2c registers */ +enum { + TPS65910_REG_RTC_SEC = 0x00, + TPS65910_REG_RTC_MIN, + TPS65910_REG_RTC_HOUR, + TPS65910_REG_RTC_DAY, + TPS65910_REG_RTC_MONTH, + TPS65910_REG_RTC_YEAR, + TPS65910_REG_RTC_WEEK, + TPS65910_REG_RTC_ALARM_SEC = 0x08, + TPS65910_REG_RTC_ALARM_MIN, + TPS65910_REG_RTC_ALARM_HOUR, + TPS65910_REG_RTC_ALARM_DAY, + TPS65910_REG_RTC_ALARM_MONTH, + TPS65910_REG_RTC_ALARM_YEAR, + TPS65910_REG_RTC_CTRL = 0x10, + TPS65910_REG_RTC_STAT, + TPS65910_REG_RTC_INT, + TPS65910_REG_RTC_COMP_LSB, + TPS65910_REG_RTC_COMP_MSB, + TPS65910_REG_RTC_RESISTOR_PRG, + TPS65910_REG_RTC_RESET_STAT, + TPS65910_REG_BACKUP1, + TPS65910_REG_BACKUP2, + TPS65910_REG_BACKUP3, + TPS65910_REG_BACKUP4, + TPS65910_REG_BACKUP5, + TPS65910_REG_PUADEN, + TPS65910_REG_REF, + TPS65910_REG_VRTC, + TPS65910_REG_VIO = 0x20, + TPS65910_REG_VDD1, + TPS65910_REG_VDD1_VAL, + TPS65910_REG_VDD1_VAL_SR, + TPS65910_REG_VDD2, + TPS65910_REG_VDD2_VAL, + TPS65910_REG_VDD2_VAL_SR, + TPS65910_REG_VDD3, + TPS65910_REG_VDIG1 = 0x30, + TPS65910_REG_VDIG2, + TPS65910_REG_VAUX1, + TPS65910_REG_VAUX2, + TPS65910_REG_VAUX33, + TPS65910_REG_VMMC, + TPS65910_REG_VPLL, + TPS65910_REG_VDAC, + TPS65910_REG_THERM, + TPS65910_REG_BATTERY_BACKUP_CHARGE, + TPS65910_REG_DCDC_CTRL = 0x3e, + TPS65910_REG_DEVICE_CTRL, + TPS65910_REG_DEVICE_CTRL2, + TPS65910_REG_SLEEP_KEEP_LDO_ON, + TPS65910_REG_SLEEP_KEEP_RES_ON, + TPS65910_REG_SLEEP_SET_LDO_OFF, + TPS65910_REG_SLEEP_SET_RES_OFF, + TPS65910_REG_EN1_LDO_ASS, + TPS65910_REG_EM1_SMPS_ASS, + TPS65910_REG_EN2_LDO_ASS, + TPS65910_REG_EM2_SMPS_ASS, + TPS65910_REG_INT_STAT = 0x50, + TPS65910_REG_INT_MASK, + TPS65910_REG_INT_STAT2, + TPS65910_REG_INT_MASK2, + TPS65910_REG_GPIO = 0x60, + TPS65910_REG_JTAGREVNUM = 0x80, + TPS65910_NUM_REGS +}; + +/* chip supplies */ +enum { + TPS65910_SUPPLY_VCCIO = 0x00, + TPS65910_SUPPLY_VCC1, + TPS65910_SUPPLY_VCC2, + TPS65910_SUPPLY_VCC3, + TPS65910_SUPPLY_VCC4, + TPS65910_SUPPLY_VCC5, + TPS65910_SUPPLY_VCC6, + TPS65910_SUPPLY_VCC7, + TPS65910_NUM_SUPPLIES +}; + +/* regulator unit numbers */ +enum { + TPS65910_UNIT_VRTC = 0x00, + TPS65910_UNIT_VIO, + TPS65910_UNIT_VDD1, + TPS65910_UNIT_VDD2, + TPS65910_UNIT_VDD3, + TPS65910_UNIT_VDIG1, + TPS65910_UNIT_VDIG2, + TPS65910_UNIT_VPLL, + TPS65910_UNIT_VDAC, + TPS65910_UNIT_VAUX1, + TPS65910_UNIT_VAUX2, + TPS65910_UNIT_VAUX33, + TPS65910_UNIT_VMMC, +}; + +/* platform data */ +struct tps65910_regulator_pdata { + u32 supply; /* regulator supply voltage in uV */ + uint unit; /* unit-address according to DT */ +}; + +/* driver names */ +#define TPS65910_BUCK_DRIVER "tps65910_buck" +#define TPS65910_BOOST_DRIVER "tps65910_boost" +#define TPS65910_LDO_DRIVER "tps65910_ldo" + +#endif /* __TPS65910_PMIC_H_ */ diff --git a/include/samsung/exynos5-dt-types.h b/include/samsung/exynos5-dt-types.h index 479e2e793d..8e11af30d1 100644 --- a/include/samsung/exynos5-dt-types.h +++ b/include/samsung/exynos5-dt-types.h @@ -8,6 +8,7 @@ enum { EXYNOS5_BOARD_ODROID_XU3_REV01, EXYNOS5_BOARD_ODROID_XU3_REV02, EXYNOS5_BOARD_ODROID_XU4_REV01, + EXYNOS5_BOARD_ODROID_HC1_REV01, EXYNOS5_BOARD_ODROID_UNKNOWN, EXYNOS5_BOARD_COUNT, @@ -23,5 +24,6 @@ struct odroid_rev_info { bool board_is_generic(void); bool board_is_odroidxu3(void); bool board_is_odroidxu4(void); +bool board_is_odroidhc1(void); #endif diff --git a/include/spl.h b/include/spl.h index b14a29c57c..c14448b8fc 100644 --- a/include/spl.h +++ b/include/spl.h @@ -7,6 +7,8 @@ #ifndef _SPL_H_ #define _SPL_H_ +#include <binman_sym.h> + /* Platform-specific defines */ #include <linux/compiler.h> #include <asm/spl.h> @@ -23,8 +25,11 @@ struct spl_image_info { const char *name; u8 os; - ulong load_addr; - ulong entry_point; + uintptr_t load_addr; + uintptr_t entry_point; +#if CONFIG_IS_ENABLED(LOAD_FIT) + void *fdt_addr; +#endif u32 size; u32 flags; void *arg; @@ -48,6 +53,15 @@ struct spl_load_info { void *buf); }; +/* + * We need to know the position of U-Boot in memory so we can jump to it. We + * allow any U-Boot binary to be used (u-boot.bin, u-boot-nodtb.bin, + * u-boot.img), hence the '_any'. These is no checking here that the correct + * image is found. For * example if u-boot.img is used we don't check that + * spl_parse_image_header() can parse a valid header. + */ +binman_sym_extern(ulong, u_boot_any, pos); + /** * spl_load_simple_fit() - Loads a fit image from a device. * @spl_image: Image description to set up @@ -268,7 +282,10 @@ int spl_dfu_cmd(int usbctrl, char *dfu_alt_info, char *interface, char *devstr); int spl_mmc_load_image(struct spl_image_info *spl_image, struct spl_boot_device *bootdev); -void bl31_entry(void); +/** + * spl_invoke_atf - boot using an ARM trusted firmware image + */ +void spl_invoke_atf(struct spl_image_info *spl_image); /** * board_return_to_bootrom - allow for boards to continue with the boot ROM diff --git a/include/stm32_rcc.h b/include/stm32_rcc.h new file mode 100644 index 0000000000..063177bc98 --- /dev/null +++ b/include/stm32_rcc.h @@ -0,0 +1,91 @@ +/* + * Copyright (C) STMicroelectronics SA 2017 + * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __STM32_RCC_H_ +#define __STM32_RCC_H_ + +#define AHB_PSC_1 0 +#define AHB_PSC_2 0x8 +#define AHB_PSC_4 0x9 +#define AHB_PSC_8 0xA +#define AHB_PSC_16 0xB +#define AHB_PSC_64 0xC +#define AHB_PSC_128 0xD +#define AHB_PSC_256 0xE +#define AHB_PSC_512 0xF + +#define APB_PSC_1 0 +#define APB_PSC_2 0x4 +#define APB_PSC_4 0x5 +#define APB_PSC_8 0x6 +#define APB_PSC_16 0x7 + +struct pll_psc { + u8 pll_m; + u16 pll_n; + u8 pll_p; + u8 pll_q; + u8 ahb_psc; + u8 apb1_psc; + u8 apb2_psc; +}; + +struct stm32_clk_info { + struct pll_psc sys_pll_psc; + bool has_overdrive; + bool v2; +}; + +enum soc_family { + STM32F4, + STM32F7, +}; + +struct stm32_rcc_clk { + char *drv_name; + enum soc_family soc; +}; + +struct stm32_rcc_regs { + u32 cr; /* RCC clock control */ + u32 pllcfgr; /* RCC PLL configuration */ + u32 cfgr; /* RCC clock configuration */ + u32 cir; /* RCC clock interrupt */ + u32 ahb1rstr; /* RCC AHB1 peripheral reset */ + u32 ahb2rstr; /* RCC AHB2 peripheral reset */ + u32 ahb3rstr; /* RCC AHB3 peripheral reset */ + u32 rsv0; + u32 apb1rstr; /* RCC APB1 peripheral reset */ + u32 apb2rstr; /* RCC APB2 peripheral reset */ + u32 rsv1[2]; + u32 ahb1enr; /* RCC AHB1 peripheral clock enable */ + u32 ahb2enr; /* RCC AHB2 peripheral clock enable */ + u32 ahb3enr; /* RCC AHB3 peripheral clock enable */ + u32 rsv2; + u32 apb1enr; /* RCC APB1 peripheral clock enable */ + u32 apb2enr; /* RCC APB2 peripheral clock enable */ + u32 rsv3[2]; + u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */ + u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */ + u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */ + u32 rsv4; + u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */ + u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */ + u32 rsv5[2]; + u32 bdcr; /* RCC Backup domain control */ + u32 csr; /* RCC clock control & status */ + u32 rsv6[2]; + u32 sscgr; /* RCC spread spectrum clock generation */ + u32 plli2scfgr; /* RCC PLLI2S configuration */ + /* below registers are only available on STM32F46x and STM32F7 SoCs*/ + u32 pllsaicfgr; /* PLLSAI configuration */ + u32 dckcfgr; /* dedicated clocks configuration register */ + /* Below registers are only available on STM32F7 SoCs */ + u32 dckcfgr2; /* dedicated clocks configuration register */ +}; + +#endif /* __STM32_RCC_H_ */ diff --git a/include/test/compression.h b/include/test/compression.h new file mode 100644 index 0000000000..646f117ed8 --- /dev/null +++ b/include/test/compression.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2017 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __TEST_COMPRESSION_H__ +#define __TEST_COMPRESSION_H__ + +#include <test/test.h> + +/* Declare a new compression test */ +#define COMPRESSION_TEST(_name, _flags) \ + UNIT_TEST(_name, _flags, compression_test) + +#endif /* __TEST_ENV_H__ */ diff --git a/include/test/suites.h b/include/test/suites.h index 0e94feb07a..5f2e519084 100644 --- a/include/test/suites.h +++ b/include/test/suites.h @@ -8,9 +8,26 @@ #ifndef __TEST_SUITES_H__ #define __TEST_SUITES_H__ +struct unit_test; + +/** + * cmd_ut_category() - Run a category of unit tests + * + * @name: Category name + * @tests: List of tests to run + * @n_ents: Number of tests in @tests + * @argc: Argument count provided. Must be <= 1. If this is 1 then all + * tests are run, otherwise only the one named @argv[1] is run. + * @argv: Arguments: argv[1] is the test to run (if @argc >= 2) + * @return 0 if OK, CMD_RET_FAILURE on failure + */ +int cmd_ut_category(const char *name, struct unit_test *tests, int n_ents, + int argc, char * const argv[]); + int do_ut_dm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); int do_ut_env(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); int do_ut_overlay(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); int do_ut_time(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); +int do_ut_compression(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]); #endif /* __TEST_SUITES_H__ */ diff --git a/include/usb/lin_gadget_compat.h b/include/usb/lin_gadget_compat.h index 4a01585f80..d0d71f7c32 100644 --- a/include/usb/lin_gadget_compat.h +++ b/include/usb/lin_gadget_compat.h @@ -10,12 +10,10 @@ #ifndef __LIN_COMPAT_H__ #define __LIN_COMPAT_H__ +#include <linux/bitops.h> #include <linux/compat.h> /* common */ -#define BITS_PER_BYTE 8 -#define BITS_TO_LONGS(nr) \ - DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long)) #define DECLARE_BITMAP(name, bits) \ unsigned long name[BITS_TO_LONGS(bits)] |