diff options
Diffstat (limited to 'include')
34 files changed, 900 insertions, 295 deletions
diff --git a/include/common.h b/include/common.h index eddec22752..6a79ec2aad 100644 --- a/include/common.h +++ b/include/common.h @@ -256,7 +256,7 @@ int env_init (void); void env_relocate (void); int envmatch (uchar *, int); char *getenv (char *); -int getenv_r (char *name, char *buf, unsigned len); +int getenv_f (char *name, char *buf, unsigned len); int saveenv (void); #ifdef CONFIG_PPC /* ARM version to be fixed! */ int inline setenv (char *, char *); diff --git a/include/configs/KUP4K.h b/include/configs/KUP4K.h index a829984649..14d412d183 100644 --- a/include/configs/KUP4K.h +++ b/include/configs/KUP4K.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2005 + * (C) Copyright 2000-2010 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de * @@ -42,46 +42,46 @@ #undef CONFIG_8xx_CONS_SMC2 #undef CONFIG_8xx_CONS_NONE #define CONFIG_BAUDRATE 115200 /* console baudrate */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else #define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ -#endif #define CONFIG_BOARD_TYPES 1 /* support board types */ - #undef CONFIG_BOOTARGS - #define CONFIG_EXTRA_ENV_SETTINGS \ -"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;" \ - "run addhw; diskboot 200000 0:1; bootm 200000\0" \ -"slot_b_boot=setenv bootargs root=/dev/hda2 ip=off;" \ - "run addhw; diskboot 200000 2:1; bootm 200000\0" \ -"nfs_boot=dhcp; run nfsargs addip addhw; bootm 200000\0" \ +"slot_a_boot=setenv bootargs root=/dev/sda2 ip=off;" \ + "run addhw; mw.b 400000 00 80; diskboot 400000 0:1; bootm 400000\0" \ +"slot_b_boot=setenv bootargs root=/dev/sda2 ip=off;" \ + "run addhw; mw.b 400000 00 80; diskboot 400000 2:1; bootm 400000\0" \ +"nfs_boot=mw.b 400000 00 80; dhcp; run nfsargs addip addhw; bootm 400000\0" \ +"fat_boot=mw.b 400000 00 80; fatload ide 2:1 400000 st.bin; run addhw; \ + bootm 400000 \0" \ "panic_boot=echo No Bootdevice !!! reset\0" \ -"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \ +"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ -"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}" \ +"addip=setenv bootargs ${bootargs} ip=${ipaddr}::${gatewayip}" \ ":${netmask}:${hostname}:${netdev}:off\0" \ -"addhw=setenv bootargs ${bootargs} hw=${hw} key1=${key1} panic=1\0" \ +"addhw=setenv bootargs ${bootargs} ${mtdparts} console=${console} ${debug} \ + hw=${hw} key1=${key1} panic=1 mem=${mem}\0" \ +"console=ttyCPM0,115200\0" \ "netdev=eth0\0" \ -"contrast=55\0" \ +"contrast=20\0" \ "silent=1\0" \ +"mtdparts=" MTDPARTS_DEFAULT "\0" \ "load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0" \ -"update=protect off 1:0-7;era 1:0-7;cp.b 100000 40000000 ${filesize};" \ +"update=protect off 1:0-9;era 1:0-9;cp.b 100000 40000000 ${filesize};" \ "cp.b 200000 40050000 14000\0" #define CONFIG_BOOTCOMMAND \ - "run slot_a_boot;run slot_b_boot;run nfs_boot;run panic_boot" + "run fat_boot;run slot_b_boot;run slot_a_boot;run nfs_boot;run panic_boot" +#define CONFIG_PREBOOT "setenv preboot; saveenv" #define CONFIG_MISC_INIT_R 1 #define CONFIG_MISC_INIT_F 1 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ +#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ #define CONFIG_WATCHDOG 1 /* watchdog enabled */ @@ -98,19 +98,17 @@ #define CONFIG_BOOTP_BOOTPATH #define CONFIG_BOOTP_BOOTFILESIZE - #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION - /* * enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SLAVE 0xFE +#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */ +#define CONFIG_SYS_I2C_SLAVE 0xFE #ifdef CONFIG_SOFT_I2C /* @@ -130,14 +128,12 @@ #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ #endif /* CONFIG_SOFT_I2C */ - /*----------------------------------------------------------------------- * I2C Configuration */ -#define CONFIG_SYS_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */ - +#define CONFIG_SYS_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */ /* List of I2C addresses to be verified by POST */ @@ -145,27 +141,13 @@ CONFIG_SYS_I2C_RTC_ADDR, \ } - #define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ #define CONFIG_SYS_DISCOVER_PHY #define CONFIG_MII -#if 0 -#define CONFIG_ETHADDR 00:0B:64:00:00:00 /* our OUI from IEEE */ -#endif -#define CONFIG_KUP4K_LOGO 0x40050000 /* Address of logo bitmap */ - /* Define to allow the user to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#if 1 -/* POST support */ - -#define CONFIG_POST (CONFIG_SYS_POST_CPU | \ - CONFIG_SYS_POST_RTC | \ - CONFIG_SYS_POST_I2C) -#endif - /* * Command line configuration. @@ -176,7 +158,9 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_I2C #define CONFIG_CMD_IDE +#define CONFIG_CMD_MII #define CONFIG_CMD_NFS +#define CONFIG_CMD_FAT #define CONFIG_CMD_SNTP #ifdef CONFIG_POST @@ -191,18 +175,21 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ #endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_MEMTEST_START 0x000400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x002C00000 /* 4 ... 44 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0x000400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x005C00000 /* 4 ... 92 MB in DRAM */ +#define CONFIG_SYS_ALT_MEMTEST 1 +#define CONFIG_SYS_MEMTEST_SCRATCH 0x90000200 /* using latch as scratch register */ -#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 115200 } @@ -259,19 +246,22 @@ #define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ #define CONFIG_ENV_SECT_SIZE 0x10000 -/* Address and size of Redundant Environment Sector */ -#if 0 -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#endif +/*----------------------------------------------------------------------- + * Dynamic MTD partition support + */ +#define MTDPARTS_DEFAULT "mtdparts=40000000.flash:256k(u-boot)," \ + "64k(env)," \ + "128k(splash)," \ + "512k(etc)," \ + "64k(hw-info)" + /*----------------------------------------------------------------------- * Hardware Information Block */ -#if 1 #define CONFIG_SYS_HWINFO_OFFSET 0x000F0000 /* offset of HW Info block */ #define CONFIG_SYS_HWINFO_SIZE 0x00000100 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x4B26500D /* 'K&P<CR>' */ -#endif +#define CONFIG_SYS_HWINFO_MAGIC 0x4B26500D /* 'K&P<CR>' */ + /*----------------------------------------------------------------------- * Cache Configuration */ @@ -286,12 +276,7 @@ *----------------------------------------------------------------------- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze */ -#if 0 && defined(CONFIG_WATCHDOG) /* KUP uses external TPS3705 WD */ -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif /*----------------------------------------------------------------------- * SIUMCR - SIU Module Configuration 11-6 @@ -391,7 +376,6 @@ /* Offset for alternate registers */ #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - /*----------------------------------------------------------------------- * *----------------------------------------------------------------------- @@ -416,18 +400,20 @@ /* * FLASH timing: */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_2_CLK | OR_EHTR | OR_BI) +#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_CSNT_SAM | \ + OR_SCY_5_CLK | OR_EHTR | OR_BI) -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) +#define CONFIG_SYS_OR0_REMAP \ + (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) +#define CONFIG_SYS_OR0_PRELIM \ + (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) +#define CONFIG_SYS_BR0_PRELIM \ + ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - /* * Memory Periodic Timer Prescaler * @@ -475,7 +461,39 @@ /* * MAMR settings for SDRAM */ -#define CONFIG_SYS_MAMR 0x80802114 + +/* 8 column SDRAM */ +#define CONFIG_SYS_MAMR_8COL 0x68802114 +/* 9 column SDRAM */ +#define CONFIG_SYS_MAMR_9COL 0x68904114 + +/* + * Chip Selects + */ +#define CONFIG_SYS_OR0 +#define CONFIG_SYS_BR0 + +#define CONFIG_SYS_OR1_8COL 0xFF000A00 +#define CONFIG_SYS_BR1_8COL 0x00000081 +#define CONFIG_SYS_OR2_8COL 0xFE000A00 +#define CONFIG_SYS_BR2_8COL 0x01000081 +#define CONFIG_SYS_OR3_8COL 0xFC000A00 +#define CONFIG_SYS_BR3_8COL 0x02000081 + +#define CONFIG_SYS_OR1_9COL 0xFE000A00 +#define CONFIG_SYS_BR1_9COL 0x00000081 +#define CONFIG_SYS_OR2_9COL 0xFE000A00 +#define CONFIG_SYS_BR2_9COL 0x02000081 +#define CONFIG_SYS_OR3_9COL 0xFE000A00 +#define CONFIG_SYS_BR3_9COL 0x04000081 + +#define CONFIG_SYS_OR4 0xFFFF8926 +#define CONFIG_SYS_BR4 0x90000401 + +#define CONFIG_SYS_OR5 0xFFC007F0 /* EPSON: 4 MB 17 WS or externel TA */ +#define CONFIG_SYS_BR5 0x80080801 /* Start at 0x80080000 */ + +#define LATCH_ADDR 0x90000200 /* * Internal Definitions @@ -487,11 +505,14 @@ #define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ -#if 0 -#define CONFIG_AUTOBOOT_PROMPT \ - "Boote in %d Sekunden - stop mit \"2\"\n", bootdelay -#endif -#define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */ -#define CONFIG_SILENT_CONSOLE 1 +#define CONFIG_AUTOBOOT_STOP_STR "." +#define CONFIG_SILENT_CONSOLE 1 +#define CONFIG_SYS_DEVICE_NULLDEV 1 /* enble null device */ +#define CONFIG_VERSION_VARIABLE 1 + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 #endif /* __CONFIG_H */ + diff --git a/include/configs/KUP4X.h b/include/configs/KUP4X.h index be6dfda6e7..ab535e15b5 100644 --- a/include/configs/KUP4X.h +++ b/include/configs/KUP4X.h @@ -35,23 +35,20 @@ * (easy to change) */ -#define CONFIG_MPC859T 1 /* This is a MPC859T CPU */ -#define CONFIG_KUP4X 1 /* ...on a KUP4X module */ +#define CONFIG_MPC859T 1 /* This is a MPC859T CPU */ +#define CONFIG_KUP4X 1 /* ...on a KUP4X module */ -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #undef CONFIG_8xx_CONS_SMC2 #undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ -#endif +#define CONFIG_BAUDRATE 115200 /* console baudrate */ -#define CONFIG_BOARD_TYPES 1 /* support board types */ +#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ -#define CONFIG_SYS_8XX_FACT 8 /* Multiply by 8 */ -#define CONFIG_SYS_8XX_XIN 16000000 /* 16 MHz in */ +#define CONFIG_BOARD_TYPES 1 /* support board types */ + +#define CONFIG_SYS_8XX_FACT 8 /* Multiply by 8 */ +#define CONFIG_SYS_8XX_XIN 16000000 /* 16 MHz in */ #define MPC8XX_HZ ((CONFIG_SYS_8XX_XIN) * (CONFIG_SYS_8XX_FACT)) @@ -67,9 +64,9 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;" \ "run addhw;diskboot 200000 0:1;bootm 200000\0" \ -"usb_boot=setenv bootargs root=/dev/sda2 ip=off;\ - run addhw; sleep 2; usb reset; usb scan; usbboot 200000 0:1;\ - usb stop; bootm 200000\0" \ +"usb_boot=setenv bootargs root=/dev/sda2 ip=off; \ + run addhw; sleep 2; usb reset; usb scan; usbboot 200000 0:1; \ + usb stop; bootm 200000\0" \ "nfs_boot=dhcp;run nfsargs addip addhw;bootm 200000\0" \ "panic_boot=echo No Bootdevice !!! reset\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \ @@ -84,14 +81,14 @@ "cp.b 200000 40040000 14000\0" #define CONFIG_BOOTCOMMAND \ - "run usb_boot;run_slot_a_boot;run nfs_boot;run panic_boot" + "run usb_boot;run slot_a_boot;run nfs_boot;run panic_boot" #define CONFIG_MISC_INIT_R 1 #define CONFIG_MISC_INIT_F 1 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ +#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ #define CONFIG_WATCHDOG 1 /* watchdog enabled */ @@ -144,8 +141,8 @@ * I2C Configuration */ -#define CONFIG_SYS_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */ +#define CONFIG_SYS_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */ /* List of I2C addresses to be verified by POST */ @@ -160,22 +157,16 @@ #define CONFIG_SYS_DISCOVER_PHY #define CONFIG_MII -#if 0 -#define CONFIG_ETHADDR 00:0B:64:80:00:00 /* our OUI from IEEE */ -#endif #undef CONFIG_KUP4K_LOGO /* Define to allow the user to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#if 1 /* POST support */ - #define CONFIG_POST (CONFIG_SYS_POST_CPU | \ CONFIG_SYS_POST_RTC | \ CONFIG_SYS_POST_I2C) -#endif /* @@ -426,9 +417,12 @@ #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ OR_SCY_2_CLK | OR_EHTR | OR_BI) -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) +#define CONFIG_SYS_OR0_REMAP \ + (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) +#define CONFIG_SYS_OR0_PRELIM \ + (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) +#define CONFIG_SYS_BR0_PRELIM \ + ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ @@ -444,6 +438,15 @@ /* + * Chip Selects + */ + +#define CONFIG_SYS_OR4 0xFFFF8926 +#define CONFIG_SYS_BR4 0x90000401 + +#define LATCH_ADDR 0x90000200 + +/* * Internal Definitions * * Boot Flags @@ -453,10 +456,7 @@ #define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ -#if 0 -#define CONFIG_AUTOBOOT_PROMPT \ - "Boote in %d Sekunden - stop mit \"2\"\n", bootdelay -#endif + #define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */ #define CONFIG_SILENT_CONSOLE 1 diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 890a6c9bc4..2a3c058619 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -687,6 +687,7 @@ */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 78bb74bdc1..577c276107 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -398,7 +398,8 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index ae4fba8014..8797b3099d 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -416,7 +416,8 @@ extern unsigned long get_clock_freq(void); * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 96fd0241ca..d1ac32f4ad 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -431,7 +431,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 23594a74cb..33f49f5f08 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -471,7 +471,8 @@ extern unsigned long get_clock_freq(void); * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 5011e5a8bf..0f71f11c65 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -414,7 +414,8 @@ extern unsigned long get_clock_freq(void); * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 98677e5f1b..31740fdb25 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -438,7 +438,8 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index bc6c5c7b46..ea7a134b8d 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -431,7 +431,8 @@ extern unsigned long get_clock_freq(void); * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 92c2b49c1f..f69b650185 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -560,8 +560,9 @@ extern unsigned long get_clock_freq(void); /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 51e5d06db9..081661e6b3 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -581,7 +581,8 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 0d1f7799cf..974cb6ba7d 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -122,6 +122,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW #endif +#define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */ + /* * DDR Setup */ diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index f9d12f55f9..dcaca2b617 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -366,6 +366,7 @@ */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #ifdef CONFIG_CMD_KGDB diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index fca3cddf11..7e901e17cc 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -518,6 +518,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index bf2acbf4c4..79ce2c0a8b 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -92,7 +92,11 @@ /* DDR Setup */ #define CONFIG_VERY_BIG_RAM +#ifdef CONFIG_MK_DDR2 +#define CONFIG_FSL_DDR2 +#else #define CONFIG_FSL_DDR3 1 +#endif #undef CONFIG_FSL_DDR_INTERACTIVE /* ECC will be enabled based on perf_mode environment variable */ @@ -109,6 +113,7 @@ #define CONFIG_CHIP_SELECTS_PER_CTRL 2 /* I2C addresses of SPD EEPROMs */ +#define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */ #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ @@ -228,6 +233,7 @@ #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ +#define CONFIG_HWCONFIG /* enable hwconfig */ #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ #ifdef CONFIG_FSL_NGPIXIS @@ -249,6 +255,18 @@ #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#else +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#endif #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ @@ -567,7 +585,8 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h new file mode 100644 index 0000000000..87703c98b3 --- /dev/null +++ b/include/configs/P4080DS.h @@ -0,0 +1,39 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * P4080 DS board configuration file + */ +#define CONFIG_P4080DS +#define CONFIG_PHYS_64BIT +#define CONFIG_PPC_P4080 +#define CONFIG_SYS_NUM_FMAN 2 +#define CONFIG_SYS_NUM_FM1_DTSEC 4 +#define CONFIG_SYS_NUM_FM2_DTSEC 4 +#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CONFIG_SYS_NUM_FM2_10GEC 1 +#define CONFIG_NUM_DDR_CONTROLLERS 2 + +#define CONFIG_SYS_P4080_ERRATUM_CPU22 +#define CONFIG_SYS_P4080_ERRATUM_SERDES8 + +#include "corenet_ds.h" diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index d8f2602e59..abbaf383c7 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -280,6 +280,7 @@ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h index 83aeffd29f..1fbe4fbab4 100644 --- a/include/configs/XPEDITE5200.h +++ b/include/configs/XPEDITE5200.h @@ -351,6 +351,7 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ #define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ #define CONFIG_PANIC_HANG /* do not reset board on panic */ diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h index fc4a986039..8225ffff55 100644 --- a/include/configs/XPEDITE5370.h +++ b/include/configs/XPEDITE5370.h @@ -409,6 +409,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ #define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ #define CONFIG_PANIC_HANG /* do not reset board on panic */ diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h index 37a70592f8..95d3afa85c 100644 --- a/include/configs/bf533-ezkit.h +++ b/include/configs/bf533-ezkit.h @@ -94,49 +94,10 @@ /* * I2C Settings - * By default PF1 is used as SDA and PF0 as SCL on the Stamp board */ #define CONFIG_SOFT_I2C -#ifdef CONFIG_SOFT_I2C -#define PF_SCL PF0 -#define PF_SDA PF1 -#define I2C_INIT \ - do { \ - *pFIO_DIR |= PF_SCL; \ - SSYNC(); \ - } while (0) -#define I2C_ACTIVE \ - do { \ - *pFIO_DIR |= PF_SDA; \ - *pFIO_INEN &= ~PF_SDA; \ - SSYNC(); \ - } while (0) -#define I2C_TRISTATE \ - do { \ - *pFIO_DIR &= ~PF_SDA; \ - *pFIO_INEN |= PF_SDA; \ - SSYNC(); \ - } while (0) -#define I2C_READ ((*pFIO_FLAG_D & PF_SDA) != 0) -#define I2C_SDA(bit) \ - do { \ - if (bit) \ - *pFIO_FLAG_S = PF_SDA; \ - else \ - *pFIO_FLAG_C = PF_SDA; \ - SSYNC(); \ - } while (0) -#define I2C_SCL(bit) \ - do { \ - if (bit) \ - *pFIO_FLAG_S = PF_SCL; \ - else \ - *pFIO_FLAG_C = PF_SCL; \ - SSYNC(); \ - } while (0) -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#endif +#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0 +#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1 /* diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h index 02c8bc3c36..f39bfee0a4 100644 --- a/include/configs/bf533-stamp.h +++ b/include/configs/bf533-stamp.h @@ -138,49 +138,10 @@ /* * I2C Settings - * By default PF2 is used as SDA and PF3 as SCL on the Stamp board */ #define CONFIG_SOFT_I2C -#ifdef CONFIG_SOFT_I2C -#define PF_SCL PF3 -#define PF_SDA PF2 -#define I2C_INIT \ - do { \ - *pFIO_DIR |= PF_SCL; \ - SSYNC(); \ - } while (0) -#define I2C_ACTIVE \ - do { \ - *pFIO_DIR |= PF_SDA; \ - *pFIO_INEN &= ~PF_SDA; \ - SSYNC(); \ - } while (0) -#define I2C_TRISTATE \ - do { \ - *pFIO_DIR &= ~PF_SDA; \ - *pFIO_INEN |= PF_SDA; \ - SSYNC(); \ - } while (0) -#define I2C_READ ((*pFIO_FLAG_D & PF_SDA) != 0) -#define I2C_SDA(bit) \ - do { \ - if (bit) \ - *pFIO_FLAG_S = PF_SDA; \ - else \ - *pFIO_FLAG_C = PF_SDA; \ - SSYNC(); \ - } while (0) -#define I2C_SCL(bit) \ - do { \ - if (bit) \ - *pFIO_FLAG_S = PF_SCL; \ - else \ - *pFIO_FLAG_C = PF_SCL; \ - SSYNC(); \ - } while (0) -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#endif +#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF3 +#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF2 /* diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h index 036bfe412f..4e293b58a8 100644 --- a/include/configs/bf561-ezkit.h +++ b/include/configs/bf561-ezkit.h @@ -112,46 +112,8 @@ * I2C Settings */ #define CONFIG_SOFT_I2C -#ifdef CONFIG_SOFT_I2C -#define PF_SCL PF0 -#define PF_SDA PF1 -#define I2C_INIT \ - do { \ - *pFIO0_DIR |= PF_SCL; \ - SSYNC(); \ - } while (0) -#define I2C_ACTIVE \ - do { \ - *pFIO0_DIR |= PF_SDA; \ - *pFIO0_INEN &= ~PF_SDA; \ - SSYNC(); \ - } while (0) -#define I2C_TRISTATE \ - do { \ - *pFIO0_DIR &= ~PF_SDA; \ - *pFIO0_INEN |= PF_SDA; \ - SSYNC(); \ - } while (0) -#define I2C_READ ((*pFIO0_FLAG_D & PF_SDA) != 0) -#define I2C_SDA(bit) \ - do { \ - if (bit) \ - *pFIO0_FLAG_S = PF_SDA; \ - else \ - *pFIO0_FLAG_C = PF_SDA; \ - SSYNC(); \ - } while (0) -#define I2C_SCL(bit) \ - do { \ - if (bit) \ - *pFIO0_FLAG_S = PF_SCL; \ - else \ - *pFIO0_FLAG_C = PF_SCL; \ - SSYNC(); \ - } while (0) -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#endif +#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0 +#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1 /* diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index 901a32fb72..44762689ce 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -68,6 +68,7 @@ # endif # if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) # define CONFIG_CMD_I2C +# define CONFIG_SOFT_I2C_READ_REPEATED_START # endif # ifdef CONFIG_SYS_NO_FLASH # undef CONFIG_CMD_FLASH diff --git a/include/configs/blackstamp.h b/include/configs/blackstamp.h index aa33933164..85f08ea888 100644 --- a/include/configs/blackstamp.h +++ b/include/configs/blackstamp.h @@ -206,32 +206,8 @@ * them yet. You can (and probably should) change these values! */ #ifdef CONFIG_SOFT_I2C - -#define PF_SCL PF9 -#define PF_SDA PF8 - -#define I2C_INIT do { *pFIO_DIR |= PF_SCL; SSYNC(); } while (0) -#define I2C_ACTIVE do { *pFIO_DIR |= PF_SDA; *pFIO_INEN &= ~PF_SDA; SSYNC(); } while (0) -#define I2C_TRISTATE do { *pFIO_DIR &= ~PF_SDA; *pFIO_INEN |= PF_SDA; SSYNC(); } while (0) -#define I2C_READ ((*pFIO_FLAG_D & PF_SDA) != 0) -#define I2C_SDA(bit) \ - do { \ - if (bit) \ - *pFIO_FLAG_S = PF_SDA; \ - else \ - *pFIO_FLAG_C = PF_SDA; \ - SSYNC(); \ - } while (0) -#define I2C_SCL(bit) \ - do { \ - if (bit) \ - *pFIO_FLAG_S = PF_SCL; \ - else \ - *pFIO_FLAG_C = PF_SCL; \ - SSYNC(); \ - } while (0) -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - +#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF9 +#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF8 #define CONFIG_SYS_I2C_SPEED 50000 #define CONFIG_SYS_I2C_SLAVE 0xFE #endif diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h new file mode 100644 index 0000000000..dd609da8f0 --- /dev/null +++ b/include/configs/corenet_ds.h @@ -0,0 +1,653 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Corenet DS style board configuration file + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "../board/freescale/common/ics307_clk.h" + +/* High Level Configuration Options */ +#define CONFIG_BOOKE +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_E500MC /* BOOKE e500mc family */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ +#define CONFIG_MP /* support multiple processors */ + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE3 /* PCIE controler 3 */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ +#define CONFIG_SYS_HAS_SERDES /* has SERDES */ + +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ + +#define CONFIG_FSL_LAW /* Use common FSL init code */ + +#define CONFIG_ENV_OVERWRITE + +#ifdef CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_NOWHERE +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#endif + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ +#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BACKSIDE_L2_CACHE +#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CONFIG_BTB /* toggle branch predition */ +//#define CONFIG_DDR_ECC +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#define CONFIG_ENABLE_36BIT_PHYS + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ +#endif + +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSRBAR 0xfe000000 /* relocated CCSRBAR */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_CCSRBAR_PHYS 0xffe000000ull /* physical addr of CCSRBAR */ +#else +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ +#endif +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#endif + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) + +#define CONFIG_DDR_SPD +#define CONFIG_FSL_DDR3 + +#ifdef CONFIG_DDR_SPD +#define CONFIG_SYS_SPD_BUS_NUM 1 +#define SPD_EEPROM_ADDRESS1 0x51 +#define SPD_EEPROM_ADDRESS2 0x52 +#else +#define CONFIG_SYS_SDRAM_SIZE 4096 + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f +#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 +#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 +#define CONFIG_SYS_DDR_TIMING_3 0x01031000 +#define CONFIG_SYS_DDR_TIMING_0 0x55440804 +#define CONFIG_SYS_DDR_TIMING_1 0x74713a66 +#define CONFIG_SYS_DDR_TIMING_2 0x0fb8911b +#define CONFIG_SYS_DDR_MODE_1 0x00421850 +#define CONFIG_SYS_DDR_MODE_2 0x00100000 +#define CONFIG_SYS_DDR_MODE_CTRL 0x00000000 +#define CONFIG_SYS_DDR_INTERVAL 0x10400100 +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef +#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 +#define CONFIG_SYS_DDR_TIMING_4 0x00220001 +#define CONFIG_SYS_DDR_TIMING_5 0x03401500 +#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 +#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655a608 +#define CONFIG_SYS_DDR_CONTROL 0xc7048000 +#define CONFIG_SYS_DDR_CONTROL2 0x24400011 +#define CONFIG_SYS_DDR_CDR1 0x00000000 +#define CONFIG_SYS_DDR_CDR2 0x00000000 +#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d +#define CONFIG_SYS_DDR_ERR_DIS 0x00000000 +#define CONFIG_SYS_DDR_SBE 0x00010000 +#define CONFIG_SYS_DDR_DEBUG_18 0x40100400 + +#define CONFIG_SYS_DDR2_CS0_BNDS 0x008000bf +#define CONFIG_SYS_DDR2_CS1_BNDS 0x00C000ff +#define CONFIG_SYS_DDR2_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG +#define CONFIG_SYS_DDR2_CS1_CONFIG CONFIG_SYS_DDR_CS1_CONFIG +#define CONFIG_SYS_DDR2_TIMING_3 CONFIG_SYS_DDR_TIMING_3 +#define CONFIG_SYS_DDR2_TIMING_0 CONFIG_SYS_DDR_TIMING_0 +#define CONFIG_SYS_DDR2_TIMING_1 CONFIG_SYS_DDR_TIMING_1 +#define CONFIG_SYS_DDR2_TIMING_2 CONFIG_SYS_DDR_TIMING_2 +#define CONFIG_SYS_DDR2_MODE_1 CONFIG_SYS_DDR_MODE_1 +#define CONFIG_SYS_DDR2_MODE_2 CONFIG_SYS_DDR_MODE_2 +#define CONFIG_SYS_DDR2_MODE_CTRL CONFIG_SYS_DDR_MODE_CTRL +#define CONFIG_SYS_DDR2_INTERVAL CONFIG_SYS_DDR_INTERVAL +#define CONFIG_SYS_DDR2_DATA_INIT CONFIG_SYS_DDR_DATA_INIT +#define CONFIG_SYS_DDR2_CLK_CTRL CONFIG_SYS_DDR_CLK_CTRL +#define CONFIG_SYS_DDR2_TIMING_4 CONFIG_SYS_DDR_TIMING_4 +#define CONFIG_SYS_DDR2_TIMING_5 CONFIG_SYS_DDR_TIMING_5 +#define CONFIG_SYS_DDR2_ZQ_CNTL CONFIG_SYS_DDR_ZQ_CNTL +#define CONFIG_SYS_DDR2_WRLVL_CNTL CONFIG_SYS_DDR_WRLVL_CNTL +#define CONFIG_SYS_DDR2_CONTROL CONFIG_SYS_DDR_CONTROL +#define CONFIG_SYS_DDR2_CONTROL2 CONFIG_SYS_DDR_CONTROL2 +#define CONFIG_SYS_DDR2_CDR1 CONFIG_SYS_DDR_CDR1 +#define CONFIG_SYS_DDR2_CDR2 CONFIG_SYS_DDR_CDR2 +#define CONFIG_SYS_DDR2_ERR_INT_EN CONFIG_SYS_DDR_ERR_INT_EN +#define CONFIG_SYS_DDR2_ERR_DIS CONFIG_SYS_DDR_ERR_DIS +#define CONFIG_SYS_DDR2_SBE CONFIG_SYS_DDR_SBE +#define CONFIG_SYS_DDR2_DEBUG_18 CONFIG_SYS_DDR_DEBUG_18 + +#endif + +/* + * Local Bus Definitions + */ + +/* Set the local bus clock 1/8 of platform clock */ +#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 + +#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull +#else +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif + +#define CONFIG_SYS_BR0_PRELIM \ + (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \ + BR_PS_16 | BR_V) +#define CONFIG_SYS_OR0_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ + | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) + +#define CONFIG_SYS_BR1_PRELIM \ + (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) +#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 + +#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ +#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ +#ifdef CONFIG_PHYS_64BIT +#define PIXIS_BASE_PHYS 0xfffdf0000ull +#else +#define PIXIS_BASE_PHYS PIXIS_BASE +#endif + +#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) +#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ + +#define PIXIS_LBMAP_SWITCH 7 +#define PIXIS_LBMAP_MASK 0xf0 +#define PIXIS_LBMAP_SHIFT 4 +#define PIXIS_LBMAP_ALTBANK 0x40 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#else +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#endif +#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ + +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ + +/* Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* I2C */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x118000 +#define CONFIG_SYS_I2C2_OFFSET 0x118100 + +/* + * RapidIO + */ +#define CONFIG_SYS_RIO1_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_RIO1_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_RIO1_MEM_PHYS 0xa0000000 +#endif +#define CONFIG_SYS_RIO1_MEM_SIZE 0x10000000 /* 256M */ + +#define CONFIG_SYS_RIO2_MEM_VIRT 0xb0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_RIO2_MEM_PHYS 0xc30000000ull +#else +#define CONFIG_SYS_RIO2_MEM_PHYS 0xb0000000 +#endif +#define CONFIG_SYS_RIO2_MEM_SIZE 0x10000000 /* 256M */ + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 +#endif +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#else +#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 +#endif +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +/* controller 2, Slot 2, tgtid 2, Base address 201000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#endif +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#else +#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 +#endif +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xe0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull +#else +#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 +#endif +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#else +#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 +#endif +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ + +/* Qman/Bman */ +#define CONFIG_SYS_BMAN_NUM_PORTALS 10 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#else +#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE +#endif +#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 +#define CONFIG_SYS_QMAN_NUM_PORTALS 10 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull +#else +#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE +#endif +#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 + +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_PME +/* Default address of microcode for the Linux Fman driver */ +#define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_FMAN_FW_ADDR_PHYS 0xFEF000000ULL +#else +#define CONFIG_SYS_FMAN_FW_ADDR_PHYS CONFIG_SYS_FMAN_FW_ADDR +#endif + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#endif + +#ifdef CONFIG_PCI + +/*PCIE video card used*/ +#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT + +/* video */ +#define CONFIG_VIDEO + +#ifdef CONFIG_VIDEO +#define CONFIG_BIOSEMU +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_ATI_RADEON_FB +#define CONFIG_VIDEO_LOGO +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET +#endif + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_E1000 + +#ifndef CONFIG_PCI_PNP +#define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS +#define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS +#define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ +#endif + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif /* CONFIG_PCI */ + +/* SATA */ +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA + +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA + +#define CONFIG_LBA48 +#define CONFIG_CMD_SATA +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#endif + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c +#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d +#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e +#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f +#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 + +#if (CONFIG_SYS_NUM_FMAN == 2) +#define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c +#define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d +#define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e +#define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f +#define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 +#endif + +#define CONFIG_SYS_TBIPA_VALUE 8 +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_ETHPRIME "FM1@DTSEC1" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* + * Environment + */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ + +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR + +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + +/* +* USB +*/ +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_CMD_EXT2 + +#define CONFIG_MMC + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 16 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH /opt/nfsroot +#define CONFIG_BOOTFILE uImage +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=p4080ds/ramdisk.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=p4080ds/p4080ds.dtb\0" \ + "bdev=sda3\0" \ + "c=ffe\0" \ + "fman_ucode="MK_STR(CONFIG_SYS_FMAN_FW_ADDR_PHYS)"\0" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT + +#endif /* __CONFIG_H */ diff --git a/include/configs/ibf-dsp561.h b/include/configs/ibf-dsp561.h index 2c0a263da2..53b5197112 100644 --- a/include/configs/ibf-dsp561.h +++ b/include/configs/ibf-dsp561.h @@ -112,33 +112,8 @@ * I2C Settings */ #define CONFIG_SOFT_I2C 1 -#define PF_SCL 0x1/*PF0*/ -#define PF_SDA 0x2/*PF1*/ - -#ifdef CONFIG_SOFT_I2C -#define I2C_INIT do { *pFIO0_DIR |= PF_SCL; SSYNC(); } while (0) -#define I2C_ACTIVE do { *pFIO0_DIR |= PF_SDA; *pFIO0_INEN &= ~PF_SDA; SSYNC(); } while (0) -#define I2C_TRISTATE do { *pFIO0_DIR &= ~PF_SDA; *pFIO0_INEN |= PF_SDA; SSYNC(); } while (0) -#define I2C_READ ((*pFIO0_FLAG_D & PF_SDA) != 0) -#define I2C_SDA(bit) \ - do { \ - if (bit) \ - *pFIO0_FLAG_S = PF_SDA; \ - else \ - *pFIO0_FLAG_C = PF_SDA; \ - SSYNC(); \ - } while (0) -#define I2C_SCL(bit) \ - do { \ - if (bit) \ - *pFIO0_FLAG_S = PF_SCL; \ - else \ - *pFIO0_FLAG_C = PF_SCL; \ - SSYNC(); \ - } while (0) -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#endif +#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0 +#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1 /* diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index c8b8d0d80d..564f661bcb 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -496,6 +496,7 @@ * Miscellaneous configurable options */ #define CONFIG_CMDLINE_EDITING /* undef to save memory */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index ad7010900d..af1e19ee0a 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -233,6 +233,7 @@ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index 363f7b473a..57bb8d1a38 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -189,6 +189,7 @@ #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index 6d029954b1..d3e22d9018 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -228,6 +228,8 @@ #undef CONFIG_IDE_LED #undef CONFIG_IDE_RESET +#define __io + #define CONFIG_SYS_IDE_MAXBUS 1 #define CONFIG_SYS_IDE_MAXDEVICE 1 diff --git a/include/ddr_spd.h b/include/ddr_spd.h index 10402c5bbb..710e5289c7 100644 --- a/include/ddr_spd.h +++ b/include/ddr_spd.h @@ -243,6 +243,20 @@ typedef struct ddr3_spd_eeprom_s { unsigned char mod_thickness; /* 62 (Registered) Reference Raw Card Used */ unsigned char ref_raw_card; + /* 63 DIMM Module Attributes */ + unsigned char modu_attr; + /* 64 RDIMM Thermal Heat Spreader Solution */ + unsigned char thermal; + /* 65 Register Manufacturer ID Code, Least Significant Byte */ + unsigned char reg_id_lo; + /* 66 Register Manufacturer ID Code, Most Significant Byte */ + unsigned char reg_id_hi; + /* 67 Register Revision Number */ + unsigned char reg_rev; + /* 68 Register Type */ + unsigned char reg_type; + /* 69-76 RC1,3,5...15 (MS Nibble) / RC0,2,4...14 (LS Nibble) */ + unsigned char rcw[8]; } registered; unsigned char uc[57]; /* 60-116 Module-Specific Section */ } mod_section; diff --git a/include/fdt_support.h b/include/fdt_support.h index 54af9fe712..871ef4524b 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -86,6 +86,7 @@ void fdt_del_node_and_alias(void *blob, const char *alias); u64 fdt_translate_address(void *blob, int node_offset, const u32 *in_addr); int fdt_node_offset_by_compat_reg(void *blob, const char *compat, phys_addr_t compat_off); +int fdt_alloc_phandle(void *blob); #endif /* ifdef CONFIG_OF_LIBFDT */ #endif /* ifndef __FDT_SUPPORT_H */ |