4 files changed, 125 insertions, 1 deletions

diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig
index 81fc9f8fda..644881b948 100644
--- a/drivers/clk/sifive/Kconfig
+++ b/drivers/clk/sifive/Kconfig
@@ -17,3 +17,10 @@ config CLK_SIFIVE_FU540_PRCI
 	  Supports the Power Reset Clock interface (PRCI) IP block found in
 	  FU540 SoCs.  If this kernel is meant to run on a SiFive FU540 SoC,
 	  enable this driver.
+
+config CLK_SIFIVE_GEMGXL_MGMT
+	bool "GEMGXL management for SiFive FU540 SoCs"
+	depends on CLK_SIFIVE
+	help
+	  Supports the GEMGXL management IP block found in FU540 SoCs to
+	  control GEM TX clock operation mode for 10/100/1000 Mbps.
diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile
index 1155e07e37..f8263e79b7 100644
--- a/drivers/clk/sifive/Makefile
+++ b/drivers/clk/sifive/Makefile
@@ -3,3 +3,5 @@
 obj-$(CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC)	+= wrpll-cln28hpc.o
 
 obj-$(CONFIG_CLK_SIFIVE_FU540_PRCI)		+= fu540-prci.o
+
+obj-$(CONFIG_CLK_SIFIVE_GEMGXL_MGMT)		+= gemgxl-mgmt.o
diff --git a/drivers/clk/sifive/gemgxl-mgmt.c b/drivers/clk/sifive/gemgxl-mgmt.c
new file mode 100644
index 0000000000..eb37416b5e
--- /dev/null
+++ b/drivers/clk/sifive/gemgxl-mgmt.c
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <asm/io.h>
+
+struct gemgxl_mgmt_regs {
+	__u32 tx_clk_sel;
+};
+
+struct gemgxl_mgmt_platdata {
+	struct gemgxl_mgmt_regs *regs;
+};
+
+static int gemgxl_mgmt_ofdata_to_platdata(struct udevice *dev)
+{
+	struct gemgxl_mgmt_platdata *plat = dev_get_platdata(dev);
+
+	plat->regs = (struct gemgxl_mgmt_regs *)dev_read_addr(dev);
+
+	return 0;
+}
+
+static ulong gemgxl_mgmt_set_rate(struct clk *clk, ulong rate)
+{
+	struct gemgxl_mgmt_platdata *plat = dev_get_platdata(clk->dev);
+
+	/*
+	 * GEMGXL TX clock operation mode:
+	 *
+	 * 0 = GMII mode. Use 125 MHz gemgxlclk from PRCI in TX logic
+	 *     and output clock on GMII output signal GTX_CLK
+	 * 1 = MII mode. Use MII input signal TX_CLK in TX logic
+	 */
+	writel(rate != 125000000, &plat->regs->tx_clk_sel);
+
+	return 0;
+}
+
+const struct clk_ops gemgxl_mgmt_ops = {
+	.set_rate = gemgxl_mgmt_set_rate,
+};
+
+static const struct udevice_id gemgxl_mgmt_match[] = {
+	{ .compatible = "sifive,cadencegemgxlmgmt0", },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(sifive_gemgxl_mgmt) = {
+	.name = "sifive-gemgxl-mgmt",
+	.id = UCLASS_CLK,
+	.of_match = gemgxl_mgmt_match,
+	.ofdata_to_platdata = gemgxl_mgmt_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct gemgxl_mgmt_platdata),
+	.ops = &gemgxl_mgmt_ops,
+};
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 72614164e9..c5560a7111 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -488,15 +488,58 @@ static int macb_phy_find(struct macb_device *macb, const char *name)
 
 /**
  * macb_linkspd_cb - Linkspeed change callback function
- * @regs:	Base Register of MACB devices
+ * @dev/@regs:	MACB udevice (DM version) or
+ *		Base Register of MACB devices (non-DM version)
  * @speed:	Linkspeed
  * Returns 0 when operation success and negative errno number
  * when operation failed.
  */
+#ifdef CONFIG_DM_ETH
+int __weak macb_linkspd_cb(struct udevice *dev, unsigned int speed)
+{
+#ifdef CONFIG_CLK
+	struct clk tx_clk;
+	ulong rate;
+	int ret;
+
+	/*
+	 * "tx_clk" is an optional clock source for MACB.
+	 * Ignore if it does not exist in DT.
+	 */
+	ret = clk_get_by_name(dev, "tx_clk", &tx_clk);
+	if (ret)
+		return 0;
+
+	switch (speed) {
+	case _10BASET:
+		rate = 2500000;		/* 2.5 MHz */
+		break;
+	case _100BASET:
+		rate = 25000000;	/* 25 MHz */
+		break;
+	case _1000BASET:
+		rate = 125000000;	/* 125 MHz */
+		break;
+	default:
+		/* does not change anything */
+		return 0;
+	}
+
+	if (tx_clk.dev) {
+		ret = clk_set_rate(&tx_clk, rate);
+		if (ret)
+			return ret;
+	}
+#endif
+
+	return 0;
+}
+#else
 int __weak macb_linkspd_cb(void *regs, unsigned int speed)
 {
 	return 0;
 }
+#endif
 
 #ifdef CONFIG_DM_ETH
 static int macb_phy_init(struct udevice *dev, const char *name)
@@ -589,7 +632,11 @@ static int macb_phy_init(struct macb_device *macb, const char *name)
 
 			macb_writel(macb, NCFGR, ncfgr);
 
+#ifdef CONFIG_DM_ETH
+			ret = macb_linkspd_cb(dev, _1000BASET);
+#else
 			ret = macb_linkspd_cb(macb->regs, _1000BASET);
+#endif
 			if (ret)
 				return ret;
 
@@ -614,9 +661,17 @@ static int macb_phy_init(struct macb_device *macb, const char *name)
 	ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE));
 	if (speed) {
 		ncfgr |= MACB_BIT(SPD);
+#ifdef CONFIG_DM_ETH
+		ret = macb_linkspd_cb(dev, _100BASET);
+#else
 		ret = macb_linkspd_cb(macb->regs, _100BASET);
+#endif
 	} else {
+#ifdef CONFIG_DM_ETH
+		ret = macb_linkspd_cb(dev, _10BASET);
+#else
 		ret = macb_linkspd_cb(macb->regs, _10BASET);
+#endif
 	}
 
 	if (ret)