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-rw-r--r--drivers/misc/Makefile1
-rw-r--r--drivers/misc/fsl_law.c70
-rw-r--r--drivers/mtd/nand/Makefile2
-rw-r--r--drivers/mtd/nand/fsl_upm.c201
-rw-r--r--drivers/mtd/onenand/Makefile2
-rw-r--r--drivers/mtd/onenand/onenand_base.c20
-rw-r--r--drivers/mtd/onenand/onenand_uboot.c41
-rw-r--r--drivers/pcmcia/marubun_pcmcia.c6
-rw-r--r--drivers/serial/serial_sh.c36
-rw-r--r--drivers/spi/Makefile46
-rw-r--r--drivers/spi/mpc8xxx_spi.c143
11 files changed, 538 insertions, 30 deletions
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 78cec21fba..67521720e7 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -28,6 +28,7 @@ LIB := $(obj)libmisc.a
COBJS-y += ali512x.o
COBJS-y += ns87308.o
COBJS-y += status_led.o
+COBJS-$(CONFIG_FSL_LAW) += fsl_law.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c
new file mode 100644
index 0000000000..8bdf5a7f41
--- /dev/null
+++ b/drivers/misc/fsl_law.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/io.h>
+
+#define LAWAR_EN 0x80000000
+
+void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
+{
+ volatile u32 *base = (volatile u32 *)(CFG_IMMR + 0xc08);
+ volatile u32 *lawbar = base + 8 * idx;
+ volatile u32 *lawar = base + 8 * idx + 2;
+
+ out_be32(lawbar, addr >> 12);
+ out_be32(lawar, LAWAR_EN | ((u32)id << 20) | (u32)sz);
+
+ return ;
+}
+
+void disable_law(u8 idx)
+{
+ volatile u32 *base = (volatile u32 *)(CFG_IMMR + 0xc08);
+ volatile u32 *lawbar = base + 8 * idx;
+ volatile u32 *lawar = base + 8 * idx + 2;
+
+ out_be32(lawar, 0);
+ out_be32(lawbar, 0);
+
+ return;
+}
+
+void init_laws(void)
+{
+ int i;
+ u8 law_idx = 0;
+
+ for (i = 0; i < num_law_entries; i++) {
+ if (law_table[i].index != -1)
+ law_idx = law_table[i].index;
+
+ set_law(law_idx++, law_table[i].addr,
+ law_table[i].size, law_table[i].trgt_id);
+ }
+
+ return ;
+}
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 42864f98f4..244fa09b20 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -32,6 +32,8 @@ COBJS-y += nand_ecc.o
COBJS-y += nand_bbt.o
COBJS-y += nand_util.o
+COBJS-y += fsl_upm.o
+
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/drivers/mtd/nand/fsl_upm.c b/drivers/mtd/nand/fsl_upm.c
new file mode 100644
index 0000000000..5cc410a5e2
--- /dev/null
+++ b/drivers/mtd/nand/fsl_upm.c
@@ -0,0 +1,201 @@
+/*
+ * FSL UPM NAND driver
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ * Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <config.h>
+
+#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_FSL_UPM)
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/fsl_upm.h>
+#include <nand.h>
+
+#define FSL_UPM_MxMR_OP_NO (0 << 28) /* normal operation */
+#define FSL_UPM_MxMR_OP_WA (1 << 28) /* write array */
+#define FSL_UPM_MxMR_OP_RA (2 << 28) /* read array */
+#define FSL_UPM_MxMR_OP_RP (3 << 28) /* run pattern */
+
+static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset)
+{
+ out_be32(upm->mxmr, FSL_UPM_MxMR_OP_RP | pat_offset);
+}
+
+static void fsl_upm_end_pattern(struct fsl_upm *upm)
+{
+ out_be32(upm->mxmr, FSL_UPM_MxMR_OP_NO);
+ while (in_be32(upm->mxmr) != FSL_UPM_MxMR_OP_NO)
+ eieio();
+}
+
+static void fsl_upm_run_pattern(struct fsl_upm *upm, int width, u32 cmd)
+{
+ out_be32(upm->mar, cmd << (32 - width * 8));
+ out_8(upm->io_addr, 0x0);
+}
+
+static void fsl_upm_setup(struct fsl_upm *upm)
+{
+ int i;
+
+ /* write upm array */
+ out_be32(upm->mxmr, FSL_UPM_MxMR_OP_WA);
+
+ for (i = 0; i < 64; i++) {
+ out_be32(upm->mdr, upm->array[i]);
+ out_8(upm->io_addr, 0x0);
+ }
+
+ /* normal operation */
+ out_be32(upm->mxmr, FSL_UPM_MxMR_OP_NO);
+ while (in_be32(upm->mxmr) != FSL_UPM_MxMR_OP_NO)
+ eieio();
+}
+
+static void fun_cmdfunc(struct mtd_info *mtd, unsigned command, int column,
+ int page_addr)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct fsl_upm_nand *fun = chip->priv;
+
+ fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
+
+ if (command == NAND_CMD_SEQIN) {
+ int readcmd;
+
+ if (column >= mtd->oobblock) {
+ /* OOB area */
+ column -= mtd->oobblock;
+ readcmd = NAND_CMD_READOOB;
+ } else if (column < 256) {
+ /* First 256 bytes --> READ0 */
+ readcmd = NAND_CMD_READ0;
+ } else {
+ column -= 256;
+ readcmd = NAND_CMD_READ1;
+ }
+ fsl_upm_run_pattern(&fun->upm, fun->width, readcmd);
+ }
+
+ fsl_upm_run_pattern(&fun->upm, fun->width, command);
+
+ fsl_upm_end_pattern(&fun->upm);
+
+ fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
+
+ if (column != -1)
+ fsl_upm_run_pattern(&fun->upm, fun->width, column);
+
+ if (page_addr != -1) {
+ fsl_upm_run_pattern(&fun->upm, fun->width, page_addr);
+ fsl_upm_run_pattern(&fun->upm, fun->width,
+ (page_addr >> 8) & 0xFF);
+ if (chip->chipsize > (32 << 20)) {
+ fsl_upm_run_pattern(&fun->upm, fun->width,
+ (page_addr >> 16) & 0x0f);
+ }
+ }
+
+ fsl_upm_end_pattern(&fun->upm);
+
+ if (fun->wait_pattern) {
+ /*
+ * Some boards/chips needs this. At least on MPC8360E-RDK we
+ * need it. Probably weird chip, because I don't see any need
+ * for this on MPC8555E + Samsung K9F1G08U0A. Usually here are
+ * 0-2 unexpected busy states per block read.
+ */
+ while (!fun->dev_ready())
+ debug("unexpected busy state\n");
+ }
+}
+
+static void nand_write_byte(struct mtd_info *mtd, u_char byte)
+{
+ struct nand_chip *chip = mtd->priv;
+
+ out_8(chip->IO_ADDR_W, byte);
+}
+
+static u8 nand_read_byte(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd->priv;
+
+ return in_8(chip->IO_ADDR_R);
+}
+
+static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+ int i;
+ struct nand_chip *chip = mtd->priv;
+
+ for (i = 0; i < len; i++)
+ out_8(chip->IO_ADDR_W, buf[i]);
+}
+
+static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+ int i;
+ struct nand_chip *chip = mtd->priv;
+
+ for (i = 0; i < len; i++)
+ buf[i] = in_8(chip->IO_ADDR_R);
+}
+
+static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+ int i;
+ struct nand_chip *chip = mtd->priv;
+
+ for (i = 0; i < len; i++) {
+ if (buf[i] != in_8(chip->IO_ADDR_R))
+ return -EFAULT;
+ }
+
+ return 0;
+}
+
+static void nand_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+}
+
+static int nand_dev_ready(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct fsl_upm_nand *fun = chip->priv;
+
+ return fun->dev_ready();
+}
+
+int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun)
+{
+ /* yet only 8 bit accessors implemented */
+ if (fun->width != 1)
+ return -ENOSYS;
+
+ fsl_upm_setup(&fun->upm);
+
+ chip->priv = fun;
+ chip->chip_delay = fun->chip_delay;
+ chip->eccmode = NAND_ECC_SOFT;
+ chip->cmdfunc = fun_cmdfunc;
+ chip->hwcontrol = nand_hwcontrol;
+ chip->read_byte = nand_read_byte;
+ chip->read_buf = nand_read_buf;
+ chip->write_byte = nand_write_byte;
+ chip->write_buf = nand_write_buf;
+ chip->verify_buf = nand_verify_buf;
+ chip->dev_ready = nand_dev_ready;
+
+ return 0;
+}
+#endif /* CONFIG_CMD_NAND */
diff --git a/drivers/mtd/onenand/Makefile b/drivers/mtd/onenand/Makefile
index 2049413327..92074b2552 100644
--- a/drivers/mtd/onenand/Makefile
+++ b/drivers/mtd/onenand/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB := $(obj)libonenand.a
-COBJS := onenand_base.o onenand_bbt.o
+COBJS := onenand_uboot.o onenand_base.o onenand_bbt.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c
index 7983a4a0d8..d4003a20f2 100644
--- a/drivers/mtd/onenand/onenand_base.c
+++ b/drivers/mtd/onenand/onenand_base.c
@@ -1271,24 +1271,4 @@ void onenand_release(struct mtd_info *mtd)
{
}
-/*
- * OneNAND initialization at U-Boot
- */
-struct mtd_info onenand_mtd;
-struct onenand_chip onenand_chip;
-
-void onenand_init(void)
-{
- memset(&onenand_mtd, 0, sizeof(struct mtd_info));
- memset(&onenand_chip, 0, sizeof(struct onenand_chip));
-
- onenand_chip.base = (void *)CFG_ONENAND_BASE;
- onenand_mtd.priv = &onenand_chip;
-
- onenand_scan(&onenand_mtd, 1);
-
- puts("OneNAND: ");
- print_size(onenand_mtd.size, "\n");
-}
-
#endif /* CONFIG_CMD_ONENAND */
diff --git a/drivers/mtd/onenand/onenand_uboot.c b/drivers/mtd/onenand/onenand_uboot.c
new file mode 100644
index 0000000000..bd7466ac9d
--- /dev/null
+++ b/drivers/mtd/onenand/onenand_uboot.c
@@ -0,0 +1,41 @@
+/*
+ * drivers/mtd/onenand/onenand_uboot.c
+ *
+ * Copyright (C) 2005-2008 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * OneNAND initialization at U-Boot
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_CMD_ONENAND
+
+#include <linux/mtd/compat.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+
+struct mtd_info onenand_mtd;
+struct onenand_chip onenand_chip;
+
+void onenand_init(void)
+{
+ memset(&onenand_mtd, 0, sizeof(struct mtd_info));
+ memset(&onenand_chip, 0, sizeof(struct onenand_chip));
+
+ onenand_chip.base = (void *) CFG_ONENAND_BASE;
+ onenand_mtd.priv = &onenand_chip;
+
+ onenand_scan(&onenand_mtd, 1);
+
+ puts("OneNAND: ");
+ print_size(onenand_mtd.size, "\n");
+}
+
+#endif /* CONFIG_CMD_ONENAND */
diff --git a/drivers/pcmcia/marubun_pcmcia.c b/drivers/pcmcia/marubun_pcmcia.c
index 7b112af922..2479a6662a 100644
--- a/drivers/pcmcia/marubun_pcmcia.c
+++ b/drivers/pcmcia/marubun_pcmcia.c
@@ -25,11 +25,13 @@
#include <pcmcia.h>
#include <asm/io.h>
-#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+#undef CONFIG_PCMCIA
+
+#if defined(CONFIG_CMD_PCMCIA)
#define CONFIG_PCMCIA
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_IDE)
+#if defined(CONFIG_CMD_IDE)
#define CONFIG_PCMCIA
#endif
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index ee44ba2644..00a9b39195 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -30,24 +30,39 @@
#error "Default SCIF doesn't set....."
#endif
-#define SCSMR (vu_short *)(SCIF_BASE + 0x0)
-#define SCBRR (vu_char *)(SCIF_BASE + 0x4)
-#define SCSCR (vu_short *)(SCIF_BASE + 0x8)
+/* Base register */
+#define SCSMR (vu_short *)(SCIF_BASE + 0x0)
+#define SCBRR (vu_char *)(SCIF_BASE + 0x4)
+#define SCSCR (vu_short *)(SCIF_BASE + 0x8)
+#define SCFCR (vu_short *)(SCIF_BASE + 0x18)
+#define SCFDR (vu_short *)(SCIF_BASE + 0x1C)
+#ifdef CONFIG_SH7720 /* SH7720 specific */
+#define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */
+#define SCFTDR (vu_char *)(SCIF_BASE + 0x20)
+#define SCFRDR (vu_char *)(SCIF_BASE + 0x24)
+#else
#define SCFTDR (vu_char *)(SCIF_BASE + 0xC)
#define SCFSR (vu_short *)(SCIF_BASE + 0x10)
#define SCFRDR (vu_char *)(SCIF_BASE + 0x14)
-#define SCFCR (vu_short *)(SCIF_BASE + 0x18)
-#define SCFDR (vu_short *)(SCIF_BASE + 0x1C)
+#endif
+
#if defined(CONFIG_SH4A)
#define SCRFDR (vu_short *)(SCIF_BASE + 0x20)
#define SCSPTR (vu_short *)(SCIF_BASE + 0x24)
#define SCLSR (vu_short *)(SCIF_BASE + 0x28)
#define SCRER (vu_short *)(SCIF_BASE + 0x2C)
+#define LSR_ORER 1
#elif defined (CONFIG_SH4)
#define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
#define SCLSR (vu_short *)(SCIF_BASE + 0x24)
+#define LSR_ORER 1
#elif defined (CONFIG_SH3)
-#define SCLSR (vu_short *)(SCIF_BASE + 0x24)
+#ifdef CONFIG_SH7720 /* SH7720 specific */
+# define SCLSR SCFSR /* SCSSR */
+#else
+# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
+#endif
+#define LSR_ORER 0x0200
#endif
#define SCR_RE (1 << 4)
@@ -67,10 +82,18 @@
void serial_setbrg (void)
{
DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CPU_SH7720)
+ int divisor = gd->baudrate * 16;
+
+ *SCBRR = (CONFIG_SYS_CLK_FREQ * 2 + (divisor / 2)) /
+ (gd->baudrate * 32) - 1;
+#else
int divisor = gd->baudrate * 32;
*SCBRR = (CONFIG_SYS_CLK_FREQ + (divisor / 2)) /
(gd->baudrate * 32) - 1;
+#endif
}
int serial_init (void)
@@ -133,7 +156,6 @@ int serial_tstc (void)
#define FSR_ERR_CLEAR 0x0063
#define RDRF_CLEAR 0x00fc
-#define LSR_ORER 1
void handle_error( void ){
(void)*SCFSR ;
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
new file mode 100644
index 0000000000..0b7a2dfd3b
--- /dev/null
+++ b/drivers/spi/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB := $(obj)libspi.a
+
+COBJS-y += mpc8xxx_spi.o
+
+COBJS := $(COBJS-y)
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+all: $(LIB)
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/drivers/spi/mpc8xxx_spi.c b/drivers/spi/mpc8xxx_spi.c
new file mode 100644
index 0000000000..a3d1c95515
--- /dev/null
+++ b/drivers/spi/mpc8xxx_spi.c
@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) 2006 Ben Warren, Qstreams Networks Inc.
+ * With help from the common/soft_spi and cpu/mpc8260 drivers
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <asm/mpc8xxx_spi.h>
+
+#ifdef CONFIG_HARD_SPI
+
+#define SPI_EV_NE (0x80000000 >> 22) /* Receiver Not Empty */
+#define SPI_EV_NF (0x80000000 >> 23) /* Transmitter Not Full */
+
+#define SPI_MODE_LOOP (0x80000000 >> 1) /* Loopback mode */
+#define SPI_MODE_REV (0x80000000 >> 5) /* Reverse mode - MSB first */
+#define SPI_MODE_MS (0x80000000 >> 6) /* Always master */
+#define SPI_MODE_EN (0x80000000 >> 7) /* Enable interface */
+
+#define SPI_TIMEOUT 1000
+
+void spi_init(void)
+{
+ volatile spi8xxx_t *spi = &((immap_t *) (CFG_IMMR))->spi;
+
+ /*
+ * SPI pins on the MPC83xx are not muxed, so all we do is initialize
+ * some registers
+ */
+ spi->mode = SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN;
+ spi->mode = (spi->mode & 0xfff0ffff) | (1 << 16); /* Use SYSCLK / 8
+ (16.67MHz typ.) */
+ spi->event = 0xffffffff; /* Clear all SPI events */
+ spi->mask = 0x00000000; /* Mask all SPI interrupts */
+ spi->com = 0; /* LST bit doesn't do anything, so disregard */
+}
+
+int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din)
+{
+ volatile spi8xxx_t *spi = &((immap_t *) (CFG_IMMR))->spi;
+ unsigned int tmpdout, tmpdin, event;
+ int numBlks = bitlen / 32 + (bitlen % 32 ? 1 : 0);
+ int tm, isRead = 0;
+ unsigned char charSize = 32;
+
+ debug("spi_xfer: chipsel %08X dout %08X din %08X bitlen %d\n",
+ (int)chipsel, *(uint *) dout, *(uint *) din, bitlen);
+
+ if (chipsel != NULL)
+ (*chipsel) (1); /* select the target chip */
+
+ spi->event = 0xffffffff; /* Clear all SPI events */
+
+ /* handle data in 32-bit chunks */
+ while (numBlks--) {
+ tmpdout = 0;
+ charSize = (bitlen >= 32 ? 32 : bitlen);
+
+ /* Shift data so it's msb-justified */
+ tmpdout = *(u32 *) dout >> (32 - charSize);
+
+ /* The LEN field of the SPMODE register is set as follows:
+ *
+ * Bit length setting
+ * len <= 4 3
+ * 4 < len <= 16 len - 1
+ * len > 16 0
+ */
+
+ if (bitlen <= 16) {
+ if (bitlen <= 4)
+ spi->mode = (spi->mode & 0xff0fffff) |
+ (3 << 20);
+ else
+ spi->mode = (spi->mode & 0xff0fffff) |
+ ((bitlen - 1) << 20);
+ } else {
+ spi->mode = (spi->mode & 0xff0fffff);
+ /* Set up the next iteration if sending > 32 bits */
+ bitlen -= 32;
+ dout += 4;
+ }
+
+ spi->tx = tmpdout; /* Write the data out */
+ debug("*** spi_xfer: ... %08x written\n", tmpdout);
+
+ /*
+ * Wait for SPI transmit to get out
+ * or time out (1 second = 1000 ms)
+ * The NE event must be read and cleared first
+ */
+ for (tm = 0, isRead = 0; tm < SPI_TIMEOUT; ++tm) {
+ event = spi->event;
+ if (event & SPI_EV_NE) {
+ tmpdin = spi->rx;
+ spi->event |= SPI_EV_NE;
+ isRead = 1;
+
+ *(u32 *) din = (tmpdin << (32 - charSize));
+ if (charSize == 32) {
+ /* Advance output buffer by 32 bits */
+ din += 4;
+ }
+ }
+ /*
+ * Only bail when we've had both NE and NF events.
+ * This will cause timeouts on RO devices, so maybe
+ * in the future put an arbitrary delay after writing
+ * the device. Arbitrary delays suck, though...
+ */
+ if (isRead && (event & SPI_EV_NF))
+ break;
+ }
+ if (tm >= SPI_TIMEOUT)
+ puts("*** spi_xfer: Time out during SPI transfer");
+
+ debug("*** spi_xfer: transfer ended. Value=%08x\n", tmpdin);
+ }
+
+ if (chipsel != NULL)
+ (*chipsel) (0); /* deselect the target chip */
+
+ return 0;
+}
+#endif /* CONFIG_HARD_SPI */