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-rw-r--r--drivers/clk/Kconfig9
-rw-r--r--drivers/clk/Makefile2
-rw-r--r--drivers/clk/altera/clk-agilex.c54
-rw-r--r--drivers/clk/altera/clk-arria10.c24
-rw-r--r--drivers/clk/aspeed/clk_ast2500.c6
-rw-r--r--drivers/clk/at91/compat.c86
-rw-r--r--drivers/clk/at91/sckc.c2
-rw-r--r--drivers/clk/clk-cdce9xx.c2
-rw-r--r--drivers/clk/clk-divider.c24
-rw-r--r--drivers/clk/clk-hsdk-cgu.c2
-rw-r--r--drivers/clk/clk-uclass.c17
-rw-r--r--drivers/clk/clk.c8
-rw-r--r--drivers/clk/clk_bcm6345.c2
-rw-r--r--drivers/clk/clk_boston.c10
-rw-r--r--drivers/clk/clk_fixed_factor.c8
-rw-r--r--drivers/clk/clk_fixed_rate.c10
-rw-r--r--drivers/clk/clk_octeon.c2
-rw-r--r--drivers/clk/clk_pic32.c2
-rw-r--r--drivers/clk/clk_sandbox.c19
-rw-r--r--drivers/clk/clk_sandbox_test.c12
-rw-r--r--drivers/clk/clk_stm32f.c2
-rw-r--r--drivers/clk/clk_stm32h7.c2
-rw-r--r--drivers/clk/clk_stm32mp1.c4
-rw-r--r--drivers/clk/clk_versal.c2
-rw-r--r--drivers/clk/clk_vexpress_osc.c2
-rw-r--r--drivers/clk/clk_zynq.c2
-rw-r--r--drivers/clk/clk_zynqmp.c4
-rw-r--r--drivers/clk/exynos/clk-exynos7420.c4
-rw-r--r--drivers/clk/ics8n3qv01.c2
-rw-r--r--drivers/clk/imx/clk-imx8.c2
-rw-r--r--drivers/clk/mediatek/clk-mt7622.c16
-rw-r--r--drivers/clk/mediatek/clk-mt7623.c12
-rw-r--r--drivers/clk/mediatek/clk-mt7629.c14
-rw-r--r--drivers/clk/mediatek/clk-mt8512.c8
-rw-r--r--drivers/clk/mediatek/clk-mt8516.c6
-rw-r--r--drivers/clk/mediatek/clk-mt8518.c6
-rw-r--r--drivers/clk/mediatek/clk-mtk.c6
-rw-r--r--drivers/clk/meson/axg.c4
-rw-r--r--drivers/clk/meson/g12a-ao.c4
-rw-r--r--drivers/clk/meson/g12a.c4
-rw-r--r--drivers/clk/meson/gxbb.c4
-rw-r--r--drivers/clk/mpc83xx_clk.c2
-rw-r--r--drivers/clk/mtmips/clk-mt7628.c2
-rw-r--r--drivers/clk/mvebu/armada-37xx-periph.c2
-rw-r--r--drivers/clk/mvebu/armada-37xx-tbg.c2
-rw-r--r--drivers/clk/owl/clk_owl.c2
-rw-r--r--drivers/clk/renesas/r8a774a1-cpg-mssr.c2
-rw-r--r--drivers/clk/renesas/r8a774b1-cpg-mssr.c2
-rw-r--r--drivers/clk/renesas/r8a774c0-cpg-mssr.c2
-rw-r--r--drivers/clk/renesas/r8a774e1-cpg-mssr.c2
-rw-r--r--drivers/clk/renesas/r8a7790-cpg-mssr.c2
-rw-r--r--drivers/clk/renesas/r8a7791-cpg-mssr.c2
-rw-r--r--drivers/clk/renesas/r8a7792-cpg-mssr.c2
-rw-r--r--drivers/clk/renesas/r8a7794-cpg-mssr.c2
-rw-r--r--drivers/clk/renesas/r8a7795-cpg-mssr.c2
-rw-r--r--drivers/clk/renesas/r8a7796-cpg-mssr.c2
-rw-r--r--drivers/clk/renesas/r8a77965-cpg-mssr.c2
-rw-r--r--drivers/clk/renesas/r8a77970-cpg-mssr.c2
-rw-r--r--drivers/clk/renesas/r8a77980-cpg-mssr.c2
-rw-r--r--drivers/clk/renesas/r8a77990-cpg-mssr.c2
-rw-r--r--drivers/clk/renesas/r8a77995-cpg-mssr.c2
-rw-r--r--drivers/clk/rockchip/clk_px30.c15
-rw-r--r--drivers/clk/rockchip/clk_rk3036.c9
-rw-r--r--drivers/clk/rockchip/clk_rk3128.c9
-rw-r--r--drivers/clk/rockchip/clk_rk3188.c12
-rw-r--r--drivers/clk/rockchip/clk_rk322x.c9
-rw-r--r--drivers/clk/rockchip/clk_rk3288.c12
-rw-r--r--drivers/clk/rockchip/clk_rk3308.c9
-rw-r--r--drivers/clk/rockchip/clk_rk3328.c9
-rw-r--r--drivers/clk/rockchip/clk_rk3368.c13
-rw-r--r--drivers/clk/rockchip/clk_rk3399.c23
-rw-r--r--drivers/clk/rockchip/clk_rv1108.c9
-rw-r--r--drivers/clk/sifive/fu540-prci.c4
-rw-r--r--drivers/clk/sunxi/clk_a10.c2
-rw-r--r--drivers/clk/sunxi/clk_a10s.c2
-rw-r--r--drivers/clk/sunxi/clk_a23.c2
-rw-r--r--drivers/clk/sunxi/clk_a31.c2
-rw-r--r--drivers/clk/sunxi/clk_a64.c2
-rw-r--r--drivers/clk/sunxi/clk_a80.c2
-rw-r--r--drivers/clk/sunxi/clk_a83t.c2
-rw-r--r--drivers/clk/sunxi/clk_h3.c2
-rw-r--r--drivers/clk/sunxi/clk_h6.c2
-rw-r--r--drivers/clk/sunxi/clk_r40.c2
-rw-r--r--drivers/clk/sunxi/clk_v3s.c2
-rw-r--r--drivers/clk/ti/Kconfig43
-rw-r--r--drivers/clk/ti/Makefile13
-rw-r--r--drivers/clk/ti/clk-am3-dpll-x2.c79
-rw-r--r--drivers/clk/ti/clk-am3-dpll.c268
-rw-r--r--drivers/clk/ti/clk-ctrl.c154
-rw-r--r--drivers/clk/ti/clk-divider.c381
-rw-r--r--drivers/clk/ti/clk-gate.c93
-rw-r--r--drivers/clk/ti/clk-mux.c253
-rw-r--r--drivers/clk/ti/clk-sci.c (renamed from drivers/clk/clk-ti-sci.c)2
-rw-r--r--drivers/clk/ti/clk.c34
-rw-r--r--drivers/clk/ti/clk.h13
-rw-r--r--drivers/clk/ti/omap4-cm.c22
-rw-r--r--drivers/clk/uniphier/clk-uniphier-core.c2
97 files changed, 1680 insertions, 283 deletions
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 4dfbad7986..db06f276ec 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -98,14 +98,6 @@ config CLK_STM32F
This clock driver adds support for RCC clock management
for STM32F4 and STM32F7 SoCs.
-config CLK_TI_SCI
- bool "TI System Control Interface (TI SCI) clock driver"
- depends on CLK && TI_SCI_PROTOCOL && OF_CONTROL
- help
- This enables the clock driver support over TI System Control Interface
- available on some new TI's SoCs. If you wish to use clock resources
- managed by the TI System Controller, say Y here. Otherwise, say N.
-
config CLK_HSDK
bool "Enable cgu clock driver for HSDK boards"
depends on CLK && TARGET_HSDK
@@ -179,6 +171,7 @@ source "drivers/clk/renesas/Kconfig"
source "drivers/clk/sunxi/Kconfig"
source "drivers/clk/sifive/Kconfig"
source "drivers/clk/tegra/Kconfig"
+source "drivers/clk/ti/Kconfig"
source "drivers/clk/uniphier/Kconfig"
config ICS8N3QV01
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d1e295ac7c..f8383e523d 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_COMPOSITE_CCF) += clk-composite.o
obj-y += analogbits/
obj-y += imx/
obj-y += tegra/
+obj-y += ti/
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
@@ -47,6 +48,5 @@ obj-$(CONFIG_SANDBOX) += clk_sandbox.o
obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
obj-$(CONFIG_SANDBOX_CLK_CCF) += clk_sandbox_ccf.o
obj-$(CONFIG_STM32H7) += clk_stm32h7.o
-obj-$(CONFIG_CLK_TI_SCI) += clk-ti-sci.o
obj-$(CONFIG_CLK_VERSAL) += clk_versal.o
obj-$(CONFIG_CLK_CDCE9XX) += clk-cdce9xx.o
diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c
index a539889d5b..bac1d98e19 100644
--- a/drivers/clk/altera/clk-agilex.c
+++ b/drivers/clk/altera/clk-agilex.c
@@ -17,7 +17,7 @@
DECLARE_GLOBAL_DATA_PTR;
-struct socfpga_clk_platdata {
+struct socfpga_clk_plat {
void __iomem *regs;
};
@@ -25,20 +25,20 @@ struct socfpga_clk_platdata {
* function to write the bypass register which requires a poll of the
* busy bit
*/
-static void clk_write_bypass_mainpll(struct socfpga_clk_platdata *plat, u32 val)
+static void clk_write_bypass_mainpll(struct socfpga_clk_plat *plat, u32 val)
{
CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS);
cm_wait_for_fsm();
}
-static void clk_write_bypass_perpll(struct socfpga_clk_platdata *plat, u32 val)
+static void clk_write_bypass_perpll(struct socfpga_clk_plat *plat, u32 val)
{
CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS);
cm_wait_for_fsm();
}
/* function to write the ctrl register which requires a poll of the busy bit */
-static void clk_write_ctrl(struct socfpga_clk_platdata *plat, u32 val)
+static void clk_write_ctrl(struct socfpga_clk_plat *plat, u32 val)
{
CM_REG_WRITEL(plat, val, CLKMGR_CTRL);
cm_wait_for_fsm();
@@ -108,7 +108,7 @@ static const struct {
},
};
-static int membus_wait_for_req(struct socfpga_clk_platdata *plat, u32 pll,
+static int membus_wait_for_req(struct socfpga_clk_plat *plat, u32 pll,
int timeout)
{
int cnt = 0;
@@ -133,7 +133,7 @@ static int membus_wait_for_req(struct socfpga_clk_platdata *plat, u32 pll,
return 0;
}
-static int membus_write_pll(struct socfpga_clk_platdata *plat, u32 pll,
+static int membus_write_pll(struct socfpga_clk_plat *plat, u32 pll,
u32 addr_offset, u32 wdat, int timeout)
{
u32 addr;
@@ -154,7 +154,7 @@ static int membus_write_pll(struct socfpga_clk_platdata *plat, u32 pll,
return membus_wait_for_req(plat, pll, timeout);
}
-static int membus_read_pll(struct socfpga_clk_platdata *plat, u32 pll,
+static int membus_read_pll(struct socfpga_clk_plat *plat, u32 pll,
u32 addr_offset, u32 *rdata, int timeout)
{
u32 addr;
@@ -184,7 +184,7 @@ static int membus_read_pll(struct socfpga_clk_platdata *plat, u32 pll,
return 0;
}
-static void membus_pll_configs(struct socfpga_clk_platdata *plat, u32 pll)
+static void membus_pll_configs(struct socfpga_clk_plat *plat, u32 pll)
{
int i;
u32 rdata;
@@ -236,7 +236,7 @@ static u32 calc_vocalib_pll(u32 pllm, u32 pllglob)
static void clk_basic_init(struct udevice *dev,
const struct cm_config * const cfg)
{
- struct socfpga_clk_platdata *plat = dev_get_platdata(dev);
+ struct socfpga_clk_plat *plat = dev_get_plat(dev);
u32 vcocalib;
if (!cfg)
@@ -342,7 +342,7 @@ static void clk_basic_init(struct udevice *dev,
CM_REG_READL(plat, CLKMGR_CTRL) & ~CLKMGR_CTRL_BOOTMODE);
}
-static u64 clk_get_vco_clk_hz(struct socfpga_clk_platdata *plat,
+static u64 clk_get_vco_clk_hz(struct socfpga_clk_plat *plat,
u32 pllglob_reg, u32 pllm_reg)
{
u64 fref, arefdiv, mdiv, reg, vco;
@@ -375,26 +375,26 @@ static u64 clk_get_vco_clk_hz(struct socfpga_clk_platdata *plat,
return vco;
}
-static u64 clk_get_main_vco_clk_hz(struct socfpga_clk_platdata *plat)
+static u64 clk_get_main_vco_clk_hz(struct socfpga_clk_plat *plat)
{
return clk_get_vco_clk_hz(plat, CLKMGR_MAINPLL_PLLGLOB,
CLKMGR_MAINPLL_PLLM);
}
-static u64 clk_get_per_vco_clk_hz(struct socfpga_clk_platdata *plat)
+static u64 clk_get_per_vco_clk_hz(struct socfpga_clk_plat *plat)
{
return clk_get_vco_clk_hz(plat, CLKMGR_PERPLL_PLLGLOB,
CLKMGR_PERPLL_PLLM);
}
-static u32 clk_get_5_1_clk_src(struct socfpga_clk_platdata *plat, u64 reg)
+static u32 clk_get_5_1_clk_src(struct socfpga_clk_plat *plat, u64 reg)
{
u32 clksrc = CM_REG_READL(plat, reg);
return (clksrc & CLKMGR_CLKSRC_MASK) >> CLKMGR_CLKSRC_OFFSET;
}
-static u64 clk_get_clksrc_hz(struct socfpga_clk_platdata *plat, u32 clksrc_reg,
+static u64 clk_get_clksrc_hz(struct socfpga_clk_plat *plat, u32 clksrc_reg,
u32 main_reg, u32 per_reg)
{
u64 clock;
@@ -431,7 +431,7 @@ static u64 clk_get_clksrc_hz(struct socfpga_clk_platdata *plat, u32 clksrc_reg,
return clock;
}
-static u64 clk_get_mpu_clk_hz(struct socfpga_clk_platdata *plat)
+static u64 clk_get_mpu_clk_hz(struct socfpga_clk_plat *plat)
{
u64 clock = clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_MPUCLK,
CLKMGR_MAINPLL_PLLC0,
@@ -443,14 +443,14 @@ static u64 clk_get_mpu_clk_hz(struct socfpga_clk_platdata *plat)
return clock;
}
-static u32 clk_get_l3_main_clk_hz(struct socfpga_clk_platdata *plat)
+static u32 clk_get_l3_main_clk_hz(struct socfpga_clk_plat *plat)
{
return clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_NOCCLK,
CLKMGR_MAINPLL_PLLC1,
CLKMGR_PERPLL_PLLC1);
}
-static u32 clk_get_l4_main_clk_hz(struct socfpga_clk_platdata *plat)
+static u32 clk_get_l4_main_clk_hz(struct socfpga_clk_plat *plat)
{
u64 clock = clk_get_l3_main_clk_hz(plat);
@@ -461,7 +461,7 @@ static u32 clk_get_l4_main_clk_hz(struct socfpga_clk_platdata *plat)
return clock;
}
-static u32 clk_get_sdmmc_clk_hz(struct socfpga_clk_platdata *plat)
+static u32 clk_get_sdmmc_clk_hz(struct socfpga_clk_plat *plat)
{
u64 clock = clk_get_clksrc_hz(plat, CLKMGR_ALTR_SDMMCCTR,
CLKMGR_MAINPLL_PLLC3,
@@ -473,7 +473,7 @@ static u32 clk_get_sdmmc_clk_hz(struct socfpga_clk_platdata *plat)
return clock / 4;
}
-static u32 clk_get_l4_sp_clk_hz(struct socfpga_clk_platdata *plat)
+static u32 clk_get_l4_sp_clk_hz(struct socfpga_clk_plat *plat)
{
u64 clock = clk_get_l3_main_clk_hz(plat);
@@ -484,7 +484,7 @@ static u32 clk_get_l4_sp_clk_hz(struct socfpga_clk_platdata *plat)
return clock;
}
-static u32 clk_get_l4_mp_clk_hz(struct socfpga_clk_platdata *plat)
+static u32 clk_get_l4_mp_clk_hz(struct socfpga_clk_plat *plat)
{
u64 clock = clk_get_l3_main_clk_hz(plat);
@@ -495,7 +495,7 @@ static u32 clk_get_l4_mp_clk_hz(struct socfpga_clk_platdata *plat)
return clock;
}
-static u32 clk_get_l4_sys_free_clk_hz(struct socfpga_clk_platdata *plat)
+static u32 clk_get_l4_sys_free_clk_hz(struct socfpga_clk_plat *plat)
{
if (CM_REG_READL(plat, CLKMGR_STAT) & CLKMGR_STAT_BOOTMODE)
return clk_get_l3_main_clk_hz(plat) / 2;
@@ -503,7 +503,7 @@ static u32 clk_get_l4_sys_free_clk_hz(struct socfpga_clk_platdata *plat)
return clk_get_l3_main_clk_hz(plat) / 4;
}
-static u32 clk_get_emac_clk_hz(struct socfpga_clk_platdata *plat, u32 emac_id)
+static u32 clk_get_emac_clk_hz(struct socfpga_clk_plat *plat, u32 emac_id)
{
bool emacsel_a;
u32 ctl;
@@ -585,7 +585,7 @@ static u32 clk_get_emac_clk_hz(struct socfpga_clk_platdata *plat, u32 emac_id)
static ulong socfpga_clk_get_rate(struct clk *clk)
{
- struct socfpga_clk_platdata *plat = dev_get_platdata(clk->dev);
+ struct socfpga_clk_plat *plat = dev_get_plat(clk->dev);
switch (clk->id) {
case AGILEX_MPU_CLK:
@@ -628,9 +628,9 @@ static int socfpga_clk_probe(struct udevice *dev)
return 0;
}
-static int socfpga_clk_ofdata_to_platdata(struct udevice *dev)
+static int socfpga_clk_of_to_plat(struct udevice *dev)
{
- struct socfpga_clk_platdata *plat = dev_get_platdata(dev);
+ struct socfpga_clk_plat *plat = dev_get_plat(dev);
fdt_addr_t addr;
addr = dev_read_addr(dev);
@@ -657,6 +657,6 @@ U_BOOT_DRIVER(socfpga_agilex_clk) = {
.of_match = socfpga_clk_match,
.ops = &socfpga_clk_ops,
.probe = socfpga_clk_probe,
- .ofdata_to_platdata = socfpga_clk_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct socfpga_clk_platdata),
+ .of_to_plat = socfpga_clk_of_to_plat,
+ .plat_auto = sizeof(struct socfpga_clk_plat),
};
diff --git a/drivers/clk/altera/clk-arria10.c b/drivers/clk/altera/clk-arria10.c
index 732ed4d79b..1812152d56 100644
--- a/drivers/clk/altera/clk-arria10.c
+++ b/drivers/clk/altera/clk-arria10.c
@@ -24,7 +24,7 @@ enum socfpga_a10_clk_type {
SOCFPGA_A10_CLK_UNKNOWN_CLK,
};
-struct socfpga_a10_clk_platdata {
+struct socfpga_a10_clk_plat {
enum socfpga_a10_clk_type type;
struct clk_bulk clks;
u32 regs;
@@ -43,7 +43,7 @@ struct socfpga_a10_clk_platdata {
static int socfpga_a10_clk_get_upstream(struct clk *clk, struct clk **upclk)
{
- struct socfpga_a10_clk_platdata *plat = dev_get_platdata(clk->dev);
+ struct socfpga_a10_clk_plat *plat = dev_get_plat(clk->dev);
u32 reg, maxval;
if (plat->clks.count == 0)
@@ -84,7 +84,7 @@ static int socfpga_a10_clk_get_upstream(struct clk *clk, struct clk **upclk)
static int socfpga_a10_clk_endisable(struct clk *clk, bool enable)
{
- struct socfpga_a10_clk_platdata *plat = dev_get_platdata(clk->dev);
+ struct socfpga_a10_clk_plat *plat = dev_get_plat(clk->dev);
struct clk *upclk = NULL;
int ret;
@@ -120,7 +120,7 @@ static int socfpga_a10_clk_disable(struct clk *clk)
static ulong socfpga_a10_clk_get_rate(struct clk *clk)
{
- struct socfpga_a10_clk_platdata *plat = dev_get_platdata(clk->dev);
+ struct socfpga_a10_clk_plat *plat = dev_get_plat(clk->dev);
struct clk *upclk = NULL;
ulong rate = 0, reg, numer, denom;
int ret;
@@ -190,7 +190,7 @@ static struct clk_ops socfpga_a10_clk_ops = {
*/
static void socfpga_a10_handoff_workaround(struct udevice *dev)
{
- struct socfpga_a10_clk_platdata *plat = dev_get_platdata(dev);
+ struct socfpga_a10_clk_plat *plat = dev_get_plat(dev);
const void *fdt = gd->fdt_blob;
struct clk_bulk *bulk = &plat->clks;
int i, ret, offset = dev_of_offset(dev);
@@ -274,8 +274,8 @@ static int socfpga_a10_clk_bind(struct udevice *dev)
static int socfpga_a10_clk_probe(struct udevice *dev)
{
- struct socfpga_a10_clk_platdata *plat = dev_get_platdata(dev);
- struct socfpga_a10_clk_platdata *pplat;
+ struct socfpga_a10_clk_plat *plat = dev_get_plat(dev);
+ struct socfpga_a10_clk_plat *pplat;
struct udevice *pdev;
const void *fdt = gd->fdt_blob;
int offset = dev_of_offset(dev);
@@ -291,7 +291,7 @@ static int socfpga_a10_clk_probe(struct udevice *dev)
if (!pdev)
return -ENODEV;
- pplat = dev_get_platdata(pdev);
+ pplat = dev_get_plat(pdev);
if (!pplat)
return -EINVAL;
@@ -319,9 +319,9 @@ static int socfpga_a10_clk_probe(struct udevice *dev)
return 0;
}
-static int socfpga_a10_ofdata_to_platdata(struct udevice *dev)
+static int socfpga_a10_of_to_plat(struct udevice *dev)
{
- struct socfpga_a10_clk_platdata *plat = dev_get_platdata(dev);
+ struct socfpga_a10_clk_plat *plat = dev_get_plat(dev);
unsigned int divreg[3], gatereg[2];
int ret;
@@ -357,7 +357,7 @@ U_BOOT_DRIVER(socfpga_a10_clk) = {
.ops = &socfpga_a10_clk_ops,
.bind = socfpga_a10_clk_bind,
.probe = socfpga_a10_clk_probe,
- .ofdata_to_platdata = socfpga_a10_ofdata_to_platdata,
+ .of_to_plat = socfpga_a10_of_to_plat,
- .platdata_auto_alloc_size = sizeof(struct socfpga_a10_clk_platdata),
+ .plat_auto = sizeof(struct socfpga_a10_clk_plat),
};
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index aab7d14deb..a090671625 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -491,7 +491,7 @@ struct clk_ops ast2500_clk_ops = {
.enable = ast2500_clk_enable,
};
-static int ast2500_clk_ofdata_to_platdata(struct udevice *dev)
+static int ast2500_clk_of_to_plat(struct udevice *dev)
{
struct ast2500_clk_priv *priv = dev_get_priv(dev);
@@ -523,8 +523,8 @@ U_BOOT_DRIVER(aspeed_ast2500_scu) = {
.name = "aspeed_ast2500_scu",
.id = UCLASS_CLK,
.of_match = ast2500_clk_ids,
- .priv_auto_alloc_size = sizeof(struct ast2500_clk_priv),
+ .priv_auto = sizeof(struct ast2500_clk_priv),
.ops = &ast2500_clk_ops,
.bind = ast2500_clk_bind,
- .ofdata_to_platdata = ast2500_clk_ofdata_to_platdata,
+ .of_to_plat = ast2500_clk_of_to_plat,
};
diff --git a/drivers/clk/at91/compat.c b/drivers/clk/at91/compat.c
index 9563285674..e514f26656 100644
--- a/drivers/clk/at91/compat.c
+++ b/drivers/clk/at91/compat.c
@@ -21,7 +21,7 @@
DECLARE_GLOBAL_DATA_PTR;
-struct pmc_platdata {
+struct pmc_plat {
struct at91_pmc *reg_base;
struct regmap *regmap_sfr;
};
@@ -45,7 +45,7 @@ U_BOOT_DRIVER(at91_pmc) = {
static int at91_pmc_core_probe(struct udevice *dev)
{
- struct pmc_platdata *plat = dev_get_platdata(dev);
+ struct pmc_plat *plat = dev_get_plat(dev);
dev = dev_get_parent(dev);
@@ -62,34 +62,30 @@ static int at91_pmc_core_probe(struct udevice *dev)
*/
int at91_clk_sub_device_bind(struct udevice *dev, const char *drv_name)
{
- const void *fdt = gd->fdt_blob;
- int offset = dev_of_offset(dev);
+ ofnode parent = dev_ofnode(dev);
+ ofnode node;
bool pre_reloc_only = !(gd->flags & GD_FLG_RELOC);
const char *name;
int ret;
- for (offset = fdt_first_subnode(fdt, offset);
- offset > 0;
- offset = fdt_next_subnode(fdt, offset)) {
- if (pre_reloc_only &&
- !ofnode_pre_reloc(offset_to_ofnode(offset)))
+ ofnode_for_each_subnode(node, parent) {
+ if (pre_reloc_only && !ofnode_pre_reloc(node))
continue;
/*
* If this node has "compatible" property, this is not
* a clock sub-node, but a normal device. skip.
*/
- fdt_get_property(fdt, offset, "compatible", &ret);
- if (ret >= 0)
+ if (ofnode_read_prop(node, "compatible", NULL))
continue;
if (ret != -FDT_ERR_NOTFOUND)
return ret;
- name = fdt_get_name(fdt, offset, NULL);
+ name = ofnode_get_name(node);
if (!name)
return -EINVAL;
- ret = device_bind_driver_to_node(dev, drv_name, name,
- offset_to_ofnode(offset), NULL);
+ ret = device_bind_driver_to_node(dev, drv_name, name, node,
+ NULL);
if (ret)
return ret;
}
@@ -119,7 +115,7 @@ int at91_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
int at91_clk_probe(struct udevice *dev)
{
struct udevice *dev_periph_container, *dev_pmc;
- struct pmc_platdata *plat = dev_get_platdata(dev);
+ struct pmc_plat *plat = dev_get_plat(dev);
dev_periph_container = dev_get_parent(dev);
dev_pmc = dev_get_parent(dev_periph_container);
@@ -195,7 +191,7 @@ U_BOOT_DRIVER(at91_master_clk) = {
/* Main osc clock specific code. */
static int main_osc_clk_enable(struct clk *clk)
{
- struct pmc_platdata *plat = dev_get_platdata(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
if (readl(&pmc->sr) & AT91_PMC_MOSCSELS)
@@ -229,14 +225,14 @@ U_BOOT_DRIVER(at91sam9x5_main_osc_clk) = {
.id = UCLASS_CLK,
.of_match = main_osc_clk_match,
.probe = main_osc_clk_probe,
- .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
+ .plat_auto = sizeof(struct pmc_plat),
.ops = &main_osc_clk_ops,
};
/* PLLA clock specific code. */
static int plla_clk_enable(struct clk *clk)
{
- struct pmc_platdata *plat = dev_get_platdata(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
if (readl(&pmc->sr) & AT91_PMC_LOCKA)
@@ -270,7 +266,7 @@ U_BOOT_DRIVER(at91_plla_clk) = {
.id = UCLASS_CLK,
.of_match = plla_clk_match,
.probe = plla_clk_probe,
- .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
+ .plat_auto = sizeof(struct pmc_plat),
.ops = &plla_clk_ops,
};
@@ -282,7 +278,7 @@ static int at91_plladiv_clk_enable(struct clk *clk)
static ulong at91_plladiv_clk_get_rate(struct clk *clk)
{
- struct pmc_platdata *plat = dev_get_platdata(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
struct clk source;
ulong clk_rate;
@@ -301,7 +297,7 @@ static ulong at91_plladiv_clk_get_rate(struct clk *clk)
static ulong at91_plladiv_clk_set_rate(struct clk *clk, ulong rate)
{
- struct pmc_platdata *plat = dev_get_platdata(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
struct clk source;
ulong parent_rate;
@@ -344,7 +340,7 @@ U_BOOT_DRIVER(at91_plladiv_clk) = {
.id = UCLASS_CLK,
.of_match = at91_plladiv_clk_match,
.probe = at91_plladiv_clk_probe,
- .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
+ .plat_auto = sizeof(struct pmc_plat),
.ops = &at91_plladiv_clk_ops,
};
@@ -405,7 +401,7 @@ static ulong system_clk_set_rate(struct clk *clk, ulong rate)
static int system_clk_enable(struct clk *clk)
{
- struct pmc_platdata *plat = dev_get_platdata(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
u32 mask;
@@ -441,7 +437,7 @@ U_BOOT_DRIVER(system_clk) = {
.name = "system-clk",
.id = UCLASS_CLK,
.probe = at91_clk_probe,
- .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
+ .plat_auto = sizeof(struct pmc_plat),
.ops = &system_clk_ops,
};
@@ -487,7 +483,7 @@ U_BOOT_DRIVER(sam9x5_periph_clk) = {
static int periph_clk_enable(struct clk *clk)
{
- struct pmc_platdata *plat = dev_get_platdata(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
enum periph_clk_type clk_type;
void *addr;
@@ -540,7 +536,7 @@ static struct clk_ops periph_clk_ops = {
U_BOOT_DRIVER(clk_periph) = {
.name = "periph-clk",
.id = UCLASS_CLK,
- .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
+ .plat_auto = sizeof(struct pmc_plat),
.probe = at91_clk_probe,
.ops = &periph_clk_ops,
};
@@ -556,7 +552,7 @@ U_BOOT_DRIVER(clk_periph) = {
static int utmi_clk_enable(struct clk *clk)
{
- struct pmc_platdata *plat = dev_get_platdata(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
struct clk clk_dev;
ulong clk_rate;
@@ -642,9 +638,9 @@ static struct clk_ops utmi_clk_ops = {
.get_rate = utmi_clk_get_rate,
};
-static int utmi_clk_ofdata_to_platdata(struct udevice *dev)
+static int utmi_clk_of_to_plat(struct udevice *dev)
{
- struct pmc_platdata *plat = dev_get_platdata(dev);
+ struct pmc_plat *plat = dev_get_plat(dev);
struct udevice *syscon;
uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
@@ -671,8 +667,8 @@ U_BOOT_DRIVER(at91sam9x5_utmi_clk) = {
.id = UCLASS_CLK,
.of_match = utmi_clk_match,
.probe = utmi_clk_probe,
- .ofdata_to_platdata = utmi_clk_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
+ .of_to_plat = utmi_clk_of_to_plat,
+ .plat_auto = sizeof(struct pmc_plat),
.ops = &utmi_clk_ops,
};
@@ -685,7 +681,7 @@ U_BOOT_DRIVER(at91sam9x5_utmi_clk) = {
static ulong sama5d4_h32mx_clk_get_rate(struct clk *clk)
{
- struct pmc_platdata *plat = dev_get_platdata(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
ulong rate = gd->arch.mck_rate_hz;
@@ -717,7 +713,7 @@ U_BOOT_DRIVER(sama5d4_h32mx_clk) = {
.id = UCLASS_CLK,
.of_match = sama5d4_h32mx_clk_match,
.probe = sama5d4_h32mx_clk_probe,
- .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
+ .plat_auto = sizeof(struct pmc_plat),
.ops = &sama5d4_h32mx_clk_ops,
};
@@ -758,7 +754,7 @@ struct generic_clk_priv {
static ulong generic_clk_get_rate(struct clk *clk)
{
- struct pmc_platdata *plat = dev_get_platdata(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
struct clk parent;
ulong clk_rate;
@@ -786,7 +782,7 @@ static ulong generic_clk_get_rate(struct clk *clk)
static ulong generic_clk_set_rate(struct clk *clk, ulong rate)
{
- struct pmc_platdata *plat = dev_get_platdata(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
struct generic_clk_priv *priv = dev_get_priv(clk->dev);
struct clk parent, best_parent;
@@ -857,7 +853,7 @@ static struct clk_ops generic_clk_ops = {
.set_rate = generic_clk_set_rate,
};
-static int generic_clk_ofdata_to_platdata(struct udevice *dev)
+static int generic_clk_of_to_plat(struct udevice *dev)
{
struct generic_clk_priv *priv = dev_get_priv(dev);
u32 cells[GENERATED_SOURCE_MAX];
@@ -879,9 +875,9 @@ U_BOOT_DRIVER(generic_clk) = {
.name = "generic-clk",
.id = UCLASS_CLK,
.probe = at91_clk_probe,
- .ofdata_to_platdata = generic_clk_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct generic_clk_priv),
- .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
+ .of_to_plat = generic_clk_of_to_plat,
+ .priv_auto = sizeof(struct generic_clk_priv),
+ .plat_auto = sizeof(struct pmc_plat),
.ops = &generic_clk_ops,
};
@@ -899,7 +895,7 @@ struct at91_usb_clk_priv {
static ulong at91_usb_clk_get_rate(struct clk *clk)
{
- struct pmc_platdata *plat = dev_get_platdata(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
struct clk source;
u32 tmp, usbdiv;
@@ -920,7 +916,7 @@ static ulong at91_usb_clk_get_rate(struct clk *clk)
static ulong at91_usb_clk_set_rate(struct clk *clk, ulong rate)
{
- struct pmc_platdata *plat = dev_get_platdata(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
struct at91_usb_clk_priv *priv = dev_get_priv(clk->dev);
struct clk source, best_source;
@@ -981,7 +977,7 @@ static struct clk_ops at91_usb_clk_ops = {
.set_rate = at91_usb_clk_set_rate,
};
-static int at91_usb_clk_ofdata_to_platdata(struct udevice *dev)
+static int at91_usb_clk_of_to_plat(struct udevice *dev)
{
struct at91_usb_clk_priv *priv = dev_get_priv(dev);
u32 cells[AT91_USB_CLK_SOURCE_MAX];
@@ -1015,9 +1011,9 @@ U_BOOT_DRIVER(at91_usb_clk) = {
.id = UCLASS_CLK,
.of_match = at91_usb_clk_match,
.probe = at91_usb_clk_probe,
- .ofdata_to_platdata = at91_usb_clk_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct at91_usb_clk_priv),
- .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
+ .of_to_plat = at91_usb_clk_of_to_plat,
+ .priv_auto = sizeof(struct at91_usb_clk_priv),
+ .plat_auto = sizeof(struct pmc_plat),
.ops = &at91_usb_clk_ops,
};
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index dd62dc5510..34ce611a98 100644
--- a/drivers/clk/at91/sckc.c
+++ b/drivers/clk/at91/sckc.c
@@ -165,7 +165,7 @@ U_BOOT_DRIVER(at91_sckc) = {
.name = UBOOT_DM_CLK_AT91_SCKC,
.id = UCLASS_CLK,
.of_match = sam9x60_sckc_ids,
- .priv_auto_alloc_size = sizeof(struct sam9x60_sckc) * 2,
+ .priv_auto = sizeof(struct sam9x60_sckc) * 2,
.ops = &sam9x60_sckc_ops,
.probe = at91_sam9x60_sckc_probe,
.flags = DM_FLAG_PRE_RELOC,
diff --git a/drivers/clk/clk-cdce9xx.c b/drivers/clk/clk-cdce9xx.c
index fd47872ab9..6634b7b799 100644
--- a/drivers/clk/clk-cdce9xx.c
+++ b/drivers/clk/clk-cdce9xx.c
@@ -251,6 +251,6 @@ U_BOOT_DRIVER(cdce9xx_clk) = {
.id = UCLASS_CLK,
.of_match = cdce9xx_clk_of_match,
.probe = cdce9xx_clk_probe,
- .priv_auto_alloc_size = sizeof(struct cdce9xx_clk_data),
+ .priv_auto = sizeof(struct cdce9xx_clk_data),
.ops = &cdce9xx_clk_ops,
};
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 8f59d7fb72..9df50a5e72 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -28,8 +28,8 @@
#define UBOOT_DM_CLK_CCF_DIVIDER "ccf_clk_divider"
-static unsigned int _get_table_div(const struct clk_div_table *table,
- unsigned int val)
+unsigned int clk_divider_get_table_div(const struct clk_div_table *table,
+ unsigned int val)
{
const struct clk_div_table *clkt;
@@ -49,7 +49,7 @@ static unsigned int _get_div(const struct clk_div_table *table,
if (flags & CLK_DIVIDER_MAX_AT_ZERO)
return val ? val : clk_div_mask(width) + 1;
if (table)
- return _get_table_div(table, val);
+ return clk_divider_get_table_div(table, val);
return val + 1;
}
@@ -89,8 +89,8 @@ static ulong clk_divider_recalc_rate(struct clk *clk)
divider->flags, divider->width);
}
-static bool _is_valid_table_div(const struct clk_div_table *table,
- unsigned int div)
+bool clk_divider_is_valid_table_div(const struct clk_div_table *table,
+ unsigned int div)
{
const struct clk_div_table *clkt;
@@ -100,18 +100,18 @@ static bool _is_valid_table_div(const struct clk_div_table *table,
return false;
}
-static bool _is_valid_div(const struct clk_div_table *table, unsigned int div,
- unsigned long flags)
+bool clk_divider_is_valid_div(const struct clk_div_table *table,
+ unsigned int div, unsigned long flags)
{
if (flags & CLK_DIVIDER_POWER_OF_TWO)
return is_power_of_2(div);
if (table)
- return _is_valid_table_div(table, div);
+ return clk_divider_is_valid_table_div(table, div);
return true;
}
-static unsigned int _get_table_val(const struct clk_div_table *table,
- unsigned int div)
+unsigned int clk_divider_get_table_val(const struct clk_div_table *table,
+ unsigned int div)
{
const struct clk_div_table *clkt;
@@ -131,7 +131,7 @@ static unsigned int _get_val(const struct clk_div_table *table,
if (flags & CLK_DIVIDER_MAX_AT_ZERO)
return (div == clk_div_mask(width) + 1) ? 0 : div;
if (table)
- return _get_table_val(table, div);
+ return clk_divider_get_table_val(table, div);
return div - 1;
}
int divider_get_val(unsigned long rate, unsigned long parent_rate,
@@ -142,7 +142,7 @@ int divider_get_val(unsigned long rate, unsigned long parent_rate,
div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
- if (!_is_valid_div(table, div, flags))
+ if (!clk_divider_is_valid_div(table, div, flags))
return -EINVAL;
value = _get_val(table, div, flags, width);
diff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c
index 3eb93a55fc..449b430e23 100644
--- a/drivers/clk/clk-hsdk-cgu.c
+++ b/drivers/clk/clk-hsdk-cgu.c
@@ -774,6 +774,6 @@ U_BOOT_DRIVER(hsdk_cgu_clk) = {
.id = UCLASS_CLK,
.of_match = hsdk_cgu_clk_id,
.probe = hsdk_cgu_clk_probe,
- .priv_auto_alloc_size = sizeof(struct hsdk_cgu_clk),
+ .priv_auto = sizeof(struct hsdk_cgu_clk),
.ops = &hsdk_cgu_ops,
};
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index ac954a34d2..b75056718b 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -345,7 +345,7 @@ int clk_set_defaults(struct udevice *dev, int stage)
{
int ret;
- if (!dev_of_valid(dev))
+ if (!dev_has_ofnode(dev))
return 0;
/* If this not in SPL and pre-reloc state, don't take any action. */
@@ -523,6 +523,21 @@ long long clk_get_parent_rate(struct clk *clk)
return pclk->rate;
}
+ulong clk_round_rate(struct clk *clk, ulong rate)
+{
+ const struct clk_ops *ops;
+
+ debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
+ if (!clk_valid(clk))
+ return 0;
+
+ ops = clk_dev_ops(clk->dev);
+ if (!ops->round_rate)
+ return -ENOSYS;
+
+ return ops->round_rate(clk, rate);
+}
+
ulong clk_set_rate(struct clk *clk, ulong rate)
{
const struct clk_ops *ops;
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 319808d433..1efb7fe9f3 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -36,7 +36,7 @@ int clk_register(struct clk *clk, const char *drv_name,
return -ENOENT;
}
- ret = device_bind(parent, drv, name, NULL, -1, &clk->dev);
+ ret = device_bind(parent, drv, name, NULL, ofnode_null(), &clk->dev);
if (ret) {
printf("%s: CLK: %s driver bind error [%d]!\n", __func__, name,
ret);
@@ -44,8 +44,10 @@ int clk_register(struct clk *clk, const char *drv_name,
}
clk->enable_count = 0;
+
/* Store back pointer to clk from udevice */
- clk->dev->uclass_priv = clk;
+ /* FIXME: This is not allowed...should be allocated by driver model */
+ dev_set_uclass_priv(clk->dev, clk);
return 0;
}
@@ -65,7 +67,7 @@ const char *clk_hw_get_name(const struct clk *hw)
bool clk_dev_binded(struct clk *clk)
{
- if (clk->dev && (clk->dev->flags & DM_FLAG_BOUND))
+ if (clk->dev && (dev_get_flags(clk->dev) & DM_FLAG_BOUND))
return true;
return false;
diff --git a/drivers/clk/clk_bcm6345.c b/drivers/clk/clk_bcm6345.c
index b850b9fc06..8c22ed2f43 100644
--- a/drivers/clk/clk_bcm6345.c
+++ b/drivers/clk/clk_bcm6345.c
@@ -70,5 +70,5 @@ U_BOOT_DRIVER(clk_bcm6345) = {
.of_match = bcm6345_clk_ids,
.ops = &bcm6345_clk_ops,
.probe = bcm63xx_clk_probe,
- .priv_auto_alloc_size = sizeof(struct bcm6345_clk_priv),
+ .priv_auto = sizeof(struct bcm6345_clk_priv),
};
diff --git a/drivers/clk/clk_boston.c b/drivers/clk/clk_boston.c
index 2318dcf6a4..2e81777b70 100644
--- a/drivers/clk/clk_boston.c
+++ b/drivers/clk/clk_boston.c
@@ -28,7 +28,7 @@ static uint32_t ext_field(uint32_t val, uint32_t mask)
static ulong clk_boston_get_rate(struct clk *clk)
{
- struct clk_boston *state = dev_get_platdata(clk->dev);
+ struct clk_boston *state = dev_get_plat(clk->dev);
uint32_t in_rate, mul, div;
uint mmcmdiv;
int err;
@@ -58,9 +58,9 @@ const struct clk_ops clk_boston_ops = {
.get_rate = clk_boston_get_rate,
};
-static int clk_boston_ofdata_to_platdata(struct udevice *dev)
+static int clk_boston_of_to_plat(struct udevice *dev)
{
- struct clk_boston *state = dev_get_platdata(dev);
+ struct clk_boston *state = dev_get_plat(dev);
struct udevice *syscon;
int err;
@@ -91,7 +91,7 @@ U_BOOT_DRIVER(clk_boston) = {
.name = "boston_clock",
.id = UCLASS_CLK,
.of_match = clk_boston_match,
- .ofdata_to_platdata = clk_boston_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct clk_boston),
+ .of_to_plat = clk_boston_of_to_plat,
+ .plat_auto = sizeof(struct clk_boston),
.ops = &clk_boston_ops,
};
diff --git a/drivers/clk/clk_fixed_factor.c b/drivers/clk/clk_fixed_factor.c
index cf9c4ae367..e51f94a937 100644
--- a/drivers/clk/clk_fixed_factor.c
+++ b/drivers/clk/clk_fixed_factor.c
@@ -18,7 +18,7 @@ struct clk_fixed_factor {
};
#define to_clk_fixed_factor(dev) \
- ((struct clk_fixed_factor *)dev_get_platdata(dev))
+ ((struct clk_fixed_factor *)dev_get_plat(dev))
static ulong clk_fixed_factor_get_rate(struct clk *clk)
{
@@ -38,7 +38,7 @@ const struct clk_ops clk_fixed_factor_ops = {
.get_rate = clk_fixed_factor_get_rate,
};
-static int clk_fixed_factor_ofdata_to_platdata(struct udevice *dev)
+static int clk_fixed_factor_of_to_plat(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
int err;
@@ -66,7 +66,7 @@ U_BOOT_DRIVER(clk_fixed_factor) = {
.name = "fixed_factor_clock",
.id = UCLASS_CLK,
.of_match = clk_fixed_factor_match,
- .ofdata_to_platdata = clk_fixed_factor_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct clk_fixed_factor),
+ .of_to_plat = clk_fixed_factor_of_to_plat,
+ .plat_auto = sizeof(struct clk_fixed_factor),
.ops = &clk_fixed_factor_ops,
};
diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c
index f86b4a0e92..3c5a83c523 100644
--- a/drivers/clk/clk_fixed_rate.c
+++ b/drivers/clk/clk_fixed_rate.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
+#include <dm/device-internal.h>
#include <linux/clk-provider.h>
static ulong clk_fixed_rate_get_rate(struct clk *clk)
@@ -24,7 +25,7 @@ const struct clk_ops clk_fixed_rate_ops = {
.enable = dummy_enable,
};
-static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev)
+static int clk_fixed_rate_of_to_plat(struct udevice *dev)
{
struct clk *clk = &to_clk_fixed_rate(dev)->clk;
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
@@ -32,7 +33,8 @@ static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev)
dev_read_u32_default(dev, "clock-frequency", 0);
#endif
/* Make fixed rate clock accessible from higher level struct clk */
- dev->uclass_priv = clk;
+ /* FIXME: This is not allowed */
+ dev_set_uclass_priv(dev, clk);
clk->dev = dev;
clk->enable_count = 0;
@@ -50,8 +52,8 @@ U_BOOT_DRIVER(fixed_clock) = {
.name = "fixed_clock",
.id = UCLASS_CLK,
.of_match = clk_fixed_rate_match,
- .ofdata_to_platdata = clk_fixed_rate_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct clk_fixed_rate),
+ .of_to_plat = clk_fixed_rate_of_to_plat,
+ .plat_auto = sizeof(struct clk_fixed_rate),
.ops = &clk_fixed_rate_ops,
.flags = DM_FLAG_PRE_RELOC,
};
diff --git a/drivers/clk/clk_octeon.c b/drivers/clk/clk_octeon.c
index fd559e05fc..ce274549da 100644
--- a/drivers/clk/clk_octeon.c
+++ b/drivers/clk/clk_octeon.c
@@ -68,5 +68,5 @@ U_BOOT_DRIVER(clk_octeon) = {
.of_match = octeon_clk_ids,
.ops = &octeon_clk_ops,
.probe = octeon_clk_probe,
- .priv_auto_alloc_size = sizeof(struct octeon_clk_priv),
+ .priv_auto = sizeof(struct octeon_clk_priv),
};
diff --git a/drivers/clk/clk_pic32.c b/drivers/clk/clk_pic32.c
index dc46de2a7c..5a10d4640d 100644
--- a/drivers/clk/clk_pic32.c
+++ b/drivers/clk/clk_pic32.c
@@ -423,5 +423,5 @@ U_BOOT_DRIVER(pic32_clk) = {
.of_match = pic32_clk_ids,
.ops = &pic32_pic32_clk_ops,
.probe = pic32_clk_probe,
- .priv_auto_alloc_size = sizeof(struct pic32_clk_priv),
+ .priv_auto = sizeof(struct pic32_clk_priv),
};
diff --git a/drivers/clk/clk_sandbox.c b/drivers/clk/clk_sandbox.c
index 0ff1b49633..b28b67b448 100644
--- a/drivers/clk/clk_sandbox.c
+++ b/drivers/clk/clk_sandbox.c
@@ -30,6 +30,22 @@ static ulong sandbox_clk_get_rate(struct clk *clk)
return priv->rate[clk->id];
}
+static ulong sandbox_clk_round_rate(struct clk *clk, ulong rate)
+{
+ struct sandbox_clk_priv *priv = dev_get_priv(clk->dev);
+
+ if (!priv->probed)
+ return -ENODEV;
+
+ if (clk->id >= SANDBOX_CLK_ID_COUNT)
+ return -EINVAL;
+
+ if (!rate)
+ return -EINVAL;
+
+ return rate;
+}
+
static ulong sandbox_clk_set_rate(struct clk *clk, ulong rate)
{
struct sandbox_clk_priv *priv = dev_get_priv(clk->dev);
@@ -103,6 +119,7 @@ static int sandbox_clk_free(struct clk *clk)
}
static struct clk_ops sandbox_clk_ops = {
+ .round_rate = sandbox_clk_round_rate,
.get_rate = sandbox_clk_get_rate,
.set_rate = sandbox_clk_set_rate,
.enable = sandbox_clk_enable,
@@ -130,7 +147,7 @@ U_BOOT_DRIVER(sandbox_clk) = {
.of_match = sandbox_clk_ids,
.ops = &sandbox_clk_ops,
.probe = sandbox_clk_probe,
- .priv_auto_alloc_size = sizeof(struct sandbox_clk_priv),
+ .priv_auto = sizeof(struct sandbox_clk_priv),
};
ulong sandbox_clk_query_rate(struct udevice *dev, int id)
diff --git a/drivers/clk/clk_sandbox_test.c b/drivers/clk/clk_sandbox_test.c
index 873383856f..c4e4481508 100644
--- a/drivers/clk/clk_sandbox_test.c
+++ b/drivers/clk/clk_sandbox_test.c
@@ -86,6 +86,16 @@ ulong sandbox_clk_test_get_rate(struct udevice *dev, int id)
return clk_get_rate(sbct->clkps[id]);
}
+ulong sandbox_clk_test_round_rate(struct udevice *dev, int id, ulong rate)
+{
+ struct sandbox_clk_test *sbct = dev_get_priv(dev);
+
+ if (id < 0 || id >= SANDBOX_CLK_TEST_ID_COUNT)
+ return -EINVAL;
+
+ return clk_round_rate(sbct->clkps[id], rate);
+}
+
ulong sandbox_clk_test_set_rate(struct udevice *dev, int id, ulong rate)
{
struct sandbox_clk_test *sbct = dev_get_priv(dev);
@@ -189,5 +199,5 @@ U_BOOT_DRIVER(sandbox_clk_test) = {
.id = UCLASS_MISC,
.of_match = sandbox_clk_test_ids,
.probe = sandbox_clk_test_probe,
- .priv_auto_alloc_size = sizeof(struct sandbox_clk_test),
+ .priv_auto = sizeof(struct sandbox_clk_test),
};
diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c
index 93722f74ae..7e67895ab7 100644
--- a/drivers/clk/clk_stm32f.c
+++ b/drivers/clk/clk_stm32f.c
@@ -726,6 +726,6 @@ U_BOOT_DRIVER(stm32fx_clk) = {
.id = UCLASS_CLK,
.ops = &stm32_clk_ops,
.probe = stm32_clk_probe,
- .priv_auto_alloc_size = sizeof(struct stm32_clk),
+ .priv_auto = sizeof(struct stm32_clk),
.flags = DM_FLAG_PRE_RELOC,
};
diff --git a/drivers/clk/clk_stm32h7.c b/drivers/clk/clk_stm32h7.c
index edf90ee00f..0171fe8c11 100644
--- a/drivers/clk/clk_stm32h7.c
+++ b/drivers/clk/clk_stm32h7.c
@@ -868,6 +868,6 @@ U_BOOT_DRIVER(stm32h7_clk) = {
.id = UCLASS_CLK,
.ops = &stm32_clk_ops,
.probe = stm32_clk_probe,
- .priv_auto_alloc_size = sizeof(struct stm32_clk),
+ .priv_auto = sizeof(struct stm32_clk),
.flags = DM_FLAG_PRE_RELOC,
};
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
index c8840b9e5f..5bea2b60b9 100644
--- a/drivers/clk/clk_stm32mp1.c
+++ b/drivers/clk/clk_stm32mp1.c
@@ -2253,7 +2253,7 @@ int soc_clk_dump(void)
int ret;
ret = uclass_get_device_by_driver(UCLASS_CLK,
- DM_GET_DRIVER(stm32mp1_clock),
+ DM_DRIVER_GET(stm32mp1_clock),
&dev);
if (ret)
return ret;
@@ -2332,6 +2332,6 @@ U_BOOT_DRIVER(stm32mp1_clock) = {
.name = "stm32mp1_clk",
.id = UCLASS_CLK,
.ops = &stm32mp1_clk_ops,
- .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv),
+ .priv_auto = sizeof(struct stm32mp1_clk_priv),
.probe = stm32mp1_clk_probe,
};
diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c
index d93b860aed..908bc7519c 100644
--- a/drivers/clk/clk_versal.c
+++ b/drivers/clk/clk_versal.c
@@ -734,5 +734,5 @@ U_BOOT_DRIVER(versal_clk) = {
.of_match = versal_clk_ids,
.probe = versal_clk_probe,
.ops = &versal_clk_ops,
- .priv_auto_alloc_size = sizeof(struct versal_clk_priv),
+ .priv_auto = sizeof(struct versal_clk_priv),
};
diff --git a/drivers/clk/clk_vexpress_osc.c b/drivers/clk/clk_vexpress_osc.c
index b48319bba6..3b1e0208d4 100644
--- a/drivers/clk/clk_vexpress_osc.c
+++ b/drivers/clk/clk_vexpress_osc.c
@@ -107,6 +107,6 @@ U_BOOT_DRIVER(vexpress_osc_clk) = {
.id = UCLASS_CLK,
.of_match = vexpress_osc_clk_ids,
.ops = &vexpress_osc_clk_ops,
- .priv_auto_alloc_size = sizeof(struct vexpress_osc_clk_priv),
+ .priv_auto = sizeof(struct vexpress_osc_clk_priv),
.probe = vexpress_osc_clk_probe,
};
diff --git a/drivers/clk/clk_zynq.c b/drivers/clk/clk_zynq.c
index a699a3664c..bf32d8317a 100644
--- a/drivers/clk/clk_zynq.c
+++ b/drivers/clk/clk_zynq.c
@@ -485,6 +485,6 @@ U_BOOT_DRIVER(zynq_clk) = {
.id = UCLASS_CLK,
.of_match = zynq_clk_ids,
.ops = &zynq_clk_ops,
- .priv_auto_alloc_size = sizeof(struct zynq_clk_priv),
+ .priv_auto = sizeof(struct zynq_clk_priv),
.probe = zynq_clk_probe,
};
diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c
index 7795119756..e8acca0066 100644
--- a/drivers/clk/clk_zynqmp.c
+++ b/drivers/clk/clk_zynqmp.c
@@ -617,7 +617,7 @@ int soc_clk_dump(void)
int i, ret;
ret = uclass_get_device_by_driver(UCLASS_CLK,
- DM_GET_DRIVER(zynqmp_clk), &dev);
+ DM_DRIVER_GET(zynqmp_clk), &dev);
if (ret)
return ret;
@@ -715,5 +715,5 @@ U_BOOT_DRIVER(zynqmp_clk) = {
.of_match = zynqmp_clk_ids,
.probe = zynqmp_clk_probe,
.ops = &zynqmp_clk_ops,
- .priv_auto_alloc_size = sizeof(struct zynqmp_clk_priv),
+ .priv_auto = sizeof(struct zynqmp_clk_priv),
};
diff --git a/drivers/clk/exynos/clk-exynos7420.c b/drivers/clk/exynos/clk-exynos7420.c
index 4a023ea736..7d869eb02b 100644
--- a/drivers/clk/exynos/clk-exynos7420.c
+++ b/drivers/clk/exynos/clk-exynos7420.c
@@ -199,7 +199,7 @@ U_BOOT_DRIVER(exynos7420_clk_topc) = {
.id = UCLASS_CLK,
.of_match = exynos7420_clk_topc_compat,
.probe = exynos7420_clk_topc_probe,
- .priv_auto_alloc_size = sizeof(struct exynos7420_clk_topc_priv),
+ .priv_auto = sizeof(struct exynos7420_clk_topc_priv),
.ops = &exynos7420_clk_topc_ops,
};
@@ -213,7 +213,7 @@ U_BOOT_DRIVER(exynos7420_clk_top0) = {
.id = UCLASS_CLK,
.of_match = exynos7420_clk_top0_compat,
.probe = exynos7420_clk_top0_probe,
- .priv_auto_alloc_size = sizeof(struct exynos7420_clk_top0_priv),
+ .priv_auto = sizeof(struct exynos7420_clk_top0_priv),
.ops = &exynos7420_clk_top0_ops,
};
diff --git a/drivers/clk/ics8n3qv01.c b/drivers/clk/ics8n3qv01.c
index 76b27ad7fd..6bc1b8ba9d 100644
--- a/drivers/clk/ics8n3qv01.c
+++ b/drivers/clk/ics8n3qv01.c
@@ -226,5 +226,5 @@ U_BOOT_DRIVER(ics8n3qv01) = {
.ops = &ics8n3qv01_ops,
.of_match = ics8n3qv01_ids,
.probe = ics8n3qv01_probe,
- .priv_auto_alloc_size = sizeof(struct ics8n3qv01_priv),
+ .priv_auto = sizeof(struct ics8n3qv01_priv),
};
diff --git a/drivers/clk/imx/clk-imx8.c b/drivers/clk/imx/clk-imx8.c
index 27a652a625..8484613eed 100644
--- a/drivers/clk/imx/clk-imx8.c
+++ b/drivers/clk/imx/clk-imx8.c
@@ -51,7 +51,7 @@ int soc_clk_dump(void)
int i, ret;
ret = uclass_get_device_by_driver(UCLASS_CLK,
- DM_GET_DRIVER(imx8_clk), &dev);
+ DM_DRIVER_GET(imx8_clk), &dev);
if (ret)
return ret;
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
index 0246149107..259ea33595 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -716,7 +716,7 @@ U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
.id = UCLASS_CLK,
.of_match = mt7622_apmixed_compat,
.probe = mt7622_apmixedsys_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .priv_auto = sizeof(struct mtk_clk_priv),
.ops = &mtk_clk_apmixedsys_ops,
.flags = DM_FLAG_PRE_RELOC,
};
@@ -726,7 +726,7 @@ U_BOOT_DRIVER(mtk_clk_topckgen) = {
.id = UCLASS_CLK,
.of_match = mt7622_topckgen_compat,
.probe = mt7622_topckgen_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .priv_auto = sizeof(struct mtk_clk_priv),
.ops = &mtk_clk_topckgen_ops,
.flags = DM_FLAG_PRE_RELOC,
};
@@ -736,7 +736,7 @@ U_BOOT_DRIVER(mtk_clk_infracfg) = {
.id = UCLASS_CLK,
.of_match = mt7622_infracfg_compat,
.probe = mt7622_infracfg_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
.flags = DM_FLAG_PRE_RELOC,
};
@@ -746,7 +746,7 @@ U_BOOT_DRIVER(mtk_clk_pericfg) = {
.id = UCLASS_CLK,
.of_match = mt7622_pericfg_compat,
.probe = mt7622_pericfg_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
.flags = DM_FLAG_PRE_RELOC,
};
@@ -757,7 +757,7 @@ U_BOOT_DRIVER(mtk_clk_pciesys) = {
.of_match = mt7622_pciesys_compat,
.probe = mt7622_pciesys_probe,
.bind = mt7622_pciesys_bind,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};
@@ -767,7 +767,7 @@ U_BOOT_DRIVER(mtk_clk_ethsys) = {
.of_match = mt7622_ethsys_compat,
.probe = mt7622_ethsys_probe,
.bind = mt7622_ethsys_bind,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};
@@ -776,7 +776,7 @@ U_BOOT_DRIVER(mtk_clk_sgmiisys) = {
.id = UCLASS_CLK,
.of_match = mt7622_sgmiisys_compat,
.probe = mt7622_sgmiisys_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};
@@ -785,6 +785,6 @@ U_BOOT_DRIVER(mtk_clk_ssusbsys) = {
.id = UCLASS_CLK,
.of_match = mt7622_ssusbsys_compat,
.probe = mt7622_ssusbsys_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};
diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c
index a15fb45e8e..0c7411ee81 100644
--- a/drivers/clk/mediatek/clk-mt7623.c
+++ b/drivers/clk/mediatek/clk-mt7623.c
@@ -859,7 +859,7 @@ U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
.id = UCLASS_CLK,
.of_match = mt7623_apmixed_compat,
.probe = mt7623_apmixedsys_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .priv_auto = sizeof(struct mtk_clk_priv),
.ops = &mtk_clk_apmixedsys_ops,
.flags = DM_FLAG_PRE_RELOC,
};
@@ -869,7 +869,7 @@ U_BOOT_DRIVER(mtk_clk_topckgen) = {
.id = UCLASS_CLK,
.of_match = mt7623_topckgen_compat,
.probe = mt7623_topckgen_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .priv_auto = sizeof(struct mtk_clk_priv),
.ops = &mtk_clk_topckgen_ops,
.flags = DM_FLAG_PRE_RELOC,
};
@@ -879,7 +879,7 @@ U_BOOT_DRIVER(mtk_clk_infracfg) = {
.id = UCLASS_CLK,
.of_match = mt7623_infracfg_compat,
.probe = mt7623_infracfg_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
.flags = DM_FLAG_PRE_RELOC,
};
@@ -889,7 +889,7 @@ U_BOOT_DRIVER(mtk_clk_pericfg) = {
.id = UCLASS_CLK,
.of_match = mt7623_pericfg_compat,
.probe = mt7623_pericfg_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
.flags = DM_FLAG_PRE_RELOC,
};
@@ -900,7 +900,7 @@ U_BOOT_DRIVER(mtk_clk_hifsys) = {
.of_match = mt7623_hifsys_compat,
.probe = mt7623_hifsys_probe,
.bind = mt7623_ethsys_hifsys_bind,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};
@@ -910,6 +910,6 @@ U_BOOT_DRIVER(mtk_clk_ethsys) = {
.of_match = mt7623_ethsys_compat,
.probe = mt7623_ethsys_probe,
.bind = mt7623_ethsys_hifsys_bind,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};
diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c
index 5b2aa5f200..31b6fa0225 100644
--- a/drivers/clk/mediatek/clk-mt7629.c
+++ b/drivers/clk/mediatek/clk-mt7629.c
@@ -704,7 +704,7 @@ U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
.id = UCLASS_CLK,
.of_match = mt7629_apmixed_compat,
.probe = mt7629_apmixedsys_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .priv_auto = sizeof(struct mtk_clk_priv),
.ops = &mtk_clk_apmixedsys_ops,
.flags = DM_FLAG_PRE_RELOC,
};
@@ -714,7 +714,7 @@ U_BOOT_DRIVER(mtk_clk_topckgen) = {
.id = UCLASS_CLK,
.of_match = mt7629_topckgen_compat,
.probe = mt7629_topckgen_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .priv_auto = sizeof(struct mtk_clk_priv),
.ops = &mtk_clk_topckgen_ops,
.flags = DM_FLAG_PRE_RELOC,
};
@@ -724,7 +724,7 @@ U_BOOT_DRIVER(mtk_clk_infracfg) = {
.id = UCLASS_CLK,
.of_match = mt7629_infracfg_compat,
.probe = mt7629_infracfg_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
.flags = DM_FLAG_PRE_RELOC,
};
@@ -734,7 +734,7 @@ U_BOOT_DRIVER(mtk_clk_pericfg) = {
.id = UCLASS_CLK,
.of_match = mt7629_pericfg_compat,
.probe = mt7629_pericfg_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
.flags = DM_FLAG_PRE_RELOC,
};
@@ -745,7 +745,7 @@ U_BOOT_DRIVER(mtk_clk_ethsys) = {
.of_match = mt7629_ethsys_compat,
.probe = mt7629_ethsys_probe,
.bind = mt7629_ethsys_bind,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};
@@ -754,7 +754,7 @@ U_BOOT_DRIVER(mtk_clk_sgmiisys) = {
.id = UCLASS_CLK,
.of_match = mt7629_sgmiisys_compat,
.probe = mt7629_sgmiisys_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};
@@ -763,6 +763,6 @@ U_BOOT_DRIVER(mtk_clk_ssusbsys) = {
.id = UCLASS_CLK,
.of_match = mt7629_ssusbsys_compat,
.probe = mt7629_ssusbsys_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};
diff --git a/drivers/clk/mediatek/clk-mt8512.c b/drivers/clk/mediatek/clk-mt8512.c
index ad254d1cce..193e069cb0 100644
--- a/drivers/clk/mediatek/clk-mt8512.c
+++ b/drivers/clk/mediatek/clk-mt8512.c
@@ -838,7 +838,7 @@ U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
.id = UCLASS_CLK,
.of_match = mt8512_apmixed_compat,
.probe = mt8512_apmixedsys_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .priv_auto = sizeof(struct mtk_clk_priv),
.ops = &mtk_clk_apmixedsys_ops,
.flags = DM_FLAG_PRE_RELOC,
};
@@ -848,7 +848,7 @@ U_BOOT_DRIVER(mtk_clk_topckgen) = {
.id = UCLASS_CLK,
.of_match = mt8512_topckgen_compat,
.probe = mt8512_topckgen_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .priv_auto = sizeof(struct mtk_clk_priv),
.ops = &mtk_clk_topckgen_ops,
.flags = DM_FLAG_PRE_RELOC,
};
@@ -858,7 +858,7 @@ U_BOOT_DRIVER(mtk_clk_topckgen_cg) = {
.id = UCLASS_CLK,
.of_match = mt8512_topckgen_cg_compat,
.probe = mt8512_topckgen_cg_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
.flags = DM_FLAG_PRE_RELOC,
};
@@ -868,7 +868,7 @@ U_BOOT_DRIVER(mtk_clk_infracfg) = {
.id = UCLASS_CLK,
.of_match = mt8512_infracfg_compat,
.probe = mt8512_infracfg_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
.flags = DM_FLAG_PRE_RELOC,
};
diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c
index cd1db25783..29f70620e0 100644
--- a/drivers/clk/mediatek/clk-mt8516.c
+++ b/drivers/clk/mediatek/clk-mt8516.c
@@ -777,7 +777,7 @@ U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
.id = UCLASS_CLK,
.of_match = mt8516_apmixed_compat,
.probe = mt8516_apmixedsys_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .priv_auto = sizeof(struct mtk_clk_priv),
.ops = &mtk_clk_apmixedsys_ops,
.flags = DM_FLAG_PRE_RELOC,
};
@@ -787,7 +787,7 @@ U_BOOT_DRIVER(mtk_clk_topckgen) = {
.id = UCLASS_CLK,
.of_match = mt8516_topckgen_compat,
.probe = mt8516_topckgen_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .priv_auto = sizeof(struct mtk_clk_priv),
.ops = &mtk_clk_topckgen_ops,
.flags = DM_FLAG_PRE_RELOC,
};
@@ -797,7 +797,7 @@ U_BOOT_DRIVER(mtk_clk_topckgen_cg) = {
.id = UCLASS_CLK,
.of_match = mt8516_topckgen_cg_compat,
.probe = mt8516_topckgen_cg_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
.flags = DM_FLAG_PRE_RELOC,
};
diff --git a/drivers/clk/mediatek/clk-mt8518.c b/drivers/clk/mediatek/clk-mt8518.c
index 985a0c1de5..2386514837 100644
--- a/drivers/clk/mediatek/clk-mt8518.c
+++ b/drivers/clk/mediatek/clk-mt8518.c
@@ -1533,7 +1533,7 @@ U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
.id = UCLASS_CLK,
.of_match = mt8518_apmixed_compat,
.probe = mt8518_apmixedsys_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .priv_auto = sizeof(struct mtk_clk_priv),
.ops = &mtk_clk_apmixedsys_ops,
.flags = DM_FLAG_PRE_RELOC,
};
@@ -1543,7 +1543,7 @@ U_BOOT_DRIVER(mtk_clk_topckgen) = {
.id = UCLASS_CLK,
.of_match = mt8518_topckgen_compat,
.probe = mt8518_topckgen_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .priv_auto = sizeof(struct mtk_clk_priv),
.ops = &mtk_clk_topckgen_ops,
.flags = DM_FLAG_PRE_RELOC,
};
@@ -1553,7 +1553,7 @@ U_BOOT_DRIVER(mtk_clk_topckgen_cg) = {
.id = UCLASS_CLK,
.of_match = mt8518_topckgen_cg_compat,
.probe = mt8518_topckgen_cg_probe,
- .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
.flags = DM_FLAG_PRE_RELOC,
};
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 388471b03a..d43b8a0648 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -296,7 +296,7 @@ static ulong mtk_topckgen_get_factor_rate(struct clk *clk, u32 off)
switch (fdiv->flags & CLK_PARENT_MASK) {
case CLK_PARENT_APMIXED:
rate = mtk_clk_find_parent_rate(clk, fdiv->parent,
- DM_GET_DRIVER(mtk_clk_apmixedsys));
+ DM_DRIVER_GET(mtk_clk_apmixedsys));
break;
case CLK_PARENT_TOPCKGEN:
rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL);
@@ -474,11 +474,11 @@ static ulong mtk_clk_gate_get_rate(struct clk *clk)
switch (gate->flags & CLK_PARENT_MASK) {
case CLK_PARENT_APMIXED:
return mtk_clk_find_parent_rate(clk, gate->parent,
- DM_GET_DRIVER(mtk_clk_apmixedsys));
+ DM_DRIVER_GET(mtk_clk_apmixedsys));
break;
case CLK_PARENT_TOPCKGEN:
return mtk_clk_find_parent_rate(clk, gate->parent,
- DM_GET_DRIVER(mtk_clk_topckgen));
+ DM_DRIVER_GET(mtk_clk_topckgen));
break;
default:
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 6ef8b418d7..d6da59d269 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -289,7 +289,7 @@ static int meson_clk_probe(struct udevice *dev)
{
struct meson_clk *priv = dev_get_priv(dev);
- priv->map = syscon_node_to_regmap(dev_get_parent(dev)->node);
+ priv->map = syscon_node_to_regmap(dev_ofnode(dev_get_parent(dev)));
if (IS_ERR(priv->map))
return PTR_ERR(priv->map);
@@ -320,7 +320,7 @@ U_BOOT_DRIVER(meson_clk_axg) = {
.name = "meson_clk_axg",
.id = UCLASS_CLK,
.of_match = meson_clk_ids,
- .priv_auto_alloc_size = sizeof(struct meson_clk),
+ .priv_auto = sizeof(struct meson_clk),
.ops = &meson_clk_ops,
.probe = meson_clk_probe,
};
diff --git a/drivers/clk/meson/g12a-ao.c b/drivers/clk/meson/g12a-ao.c
index 7a0abea77c..0148529e04 100644
--- a/drivers/clk/meson/g12a-ao.c
+++ b/drivers/clk/meson/g12a-ao.c
@@ -56,7 +56,7 @@ static int meson_clk_probe(struct udevice *dev)
{
struct meson_clk *priv = dev_get_priv(dev);
- priv->map = syscon_node_to_regmap(dev_get_parent(dev)->node);
+ priv->map = syscon_node_to_regmap(dev_ofnode(dev_get_parent(dev)));
if (IS_ERR(priv->map))
return PTR_ERR(priv->map);
@@ -77,7 +77,7 @@ U_BOOT_DRIVER(meson_clk_axg) = {
.name = "meson_clk_g12a_ao",
.id = UCLASS_CLK,
.of_match = meson_clk_ids,
- .priv_auto_alloc_size = sizeof(struct meson_clk),
+ .priv_auto = sizeof(struct meson_clk),
.ops = &meson_clk_ops,
.probe = meson_clk_probe,
};
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index bf2f357435..5058db1a47 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -979,7 +979,7 @@ static int meson_clk_probe(struct udevice *dev)
{
struct meson_clk *priv = dev_get_priv(dev);
- priv->map = syscon_node_to_regmap(dev_get_parent(dev)->node);
+ priv->map = syscon_node_to_regmap(dev_ofnode(dev_get_parent(dev)));
if (IS_ERR(priv->map))
return PTR_ERR(priv->map);
@@ -1014,7 +1014,7 @@ U_BOOT_DRIVER(meson_clk_g12a) = {
.name = "meson_clk_g12a",
.id = UCLASS_CLK,
.of_match = meson_clk_ids,
- .priv_auto_alloc_size = sizeof(struct meson_clk),
+ .priv_auto = sizeof(struct meson_clk),
.ops = &meson_clk_ops,
.probe = meson_clk_probe,
};
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index b9353c053e..e379540dee 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -885,7 +885,7 @@ static int meson_clk_probe(struct udevice *dev)
{
struct meson_clk *priv = dev_get_priv(dev);
- priv->map = syscon_node_to_regmap(dev_get_parent(dev)->node);
+ priv->map = syscon_node_to_regmap(dev_ofnode(dev_get_parent(dev)));
if (IS_ERR(priv->map))
return PTR_ERR(priv->map);
@@ -919,7 +919,7 @@ U_BOOT_DRIVER(meson_clk) = {
.name = "meson_clk",
.id = UCLASS_CLK,
.of_match = meson_clk_ids,
- .priv_auto_alloc_size = sizeof(struct meson_clk),
+ .priv_auto = sizeof(struct meson_clk),
.ops = &meson_clk_ops,
.probe = meson_clk_probe,
};
diff --git a/drivers/clk/mpc83xx_clk.c b/drivers/clk/mpc83xx_clk.c
index 8d96ec767a..c5ced1f132 100644
--- a/drivers/clk/mpc83xx_clk.c
+++ b/drivers/clk/mpc83xx_clk.c
@@ -389,7 +389,7 @@ U_BOOT_DRIVER(mpc83xx_clk) = {
.of_match = mpc83xx_clk_match,
.ops = &mpc83xx_clk_ops,
.probe = mpc83xx_clk_probe,
- .priv_auto_alloc_size = sizeof(struct mpc83xx_clk_priv),
+ .priv_auto = sizeof(struct mpc83xx_clk_priv),
.bind = mpc83xx_clk_bind,
};
diff --git a/drivers/clk/mtmips/clk-mt7628.c b/drivers/clk/mtmips/clk-mt7628.c
index 35780de8c4..4d3ac847d1 100644
--- a/drivers/clk/mtmips/clk-mt7628.c
+++ b/drivers/clk/mtmips/clk-mt7628.c
@@ -153,6 +153,6 @@ U_BOOT_DRIVER(mt7628_clk) = {
.id = UCLASS_CLK,
.of_match = mt7628_clk_ids,
.probe = mt7628_clk_probe,
- .priv_auto_alloc_size = sizeof(struct mt7628_clk_priv),
+ .priv_auto = sizeof(struct mt7628_clk_priv),
.ops = &mt7628_clk_ops,
};
diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c
index 223da22c1b..0132fcb7e6 100644
--- a/drivers/clk/mvebu/armada-37xx-periph.c
+++ b/drivers/clk/mvebu/armada-37xx-periph.c
@@ -624,6 +624,6 @@ U_BOOT_DRIVER(armada_37xx_periph_clk) = {
.id = UCLASS_CLK,
.of_match = armada_37xx_periph_clk_ids,
.ops = &armada_37xx_periph_clk_ops,
- .priv_auto_alloc_size = sizeof(struct a37xx_periphclk),
+ .priv_auto = sizeof(struct a37xx_periphclk),
.probe = armada_37xx_periph_clk_probe,
};
diff --git a/drivers/clk/mvebu/armada-37xx-tbg.c b/drivers/clk/mvebu/armada-37xx-tbg.c
index 233926e9b6..b1c0852e89 100644
--- a/drivers/clk/mvebu/armada-37xx-tbg.c
+++ b/drivers/clk/mvebu/armada-37xx-tbg.c
@@ -150,6 +150,6 @@ U_BOOT_DRIVER(armada_37xx_tbg_clk) = {
.id = UCLASS_CLK,
.of_match = armada_37xx_tbg_clk_ids,
.ops = &armada_37xx_tbg_clk_ops,
- .priv_auto_alloc_size = sizeof(struct a37xx_tbgclk),
+ .priv_auto = sizeof(struct a37xx_tbgclk),
.probe = armada_37xx_tbg_clk_probe,
};
diff --git a/drivers/clk/owl/clk_owl.c b/drivers/clk/owl/clk_owl.c
index 1999c87a33..96ab7fed1f 100644
--- a/drivers/clk/owl/clk_owl.c
+++ b/drivers/clk/owl/clk_owl.c
@@ -161,6 +161,6 @@ U_BOOT_DRIVER(clk_owl) = {
.id = UCLASS_CLK,
.of_match = owl_clk_ids,
.ops = &owl_clk_ops,
- .priv_auto_alloc_size = sizeof(struct owl_clk_priv),
+ .priv_auto = sizeof(struct owl_clk_priv),
.probe = owl_clk_probe,
};
diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
index 6997054b30..1c54eca6c0 100644
--- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
@@ -336,7 +336,7 @@ U_BOOT_DRIVER(clk_r8a774a1) = {
.name = "clk_r8a774a1",
.id = UCLASS_CLK,
.of_match = r8a774a1_clk_ids,
- .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
+ .priv_auto = sizeof(struct gen3_clk_priv),
.ops = &gen3_clk_ops,
.probe = gen3_clk_probe,
.remove = gen3_clk_remove,
diff --git a/drivers/clk/renesas/r8a774b1-cpg-mssr.c b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
index 7b6947b5b9..03851d0b5a 100644
--- a/drivers/clk/renesas/r8a774b1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
@@ -329,7 +329,7 @@ U_BOOT_DRIVER(clk_r8a774b1) = {
.name = "clk_r8a774b1",
.id = UCLASS_CLK,
.of_match = r8a774b1_clk_ids,
- .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
+ .priv_auto = sizeof(struct gen3_clk_priv),
.ops = &gen3_clk_ops,
.probe = gen3_clk_probe,
.remove = gen3_clk_remove,
diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
index c9f0f7221d..37a7123f73 100644
--- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
@@ -301,7 +301,7 @@ U_BOOT_DRIVER(clk_r8a774c0) = {
.name = "clk_r8a774c0",
.id = UCLASS_CLK,
.of_match = r8a774c0_clk_ids,
- .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
+ .priv_auto = sizeof(struct gen3_clk_priv),
.ops = &gen3_clk_ops,
.probe = gen3_clk_probe,
.remove = gen3_clk_remove,
diff --git a/drivers/clk/renesas/r8a774e1-cpg-mssr.c b/drivers/clk/renesas/r8a774e1-cpg-mssr.c
index 6cce007aa1..c969ec6888 100644
--- a/drivers/clk/renesas/r8a774e1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774e1-cpg-mssr.c
@@ -351,7 +351,7 @@ U_BOOT_DRIVER(clk_r8a774e1) = {
.name = "clk_r8a774e1",
.id = UCLASS_CLK,
.of_match = r8a774e1_clk_ids,
- .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
+ .priv_auto = sizeof(struct gen3_clk_priv),
.ops = &gen3_clk_ops,
.probe = gen3_clk_probe,
.remove = gen3_clk_remove,
diff --git a/drivers/clk/renesas/r8a7790-cpg-mssr.c b/drivers/clk/renesas/r8a7790-cpg-mssr.c
index 7451f53ba3..09e7dbd3a3 100644
--- a/drivers/clk/renesas/r8a7790-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7790-cpg-mssr.c
@@ -283,7 +283,7 @@ U_BOOT_DRIVER(clk_r8a7790) = {
.name = "clk_r8a7790",
.id = UCLASS_CLK,
.of_match = r8a7790_clk_ids,
- .priv_auto_alloc_size = sizeof(struct gen2_clk_priv),
+ .priv_auto = sizeof(struct gen2_clk_priv),
.ops = &gen2_clk_ops,
.probe = gen2_clk_probe,
.remove = gen2_clk_remove,
diff --git a/drivers/clk/renesas/r8a7791-cpg-mssr.c b/drivers/clk/renesas/r8a7791-cpg-mssr.c
index 25fd489609..675ac83a61 100644
--- a/drivers/clk/renesas/r8a7791-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7791-cpg-mssr.c
@@ -289,7 +289,7 @@ U_BOOT_DRIVER(clk_r8a7791) = {
.name = "clk_r8a7791",
.id = UCLASS_CLK,
.of_match = r8a7791_clk_ids,
- .priv_auto_alloc_size = sizeof(struct gen2_clk_priv),
+ .priv_auto = sizeof(struct gen2_clk_priv),
.ops = &gen2_clk_ops,
.probe = gen2_clk_probe,
.remove = gen2_clk_remove,
diff --git a/drivers/clk/renesas/r8a7792-cpg-mssr.c b/drivers/clk/renesas/r8a7792-cpg-mssr.c
index d47ab99e88..d2225a3ff5 100644
--- a/drivers/clk/renesas/r8a7792-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7792-cpg-mssr.c
@@ -235,7 +235,7 @@ U_BOOT_DRIVER(clk_r8a7792) = {
.name = "clk_r8a7792",
.id = UCLASS_CLK,
.of_match = r8a7792_clk_ids,
- .priv_auto_alloc_size = sizeof(struct gen2_clk_priv),
+ .priv_auto = sizeof(struct gen2_clk_priv),
.ops = &gen2_clk_ops,
.probe = gen2_clk_probe,
.remove = gen2_clk_remove,
diff --git a/drivers/clk/renesas/r8a7794-cpg-mssr.c b/drivers/clk/renesas/r8a7794-cpg-mssr.c
index 7093e0d42c..1fcac9b59d 100644
--- a/drivers/clk/renesas/r8a7794-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7794-cpg-mssr.c
@@ -264,7 +264,7 @@ U_BOOT_DRIVER(clk_r8a7794) = {
.name = "clk_r8a7794",
.id = UCLASS_CLK,
.of_match = r8a7794_clk_ids,
- .priv_auto_alloc_size = sizeof(struct gen2_clk_priv),
+ .priv_auto = sizeof(struct gen2_clk_priv),
.ops = &gen2_clk_ops,
.probe = gen2_clk_probe,
.remove = gen2_clk_remove,
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index dcd96ad017..101f6583fa 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -373,7 +373,7 @@ U_BOOT_DRIVER(clk_r8a7795) = {
.name = "clk_r8a7795",
.id = UCLASS_CLK,
.of_match = r8a7795_clk_ids,
- .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
+ .priv_auto = sizeof(struct gen3_clk_priv),
.ops = &gen3_clk_ops,
.probe = gen3_clk_probe,
.remove = gen3_clk_remove,
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 89dc141239..3c17bcbb18 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -351,7 +351,7 @@ U_BOOT_DRIVER(clk_r8a7796) = {
.name = "clk_r8a7796",
.id = UCLASS_CLK,
.of_match = r8a7796_clk_ids,
- .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
+ .priv_auto = sizeof(struct gen3_clk_priv),
.ops = &gen3_clk_ops,
.probe = gen3_clk_probe,
.remove = gen3_clk_remove,
diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
index 6ed88295c9..5f37f6285f 100644
--- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
@@ -349,7 +349,7 @@ U_BOOT_DRIVER(clk_r8a77965) = {
.name = "clk_r8a77965",
.id = UCLASS_CLK,
.of_match = r8a77965_clk_ids,
- .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
+ .priv_auto = sizeof(struct gen3_clk_priv),
.ops = &gen3_clk_ops,
.probe = gen3_clk_probe,
.remove = gen3_clk_remove,
diff --git a/drivers/clk/renesas/r8a77970-cpg-mssr.c b/drivers/clk/renesas/r8a77970-cpg-mssr.c
index df07120171..bafe4bbb09 100644
--- a/drivers/clk/renesas/r8a77970-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77970-cpg-mssr.c
@@ -226,7 +226,7 @@ U_BOOT_DRIVER(clk_r8a77970) = {
.name = "clk_r8a77970",
.id = UCLASS_CLK,
.of_match = r8a77970_clk_ids,
- .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
+ .priv_auto = sizeof(struct gen3_clk_priv),
.ops = &gen3_clk_ops,
.probe = gen3_clk_probe,
.remove = gen3_clk_remove,
diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c b/drivers/clk/renesas/r8a77980-cpg-mssr.c
index c8d7a9469b..a202005121 100644
--- a/drivers/clk/renesas/r8a77980-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c
@@ -249,7 +249,7 @@ U_BOOT_DRIVER(clk_r8a77980) = {
.name = "clk_r8a77980",
.id = UCLASS_CLK,
.of_match = r8a77980_clk_ids,
- .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
+ .priv_auto = sizeof(struct gen3_clk_priv),
.ops = &gen3_clk_ops,
.probe = gen3_clk_probe,
.remove = gen3_clk_remove,
diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
index 357e7b534d..5cc9270869 100644
--- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
@@ -308,7 +308,7 @@ U_BOOT_DRIVER(clk_r8a77990) = {
.name = "clk_r8a77990",
.id = UCLASS_CLK,
.of_match = r8a77990_clk_ids,
- .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
+ .priv_auto = sizeof(struct gen3_clk_priv),
.ops = &gen3_clk_ops,
.probe = gen3_clk_probe,
.remove = gen3_clk_remove,
diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c
index d62aeba635..eef154bc82 100644
--- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
@@ -247,7 +247,7 @@ U_BOOT_DRIVER(clk_r8a77995) = {
.name = "clk_r8a77995",
.id = UCLASS_CLK,
.of_match = r8a77995_clk_ids,
- .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
+ .priv_auto = sizeof(struct gen3_clk_priv),
.ops = &gen3_clk_ops,
.probe = gen3_clk_probe,
.remove = gen3_clk_remove,
diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c
index 71916dbf3b..a2a5939d4b 100644
--- a/drivers/clk/rockchip/clk_px30.c
+++ b/drivers/clk/rockchip/clk_px30.c
@@ -15,6 +15,7 @@
#include <asm/arch-rockchip/cru_px30.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/io.h>
+#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/px30-cru.h>
#include <linux/bitops.h>
@@ -1432,7 +1433,7 @@ static int px30_clk_probe(struct udevice *dev)
return 0;
}
-static int px30_clk_ofdata_to_platdata(struct udevice *dev)
+static int px30_clk_of_to_plat(struct udevice *dev)
{
struct px30_clk_priv *priv = dev_get_priv(dev);
@@ -1458,7 +1459,7 @@ static int px30_clk_bind(struct udevice *dev)
glb_srst_fst);
priv->glb_srst_snd_value = offsetof(struct px30_cru,
glb_srst_snd);
- sys_child->priv = priv;
+ dev_set_priv(sys_child, priv);
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
@@ -1480,8 +1481,8 @@ U_BOOT_DRIVER(rockchip_px30_cru) = {
.name = "rockchip_px30_cru",
.id = UCLASS_CLK,
.of_match = px30_clk_ids,
- .priv_auto_alloc_size = sizeof(struct px30_clk_priv),
- .ofdata_to_platdata = px30_clk_ofdata_to_platdata,
+ .priv_auto = sizeof(struct px30_clk_priv),
+ .of_to_plat = px30_clk_of_to_plat,
.ops = &px30_clk_ops,
.bind = px30_clk_bind,
.probe = px30_clk_probe,
@@ -1609,7 +1610,7 @@ static int px30_pmuclk_probe(struct udevice *dev)
return 0;
}
-static int px30_pmuclk_ofdata_to_platdata(struct udevice *dev)
+static int px30_pmuclk_of_to_plat(struct udevice *dev)
{
struct px30_pmuclk_priv *priv = dev_get_priv(dev);
@@ -1627,8 +1628,8 @@ U_BOOT_DRIVER(rockchip_px30_pmucru) = {
.name = "rockchip_px30_pmucru",
.id = UCLASS_CLK,
.of_match = px30_pmuclk_ids,
- .priv_auto_alloc_size = sizeof(struct px30_pmuclk_priv),
- .ofdata_to_platdata = px30_pmuclk_ofdata_to_platdata,
+ .priv_auto = sizeof(struct px30_pmuclk_priv),
+ .of_to_plat = px30_pmuclk_of_to_plat,
.ops = &px30_pmuclk_ops,
.probe = px30_pmuclk_probe,
};
diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c
index 274572f70c..026858459e 100644
--- a/drivers/clk/rockchip/clk_rk3036.c
+++ b/drivers/clk/rockchip/clk_rk3036.c
@@ -14,6 +14,7 @@
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk3036.h>
#include <asm/arch-rockchip/hardware.h>
+#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3036-cru.h>
#include <linux/delay.h>
@@ -318,7 +319,7 @@ static struct clk_ops rk3036_clk_ops = {
.set_rate = rk3036_clk_set_rate,
};
-static int rk3036_clk_ofdata_to_platdata(struct udevice *dev)
+static int rk3036_clk_of_to_plat(struct udevice *dev)
{
struct rk3036_clk_priv *priv = dev_get_priv(dev);
@@ -353,7 +354,7 @@ static int rk3036_clk_bind(struct udevice *dev)
cru_glb_srst_fst_value);
priv->glb_srst_snd_value = offsetof(struct rk3036_cru,
cru_glb_srst_snd_value);
- sys_child->priv = priv;
+ dev_set_priv(sys_child, priv);
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
@@ -375,8 +376,8 @@ U_BOOT_DRIVER(rockchip_rk3036_cru) = {
.name = "clk_rk3036",
.id = UCLASS_CLK,
.of_match = rk3036_clk_ids,
- .priv_auto_alloc_size = sizeof(struct rk3036_clk_priv),
- .ofdata_to_platdata = rk3036_clk_ofdata_to_platdata,
+ .priv_auto = sizeof(struct rk3036_clk_priv),
+ .of_to_plat = rk3036_clk_of_to_plat,
.ops = &rk3036_clk_ops,
.bind = rk3036_clk_bind,
.probe = rk3036_clk_probe,
diff --git a/drivers/clk/rockchip/clk_rk3128.c b/drivers/clk/rockchip/clk_rk3128.c
index 61f823e254..d5b2b63dd7 100644
--- a/drivers/clk/rockchip/clk_rk3128.c
+++ b/drivers/clk/rockchip/clk_rk3128.c
@@ -15,6 +15,7 @@
#include <asm/arch-rockchip/cru_rk3128.h>
#include <asm/arch-rockchip/hardware.h>
#include <bitfield.h>
+#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3128-cru.h>
#include <linux/delay.h>
@@ -546,7 +547,7 @@ static struct clk_ops rk3128_clk_ops = {
.set_rate = rk3128_clk_set_rate,
};
-static int rk3128_clk_ofdata_to_platdata(struct udevice *dev)
+static int rk3128_clk_of_to_plat(struct udevice *dev)
{
struct rk3128_clk_priv *priv = dev_get_priv(dev);
@@ -581,7 +582,7 @@ static int rk3128_clk_bind(struct udevice *dev)
cru_glb_srst_fst_value);
priv->glb_srst_snd_value = offsetof(struct rk3128_cru,
cru_glb_srst_snd_value);
- sys_child->priv = priv;
+ dev_set_priv(sys_child, priv);
}
return 0;
@@ -597,8 +598,8 @@ U_BOOT_DRIVER(rockchip_rk3128_cru) = {
.name = "clk_rk3128",
.id = UCLASS_CLK,
.of_match = rk3128_clk_ids,
- .priv_auto_alloc_size = sizeof(struct rk3128_clk_priv),
- .ofdata_to_platdata = rk3128_clk_ofdata_to_platdata,
+ .priv_auto = sizeof(struct rk3128_clk_priv),
+ .of_to_plat = rk3128_clk_of_to_plat,
.ops = &rk3128_clk_ops,
.bind = rk3128_clk_bind,
.probe = rk3128_clk_probe,
diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c
index aacc8cf2d1..1b62d8d289 100644
--- a/drivers/clk/rockchip/clk_rk3188.c
+++ b/drivers/clk/rockchip/clk_rk3188.c
@@ -538,7 +538,7 @@ static struct clk_ops rk3188_clk_ops = {
.set_rate = rk3188_clk_set_rate,
};
-static int rk3188_clk_ofdata_to_platdata(struct udevice *dev)
+static int rk3188_clk_of_to_plat(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3188_clk_priv *priv = dev_get_priv(dev);
@@ -561,7 +561,7 @@ static int rk3188_clk_probe(struct udevice *dev)
#ifdef CONFIG_SPL_BUILD
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- struct rk3188_clk_plat *plat = dev_get_platdata(dev);
+ struct rk3188_clk_plat *plat = dev_get_plat(dev);
priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
#endif
@@ -593,7 +593,7 @@ static int rk3188_clk_bind(struct udevice *dev)
cru_glb_srst_fst_value);
priv->glb_srst_snd_value = offsetof(struct rk3188_cru,
cru_glb_srst_snd_value);
- sys_child->priv = priv;
+ dev_set_priv(sys_child, priv);
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
@@ -616,10 +616,10 @@ U_BOOT_DRIVER(rockchip_rk3188_cru) = {
.name = "rockchip_rk3188_cru",
.id = UCLASS_CLK,
.of_match = rk3188_clk_ids,
- .priv_auto_alloc_size = sizeof(struct rk3188_clk_priv),
- .platdata_auto_alloc_size = sizeof(struct rk3188_clk_plat),
+ .priv_auto = sizeof(struct rk3188_clk_priv),
+ .plat_auto = sizeof(struct rk3188_clk_plat),
.ops = &rk3188_clk_ops,
.bind = rk3188_clk_bind,
- .ofdata_to_platdata = rk3188_clk_ofdata_to_platdata,
+ .of_to_plat = rk3188_clk_of_to_plat,
.probe = rk3188_clk_probe,
};
diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c
index 054b2fd349..dbef606d88 100644
--- a/drivers/clk/rockchip/clk_rk322x.c
+++ b/drivers/clk/rockchip/clk_rk322x.c
@@ -14,6 +14,7 @@
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk322x.h>
#include <asm/arch-rockchip/hardware.h>
+#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3228-cru.h>
#include <linux/bitops.h>
@@ -475,7 +476,7 @@ static struct clk_ops rk322x_clk_ops = {
.set_parent = rk322x_clk_set_parent,
};
-static int rk322x_clk_ofdata_to_platdata(struct udevice *dev)
+static int rk322x_clk_of_to_plat(struct udevice *dev)
{
struct rk322x_clk_priv *priv = dev_get_priv(dev);
@@ -510,7 +511,7 @@ static int rk322x_clk_bind(struct udevice *dev)
cru_glb_srst_fst_value);
priv->glb_srst_snd_value = offsetof(struct rk322x_cru,
cru_glb_srst_snd_value);
- sys_child->priv = priv;
+ dev_set_priv(sys_child, priv);
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
@@ -532,8 +533,8 @@ U_BOOT_DRIVER(rockchip_rk322x_cru) = {
.name = "clk_rk322x",
.id = UCLASS_CLK,
.of_match = rk322x_clk_ids,
- .priv_auto_alloc_size = sizeof(struct rk322x_clk_priv),
- .ofdata_to_platdata = rk322x_clk_ofdata_to_platdata,
+ .priv_auto = sizeof(struct rk322x_clk_priv),
+ .of_to_plat = rk322x_clk_of_to_plat,
.ops = &rk322x_clk_ops,
.bind = rk322x_clk_bind,
.probe = rk322x_clk_probe,
diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
index a1dd642eef..6226d55658 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -954,7 +954,7 @@ static struct clk_ops rk3288_clk_ops = {
#endif
};
-static int rk3288_clk_ofdata_to_platdata(struct udevice *dev)
+static int rk3288_clk_of_to_plat(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3288_clk_priv *priv = dev_get_priv(dev);
@@ -975,7 +975,7 @@ static int rk3288_clk_probe(struct udevice *dev)
return PTR_ERR(priv->grf);
#ifdef CONFIG_SPL_BUILD
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- struct rk3288_clk_plat *plat = dev_get_platdata(dev);
+ struct rk3288_clk_plat *plat = dev_get_plat(dev);
priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
#endif
@@ -1018,7 +1018,7 @@ static int rk3288_clk_bind(struct udevice *dev)
cru_glb_srst_fst_value);
priv->glb_srst_snd_value = offsetof(struct rockchip_cru,
cru_glb_srst_snd_value);
- sys_child->priv = priv;
+ dev_set_priv(sys_child, priv);
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
@@ -1040,10 +1040,10 @@ U_BOOT_DRIVER(rockchip_rk3288_cru) = {
.name = "rockchip_rk3288_cru",
.id = UCLASS_CLK,
.of_match = rk3288_clk_ids,
- .priv_auto_alloc_size = sizeof(struct rk3288_clk_priv),
- .platdata_auto_alloc_size = sizeof(struct rk3288_clk_plat),
+ .priv_auto = sizeof(struct rk3288_clk_priv),
+ .plat_auto = sizeof(struct rk3288_clk_plat),
.ops = &rk3288_clk_ops,
.bind = rk3288_clk_bind,
- .ofdata_to_platdata = rk3288_clk_ofdata_to_platdata,
+ .of_to_plat = rk3288_clk_of_to_plat,
.probe = rk3288_clk_probe,
};
diff --git a/drivers/clk/rockchip/clk_rk3308.c b/drivers/clk/rockchip/clk_rk3308.c
index d3633b6979..a05efcfbab 100644
--- a/drivers/clk/rockchip/clk_rk3308.c
+++ b/drivers/clk/rockchip/clk_rk3308.c
@@ -15,6 +15,7 @@
#include <asm/arch/cru_rk3308.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/hardware.h>
+#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3308-cru.h>
#include <linux/bitops.h>
@@ -1019,7 +1020,7 @@ static int rk3308_clk_probe(struct udevice *dev)
return ret;
}
-static int rk3308_clk_ofdata_to_platdata(struct udevice *dev)
+static int rk3308_clk_of_to_plat(struct udevice *dev)
{
struct rk3308_clk_priv *priv = dev_get_priv(dev);
@@ -1045,7 +1046,7 @@ static int rk3308_clk_bind(struct udevice *dev)
glb_srst_fst);
priv->glb_srst_snd_value = offsetof(struct rk3308_cru,
glb_srst_snd);
- sys_child->priv = priv;
+ dev_set_priv(sys_child, priv);
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
@@ -1067,8 +1068,8 @@ U_BOOT_DRIVER(rockchip_rk3308_cru) = {
.name = "rockchip_rk3308_cru",
.id = UCLASS_CLK,
.of_match = rk3308_clk_ids,
- .priv_auto_alloc_size = sizeof(struct rk3308_clk_priv),
- .ofdata_to_platdata = rk3308_clk_ofdata_to_platdata,
+ .priv_auto = sizeof(struct rk3308_clk_priv),
+ .of_to_plat = rk3308_clk_of_to_plat,
.ops = &rk3308_clk_ops,
.bind = rk3308_clk_bind,
.probe = rk3308_clk_probe,
diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c
index bf4f1069ea..b825ff4cf8 100644
--- a/drivers/clk/rockchip/clk_rk3328.c
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -16,6 +16,7 @@
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/grf_rk3328.h>
#include <asm/io.h>
+#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3328-cru.h>
#include <linux/bitops.h>
@@ -797,7 +798,7 @@ static int rk3328_clk_probe(struct udevice *dev)
return 0;
}
-static int rk3328_clk_ofdata_to_platdata(struct udevice *dev)
+static int rk3328_clk_of_to_plat(struct udevice *dev)
{
struct rk3328_clk_priv *priv = dev_get_priv(dev);
@@ -823,7 +824,7 @@ static int rk3328_clk_bind(struct udevice *dev)
glb_srst_fst_value);
priv->glb_srst_snd_value = offsetof(struct rk3328_cru,
glb_srst_snd_value);
- sys_child->priv = priv;
+ dev_set_priv(sys_child, priv);
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
@@ -845,8 +846,8 @@ U_BOOT_DRIVER(rockchip_rk3328_cru) = {
.name = "rockchip_rk3328_cru",
.id = UCLASS_CLK,
.of_match = rk3328_clk_ids,
- .priv_auto_alloc_size = sizeof(struct rk3328_clk_priv),
- .ofdata_to_platdata = rk3328_clk_ofdata_to_platdata,
+ .priv_auto = sizeof(struct rk3328_clk_priv),
+ .of_to_plat = rk3328_clk_of_to_plat,
.ops = &rk3328_clk_ops,
.bind = rk3328_clk_bind,
.probe = rk3328_clk_probe,
diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
index d1804c6e16..780b49ccd8 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -19,6 +19,7 @@
#include <asm/arch-rockchip/cru_rk3368.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/io.h>
+#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3368-cru.h>
#include <linux/delay.h>
@@ -582,7 +583,7 @@ static int rk3368_clk_probe(struct udevice *dev)
{
struct rk3368_clk_priv __maybe_unused *priv = dev_get_priv(dev);
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- struct rk3368_clk_plat *plat = dev_get_platdata(dev);
+ struct rk3368_clk_plat *plat = dev_get_plat(dev);
priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
#endif
@@ -593,7 +594,7 @@ static int rk3368_clk_probe(struct udevice *dev)
return 0;
}
-static int rk3368_clk_ofdata_to_platdata(struct udevice *dev)
+static int rk3368_clk_of_to_plat(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3368_clk_priv *priv = dev_get_priv(dev);
@@ -621,7 +622,7 @@ static int rk3368_clk_bind(struct udevice *dev)
glb_srst_fst_val);
priv->glb_srst_snd_value = offsetof(struct rk3368_cru,
glb_srst_snd_val);
- sys_child->priv = priv;
+ dev_set_priv(sys_child, priv);
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
@@ -643,11 +644,11 @@ U_BOOT_DRIVER(rockchip_rk3368_cru) = {
.name = "rockchip_rk3368_cru",
.id = UCLASS_CLK,
.of_match = rk3368_clk_ids,
- .priv_auto_alloc_size = sizeof(struct rk3368_clk_priv),
+ .priv_auto = sizeof(struct rk3368_clk_priv),
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- .platdata_auto_alloc_size = sizeof(struct rk3368_clk_plat),
+ .plat_auto = sizeof(struct rk3368_clk_plat),
#endif
- .ofdata_to_platdata = rk3368_clk_ofdata_to_platdata,
+ .of_to_plat = rk3368_clk_of_to_plat,
.ops = &rk3368_clk_ops,
.bind = rk3368_clk_bind,
.probe = rk3368_clk_probe,
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 3fd863e7bd..55ebac7057 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -18,6 +18,7 @@
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru.h>
#include <asm/arch-rockchip/hardware.h>
+#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3399-cru.h>
#include <linux/bitops.h>
@@ -1378,7 +1379,7 @@ static int rk3399_clk_probe(struct udevice *dev)
bool init_clocks = false;
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- struct rk3399_clk_plat *plat = dev_get_platdata(dev);
+ struct rk3399_clk_plat *plat = dev_get_plat(dev);
priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
#endif
@@ -1398,7 +1399,7 @@ static int rk3399_clk_probe(struct udevice *dev)
return 0;
}
-static int rk3399_clk_ofdata_to_platdata(struct udevice *dev)
+static int rk3399_clk_of_to_plat(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3399_clk_priv *priv = dev_get_priv(dev);
@@ -1425,7 +1426,7 @@ static int rk3399_clk_bind(struct udevice *dev)
glb_srst_fst_value);
priv->glb_srst_snd_value = offsetof(struct rockchip_cru,
glb_srst_snd_value);
- sys_child->priv = priv;
+ dev_set_priv(sys_child, priv);
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
@@ -1447,13 +1448,13 @@ U_BOOT_DRIVER(clk_rk3399) = {
.name = "rockchip_rk3399_cru",
.id = UCLASS_CLK,
.of_match = rk3399_clk_ids,
- .priv_auto_alloc_size = sizeof(struct rk3399_clk_priv),
- .ofdata_to_platdata = rk3399_clk_ofdata_to_platdata,
+ .priv_auto = sizeof(struct rk3399_clk_priv),
+ .of_to_plat = rk3399_clk_of_to_plat,
.ops = &rk3399_clk_ops,
.bind = rk3399_clk_bind,
.probe = rk3399_clk_probe,
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- .platdata_auto_alloc_size = sizeof(struct rk3399_clk_plat),
+ .plat_auto = sizeof(struct rk3399_clk_plat),
#endif
};
@@ -1599,7 +1600,7 @@ static int rk3399_pmuclk_probe(struct udevice *dev)
#endif
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev);
+ struct rk3399_pmuclk_plat *plat = dev_get_plat(dev);
priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
#endif
@@ -1610,7 +1611,7 @@ static int rk3399_pmuclk_probe(struct udevice *dev)
return 0;
}
-static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev)
+static int rk3399_pmuclk_of_to_plat(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
@@ -1642,12 +1643,12 @@ U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = {
.name = "rockchip_rk3399_pmucru",
.id = UCLASS_CLK,
.of_match = rk3399_pmuclk_ids,
- .priv_auto_alloc_size = sizeof(struct rk3399_pmuclk_priv),
- .ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata,
+ .priv_auto = sizeof(struct rk3399_pmuclk_priv),
+ .of_to_plat = rk3399_pmuclk_of_to_plat,
.ops = &rk3399_pmuclk_ops,
.probe = rk3399_pmuclk_probe,
.bind = rk3399_pmuclk_bind,
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- .platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat),
+ .plat_auto = sizeof(struct rk3399_pmuclk_plat),
#endif
};
diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c
index aa1d98ca2a..1e22db0cb7 100644
--- a/drivers/clk/rockchip/clk_rv1108.c
+++ b/drivers/clk/rockchip/clk_rv1108.c
@@ -16,6 +16,7 @@
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rv1108.h>
#include <asm/arch-rockchip/hardware.h>
+#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rv1108-cru.h>
#include <linux/delay.h>
@@ -662,7 +663,7 @@ static void rkclk_init(struct rv1108_cru *cru)
aclk_bus, aclk_peri, hclk_peri, pclk_peri);
}
-static int rv1108_clk_ofdata_to_platdata(struct udevice *dev)
+static int rv1108_clk_of_to_plat(struct udevice *dev)
{
struct rv1108_clk_priv *priv = dev_get_priv(dev);
@@ -697,7 +698,7 @@ static int rv1108_clk_bind(struct udevice *dev)
glb_srst_fst_val);
priv->glb_srst_snd_value = offsetof(struct rv1108_cru,
glb_srst_snd_val);
- sys_child->priv = priv;
+ dev_set_priv(sys_child, priv);
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
@@ -719,9 +720,9 @@ U_BOOT_DRIVER(clk_rv1108) = {
.name = "clk_rv1108",
.id = UCLASS_CLK,
.of_match = rv1108_clk_ids,
- .priv_auto_alloc_size = sizeof(struct rv1108_clk_priv),
+ .priv_auto = sizeof(struct rv1108_clk_priv),
.ops = &rv1108_clk_ops,
.bind = rv1108_clk_bind,
- .ofdata_to_platdata = rv1108_clk_ofdata_to_platdata,
+ .of_to_plat = rv1108_clk_of_to_plat,
.probe = rv1108_clk_probe,
};
diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
index 1b4d81d4f0..b3882d0b77 100644
--- a/drivers/clk/sifive/fu540-prci.c
+++ b/drivers/clk/sifive/fu540-prci.c
@@ -537,7 +537,7 @@ static int __prci_consumer_reset(const char *rst_name, bool trigger)
int ret;
ret = uclass_get_device_by_driver(UCLASS_RESET,
- DM_GET_DRIVER(sifive_reset),
+ DM_DRIVER_GET(sifive_reset),
&dev);
if (ret) {
dev_err(dev, "Reset driver not found: %d\n", ret);
@@ -807,6 +807,6 @@ U_BOOT_DRIVER(sifive_fu540_prci) = {
.of_match = sifive_fu540_prci_ids,
.probe = sifive_fu540_prci_probe,
.ops = &sifive_fu540_prci_ops,
- .priv_auto_alloc_size = sizeof(struct __prci_data),
+ .priv_auto = sizeof(struct __prci_data),
.bind = sifive_fu540_clk_bind,
};
diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c
index 67507c5ab1..1b5de86e20 100644
--- a/drivers/clk/sunxi/clk_a10.c
+++ b/drivers/clk/sunxi/clk_a10.c
@@ -79,7 +79,7 @@ U_BOOT_DRIVER(clk_sun4i_a10) = {
.name = "sun4i_a10_ccu",
.id = UCLASS_CLK,
.of_match = a10_ccu_ids,
- .priv_auto_alloc_size = sizeof(struct ccu_priv),
+ .priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = a10_clk_bind,
diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c
index d11a4b5f03..184f61ab23 100644
--- a/drivers/clk/sunxi/clk_a10s.c
+++ b/drivers/clk/sunxi/clk_a10s.c
@@ -66,7 +66,7 @@ U_BOOT_DRIVER(clk_sun5i_a10s) = {
.name = "sun5i_a10s_ccu",
.id = UCLASS_CLK,
.of_match = a10s_ccu_ids,
- .priv_auto_alloc_size = sizeof(struct ccu_priv),
+ .priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = a10s_clk_bind,
diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c
index 4d562bfe42..5750514a74 100644
--- a/drivers/clk/sunxi/clk_a23.c
+++ b/drivers/clk/sunxi/clk_a23.c
@@ -82,7 +82,7 @@ U_BOOT_DRIVER(clk_sun8i_a23) = {
.name = "sun8i_a23_ccu",
.id = UCLASS_CLK,
.of_match = a23_clk_ids,
- .priv_auto_alloc_size = sizeof(struct ccu_priv),
+ .priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = a23_clk_bind,
diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
index 4a9454eebe..9226112f4a 100644
--- a/drivers/clk/sunxi/clk_a31.c
+++ b/drivers/clk/sunxi/clk_a31.c
@@ -99,7 +99,7 @@ U_BOOT_DRIVER(clk_sun6i_a31) = {
.name = "sun6i_a31_ccu",
.id = UCLASS_CLK,
.of_match = a31_clk_ids,
- .priv_auto_alloc_size = sizeof(struct ccu_priv),
+ .priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = a31_clk_bind,
diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
index d96cb1aac1..0553ffa439 100644
--- a/drivers/clk/sunxi/clk_a64.c
+++ b/drivers/clk/sunxi/clk_a64.c
@@ -87,7 +87,7 @@ U_BOOT_DRIVER(clk_sun50i_a64) = {
.name = "sun50i_a64_ccu",
.id = UCLASS_CLK,
.of_match = a64_ccu_ids,
- .priv_auto_alloc_size = sizeof(struct ccu_priv),
+ .priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = a64_clk_bind,
diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c
index 80d7407037..68973d528e 100644
--- a/drivers/clk/sunxi/clk_a80.c
+++ b/drivers/clk/sunxi/clk_a80.c
@@ -94,7 +94,7 @@ U_BOOT_DRIVER(clk_sun9i_a80) = {
.name = "sun9i_a80_ccu",
.id = UCLASS_CLK,
.of_match = a80_ccu_ids,
- .priv_auto_alloc_size = sizeof(struct ccu_priv),
+ .priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = a80_clk_bind,
diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c
index d6f23ddc77..880c7d7599 100644
--- a/drivers/clk/sunxi/clk_a83t.c
+++ b/drivers/clk/sunxi/clk_a83t.c
@@ -84,7 +84,7 @@ U_BOOT_DRIVER(clk_sun8i_a83t) = {
.name = "sun8i_a83t_ccu",
.id = UCLASS_CLK,
.of_match = a83t_clk_ids,
- .priv_auto_alloc_size = sizeof(struct ccu_priv),
+ .priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = a83t_clk_bind,
diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
index 7e844f4ff1..f81633b92d 100644
--- a/drivers/clk/sunxi/clk_h3.c
+++ b/drivers/clk/sunxi/clk_h3.c
@@ -102,7 +102,7 @@ U_BOOT_DRIVER(clk_sun8i_h3) = {
.name = "sun8i_h3_ccu",
.id = UCLASS_CLK,
.of_match = h3_ccu_ids,
- .priv_auto_alloc_size = sizeof(struct ccu_priv),
+ .priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = h3_clk_bind,
diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c
index a1cb8952d3..ac8656fe89 100644
--- a/drivers/clk/sunxi/clk_h6.c
+++ b/drivers/clk/sunxi/clk_h6.c
@@ -95,7 +95,7 @@ U_BOOT_DRIVER(clk_sun50i_h6) = {
.name = "sun50i_h6_ccu",
.id = UCLASS_CLK,
.of_match = h6_ccu_ids,
- .priv_auto_alloc_size = sizeof(struct ccu_priv),
+ .priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = h6_clk_bind,
diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c
index ac360b2beb..ee1e86d22e 100644
--- a/drivers/clk/sunxi/clk_r40.c
+++ b/drivers/clk/sunxi/clk_r40.c
@@ -107,7 +107,7 @@ U_BOOT_DRIVER(clk_sun8i_r40) = {
.name = "sun8i_r40_ccu",
.id = UCLASS_CLK,
.of_match = r40_clk_ids,
- .priv_auto_alloc_size = sizeof(struct ccu_priv),
+ .priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = r40_clk_bind,
diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c
index f3fc06ab31..29622199fd 100644
--- a/drivers/clk/sunxi/clk_v3s.c
+++ b/drivers/clk/sunxi/clk_v3s.c
@@ -65,7 +65,7 @@ U_BOOT_DRIVER(clk_sun8i_v3s) = {
.name = "sun8i_v3s_ccu",
.id = UCLASS_CLK,
.of_match = v3s_clk_ids,
- .priv_auto_alloc_size = sizeof(struct ccu_priv),
+ .priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = v3s_clk_bind,
diff --git a/drivers/clk/ti/Kconfig b/drivers/clk/ti/Kconfig
new file mode 100644
index 0000000000..2dc86d44a9
--- /dev/null
+++ b/drivers/clk/ti/Kconfig
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
+#
+
+config CLK_TI_AM3_DPLL
+ bool "TI AM33XX Digital Phase-Locked Loop (DPLL) clock drivers"
+ depends on CLK && OF_CONTROL
+ help
+ This enables the DPLL clock drivers support on AM33XX SoCs. The DPLL
+ provides all interface clocks and functional clocks to the processor.
+
+config CLK_TI_CTRL
+ bool "TI OMAP4 clock controller"
+ depends on CLK && OF_CONTROL
+ help
+ This enables the clock controller driver support on TI's SoCs.
+
+config CLK_TI_DIVIDER
+ bool "TI divider clock driver"
+ depends on CLK && OF_CONTROL && CLK_CCF
+ help
+ This enables the divider clock driver support on TI's SoCs.
+
+config CLK_TI_GATE
+ bool "TI gate clock driver"
+ depends on CLK && OF_CONTROL
+ help
+ This enables the gate clock driver support on TI's SoCs.
+
+config CLK_TI_MUX
+ bool "TI mux clock driver"
+ depends on CLK && OF_CONTROL && CLK_CCF
+ help
+ This enables the mux clock driver support on TI's SoCs.
+
+config CLK_TI_SCI
+ bool "TI System Control Interface (TI SCI) clock driver"
+ depends on CLK && TI_SCI_PROTOCOL && OF_CONTROL
+ help
+ This enables the clock driver support over TI System Control Interface
+ available on some new TI's SoCs. If you wish to use clock resources
+ managed by the TI System Controller, say Y here. Otherwise, say N.
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
new file mode 100644
index 0000000000..9f56b47736
--- /dev/null
+++ b/drivers/clk/ti/Makefile
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
+#
+
+obj-$(CONFIG_ARCH_OMAP2PLUS) += clk.o omap4-cm.o
+
+obj-$(CONFIG_CLK_TI_AM3_DPLL) += clk-am3-dpll.o clk-am3-dpll-x2.o
+obj-$(CONFIG_CLK_TI_CTRL) += clk-ctrl.o
+obj-$(CONFIG_CLK_TI_DIVIDER) += clk-divider.o
+obj-$(CONFIG_CLK_TI_GATE) += clk-gate.o
+obj-$(CONFIG_CLK_TI_MUX) += clk-mux.o
+obj-$(CONFIG_CLK_TI_SCI) += clk-sci.o
diff --git a/drivers/clk/ti/clk-am3-dpll-x2.c b/drivers/clk/ti/clk-am3-dpll-x2.c
new file mode 100644
index 0000000000..3cf279d6a3
--- /dev/null
+++ b/drivers/clk/ti/clk-am3-dpll-x2.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * TI DPLL x2 clock support
+ *
+ * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
+ *
+ * Loosely based on Linux kernel drivers/clk/ti/dpll.c
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <linux/clk-provider.h>
+
+struct clk_ti_am3_dpll_x2_priv {
+ struct clk parent;
+};
+
+static ulong clk_ti_am3_dpll_x2_get_rate(struct clk *clk)
+{
+ struct clk_ti_am3_dpll_x2_priv *priv = dev_get_priv(clk->dev);
+ unsigned long rate;
+
+ rate = clk_get_rate(&priv->parent);
+ if (IS_ERR_VALUE(rate))
+ return rate;
+
+ rate *= 2;
+ dev_dbg(clk->dev, "rate=%ld\n", rate);
+ return rate;
+}
+
+const struct clk_ops clk_ti_am3_dpll_x2_ops = {
+ .get_rate = clk_ti_am3_dpll_x2_get_rate,
+};
+
+static int clk_ti_am3_dpll_x2_remove(struct udevice *dev)
+{
+ struct clk_ti_am3_dpll_x2_priv *priv = dev_get_priv(dev);
+ int err;
+
+ err = clk_release_all(&priv->parent, 1);
+ if (err) {
+ dev_err(dev, "failed to release parent clock\n");
+ return err;
+ }
+
+ return 0;
+}
+
+static int clk_ti_am3_dpll_x2_probe(struct udevice *dev)
+{
+ struct clk_ti_am3_dpll_x2_priv *priv = dev_get_priv(dev);
+ int err;
+
+ err = clk_get_by_index(dev, 0, &priv->parent);
+ if (err) {
+ dev_err(dev, "%s: failed to get parent clock\n", __func__);
+ return err;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id clk_ti_am3_dpll_x2_of_match[] = {
+ {.compatible = "ti,am3-dpll-x2-clock"},
+ {}
+};
+
+U_BOOT_DRIVER(clk_ti_am3_dpll_x2) = {
+ .name = "ti_am3_dpll_x2_clock",
+ .id = UCLASS_CLK,
+ .of_match = clk_ti_am3_dpll_x2_of_match,
+ .probe = clk_ti_am3_dpll_x2_probe,
+ .remove = clk_ti_am3_dpll_x2_remove,
+ .priv_auto = sizeof(struct clk_ti_am3_dpll_x2_priv),
+ .ops = &clk_ti_am3_dpll_x2_ops,
+};
diff --git a/drivers/clk/ti/clk-am3-dpll.c b/drivers/clk/ti/clk-am3-dpll.c
new file mode 100644
index 0000000000..7916a24538
--- /dev/null
+++ b/drivers/clk/ti/clk-am3-dpll.c
@@ -0,0 +1,268 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * TI DPLL clock support
+ *
+ * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
+ *
+ * Loosely based on Linux kernel drivers/clk/ti/dpll.c
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <clk-uclass.h>
+#include <div64.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <hang.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+
+struct clk_ti_am3_dpll_drv_data {
+ ulong max_rate;
+};
+
+struct clk_ti_am3_dpll_priv {
+ fdt_addr_t clkmode_reg;
+ fdt_addr_t idlest_reg;
+ fdt_addr_t clksel_reg;
+ struct clk clk_bypass;
+ struct clk clk_ref;
+ u16 last_rounded_mult;
+ u8 last_rounded_div;
+ ulong max_rate;
+};
+
+static ulong clk_ti_am3_dpll_round_rate(struct clk *clk, ulong rate)
+{
+ struct clk_ti_am3_dpll_priv *priv = dev_get_priv(clk->dev);
+ ulong ret, ref_rate, r;
+ int m, d, err_min, err;
+ int mult = INT_MAX, div = INT_MAX;
+
+ if (priv->max_rate && rate > priv->max_rate) {
+ dev_warn(clk->dev, "%ld is to high a rate, lowered to %ld\n",
+ rate, priv->max_rate);
+ rate = priv->max_rate;
+ }
+
+ ret = -EFAULT;
+ err = rate;
+ err_min = rate;
+ ref_rate = clk_get_rate(&priv->clk_ref);
+ for (d = 1; err_min && d <= 128; d++) {
+ for (m = 2; m <= 2047; m++) {
+ r = (ref_rate * m) / d;
+ err = abs(r - rate);
+ if (err < err_min) {
+ err_min = err;
+ ret = r;
+ mult = m;
+ div = d;
+
+ if (err == 0)
+ break;
+ } else if (r > rate) {
+ break;
+ }
+ }
+ }
+
+ priv->last_rounded_mult = mult;
+ priv->last_rounded_div = div;
+ dev_dbg(clk->dev, "rate=%ld, best_rate=%ld, mult=%d, div=%d\n", rate,
+ ret, mult, div);
+ return ret;
+}
+
+static ulong clk_ti_am3_dpll_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk_ti_am3_dpll_priv *priv = dev_get_priv(clk->dev);
+ u32 v;
+ ulong round_rate;
+
+ round_rate = clk_ti_am3_dpll_round_rate(clk, rate);
+ if (IS_ERR_VALUE(round_rate))
+ return round_rate;
+
+ v = readl(priv->clksel_reg);
+
+ /* enter bypass mode */
+ clrsetbits_le32(priv->clkmode_reg, CM_CLKMODE_DPLL_DPLL_EN_MASK,
+ DPLL_EN_MN_BYPASS << CM_CLKMODE_DPLL_EN_SHIFT);
+
+ /* wait for bypass mode */
+ if (!wait_on_value(ST_DPLL_CLK_MASK, 0,
+ (void *)priv->idlest_reg, LDELAY))
+ dev_err(clk->dev, "failed bypassing dpll\n");
+
+ /* set M & N */
+ v &= ~CM_CLKSEL_DPLL_M_MASK;
+ v |= (priv->last_rounded_mult << CM_CLKSEL_DPLL_M_SHIFT) &
+ CM_CLKSEL_DPLL_M_MASK;
+
+ v &= ~CM_CLKSEL_DPLL_N_MASK;
+ v |= ((priv->last_rounded_div - 1) << CM_CLKSEL_DPLL_N_SHIFT) &
+ CM_CLKSEL_DPLL_N_MASK;
+
+ writel(v, priv->clksel_reg);
+
+ /* lock dpll */
+ clrsetbits_le32(priv->clkmode_reg, CM_CLKMODE_DPLL_DPLL_EN_MASK,
+ DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
+
+ /* wait till the dpll locks */
+ if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
+ (void *)priv->idlest_reg, LDELAY)) {
+ dev_err(clk->dev, "failed locking dpll\n");
+ hang();
+ }
+
+ return round_rate;
+}
+
+static ulong clk_ti_am3_dpll_get_rate(struct clk *clk)
+{
+ struct clk_ti_am3_dpll_priv *priv = dev_get_priv(clk->dev);
+ u64 rate;
+ u32 m, n, v;
+
+ /* Return bypass rate if DPLL is bypassed */
+ v = readl(priv->clkmode_reg);
+ v &= CM_CLKMODE_DPLL_EN_MASK;
+ v >>= CM_CLKMODE_DPLL_EN_SHIFT;
+
+ switch (v) {
+ case DPLL_EN_MN_BYPASS:
+ case DPLL_EN_LOW_POWER_BYPASS:
+ case DPLL_EN_FAST_RELOCK_BYPASS:
+ rate = clk_get_rate(&priv->clk_bypass);
+ dev_dbg(clk->dev, "rate=%lld\n", rate);
+ return rate;
+ }
+
+ v = readl(priv->clksel_reg);
+ m = v & CM_CLKSEL_DPLL_M_MASK;
+ m >>= CM_CLKSEL_DPLL_M_SHIFT;
+ n = v & CM_CLKSEL_DPLL_N_MASK;
+ n >>= CM_CLKSEL_DPLL_N_SHIFT;
+
+ rate = clk_get_rate(&priv->clk_ref) * m;
+ do_div(rate, n + 1);
+ dev_dbg(clk->dev, "rate=%lld\n", rate);
+ return rate;
+}
+
+const struct clk_ops clk_ti_am3_dpll_ops = {
+ .round_rate = clk_ti_am3_dpll_round_rate,
+ .get_rate = clk_ti_am3_dpll_get_rate,
+ .set_rate = clk_ti_am3_dpll_set_rate,
+};
+
+static int clk_ti_am3_dpll_remove(struct udevice *dev)
+{
+ struct clk_ti_am3_dpll_priv *priv = dev_get_priv(dev);
+ int err;
+
+ err = clk_release_all(&priv->clk_bypass, 1);
+ if (err) {
+ dev_err(dev, "failed to release bypass clock\n");
+ return err;
+ }
+
+ err = clk_release_all(&priv->clk_ref, 1);
+ if (err) {
+ dev_err(dev, "failed to release reference clock\n");
+ return err;
+ }
+
+ return 0;
+}
+
+static int clk_ti_am3_dpll_probe(struct udevice *dev)
+{
+ struct clk_ti_am3_dpll_priv *priv = dev_get_priv(dev);
+ int err;
+
+ err = clk_get_by_index(dev, 0, &priv->clk_ref);
+ if (err) {
+ dev_err(dev, "failed to get reference clock\n");
+ return err;
+ }
+
+ err = clk_get_by_index(dev, 1, &priv->clk_bypass);
+ if (err) {
+ dev_err(dev, "failed to get bypass clock\n");
+ return err;
+ }
+
+ return 0;
+}
+
+static int clk_ti_am3_dpll_of_to_plat(struct udevice *dev)
+{
+ struct clk_ti_am3_dpll_priv *priv = dev_get_priv(dev);
+ struct clk_ti_am3_dpll_drv_data *data =
+ (struct clk_ti_am3_dpll_drv_data *)dev_get_driver_data(dev);
+
+ priv->max_rate = data->max_rate;
+
+ priv->clkmode_reg = dev_read_addr_index(dev, 0);
+ if (priv->clkmode_reg == FDT_ADDR_T_NONE) {
+ dev_err(dev, "failed to get clkmode register\n");
+ return -EINVAL;
+ }
+
+ dev_dbg(dev, "clkmode_reg=0x%08lx\n", priv->clkmode_reg);
+
+ priv->idlest_reg = dev_read_addr_index(dev, 1);
+ if (priv->idlest_reg == FDT_ADDR_T_NONE) {
+ dev_err(dev, "failed to get idlest register\n");
+ return -EINVAL;
+ }
+
+ dev_dbg(dev, "idlest_reg=0x%08lx\n", priv->idlest_reg);
+
+ priv->clksel_reg = dev_read_addr_index(dev, 2);
+ if (priv->clksel_reg == FDT_ADDR_T_NONE) {
+ dev_err(dev, "failed to get clksel register\n");
+ return -EINVAL;
+ }
+
+ dev_dbg(dev, "clksel_reg=0x%08lx\n", priv->clksel_reg);
+
+ return 0;
+}
+
+static const struct clk_ti_am3_dpll_drv_data dpll_no_gate_data = {
+ .max_rate = 1000000000
+};
+
+static const struct clk_ti_am3_dpll_drv_data dpll_no_gate_j_type_data = {
+ .max_rate = 2000000000
+};
+
+static const struct clk_ti_am3_dpll_drv_data dpll_core_data = {
+ .max_rate = 1000000000
+};
+
+static const struct udevice_id clk_ti_am3_dpll_of_match[] = {
+ {.compatible = "ti,am3-dpll-core-clock",
+ .data = (ulong)&dpll_core_data},
+ {.compatible = "ti,am3-dpll-no-gate-clock",
+ .data = (ulong)&dpll_no_gate_data},
+ {.compatible = "ti,am3-dpll-no-gate-j-type-clock",
+ .data = (ulong)&dpll_no_gate_j_type_data},
+ {}
+};
+
+U_BOOT_DRIVER(clk_ti_am3_dpll) = {
+ .name = "ti_am3_dpll_clock",
+ .id = UCLASS_CLK,
+ .of_match = clk_ti_am3_dpll_of_match,
+ .ofdata_to_platdata = clk_ti_am3_dpll_of_to_plat,
+ .probe = clk_ti_am3_dpll_probe,
+ .remove = clk_ti_am3_dpll_remove,
+ .priv_auto = sizeof(struct clk_ti_am3_dpll_priv),
+ .ops = &clk_ti_am3_dpll_ops,
+};
diff --git a/drivers/clk/ti/clk-ctrl.c b/drivers/clk/ti/clk-ctrl.c
new file mode 100644
index 0000000000..940e8d6caf
--- /dev/null
+++ b/drivers/clk/ti/clk-ctrl.c
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * OMAP clock controller support
+ *
+ * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <clk-uclass.h>
+#include <asm/arch-am33xx/clock.h>
+
+struct clk_ti_ctrl_offs {
+ fdt_addr_t start;
+ fdt_size_t end;
+};
+
+struct clk_ti_ctrl_priv {
+ int offs_num;
+ struct clk_ti_ctrl_offs *offs;
+};
+
+static int clk_ti_ctrl_check_offs(struct clk *clk, fdt_addr_t offs)
+{
+ struct clk_ti_ctrl_priv *priv = dev_get_priv(clk->dev);
+ int i;
+
+ for (i = 0; i < priv->offs_num; i++) {
+ if (offs >= priv->offs[i].start && offs <= priv->offs[i].end)
+ return 0;
+ }
+
+ return -EFAULT;
+}
+
+static int clk_ti_ctrl_disable(struct clk *clk)
+{
+ struct clk_ti_ctrl_priv *priv = dev_get_priv(clk->dev);
+ u32 *clk_modules[2] = { };
+ fdt_addr_t offs;
+ int err;
+
+ offs = priv->offs[0].start + clk->id;
+ err = clk_ti_ctrl_check_offs(clk, offs);
+ if (err) {
+ dev_err(clk->dev, "invalid offset: 0x%lx\n", offs);
+ return err;
+ }
+
+ clk_modules[0] = (u32 *)(offs);
+ dev_dbg(clk->dev, "module address=%p\n", clk_modules[0]);
+ do_disable_clocks(NULL, clk_modules, 1);
+ return 0;
+}
+
+static int clk_ti_ctrl_enable(struct clk *clk)
+{
+ struct clk_ti_ctrl_priv *priv = dev_get_priv(clk->dev);
+ u32 *clk_modules[2] = { };
+ fdt_addr_t offs;
+ int err;
+
+ offs = priv->offs[0].start + clk->id;
+ err = clk_ti_ctrl_check_offs(clk, offs);
+ if (err) {
+ dev_err(clk->dev, "invalid offset: 0x%lx\n", offs);
+ return err;
+ }
+
+ clk_modules[0] = (u32 *)(offs);
+ dev_dbg(clk->dev, "module address=%p\n", clk_modules[0]);
+ do_enable_clocks(NULL, clk_modules, 1);
+ return 0;
+}
+
+static ulong clk_ti_ctrl_get_rate(struct clk *clk)
+{
+ return 0;
+}
+
+static int clk_ti_ctrl_of_xlate(struct clk *clk,
+ struct ofnode_phandle_args *args)
+{
+ if (args->args_count != 2) {
+ dev_err(clk->dev, "invaild args_count: %d\n", args->args_count);
+ return -EINVAL;
+ }
+
+ if (args->args_count)
+ clk->id = args->args[0];
+ else
+ clk->id = 0;
+
+ dev_dbg(clk->dev, "name=%s, id=%ld\n", clk->dev->name, clk->id);
+ return 0;
+}
+
+static int clk_ti_ctrl_of_to_plat(struct udevice *dev)
+{
+ struct clk_ti_ctrl_priv *priv = dev_get_priv(dev);
+ fdt_size_t fdt_size;
+ int i, size;
+
+ size = dev_read_size(dev, "reg");
+ if (size < 0) {
+ dev_err(dev, "failed to get 'reg' size\n");
+ return size;
+ }
+
+ priv->offs_num = size / 2 / sizeof(u32);
+ dev_dbg(dev, "size=%d, regs_num=%d\n", size, priv->offs_num);
+
+ priv->offs = kmalloc_array(priv->offs_num, sizeof(*priv->offs),
+ GFP_KERNEL);
+ if (!priv->offs)
+ return -ENOMEM;
+
+ for (i = 0; i < priv->offs_num; i++) {
+ priv->offs[i].start =
+ dev_read_addr_size_index(dev, i, &fdt_size);
+ if (priv->offs[i].start == FDT_ADDR_T_NONE) {
+ dev_err(dev, "failed to get offset %d\n", i);
+ return -EINVAL;
+ }
+
+ priv->offs[i].end = priv->offs[i].start + fdt_size;
+ dev_dbg(dev, "start=0x%08lx, end=0x%08lx\n",
+ priv->offs[i].start, priv->offs[i].end);
+ }
+
+ return 0;
+}
+
+static struct clk_ops clk_ti_ctrl_ops = {
+ .of_xlate = clk_ti_ctrl_of_xlate,
+ .enable = clk_ti_ctrl_enable,
+ .disable = clk_ti_ctrl_disable,
+ .get_rate = clk_ti_ctrl_get_rate,
+};
+
+static const struct udevice_id clk_ti_ctrl_ids[] = {
+ {.compatible = "ti,clkctrl"},
+ {},
+};
+
+U_BOOT_DRIVER(clk_ti_ctrl) = {
+ .name = "ti_ctrl_clk",
+ .id = UCLASS_CLK,
+ .of_match = clk_ti_ctrl_ids,
+ .ofdata_to_platdata = clk_ti_ctrl_of_to_plat,
+ .ops = &clk_ti_ctrl_ops,
+ .priv_auto = sizeof(struct clk_ti_ctrl_priv),
+};
diff --git a/drivers/clk/ti/clk-divider.c b/drivers/clk/ti/clk-divider.c
new file mode 100644
index 0000000000..a862637785
--- /dev/null
+++ b/drivers/clk/ti/clk-divider.c
@@ -0,0 +1,381 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * TI divider clock support
+ *
+ * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
+ *
+ * Loosely based on Linux kernel drivers/clk/ti/divider.c
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <clk-uclass.h>
+#include <div64.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <asm/io.h>
+#include <linux/clk-provider.h>
+#include <linux/kernel.h>
+#include <linux/log2.h>
+#include "clk.h"
+
+/*
+ * The reverse of DIV_ROUND_UP: The maximum number which
+ * divided by m is r
+ */
+#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
+
+struct clk_ti_divider_priv {
+ struct clk parent;
+ fdt_addr_t reg;
+ const struct clk_div_table *table;
+ u8 shift;
+ u8 flags;
+ u8 div_flags;
+ s8 latch;
+ u16 min;
+ u16 max;
+ u16 mask;
+};
+
+static unsigned int _get_div(const struct clk_div_table *table, ulong flags,
+ unsigned int val)
+{
+ if (flags & CLK_DIVIDER_ONE_BASED)
+ return val;
+
+ if (flags & CLK_DIVIDER_POWER_OF_TWO)
+ return 1 << val;
+
+ if (table)
+ return clk_divider_get_table_div(table, val);
+
+ return val + 1;
+}
+
+static unsigned int _get_val(const struct clk_div_table *table, ulong flags,
+ unsigned int div)
+{
+ if (flags & CLK_DIVIDER_ONE_BASED)
+ return div;
+
+ if (flags & CLK_DIVIDER_POWER_OF_TWO)
+ return __ffs(div);
+
+ if (table)
+ return clk_divider_get_table_val(table, div);
+
+ return div - 1;
+}
+
+static int _div_round_up(const struct clk_div_table *table, ulong parent_rate,
+ ulong rate)
+{
+ const struct clk_div_table *clkt;
+ int up = INT_MAX;
+ int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
+
+ for (clkt = table; clkt->div; clkt++) {
+ if (clkt->div == div)
+ return clkt->div;
+ else if (clkt->div < div)
+ continue;
+
+ if ((clkt->div - div) < (up - div))
+ up = clkt->div;
+ }
+
+ return up;
+}
+
+static int _div_round(const struct clk_div_table *table, ulong parent_rate,
+ ulong rate)
+{
+ if (table)
+ return _div_round_up(table, parent_rate, rate);
+
+ return DIV_ROUND_UP(parent_rate, rate);
+}
+
+static int clk_ti_divider_best_div(struct clk *clk, ulong rate,
+ ulong *best_parent_rate)
+{
+ struct clk_ti_divider_priv *priv = dev_get_priv(clk->dev);
+ ulong parent_rate, parent_round_rate, max_div;
+ ulong best_rate, r;
+ int i, best_div = 0;
+
+ parent_rate = clk_get_rate(&priv->parent);
+ if (IS_ERR_VALUE(parent_rate))
+ return parent_rate;
+
+ if (!rate)
+ rate = 1;
+
+ if (!(clk->flags & CLK_SET_RATE_PARENT)) {
+ best_div = _div_round(priv->table, parent_rate, rate);
+ if (best_div == 0)
+ best_div = 1;
+
+ if (best_div > priv->max)
+ best_div = priv->max;
+
+ *best_parent_rate = parent_rate;
+ return best_div;
+ }
+
+ max_div = min(ULONG_MAX / rate, (ulong)priv->max);
+ for (best_rate = 0, i = 1; i <= max_div; i++) {
+ if (!clk_divider_is_valid_div(priv->table, priv->div_flags, i))
+ continue;
+
+ /*
+ * It's the most ideal case if the requested rate can be
+ * divided from parent clock without needing to change
+ * parent rate, so return the divider immediately.
+ */
+ if ((rate * i) == parent_rate) {
+ *best_parent_rate = parent_rate;
+ dev_dbg(clk->dev, "rate=%ld, best_rate=%ld, div=%d\n",
+ rate, rate, i);
+ return i;
+ }
+
+ parent_round_rate = clk_round_rate(&priv->parent,
+ MULT_ROUND_UP(rate, i));
+ if (IS_ERR_VALUE(parent_round_rate))
+ continue;
+
+ r = DIV_ROUND_UP(parent_round_rate, i);
+ if (r <= rate && r > best_rate) {
+ best_div = i;
+ best_rate = r;
+ *best_parent_rate = parent_round_rate;
+ if (best_rate == rate)
+ break;
+ }
+ }
+
+ if (best_div == 0) {
+ best_div = priv->max;
+ parent_round_rate = clk_round_rate(&priv->parent, 1);
+ if (IS_ERR_VALUE(parent_round_rate))
+ return parent_round_rate;
+ }
+
+ dev_dbg(clk->dev, "rate=%ld, best_rate=%ld, div=%d\n", rate, best_rate,
+ best_div);
+
+ return best_div;
+}
+
+static ulong clk_ti_divider_round_rate(struct clk *clk, ulong rate)
+{
+ ulong parent_rate;
+ int div;
+
+ div = clk_ti_divider_best_div(clk, rate, &parent_rate);
+ if (div < 0)
+ return div;
+
+ return DIV_ROUND_UP(parent_rate, div);
+}
+
+static ulong clk_ti_divider_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk_ti_divider_priv *priv = dev_get_priv(clk->dev);
+ ulong parent_rate;
+ int div;
+ u32 val, v;
+
+ div = clk_ti_divider_best_div(clk, rate, &parent_rate);
+ if (div < 0)
+ return div;
+
+ if (clk->flags & CLK_SET_RATE_PARENT) {
+ parent_rate = clk_set_rate(&priv->parent, parent_rate);
+ if (IS_ERR_VALUE(parent_rate))
+ return parent_rate;
+ }
+
+ val = _get_val(priv->table, priv->div_flags, div);
+
+ v = readl(priv->reg);
+ v &= ~(priv->mask << priv->shift);
+ v |= val << priv->shift;
+ writel(v, priv->reg);
+ clk_ti_latch(priv->reg, priv->latch);
+
+ return clk_get_rate(clk);
+}
+
+static ulong clk_ti_divider_get_rate(struct clk *clk)
+{
+ struct clk_ti_divider_priv *priv = dev_get_priv(clk->dev);
+ ulong rate, parent_rate;
+ unsigned int div;
+ u32 v;
+
+ parent_rate = clk_get_rate(&priv->parent);
+ if (IS_ERR_VALUE(parent_rate))
+ return parent_rate;
+
+ v = readl(priv->reg) >> priv->shift;
+ v &= priv->mask;
+
+ div = _get_div(priv->table, priv->div_flags, v);
+ if (!div) {
+ if (!(priv->div_flags & CLK_DIVIDER_ALLOW_ZERO))
+ dev_warn(clk->dev,
+ "zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n");
+ return parent_rate;
+ }
+
+ rate = DIV_ROUND_UP(parent_rate, div);
+ dev_dbg(clk->dev, "rate=%ld\n", rate);
+ return rate;
+}
+
+static int clk_ti_divider_request(struct clk *clk)
+{
+ struct clk_ti_divider_priv *priv = dev_get_priv(clk->dev);
+
+ clk->flags = priv->flags;
+ return 0;
+}
+
+const struct clk_ops clk_ti_divider_ops = {
+ .request = clk_ti_divider_request,
+ .round_rate = clk_ti_divider_round_rate,
+ .get_rate = clk_ti_divider_get_rate,
+ .set_rate = clk_ti_divider_set_rate
+};
+
+static int clk_ti_divider_remove(struct udevice *dev)
+{
+ struct clk_ti_divider_priv *priv = dev_get_priv(dev);
+ int err;
+
+ err = clk_release_all(&priv->parent, 1);
+ if (err) {
+ dev_err(dev, "failed to release parent clock\n");
+ return err;
+ }
+
+ return 0;
+}
+
+static int clk_ti_divider_probe(struct udevice *dev)
+{
+ struct clk_ti_divider_priv *priv = dev_get_priv(dev);
+ int err;
+
+ err = clk_get_by_index(dev, 0, &priv->parent);
+ if (err) {
+ dev_err(dev, "failed to get parent clock\n");
+ return err;
+ }
+
+ return 0;
+}
+
+static int clk_ti_divider_of_to_plat(struct udevice *dev)
+{
+ struct clk_ti_divider_priv *priv = dev_get_priv(dev);
+ struct clk_div_table *table = NULL;
+ u32 val, valid_div;
+ u32 min_div = 0;
+ u32 max_val, max_div = 0;
+ u16 mask;
+ int i, div_num;
+
+ priv->reg = dev_read_addr(dev);
+ dev_dbg(dev, "reg=0x%08lx\n", priv->reg);
+ priv->shift = dev_read_u32_default(dev, "ti,bit-shift", 0);
+ priv->latch = dev_read_s32_default(dev, "ti,latch-bit", -EINVAL);
+ if (dev_read_bool(dev, "ti,index-starts-at-one"))
+ priv->div_flags |= CLK_DIVIDER_ONE_BASED;
+
+ if (dev_read_bool(dev, "ti,index-power-of-two"))
+ priv->div_flags |= CLK_DIVIDER_POWER_OF_TWO;
+
+ if (dev_read_bool(dev, "ti,set-rate-parent"))
+ priv->flags |= CLK_SET_RATE_PARENT;
+
+ if (dev_read_prop(dev, "ti,dividers", &div_num)) {
+ div_num /= sizeof(u32);
+
+ /* Determine required size for divider table */
+ for (i = 0, valid_div = 0; i < div_num; i++) {
+ dev_read_u32_index(dev, "ti,dividers", i, &val);
+ if (val)
+ valid_div++;
+ }
+
+ if (!valid_div) {
+ dev_err(dev, "no valid dividers\n");
+ return -EINVAL;
+ }
+
+ table = calloc(valid_div + 1, sizeof(*table));
+ if (!table)
+ return -ENOMEM;
+
+ for (i = 0, valid_div = 0; i < div_num; i++) {
+ dev_read_u32_index(dev, "ti,dividers", i, &val);
+ if (!val)
+ continue;
+
+ table[valid_div].div = val;
+ table[valid_div].val = i;
+ valid_div++;
+ if (val > max_div)
+ max_div = val;
+
+ if (!min_div || val < min_div)
+ min_div = val;
+ }
+
+ max_val = max_div;
+ } else {
+ /* Divider table not provided, determine min/max divs */
+ min_div = dev_read_u32_default(dev, "ti,min-div", 1);
+ if (dev_read_u32(dev, "ti,max-div", &max_div)) {
+ dev_err(dev, "missing 'max-div' property\n");
+ return -EFAULT;
+ }
+
+ max_val = max_div;
+ if (!(priv->div_flags & CLK_DIVIDER_ONE_BASED) &&
+ !(priv->div_flags & CLK_DIVIDER_POWER_OF_TWO))
+ max_val--;
+ }
+
+ priv->table = table;
+ priv->min = min_div;
+ priv->max = max_div;
+
+ if (priv->div_flags & CLK_DIVIDER_POWER_OF_TWO)
+ mask = fls(max_val) - 1;
+ else
+ mask = max_val;
+
+ priv->mask = (1 << fls(mask)) - 1;
+ return 0;
+}
+
+static const struct udevice_id clk_ti_divider_of_match[] = {
+ {.compatible = "ti,divider-clock"},
+ {}
+};
+
+U_BOOT_DRIVER(clk_ti_divider) = {
+ .name = "ti_divider_clock",
+ .id = UCLASS_CLK,
+ .of_match = clk_ti_divider_of_match,
+ .ofdata_to_platdata = clk_ti_divider_of_to_plat,
+ .probe = clk_ti_divider_probe,
+ .remove = clk_ti_divider_remove,
+ .priv_auto = sizeof(struct clk_ti_divider_priv),
+ .ops = &clk_ti_divider_ops,
+};
diff --git a/drivers/clk/ti/clk-gate.c b/drivers/clk/ti/clk-gate.c
new file mode 100644
index 0000000000..236eaed6df
--- /dev/null
+++ b/drivers/clk/ti/clk-gate.c
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * TI gate clock support
+ *
+ * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
+ *
+ * Loosely based on Linux kernel drivers/clk/ti/gate.c
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <clk-uclass.h>
+#include <asm/io.h>
+#include <linux/clk-provider.h>
+
+struct clk_ti_gate_priv {
+ fdt_addr_t reg;
+ u8 enable_bit;
+ u32 flags;
+ bool invert_enable;
+};
+
+static int clk_ti_gate_disable(struct clk *clk)
+{
+ struct clk_ti_gate_priv *priv = dev_get_priv(clk->dev);
+ u32 v;
+
+ v = readl(priv->reg);
+ if (priv->invert_enable)
+ v |= (1 << priv->enable_bit);
+ else
+ v &= ~(1 << priv->enable_bit);
+
+ writel(v, priv->reg);
+ /* No OCP barrier needed here since it is a disable operation */
+ return 0;
+}
+
+static int clk_ti_gate_enable(struct clk *clk)
+{
+ struct clk_ti_gate_priv *priv = dev_get_priv(clk->dev);
+ u32 v;
+
+ v = readl(priv->reg);
+ if (priv->invert_enable)
+ v &= ~(1 << priv->enable_bit);
+ else
+ v |= (1 << priv->enable_bit);
+
+ writel(v, priv->reg);
+ /* OCP barrier */
+ v = readl(priv->reg);
+ return 0;
+}
+
+static int clk_ti_gate_of_to_plat(struct udevice *dev)
+{
+ struct clk_ti_gate_priv *priv = dev_get_priv(dev);
+
+ priv->reg = dev_read_addr(dev);
+ if (priv->reg == FDT_ADDR_T_NONE) {
+ dev_err(dev, "failed to get control register\n");
+ return -EINVAL;
+ }
+
+ dev_dbg(dev, "reg=0x%08lx\n", priv->reg);
+ priv->enable_bit = dev_read_u32_default(dev, "ti,bit-shift", 0);
+ if (dev_read_bool(dev, "ti,set-rate-parent"))
+ priv->flags |= CLK_SET_RATE_PARENT;
+
+ priv->invert_enable = dev_read_bool(dev, "ti,set-bit-to-disable");
+ return 0;
+}
+
+static struct clk_ops clk_ti_gate_ops = {
+ .enable = clk_ti_gate_enable,
+ .disable = clk_ti_gate_disable,
+};
+
+static const struct udevice_id clk_ti_gate_of_match[] = {
+ { .compatible = "ti,gate-clock" },
+ { },
+};
+
+U_BOOT_DRIVER(clk_ti_gate) = {
+ .name = "ti_gate_clock",
+ .id = UCLASS_CLK,
+ .of_match = clk_ti_gate_of_match,
+ .ofdata_to_platdata = clk_ti_gate_of_to_plat,
+ .priv_auto = sizeof(struct clk_ti_gate_priv),
+ .ops = &clk_ti_gate_ops,
+};
diff --git a/drivers/clk/ti/clk-mux.c b/drivers/clk/ti/clk-mux.c
new file mode 100644
index 0000000000..419502c389
--- /dev/null
+++ b/drivers/clk/ti/clk-mux.c
@@ -0,0 +1,253 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * TI multiplexer clock support
+ *
+ * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
+ *
+ * Based on Linux kernel drivers/clk/ti/mux.c
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <clk-uclass.h>
+#include <asm/io.h>
+#include <linux/clk-provider.h>
+#include "clk.h"
+
+struct clk_ti_mux_priv {
+ struct clk_bulk parents;
+ fdt_addr_t reg;
+ u32 flags;
+ u32 mux_flags;
+ u32 mask;
+ u32 shift;
+ s32 latch;
+};
+
+static struct clk *clk_ti_mux_get_parent_by_index(struct clk_bulk *parents,
+ int index)
+{
+ if (index < 0 || !parents)
+ return ERR_PTR(-EINVAL);
+
+ if (index >= parents->count)
+ return ERR_PTR(-ENODEV);
+
+ return &parents->clks[index];
+}
+
+static int clk_ti_mux_get_parent_index(struct clk_bulk *parents,
+ struct clk *parent)
+{
+ int i;
+
+ if (!parents || !parent)
+ return -EINVAL;
+
+ for (i = 0; i < parents->count; i++) {
+ if (parents->clks[i].dev == parent->dev)
+ return i;
+ }
+
+ return -ENODEV;
+}
+
+static int clk_ti_mux_get_index(struct clk *clk)
+{
+ struct clk_ti_mux_priv *priv = dev_get_priv(clk->dev);
+ u32 val;
+
+ val = readl(priv->reg);
+ val >>= priv->shift;
+ val &= priv->mask;
+
+ if (val && (priv->flags & CLK_MUX_INDEX_BIT))
+ val = ffs(val) - 1;
+
+ if (val && (priv->flags & CLK_MUX_INDEX_ONE))
+ val--;
+
+ if (val >= priv->parents.count)
+ return -EINVAL;
+
+ return val;
+}
+
+static int clk_ti_mux_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct clk_ti_mux_priv *priv = dev_get_priv(clk->dev);
+ int index;
+ u32 val;
+
+ index = clk_ti_mux_get_parent_index(&priv->parents, parent);
+ if (index < 0) {
+ dev_err(clk->dev, "failed to get parent clock\n");
+ return index;
+ }
+
+ index = clk_mux_index_to_val(NULL, priv->flags, index);
+
+ if (priv->flags & CLK_MUX_HIWORD_MASK) {
+ val = priv->mask << (priv->shift + 16);
+ } else {
+ val = readl(priv->reg);
+ val &= ~(priv->mask << priv->shift);
+ }
+
+ val |= index << priv->shift;
+ writel(val, priv->reg);
+ clk_ti_latch(priv->reg, priv->latch);
+ return 0;
+}
+
+static ulong clk_ti_mux_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk_ti_mux_priv *priv = dev_get_priv(clk->dev);
+ struct clk *parent;
+ int index;
+
+ if ((clk->flags & CLK_SET_RATE_PARENT) == 0)
+ return -ENOSYS;
+
+ index = clk_ti_mux_get_index(clk);
+ parent = clk_ti_mux_get_parent_by_index(&priv->parents, index);
+ if (IS_ERR(parent))
+ return PTR_ERR(parent);
+
+ rate = clk_set_rate(parent, rate);
+ dev_dbg(clk->dev, "rate=%ld\n", rate);
+ return rate;
+}
+
+static ulong clk_ti_mux_get_rate(struct clk *clk)
+{
+ struct clk_ti_mux_priv *priv = dev_get_priv(clk->dev);
+ int index;
+ struct clk *parent;
+ ulong rate;
+
+ index = clk_ti_mux_get_index(clk);
+ parent = clk_ti_mux_get_parent_by_index(&priv->parents, index);
+ if (IS_ERR(parent))
+ return PTR_ERR(parent);
+
+ rate = clk_get_rate(parent);
+ dev_dbg(clk->dev, "rate=%ld\n", rate);
+ return rate;
+}
+
+static ulong clk_ti_mux_round_rate(struct clk *clk, ulong rate)
+{
+ struct clk_ti_mux_priv *priv = dev_get_priv(clk->dev);
+ struct clk *parent;
+ int index;
+
+ if ((clk->flags & CLK_SET_RATE_PARENT) == 0)
+ return -ENOSYS;
+
+ index = clk_ti_mux_get_index(clk);
+ parent = clk_ti_mux_get_parent_by_index(&priv->parents, index);
+ if (IS_ERR(parent))
+ return PTR_ERR(parent);
+
+ rate = clk_round_rate(parent, rate);
+ dev_dbg(clk->dev, "rate=%ld\n", rate);
+ return rate;
+}
+
+static int clk_ti_mux_request(struct clk *clk)
+{
+ struct clk_ti_mux_priv *priv = dev_get_priv(clk->dev);
+ struct clk *parent;
+ int index;
+
+ clk->flags = priv->flags;
+
+ index = clk_ti_mux_get_index(clk);
+ parent = clk_ti_mux_get_parent_by_index(&priv->parents, index);
+ if (IS_ERR(parent))
+ return PTR_ERR(parent);
+
+ return clk_ti_mux_set_parent(clk, parent);
+}
+
+static struct clk_ops clk_ti_mux_ops = {
+ .request = clk_ti_mux_request,
+ .round_rate = clk_ti_mux_round_rate,
+ .get_rate = clk_ti_mux_get_rate,
+ .set_rate = clk_ti_mux_set_rate,
+ .set_parent = clk_ti_mux_set_parent,
+};
+
+static int clk_ti_mux_remove(struct udevice *dev)
+{
+ struct clk_ti_mux_priv *priv = dev_get_priv(dev);
+ int err;
+
+ err = clk_release_all(priv->parents.clks, priv->parents.count);
+ if (err)
+ dev_dbg(dev, "could not release all parents' clocks\n");
+
+ return err;
+}
+
+static int clk_ti_mux_probe(struct udevice *dev)
+{
+ struct clk_ti_mux_priv *priv = dev_get_priv(dev);
+ int err;
+
+ err = clk_get_bulk(dev, &priv->parents);
+ if (err || priv->parents.count < 2) {
+ dev_err(dev, "mux-clock must have parents\n");
+ return err ? err : -EFAULT;
+ }
+
+ /* Generate bit-mask based on parents info */
+ priv->mask = priv->parents.count;
+ if (!(priv->mux_flags & CLK_MUX_INDEX_ONE))
+ priv->mask--;
+
+ priv->mask = (1 << fls(priv->mask)) - 1;
+ return 0;
+}
+
+static int clk_ti_mux_of_to_plat(struct udevice *dev)
+{
+ struct clk_ti_mux_priv *priv = dev_get_priv(dev);
+
+ priv->reg = dev_read_addr(dev);
+ if (priv->reg == FDT_ADDR_T_NONE) {
+ dev_err(dev, "failed to get register\n");
+ return -EINVAL;
+ }
+
+ dev_dbg(dev, "reg=0x%08lx\n", priv->reg);
+ priv->shift = dev_read_u32_default(dev, "ti,bit-shift", 0);
+ priv->latch = dev_read_s32_default(dev, "ti,latch-bit", -EINVAL);
+
+ priv->flags = CLK_SET_RATE_NO_REPARENT;
+ if (dev_read_bool(dev, "ti,set-rate-parent"))
+ priv->flags |= CLK_SET_RATE_PARENT;
+
+ if (dev_read_bool(dev, "ti,index-starts-at-one"))
+ priv->mux_flags |= CLK_MUX_INDEX_ONE;
+
+ return 0;
+}
+
+static const struct udevice_id clk_ti_mux_of_match[] = {
+ {.compatible = "ti,mux-clock"},
+ {},
+};
+
+U_BOOT_DRIVER(clk_ti_mux) = {
+ .name = "ti_mux_clock",
+ .id = UCLASS_CLK,
+ .of_match = clk_ti_mux_of_match,
+ .ofdata_to_platdata = clk_ti_mux_of_to_plat,
+ .probe = clk_ti_mux_probe,
+ .remove = clk_ti_mux_remove,
+ .priv_auto = sizeof(struct clk_ti_mux_priv),
+ .ops = &clk_ti_mux_ops,
+};
diff --git a/drivers/clk/clk-ti-sci.c b/drivers/clk/ti/clk-sci.c
index 7a9a645137..6f0fdaa111 100644
--- a/drivers/clk/clk-ti-sci.c
+++ b/drivers/clk/ti/clk-sci.c
@@ -220,6 +220,6 @@ U_BOOT_DRIVER(ti_sci_clk) = {
.id = UCLASS_CLK,
.of_match = ti_sci_clk_of_match,
.probe = ti_sci_clk_probe,
- .priv_auto_alloc_size = sizeof(struct ti_sci_clk_data),
+ .priv_auto = sizeof(struct ti_sci_clk_data),
.ops = &ti_sci_clk_ops,
};
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
new file mode 100644
index 0000000000..e44b90ad6a
--- /dev/null
+++ b/drivers/clk/ti/clk.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * TI clock utilities
+ *
+ * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include "clk.h"
+
+static void clk_ti_rmw(u32 val, u32 mask, fdt_addr_t reg)
+{
+ u32 v;
+
+ v = readl(reg);
+ v &= ~mask;
+ v |= val;
+ writel(v, reg);
+}
+
+void clk_ti_latch(fdt_addr_t reg, s8 shift)
+{
+ u32 latch;
+
+ if (shift < 0)
+ return;
+
+ latch = 1 << shift;
+
+ clk_ti_rmw(latch, latch, reg);
+ clk_ti_rmw(0, latch, reg);
+ readl(reg); /* OCP barrier */
+}
diff --git a/drivers/clk/ti/clk.h b/drivers/clk/ti/clk.h
new file mode 100644
index 0000000000..601c3823f7
--- /dev/null
+++ b/drivers/clk/ti/clk.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * TI clock utilities header
+ *
+ * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
+ */
+
+#ifndef _CLK_TI_H
+#define _CLK_TI_H
+
+void clk_ti_latch(fdt_addr_t reg, s8 shift);
+
+#endif /* #ifndef _CLK_TI_H */
diff --git a/drivers/clk/ti/omap4-cm.c b/drivers/clk/ti/omap4-cm.c
new file mode 100644
index 0000000000..3cdc9b2888
--- /dev/null
+++ b/drivers/clk/ti/omap4-cm.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * OMAP4 clock manager (cm)
+ *
+ * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/lists.h>
+
+static const struct udevice_id ti_omap4_cm_ids[] = {
+ {.compatible = "ti,omap4-cm"},
+ {}
+};
+
+U_BOOT_DRIVER(ti_omap4_cm) = {
+ .name = "ti_omap4_cm",
+ .id = UCLASS_SIMPLE_BUS,
+ .of_match = ti_omap4_cm_ids,
+ .bind = dm_scan_fdt_dev,
+};
diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c
index 4e25db354e..c31e59641d 100644
--- a/drivers/clk/uniphier/clk-uniphier-core.c
+++ b/drivers/clk/uniphier/clk-uniphier-core.c
@@ -342,6 +342,6 @@ U_BOOT_DRIVER(uniphier_clk) = {
.id = UCLASS_CLK,
.of_match = uniphier_clk_match,
.probe = uniphier_clk_probe,
- .priv_auto_alloc_size = sizeof(struct uniphier_clk_priv),
+ .priv_auto = sizeof(struct uniphier_clk_priv),
.ops = &uniphier_clk_ops,
};
generated by cgit (git 2.34.1) at 2024-11-19 06:34:32 +0000