diff options
Diffstat (limited to 'cpu/mpc85xx')
| -rw-r--r-- | cpu/mpc85xx/Makefile | 1 | ||||
| -rw-r--r-- | cpu/mpc85xx/cpu.c | 26 | ||||
| -rw-r--r-- | cpu/mpc85xx/ddr-gen3.c | 9 | ||||
| -rw-r--r-- | cpu/mpc85xx/tlb.c | 74 |
4 files changed, 59 insertions, 51 deletions
diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index 627e61b059..99d88a888d 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -48,6 +48,7 @@ COBJS-$(CONFIG_MPC8544) += ddr-gen2.o # supports ddr1/2/3 COBJS-$(CONFIG_MPC8572) += ddr-gen3.o COBJS-$(CONFIG_MPC8536) += ddr-gen3.o +COBJS-$(CONFIG_P2020) += ddr-gen3.o COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \ diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index a34e2515e8..5b72fe544f 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -31,6 +31,7 @@ #include <command.h> #include <tsec.h> #include <netdev.h> +#include <fsl_esdhc.h> #include <asm/cache.h> #include <asm/io.h> @@ -62,6 +63,8 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(8568, 8568_E), CPU_TYPE_ENTRY(8572, 8572), CPU_TYPE_ENTRY(8572, 8572_E), + CPU_TYPE_ENTRY(P2020, P2020), + CPU_TYPE_ENTRY(P2020, P2020_E), }; struct cpu_type *identify_cpu(u32 ver) @@ -142,11 +145,14 @@ int checkcpu (void) get_sys_info(&sysinfo); - puts("Clock Configuration:\n "); - for (i = 0; i < CONFIG_NUM_CPUS; i++) + puts("Clock Configuration:"); + for (i = 0; i < CONFIG_NUM_CPUS; i++) { + if (!(i & 3)) + printf ("\n "); printf("CPU%d:%-4s MHz, ", i,strmhz(buf1, sysinfo.freqProcessor[i])); - printf("CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); + } + printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); switch (ddr_ratio) { case 0x0: @@ -390,5 +396,19 @@ int cpu_eth_init(bd_t *bis) #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC) tsec_standard_init(bis); #endif + + return 0; +} + +/* + * Initializes on-chip MMC controllers. + * to override, implement board_mmc_init() + */ +int cpu_mmc_init(bd_t *bis) +{ +#ifdef CONFIG_FSL_ESDHC + return fsl_esdhc_mmc_init(bis); +#else return 0; +#endif } diff --git a/cpu/mpc85xx/ddr-gen3.c b/cpu/mpc85xx/ddr-gen3.c index a2b45c5719..8dc2b3ac52 100644 --- a/cpu/mpc85xx/ddr-gen3.c +++ b/cpu/mpc85xx/ddr-gen3.c @@ -19,6 +19,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, { unsigned int i; volatile ccsr_ddr_t *ddr; + u32 temp_sdram_cfg; switch (ctrl_num) { case 0: @@ -78,6 +79,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); + /* Do not enable the memory */ + temp_sdram_cfg = in_be32(&ddr->sdram_cfg); + temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); + out_be32(&ddr->sdram_cfg, temp_sdram_cfg); /* * For 8572 DDR1 erratum - DDR controller may enter illegal state * when operatiing in 32-bit bus mode with 4-beat bursts, @@ -99,7 +104,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, udelay(200); asm volatile("sync;isync"); - out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg); + /* Let the controller go */ + temp_sdram_cfg = in_be32(&ddr->sdram_cfg); + out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ while (in_be32(&ddr->sdram_cfg_2) & 0x10) { diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index 25fa9ee8f8..c73bf056ec 100644 --- a/cpu/mpc85xx/tlb.c +++ b/cpu/mpc85xx/tlb.c @@ -132,61 +132,41 @@ void init_addr_map(void) unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) { unsigned int tlb_size; - unsigned int ram_tlb_index; - unsigned int ram_tlb_address; + unsigned int ram_tlb_index = CONFIG_SYS_DDR_TLB_START; + unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; + unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xff; + u64 size, memsize = (u64)memsize_in_meg << 20; - /* - * Determine size of each TLB1 entry. - */ - switch (memsize_in_meg) { - case 16: - case 32: - tlb_size = BOOKE_PAGESZ_16M; - break; - case 64: - case 128: - tlb_size = BOOKE_PAGESZ_64M; - break; - case 256: - case 512: - tlb_size = BOOKE_PAGESZ_256M; - break; - case 1024: - case 2048: - if (PVR_VER(get_pvr()) > PVR_VER(PVR_85xx)) - tlb_size = BOOKE_PAGESZ_1G; - else - tlb_size = BOOKE_PAGESZ_256M; - break; - default: - puts("DDR: only 16M, 32M, 64M, 128M, 256M, 512M, 1G" - " and 2G are supported.\n"); - - /* - * The memory was not able to be mapped. - * Default to a small size. - */ - tlb_size = BOOKE_PAGESZ_64M; - memsize_in_meg = 64; - break; - } + size = min(memsize, CONFIG_MAX_MEM_MAPPED); + + /* Convert (4^max) kB to (2^max) bytes */ + max_cam = max_cam * 2 + 10; + + for (; size && ram_tlb_index < 16; ram_tlb_index++) { + u32 camsize = __ilog2_u64(size) & ~1U; + u32 align = __ilog2(ram_tlb_address) & ~1U; + + if (align == -2) align = max_cam; + if (camsize > align) + camsize = align; + + if (camsize > max_cam) + camsize = max_cam; + + tlb_size = (camsize - 10) / 2; - /* - * Configure DDR TLB1 entries. - * Starting at TLB1 8, use no more than 8 TLB1 entries. - */ - ram_tlb_index = CONFIG_SYS_DDR_TLB_START; - ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; - while (ram_tlb_address < (memsize_in_meg * 1024 * 1024) - && ram_tlb_index < 16) { set_tlb(1, ram_tlb_address, ram_tlb_address, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, ram_tlb_index, tlb_size, 1); - ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2)); - ram_tlb_index++; + size -= 1ULL << camsize; + memsize -= 1ULL << camsize; + ram_tlb_address += 1UL << camsize; } + if (memsize) + printf("%lldM left unmapped\n", memsize >> 20); + /* * Confirm that the requested amount of memory was mapped. */ |