diff options
Diffstat (limited to 'board')
38 files changed, 360 insertions, 116 deletions
diff --git a/board/advantech/som-db5800-som-6867/Kconfig b/board/advantech/som-db5800-som-6867/Kconfig index f6f3748fc3..fac562ad4f 100644 --- a/board/advantech/som-db5800-som-6867/Kconfig +++ b/board/advantech/som-db5800-som-6867/Kconfig @@ -21,6 +21,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select X86_RESET_VECTOR if !EFI_STUB select INTEL_BAYTRAIL select BOARD_ROMSIZE_KB_8192 + select BOARD_EARLY_INIT_F + select SPI_FLASH_MACRONIX config PCIE_ECAM_BASE default 0xe0000000 diff --git a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c index 5bed2c1146..615879575c 100644 --- a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c +++ b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c @@ -17,8 +17,3 @@ int board_early_init_f(void) return 0; } - -int arch_early_init_r(void) -{ - return 0; -} diff --git a/board/cei/cei-tk1-som/cei-tk1-som.c b/board/cei/cei-tk1-som/cei-tk1-som.c index 9ba7490c38..7c87bd1eb1 100644 --- a/board/cei/cei-tk1-som/cei-tk1-som.c +++ b/board/cei/cei-tk1-som/cei-tk1-som.c @@ -39,6 +39,7 @@ void pinmux_init(void) #ifdef CONFIG_PCI_TEGRA int tegra_pcie_board_init(void) { +/* TODO: Convert to driver model struct udevice *pmic; int err; @@ -59,6 +60,7 @@ int tegra_pcie_board_init(void) error("failed to set SD4 voltage: %d\n", err); return err; } +*/ return 0; } diff --git a/board/congatec/conga-qeval20-qa3-e3845/Kconfig b/board/congatec/conga-qeval20-qa3-e3845/Kconfig index 9f31238930..c2649d299f 100644 --- a/board/congatec/conga-qeval20-qa3-e3845/Kconfig +++ b/board/congatec/conga-qeval20-qa3-e3845/Kconfig @@ -21,6 +21,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy select X86_RESET_VECTOR if !EFI_STUB select INTEL_BAYTRAIL select BOARD_ROMSIZE_KB_8192 + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + select SPI_FLASH_STMICRO config PCIE_ECAM_BASE default 0xe0000000 diff --git a/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c index 7a5b7659ef..1283eebd38 100644 --- a/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c +++ b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c @@ -28,11 +28,6 @@ int board_early_init_f(void) return 0; } -int arch_early_init_r(void) -{ - return 0; -} - int board_late_init(void) { struct udevice *dev; diff --git a/board/coreboot/coreboot/Kconfig b/board/coreboot/coreboot/Kconfig index 3ff64f4084..cfa1d50ee4 100644 --- a/board/coreboot/coreboot/Kconfig +++ b/board/coreboot/coreboot/Kconfig @@ -12,6 +12,17 @@ config SYS_SOC config SYS_TEXT_BASE default 0x01110000 +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + imply SPI_FLASH_ATMEL + imply SPI_FLASH_EON + imply SPI_FLASH_GIGADEVICE + imply SPI_FLASH_MACRONIX + imply SPI_FLASH_SPANSION + imply SPI_FLASH_STMICRO + imply SPI_FLASH_SST + imply SPI_FLASH_WINBOND + comment "coreboot-specific options" config SYS_CONFIG_NAME diff --git a/board/coreboot/coreboot/Makefile b/board/coreboot/coreboot/Makefile index 27ebe78eb1..4f2ac898eb 100644 --- a/board/coreboot/coreboot/Makefile +++ b/board/coreboot/coreboot/Makefile @@ -12,4 +12,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += coreboot_start.o coreboot.o +obj-y += coreboot_start.o diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c deleted file mode 100644 index bb7f778a8f..0000000000 --- a/board/coreboot/coreboot/coreboot.c +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (C) 2013 Google, Inc - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <cros_ec.h> -#include <asm/gpio.h> - -int arch_early_init_r(void) -{ - return 0; -} diff --git a/board/dfi/dfi-bt700/Kconfig b/board/dfi/dfi-bt700/Kconfig index 3f0acb39f7..81a2575d11 100644 --- a/board/dfi/dfi-bt700/Kconfig +++ b/board/dfi/dfi-bt700/Kconfig @@ -21,6 +21,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy select X86_RESET_VECTOR if !EFI_STUB select INTEL_BAYTRAIL select BOARD_ROMSIZE_KB_8192 + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + select SPI_FLASH_STMICRO config PCIE_ECAM_BASE default 0xe0000000 diff --git a/board/dfi/dfi-bt700/dfi-bt700.c b/board/dfi/dfi-bt700/dfi-bt700.c index 8645bdc795..3dd2036d11 100644 --- a/board/dfi/dfi-bt700/dfi-bt700.c +++ b/board/dfi/dfi-bt700/dfi-bt700.c @@ -28,3 +28,30 @@ int board_early_init_f(void) return 0; } + +int board_late_init(void) +{ + struct gpio_desc desc; + int ret; + + ret = dm_gpio_lookup_name("F10", &desc); + if (ret) + debug("gpio ret=%d\n", ret); + ret = dm_gpio_request(&desc, "xhci_hub_reset"); + if (ret) + debug("gpio_request ret=%d\n", ret); + ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + if (ret) + debug("gpio dir ret=%d\n", ret); + + /* Pull xHCI hub reset to low (active low) */ + dm_gpio_set_value(&desc, 0); + + /* Wait at least 5 ms, so lets choose 10 to be safe */ + mdelay(10); + + /* Pull xHCI hub reset to high (active low) */ + dm_gpio_set_value(&desc, 1); + + return 0; +} diff --git a/board/efi/efi-x86/efi.c b/board/efi/efi-x86/efi.c index 1fbe36a399..2adc202be0 100644 --- a/board/efi/efi-x86/efi.c +++ b/board/efi/efi-x86/efi.c @@ -5,9 +5,3 @@ */ #include <common.h> -#include <asm/gpio.h> - -int arch_early_init_r(void) -{ - return 0; -} diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig index 8999b58294..944716d002 100644 --- a/board/google/chromebook_link/Kconfig +++ b/board/google/chromebook_link/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_IVYBRIDGE select HAVE_INTEL_ME select BOARD_ROMSIZE_KB_8192 + select SPI_FLASH_WINBOND config PCIE_ECAM_BASE default 0xf0000000 diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c index 42615e1e23..dc22592095 100644 --- a/board/google/chromebook_link/link.c +++ b/board/google/chromebook_link/link.c @@ -5,19 +5,3 @@ */ #include <common.h> -#include <cros_ec.h> -#include <dm.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/pci.h> -#include <asm/arch/pch.h> - -int arch_early_init_r(void) -{ - return 0; -} - -int board_early_init_f(void) -{ - return 0; -} diff --git a/board/google/chromebook_samus/Kconfig b/board/google/chromebook_samus/Kconfig index f2b9481563..afbfe53deb 100644 --- a/board/google/chromebook_samus/Kconfig +++ b/board/google/chromebook_samus/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_BROADWELL select HAVE_INTEL_ME select BOARD_ROMSIZE_KB_8192 + select SPI_FLASH_WINBOND config PCIE_ECAM_BASE default 0xf0000000 diff --git a/board/google/chromebook_samus/samus.c b/board/google/chromebook_samus/samus.c index 3c3f5d4833..5b5eb19ee8 100644 --- a/board/google/chromebook_samus/samus.c +++ b/board/google/chromebook_samus/samus.c @@ -5,14 +5,3 @@ */ #include <common.h> -#include <asm/cpu.h> - -int arch_early_init_r(void) -{ - return cpu_run_reference_code(); -} - -int board_early_init_f(void) -{ - return 0; -} diff --git a/board/google/chromebox_panther/Kconfig b/board/google/chromebox_panther/Kconfig index 2af3aa9e74..875df9d59f 100644 --- a/board/google/chromebox_panther/Kconfig +++ b/board/google/chromebox_panther/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_IVYBRIDGE select HAVE_INTEL_ME select BOARD_ROMSIZE_KB_8192 + select SPI_FLASH_WINBOND config SYS_CAR_ADDR hex diff --git a/board/google/chromebox_panther/panther.c b/board/google/chromebox_panther/panther.c index e3baf88783..2adc202be0 100644 --- a/board/google/chromebox_panther/panther.c +++ b/board/google/chromebox_panther/panther.c @@ -5,14 +5,3 @@ */ #include <common.h> -#include <asm/arch/pch.h> - -int arch_early_init_r(void) -{ - return 0; -} - -int board_early_init_f(void) -{ - return 0; -} diff --git a/board/intel/Kconfig b/board/intel/Kconfig index 4d341aa799..d7d950e877 100644 --- a/board/intel/Kconfig +++ b/board/intel/Kconfig @@ -35,6 +35,13 @@ config TARGET_CROWNBAY Intel Platform Controller Hub EG20T, other system components and peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS. +config TARGET_EDISON + bool "Edison" + help + This is the Intel Edison Compute Module. It contains a dual core Intel + Atom Tangier CPU, 1 GB RAM integrated on package. There is also 4 GB + eMMC flash on board, Wi-Fi, Bluetooth 4 and USB controllers. + config TARGET_GALILEO bool "Galileo" help @@ -64,6 +71,7 @@ endchoice source "board/intel/bayleybay/Kconfig" source "board/intel/cougarcanyon2/Kconfig" source "board/intel/crownbay/Kconfig" +source "board/intel/edison/Kconfig" source "board/intel/galileo/Kconfig" source "board/intel/minnowmax/Kconfig" diff --git a/board/intel/bayleybay/Kconfig b/board/intel/bayleybay/Kconfig index 597228fdbc..a62249936f 100644 --- a/board/intel/bayleybay/Kconfig +++ b/board/intel/bayleybay/Kconfig @@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select X86_RESET_VECTOR select INTEL_BAYTRAIL select BOARD_ROMSIZE_KB_8192 + select SPI_FLASH_WINBOND config PCIE_ECAM_BASE default 0xe0000000 diff --git a/board/intel/cougarcanyon2/Kconfig b/board/intel/cougarcanyon2/Kconfig index 95a617b725..ed764485a5 100644 --- a/board/intel/cougarcanyon2/Kconfig +++ b/board/intel/cougarcanyon2/Kconfig @@ -21,5 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_IVYBRIDGE select HAVE_FSP select BOARD_ROMSIZE_KB_2048 + select BOARD_EARLY_INIT_F + select SPI_FLASH_WINBOND endif diff --git a/board/intel/crownbay/Kconfig b/board/intel/crownbay/Kconfig index b30701afc8..1eed227c75 100644 --- a/board/intel/crownbay/Kconfig +++ b/board/intel/crownbay/Kconfig @@ -20,5 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select X86_RESET_VECTOR select INTEL_QUEENSBAY select BOARD_ROMSIZE_KB_1024 + select BOARD_EARLY_INIT_F + select SPI_FLASH_SST endif diff --git a/board/intel/edison/Kconfig b/board/intel/edison/Kconfig new file mode 100644 index 0000000000..4ff9d5adec --- /dev/null +++ b/board/intel/edison/Kconfig @@ -0,0 +1,26 @@ +if TARGET_EDISON + +config SYS_BOARD + default "edison" + +config SYS_VENDOR + default "intel" + +config SYS_SOC + default "tangier" + +config SYS_CONFIG_NAME + default "edison" + +config SYS_TEXT_BASE + default 0x01101000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_LOAD_FROM_32_BIT + select INTEL_MID + select INTEL_TANGIER + select BOARD_LATE_INIT + select MD5 + +endif diff --git a/board/intel/edison/MAINTAINERS b/board/intel/edison/MAINTAINERS new file mode 100644 index 0000000000..4bc4a00c8a --- /dev/null +++ b/board/intel/edison/MAINTAINERS @@ -0,0 +1,6 @@ +Intel Edison Board +M: Andy Shevchenko <andriy.shevchenko@linux.intel.com> +S: Maintained +F: board/intel/edison +F: include/configs/edison.h +F: configs/edison_defconfig diff --git a/board/intel/edison/Makefile b/board/intel/edison/Makefile new file mode 100644 index 0000000000..dde159435b --- /dev/null +++ b/board/intel/edison/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2017 Intel Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += start.o edison.o diff --git a/board/intel/edison/config.mk b/board/intel/edison/config.mk new file mode 100644 index 0000000000..465133fd77 --- /dev/null +++ b/board/intel/edison/config.mk @@ -0,0 +1,18 @@ +# +# Copyright (c) 2011 The Chromium OS Authors. All rights reserved. +# Copyright (c) 2017 Intel Corporation +# +# SPDX-License-Identifier: GPL-2.0 BSD-3-Clause +# + +# Add 4096 bytes of zeroes to u-boot.bin +quiet_cmd_mkalign_eds = EDSALGN $@ +cmd_mkalign_eds = \ + dd if=$^ of=$@ bs=4k seek=1 2>/dev/null && \ + mv $@ $^ + +ALL-y += u-boot-align.bin +u-boot-align.bin: u-boot.bin + $(call if_changed,mkalign_eds) + +HOSTCFLAGS_autoconf.mk.dep = -Wno-variadic-macros diff --git a/board/intel/edison/edison.c b/board/intel/edison/edison.c new file mode 100644 index 0000000000..a1a7d4d7c8 --- /dev/null +++ b/board/intel/edison/edison.c @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2017 Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <dwc3-uboot.h> +#include <mmc.h> +#include <u-boot/md5.h> +#include <usb.h> +#include <watchdog.h> + +#include <linux/usb/gadget.h> + +#include <asm/cache.h> +#include <asm/scu.h> +#include <asm/u-boot-x86.h> + +DECLARE_GLOBAL_DATA_PTR; + +static struct dwc3_device dwc3_device_data = { + .maximum_speed = USB_SPEED_HIGH, + .base = CONFIG_SYS_USB_OTG_BASE, + .dr_mode = USB_DR_MODE_PERIPHERAL, + .index = 0, +}; + +int usb_gadget_handle_interrupts(int controller_index) +{ + dwc3_uboot_handle_interrupt(controller_index); + WATCHDOG_RESET(); + return 0; +} + +int board_usb_init(int index, enum usb_init_type init) +{ + if (index == 0 && init == USB_INIT_DEVICE) + return dwc3_uboot_init(&dwc3_device_data); + return -EINVAL; +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + if (index == 0 && init == USB_INIT_DEVICE) { + dwc3_uboot_exit(index); + return 0; + } + return -EINVAL; +} + +static void assign_serial(void) +{ + struct mmc *mmc = find_mmc_device(0); + unsigned char ssn[16]; + char usb0addr[18]; + char serial[33]; + int i; + + if (!mmc) + return; + + md5((unsigned char *)mmc->cid, sizeof(mmc->cid), ssn); + + snprintf(usb0addr, sizeof(usb0addr), "02:00:86:%02x:%02x:%02x", + ssn[13], ssn[14], ssn[15]); + setenv("usb0addr", usb0addr); + + for (i = 0; i < 16; i++) + snprintf(&serial[2 * i], 3, "%02x", ssn[i]); + setenv("serial#", serial); + +#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE) + saveenv(); +#endif +} + +static void assign_hardware_id(void) +{ + struct ipc_ifwi_version v; + char hardware_id[4]; + int ret; + + ret = scu_ipc_command(IPCMSG_GET_FW_REVISION, 1, NULL, 0, (u32 *)&v, 4); + if (ret < 0) + printf("Can't retrieve hardware revision\n"); + + snprintf(hardware_id, sizeof(hardware_id), "%02X", v.hardware_id); + setenv("hardware_id", hardware_id); + +#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE) + saveenv(); +#endif +} + +int board_late_init(void) +{ + if (!getenv("serial#")) + assign_serial(); + + if (!getenv("hardware_id")) + assign_hardware_id(); + + return 0; +} diff --git a/board/intel/edison/start.S b/board/intel/edison/start.S new file mode 100644 index 0000000000..932fe6c24b --- /dev/null +++ b/board/intel/edison/start.S @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2008 + * Graeme Russ, graeme.russ@gmail.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* board early intialization */ +.globl early_board_init +early_board_init: + /* No 32-bit board specific initialisation */ + jmp early_board_init_ret diff --git a/board/intel/galileo/Kconfig b/board/intel/galileo/Kconfig index 87a0ec4ccc..1416c891e8 100644 --- a/board/intel/galileo/Kconfig +++ b/board/intel/galileo/Kconfig @@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select X86_RESET_VECTOR select INTEL_QUARK select BOARD_ROMSIZE_KB_1024 + select SPI_FLASH_WINBOND config SMBIOS_PRODUCT_NAME default "GalileoGen2" diff --git a/board/intel/galileo/galileo.c b/board/intel/galileo/galileo.c index 568bd4db49..2fe1923a9f 100644 --- a/board/intel/galileo/galileo.c +++ b/board/intel/galileo/galileo.c @@ -9,11 +9,6 @@ #include <asm/arch/device.h> #include <asm/arch/quark.h> -int board_early_init_f(void) -{ - return 0; -} - /* * Intel Galileo gen2 board uses GPIO Resume Well bank pin0 as the PERST# pin. * diff --git a/board/intel/minnowmax/Kconfig b/board/intel/minnowmax/Kconfig index 7e975f9c3a..a8668e4efc 100644 --- a/board/intel/minnowmax/Kconfig +++ b/board/intel/minnowmax/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select X86_RESET_VECTOR if !EFI_STUB select INTEL_BAYTRAIL select BOARD_ROMSIZE_KB_8192 + select SPI_FLASH_STMICRO config PCIE_ECAM_BASE default 0xe0000000 diff --git a/board/intel/minnowmax/minnowmax.c b/board/intel/minnowmax/minnowmax.c index 99aed53100..5bdb2fdbc7 100644 --- a/board/intel/minnowmax/minnowmax.c +++ b/board/intel/minnowmax/minnowmax.c @@ -12,11 +12,6 @@ #define GPIO_BANKE_NAME "gpioe" -int arch_early_init_r(void) -{ - return 0; -} - int misc_init_r(void) { struct udevice *dev; diff --git a/board/nvidia/jetson-tk1/jetson-tk1.c b/board/nvidia/jetson-tk1/jetson-tk1.c index a66b710cdd..bd08a2eed4 100644 --- a/board/nvidia/jetson-tk1/jetson-tk1.c +++ b/board/nvidia/jetson-tk1/jetson-tk1.c @@ -6,7 +6,9 @@ */ #include <common.h> +#include <dm.h> #include <power/as3722.h> +#include <power/pmic.h> #include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> @@ -37,27 +39,45 @@ void pinmux_init(void) } #ifdef CONFIG_PCI_TEGRA -int tegra_pcie_board_init(void) +/* TODO: Convert to driver model */ +static int as3722_sd_enable(struct udevice *pmic, unsigned int sd) { - struct udevice *pmic; int err; - err = as3722_init(&pmic); + if (sd > 6) + return -EINVAL; + + err = pmic_clrsetbits(pmic, AS3722_SD_CONTROL, 0, 1 << sd); if (err) { - error("failed to initialize AS3722 PMIC: %d\n", err); + error("failed to update SD control register: %d", err); return err; } - err = as3722_sd_enable(pmic, 4); - if (err < 0) { - error("failed to enable SD4: %d\n", err); - return err; + return 0; +} + +int tegra_pcie_board_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_PMIC, + DM_GET_DRIVER(pmic_as3722), &dev); + if (ret) { + debug("%s: Failed to find PMIC\n", __func__); + return ret; } - err = as3722_sd_set_voltage(pmic, 4, 0x24); - if (err < 0) { - error("failed to set SD4 voltage: %d\n", err); - return err; + ret = as3722_sd_enable(dev, 4); + if (ret < 0) { + error("failed to enable SD4: %d\n", ret); + return ret; + } + + ret = as3722_sd_set_voltage(dev, 4, 0x24); + if (ret < 0) { + error("failed to set SD4 voltage: %d\n", ret); + return ret; } return 0; diff --git a/board/nvidia/nyan-big/nyan-big.c b/board/nvidia/nyan-big/nyan-big.c index 8f68ae9fbe..54acf5418d 100644 --- a/board/nvidia/nyan-big/nyan-big.c +++ b/board/nvidia/nyan-big/nyan-big.c @@ -6,6 +6,7 @@ */ #include <common.h> +#include <dm.h> #include <errno.h> #include <asm/gpio.h> #include <asm/io.h> @@ -46,20 +47,23 @@ int tegra_board_id(void) int tegra_lcd_pmic_init(int board_id) { - struct udevice *pmic; + struct udevice *dev; int ret; - ret = as3722_get(&pmic); - if (ret) - return -ENOENT; + ret = uclass_get_device_by_driver(UCLASS_PMIC, + DM_GET_DRIVER(pmic_as3722), &dev); + if (ret) { + debug("%s: Failed to find PMIC\n", __func__); + return ret; + } if (board_id == 0) - as3722_write(pmic, 0x00, 0x3c); + pmic_reg_write(dev, 0x00, 0x3c); else - as3722_write(pmic, 0x00, 0x50); - as3722_write(pmic, 0x12, 0x10); - as3722_write(pmic, 0x0c, 0x07); - as3722_write(pmic, 0x20, 0x10); + pmic_reg_write(dev, 0x00, 0x50); + pmic_reg_write(dev, 0x12, 0x10); + pmic_reg_write(dev, 0x0c, 0x07); + pmic_reg_write(dev, 0x20, 0x10); return 0; } diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile index 43766e0ef4..f4411f01c3 100644 --- a/board/sunxi/Makefile +++ b/board/sunxi/Makefile @@ -10,7 +10,9 @@ # obj-y += board.o obj-$(CONFIG_SUNXI_GMAC) += gmac.o +ifndef CONFIG_SPL_BUILD obj-$(CONFIG_SUNXI_AHCI) += ahci.o +endif obj-$(CONFIG_MACH_SUN4I) += dram_sun4i_auto.o obj-$(CONFIG_MACH_SUN5I) += dram_sun5i_auto.o obj-$(CONFIG_MACH_SUN7I) += dram_sun5i_auto.o diff --git a/board/sunxi/ahci.c b/board/sunxi/ahci.c index 522e54ab16..a79b80ca1e 100644 --- a/board/sunxi/ahci.c +++ b/board/sunxi/ahci.c @@ -1,5 +1,6 @@ #include <common.h> #include <ahci.h> +#include <dm.h> #include <scsi.h> #include <errno.h> #include <asm/io.h> @@ -13,9 +14,8 @@ /* This magic PHY initialisation was taken from the Allwinner releases * and Linux driver, but is completely undocumented. */ -static int sunxi_ahci_phy_init(u32 base) +static int sunxi_ahci_phy_init(u8 *reg_base) { - u8 *reg_base = (u8 *)base; u32 reg_val; int timeout; @@ -70,10 +70,65 @@ static int sunxi_ahci_phy_init(u32 base) return 0; } +#ifndef CONFIG_DM_SCSI void scsi_init(void) { - if (sunxi_ahci_phy_init(SUNXI_SATA_BASE) < 0) + if (sunxi_ahci_phy_init((u8 *)SUNXI_SATA_BASE) < 0) return; ahci_init((void __iomem *)SUNXI_SATA_BASE); } +#else +static int sunxi_sata_probe(struct udevice *dev) +{ + ulong base; + u8 *reg; + int ret; + + base = dev_read_addr(dev); + if (base == FDT_ADDR_T_NONE) { + debug("%s: Failed to find address (err=%d\n)", __func__, ret); + return -EINVAL; + } + reg = (u8 *)base; + ret = sunxi_ahci_phy_init(reg); + if (ret) { + debug("%s: Failed to init phy (err=%d\n)", __func__, ret); + return ret; + } + ret = ahci_probe_scsi(dev, base); + if (ret) { + debug("%s: Failed to probe (err=%d\n)", __func__, ret); + return ret; + } + + return 0; +} + +static int sunxi_sata_bind(struct udevice *dev) +{ + struct udevice *scsi_dev; + int ret; + + ret = ahci_bind_scsi(dev, &scsi_dev); + if (ret) { + debug("%s: Failed to bind (err=%d\n)", __func__, ret); + return ret; + } + + return 0; +} + +static const struct udevice_id sunxi_ahci_ids[] = { + { .compatible = "allwinner,sun4i-a10-ahci" }, + { } +}; + +U_BOOT_DRIVER(ahci_sunxi_drv) = { + .name = "ahci_sunxi", + .id = UCLASS_AHCI, + .of_match = sunxi_ahci_ids, + .bind = sunxi_sata_bind, + .probe = sunxi_sata_probe, +}; +#endif diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c index 36e9cd7f84..9347329eac 100644 --- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c +++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c @@ -9,20 +9,11 @@ #include <ram.h> #include <dm/pinctrl.h> #include <dm/uclass-internal.h> -#include <misc.h> #include <asm/setup.h> #include <asm/arch/periph.h> #include <power/regulator.h> #include <u-boot/sha256.h> -#define RK3399_CPUID_OFF 0x7 -#define RK3399_CPUID_LEN 0x10 - -DECLARE_GLOBAL_DATA_PTR; - -#define RK3399_CPUID_OFF 0x7 -#define RK3399_CPUID_LEN 0x10 - DECLARE_GLOBAL_DATA_PTR; int board_init(void) @@ -107,11 +98,14 @@ static void setup_macaddr(void) static void setup_serial(void) { #if CONFIG_IS_ENABLED(ROCKCHIP_EFUSE) + const u32 cpuid_offset = 0x7; + const u32 cpuid_length = 0x10; + struct udevice *dev; int ret, i; - u8 cpuid[RK3399_CPUID_LEN]; - u8 low[RK3399_CPUID_LEN/2], high[RK3399_CPUID_LEN/2]; - char cpuid_str[RK3399_CPUID_LEN * 2 + 1]; + u8 cpuid[cpuid_length]; + u8 low[cpuid_length/2], high[cpuid_length/2]; + char cpuid_str[cpuid_length * 2 + 1]; u64 serialno; char serialno_str[16]; @@ -124,7 +118,7 @@ static void setup_serial(void) } /* read the cpu_id range from the efuses */ - ret = misc_read(dev, RK3399_CPUID_OFF, &cpuid, sizeof(cpuid)); + ret = misc_read(dev, cpuid_offset, &cpuid, sizeof(cpuid)); if (ret) { debug("%s: reading cpuid from the efuses failed\n", __func__); diff --git a/board/ti/common/Kconfig b/board/ti/common/Kconfig index c21eb8c2d2..c81baa12be 100644 --- a/board/ti/common/Kconfig +++ b/board/ti/common/Kconfig @@ -42,3 +42,4 @@ config TI_COMMON_CMD_OPTIONS imply CMD_SPI imply CMD_TIME imply CMD_USB if USB + imply ENV_IS_IN_FAT if MMC_OMAP_HS diff --git a/board/toradex/apalis-tk1/apalis-tk1.c b/board/toradex/apalis-tk1/apalis-tk1.c index c7e519c19b..5de61e7c2b 100644 --- a/board/toradex/apalis-tk1/apalis-tk1.c +++ b/board/toradex/apalis-tk1/apalis-tk1.c @@ -61,6 +61,7 @@ void pinmux_init(void) #ifdef CONFIG_PCI_TEGRA int tegra_pcie_board_init(void) { + /* TODO: Convert to driver model struct udevice *pmic; int err; @@ -94,6 +95,7 @@ int tegra_pcie_board_init(void) error("failed to set GPIO#2 high: %d\n", err); return err; } + */ /* Reset I210 Gigabit Ethernet Controller */ gpio_request(LAN_RESET_N, "LAN_RESET_N"); @@ -110,6 +112,7 @@ int tegra_pcie_board_init(void) gpio_direction_output(TEGRA_GPIO(O, 6), 0); /* Make sure LDO9 and LDO10 are initially enabled @ 0V */ + /* TODO: Convert to driver model err = as3722_ldo_enable(pmic, 9); if (err < 0) { error("failed to enable LDO9: %d\n", err); @@ -130,6 +133,7 @@ int tegra_pcie_board_init(void) error("failed to set LDO10 voltage: %d\n", err); return err; } + */ mdelay(100); @@ -137,6 +141,7 @@ int tegra_pcie_board_init(void) gpio_set_value(TEGRA_GPIO(O, 6), 1); /* Enable LDO9 and LDO10 for +V3.3_ETH on patched prototypes */ + /* TODO: Convert to driver model err = as3722_ldo_set_voltage(pmic, 9, 0xff); if (err < 0) { error("failed to set LDO9 voltage: %d\n", err); @@ -147,6 +152,7 @@ int tegra_pcie_board_init(void) error("failed to set LDO10 voltage: %d\n", err); return err; } + */ mdelay(100); gpio_set_value(LAN_RESET_N, 1); |