diff options
Diffstat (limited to 'board')
48 files changed, 1374 insertions, 287 deletions
diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig index e05f353b80..9014418433 100644 --- a/board/armltd/vexpress64/Kconfig +++ b/board/armltd/vexpress64/Kconfig @@ -1,4 +1,4 @@ -if TARGET_VEXPRESS64_BASE_FVP || TARGET_VEXPRESS64_JUNO || TARGET_VEXPRESS64_BASE_FVP_DRAM +if TARGET_VEXPRESS64_BASE_FVP || TARGET_VEXPRESS64_JUNO config SYS_BOARD default "vexpress64" diff --git a/board/armltd/vexpress64/MAINTAINERS b/board/armltd/vexpress64/MAINTAINERS index 15b0a08646..0ba044d7ff 100644 --- a/board/armltd/vexpress64/MAINTAINERS +++ b/board/armltd/vexpress64/MAINTAINERS @@ -10,11 +10,6 @@ M: Linus Walleij <linus.walleij@linaro.org> S: Maintained F: configs/vexpress_aemv8a_semi_defconfig -VEXPRESS_AEMV8A_DRAM BOARD -M: Ryan Harkin <ryan.harkin@linaro.org> -S: Maintained -F: configs/vexpress_aemv8a_dram_defconfig - JUNO DEVELOPMENT PLATFORM BOARD M: Linus Walleij <linus.walleij@linaro.org> S: Maintained diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index 6cc7c31dc6..7ce12018e7 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -13,13 +13,22 @@ config SYS_CONFIG_NAME default "qemu-riscv" config SYS_TEXT_BASE + default 0x81200000 if SPL default 0x80000000 if !RISCV_SMODE default 0x80200000 if RISCV_SMODE && ARCH_RV64I default 0x80400000 if RISCV_SMODE && ARCH_RV32I +config SPL_TEXT_BASE + default 0x80000000 + +config SPL_OPENSBI_LOAD_ADDR + hex + default 0x81000000 + config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select GENERIC_RISCV + select SUPPORT_SPL imply SYS_NS16550 imply VIRTIO_MMIO imply VIRTIO_NET @@ -43,5 +52,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply CMD_PCI imply E1000 imply NVME + imply SPL_RAM_SUPPORT + imply SPL_RAM_DEVICE endif diff --git a/board/emulation/qemu-riscv/MAINTAINERS b/board/emulation/qemu-riscv/MAINTAINERS index c701c83d77..78969ed6bd 100644 --- a/board/emulation/qemu-riscv/MAINTAINERS +++ b/board/emulation/qemu-riscv/MAINTAINERS @@ -5,5 +5,7 @@ F: board/emulation/qemu-riscv/ F: include/configs/qemu-riscv.h F: configs/qemu-riscv32_defconfig F: configs/qemu-riscv32_smode_defconfig +F: configs/qemu-riscv32_spl_defconfig F: configs/qemu-riscv64_defconfig F: configs/qemu-riscv64_smode_defconfig +F: configs/qemu-riscv64_spl_defconfig diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c index 49e304f7eb..37d48d04f2 100644 --- a/board/emulation/qemu-riscv/qemu-riscv.c +++ b/board/emulation/qemu-riscv/qemu-riscv.c @@ -7,6 +7,7 @@ #include <dm.h> #include <env.h> #include <fdtdec.h> +#include <spl.h> #include <virtio_types.h> #include <virtio.h> @@ -88,3 +89,19 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } + +#ifdef CONFIG_SPL +u32 spl_boot_device(void) +{ + /* RISC-V QEMU only supports RAM as SPL boot device */ + return BOOT_DEVICE_RAM; +} +#endif + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* boot using first FIT config */ + return 0; +} +#endif diff --git a/board/freescale/common/cds_pci_ft.c b/board/freescale/common/cds_pci_ft.c index 3ff2fa416b..fb2e5c7bf3 100644 --- a/board/freescale/common/cds_pci_ft.c +++ b/board/freescale/common/cds_pci_ft.c @@ -9,6 +9,7 @@ #include "cadmus.h" #if defined(CONFIG_OF_BOARD_SETUP) +#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI) static void cds_pci_fixup(void *blob) { int node; @@ -61,11 +62,12 @@ static void cds_pci_fixup(void *blob) } } } +#endif int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI +#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI) ft_pci_setup(blob, bd); cds_pci_fixup(blob); #endif diff --git a/board/freescale/common/emc2305.c b/board/freescale/common/emc2305.c index 8523084da9..b1ca051db2 100644 --- a/board/freescale/common/emc2305.c +++ b/board/freescale/common/emc2305.c @@ -24,10 +24,22 @@ void set_fan_speed(u8 data) I2C_EMC2305_FAN5}; for (index = 0; index < NUM_OF_FANS; index++) { +#ifndef CONFIG_DM_I2C if (i2c_write(I2C_EMC2305_ADDR, Fan[index], 1, &data, 1) != 0) { printf("Error: failed to change fan speed @%x\n", Fan[index]); } +#else + struct udevice *dev; + + if (i2c_get_chip_for_busnum(0, I2C_EMC2305_ADDR, 1, &dev)) + continue; + + if (dm_i2c_write(dev, Fan[index], &data, 1) != 0) { + printf("Error: failed to change fan speed @%x\n", + Fan[index]); + } +#endif } } @@ -36,6 +48,15 @@ void emc2305_init(void) u8 data; data = I2C_EMC2305_CMD; +#ifndef CONFIG_DM_I2C if (i2c_write(I2C_EMC2305_ADDR, I2C_EMC2305_CONF, 1, &data, 1) != 0) printf("Error: failed to configure EMC2305\n"); +#else + struct udevice *dev; + + if (!i2c_get_chip_for_busnum(0, I2C_EMC2305_ADDR, 1, &dev)) + if (dm_i2c_write(dev, I2C_EMC2305_CONF, &data, 1)) + printf("Error: failed to configure EMC2305\n"); +#endif + } diff --git a/board/freescale/common/p_corenet/pci.c b/board/freescale/common/p_corenet/pci.c index a2df928fc5..a6abe66dc0 100644 --- a/board/freescale/common/p_corenet/pci.c +++ b/board/freescale/common/p_corenet/pci.c @@ -11,6 +11,7 @@ #include <fdt_support.h> #include <asm/fsl_serdes.h> +#if !defined(CONFIG_DM_PCI) void pci_init_board(void) { fsl_pcie_init_board(0); @@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd) { FT_FSL_PCI_SETUP; } +#endif diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index f1b98bcd2a..716c93b2c2 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -21,16 +21,40 @@ #define QIXIS_LBMAP_BRDCFG_REG 0x00 #endif +#ifndef QIXIS_RCFG_CTL_RECONFIG_IDLE +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#endif +#ifndef QIXIS_RCFG_CTL_RECONFIG_START +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#endif + #ifdef CONFIG_SYS_I2C_FPGA_ADDR u8 qixis_read_i2c(unsigned int reg) { +#ifndef CONFIG_DM_I2C return i2c_reg_read(CONFIG_SYS_I2C_FPGA_ADDR, reg); +#else + struct udevice *dev; + + if (i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev)) + return 0xff; + + return dm_i2c_reg_read(dev, reg); +#endif } void qixis_write_i2c(unsigned int reg, u8 value) { u8 val = value; +#ifndef CONFIG_DM_I2C i2c_reg_write(CONFIG_SYS_I2C_FPGA_ADDR, reg, val); +#else + struct udevice *dev; + + if (!i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev)) + dm_i2c_reg_write(dev, reg, val); +#endif + } #endif @@ -142,11 +166,13 @@ static void qixis_reset(void) QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET); } +#ifdef QIXIS_LBMAP_ALTBANK static void qixis_bank_reset(void) { QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); } +#endif static void __maybe_unused set_lbmap(int lbmap) { @@ -159,12 +185,16 @@ static void __maybe_unused set_lbmap(int lbmap) static void __maybe_unused set_rcw_src(int rcw_src) { +#ifdef CONFIG_NXP_LSCH3_2 + QIXIS_WRITE(dutcfg[0], (rcw_src & 0xff)); +#else u8 reg; reg = QIXIS_READ(dutcfg[1]); reg = (reg & ~1) | (rcw_src & 1); QIXIS_WRITE(dutcfg[1], reg); QIXIS_WRITE(dutcfg[0], (rcw_src >> 1) & 0xff); +#endif } static void qixis_dump_regs(void) @@ -210,16 +240,20 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar set_lbmap(QIXIS_LBMAP_DFLTBANK); qixis_reset(); } else if (strcmp(argv[1], "altbank") == 0) { +#ifdef QIXIS_LBMAP_ALTBANK set_lbmap(QIXIS_LBMAP_ALTBANK); qixis_bank_reset(); +#else + printf("No Altbank!\n"); +#endif } else if (strcmp(argv[1], "nand") == 0) { #ifdef QIXIS_LBMAP_NAND QIXIS_WRITE(rst_ctl, 0x30); QIXIS_WRITE(rcfg_ctl, 0); set_lbmap(QIXIS_LBMAP_NAND); set_rcw_src(QIXIS_RCW_SRC_NAND); - QIXIS_WRITE(rcfg_ctl, 0x20); - QIXIS_WRITE(rcfg_ctl, 0x21); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); #else printf("Not implemented\n"); #endif @@ -233,8 +267,8 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar set_lbmap(QIXIS_LBMAP_SD); set_rcw_src(QIXIS_RCW_SRC_SD); #endif - QIXIS_WRITE(rcfg_ctl, 0x20); - QIXIS_WRITE(rcfg_ctl, 0x21); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); #else printf("Not implemented\n"); #endif @@ -244,8 +278,8 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar QIXIS_WRITE(rcfg_ctl, 0); set_lbmap(QIXIS_LBMAP_IFC); set_rcw_src(QIXIS_RCW_SRC_IFC); - QIXIS_WRITE(rcfg_ctl, 0x20); - QIXIS_WRITE(rcfg_ctl, 0x21); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); #else printf("Not implemented\n"); #endif @@ -255,8 +289,8 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar QIXIS_WRITE(rcfg_ctl, 0); set_lbmap(QIXIS_LBMAP_EMMC); set_rcw_src(QIXIS_RCW_SRC_EMMC); - QIXIS_WRITE(rcfg_ctl, 0x20); - QIXIS_WRITE(rcfg_ctl, 0x21); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); #else printf("Not implemented\n"); #endif @@ -266,8 +300,10 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar QIXIS_WRITE(rcfg_ctl, 0); set_lbmap(QIXIS_LBMAP_SD_QSPI); set_rcw_src(QIXIS_RCW_SRC_SD); - qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20); - qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), + QIXIS_RCFG_CTL_RECONFIG_IDLE); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), + QIXIS_RCFG_CTL_RECONFIG_START); #else printf("Not implemented\n"); #endif @@ -277,8 +313,10 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar QIXIS_WRITE(rcfg_ctl, 0); set_lbmap(QIXIS_LBMAP_QSPI); set_rcw_src(QIXIS_RCW_SRC_QSPI); - qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20); - qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), + QIXIS_RCFG_CTL_RECONFIG_IDLE); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), + QIXIS_RCFG_CTL_RECONFIG_START); #else printf("Not implemented\n"); #endif diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index 510d7c266b..bb655ca744 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -149,23 +149,42 @@ static int read_eeprom(void) { int ret; #ifdef CONFIG_SYS_EEPROM_BUS_NUM +#ifndef CONFIG_DM_I2C unsigned int bus; #endif +#endif if (has_been_read) return 0; #ifdef CONFIG_SYS_EEPROM_BUS_NUM +#ifndef CONFIG_DM_I2C bus = i2c_get_bus_num(); i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); #endif +#endif - ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, - (void *)&e, sizeof(e)); +#ifndef CONFIG_DM_I2C + ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + (void *)&e, sizeof(e)); +#else + struct udevice *dev; +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, + CONFIG_SYS_I2C_EEPROM_ADDR, 1, &dev); +#else + ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, 1, &dev); +#endif + if (!ret) + ret = dm_i2c_read(dev, 0, (void *)&e, sizeof(e)); +#endif #ifdef CONFIG_SYS_EEPROM_BUS_NUM +#ifndef CONFIG_DM_I2C i2c_set_bus_num(bus); #endif +#endif #ifdef DEBUG show_eeprom(); @@ -199,8 +218,10 @@ static int prog_eeprom(void) int i; void *p; #ifdef CONFIG_SYS_EEPROM_BUS_NUM +#ifndef CONFIG_DM_I2C unsigned int bus; #endif +#endif /* Set the reserved values to 0xFF */ #ifdef CONFIG_SYS_I2C_EEPROM_NXID @@ -211,10 +232,12 @@ static int prog_eeprom(void) #endif update_crc(); +#ifndef CONFIG_DM_I2C #ifdef CONFIG_SYS_EEPROM_BUS_NUM bus = i2c_get_bus_num(); i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); #endif +#endif /* * The AT24C02 datasheet says that data can only be written in page @@ -222,8 +245,26 @@ static int prog_eeprom(void) * complete a given write. */ for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) { - ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, +#ifndef CONFIG_DM_I2C + ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, p, min((int)(sizeof(e) - i), 8)); +#else + struct udevice *dev; +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, + CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + &dev); +#else + ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + &dev); +#endif + if (!ret) + ret = dm_i2c_write(dev, i, p, min((int)(sizeof(e) - i), + 8)); +#endif if (ret) break; udelay(5000); /* 5ms write cycle timing */ @@ -233,15 +274,34 @@ static int prog_eeprom(void) /* Verify the write by reading back the EEPROM and comparing */ struct eeprom e2; +#ifndef CONFIG_DM_I2C ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (void *)&e2, sizeof(e2)); + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + (void *)&e2, sizeof(e2)); +#else + struct udevice *dev; +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, + CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + &dev); +#else + ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + &dev); +#endif + if (!ret) + ret = dm_i2c_read(dev, 0, (void *)&e2, sizeof(e2)); +#endif if (!ret && memcmp(&e, &e2, sizeof(e))) ret = -1; } +#ifndef CONFIG_DM_I2C #ifdef CONFIG_SYS_EEPROM_BUS_NUM i2c_set_bus_num(bus); #endif +#endif if (ret) { printf("Programming failed.\n"); @@ -529,8 +589,24 @@ unsigned int get_cpu_board_revision(void) u8 minor; /* 0x05 Board revision, minor */ } be; +#ifndef CONFIG_DM_I2C i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (void *)&be, sizeof(be)); +#else + struct udevice *dev; +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, + CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + &dev); +#else + ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + &dev) +#endif + if (!ret) + dm_i2c_read(dev, 0, (void *)&be, sizeof(be)); +#endif if (be.id != (('C' << 24) | ('C' << 16) | ('I' << 8) | 'D')) return MPC85XX_CPU_BOARD_REV(0, 0); diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index b804971981..b37f3bf4f8 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -61,13 +61,23 @@ static int find_ir_chip_on_i2c(void) u8 byte; int i; const int ir_i2c_addr[] = {0x38, 0x08, 0x09}; +#ifdef CONFIG_DM_I2C + struct udevice *dev; +#endif /* Check all the address */ for (i = 0; i < (sizeof(ir_i2c_addr)/sizeof(ir_i2c_addr[0])); i++) { i2caddress = ir_i2c_addr[i]; +#ifndef CONFIG_DM_I2C ret = i2c_read(i2caddress, IR36021_MFR_ID_OFFSET, 1, (void *)&byte, sizeof(byte)); +#else + ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev); + if (!ret) + ret = dm_i2c_read(dev, IR36021_MFR_ID_OFFSET, + (void *)&byte, sizeof(byte)); +#endif if ((ret >= 0) && (byte == IR36021_MFR_ID)) return i2caddress; } @@ -103,11 +113,21 @@ static int read_voltage_from_INA220(int i2caddress) int i, ret, voltage_read = 0; u16 vol_mon; u8 buf[2]; +#ifdef CONFIG_DM_I2C + struct udevice *dev; +#endif for (i = 0; i < NUM_READINGS; i++) { +#ifndef CONFIG_DM_I2C ret = i2c_read(I2C_VOL_MONITOR_ADDR, I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&buf, 2); +#else + ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev); + if (!ret) + ret = dm_i2c_read(dev, I2C_VOL_MONITOR_BUS_V_OFFSET, + (void *)&buf, 2); +#endif if (ret) { printf("VID: failed to read core voltage\n"); return ret; @@ -136,11 +156,21 @@ static int read_voltage_from_IR(int i2caddress) int i, ret, voltage_read = 0; u16 vol_mon; u8 buf; +#ifdef CONFIG_DM_I2C + struct udevice *dev; +#endif for (i = 0; i < NUM_READINGS; i++) { +#ifndef CONFIG_DM_I2C ret = i2c_read(i2caddress, IR36021_LOOP1_VOUT_OFFSET, 1, (void *)&buf, 1); +#else + ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev); + if (!ret) + ret = dm_i2c_read(dev, IR36021_LOOP1_VOUT_OFFSET, + (void *)&buf, 1); +#endif if (ret) { printf("VID: failed to read vcpu\n"); return ret; @@ -179,17 +209,33 @@ static int read_voltage_from_LTC(int i2caddress) int ret, vcode = 0; u8 chan = PWM_CHANNEL0; +#ifndef CONFIG_DM_I2C /* select the PAGE 0 using PMBus commands PAGE for VDD*/ ret = i2c_write(I2C_VOL_MONITOR_ADDR, PMBUS_CMD_PAGE, 1, &chan, 1); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev); + if (!ret) + ret = dm_i2c_write(dev, PMBUS_CMD_PAGE, &chan, 1); +#endif if (ret) { printf("VID: failed to select VDD Page 0\n"); return ret; } +#ifndef CONFIG_DM_I2C /*read the output voltage using PMBus command READ_VOUT*/ ret = i2c_read(I2C_VOL_MONITOR_ADDR, PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2); +#else + ret = dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2); + if (ret) { + printf("VID: failed to read the volatge\n"); + return ret; + } +#endif if (ret) { printf("VID: failed to read the volatge\n"); return ret; @@ -294,8 +340,18 @@ static int set_voltage_to_IR(int i2caddress, int vdd) vid = DIV_ROUND_UP(vdd - 245, 5); #endif +#ifndef CONFIG_DM_I2C ret = i2c_write(i2caddress, IR36021_LOOP1_MANUAL_ID_OFFSET, 1, (void *)&vid, sizeof(vid)); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev); + if (!ret) + ret = dm_i2c_write(dev, IR36021_LOOP1_MANUAL_ID_OFFSET, + (void *)&vid, sizeof(vid)); + +#endif if (ret) { printf("VID: failed to write VID\n"); return -1; @@ -331,8 +387,17 @@ static int set_voltage_to_LTC(int i2caddress, int vdd) vdd & 0xFF, (vdd & 0xFF00) >> 8}; /* Write the desired voltage code to the regulator */ +#ifndef CONFIG_DM_I2C ret = i2c_write(I2C_VOL_MONITOR_ADDR, PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev); + if (!ret) + ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE, + (void *)&buff, 5); +#endif if (ret) { printf("VID: I2C failed to write to the volatge regulator\n"); return -1; @@ -516,14 +581,24 @@ int adjust_vdd(ulong vdd_override) } /* check IR chip work on Intel mode*/ +#ifndef CONFIG_DM_I2C ret = i2c_read(i2caddress, IR36021_INTEL_MODE_OOFSET, 1, (void *)&buf, 1); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev); + if (!ret) + ret = dm_i2c_read(dev, IR36021_INTEL_MODE_OOFSET, + (void *)&buf, 1); +#endif if (ret) { printf("VID: failed to read IR chip mode.\n"); ret = -1; goto exit; } + if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) { printf("VID: IR Chip is not used in Intel mode.\n"); ret = -1; @@ -688,9 +763,18 @@ int adjust_vdd(ulong vdd_override) } /* check IR chip work on Intel mode*/ +#ifndef CONFIG_DM_I2C ret = i2c_read(i2caddress, IR36021_INTEL_MODE_OOFSET, 1, (void *)&buf, 1); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev); + if (!ret) + ret = dm_i2c_read(dev, IR36021_INTEL_MODE_OOFSET, + (void *)&buf, 1); +#endif if (ret) { printf("VID: failed to read IR chip mode.\n"); ret = -1; diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c index 4aa7cec9ce..095971448f 100644 --- a/board/freescale/ls1028a/ls1028a.c +++ b/board/freescale/ls1028a/ls1028a.c @@ -13,6 +13,7 @@ #include <linux/libfdt.h> #include <env_internal.h> #include <asm/arch-fsl-layerscape/soc.h> +#include <asm/arch-fsl-layerscape/fsl_icid.h> #include <i2c.h> #include <asm/arch/soc.h> #ifdef CONFIG_FSL_LS_PPA @@ -73,7 +74,15 @@ int board_init(void) #if defined(CONFIG_TARGET_LS1028ARDB) u8 val = I2C_MUX_CH_DEFAULT; +#ifndef CONFIG_DM_I2C i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1); +#else + struct udevice *dev; + + if (!i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev)) + dm_i2c_write(dev, 0x0b, &val, 1); +#endif + #endif return 0; } @@ -135,6 +144,8 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory_banks(blob, base, size, 2); + fdt_fixup_icid(blob); + return 0; } #endif diff --git a/board/freescale/ls1088a/eth_ls1088aqds.c b/board/freescale/ls1088a/eth_ls1088aqds.c index d4ab9791e9..237088a537 100644 --- a/board/freescale/ls1088a/eth_ls1088aqds.c +++ b/board/freescale/ls1088a/eth_ls1088aqds.c @@ -81,11 +81,16 @@ struct ls1088a_qds_mdio { struct mii_dev *realbus; }; +struct reg_pair { + uint addr; + u8 *val; +}; + static void sgmii_configure_repeater(int dpmac) { struct mii_dev *bus; uint8_t a = 0xf; - int i, j, ret; + int i, j, k, ret; unsigned short value; const char *dev = "LS1088A_QDS_MDIO2"; int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b}; @@ -97,8 +102,28 @@ static void sgmii_configure_repeater(int dpmac) uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7}; uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84}; + u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20}; + struct reg_pair reg_pair[10] = { + {6, ®_val[0]}, {4, ®_val[1]}, + {8, ®_val[2]}, {0xf, NULL}, + {0x11, NULL}, {0x16, NULL}, + {0x18, NULL}, {0x23, ®_val[3]}, + {0x2d, ®_val[4]}, {4, ®_val[5]}, + }; +#ifdef CONFIG_DM_I2C + struct udevice *udev; +#endif + /* Set I2c to Slot 1 */ - i2c_write(0x77, 0, 0, &a, 1); +#ifndef CONFIG_DM_I2C + ret = i2c_write(0x77, 0, 0, &a, 1); +#else + ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, 0, &a, 1); +#endif + if (ret) + goto error; switch (dpmac) { case 1: @@ -144,31 +169,34 @@ static void sgmii_configure_repeater(int dpmac) return; } +#ifdef CONFIG_DM_I2C + i2c_get_chip_for_busnum(0, i2c_phy_addr, 1, &udev); +#endif + for (i = 0; i < 4; i++) { for (j = 0; j < 4; j++) { - a = 0x18; - i2c_write(i2c_phy_addr, 6, 1, &a, 1); - a = 0x38; - i2c_write(i2c_phy_addr, 4, 1, &a, 1); - a = 0x4; - i2c_write(i2c_phy_addr, 8, 1, &a, 1); - - i2c_write(i2c_phy_addr, 0xf, 1, - &ch_a_eq[i], 1); - i2c_write(i2c_phy_addr, 0x11, 1, - &ch_a_ctl2[j], 1); - - i2c_write(i2c_phy_addr, 0x16, 1, - &ch_b_eq[i], 1); - i2c_write(i2c_phy_addr, 0x18, 1, - &ch_b_ctl2[j], 1); - - a = 0x14; - i2c_write(i2c_phy_addr, 0x23, 1, &a, 1); - a = 0xb5; - i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1); - a = 0x20; - i2c_write(i2c_phy_addr, 4, 1, &a, 1); + reg_pair[3].val = &ch_a_eq[i]; + reg_pair[4].val = &ch_a_ctl2[j]; + reg_pair[5].val = &ch_b_eq[i]; + reg_pair[6].val = &ch_b_ctl2[j]; + for (k = 0; k < 10; k++) { +#ifndef CONFIG_DM_I2C + ret = i2c_write(i2c_phy_addr, + reg_pair[k].addr, + 1, reg_pair[k].val, 1); +#else + ret = i2c_get_chip_for_busnum(0, + i2c_phy_addr, + 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, + reg_pair[k].addr, + reg_pair[k].val, 1); +#endif + if (ret) + goto error; + } + mdelay(100); ret = miiphy_read(dev, phy_addr, 0x11, &value); if (ret > 0) @@ -203,7 +231,7 @@ error: static void qsgmii_configure_repeater(int dpmac) { uint8_t a = 0xf; - int i, j; + int i, j, k; int i2c_phy_addr = 0; int phy_addr = 0; int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b}; @@ -213,12 +241,32 @@ static void qsgmii_configure_repeater(int dpmac) uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7}; uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84}; + u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20}; + struct reg_pair reg_pair[10] = { + {6, ®_val[0]}, {4, ®_val[1]}, + {8, ®_val[2]}, {0xf, NULL}, + {0x11, NULL}, {0x16, NULL}, + {0x18, NULL}, {0x23, ®_val[3]}, + {0x2d, ®_val[4]}, {4, ®_val[5]}, + }; + const char *dev = mdio_names[EMI1_SLOT1]; int ret = 0; unsigned short value; +#ifdef CONFIG_DM_I2C + struct udevice *udev; +#endif /* Set I2c to Slot 1 */ - i2c_write(0x77, 0, 0, &a, 1); +#ifndef CONFIG_DM_I2C + ret = i2c_write(0x77, 0, 0, &a, 1); +#else + ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, 0, &a, 1); +#endif + if (ret) + goto error; switch (dpmac) { case 7: @@ -252,28 +300,35 @@ static void qsgmii_configure_repeater(int dpmac) return; } +#ifdef CONFIG_DM_I2C + i2c_get_chip_for_busnum(0, i2c_phy_addr, 1, &udev); +#endif + for (i = 0; i < 4; i++) { for (j = 0; j < 4; j++) { - a = 0x18; - i2c_write(i2c_phy_addr, 6, 1, &a, 1); - a = 0x38; - i2c_write(i2c_phy_addr, 4, 1, &a, 1); - a = 0x4; - i2c_write(i2c_phy_addr, 8, 1, &a, 1); - - i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1); - i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1); - - i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1); - i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1); - - a = 0x14; - i2c_write(i2c_phy_addr, 0x23, 1, &a, 1); - a = 0xb5; - i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1); - a = 0x20; - i2c_write(i2c_phy_addr, 4, 1, &a, 1); - mdelay(100); + reg_pair[3].val = &ch_a_eq[i]; + reg_pair[4].val = &ch_a_ctl2[j]; + reg_pair[5].val = &ch_b_eq[i]; + reg_pair[6].val = &ch_b_ctl2[j]; + + for (k = 0; k < 10; k++) { +#ifndef CONFIG_DM_I2C + ret = i2c_write(i2c_phy_addr, + reg_pair[k].addr, + 1, reg_pair[k].val, 1); +#else + ret = i2c_get_chip_for_busnum(0, + i2c_addr[dpmac], + 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, + reg_pair[k].addr, + reg_pair[k].val, 1); +#endif + if (ret) + goto error; + } + ret = miiphy_read(dev, phy_addr, 0x11, &value); if (ret > 0) goto error; diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index f0bea7327d..f1592982a3 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -21,6 +21,7 @@ #include <hwconfig.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/soc.h> +#include <asm/arch-fsl-layerscape/fsl_icid.h> #include "../common/qixis.h" #include "ls1088a_qixis.h" @@ -374,7 +375,15 @@ int select_i2c_ch_pca9547(u8 ch) { int ret; +#ifndef CONFIG_DM_I2C ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev); + if (!ret) + ret = dm_i2c_write(dev, 0, &ch, 1); +#endif if (ret) { puts("PCA: failed to select proper channel\n"); return ret; @@ -393,38 +402,89 @@ void board_retimer_init(void) /* Access to Control/Shared register */ reg = 0x0; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); +#else + struct udevice *dev; + + i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR, 1, &dev); + dm_i2c_write(dev, 0xff, ®, 1); +#endif /* Read device revision and ID */ +#ifndef CONFIG_DM_I2C i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1); +#else + dm_i2c_read(dev, 1, ®, 1); +#endif debug("Retimer version id = 0x%x\n", reg); /* Enable Broadcast. All writes target all channel register sets */ reg = 0x0c; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); +#else + dm_i2c_write(dev, 0xff, ®, 1); +#endif /* Reset Channel Registers */ +#ifndef CONFIG_DM_I2C i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1); +#else + dm_i2c_read(dev, 0, ®, 1); +#endif reg |= 0x4; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1); +#else + dm_i2c_write(dev, 0, ®, 1); +#endif /* Set data rate as 10.3125 Gbps */ reg = 0x90; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1); +#else + dm_i2c_write(dev, 0x60, ®, 1); +#endif reg = 0xb3; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1); +#else + dm_i2c_write(dev, 0x61, ®, 1); +#endif reg = 0x90; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1); +#else + dm_i2c_write(dev, 0x62, ®, 1); +#endif reg = 0xb3; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1); +#else + dm_i2c_write(dev, 0x63, ®, 1); +#endif reg = 0xcd; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); +#else + dm_i2c_write(dev, 0x64, ®, 1); +#endif /* Select VCO Divider to full rate (000) */ +#ifndef CONFIG_DM_I2C i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1); +#else + dm_i2c_read(dev, 0x2F, ®, 1); +#endif reg &= 0x0f; reg |= 0x70; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1); +#else + dm_i2c_write(dev, 0x2F, ®, 1); +#endif #ifdef CONFIG_TARGET_LS1088AQDS /* Retimer is connected to I2C1_CH5 */ @@ -432,38 +492,88 @@ void board_retimer_init(void) /* Access to Control/Shared register */ reg = 0x0; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1); +#else + i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2, 1, &dev); + dm_i2c_write(dev, 0xff, ®, 1); +#endif /* Read device revision and ID */ +#ifndef CONFIG_DM_I2C i2c_read(I2C_RETIMER_ADDR2, 1, 1, ®, 1); +#else + dm_i2c_read(dev, 1, ®, 1); +#endif debug("Retimer version id = 0x%x\n", reg); /* Enable Broadcast. All writes target all channel register sets */ reg = 0x0c; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1); +#else + dm_i2c_write(dev, 0xff, ®, 1); +#endif /* Reset Channel Registers */ +#ifndef CONFIG_DM_I2C i2c_read(I2C_RETIMER_ADDR2, 0, 1, ®, 1); +#else + dm_i2c_read(dev, 0, ®, 1); +#endif reg |= 0x4; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR2, 0, 1, ®, 1); +#else + dm_i2c_write(dev, 0, ®, 1); +#endif /* Set data rate as 10.3125 Gbps */ reg = 0x90; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, ®, 1); +#else + dm_i2c_write(dev, 0x60, ®, 1); +#endif reg = 0xb3; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, ®, 1); +#else + dm_i2c_write(dev, 0x61, ®, 1); +#endif reg = 0x90; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, ®, 1); +#else + dm_i2c_write(dev, 0x62, ®, 1); +#endif reg = 0xb3; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, ®, 1); +#else + dm_i2c_write(dev, 0x63, ®, 1); +#endif reg = 0xcd; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, ®, 1); +#else + dm_i2c_write(dev, 0x64, ®, 1); +#endif /* Select VCO Divider to full rate (000) */ +#ifndef CONFIG_DM_I2C i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1); +#else + dm_i2c_read(dev, 0x2F, ®, 1); +#endif reg &= 0x0f; reg |= 0x70; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1); +#else + dm_i2c_write(dev, 0x2F, ®, 1); +#endif + #endif /*return the default channel*/ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); @@ -482,6 +592,32 @@ int misc_init_r(void) QIXIS_WRITE(brdcfg[5], brdcfg5); } #endif + +#ifdef CONFIG_TARGET_LS1088AQDS + u8 brdcfg4, brdcfg5; + + if (hwconfig("dspi-on-board")) { + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= ~BRDCFG4_USBOSC_MASK; + brdcfg4 |= BRDCFG4_SPI; + QIXIS_WRITE(brdcfg[4], brdcfg4); + + brdcfg5 = QIXIS_READ(brdcfg[5]); + brdcfg5 &= ~BRDCFG5_SPR_MASK; + brdcfg5 |= BRDCFG5_SPI_ON_BOARD; + QIXIS_WRITE(brdcfg[5], brdcfg5); + } else if (hwconfig("dspi-off-board")) { + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= ~BRDCFG4_USBOSC_MASK; + brdcfg4 |= BRDCFG4_SPI; + QIXIS_WRITE(brdcfg[4], brdcfg4); + + brdcfg5 = QIXIS_READ(brdcfg[5]); + brdcfg5 &= ~BRDCFG5_SPR_MASK; + brdcfg5 |= BRDCFG5_SPI_OFF_BOARD; + QIXIS_WRITE(brdcfg[5], brdcfg5); + } +#endif return 0; } #endif @@ -500,16 +636,30 @@ int get_serdes_volt(void) u8 chan = PWM_CHANNEL0; /* Select the PAGE 0 using PMBus commands PAGE for VDD */ +#ifndef CONFIG_DM_I2C ret = i2c_write(I2C_SVDD_MONITOR_ADDR, PMBUS_CMD_PAGE, 1, &chan, 1); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev); + if (!ret) + ret = dm_i2c_write(dev, PMBUS_CMD_PAGE, + &chan, 1); +#endif + if (ret) { printf("VID: failed to select VDD Page 0\n"); return ret; } /* Read the output voltage using PMBus command READ_VOUT */ +#ifndef CONFIG_DM_I2C ret = i2c_read(I2C_SVDD_MONITOR_ADDR, PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2); +#else + dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2); +#endif if (ret) { printf("VID: failed to read the volatge\n"); return ret; @@ -525,8 +675,17 @@ int set_serdes_volt(int svdd) svdd & 0xFF, (svdd & 0xFF00) >> 8}; /* Write the desired voltage code to the SVDD regulator */ +#ifndef CONFIG_DM_I2C ret = i2c_write(I2C_SVDD_MONITOR_ADDR, PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev); + if (!ret) + ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE, + (void *)&buff, 5); +#endif if (ret) { printf("VID: I2C failed to write to the volatge regulator\n"); return -1; @@ -557,8 +716,18 @@ int set_serdes_volt(int svdd) printf("SVDD changing of RDB\n"); /* Read the BRDCFG54 via CLPD */ +#ifndef CONFIG_DM_I2C ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR, QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev); + if (!ret) + ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET, + (void *)&brdcfg4, 1); +#endif + if (ret) { printf("VID: I2C failed to read the CPLD BRDCFG4\n"); return -1; @@ -567,8 +736,14 @@ int set_serdes_volt(int svdd) brdcfg4 = brdcfg4 | 0x08; /* Write to the BRDCFG4 */ +#ifndef CONFIG_DM_I2C ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1); +#else + ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET, + (void *)&brdcfg4, 1); +#endif + if (ret) { debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n"); return -1; @@ -739,11 +914,26 @@ void fsl_fdt_fixup_flash(void *fdt) int ft_board_setup(void *blob, bd_t *bd) { int i; - u64 base[CONFIG_NR_DRAM_BANKS]; - u64 size[CONFIG_NR_DRAM_BANKS]; + u16 mc_memory_bank = 0; + + u64 *base; + u64 *size; + u64 mc_memory_base = 0; + u64 mc_memory_size = 0; + u16 total_memory_banks; ft_cpu_setup(blob, bd); + fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size); + + if (mc_memory_base != 0) + mc_memory_bank++; + + total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank; + + base = calloc(total_memory_banks, sizeof(u64)); + size = calloc(total_memory_banks, sizeof(u64)); + /* fixup DT for the two GPP DDR banks */ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { base[i] = gd->bd->bi_dram[i].start; @@ -760,7 +950,17 @@ int ft_board_setup(void *blob, bd_t *bd) size[1] = gd->arch.resv_ram - base[1]; #endif - fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS); + if (mc_memory_base != 0) { + for (i = 0; i <= total_memory_banks; i++) { + if (base[i] == 0 && size[i] == 0) { + base[i] = mc_memory_base; + size[i] = mc_memory_size; + break; + } + } + } + + fdt_fixup_memory_banks(blob, base, size, total_memory_banks); fdt_fsl_mc_fixup_iommu_map_entry(blob); @@ -769,6 +969,9 @@ int ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_FSL_MC_ENET fdt_fixup_board_enet(blob); #endif + + fdt_fixup_icid(blob); + if (is_pb_board()) fixup_ls1088ardb_pb_banner(blob); diff --git a/board/freescale/ls1088a/ls1088a_qixis.h b/board/freescale/ls1088a/ls1088a_qixis.h index c58852617f..e3502eb1d1 100644 --- a/board/freescale/ls1088a/ls1088a_qixis.h +++ b/board/freescale/ls1088a/ls1088a_qixis.h @@ -41,4 +41,15 @@ #define BRDCFG5_SPISDHC_MASK 0x0C #define BRDCFG5_FORCE_SD 0x08 +/* Definitions of QIXIS Registers for LS1088AQDS */ + +/* BRDCFG4 */ +#define BRDCFG4_USBOSC_MASK 0x01 +#define BRDCFG4_SPI 0x01 + +/* BRDCFG5 */ +#define BRDCFG5_SPR_MASK 0x0f +#define BRDCFG5_SPI_ON_BOARD 0x0a +#define BRDCFG5_SPI_OFF_BOARD 0x0f + #endif diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c index 1b4e6c65fb..6a8788c312 100644 --- a/board/freescale/ls2080aqds/eth.c +++ b/board/freescale/ls2080aqds/eth.c @@ -90,11 +90,16 @@ struct ls2080a_qds_mdio { struct mii_dev *realbus; }; +struct reg_pair { + uint addr; + u8 *val; +}; + static void sgmii_configure_repeater(int serdes_port) { struct mii_dev *bus; uint8_t a = 0xf; - int i, j, ret; + int i, j, k, ret; int dpmac_id = 0, dpmac, mii_bus = 0; unsigned short value; char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"}; @@ -105,10 +110,30 @@ static void sgmii_configure_repeater(int serdes_port) uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7}; uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84}; + u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20}; + struct reg_pair reg_pair[10] = { + {6, ®_val[0]}, {4, ®_val[1]}, + {8, ®_val[2]}, {0xf, NULL}, + {0x11, NULL}, {0x16, NULL}, + {0x18, NULL}, {0x23, ®_val[3]}, + {0x2d, ®_val[4]}, {4, ®_val[5]}, + }; + int *riser_phy_addr = &xqsgii_riser_phy_addr[0]; +#ifdef CONFIG_DM_I2C + struct udevice *udev; +#endif /* Set I2c to Slot 1 */ - i2c_write(0x77, 0, 0, &a, 1); +#ifndef CONFIG_DM_I2C + ret = i2c_write(0x77, 0, 0, &a, 1); +#else + ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, 0, &a, 1); +#endif + if (ret) + goto error; for (dpmac = 0; dpmac < 8; dpmac++) { /* Check the PHY status */ @@ -121,7 +146,15 @@ static void sgmii_configure_repeater(int serdes_port) mii_bus = 1; dpmac_id = dpmac + 9; a = 0xb; - i2c_write(0x76, 0, 0, &a, 1); +#ifndef CONFIG_DM_I2C + ret = i2c_write(0x76, 0, 0, &a, 1); +#else + ret = i2c_get_chip_for_busnum(0, 0x76, 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, 0, &a, 1); +#endif + if (ret) + goto error; break; } @@ -154,29 +187,29 @@ static void sgmii_configure_repeater(int serdes_port) for (i = 0; i < 4; i++) { for (j = 0; j < 4; j++) { - a = 0x18; - i2c_write(i2c_addr[dpmac], 6, 1, &a, 1); - a = 0x38; - i2c_write(i2c_addr[dpmac], 4, 1, &a, 1); - a = 0x4; - i2c_write(i2c_addr[dpmac], 8, 1, &a, 1); - - i2c_write(i2c_addr[dpmac], 0xf, 1, - &ch_a_eq[i], 1); - i2c_write(i2c_addr[dpmac], 0x11, 1, - &ch_a_ctl2[j], 1); - - i2c_write(i2c_addr[dpmac], 0x16, 1, - &ch_b_eq[i], 1); - i2c_write(i2c_addr[dpmac], 0x18, 1, - &ch_b_ctl2[j], 1); - - a = 0x14; - i2c_write(i2c_addr[dpmac], 0x23, 1, &a, 1); - a = 0xb5; - i2c_write(i2c_addr[dpmac], 0x2d, 1, &a, 1); - a = 0x20; - i2c_write(i2c_addr[dpmac], 4, 1, &a, 1); + reg_pair[3].val = &ch_a_eq[i]; + reg_pair[4].val = &ch_a_ctl2[j]; + reg_pair[5].val = &ch_b_eq[i]; + reg_pair[6].val = &ch_b_ctl2[j]; + + for (k = 0; k < 10; k++) { +#ifndef CONFIG_DM_I2C + ret = i2c_write(i2c_addr[dpmac], + reg_pair[k].addr, + 1, reg_pair[k].val, 1); +#else + ret = i2c_get_chip_for_busnum(0, + i2c_addr[dpmac], + 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, + reg_pair[k].addr, + reg_pair[k].val, 1); +#endif + if (ret) + goto error; + } + mdelay(100); ret = miiphy_read(dev[mii_bus], riser_phy_addr[dpmac], @@ -217,7 +250,7 @@ error: static void qsgmii_configure_repeater(int dpmac) { uint8_t a = 0xf; - int i, j; + int i, j, k; int i2c_phy_addr = 0; int phy_addr = 0; int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b}; @@ -227,12 +260,32 @@ static void qsgmii_configure_repeater(int dpmac) uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7}; uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84}; + u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20}; + struct reg_pair reg_pair[10] = { + {6, ®_val[0]}, {4, ®_val[1]}, + {8, ®_val[2]}, {0xf, NULL}, + {0x11, NULL}, {0x16, NULL}, + {0x18, NULL}, {0x23, ®_val[3]}, + {0x2d, ®_val[4]}, {4, ®_val[5]}, + }; + const char *dev = "LS2080A_QDS_MDIO0"; int ret = 0; unsigned short value; +#ifdef CONFIG_DM_I2C + struct udevice *udev; +#endif /* Set I2c to Slot 1 */ - i2c_write(0x77, 0, 0, &a, 1); +#ifndef CONFIG_DM_I2C + ret = i2c_write(0x77, 0, 0, &a, 1); +#else + ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, 0, &a, 1); +#endif + if (ret) + goto error; switch (dpmac) { case 1: @@ -283,25 +336,29 @@ static void qsgmii_configure_repeater(int dpmac) for (i = 0; i < 4; i++) { for (j = 0; j < 4; j++) { - a = 0x18; - i2c_write(i2c_phy_addr, 6, 1, &a, 1); - a = 0x38; - i2c_write(i2c_phy_addr, 4, 1, &a, 1); - a = 0x4; - i2c_write(i2c_phy_addr, 8, 1, &a, 1); - - i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1); - i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1); - - i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1); - i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1); - - a = 0x14; - i2c_write(i2c_phy_addr, 0x23, 1, &a, 1); - a = 0xb5; - i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1); - a = 0x20; - i2c_write(i2c_phy_addr, 4, 1, &a, 1); + reg_pair[3].val = &ch_a_eq[i]; + reg_pair[4].val = &ch_a_ctl2[j]; + reg_pair[5].val = &ch_b_eq[i]; + reg_pair[6].val = &ch_b_ctl2[j]; + + for (k = 0; k < 10; k++) { +#ifndef CONFIG_DM_I2C + ret = i2c_write(i2c_phy_addr, + reg_pair[k].addr, + 1, reg_pair[k].val, 1); +#else + ret = i2c_get_chip_for_busnum(0, + i2c_phy_addr, + 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, + reg_pair[k].addr, + reg_pair[k].val, 1); +#endif + if (ret) + goto error; + } + mdelay(100); ret = miiphy_read(dev, phy_addr, 0x11, &value); if (ret > 0) diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index e9c055745f..91c80353ed 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -161,8 +161,16 @@ unsigned long get_board_ddr_clk(void) int select_i2c_ch_pca9547(u8 ch) { int ret; +#ifdef CONFIG_DM_I2C + struct udevice *dev; + ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev); + if (!ret) + ret = dm_i2c_write(dev, 0, &ch, 1); + +#else ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); +#endif if (ret) { puts("PCA: failed to select proper channel\n"); return ret; @@ -225,7 +233,15 @@ int board_init(void) gd->env_addr = (ulong)&default_environment[0]; #endif select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + +#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT +#ifdef CONFIG_DM_I2C + rtc_enable_32khz_output(0, CONFIG_SYS_I2C_RTC_ADDR); +#else rtc_enable_32khz_output(); +#endif +#endif + #ifdef CONFIG_FSL_CAAM sec_init(); #endif diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 2b2dbbb0ce..e20267f27c 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -164,7 +164,16 @@ int select_i2c_ch_pca9547(u8 ch) { int ret; +#ifndef CONFIG_DM_I2C ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev); + if (!ret) + ret = dm_i2c_write(dev, 0, &ch, 1); +#endif + if (ret) { puts("PCA: failed to select proper channel\n"); return ret; @@ -410,11 +419,27 @@ void fsl_fdt_fixup_flash(void *fdt) int ft_board_setup(void *blob, bd_t *bd) { - u64 base[CONFIG_NR_DRAM_BANKS]; - u64 size[CONFIG_NR_DRAM_BANKS]; + int i; + u16 mc_memory_bank = 0; + + u64 *base; + u64 *size; + u64 mc_memory_base = 0; + u64 mc_memory_size = 0; + u16 total_memory_banks; ft_cpu_setup(blob, bd); + fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size); + + if (mc_memory_base != 0) + mc_memory_bank++; + + total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank; + + base = calloc(total_memory_banks, sizeof(u64)); + size = calloc(total_memory_banks, sizeof(u64)); + /* fixup DT for the two GPP DDR banks */ base[0] = gd->bd->bi_dram[0].start; size[0] = gd->bd->bi_dram[0].size; @@ -431,7 +456,17 @@ int ft_board_setup(void *blob, bd_t *bd) size[1] = gd->arch.resv_ram - base[1]; #endif - fdt_fixup_memory_banks(blob, base, size, 2); + if (mc_memory_base != 0) { + for (i = 0; i <= total_memory_banks; i++) { + if (base[i] == 0 && size[i] == 0) { + base[i] = mc_memory_base; + size[i] = mc_memory_size; + break; + } + } + } + + fdt_fixup_memory_banks(blob, base, size, total_memory_banks); fdt_fsl_mc_fixup_iommu_map_entry(blob); diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index f3885fa8b7..7f19a1a145 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -74,7 +74,15 @@ int select_i2c_ch_pca9547(u8 ch) { int ret; +#ifndef CONFIG_DM_I2C ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev); + if (!ret) + ret = dm_i2c_write(dev, 0, &ch, 1); +#endif if (ret) { puts("PCA: failed to select proper channel\n"); return ret; @@ -402,6 +410,26 @@ int config_board_mux(void) return 0; } +#elif defined(CONFIG_TARGET_LX2160ARDB) +int config_board_mux(void) +{ + u8 brdcfg; + + brdcfg = QIXIS_READ(brdcfg[4]); + /* The BRDCFG4 register controls general board configuration. + *|-------------------------------------------| + *|Field | Function | + *|-------------------------------------------| + *|5 | CAN I/O Enable (net CFG_CAN_EN_B):| + *|CAN_EN | 0= CAN transceivers are disabled. | + *| | 1= CAN transceivers are enabled. | + *|-------------------------------------------| + */ + brdcfg |= BIT_MASK(5); + QIXIS_WRITE(brdcfg[4], brdcfg); + + return 0; +} #else int config_board_mux(void) { @@ -529,11 +557,26 @@ void board_quiesce_devices(void) int ft_board_setup(void *blob, bd_t *bd) { int i; - u64 base[CONFIG_NR_DRAM_BANKS]; - u64 size[CONFIG_NR_DRAM_BANKS]; + u16 mc_memory_bank = 0; + + u64 *base; + u64 *size; + u64 mc_memory_base = 0; + u64 mc_memory_size = 0; + u16 total_memory_banks; ft_cpu_setup(blob, bd); + fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size); + + if (mc_memory_base != 0) + mc_memory_bank++; + + total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank; + + base = calloc(total_memory_banks, sizeof(u64)); + size = calloc(total_memory_banks, sizeof(u64)); + /* fixup DT for the three GPP DDR banks */ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { base[i] = gd->bd->bi_dram[i].start; @@ -553,7 +596,17 @@ int ft_board_setup(void *blob, bd_t *bd) size[2] = gd->arch.resv_ram - base[2]; #endif - fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS); + if (mc_memory_base != 0) { + for (i = 0; i <= total_memory_banks; i++) { + if (base[i] == 0 && size[i] == 0) { + base[i] = mc_memory_base; + size[i] = mc_memory_size; + break; + } + } + } + + fdt_fixup_memory_banks(blob, base, size, total_memory_banks); #ifdef CONFIG_USB fsl_fdt_fixup_dr_usb(blob, bd); diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 7d819d8df5..2799b5b5a4 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -164,7 +164,7 @@ void lbc_sdram_init(void) #endif /* enable SDRAM init */ } -#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) +#if (defined(CONFIG_PCI) || defined(CONFIG_PCI1)) && !defined(CONFIG_DM_PCI) /* For some reason the Tundra PCI bridge shows up on itself as a * different device. Work around that by refusing to configure it. */ @@ -189,6 +189,7 @@ static struct pci_config_table pci_mpc85xxcds_config_table[] = { static struct pci_controller pci1_hose; #endif /* CONFIG_PCI */ +#if !defined(CONFIG_DM_PCI) void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); @@ -268,6 +269,7 @@ void pci_init_board(void) fsl_pcie_init_board(first_free_busno); } +#endif void configure_rgmii(void) { @@ -349,7 +351,7 @@ int board_eth_init(bd_t *bis) return pci_eth_init(bis); } -#if defined(CONFIG_OF_BOARD_SETUP) +#if defined(CONFIG_OF_BOARD_SETUP) && !defined(CONFIG_DM_PCI) void ft_pci_setup(void *blob, bd_t *bd) { FT_FSL_PCI_SETUP; diff --git a/board/freescale/p1_p2_rdb_pc/README b/board/freescale/p1_p2_rdb_pc/README index f4cc43fbfa..b85cf0209e 100644 --- a/board/freescale/p1_p2_rdb_pc/README +++ b/board/freescale/p1_p2_rdb_pc/README @@ -45,3 +45,22 @@ enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below 'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD. 'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD. + +Device tree support and how to enable it for different configs +-------------------------------------------------------------- +Device tree support is available for p1020rdb and p2020rdb for below mentioned boot, +1. NOR Boot +2. NAND Boot +3. SD Boot +4. SPIFLASH Boot + +To enable device tree support for other boot, below configs need to be +enabled in relative defconfig file, +1. CONFIG_DEFAULT_DEVICE_TREE="p1020rdb" (Change default device tree name if required) +2. CONFIG_OF_CONTROL +3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at + CONFIG_RESET_VECTOR_ADDRESS - 0xffc + +If device tree support is enabled in defconfig, +1. use 'u-boot-with-dtb.bin' for NOR boot. +2. use 'u-boot-with-spl.bin' for other boot. diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index a04a73528f..3649f16598 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -278,7 +278,7 @@ int checkboard(void) return 0; } -#ifdef CONFIG_PCI +#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI) void pci_init_board(void) { fsl_pcie_init_board(0); @@ -444,7 +444,9 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#if !defined(CONFIG_DM_PCI) FT_FSL_PCI_SETUP; +#endif #ifdef CONFIG_QE do_fixup_by_compat(blob, "fsl,qe", "status", "okay", diff --git a/board/freescale/p2041rdb/README b/board/freescale/p2041rdb/README index 9b5539fff3..79f77e4961 100644 --- a/board/freescale/p2041rdb/README +++ b/board/freescale/p2041rdb/README @@ -85,6 +85,24 @@ Boot from SPI flash SW1[1-5] = 10100 Note: 1 stands for 'on', 0 stands for 'off' +Device tree support and how to enable it for different configs +-------------------------------------------------------------- +Device tree support is available for p2041rdb for below mentioned boot, +1. NOR Boot +2. NAND Boot +3. SD Boot +4. SPIFLASH Boot + +To enable device tree support for other boot, below configs need to be +enabled in relative defconfig file, +1. CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" (Change default device tree name if required) +2. CONFIG_OF_CONTROL +3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at + CONFIG_RESET_VECTOR_ADDRESS - 0xffc + +If device tree support is enabled in defconfig, use 'u-boot-with-dtb.bin' +instead of u-boot.bin for all boot. + CPLD command ============ The CPLD is used to control the power sequence and some serdes lane diff --git a/board/freescale/t102xrdb/README b/board/freescale/t102xrdb/README index a0af25a432..dde3f8ca37 100644 --- a/board/freescale/t102xrdb/README +++ b/board/freescale/t102xrdb/README @@ -251,6 +251,25 @@ Software configurations and board settings SW3[3] = '0' for eMMC (or 'switch emmc' by software) +device tree support and how to enable it for different configs +-------------------------------------------------------------- +device tree support is available for t1024rdb for below mentioned boot, +1. nor boot +2. nand boot +3. sd boot +4. spiflash boot + +to enable device tree support for other boot, below configs need to be +enabled in relative defconfig file, +1. config_default_device_tree="t1024rdb" (change default device tree name if required) +2. config_of_control +3. config_mpc85xx_have_reset_vector if reset vector is located at + config_reset_vector_address - 0xffc + +if device tree support is enabled in defconfig, +1. use 'u-boot-with-dtb.bin' for nor boot. +2. use 'u-boot-with-spl-pbl.bin' for other boot. + 2-stage NAND/SPI/SD boot loader ------------------------------- PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM. diff --git a/board/freescale/t102xrdb/pci.c b/board/freescale/t102xrdb/pci.c index 161b8cb403..adc128d924 100644 --- a/board/freescale/t102xrdb/pci.c +++ b/board/freescale/t102xrdb/pci.c @@ -11,6 +11,7 @@ #include <fdt_support.h> #include <asm/fsl_serdes.h> +#if !defined(CONFIG_DM_PCI) void pci_init_board(void) { fsl_pcie_init_board(0); @@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd) { FT_FSL_PCI_SETUP; } +#endif diff --git a/board/freescale/t104xrdb/README b/board/freescale/t104xrdb/README index 98b3f63db2..09cb98e33d 100644 --- a/board/freescale/t104xrdb/README +++ b/board/freescale/t104xrdb/README @@ -365,3 +365,22 @@ to 2. SPI does not support flush so remove flush from pbl, make changes in tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000 with 0x091380c0 + +Device tree support and how to enable it for different configs +-------------------------------------------------------------- +Device tree support is available for t1042d4rdb for below mentioned boot, +1. NOR Boot +2. NAND Boot +3. SD Boot +4. SPIFLASH Boot + +To enable device tree support for other boot, below configs need to be +enabled in relative defconfig file, +1. CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb" (Change default device tree name if required) +2. CONFIG_OF_CONTROL +3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at + CONFIG_RESET_VECTOR_ADDRESS - 0xffc + +If device tree support is enabled in defconfig, +1. use 'u-boot-with-dtb.bin' for NOR boot. +2. use 'u-boot-with-spl-pbl.bin' for other boot. diff --git a/board/freescale/t104xrdb/pci.c b/board/freescale/t104xrdb/pci.c index 9fd66594f4..6b666ba2d2 100644 --- a/board/freescale/t104xrdb/pci.c +++ b/board/freescale/t104xrdb/pci.c @@ -11,6 +11,7 @@ #include <fdt_support.h> #include <asm/fsl_serdes.h> +#if !defined(CONFIG_DM_PCI) void pci_init_board(void) { fsl_pcie_init_board(0); @@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd) { FT_FSL_PCI_SETUP; } +#endif diff --git a/board/freescale/t208xrdb/README b/board/freescale/t208xrdb/README index 42b2b92396..9e4b28faf4 100644 --- a/board/freescale/t208xrdb/README +++ b/board/freescale/t208xrdb/README @@ -262,3 +262,22 @@ How to update the ucode of Freescale FMAN For more details, please refer to T2080PCIe-RDB User Guide and access website www.freescale.com and Freescale QorIQ SDK Infocenter document. + +Device tree support and how to enable it for different configs +-------------------------------------------------------------- +Device tree support is available for t2080rdb for below mentioned boot, +1. NOR Boot +2. NAND Boot +3. SD Boot +4. SPIFLASH Boot + +To enable device tree support for other boot, below configs need to be +enabled in relative defconfig file, +1. CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" (Change default device tree name if required) +2. CONFIG_OF_CONTROL +3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at + CONFIG_RESET_VECTOR_ADDRESS - 0xffc + +If device tree support is enabled in defconfig, +1. use 'u-boot-with-dtb.bin' for NOR boot. +2. use 'u-boot-with-spl-pbl.bin' for other boot. diff --git a/board/freescale/t208xrdb/pci.c b/board/freescale/t208xrdb/pci.c index 161b8cb403..adc128d924 100644 --- a/board/freescale/t208xrdb/pci.c +++ b/board/freescale/t208xrdb/pci.c @@ -11,6 +11,7 @@ #include <fdt_support.h> #include <asm/fsl_serdes.h> +#if !defined(CONFIG_DM_PCI) void pci_init_board(void) { fsl_pcie_init_board(0); @@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd) { FT_FSL_PCI_SETUP; } +#endif diff --git a/board/freescale/t4rdb/pci.c b/board/freescale/t4rdb/pci.c index 4100370e20..7d670e1a2f 100644 --- a/board/freescale/t4rdb/pci.c +++ b/board/freescale/t4rdb/pci.c @@ -11,6 +11,7 @@ #include <fdt_support.h> #include <asm/fsl_serdes.h> +#if !defined(CONFIG_DM_PCI) void pci_init_board(void) { fsl_pcie_init_board(0); @@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd) { FT_FSL_PCI_SETUP; } +#endif diff --git a/board/rockchip/fennec_rk3288/Kconfig b/board/rockchip/fennec_rk3288/Kconfig deleted file mode 100644 index 1dcfcf0317..0000000000 --- a/board/rockchip/fennec_rk3288/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_FENNEC_RK3288 - -config SYS_BOARD - default "fennec_rk3288" - -config SYS_VENDOR - default "rockchip" - -config SYS_CONFIG_NAME - default "fennec_rk3288" - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - -endif diff --git a/board/rockchip/fennec_rk3288/MAINTAINERS b/board/rockchip/fennec_rk3288/MAINTAINERS deleted file mode 100644 index 78a389b060..0000000000 --- a/board/rockchip/fennec_rk3288/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -FENNEC-RK3288 -M: Lin Huang <hl@rock-chips.com> -S: Maintained -F: board/rockchip/fennec_rk3288 -F: include/configs/fennec_rk3288.h -F: configs/fennec-rk3288_defconfig diff --git a/board/rockchip/fennec_rk3288/Makefile b/board/rockchip/fennec_rk3288/Makefile deleted file mode 100644 index b287db699e..0000000000 --- a/board/rockchip/fennec_rk3288/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# (C) Copyright 2016 Rockchip Electronics Co., Ltd -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += fennec-rk3288.o diff --git a/board/rockchip/fennec_rk3288/fennec-rk3288.c b/board/rockchip/fennec_rk3288/fennec-rk3288.c deleted file mode 100644 index 779bc646b2..0000000000 --- a/board/rockchip/fennec_rk3288/fennec-rk3288.c +++ /dev/null @@ -1,5 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c index 676935a843..75462d1c34 100644 --- a/board/siemens/common/board.c +++ b/board/siemens/common/board.c @@ -189,14 +189,11 @@ void set_env_gpios(unsigned char state) { char *ptr_env; char str_tmp[5]; /* must contain "ledX"*/ - char num[1]; unsigned char i, idx, pos1, pos2, ccount; unsigned char gpio_n, gpio_s0, gpio_s1; for (i = 0; i < MAX_NR_LEDS; i++) { - strcpy(str_tmp, "led"); - sprintf(num, "%d", i); - strcat(str_tmp, num); + sprintf(str_tmp, "led%d", i); /* If env var is not found we stop */ ptr_env = env_get(str_tmp); diff --git a/board/siemens/draco/MAINTAINERS b/board/siemens/draco/MAINTAINERS index e9107f08bf..c73f18c002 100644 --- a/board/siemens/draco/MAINTAINERS +++ b/board/siemens/draco/MAINTAINERS @@ -1,5 +1,5 @@ DRACO BOARD -M: Roger Meier <r.meier@siemens.com> +M: Samuel Egli <samuel.egli@siemens.com> S: Maintained F: board/siemens/draco/ F: include/configs/draco.h diff --git a/board/siemens/pxm2/MAINTAINERS b/board/siemens/pxm2/MAINTAINERS index fa734c9c11..dc02fe87c9 100644 --- a/board/siemens/pxm2/MAINTAINERS +++ b/board/siemens/pxm2/MAINTAINERS @@ -1,5 +1,5 @@ PXM2 BOARD -M: Roger Meier <r.meier@siemens.com> +M: Samuel Egli <samuel.egli@siemens.com> S: Maintained F: board/siemens/pxm2/ F: include/configs/pxm2.h diff --git a/board/siemens/rut/MAINTAINERS b/board/siemens/rut/MAINTAINERS index 8c1b77059b..1e92710904 100644 --- a/board/siemens/rut/MAINTAINERS +++ b/board/siemens/rut/MAINTAINERS @@ -1,5 +1,5 @@ RUT BOARD -M: Roger Meier <r.meier@siemens.com> +M: Samuel Egli <samuel.egli@siemens.com> S: Maintained F: board/siemens/rut/ F: include/configs/rut.h diff --git a/board/st/stm32mp1/Kconfig b/board/st/stm32mp1/Kconfig index 87216c0963..4fa2360b4f 100644 --- a/board/st/stm32mp1/Kconfig +++ b/board/st/stm32mp1/Kconfig @@ -22,4 +22,8 @@ config CMD_STBOARD This compile the stboard command to read and write the board in the OTP. +config TARGET_STM32MP157C_DK2 + bool "support of STMicroelectronics STM32MP157C-DK2 Discovery Board" + default y + endif diff --git a/board/st/stm32mp1/MAINTAINERS b/board/st/stm32mp1/MAINTAINERS index 3bf4c21b60..2930947716 100644 --- a/board/st/stm32mp1/MAINTAINERS +++ b/board/st/stm32mp1/MAINTAINERS @@ -1,9 +1,10 @@ STM32MP1 BOARD M: Patrick Delaunay <patrick.delaunay@st.com> L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers) +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git S: Maintained -F: arch/arm/dts/stm32mp157* -F: board/st/stm32mp1 +F: arch/arm/dts/stm32mp15* +F: board/st/stm32mp1/ F: configs/stm32mp15_basic_defconfig F: configs/stm32mp15_optee_defconfig F: configs/stm32mp15_trusted_defconfig diff --git a/board/st/stm32mp1/README b/board/st/stm32mp1/README index 428357cfa0..c807e0842e 100644 --- a/board/st/stm32mp1/README +++ b/board/st/stm32mp1/README @@ -139,7 +139,6 @@ the supported device trees for stm32mp157 are: # make DEVICE_TREE=<name> all - example: a) trusted boot on ev1 # export KBUILD_OUTPUT=stm32mp15_trusted @@ -190,7 +189,7 @@ the supported device trees for stm32mp157 are: 6. Switch Setting for Boot Mode =============================== -You can select the boot mode, on the board ed1 with the switch SW1 +You can select the boot mode, on the board with one switch : - on the daugther board ed1 with the switch SW1 : BOOT0, BOOT1, BOOT2 @@ -358,3 +357,36 @@ on bank 0 to access to internal OTP: 4 check env update STM32MP> print ethaddr ethaddr=12:34:56:78:9a:bc + +10. Coprocessor firmware +======================== + +U-Boot can boot the coprocessor before the kernel (coprocessor early boot). + +A/ Manuallly by using rproc commands (update the bootcmd) + Configurations + # env set name_copro "rproc-m4-fw.elf" + # env set dev_copro 0 + # env set loadaddr_copro 0xC1000000 + + Load binary from bootfs partition (number 4) on SDCard (mmc 0) + # ext4load mmc 0:4 ${loadaddr_copro} ${name_copro} + => ${filesize} updated with the size of the loaded file + + Start M4 firmware with remote proc command + # rproc init + # rproc load ${dev_copro} ${loadaddr_copro} ${filesize} + # rproc start ${dev_copro} + +B/ Automatically by using FIT feature and generic DISTRO bootcmd + + see examples in this directory : + + Generate FIT including kernel + device tree + M4 firmware + with cfg with M4 boot + $> mkimage -f fit_copro_kernel_dtb.its fit_copro_kernel_dtb.itb + + Then using DISTRO configuration file: see extlinux.conf to select + the correct configuration + => stm32mp157c-ev1-m4 + => stm32mp157c-dk2-m4 diff --git a/board/st/stm32mp1/cmd_stboard.c b/board/st/stm32mp1/cmd_stboard.c index f781c364cf..04352ae8ed 100644 --- a/board/st/stm32mp1/cmd_stboard.c +++ b/board/st/stm32mp1/cmd_stboard.c @@ -60,7 +60,7 @@ static int do_stboard(cmd_tbl_t *cmdtp, int flag, int argc, ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD), &otp, sizeof(otp)); - if (ret) { + if (ret < 0) { puts("OTP read error"); return CMD_RET_FAILURE; } diff --git a/board/st/stm32mp1/extlinux.conf b/board/st/stm32mp1/extlinux.conf new file mode 100644 index 0000000000..2b4632804d --- /dev/null +++ b/board/st/stm32mp1/extlinux.conf @@ -0,0 +1,20 @@ +# Generic Distro Configuration for STM32MP157 +menu title Select the boot mode +TIMEOUT 20 +DEFAULT stm32mp157c-ev1 + +LABEL stm32mp157c-ev1 + KERNEL /fit_kernel_dtb.itb#ev1 + APPEND root=/dev/mmcblk0p6 rootwait rw earlyprintk console=ttyS3,115200 + +LABEL stm32mp157c-ev1-m4 + KERNEL /fit_copro_kernel_dtb.itb#ev1-m4 + APPEND root=/dev/mmcblk0p6 rootwait rw earlyprintk console=ttyS3,115200 + +LABEL stm32mp157c-dk2 + KERNEL /fit_kernel_dtb.itb#dk2 + APPEND root=/dev/mmcblk0p6 rootwait rw earlyprintk console=ttyS3,115200 + +LABEL stm32mp157c-dk2-m4 + KERNEL /fit_copro_kernel_dtb.itb#dk2-m4 + APPEND root=/dev/mmcblk0p6 rootwait rw earlyprintk console=ttyS3,115200 diff --git a/board/st/stm32mp1/fit_copro_kernel_dtb.its b/board/st/stm32mp1/fit_copro_kernel_dtb.its new file mode 100644 index 0000000000..3e08fd943e --- /dev/null +++ b/board/st/stm32mp1/fit_copro_kernel_dtb.its @@ -0,0 +1,103 @@ +/* + * Compilation: + * mkimage -f fit_copro_kernel_dtb.its fit_copro_kernel_dtb.itb + */ + +/dts-v1/; +/ { + description = "U-Boot fitImage for stm32mp157"; + #address-cells = <1>; + + images { + + copro { + description = "M4 copro"; + data = /incbin/("rproc-m4-fw.elf"); + type = "copro"; + arch = "arm"; + compression = "none"; + load = <0xC0800000>; + hash-1 { + algo = "sha1"; + }; + }; + + kernel { + description = "Linux kernel"; + data = /incbin/("zImage"); + type = "kernel"; + arch = "arm"; + os = "linux"; + compression = "none"; + load = <0xC0008000>; + entry = <0xC0008000>; + hash-1 { + algo = "sha1"; + }; + }; + + fdt-dk2 { + description = "FDT dk2"; + data = /incbin/("stm32mp157c-dk2.dtb"); + type = "flat_dt"; + arch = "arm"; + compression = "none"; + hash-1 { + algo = "sha1"; + }; + }; + + fdt-ev1 { + description = "FDT ev1"; + data = /incbin/("stm32mp157c-ev1.dtb"); + type = "flat_dt"; + arch = "arm"; + compression = "none"; + hash-1 { + algo = "sha1"; + }; + }; + }; + + configurations { + default = "dk2-m4"; + + dk2-m4 { + description = "dk2-m4"; + loadables = "copro"; + kernel = "kernel"; + fdt = "fdt-dk2"; + hash-1 { + algo = "sha1"; + }; + }; + + dk2 { + description = "dk2"; + kernel = "kernel"; + fdt = "fdt-dk2"; + hash-1 { + algo = "sha1"; + }; + }; + + ev1-m4 { + description = "ev1-m4"; + loadables = "copro"; + kernel = "kernel"; + fdt = "fdt-ev1"; + hash-1 { + algo = "sha1"; + }; + }; + + ev1 { + description = "ev1"; + kernel = "kernel"; + fdt = "fdt-ev1"; + hash-1 { + algo = "sha1"; + }; + }; + }; +}; diff --git a/board/st/stm32mp1/fit_kernel_dtb.its b/board/st/stm32mp1/fit_kernel_dtb.its new file mode 100644 index 0000000000..18d03ebf3c --- /dev/null +++ b/board/st/stm32mp1/fit_kernel_dtb.its @@ -0,0 +1,82 @@ +/* + * Compilation: + * mkimage -f fit_kernel_dtb.its fit_kernel_dtb.itb + * + * Files in linux build dir: + * - arch/arm/boot/zImage + * - arch/arm/boot/dts/stm32mp157c-dk2.dtb + * - arch/arm/boot/dts/stm32mp157c-ev1.dtb + * + * load mmc 0:4 $kernel_addr_r fit_kernel_dtb.itb + * bootm $kernel_addr_r + * bootm $kernel_addr_r#dk2 + * bootm $kernel_addr_r#ev1 + * + * or use extlinux.conf in this directory + */ + +/dts-v1/; +/ { + description = "U-Boot fitImage for stm32mp157"; + #address-cells = <1>; + + images { + kernel { + description = "Linux kernel"; + data = /incbin/("zImage"); + type = "kernel"; + arch = "arm"; + os = "linux"; + compression = "none"; + load = <0xC0008000>; + entry = <0xC0008000>; + hash-1 { + algo = "sha1"; + }; + }; + + fdt-dk2 { + description = "FDT dk2"; + data = /incbin/("stm32mp157c-dk2.dtb"); + type = "flat_dt"; + arch = "arm"; + compression = "none"; + hash-1 { + algo = "sha1"; + }; + }; + + fdt-ev1 { + description = "FDT ev1"; + data = /incbin/("stm32mp157c-ev1.dtb"); + type = "flat_dt"; + arch = "arm"; + compression = "none"; + hash-1 { + algo = "sha1"; + }; + }; + }; + + configurations { + default = "dk2"; + + dk2 { + description = "dk2"; + kernel = "kernel"; + fdt = "fdt-dk2"; + hash-1 { + algo = "sha1"; + }; + }; + + ev1 { + description = "ev1"; + kernel = "kernel"; + fdt = "fdt-ev1"; + hash-1 { + algo = "sha1"; + }; + }; + }; +}; diff --git a/board/st/stm32mp1/spl.c b/board/st/stm32mp1/spl.c index e19be0f770..e65ff288ea 100644 --- a/board/st/stm32mp1/spl.c +++ b/board/st/stm32mp1/spl.c @@ -27,5 +27,19 @@ void spl_board_init(void) STPMIC1_BUCKS_MRST_CR, STPMIC1_MRST_BUCK(STPMIC1_BUCK3), STPMIC1_MRST_BUCK(STPMIC1_BUCK3)); + + /* Check if debug is enabled to program PMIC according to the bit */ + if ((readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_DEBUG_ON) && !ret) { + printf("Keep debug unit ON\n"); + + pmic_clrsetbits(dev, STPMIC1_BUCKS_MRST_CR, + STPMIC1_MRST_BUCK_DEBUG, + STPMIC1_MRST_BUCK_DEBUG); + + if (STPMIC1_MRST_LDO_DEBUG) + pmic_clrsetbits(dev, STPMIC1_LDOS_MRST_CR, + STPMIC1_MRST_LDO_DEBUG, + STPMIC1_MRST_LDO_DEBUG); + } #endif } diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 279c7b7797..fc14ad375c 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -5,8 +5,8 @@ #include <common.h> #include <adc.h> #include <bootm.h> -#include <config.h> #include <clk.h> +#include <config.h> #include <dm.h> #include <env.h> #include <env_internal.h> @@ -18,9 +18,11 @@ #include <mtd.h> #include <mtd_node.h> #include <phy.h> +#include <remoteproc.h> #include <reset.h> #include <syscon.h> #include <usb.h> +#include <watchdog.h> #include <asm/io.h> #include <asm/gpio.h> #include <asm/arch/stm32.h> @@ -102,7 +104,7 @@ int checkboard(void) if (!ret) ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD), &otp, sizeof(otp)); - if (!ret && otp) { + if (ret > 0 && otp) { printf("Board: MB%04x Var%d Rev.%c-%02d\n", otp >> 16, (otp >> 12) & 0xF, @@ -232,6 +234,7 @@ int g_dnl_board_usb_cable_connected(void) } #endif /* CONFIG_USB_GADGET */ +#ifdef CONFIG_LED static int get_led(struct udevice **dev, char *led_string) { char *led_name; @@ -264,12 +267,42 @@ static int setup_led(enum led_state_t cmd) ret = led_set_state(dev, cmd); return ret; } +#endif + +static void __maybe_unused led_error_blink(u32 nb_blink) +{ +#ifdef CONFIG_LED + int ret; + struct udevice *led; + u32 i; +#endif + + if (!nb_blink) + return; + +#ifdef CONFIG_LED + ret = get_led(&led, "u-boot,error-led"); + if (!ret) { + /* make u-boot,error-led blinking */ + /* if U32_MAX and 125ms interval, for 17.02 years */ + for (i = 0; i < 2 * nb_blink; i++) { + led_set_state(led, LEDST_TOGGLE); + mdelay(125); + WATCHDOG_RESET(); + } + } +#endif + + /* infinite: the boot process must be stopped */ + if (nb_blink == U32_MAX) + hang(); +} +#ifdef CONFIG_ADC static int board_check_usb_power(void) { struct ofnode_phandle_args adc_args; struct udevice *adc; - struct udevice *led; ofnode node; unsigned int raw; int max_uV = 0; @@ -395,23 +428,11 @@ static int board_check_usb_power(void) pr_err("****************************************************\n\n"); } - ret = get_led(&led, "u-boot,error-led"); - if (ret) { - /* in unattached case, the boot process must be stopped */ - if (nb_blink == U32_MAX) - hang(); - return ret; - } - - /* make u-boot,error-led blinking */ - for (i = 0; i < nb_blink * 2; i++) { - led_set_state(led, LEDST_TOGGLE); - mdelay(125); - } - led_set_state(led, LEDST_ON); + led_error_blink(nb_blink); return 0; } +#endif /* CONFIG_ADC */ static void sysconf_init(void) { @@ -454,7 +475,9 @@ static void sysconf_init(void) * => U-Boot set the register only if VDD < 2.7V (in DT) * but this value need to be consistent with board design */ - ret = syscon_get_by_driver_data(STM32MP_SYSCON_PWR, &pwr_dev); + ret = uclass_get_device_by_driver(UCLASS_PMIC, + DM_GET_DRIVER(stm32mp_pwr_pmic), + &pwr_dev); if (!ret) { ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(stm32mp_bsec), @@ -465,11 +488,11 @@ static void sysconf_init(void) } ret = misc_read(dev, STM32_BSEC_SHADOW(18), &otp, 4); - if (!ret) + if (ret > 0) otp = otp & BIT(13); - /* get VDD = pwr-supply */ - ret = device_get_supply_regulator(pwr_dev, "pwr-supply", + /* get VDD = vdd-supply */ + ret = device_get_supply_regulator(pwr_dev, "vdd-supply", &pwr_reg); /* check if VDD is Low Voltage */ @@ -505,6 +528,73 @@ static void sysconf_init(void) #endif } +#ifdef CONFIG_DM_REGULATOR +/* Fix to make I2C1 usable on DK2 for touchscreen usage in kernel */ +static int dk2_i2c1_fix(void) +{ + ofnode node; + struct gpio_desc hdmi, audio; + int ret = 0; + + node = ofnode_path("/soc/i2c@40012000/hdmi-transmitter@39"); + if (!ofnode_valid(node)) { + pr_debug("%s: no hdmi-transmitter@39 ?\n", __func__); + return -ENOENT; + } + + if (gpio_request_by_name_nodev(node, "reset-gpios", 0, + &hdmi, GPIOD_IS_OUT)) { + pr_debug("%s: could not find reset-gpios\n", + __func__); + return -ENOENT; + } + + node = ofnode_path("/soc/i2c@40012000/cs42l51@4a"); + if (!ofnode_valid(node)) { + pr_debug("%s: no cs42l51@4a ?\n", __func__); + return -ENOENT; + } + + if (gpio_request_by_name_nodev(node, "reset-gpios", 0, + &audio, GPIOD_IS_OUT)) { + pr_debug("%s: could not find reset-gpios\n", + __func__); + return -ENOENT; + } + + /* before power up, insure that HDMI and AUDIO IC is under reset */ + ret = dm_gpio_set_value(&hdmi, 1); + if (ret) { + pr_err("%s: can't set_value for hdmi_nrst gpio", __func__); + goto error; + } + ret = dm_gpio_set_value(&audio, 1); + if (ret) { + pr_err("%s: can't set_value for audio_nrst gpio", __func__); + goto error; + } + + /* power-up audio IC */ + regulator_autoset_by_name("v1v8_audio", NULL); + + /* power-up HDMI IC */ + regulator_autoset_by_name("v1v2_hdmi", NULL); + regulator_autoset_by_name("v3v3_hdmi", NULL); + +error: + return ret; +} + +static bool board_is_dk2(void) +{ + if (CONFIG_IS_ENABLED(TARGET_STM32MP157C_DK2) && + of_machine_is_compatible("st,stm32mp157c-dk2")) + return true; + + return false; +} +#endif + /* board dependent setup after realloc */ int board_init(void) { @@ -523,12 +613,15 @@ int board_init(void) board_key_check(); #ifdef CONFIG_DM_REGULATOR + if (board_is_dk2()) + dk2_i2c1_fix(); + regulators_enable_boot_on(_DEBUG); #endif sysconf_init(); - if (IS_ENABLED(CONFIG_LED)) + if (CONFIG_IS_ENABLED(CONFIG_LED)) led_default_state(); return 0; @@ -536,9 +629,14 @@ int board_init(void) int board_late_init(void) { + char *boot_device; #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG const void *fdt_compat; int fdt_compat_len; + int ret; + u32 otp; + struct udevice *dev; + char buf[10]; fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible", &fdt_compat_len); @@ -548,21 +646,44 @@ int board_late_init(void) else env_set("board_name", fdt_compat + 3); } + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(stm32mp_bsec), + &dev); + + if (!ret) + ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD), + &otp, sizeof(otp)); + if (!ret && otp) { + snprintf(buf, sizeof(buf), "0x%04x", otp >> 16); + env_set("board_id", buf); + + snprintf(buf, sizeof(buf), "0x%04x", + ((otp >> 8) & 0xF) - 1 + 0xA); + env_set("board_rev", buf); + } #endif +#ifdef CONFIG_ADC /* for DK1/DK2 boards */ board_check_usb_power(); +#endif /* CONFIG_ADC */ + + /* Check the boot-source to disable bootdelay */ + boot_device = env_get("boot_device"); + if (!strcmp(boot_device, "serial") || !strcmp(boot_device, "usb")) + env_set("bootdelay", "0"); return 0; } void board_quiesce_devices(void) { +#ifdef CONFIG_LED setup_led(LEDST_OFF); +#endif } /* board interface eth init */ -/* this is a weak define that we are overriding */ int board_interface_eth_init(phy_interface_t interface_type, bool eth_clk_sel_reg, bool eth_ref_clk_sel_reg) { @@ -771,3 +892,26 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } #endif + +static void board_copro_image_process(ulong fw_image, size_t fw_size) +{ + int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */ + + if (!rproc_is_initialized()) + if (rproc_init()) { + printf("Remote Processor %d initialization failed\n", + id); + return; + } + + ret = rproc_load(id, fw_image, fw_size); + printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n", + id, fw_image, fw_size, ret ? " Failed!" : " Success!"); + + if (!ret) { + rproc_start(id); + env_set("copro_state", "booted"); + } +} + +U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_COPRO, board_copro_image_process); diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c index 4113a1c6ee..47259b7149 100644 --- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c +++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c @@ -18,97 +18,10 @@ #include <asm/arch-rockchip/hardware.h> #include <asm/arch-rockchip/grf_rk3399.h> #include <asm/arch-rockchip/periph.h> +#include <asm/arch-rockchip/misc.h> #include <power/regulator.h> #include <u-boot/sha256.h> -static void setup_macaddr(void) -{ -#if CONFIG_IS_ENABLED(CMD_NET) - int ret; - const char *cpuid = env_get("cpuid#"); - u8 hash[SHA256_SUM_LEN]; - int size = sizeof(hash); - u8 mac_addr[6]; - - /* Only generate a MAC address, if none is set in the environment */ - if (env_get("ethaddr")) - return; - - if (!cpuid) { - debug("%s: could not retrieve 'cpuid#'\n", __func__); - return; - } - - ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, &size); - if (ret) { - debug("%s: failed to calculate SHA256\n", __func__); - return; - } - - /* Copy 6 bytes of the hash to base the MAC address on */ - memcpy(mac_addr, hash, 6); - - /* Make this a valid MAC address and set it */ - mac_addr[0] &= 0xfe; /* clear multicast bit */ - mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */ - eth_env_set_enetaddr("ethaddr", mac_addr); -#endif -} - -static void setup_serial(void) -{ -#if CONFIG_IS_ENABLED(ROCKCHIP_EFUSE) - const u32 cpuid_offset = 0x7; - const u32 cpuid_length = 0x10; - - struct udevice *dev; - int ret, i; - u8 cpuid[cpuid_length]; - u8 low[cpuid_length/2], high[cpuid_length/2]; - char cpuid_str[cpuid_length * 2 + 1]; - u64 serialno; - char serialno_str[17]; - - /* retrieve the device */ - ret = uclass_get_device_by_driver(UCLASS_MISC, - DM_GET_DRIVER(rockchip_efuse), &dev); - if (ret) { - debug("%s: could not find efuse device\n", __func__); - return; - } - - /* read the cpu_id range from the efuses */ - ret = misc_read(dev, cpuid_offset, &cpuid, sizeof(cpuid)); - if (ret) { - debug("%s: reading cpuid from the efuses failed\n", - __func__); - return; - } - - memset(cpuid_str, 0, sizeof(cpuid_str)); - for (i = 0; i < 16; i++) - sprintf(&cpuid_str[i * 2], "%02x", cpuid[i]); - - debug("cpuid: %s\n", cpuid_str); - - /* - * Mix the cpuid bytes using the same rules as in - * ${linux}/drivers/soc/rockchip/rockchip-cpuinfo.c - */ - for (i = 0; i < 8; i++) { - low[i] = cpuid[1 + (i << 1)]; - high[i] = cpuid[i << 1]; - } - - serialno = crc32_no_comp(0, low, 8); - serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32; - snprintf(serialno_str, sizeof(serialno_str), "%016llx", serialno); - - env_set("cpuid#", cpuid_str); - env_set("serial#", serialno_str); -#endif -} - static void setup_iodomain(void) { const u32 GRF_IO_VSEL_GPIO4CD_SHIFT = 3; @@ -198,8 +111,23 @@ static int setup_boottargets(void) int misc_init_r(void) { - setup_serial(); - setup_macaddr(); + const u32 cpuid_offset = 0x7; + const u32 cpuid_length = 0x10; + u8 cpuid[cpuid_length]; + int ret; + + ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); + if (ret) + return ret; + + ret = rockchip_cpuid_set(cpuid, cpuid_length); + if (ret) + return ret; + + ret = rockchip_setup_macaddr(); + if (ret) + return ret; + setup_iodomain(); setup_boottargets(); |