diff options
Diffstat (limited to 'board')
93 files changed, 0 insertions, 8431 deletions
diff --git a/board/Marvell/db-88f6281-bp/.gitignore b/board/Marvell/db-88f6281-bp/.gitignore deleted file mode 100644 index 775b9346b8..0000000000 --- a/board/Marvell/db-88f6281-bp/.gitignore +++ /dev/null @@ -1 +0,0 @@ -kwbimage.cfg diff --git a/board/Marvell/db-88f6281-bp/Kconfig b/board/Marvell/db-88f6281-bp/Kconfig deleted file mode 100644 index 38467399e6..0000000000 --- a/board/Marvell/db-88f6281-bp/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_DB_88F6281_BP - -config SYS_BOARD - default "db-88f6281-bp" - -config SYS_VENDOR - default "Marvell" - -config SYS_CONFIG_NAME - default "db-88f6281-bp" - -endif diff --git a/board/Marvell/db-88f6281-bp/MAINTAINERS b/board/Marvell/db-88f6281-bp/MAINTAINERS deleted file mode 100644 index acf0b051ff..0000000000 --- a/board/Marvell/db-88f6281-bp/MAINTAINERS +++ /dev/null @@ -1,10 +0,0 @@ -DB_88F6820_AMC BOARD -M: Chris Packham <judge.packham@gmail.com> -S: Maintained -F: arch/arm/dts/kirkwood-db-88f6281.dts -F: arch/arm/dts/kirkwood-db-88f6281-spi.dts -F: arch/arm/dts/kirkwood-db.dtsi -F: board/Marvell/db-88f6281-bp/ -F: include/configs/db-88f6281-bp.h -F: configs/db-88f6281-bp-nand_defconfig -F: configs/db-88f6281-bp-spi_defconfig diff --git a/board/Marvell/db-88f6281-bp/Makefile b/board/Marvell/db-88f6281-bp/Makefile deleted file mode 100644 index 003e9f66d1..0000000000 --- a/board/Marvell/db-88f6281-bp/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ - -obj-y := db-88f6281-bp.o -extra-y := kwbimage.cfg - -quiet_cmd_sed = SED $@ - cmd_sed = sed $(SEDFLAGS_$(@F)) $< >$(dir $@)$(@F) - -SEDFLAGS_kwbimage.cfg = -e "s/^\#@BOOT_FROM.*/BOOT_FROM $(if $(CONFIG_CMD_NAND),nand,spi)/" -$(obj)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \ - include/config/auto.conf - $(call if_changed,sed) diff --git a/board/Marvell/db-88f6281-bp/db-88f6281-bp.c b/board/Marvell/db-88f6281-bp/db-88f6281-bp.c deleted file mode 100644 index 62027bd638..0000000000 --- a/board/Marvell/db-88f6281-bp/db-88f6281-bp.c +++ /dev/null @@ -1,106 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ - -#include <common.h> -#include <init.h> -#include <net.h> -#include <linux/bitops.h> -#include <linux/io.h> -#include <miiphy.h> -#include <netdev.h> -#include <asm/arch/cpu.h> -#include <asm/arch/soc.h> -#include <asm/arch/mpp.h> -#include <asm/arch/gpio.h> - -#define DB_88F6281_OE_LOW ~(BIT(7)) -#define DB_88F6281_OE_HIGH ~(BIT(15) | BIT(14) | BIT(13) | BIT(4)) -#define DB_88F6281_OE_VAL_LOW BIT(7) -#define DB_88F6281_OE_VAL_HIGH 0 - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - mvebu_config_gpio(DB_88F6281_OE_VAL_LOW, - DB_88F6281_OE_VAL_HIGH, - DB_88F6281_OE_LOW, DB_88F6281_OE_HIGH); - - /* Multi-Purpose Pins Functionality configuration */ - static const u32 kwmpp_config[] = { -#ifdef CONFIG_CMD_NAND - MPP0_NF_IO2, - MPP1_NF_IO3, - MPP2_NF_IO4, - MPP3_NF_IO5, -#else - MPP0_SPI_SCn, - MPP1_SPI_MOSI, - MPP2_SPI_SCK, - MPP3_SPI_MISO, -#endif - MPP4_NF_IO6, - MPP5_NF_IO7, - MPP6_SYSRST_OUTn, - MPP7_GPO, - MPP8_TW_SDA, - MPP9_TW_SCK, - MPP10_UART0_TXD, - MPP11_UART0_RXD, - MPP12_SD_CLK, - MPP13_SD_CMD, - MPP14_SD_D0, - MPP15_SD_D1, - MPP16_SD_D2, - MPP17_SD_D3, - MPP18_NF_IO0, - MPP19_NF_IO1, - MPP20_SATA1_ACTn, - MPP21_SATA0_ACTn, - MPP22_GPIO, - MPP23_GPIO, - MPP24_GPIO, - MPP25_GPIO, - MPP26_GPIO, - MPP27_GPIO, - MPP28_GPIO, - MPP29_GPIO, - MPP30_GPIO, - MPP31_GPIO, - MPP32_GPIO, - MPP33_GPIO, - MPP34_GPIO, - MPP35_GPIO, - MPP36_GPIO, - MPP37_GPIO, - MPP38_GPIO, - MPP39_GPIO, - MPP40_GPIO, - MPP41_GPIO, - MPP42_GPIO, - MPP43_GPIO, - MPP44_GPIO, - MPP45_GPIO, - MPP46_GPIO, - MPP47_GPIO, - MPP48_GPIO, - MPP49_GPIO, - 0 - }; - kirkwood_mpp_conf(kwmpp_config, NULL); - - return 0; -} - -int board_init(void) -{ - gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; - - return 0; -} - -#ifdef CONFIG_RESET_PHY_R -/* automatically defined by kirkwood config.h */ -void reset_phy(void) -{ -} -#endif diff --git a/board/Marvell/db-88f6281-bp/kwbimage.cfg.in b/board/Marvell/db-88f6281-bp/kwbimage.cfg.in deleted file mode 100644 index 05f8b275f6..0000000000 --- a/board/Marvell/db-88f6281-bp/kwbimage.cfg.in +++ /dev/null @@ -1,36 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ - -# Boot Media configurations -#@BOOT_FROM - -DATA 0xd00100e0 0x1b1b1b9b -DATA 0xd0020134 0xbbbbbbbb -DATA 0xd0020138 0x00bbbbbb -DATA 0xd0020154 0x00000200 -DATA 0xd002014c 0x00001c00 -DATA 0xd0020148 0x00000001 - -DATA 0xd0001400 0x43000c30 -DATA 0xd0001404 0x39543000 -DATA 0xd0001408 0x22125451 -DATA 0xd000140c 0x00000833 -DATA 0xd0001410 0x000000cc -DATA 0xd0001414 0x00000000 -DATA 0xd0001418 0x00000000 -DATA 0xd000141c 0x00000c52 -DATA 0xd0001420 0x00000044 -DATA 0xd0001424 0x0000f1ff -DATA 0xd0001428 0x00085520 -DATA 0xd000147c 0x00008552 -DATA 0xd0001504 0x0ffffff1 -DATA 0xd0001508 0x10000000 -DATA 0xd000150c 0x0ffffff5 -DATA 0xd0001514 0x00000000 -DATA 0xd000151c 0x00000000 -DATA 0xd0001494 0x84210000 -DATA 0xd0001498 0x00000000 -DATA 0xd000149c 0x0000f40f -DATA 0xd0001480 0x00000001 - -# End of Header extension -DATA 0x0 0x0 diff --git a/board/bluegiga/apx4devkit/Kconfig b/board/bluegiga/apx4devkit/Kconfig deleted file mode 100644 index f327fa15cf..0000000000 --- a/board/bluegiga/apx4devkit/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_APX4DEVKIT - -config SYS_BOARD - default "apx4devkit" - -config SYS_VENDOR - default "bluegiga" - -config SYS_SOC - default "mxs" - -config SYS_CONFIG_NAME - default "apx4devkit" - -endif diff --git a/board/bluegiga/apx4devkit/MAINTAINERS b/board/bluegiga/apx4devkit/MAINTAINERS deleted file mode 100644 index 286e9e9f06..0000000000 --- a/board/bluegiga/apx4devkit/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -APX4DEVKIT BOARD -M: Lauri Hintsala <lauri.hintsala@bluegiga.com> -S: Maintained -F: board/bluegiga/apx4devkit/ -F: include/configs/apx4devkit.h -F: configs/apx4devkit_defconfig diff --git a/board/bluegiga/apx4devkit/Makefile b/board/bluegiga/apx4devkit/Makefile deleted file mode 100644 index 039d62dda2..0000000000 --- a/board/bluegiga/apx4devkit/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -ifndef CONFIG_SPL_BUILD -obj-y := apx4devkit.o -else -obj-y := spl_boot.o -endif diff --git a/board/bluegiga/apx4devkit/apx4devkit.c b/board/bluegiga/apx4devkit/apx4devkit.c deleted file mode 100644 index 739f71f5c4..0000000000 --- a/board/bluegiga/apx4devkit/apx4devkit.c +++ /dev/null @@ -1,142 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Bluegiga APX4 Development Kit - * - * Copyright (C) 2012 Bluegiga Technologies Oy - * - * Authors: - * Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com> - * Lauri Hintsala <lauri.hintsala@bluegiga.com> - * - * Based on m28evk.c: - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - */ - -#include <common.h> -#include <init.h> -#include <net.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/setup.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux-mx28.h> -#include <asm/arch/clock.h> -#include <asm/arch/sys_proto.h> -#include <env.h> -#include <linux/mii.h> -#include <miiphy.h> -#include <netdev.h> -#include <errno.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* Functions */ -int board_early_init_f(void) -{ - /* IO0 clock at 480MHz */ - mxs_set_ioclk(MXC_IOCLK0, 480000); - /* IO1 clock at 480MHz */ - mxs_set_ioclk(MXC_IOCLK1, 480000); - - /* SSP0 clock at 96MHz */ - mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); - - return 0; -} - -int dram_init(void) -{ - return mxs_dram_init(); -} - -int board_init(void) -{ - /* Adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -#ifdef CONFIG_CMD_MMC -int board_mmc_init(struct bd_info *bis) -{ - return mxsmmc_initialize(bis, 0, NULL, NULL); -} -#endif - - -#ifdef CONFIG_CMD_NET - -#define MII_PHY_CTRL2 0x1f -int fecmxc_mii_postcall(int phy) -{ - /* change PHY RMII clock to 50MHz */ - miiphy_write("FEC", 0, MII_PHY_CTRL2, 0x8180); - - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - int ret; - struct eth_device *dev; - - ret = cpu_eth_init(bis); - if (ret) { - printf("FEC MXS: Unable to init FEC clocks\n"); - return ret; - } - - ret = fecmxc_initialize(bis); - if (ret) { - printf("FEC MXS: Unable to init FEC\n"); - return ret; - } - - dev = eth_get_dev_by_name("FEC"); - if (!dev) { - printf("FEC MXS: Unable to get FEC device entry\n"); - return -EINVAL; - } - - ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); - if (ret) { - printf("FEC MXS: Unable to register FEC MII postcall\n"); - return ret; - } - - return ret; -} -#endif - -#ifdef CONFIG_SERIAL_TAG -#define MXS_OCOTP_MAX_TIMEOUT 1000000 -void get_board_serial(struct tag_serialnr *serialnr) -{ - struct mxs_ocotp_regs *ocotp_regs = - (struct mxs_ocotp_regs *)MXS_OCOTP_BASE; - - serialnr->high = 0; - serialnr->low = 0; - - writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set); - - if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY, - MXS_OCOTP_MAX_TIMEOUT)) { - printf("MXS: Can't get serial number from OCOTP\n"); - return; - } - - serialnr->low = readl(&ocotp_regs->hw_ocotp_cust3); -} -#endif - -#ifdef CONFIG_REVISION_TAG -u32 get_board_rev(void) -{ - if (env_get("revision#") != NULL) - return simple_strtoul(env_get("revision#"), NULL, 10); - return 0; -} -#endif diff --git a/board/bluegiga/apx4devkit/spl_boot.c b/board/bluegiga/apx4devkit/spl_boot.c deleted file mode 100644 index e5d5c4637b..0000000000 --- a/board/bluegiga/apx4devkit/spl_boot.c +++ /dev/null @@ -1,152 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Bluegiga APX4 Development Kit - * - * Copyright (C) 2012 Bluegiga Technologies Oy - * - * Authors: - * Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com> - * Lauri Hintsala <lauri.hintsala@bluegiga.com> - * - * Based on spl_boot.c: - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - */ - -#include <common.h> -#include <config.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch/iomux-mx28.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> - -#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) -#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) - -const iomux_cfg_t iomux_setup[] = { - /* DUART */ - MX28_PAD_PWM0__DUART_RX, - MX28_PAD_PWM1__DUART_TX, - - /* LED */ - MX28_PAD_PWM3__GPIO_3_28, - - /* MMC0 */ - MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | - (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_NOPULL), - MX28_PAD_SSP0_SCK__SSP0_SCK | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - - /* GPMI NAND */ - MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_RDN__GPMI_RDN | - (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), - MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI, - - /* FEC0 */ - MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, - MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, - MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, - - /* I2C */ - MX28_PAD_I2C0_SCL__I2C0_SCL, - MX28_PAD_I2C0_SDA__I2C0_SDA, - - /* EMI */ - MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, - MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, - MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, - - MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, - MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, - MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, - MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, - MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, - MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, -}; - -void board_init_ll(const uint32_t arg, const uint32_t *resptr) -{ - mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); - - /* switch LED on */ - gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0); -} - -void mxs_adjust_memory_params(uint32_t *dram_vals) -{ - /* - * All address lines are routed from CPU to memory chip. - * ADDR_PINS field is set to zero. - */ - dram_vals[0x74 >> 2] = 0x0f02000a; - - /* Used memory has 4 banks. EIGHT_BANK_MODE bit is disabled. */ - dram_vals[0x7c >> 2] = 0x00000101; -} diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 04e04a6358..114b7ba8f9 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -48,7 +48,6 @@ obj-$(CONFIG_TARGET_MPC8548CDS) += cds_pci_ft.o obj-$(CONFIG_TARGET_MPC8555CDS) += cds_pci_ft.o obj-$(CONFIG_TARGET_MPC8536DS) += ics307_clk.o -obj-$(CONFIG_TARGET_MPC8572DS) += ics307_clk.o obj-$(CONFIG_TARGET_P1022DS) += ics307_clk.o obj-$(CONFIG_P2020DS) += ics307_clk.o obj-$(CONFIG_TARGET_P3041DS) += ics307_clk.o diff --git a/board/freescale/common/pixis.h b/board/freescale/common/pixis.h index 40053c45bb..f19e85cb1c 100644 --- a/board/freescale/common/pixis.h +++ b/board/freescale/common/pixis.h @@ -44,117 +44,6 @@ typedef struct pixis { u8 vtempmax[2]; u8 res2[4]; } __attribute__ ((packed)) pixis_t; - -#elif defined(CONFIG_TARGET_MPC8544DS) -typedef struct pixis { - u8 id; - u8 ver; - u8 pver; - u8 csr; - u8 rst; - u8 pwr; - u8 aux1; - u8 spd; - u8 res[8]; - u8 vctl; - u8 vstat; - u8 vcfgen0; - u8 vcfgen1; - u8 vcore0; - u8 res1; - u8 vboot; - u8 vspeed[2]; - u8 vclkh; - u8 vclkl; - u8 watch; - u8 led; - u8 vspeed2; - u8 res2[34]; -} __attribute__ ((packed)) pixis_t; - -#elif defined(CONFIG_TARGET_MPC8572DS) -typedef struct pixis { - u8 id; - u8 ver; - u8 pver; - u8 csr; - u8 rst; - u8 pwr1; - u8 aux1; - u8 spd; - u8 aux2; - u8 res[7]; - u8 vctl; - u8 vstat; - u8 vcfgen0; - u8 vcfgen1; - u8 vcore0; - u8 res1; - u8 vboot; - u8 vspeed[3]; - u8 res2[2]; - u8 sclk[3]; - u8 dclk[3]; - u8 res3[2]; - u8 watch; - u8 led; - u8 res4[25]; -} __attribute__ ((packed)) pixis_t; - -#elif defined(CONFIG_TARGET_MPC8610HPCD) -typedef struct pixis { - u8 id; - u8 ver; /* also called arch */ - u8 pver; - u8 csr; - u8 rst; - u8 pwr; - u8 aux; - u8 spd; - u8 brdcfg0; - u8 brdcfg1; - u8 res[4]; - u8 led; - u8 serno; - u8 vctl; - u8 vstat; - u8 vcfgen0; - u8 vcfgen1; - u8 vcore0; - u8 res1; - u8 vboot; - u8 vspeed[2]; - u8 res2; - u8 sclk[3]; - u8 res3; - u8 watch; - u8 res4[33]; -} __attribute__ ((packed)) pixis_t; - -#elif defined(CONFIG_TARGET_MPC8641HPCN) -typedef struct pixis { - u8 id; - u8 ver; - u8 pver; - u8 csr; - u8 rst; - u8 pwr; - u8 aux; - u8 spd; - u8 res[8]; - u8 vctl; - u8 vstat; - u8 vcfgen0; - u8 vcfgen1; - u8 vcore0; - u8 res1; - u8 vboot; - u8 vspeed[2]; - u8 vclkh; - u8 vclkl; - u8 watch; - u8 res3[36]; -} __attribute__ ((packed)) pixis_t; #else #error Need to define pixis_t for this board #endif diff --git a/board/freescale/ls2080a/Kconfig b/board/freescale/ls2080a/Kconfig deleted file mode 100644 index b5033511b5..0000000000 --- a/board/freescale/ls2080a/Kconfig +++ /dev/null @@ -1,35 +0,0 @@ -if TARGET_LS2080A_EMU - -config SYS_BOARD - default "ls2080a" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "fsl-layerscape" - -config SYS_CONFIG_NAME - default "ls2080a_emu" - -source "board/freescale/common/Kconfig" - -endif - -if TARGET_LS2080A_SIMU - -config SYS_BOARD - default "ls2080a" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "fsl-layerscape" - -config SYS_CONFIG_NAME - default "ls2080a_simu" - -source "board/freescale/common/Kconfig" - -endif diff --git a/board/freescale/ls2080a/MAINTAINERS b/board/freescale/ls2080a/MAINTAINERS deleted file mode 100644 index e0e4e3f83e..0000000000 --- a/board/freescale/ls2080a/MAINTAINERS +++ /dev/null @@ -1,9 +0,0 @@ -LS2080A BOARD -M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> -M: Priyanka Jain <priyanka.jain@nxp.com> -S: Maintained -F: board/freescale/ls2080a/ -F: include/configs/ls2080a_emu.h -F: configs/ls2080a_emu_defconfig -F: include/configs/ls2080a_simu.h -F: configs/ls2080a_simu_defconfig diff --git a/board/freescale/ls2080a/Makefile b/board/freescale/ls2080a/Makefile deleted file mode 100644 index 87e26d9770..0000000000 --- a/board/freescale/ls2080a/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2014-15 Freescale Semiconductor - -obj-y += ls2080a.o -obj-y += ddr.o diff --git a/board/freescale/ls2080a/README b/board/freescale/ls2080a/README deleted file mode 100644 index 646cc02693..0000000000 --- a/board/freescale/ls2080a/README +++ /dev/null @@ -1,27 +0,0 @@ -Freescale ls2080a_emu - -This is a emulator target with limited peripherals. - -Memory map from core's view - -0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom -0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR -0x00_1800_0000 .. 0x00_181F_FFFF OCRAM -0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1 -0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1 -0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2 -0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2 - -Other addresses are either reserved, or not used directly by U-Boot. -This list should be updated when more addresses are used. - -Booting Linux flavors which do not support 48-bit VA (< Linux 3.18) -------------------------------------------------------------------- -One needs to use appropriate bootargs to boot Linux flavors which do -not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown -below: - -=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram - earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m - hugepages=16 mem=2048M' - diff --git a/board/freescale/ls2080a/ddr.c b/board/freescale/ls2080a/ddr.c deleted file mode 100644 index 229fc9cc30..0000000000 --- a/board/freescale/ls2080a/ddr.c +++ /dev/null @@ -1,171 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> -#include <log.h> -#include <asm/arch/soc.h> -#include <asm/arch/clock.h> -#include "ddr.h" - -DECLARE_GLOBAL_DATA_PTR; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - - if (ctrl_num > 3) { - printf("Not supported controller number %d\n", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - /* - * we use identical timing for all slots. If needed, change the code - * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; - */ - if (popts->registered_dimm_en) - pbsp = rdimms[ctrl_num]; - else - pbsp = udimms[ctrl_num]; - - - /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks && - (pdimm->rank_density >> 30) >= pbsp->rank_gb) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found for data rate %lu MT/s\n" - "Trying to use the highest speed (%u) parameters\n", - ddr_freq, pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - } else { - panic("DIMM is not supported by this board"); - } -found: - debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" - "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n", - pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, - pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, - pbsp->wrlvl_ctl_3); -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR - if (ctrl_num == CONFIG_DP_DDR_CTRL) { - /* force DDR bus width to 32 bits */ - popts->data_bus_width = 1; - popts->otf_burst_chop_en = 0; - popts->burst_length = DDR_BL8; - popts->bstopre = 0; /* enable auto precharge */ - } -#endif - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 1; - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - - /* - * Rtt and Rtt_WR override - */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - -#ifdef CONFIG_SYS_FSL_DDR4 - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | - DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ -#else - /* DHC_EN =1, ODT = 75 Ohm */ - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); -#endif -} - -#ifdef CONFIG_SYS_DDR_RAW_TIMING -dimm_params_t ddr_raw_timing = { - .n_ranks = 2, - .rank_density = 1073741824u, - .capacity = 2147483648, - .primary_sdram_width = 64, - .ec_sdram_width = 0, - .registered_dimm = 0, - .mirrored_dimm = 0, - .n_row_addr = 14, - .n_col_addr = 10, - .n_banks_per_sdram_device = 8, - .edc_config = 0, - .burst_lengths_bitmask = 0x0c, - - .tckmin_x_ps = 937, - .caslat_x = 0x6FC << 4, /* 14,13,11,10,9,8,7,6 */ - .taa_ps = 13090, - .twr_ps = 15000, - .trcd_ps = 13090, - .trrd_ps = 5000, - .trp_ps = 13090, - .tras_ps = 33000, - .trc_ps = 46090, - .trfc_ps = 160000, - .twtr_ps = 7500, - .trtp_ps = 7500, - .refresh_rate_ps = 7800000, - .tfaw_ps = 25000, -}; - -int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, - unsigned int controller_number, - unsigned int dimm_number) -{ - const char dimm_model[] = "Fixed DDR on board"; - - if (((controller_number == 0) && (dimm_number == 0)) || - ((controller_number == 1) && (dimm_number == 0))) { - memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); - memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); - } - - return 0; -} -#endif - -int fsl_initdram(void) -{ - puts("Initializing DDR...."); - - puts("using SPD\n"); - gd->ram_size = fsl_ddr_sdram(); - - return 0; -} diff --git a/board/freescale/ls2080a/ddr.h b/board/freescale/ls2080a/ddr.h deleted file mode 100644 index d21b926558..0000000000 --- a/board/freescale/ls2080a/ddr.h +++ /dev/null @@ -1,85 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __DDR_H__ -#define __DDR_H__ -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 rank_gb; - u32 clk_adjust; - u32 wrlvl_start; - u32 wrlvl_ctl_2; - u32 wrlvl_ctl_3; -}; - -/* - * These tables contain all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ - -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ - {2, 2140, 0, 4, 4, 0x0, 0x0}, - {1, 2140, 0, 4, 4, 0x0, 0x0}, - {} -}; - -/* DP-DDR DIMM */ -static const struct board_specific_parameters udimm2[] = { - /* - * memory controller 2 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ - {2, 2140, 0, 4, 4, 0x0, 0x0}, - {1, 2140, 0, 4, 4, 0x0, 0x0}, - {} -}; - -static const struct board_specific_parameters rdimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ - {4, 2140, 0, 5, 4, 0x0, 0x0}, - {2, 2140, 0, 5, 4, 0x0, 0x0}, - {1, 2140, 0, 4, 4, 0x0, 0x0}, - {} -}; - -/* DP-DDR DIMM */ -static const struct board_specific_parameters rdimm2[] = { - /* - * memory controller 2 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ - {4, 2140, 0, 5, 4, 0x0, 0x0}, - {2, 2140, 0, 5, 4, 0x0, 0x0}, - {1, 2140, 0, 4, 4, 0x0, 0x0}, - {} -}; - -static const struct board_specific_parameters *udimms[] = { - udimm0, - udimm0, - udimm2, -}; - -static const struct board_specific_parameters *rdimms[] = { - rdimm0, - rdimm0, - rdimm2, -}; - - -#endif diff --git a/board/freescale/ls2080a/ls2080a.c b/board/freescale/ls2080a/ls2080a.c deleted file mode 100644 index 62da2a7af1..0000000000 --- a/board/freescale/ls2080a/ls2080a.c +++ /dev/null @@ -1,147 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor - */ -#include <common.h> -#include <init.h> -#include <malloc.h> -#include <errno.h> -#include <net.h> -#include <netdev.h> -#include <fsl_ifc.h> -#include <fsl_ddr.h> -#include <asm/io.h> -#include <fdt_support.h> -#include <linux/libfdt.h> -#include <fsl-mc/fsl_mc.h> -#include <env_internal.h> -#include <asm/arch/soc.h> - -DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - init_final_memctl_regs(); - -#ifdef CONFIG_ENV_IS_NOWHERE - gd->env_addr = (ulong)&default_environment[0]; -#endif - - return 0; -} - -int board_early_init_f(void) -{ - fsl_lsch3_early_init_f(); - return 0; -} - -void detail_board_ddr_info(void) -{ - puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); - print_ddr_info(0); -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR - if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { - puts("\nDP-DDR "); - print_size(gd->bd->bi_dram[2].size, ""); - print_ddr_info(CONFIG_DP_DDR_CTRL); - } -#endif -} - -int board_eth_init(struct bd_info *bis) -{ - int error = 0; - -#ifdef CONFIG_SMC91111 - error = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) - error = cpu_eth_init(bis); -#endif - return error; -} - -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) -void fdt_fixup_board_enet(void *fdt) -{ - int offset; - - offset = fdt_path_offset(fdt, "/soc/fsl-mc"); - - /* - * TODO: Remove this when backward compatibility - * with old DT node (/fsl-mc) is no longer needed. - */ - if (offset < 0) - offset = fdt_path_offset(fdt, "/fsl-mc"); - - if (offset < 0) { - printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", - __func__, offset); - return; - } - - if (get_mc_boot_status() == 0 && - (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) - fdt_status_okay(fdt, offset); - else - fdt_status_fail(fdt, offset); -} - -void board_quiesce_devices(void) -{ - fsl_mc_ldpaa_exit(gd->bd); -} -#endif - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, struct bd_info *bd) -{ - u64 base[CONFIG_NR_DRAM_BANKS]; - u64 size[CONFIG_NR_DRAM_BANKS]; - - ft_cpu_setup(blob, bd); - - /* fixup DT for the two GPP DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; - -#ifdef CONFIG_RESV_RAM - /* reduce size if reserved memory is within this bank */ - if (gd->arch.resv_ram >= base[0] && - gd->arch.resv_ram < base[0] + size[0]) - size[0] = gd->arch.resv_ram - base[0]; - else if (gd->arch.resv_ram >= base[1] && - gd->arch.resv_ram < base[1] + size[1]) - size[1] = gd->arch.resv_ram - base[1]; -#endif - - fdt_fixup_memory_banks(blob, base, size, 2); - - fdt_fsl_mc_fixup_iommu_map_entry(blob); - -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) - fdt_fixup_board_enet(blob); -#endif - - return 0; -} -#endif - -#if defined(CONFIG_RESET_PHY_R) -void reset_phy(void) -{ -} -#endif - -#ifdef CONFIG_TFABOOT -void *env_sf_get_env_addr(void) -{ - return (void *)(CONFIG_SYS_FSL_QSPI_BASE1 + CONFIG_ENV_OFFSET); -} -#endif diff --git a/board/freescale/mpc8544ds/Kconfig b/board/freescale/mpc8544ds/Kconfig deleted file mode 100644 index c3e25b89a0..0000000000 --- a/board/freescale/mpc8544ds/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC8544DS - -config SYS_BOARD - default "mpc8544ds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8544DS" - -endif diff --git a/board/freescale/mpc8544ds/MAINTAINERS b/board/freescale/mpc8544ds/MAINTAINERS deleted file mode 100644 index 74e7249e47..0000000000 --- a/board/freescale/mpc8544ds/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MPC8544DS BOARD -M: Priyanka Jain <priyanka.jain@nxp.com> -S: Maintained -F: board/freescale/mpc8544ds/ -F: include/configs/MPC8544DS.h -F: configs/MPC8544DS_defconfig diff --git a/board/freescale/mpc8544ds/Makefile b/board/freescale/mpc8544ds/Makefile deleted file mode 100644 index 1693ae8433..0000000000 --- a/board/freescale/mpc8544ds/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2007 Freescale Semiconductor, Inc. -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y += mpc8544ds.o -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/mpc8544ds/README b/board/freescale/mpc8544ds/README deleted file mode 100644 index b49c3c07c4..0000000000 --- a/board/freescale/mpc8544ds/README +++ /dev/null @@ -1,122 +0,0 @@ -Overview --------- -The MPC8544DS system is similar to the 85xx CDS systems such -as the MPC8548CDS due to the similar E500 core. However, it -is placed on the same board as the 8641 HPCN system. - - -Flash Banks ------------ -Like the 85xx CDS systems, the 8544 DS board has two flash banks. -They are both present on boot, but there locations can be swapped -using the dip-switch SW10, bit 2. - -However, unlike the CDS systems, but similar to the 8641 HPCN -board, a runtime reset through the FPGA can also affect a swap -on the flash bank mappings for the next reset cycle. - -Irrespective of the switch SW10[2], booting is always from the -boot bank at 0xfff8_0000. - - -Memory Map ----------- - -0xff80_0000 - 0xffbf_ffff Alternate bank 4MB -0xffc0_0000 - 0xffff_ffff Boot bank 4MB - -0xffb8_0000 Alternate image start 512KB -0xfff8_0000 Boot image start 512KB - - -Flashing Images ---------------- - -For example, to place a new image in the alternate flash bank -and then reset with that new image temporarily, use this: - - tftp 1000000 u-boot.bin.8544ds - erase ffb80000 ffbfffff - cp.b 1000000 ffb80000 80000 - pixis_reset altbank - - -To overwrite the image in the boot flash bank: - - tftp 1000000 u-boot.bin.8544ds - protect off all - erase fff80000 ffffffff - cp.b 1000000 fff80000 80000 - -Other example U-Boot image and flash manipulations examples -can be found in the README.mpc85xxcds file as well. - - -The pixis_reset command ------------------------ -A new command, "pixis_reset", is introduced to reset mpc8641hpcn board -using the FPGA sequencer. When the board restarts, it has the option -of using either the current or alternate flash bank as the boot -image, with or without the watchdog timer enabled, and finally with -or without frequency changes. - -Usage is; - - pixis_reset - pixis_reset altbank - pixis_reset altbank wd - pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> - pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> - -Examples; - - /* reset to current bank, like "reset" command */ - pixis_reset - - /* reset board but use the to alternate flash bank */ - pixis_reset altbank - - /* reset board, use alternate flash bank with watchdog timer enabled*/ - pixis_reset altbank wd - - /* reset board to alternate bank with frequency changed. - * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio - */ - pixis-reset altbank cf 40 2.5 10 - -Valid clock choices are in the 8641 Reference Manuals. - - -Using the Device Tree Source File ---------------------------------- -To create the DTB (Device Tree Binary) image file, -use a command similar to this: - - dtc -b 0 -f -I dts -O dtb mpc8544ds.dts > mpc8544ds.dtb - -Likely, that .dts file will come from here; - - linux-2.6/arch/powerpc/boot/dts/mpc8544ds.dts - -After placing the DTB file in your TFTP disk area, -you can download that dtb file using a command like: - - tftp 900000 mpc8544ds.dtb - -Burn it to flash if you want. - - -Booting Linux -------------- - -Place a linux uImage in the TFTP disk area too. - - tftp 1000000 uImage.8544 - tftp 900000 mpc8544ds.dtb - bootm 1000000 - 900000 - -Watch your ethact, netdev and bootargs U-Boot environment variables. -You may want to do something like this too: - - setenv ethact eTSEC3 - setenv netdev eth1 diff --git a/board/freescale/mpc8544ds/ddr.c b/board/freescale/mpc8544ds/ddr.c deleted file mode 100644 index c4d985347b..0000000000 --- a/board/freescale/mpc8544ds/ddr.c +++ /dev/null @@ -1,56 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2008 Freescale Semiconductor, Inc. - */ - -#include <common.h> - -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for clock adjust: - * - number of chips on bus - * - position of slot - * - DDR1 vs. DDR2? - * - ??? - * - * This needs to be determined on a board-by-board basis. - * 0110 3/4 cycle late - * 0111 7/8 cycle late - */ - popts->clk_adjust = 7; - - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 10; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; - - /* 2T timing enable */ - popts->twot_en = 1; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/freescale/mpc8544ds/law.c b/board/freescale/mpc8544ds/law.c deleted file mode 100644 index 52cec7fbb5..0000000000 --- a/board/freescale/mpc8544ds/law.c +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2008, 2010 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_LBC_NONCACHE_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c deleted file mode 100644 index 30ed708365..0000000000 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ /dev/null @@ -1,321 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2007,2009-2010 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <command.h> -#include <init.h> -#include <net.h> -#include <pci.h> -#include <asm/processor.h> -#include <asm/mmu.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_pci.h> -#include <fsl_ddr_sdram.h> -#include <asm/fsl_serdes.h> -#include <asm/io.h> -#include <miiphy.h> -#include <linux/libfdt.h> -#include <fdt_support.h> -#include <fsl_mdio.h> -#include <tsec.h> -#include <netdev.h> - -#include "../common/sgmii_riser.h" - -int checkboard (void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); - u8 vboot; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - if ((uint)&gur->porpllsr != 0xe00e0000) { - printf("immap size error %lx\n",(ulong)&gur->porpllsr); - } - printf ("Board: MPC8544DS, Sys ID: 0x%02x, " - "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", - in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), - in_8(pixis_base + PIXIS_PVER)); - - vboot = in_8(pixis_base + PIXIS_VBOOT); - if (vboot & PIXIS_VBOOT_FMAP) - printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6)); - else - puts ("Promjet\n"); - - lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ - lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ - ecm->eedr = 0xffffffff; /* Clear ecm errors */ - ecm->eeer = 0xffffffff; /* Enable ecm errors */ - - return 0; -} - -#ifdef CONFIG_PCI1 -static struct pci_controller pci1_hose; -#endif - -#ifdef CONFIG_PCIE3 -static struct pci_controller pcie3_hose; -#endif - -void pci_init_board(void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - struct fsl_pci_info pci_info; - u32 devdisr, pordevsr, io_sel; - u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; - int first_free_busno = 0; - - int pcie_ep, pcie_configured; - - devdisr = in_be32(&gur->devdisr); - pordevsr = in_be32(&gur->pordevsr); - porpllsr = in_be32(&gur->porpllsr); - io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - - debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); - - puts("\n"); - -#ifdef CONFIG_PCIE3 - pcie_configured = is_serdes_configured(PCIE3); - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ - /* contains both PCIE3 MEM & IO space */ - set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M, - LAW_TRGT_IF_PCIE_3); - SET_STD_PCIE_INFO(pci_info, 3); - pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info.regs); - - /* outbound memory */ - pci_set_region(&pcie3_hose.regions[0], - CONFIG_SYS_PCIE3_MEM_BUS2, - CONFIG_SYS_PCIE3_MEM_PHYS2, - CONFIG_SYS_PCIE3_MEM_SIZE2, - PCI_REGION_MEM); - - pcie3_hose.region_count = 1; - - printf("PCIE3: connected to ULI as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info.regs); - first_free_busno = fsl_pci_init_port(&pci_info, - &pcie3_hose, first_free_busno); - - /* - * Activate ULI1575 legacy chip by performing a fake - * memory access. Needed to make ULI RTC work. - */ - in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS); - } else { - printf("PCIE3: disabled\n"); - } - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ -#endif - -#ifdef CONFIG_PCIE1 - SET_STD_PCIE_INFO(pci_info, 1); - first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE1, &pci_info); -#else - setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */ -#endif - -#ifdef CONFIG_PCIE2 - SET_STD_PCIE_INFO(pci_info, 2); - first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE2, &pci_info); -#else - setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */ -#endif - -#ifdef CONFIG_PCI1 - pci_speed = 66666000; - pci_32 = 1; - pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; - pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; - - if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { - SET_STD_PCI_INFO(pci_info, 1); - set_next_law(pci_info.mem_phys, - law_size_bits(pci_info.mem_size), pci_info.law); - set_next_law(pci_info.io_phys, - law_size_bits(pci_info.io_size), pci_info.law); - - pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); - printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", - (pci_32) ? 32 : 64, - (pci_speed == 33333000) ? "33" : - (pci_speed == 66666000) ? "66" : "unknown", - pci_clk_sel ? "sync" : "async", - pci_agent ? "agent" : "host", - pci_arb ? "arbiter" : "external-arbiter", - pci_info.regs); - - first_free_busno = fsl_pci_init_port(&pci_info, - &pci1_hose, first_free_busno); - } else { - printf("PCI: disabled\n"); - } - - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ -#endif -} - -int last_stage_init(void) -{ - return 0; -} - - -unsigned long -get_board_sys_clk(ulong dummy) -{ - u8 i, go_bit, rd_clks; - ulong val = 0; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - go_bit = in_8(pixis_base + PIXIS_VCTL); - go_bit &= 0x01; - - rd_clks = in_8(pixis_base + PIXIS_VCFGEN0); - rd_clks &= 0x1C; - - /* - * Only if both go bit and the SCLK bit in VCFGEN0 are set - * should we be using the AUX register. Remember, we also set the - * GO bit to boot from the alternate bank on the on-board flash - */ - - if (go_bit) { - if (rd_clks == 0x1c) - i = in_8(pixis_base + PIXIS_AUX); - else - i = in_8(pixis_base + PIXIS_SPD); - } else { - i = in_8(pixis_base + PIXIS_SPD); - } - - i &= 0x07; - - switch (i) { - case 0: - val = 33333333; - break; - case 1: - val = 40000000; - break; - case 2: - val = 50000000; - break; - case 3: - val = 66666666; - break; - case 4: - val = 83000000; - break; - case 5: - val = 100000000; - break; - case 6: - val = 133333333; - break; - case 7: - val = 166666666; - break; - } - - return val; -} - - -#define MIIM_CIS8204_SLED_CON 0x1b -#define MIIM_CIS8204_SLEDCON_INIT 0x1115 -/* - * Hack to write all 4 PHYs with the LED values - */ -int board_phy_config(struct phy_device *phydev) -{ - static int do_once; - uint phyid; - struct mii_dev *bus = phydev->bus; - - if (phydev->drv->config) - phydev->drv->config(phydev); - if (do_once) - return 0; - - for (phyid = 0; phyid < 4; phyid++) - bus->write(bus, phyid, MDIO_DEVAD_NONE, MIIM_CIS8204_SLED_CON, - MIIM_CIS8204_SLEDCON_INIT); - - do_once = 1; - - return 0; -} - - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_TSEC_ENET - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[2]; - int num = 0; - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - if (is_serdes_configured(SGMII_TSEC1)) { - puts("eTSEC1 is in sgmii mode.\n"); - tsec_info[num].flags |= TSEC_SGMII; - } - num++; -#endif -#ifdef CONFIG_TSEC3 - SET_STD_TSEC_INFO(tsec_info[num], 3); - if (is_serdes_configured(SGMII_TSEC3)) { - puts("eTSEC3 is in sgmii mode.\n"); - tsec_info[num].flags |= TSEC_SGMII; - } - num++; -#endif - - if (!num) { - printf("No TSECs initialized\n"); - - return 0; - } - - if (is_serdes_configured(SGMII_TSEC1) || - is_serdes_configured(SGMII_TSEC3)) { - fsl_sgmii_riser_init(tsec_info, num); - } - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - fsl_pq_mdio_init(bis, &mdio_info); - - tsec_eth_init(bis, tsec_info, num); -#endif - return pci_eth_init(bis); -} - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - ft_cpu_setup(blob, bd); - - FT_FSL_PCI_SETUP; - -#ifdef CONFIG_FSL_SGMII_RISER - fsl_sgmii_riser_fdt_fixup(blob); -#endif - - return 0; -} -#endif diff --git a/board/freescale/mpc8544ds/tlb.c b/board/freescale/mpc8544ds/tlb.c deleted file mode 100644 index 7bd462934a..0000000000 --- a/board/freescale/mpc8544ds/tlb.c +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - /* - * TLB 0: 64M Non-cacheable, guarded - * 0xfc000000 64M Covers FLASH at 0xFE800000 and 0xFF800000 - * Out of reset this entry is only 4K. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_BOOT_BLOCK, CONFIG_SYS_BOOT_BLOCK, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_64M, 1), - /* - * TLB 1: 1G Non-cacheable, guarded - * 0x80000000 1G PCIE 8,9,a,b - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE_VIRT, CONFIG_SYS_PCIE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_1G, 1), - - /* - * TLB 2: 256M Non-cacheable, guarded - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT, CONFIG_SYS_PCI_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 3: 256M Non-cacheable, guarded - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT + 0x10000000, CONFIG_SYS_PCI_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 4: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe100_0000 255M PCI IO range - */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xf8000000 64M PIXIS 0xF8000000 - 0xFBFFFFFF - */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_NONCACHE_BASE, CONFIG_SYS_LBC_NONCACHE_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_64M, 1), -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8572ds/Kconfig b/board/freescale/mpc8572ds/Kconfig deleted file mode 100644 index 38132cf3fe..0000000000 --- a/board/freescale/mpc8572ds/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC8572DS - -config SYS_BOARD - default "mpc8572ds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8572DS" - -endif diff --git a/board/freescale/mpc8572ds/MAINTAINERS b/board/freescale/mpc8572ds/MAINTAINERS deleted file mode 100644 index d7e9b1f41f..0000000000 --- a/board/freescale/mpc8572ds/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -MPC8572DS BOARD -M: Priyanka Jain <priyanka.jain@nxp.com> -S: Maintained -F: board/freescale/mpc8572ds/ -F: include/configs/MPC8572DS.h -F: configs/MPC8572DS_defconfig -F: configs/MPC8572DS_36BIT_defconfig diff --git a/board/freescale/mpc8572ds/Makefile b/board/freescale/mpc8572ds/Makefile deleted file mode 100644 index 5318e3be72..0000000000 --- a/board/freescale/mpc8572ds/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2007 Freescale Semiconductor, Inc. -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y += mpc8572ds.o -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/mpc8572ds/README b/board/freescale/mpc8572ds/README deleted file mode 100644 index f1ffdd1730..0000000000 --- a/board/freescale/mpc8572ds/README +++ /dev/null @@ -1,166 +0,0 @@ -Overview --------- -MPC8572DS is a high-performance computing, evaluation and development platform -supporting the mpc8572 PowerTM processor. - -Building U-Boot ------------ - make MPC8572DS_config - make - -Flash Banks ------------ -MPC8572DS board has two flash banks. They are both present on boot, but their -locations can be swapped using the dip-switch SW9[1:2]. - -Booting is always from the boot bank at 0xec00_0000. - - -Memory Map ----------- - -0xe800_0000 - 0xebff_ffff Alternate bank 64MB -0xec00_0000 - 0xefff_ffff Boot bank 64MB - -0xebf8_0000 - 0xebff_ffff Alternate U-Boot address 512KB -0xeff8_0000 - 0xefff_ffff Boot U-Boot address 512KB - - -Flashing Images ---------------- - -To place a new U-Boot image in the alternate flash bank and then reset with that - new image temporarily, use this: - - tftp 1000000 u-boot.bin - erase ebf80000 ebffffff - cp.b 1000000 ebf80000 80000 - pixis_reset altbank - - -To program the image in the boot flash bank: - - tftp 1000000 u-boot.bin - protect off all - erase eff80000 ffffffff - cp.b 1000000 eff80000 80000 - - -The pixis_reset command ------------------------ -The command - "pixis_reset", is introduced to reset mpc8572ds board -using the FPGA sequencer. When the board restarts, it has the option -of using either the current or alternate flash bank as the boot -image, with or without the watchdog timer enabled, and finally with -or without frequency changes. - -Usage is; - - pixis_reset - pixis_reset altbank - pixis_reset altbank wd - pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> - pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> - -Examples: - - /* reset to current bank, like "reset" command */ - pixis_reset - - /* reset board but use the to alternate flash bank */ - pixis_reset altbank - - -Using the Device Tree Source File ---------------------------------- -To create the DTB (Device Tree Binary) image file, -use a command similar to this: - - dtc -b 0 -f -I dts -O dtb mpc8572ds.dts > mpc8572ds.dtb - -Likely, that .dts file will come from here; - - linux-2.6/arch/powerpc/boot/dts/mpc8572ds.dts - - -Booting Linux -------------- - -Place a linux uImage in the TFTP disk area. - - tftp 1000000 uImage.8572 - tftp c00000 mpc8572ds.dtb - bootm 1000000 - c00000 - - -Implementing AMP(Asymmetric MultiProcessing) -------------- -1. Build kernel image for core0: - - a. $ make 85xx/mpc8572_ds_defconfig - - b. $ make menuconfig - - un-select "Processor support"->"Symetric multi-processing support" - - c. $ make uImage - - d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0 - -2. Build kernel image for core1: - - a. $ make 85xx/mpc8572_ds_defconfig - - b. $ make menuconfig - - Un-select "Processor support"->"Symetric multi-processing support" - - Select "Advanced setup" -> " Prompt for advanced kernel - configuration options" - - Select "Set physical address where the kernel is loaded" and - set it to 0x20000000, assuming core1 will start from 512MB. - - Select "Set custom page offset address" - - Select "Set custom kernel base address" - - Select "Set maximum low memory" - - "Exit" and save the selection. - - c. $ make uImage - - d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1 - -3. Create dtb for core0: - - $ dtc -I dts -O dtb -f -b 0 arch/powerpc/boot/dts/mpc8572ds_core0.dts > /tftpboot/mpc8572ds_core0.dtb - -4. Create dtb for core1: - - $ dtc -I dts -O dtb -f -b 1 arch/powerpc/boot/dts/mpc8572ds_core1.dts > /tftpboot/mpc8572ds_core1.dtb - -5. Bring up two cores separately: - - a. Power on the board, under U-Boot prompt: - => setenv <serverip> - => setenv <ipaddr> - => setenv bootargs root=/dev/ram rw console=ttyS0,115200 - b. Bring up core1's kernel first: - => setenv bootm_low 0x20000000 - => setenv bootm_size 0x10000000 - => tftp 21000000 8572/uImage.core1 - => tftp 22000000 8572/ramdiskfile - => tftp 20c00000 8572/mpc8572ds_core1.dtb - => interrupts off - => bootm start 21000000 22000000 20c00000 - => bootm loados - => bootm ramdisk - => bootm fdt - => fdt boardsetup - => fdt chosen $initrd_start $initrd_end - => bootm prep - => cpu 1 release $bootm_low - $fdtaddr - - c. Bring up core0's kernel(on the same U-Boot console): - => setenv bootm_low 0 - => setenv bootm_size 0x20000000 - => tftp 1000000 8572/uImage.core0 - => tftp 2000000 8572/ramdiskfile - => tftp c00000 8572/mpc8572ds_core0.dtb - => bootm 1000000 2000000 c00000 - -Please note only core0 will run U-Boot, core1 starts kernel directly after -"cpu release" command is issued. diff --git a/board/freescale/mpc8572ds/ddr.c b/board/freescale/mpc8572ds/ddr.c deleted file mode 100644 index 11ca08d1a0..0000000000 --- a/board/freescale/mpc8572ds/ddr.c +++ /dev/null @@ -1,166 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2008 Freescale Semiconductor, Inc. - */ - -#include <common.h> - -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> - -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 clk_adjust; - u32 cpo; - u32 write_data_delay; - u32 force_2t; -}; - -/* - * This table contains all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - * - * For DDR2 DIMM, all combinations of clk_adjust and write_data_delay have been - * tested. For RDIMM, clk_adjust = 4 and write_data_delay = 3 is optimized for - * all clocks from 400MT/s to 800MT/s, verified with Kingston KVR800D2D8P6/2G. - * For UDIMM, clk_adjust = 8 and write_delay = 5 is optimized for all clocks - * from 400MT/s to 800MT/s, verified with Micron MT18HTF25672AY-800E1. - * - * CPO value doesn't matter if workaround for errata 111 and 134 enabled. - */ -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| clk| cpo|wrdata|2T - * ranks| mhz|adjst| | delay| - */ - {2, 333, 8, 7, 5, 0}, - {2, 400, 8, 9, 5, 0}, - {2, 549, 8, 11, 5, 0}, - {2, 680, 8, 10, 5, 0}, - {2, 850, 8, 12, 5, 1}, - {1, 333, 6, 7, 3, 0}, - {1, 400, 6, 9, 3, 0}, - {1, 549, 6, 11, 3, 0}, - {1, 680, 1, 10, 5, 0}, - {1, 850, 1, 12, 5, 0}, - {} -}; - -static const struct board_specific_parameters udimm1[] = { - /* - * memory controller 1 - * num| hi| clk| cpo|wrdata|2T - * ranks| mhz|adjst| | delay| - */ - {2, 333, 8, 7, 5, 0}, - {2, 400, 8, 9, 5, 0}, - {2, 549, 8, 11, 5, 0}, - {2, 680, 8, 11, 5, 0}, - {2, 850, 8, 13, 5, 1}, - {1, 333, 6, 7, 3, 0}, - {1, 400, 6, 9, 3, 0}, - {1, 549, 6, 11, 3, 0}, - {1, 680, 1, 11, 6, 0}, - {1, 850, 1, 13, 6, 0}, - {} -}; - -static const struct board_specific_parameters *udimms[] = { - udimm0, - udimm1, -}; - -static const struct board_specific_parameters rdimm0[] = { - /* - * memory controller 0 - * num| hi| clk| cpo|wrdata|2T - * ranks| mhz|adjst| | delay| - */ - {2, 333, 4, 7, 3, 0}, - {2, 400, 4, 9, 3, 0}, - {2, 549, 4, 11, 3, 0}, - {2, 680, 4, 10, 3, 0}, - {2, 850, 4, 12, 3, 1}, - {} -}; - -static const struct board_specific_parameters rdimm1[] = { - /* - * memory controller 1 - * num| hi| clk| cpo|wrdata|2T - * ranks| mhz|adjst| | delay| - */ - {2, 333, 4, 7, 3, 0}, - {2, 400, 4, 9, 3, 0}, - {2, 549, 4, 11, 3, 0}, - {2, 680, 4, 11, 3, 0}, - {2, 850, 4, 13, 3, 1}, - {} -}; - -static const struct board_specific_parameters *rdimms[] = { - rdimm0, - rdimm1, -}; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - - if (ctrl_num > 1) { - printf("Wrong parameter for controller number %d", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - if (popts->registered_dimm_en) - pbsp = rdimms[ctrl_num]; - else - pbsp = udimms[ctrl_num]; - - /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = - pbsp->write_data_delay; - popts->twot_en = pbsp->force_2t; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found " - "for data rate %lu MT/s!\n" - "Trying to use the highest speed (%u) parameters\n", - ddr_freq, pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp->clk_adjust; - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = pbsp->write_data_delay; - popts->twot_en = pbsp->force_2t; - } else { - panic("DIMM is not supported by this board"); - } - -found: - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/freescale/mpc8572ds/law.c b/board/freescale/mpc8572ds/law.c deleted file mode 100644 index 10d1572c5d..0000000000 --- a/board/freescale/mpc8572ds/law.c +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2008, 2010 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c deleted file mode 100644 index 97e73533ab..0000000000 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ /dev/null @@ -1,260 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2007-2011 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <command.h> -#include <env.h> -#include <image.h> -#include <init.h> -#include <log.h> -#include <net.h> -#include <pci.h> -#include <asm/processor.h> -#include <asm/mmu.h> -#include <asm/cache.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_pci.h> -#include <fsl_ddr_sdram.h> -#include <asm/io.h> -#include <asm/fsl_serdes.h> -#include <miiphy.h> -#include <linux/delay.h> -#include <linux/libfdt.h> -#include <fdt_support.h> -#include <tsec.h> -#include <fsl_mdio.h> -#include <netdev.h> - -#include "../common/sgmii_riser.h" - -int checkboard (void) -{ - u8 vboot; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - printf("Board: MPC8572DS Sys ID: 0x%02x, " - "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", - in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), - in_8(pixis_base + PIXIS_PVER)); - - vboot = in_8(pixis_base + PIXIS_VBOOT); - switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) { - case PIXIS_VBOOT_LBMAP_NOR0: - puts ("vBank: 0\n"); - break; - case PIXIS_VBOOT_LBMAP_PJET: - puts ("Promjet\n"); - break; - case PIXIS_VBOOT_LBMAP_NAND: - puts ("NAND\n"); - break; - case PIXIS_VBOOT_LBMAP_NOR1: - puts ("vBank: 1\n"); - break; - } - - return 0; -} - - -#if !defined(CONFIG_SPD_EEPROM) -/* - * Fixed sdram init -- doesn't use serial presence detect. - */ - -phys_size_t fixed_sdram (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - struct ccsr_ddr __iomem *ddr = &immap->im_ddr; - uint d_init; - - ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; - ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; - - ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; - ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; - ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; - ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; - ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; - ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; - -#if defined (CONFIG_DDR_ECC) - ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; - ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; - ddr->err_sbe = CONFIG_SYS_DDR_SBE; -#endif - asm("sync;isync"); - - udelay(500); - - ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; - -#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - d_init = 1; - debug("DDR - 1st controller: memory initializing\n"); - /* - * Poll until memory is initialized. - * 512 Meg at 400 might hit this 200 times or so. - */ - while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { - udelay(1000); - } - debug("DDR: memory initialized\n\n"); - asm("sync; isync"); - udelay(500); -#endif - - return 512 * 1024 * 1024; -} - -#endif - -#ifdef CONFIG_PCI -void pci_init_board(void) -{ - struct pci_controller *hose; - - fsl_pcie_init_board(0); - - hose = find_hose_by_cfg_addr((void *)(CONFIG_SYS_PCIE3_ADDR)); - - if (hose) { - u32 temp32; - u8 uli_busno = hose->first_busno + 2; - - /* - * Activate ULI1575 legacy chip by performing a fake - * memory access. Needed to make ULI RTC work. - * Device 1d has the first on-board memory BAR. - */ - pci_hose_read_config_dword(hose, PCI_BDF(uli_busno, 0x1d, 0), - PCI_BASE_ADDRESS_1, &temp32); - - if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) { - void *p = pci_mem_to_virt(PCI_BDF(uli_busno, 0x1d, 0), - temp32, 4, 0); - debug(" uli1572 read to %p\n", p); - in_be32(p); - } - } -} -#endif - -int board_early_init_r(void) -{ - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - int flash_esel = find_tlb_idx((void *)flashbase, 1); - - /* - * Remap Boot flash + PROMJET region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - if (flash_esel == -1) { - /* very unlikely unless something is messed up */ - puts("Error: Could not find TLB for FLASH BASE\n"); - flash_esel = 2; /* give our best effort to continue */ - } else { - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); - } - - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ - 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ - - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_TSEC_ENET - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[4]; - int num = 0; - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - if (is_serdes_configured(SGMII_TSEC1)) { - puts("eTSEC1 is in sgmii mode.\n"); - tsec_info[num].flags |= TSEC_SGMII; - } - num++; -#endif -#ifdef CONFIG_TSEC2 - SET_STD_TSEC_INFO(tsec_info[num], 2); - if (is_serdes_configured(SGMII_TSEC2)) { - puts("eTSEC2 is in sgmii mode.\n"); - tsec_info[num].flags |= TSEC_SGMII; - } - num++; -#endif -#ifdef CONFIG_TSEC3 - SET_STD_TSEC_INFO(tsec_info[num], 3); - if (is_serdes_configured(SGMII_TSEC3)) { - puts("eTSEC3 is in sgmii mode.\n"); - tsec_info[num].flags |= TSEC_SGMII; - } - num++; -#endif -#ifdef CONFIG_TSEC4 - SET_STD_TSEC_INFO(tsec_info[num], 4); - if (is_serdes_configured(SGMII_TSEC4)) { - puts("eTSEC4 is in sgmii mode.\n"); - tsec_info[num].flags |= TSEC_SGMII; - } - num++; -#endif - - if (!num) { - printf("No TSECs initialized\n"); - - return 0; - } - -#ifdef CONFIG_FSL_SGMII_RISER - fsl_sgmii_riser_init(tsec_info, num); -#endif - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - fsl_pq_mdio_init(bis, &mdio_info); - - tsec_eth_init(bis, tsec_info, num); -#endif - - return pci_eth_init(bis); -} - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = env_get_bootm_low(); - size = env_get_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - - FT_FSL_PCI_SETUP; - -#ifdef CONFIG_FSL_SGMII_RISER - fsl_sgmii_riser_fdt_fixup(blob); -#endif - - return 0; -} -#endif diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c deleted file mode 100644 index 99b136b042..0000000000 --- a/board/freescale/mpc8572ds/tlb.c +++ /dev/null @@ -1,87 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2008-2010 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 1), - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_1M, 1), - - /* W**G* - Flash/promjet, localbus */ - /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - -#ifndef CONFIG_NAND_SPL - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_1G, 1), - - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_256K, 1), -#endif - - /* *I*G - NAND */ - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_1M, 1), - - SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_4K, 1), - -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) - /* *I*G - L2SRAM */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, - CONFIG_SYS_INIT_L2_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 9, BOOKE_PAGESZ_256K, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, - CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_256K, 1), -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8610hpcd/Kconfig b/board/freescale/mpc8610hpcd/Kconfig deleted file mode 100644 index 8f713beaa8..0000000000 --- a/board/freescale/mpc8610hpcd/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC8610HPCD - -config SYS_BOARD - default "mpc8610hpcd" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8610HPCD" - -endif diff --git a/board/freescale/mpc8610hpcd/MAINTAINERS b/board/freescale/mpc8610hpcd/MAINTAINERS deleted file mode 100644 index 9b1e0cd4e5..0000000000 --- a/board/freescale/mpc8610hpcd/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MPC8610HPCD BOARD -M: Priyanka Jain <priyanka.jain@nxp.com> -S: Maintained -F: board/freescale/mpc8610hpcd/ -F: include/configs/MPC8610HPCD.h -F: configs/MPC8610HPCD_defconfig diff --git a/board/freescale/mpc8610hpcd/Makefile b/board/freescale/mpc8610hpcd/Makefile deleted file mode 100644 index 3a02a06416..0000000000 --- a/board/freescale/mpc8610hpcd/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# Copyright 2007 Freescale Semiconductor, Inc. - -obj-y += mpc8610hpcd.o -obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o -obj-y += law.o -obj-$(CONFIG_FSL_DIU_FB) += mpc8610hpcd_diu.o diff --git a/board/freescale/mpc8610hpcd/README b/board/freescale/mpc8610hpcd/README deleted file mode 100644 index 066e625d48..0000000000 --- a/board/freescale/mpc8610hpcd/README +++ /dev/null @@ -1,73 +0,0 @@ -Freescale MPC8610HPCD board -=========================== - - -Building U-Boot ---------------- - - $ make MPC8610HPCD_config - Configuring for MPC8610HPCD board... - - $ make - - -Flashing U-Boot ---------------- -The flash is 128M starting at 0xF800_0000. - -The alternate image is at 0xFBF0_0000 -The boot image is at 0xFFF0_0000. - - -To Flash U-Boot into the booting bank: - - tftp 1000000 u-boot.bin - protect off all - erase fff00000 +$filesize - cp.b 1000000 fff00000 $filesize - - -To Flash U-Boot into the alternate bank - - tftp 1000000 u-boot.bin - erase fbf00000 +$filesize - cp.b 1000000 fbf00000 $filesize - - -pixis_reset command -------------------- -A new command, "pixis_reset", is introduced to reset mpc8610hpcd board -using the FPGA sequencer. When the board restarts, it has the option -of using either the current or alternate flash bank as the boot -image, with or without the watchdog timer enabled, and finally with -or without frequency changes. - -Usage is; - - pixis_reset - pixis_reset altbank - pixis_reset altbank wd - pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> - pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> - -Examples; - - /* reset to current bank, like "reset" command */ - pixis_reset - - /* reset board but use the to alternate flash bank */ - pixis_reset altbank - - /* reset board, use alternate flash bank with watchdog timer enabled*/ - pixis_reset altbank wd - - /* reset board to alternate bank with frequency changed. - * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio - */ - pixis-reset altbank cf 40 2.5 10 - - -DIP Switch Settings -------------------- -To manually switch the flash banks using the DIP switch -settings, toggle both SW6:1 and SW6:2. diff --git a/board/freescale/mpc8610hpcd/ddr.c b/board/freescale/mpc8610hpcd/ddr.c deleted file mode 100644 index c4d985347b..0000000000 --- a/board/freescale/mpc8610hpcd/ddr.c +++ /dev/null @@ -1,56 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2008 Freescale Semiconductor, Inc. - */ - -#include <common.h> - -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for clock adjust: - * - number of chips on bus - * - position of slot - * - DDR1 vs. DDR2? - * - ??? - * - * This needs to be determined on a board-by-board basis. - * 0110 3/4 cycle late - * 0111 7/8 cycle late - */ - popts->clk_adjust = 7; - - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 10; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; - - /* 2T timing enable */ - popts->twot_en = 1; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/freescale/mpc8610hpcd/law.c b/board/freescale/mpc8610hpcd/law.c deleted file mode 100644 index 7bf5e6815d..0000000000 --- a/board/freescale/mpc8610hpcd/law.c +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2008,2010 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -struct law_entry law_table[] = { -#if !defined(CONFIG_SPD_EEPROM) - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR_1), -#endif - SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c deleted file mode 100644 index 52bf4da98e..0000000000 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ /dev/null @@ -1,335 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2007,2009-2011 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <command.h> -#include <init.h> -#include <log.h> -#include <net.h> -#include <pci.h> -#include <asm/processor.h> -#include <asm/immap_86xx.h> -#include <asm/fsl_pci.h> -#include <fsl_ddr_sdram.h> -#include <asm/fsl_serdes.h> -#include <i2c.h> -#include <asm/io.h> -#include <linux/delay.h> -#include <linux/libfdt.h> -#include <fdt_support.h> -#include <spd_sdram.h> -#include <netdev.h> - -DECLARE_GLOBAL_DATA_PTR; - -void sdram_init(void); -phys_size_t fixed_sdram(void); -int mpc8610hpcd_diu_init(void); - - -/* called before any console output */ -int board_early_init_f(void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; - - gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */ - - return 0; -} - -int misc_init_r(void) -{ - u8 tmp_val, version; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - /*Do not use 8259PIC*/ - tmp_val = in_8(pixis_base + PIXIS_BRDCFG0); - out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80); - - /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/ - version = in_8(pixis_base + PIXIS_PVER); - if(version >= 0x07) { - tmp_val = in_8(pixis_base + PIXIS_BRDCFG0); - out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf); - } - - /* Using this for DIU init before the driver in linux takes over - * Enable the TFP410 Encoder (I2C address 0x38) - */ - - tmp_val = 0xBF; - i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); - /* Verify if enabled */ - tmp_val = 0; - i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); - debug("DVI Encoder Read: 0x%02x\n", tmp_val); - - tmp_val = 0x10; - i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); - /* Verify if enabled */ - tmp_val = 0; - i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); - debug("DVI Encoder Read: 0x%02x\n", tmp_val); - - return 0; -} - -int checkboard(void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - printf ("Board: MPC8610HPCD, Sys ID: 0x%02x, " - "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", - in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), - in_8(pixis_base + PIXIS_PVER)); - - /* - * The MPC8610 HPCD workbook says that LBMAP=11 is the "normal" boot - * bank and LBMAP=00 is the alternate bank. However, the pixis - * altbank code can only set bits, not clear them, so we treat 00 as - * the normal bank and 11 as the alternate. - */ - switch (in_8(pixis_base + PIXIS_VBOOT) & 0xC0) { - case 0: - puts("vBank: Standard\n"); - break; - case 0x40: - puts("Promjet\n"); - break; - case 0x80: - puts("NAND\n"); - break; - case 0xC0: - puts("vBank: Alternate\n"); - break; - } - - mcm->abcr |= 0x00010000; /* 0 */ - mcm->hpmr3 = 0x80000008; /* 4c */ - mcm->hpmr0 = 0; - mcm->hpmr1 = 0; - mcm->hpmr2 = 0; - mcm->hpmr4 = 0; - mcm->hpmr5 = 0; - - return 0; -} - - -int dram_init(void) -{ - phys_size_t dram_size = 0; - -#if defined(CONFIG_SPD_EEPROM) - dram_size = fsl_ddr_sdram(); -#else - dram_size = fixed_sdram(); -#endif - - setup_ddr_bat(dram_size); - - debug(" DDR: "); - gd->ram_size = dram_size; - - return 0; -} - - -#if !defined(CONFIG_SPD_EEPROM) -/* - * Fixed sdram init -- doesn't use serial presence detect. - */ - -phys_size_t fixed_sdram(void) -{ -#if !defined(CONFIG_SYS_RAMBOOT) - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - struct ccsr_ddr __iomem *ddr = &immap->im_ddr1; - uint d_init; - - ddr->cs0_bnds = 0x0000001f; - ddr->cs0_config = 0x80010202; - - ddr->timing_cfg_3 = 0x00000000; - ddr->timing_cfg_0 = 0x00260802; - ddr->timing_cfg_1 = 0x3935d322; - ddr->timing_cfg_2 = 0x14904cc8; - ddr->sdram_mode = 0x00480432; - ddr->sdram_mode_2 = 0x00000000; - ddr->sdram_interval = 0x06180fff; /* 0x06180100; */ - ddr->sdram_data_init = 0xDEADBEEF; - ddr->sdram_clk_cntl = 0x03800000; - ddr->sdram_cfg_2 = 0x04400010; - -#if defined(CONFIG_DDR_ECC) - ddr->err_int_en = 0x0000000d; - ddr->err_disable = 0x00000000; - ddr->err_sbe = 0x00010000; -#endif - asm("sync;isync"); - - udelay(500); - - ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/ - - -#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - d_init = 1; - debug("DDR - 1st controller: memory initializing\n"); - /* - * Poll until memory is initialized. - * 512 Meg at 400 might hit this 200 times or so. - */ - while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) - udelay(1000); - - debug("DDR: memory initialized\n\n"); - asm("sync; isync"); - udelay(500); -#endif - - return 512 * 1024 * 1024; -#endif - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; -} - -#endif - -#if defined(CONFIG_PCI) -/* - * Initialize PCI Devices, report devices found. - */ - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_fsl86xxads_config_table[] = { - {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} }, - {} -}; -#endif - - -static struct pci_controller pci1_hose; -#endif /* CONFIG_PCI */ - -void pci_init_board(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; - volatile ccsr_gur_t *gur = &immap->im_gur; - struct fsl_pci_info pci_info; - u32 devdisr; - int first_free_busno; - int pci_agent; - - devdisr = in_be32(&gur->devdisr); - - first_free_busno = fsl_pcie_init_board(0); - -#ifdef CONFIG_PCI1 - if (!(devdisr & MPC86xx_DEVDISR_PCI1)) { - SET_STD_PCI_INFO(pci_info, 1); - set_next_law(pci_info.mem_phys, - law_size_bits(pci_info.mem_size), pci_info.law); - set_next_law(pci_info.io_phys, - law_size_bits(pci_info.io_size), pci_info.law); - - pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); - printf("PCI: connected to PCI slots as %s" \ - " (base address %lx)\n", - pci_agent ? "Agent" : "Host", - pci_info.regs); -#ifndef CONFIG_PCI_PNP - pci1_hose.config_table = pci_mpc86xxcts_config_table; -#endif - first_free_busno = fsl_pci_init_port(&pci_info, - &pci1_hose, first_free_busno); - } else { - printf("PCI: disabled\n"); - } - - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */ -#endif - - fsl_pcie_init_board(first_free_busno); -} - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - ft_cpu_setup(blob, bd); - - FT_FSL_PCI_SETUP; - - return 0; -} -#endif - -/* - * get_board_sys_clk - * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ - */ - -unsigned long -get_board_sys_clk(ulong dummy) -{ - u8 i; - ulong val = 0; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - i = in_8(pixis_base + PIXIS_SPD); - i &= 0x07; - - switch (i) { - case 0: - val = 33333000; - break; - case 1: - val = 39999600; - break; - case 2: - val = 49999500; - break; - case 3: - val = 66666000; - break; - case 4: - val = 83332500; - break; - case 5: - val = 99999000; - break; - case 6: - val = 133332000; - break; - case 7: - val = 166665000; - break; - } - - return val; -} - -int board_eth_init(struct bd_info *bis) -{ - return pci_eth_init(bis); -} - -void board_reset(void) -{ - u8 *pixis_base = (u8 *)PIXIS_BASE; - - out_8(pixis_base + PIXIS_RST, 0); - - while (1) - ; -} diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c deleted file mode 100644 index 9b96d0d33f..0000000000 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2007-2011 Freescale Semiconductor, Inc. - * Authors: York Sun <yorksun@freescale.com> - * Timur Tabi <timur@freescale.com> - * - * FSL DIU Framebuffer driver - */ - -#include <common.h> -#include <clock_legacy.h> -#include <command.h> -#include <log.h> -#include <asm/io.h> -#include <fsl_diu_fb.h> -#include "../common/pixis.h" - -#define PX_BRDCFG0_DLINK 0x10 -#define PX_BRDCFG0_DVISEL 0x08 - -void diu_set_pixel_clock(unsigned int pixclock) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; - volatile unsigned int *guts_clkdvdr = &gur->clkdvdr; - unsigned long speed_ccb, temp, pixval; - - speed_ccb = get_bus_freq(0); - temp = 1000000000/pixclock; - temp *= 1000; - pixval = speed_ccb / temp; - debug("DIU pixval = %lu\n", pixval); - - /* Modify PXCLK in GUTS CLKDVDR */ - debug("DIU: Current value of CLKDVDR = 0x%08x\n", *guts_clkdvdr); - temp = *guts_clkdvdr & 0x2000FFFF; - *guts_clkdvdr = temp; /* turn off clock */ - *guts_clkdvdr = temp | 0x80000000 | ((pixval & 0x1F) << 16); - debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *guts_clkdvdr); -} - -int platform_diu_init(unsigned int xres, unsigned int yres, const char *port) -{ - const char *name; - int gamma_fix = 0; - u32 pixel_format = 0x88883316; - u8 temp; - - temp = in_8(&pixis->brdcfg0); - - if (strncmp(port, "dlvds", 5) == 0) { - /* Dual link LVDS */ - gamma_fix = 1; - temp &= ~(PX_BRDCFG0_DLINK | PX_BRDCFG0_DVISEL); - name = "Dual-Link LVDS"; - } else if (strncmp(port, "lvds", 4) == 0) { - /* Single link LVDS */ - temp = (temp & ~PX_BRDCFG0_DVISEL) | PX_BRDCFG0_DLINK; - name = "Single-Link LVDS"; - } else { - /* DVI */ - if (in_8(&pixis->ver) == 1) /* Board version */ - pixel_format = 0x88882317; - temp |= PX_BRDCFG0_DVISEL; - name = "DVI"; - } - - printf("DIU: Switching to %s monitor @ %ux%u\n", name, xres, yres); - out_8(&pixis->brdcfg0, temp); - - return fsl_diu_init(xres, yres, pixel_format, gamma_fix); -} diff --git a/board/freescale/mpc8641hpcn/Kconfig b/board/freescale/mpc8641hpcn/Kconfig deleted file mode 100644 index ae45d63337..0000000000 --- a/board/freescale/mpc8641hpcn/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC8641HPCN - -config SYS_BOARD - default "mpc8641hpcn" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8641HPCN" - -endif diff --git a/board/freescale/mpc8641hpcn/MAINTAINERS b/board/freescale/mpc8641hpcn/MAINTAINERS deleted file mode 100644 index c957218767..0000000000 --- a/board/freescale/mpc8641hpcn/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -MPC8641HPCN BOARD -M: Priyanka Jain <priyanka.jain@nxp.com> -S: Maintained -F: board/freescale/mpc8641hpcn/ -F: include/configs/MPC8641HPCN.h -F: configs/MPC8641HPCN_defconfig -F: configs/MPC8641HPCN_36BIT_defconfig diff --git a/board/freescale/mpc8641hpcn/Makefile b/board/freescale/mpc8641hpcn/Makefile deleted file mode 100644 index 86b87193dd..0000000000 --- a/board/freescale/mpc8641hpcn/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y += mpc8641hpcn.o -obj-y += law.o -obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o diff --git a/board/freescale/mpc8641hpcn/README b/board/freescale/mpc8641hpcn/README deleted file mode 100644 index 77909a8383..0000000000 --- a/board/freescale/mpc8641hpcn/README +++ /dev/null @@ -1,186 +0,0 @@ -Freescale MPC8641HPCN board -=========================== - -Created 05/24/2006 Haiying Wang -------------------------------- - -1. Building U-Boot ------------------- -The 86xx HPCN code base is known to compile using: - Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3 - - $ make MPC8641HPCN_config - Configuring for MPC8641HPCN board... - - $ make - - -2. Switch and Jumper Setting ----------------------------- -Jumpers: - J14 Pins 1-2 (near plcc32 socket) - -Switches: - SW1(1-5) = 01100 CONFIG_SYS_COREPLL = 01000 :: CORE = 2:1 - 01100 :: CORE = 2.5:1 - 10000 :: CORE = 3:1 - 11100 :: CORE = 3.5:1 - 10100 :: CORE = 4:1 - 01110 :: CORE = 4.5:1 - SW1(6-8) = 001 CONFIG_SYS_SYSCLK = 000 :: SYSCLK = 33MHz - 001 :: SYSCLK = 40MHz - - SW2(1-4) = 1100 CONFIG_SYS_CCBPLL = 0010 :: 2X - 0100 :: 4X - 0110 :: 6X - 1000 :: 8X - 1010 :: 10X - 1100 :: 12X - 1110 :: 14X - 0000 :: 16X - SW2(5-8) = 1110 CONFIG_SYS_BOOTLOC = 1110 :: boot 16-bit localbus - - SW3(1-7) = 0011000 CONFIG_SYS_VID = 0011000 :: VCORE = 1.2V - 0100000 :: VCORE = 1.11V - SW3(8) = 0 VCC_PLAT = 0 :: VCC_PLAT = 1.2V - 1 :: VCC_PLAT = 1.0V - - SW4(1-2) = 11 CONFIG_SYS_HOSTMODE = 11 :: both prots host/root - SW4(3-4) = 11 CONFIG_SYS_BOOTSEQ = 11 :: no boot seq - SW4(5-8) = 0011 CONFIG_SYS_IOPORT = 0011 :: both PEX - - SW5(1) = 1 CONFIG_SYS_FLASHMAP = 1 :: boot from flash - 0 :: boot from PromJet - SW5(2) = 1 CONFIG_SYS_FLASHBANK = 1 :: swap upper/lower - halves (virtual banks) - 0 :: normal - SW5(3) = 0 CONFIG_SYS_FLASHWP = 0 :: not protected - SW5(4) = 0 CONFIG_SYS_PORTDIV = 1 :: 2:1 for PD4 - 1:1 for PD6 - SW5(5-6) = 11 CONFIG_SYS_PIXISOPT = 11 :: s/w determined - SW5(7-8) = 11 CONFIG_SYS_LADOPT = 11 :: s/w determined - - SW6(1) = 1 CONFIG_SYS_CPUBOOT = 1 :: no boot holdoff - SW6(2) = 1 CONFIG_SYS_BOOTADDR = 1 :: no traslation - SW6(3-5) = 000 CONFIG_SYS_REFCLKSEL = 000 :: 100MHZ - SW6(6) = 1 CONFIG_SYS_SERROM_ADDR= 1 :: - SW6(7) = 1 CONFIG_SYS_MEMDEBUG = 1 :: - SW6(8) = 1 CONFIG_SYS_DDRDEBUG = 1 :: - - SW8(1) = 1 ACZ_SYNC = 1 :: 48MHz on TP49 - SW8(2) = 1 ACB_SYNC = 1 :: THRMTRIP disabled - SW8(3) = 1 ACZ_SDOUT = 1 :: p4 mode - SW8(4) = 1 ACB_SDOUT = 1 :: PATA freq. = 133MHz - SW8(5) = 0 SUSLED = 0 :: SouthBridge Mode - SW8(6) = 0 SPREAD = 0 :: REFCLK SSCG Disabled - SW8(7) = 1 ACPWR = 1 :: non-battery - SW8(8) = 0 CONFIG_SYS_IDWP = 0 :: write enable - - -3. Flash U-Boot ---------------- -The flash range 0xEF800000 to 0xEFFFFFFF can be divided into 2 halves. -It is possible to use either half to boot using U-Boot. Switch 5 bit 2 -is used for this purpose. - -0xEF800000 to 0xEFBFFFFF - 4MB -0xEFC00000 to 0xEFFFFFFF - 4MB -When this bit is 0, U-Boot is at 0xEFF00000. -When this bit is 1, U-Boot is at 0xEFB00000. - -Use the above mentioned flash commands to program the other half, and -use switch 5, bit 2 to alternate between the halves. Note: The booting -version of U-Boot will always be at 0xEFF00000. - -To Flash U-Boot into the booting bank (0xEFC00000 - 0xEFFFFFFF): - - tftp 1000000 u-boot.bin - protect off all - erase eff00000 +$filesize - cp.b 1000000 eff00000 $filesize - -or use tftpflash command: - run tftpflash - -To Flash U-Boot into the alternative bank (0xEF800000 - 0xEFBFFFFF): - - tftp 1000000 u-boot.bin - erase efb00000 +$filesize - cp.b 1000000 efb00000 $filesize - - -4. Memory Map -------------- -NOTE: RIO and PCI are mutually exclusive, so they share an address - -For 32-bit U-Boot, devices are mapped so that the virtual address == -the physical address, and the map looks liks this: - - Memory Range Device Size - ------------ ------ ---- - 0x0000_0000 0x7fff_ffff DDR 2G - 0x8000_0000 0x9fff_ffff RIO MEM 512M - 0x8000_0000 0x9fff_ffff PCI1/PEX1 MEM 512M - 0xa000_0000 0xbfff_ffff PCI2/PEX2 MEM 512M - 0xffe0_0000 0xffef_ffff CCSR 1M - 0xffdf_0000 0xffdf_7fff PIXIS 8K - 0xffdf_8000 0xffdf_ffff CF 8K - 0xf840_0000 0xf840_3fff Stack space 32K - 0xffc0_0000 0xffc0_ffff PCI1/PEX1 IO 64K - 0xffc1_0000 0xffc1_ffff PCI2/PEX2 IO 64K - 0xef80_0000 0xefff_ffff Flash 8M - -For 36-bit-enabled U-Boot, the virtual map is the same as for 32-bit. -However, the physical map is altered to reside in 36-bit space, as follows. -Addresses are no longer mapped with VA == PA. All accesses from -software use the VA; the PA is only used for setting up windows -and mappings. Note that with the exception of PCI MEM and RIO, the low - 32 bits are the same as the VA above; only the top 4 bits vary: - - Memory Range Device Size - ------------ ------ ---- - 0x0_0000_0000 0x0_7fff_ffff DDR 2G - 0xc_0000_0000 0xc_1fff_ffff RIO MEM 512M - 0xc_0000_0000 0xc_1fff_ffff PCI1/PEX1 MEM 512M - 0xc_2000_0000 0xc_3fff_ffff PCI2/PEX2 MEM 512M - 0xf_ffe0_0000 0xf_ffef_ffff CCSR 1M - 0xf_ffdf_0000 0xf_ffdf_7fff PIXIS 8K - 0xf_ffdf_8000 0xf_ffdf_ffff CF 8K - 0x0_f840_0000 0xf_f840_3fff Stack space 32K - 0xf_ffc0_0000 0xf_ffc0_ffff PCI1/PEX1 IO 64K - 0xf_ffc1_0000 0xf_ffc1_ffff PCI2/PEX2 IO 64K - 0xf_ef80_0000 0xf_efff_ffff Flash 8M - -5. pixis_reset command --------------------- -A new command, "pixis_reset", is introduced to reset mpc8641hpcn board -using the FPGA sequencer. When the board restarts, it has the option -of using either the current or alternate flash bank as the boot -image, with or without the watchdog timer enabled, and finally with -or without frequency changes. - -Usage is; - - pixis_reset - pixis_reset altbank - pixis_reset altbank wd - pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> - pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> - -Examples; - - /* reset to current bank, like "reset" command */ - pixis_reset - - /* reset board but use the to alternate flash bank */ - pixis_reset altbank - - /* reset board, use alternate flash bank with watchdog timer enabled*/ - pixis_reset altbank wd - - /* reset board to alternate bank with frequency changed. - * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio - */ - pixis-reset altbank cf 40 2.5 10 - -Valid clock choices are in the 8641 Reference Manuals. diff --git a/board/freescale/mpc8641hpcn/ddr.c b/board/freescale/mpc8641hpcn/ddr.c deleted file mode 100644 index df7e3eceed..0000000000 --- a/board/freescale/mpc8641hpcn/ddr.c +++ /dev/null @@ -1,107 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2008,2011 Freescale Semiconductor, Inc. - */ - -#include <common.h> - -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> - -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 clk_adjust; - u32 cpo; - u32 write_data_delay; -}; - -/* - * This table contains all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ -const struct board_specific_parameters dimm0[] = { - /* - * memory controller 0 - * num| hi| clk| cpo|wrdata|2T - * ranks| mhz|adjst| | delay| - */ - {4, 333, 7, 7, 3}, - {4, 549, 7, 9, 3}, - {4, 650, 7, 10, 4}, - {2, 333, 7, 7, 3}, - {2, 549, 7, 9, 3}, - {2, 650, 7, 10, 4}, - {1, 333, 7, 7, 3}, - {1, 549, 7, 9, 3}, - {1, 650, 7, 10, 4}, - {} -}; - -/* - * The two slots have slightly different timing. The center values are good - * for both slots. We use identical speed tables for them. In future use, if - * DIMMs have fewer center values that require two separated tables, copy the - * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start. - */ -const struct board_specific_parameters *dimms[] = { - dimm0, - dimm0, -}; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - unsigned int i; - ulong ddr_freq; - - if (ctrl_num > 1) { - printf("Wrong parameter for controller number %d", ctrl_num); - return; - } - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (pdimm[i].n_ranks) - break; - } - if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) /* no DIMM */ - return; - - pbsp = dimms[ctrl_num]; - - /* Get clk_adjust, cpo, write_data_delay, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm[i].n_ranks) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = - pbsp->write_data_delay; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found " - "for data rate %lu MT/s!\n" - "Trying to use the highest speed (%u) parameters\n", - ddr_freq, pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->cpo_override = pbsp_highest->cpo; - popts->write_data_delay = pbsp_highest->write_data_delay; - } else { - panic("DIMM is not supported by this board"); - } - -found: - /* 2T timing enable */ - popts->twot_en = 1; -} diff --git a/board/freescale/mpc8641hpcn/law.c b/board/freescale/mpc8641hpcn/law.c deleted file mode 100644 index b73d660883..0000000000 --- a/board/freescale/mpc8641hpcn/law.c +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2008,2010-2011 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * if PCI (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT) - * 0x8000_0000 0x9fff_ffff PCIE1 MEM 512M - * 0xa000_0000 0xbfff_ffff PCIE2 MEM 512M - * else if RIO (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT) - * 0x8000_0000 0x9fff_ffff RapidIO 512M - * endif - * (prepend 0xf_0000_0000 if CONFIG_PHYS_64BIT) - * 0xffc0_0000 0xffc0_ffff PCIE1 IO 64K - * 0xffc1_0000 0xffc1_ffff PCIE2 IO 64K - * 0xffe0_0000 0xffef_ffff CCSRBAR 1M - * 0xffdf_0000 0xffe0_0000 PIXIS, CF 64K - * 0xef80_0000 0xefff_ffff FLASH (boot bank) 8M - * - * Notes: - * CCSRBAR doesn't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -struct law_entry law_table[] = { -#if !defined(CONFIG_SPD_EEPROM) - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1), -#endif - SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c deleted file mode 100644 index 0f9aea469b..0000000000 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ /dev/null @@ -1,247 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2006, 2007, 2010-2011 Freescale Semiconductor. - */ - -#include <common.h> -#include <init.h> -#include <log.h> -#include <net.h> -#include <pci.h> -#include <asm/processor.h> -#include <asm/immap_86xx.h> -#include <asm/fsl_pci.h> -#include <fsl_ddr_sdram.h> -#include <asm/fsl_serdes.h> -#include <asm/io.h> -#include <linux/delay.h> -#include <linux/libfdt.h> -#include <fdt_support.h> -#include <netdev.h> - -DECLARE_GLOBAL_DATA_PTR; - -phys_size_t fixed_sdram(void); - -int checkboard(void) -{ - u8 vboot; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, " - "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", - in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), - in_8(pixis_base + PIXIS_PVER)); - - vboot = in_8(pixis_base + PIXIS_VBOOT); - if (vboot & PIXIS_VBOOT_FMAP) - printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6)); - else - puts ("Promjet\n"); - - return 0; -} - -int dram_init(void) -{ - phys_size_t dram_size = 0; - -#if defined(CONFIG_SPD_EEPROM) - dram_size = fsl_ddr_sdram(); -#else - dram_size = fixed_sdram(); -#endif - - setup_ddr_bat(dram_size); - - debug(" DDR: "); - gd->ram_size = dram_size; - - return 0; -} - - -#if !defined(CONFIG_SPD_EEPROM) -/* - * Fixed sdram init -- doesn't use serial presence detect. - */ -phys_size_t -fixed_sdram(void) -{ -#if !defined(CONFIG_SYS_RAMBOOT) - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - struct ccsr_ddr __iomem *ddr = &immap->im_ddr1; - - ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; - ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; - ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; - ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; - ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; - ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; - ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; - ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL; - ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS; - -#if defined (CONFIG_DDR_ECC) - ddr->err_disable = 0x0000008D; - ddr->err_sbe = 0x00ff0000; -#endif - asm("sync;isync"); - - udelay(500); - -#if defined (CONFIG_DDR_ECC) - /* Enable ECC checking */ - ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); -#else - ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; - ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; -#endif - asm("sync; isync"); - - udelay(500); -#endif - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; -} -#endif /* !defined(CONFIG_SPD_EEPROM) */ - -void pci_init_board(void) -{ - fsl_pcie_init_board(0); - -#ifdef CONFIG_PCIE1 - /* - * Activate ULI1575 legacy chip by performing a fake - * memory access. Needed to make ULI RTC work. - */ - in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT - + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000))); -#endif /* CONFIG_PCIE1 */ -} - - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - int off; - u64 *tmp; - int addrcells; - - ft_cpu_setup(blob, bd); - - FT_FSL_PCI_SETUP; - - /* - * Warn if it looks like the device tree doesn't match u-boot. - * This is just an estimation, based on the location of CCSR, - * which is defined by the "reg" property in the soc node. - */ - off = fdt_path_offset(blob, "/soc8641"); - addrcells = fdt_address_cells(blob, 0); - tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL); - - if (tmp) { - u64 addr; - - if (addrcells == 1) - addr = *(u32 *)tmp; - else - addr = *tmp; - - if (addr != CONFIG_SYS_CCSRBAR_PHYS) - printf("WARNING: The CCSRBAR address in your .dts " - "does not match the address of the CCSR " - "in u-boot. This means your .dts might " - "be old.\n"); - } - - return 0; -} -#endif - - -/* - * get_board_sys_clk - * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ - */ - -unsigned long -get_board_sys_clk(ulong dummy) -{ - u8 i, go_bit, rd_clks; - ulong val = 0; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - go_bit = in_8(pixis_base + PIXIS_VCTL); - go_bit &= 0x01; - - rd_clks = in_8(pixis_base + PIXIS_VCFGEN0); - rd_clks &= 0x1C; - - /* - * Only if both go bit and the SCLK bit in VCFGEN0 are set - * should we be using the AUX register. Remember, we also set the - * GO bit to boot from the alternate bank on the on-board flash - */ - - if (go_bit) { - if (rd_clks == 0x1c) - i = in_8(pixis_base + PIXIS_AUX); - else - i = in_8(pixis_base + PIXIS_SPD); - } else { - i = in_8(pixis_base + PIXIS_SPD); - } - - i &= 0x07; - - switch (i) { - case 0: - val = 33000000; - break; - case 1: - val = 40000000; - break; - case 2: - val = 50000000; - break; - case 3: - val = 66000000; - break; - case 4: - val = 83000000; - break; - case 5: - val = 100000000; - break; - case 6: - val = 134000000; - break; - case 7: - val = 166000000; - break; - } - - return val; -} - -int board_eth_init(struct bd_info *bis) -{ - /* Initialize TSECs */ - cpu_eth_init(bis); - return pci_eth_init(bis); -} - -void board_reset(void) -{ - u8 *pixis_base = (u8 *)PIXIS_BASE; - - out_8(pixis_base + PIXIS_RST, 0); - - while (1) - ; -} diff --git a/board/freescale/mx35pdk/Kconfig b/board/freescale/mx35pdk/Kconfig deleted file mode 100644 index 021d19e551..0000000000 --- a/board/freescale/mx35pdk/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_MX35PDK - -config SYS_BOARD - default "mx35pdk" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "mx35" - -config SYS_CONFIG_NAME - default "mx35pdk" - -endif diff --git a/board/freescale/mx35pdk/MAINTAINERS b/board/freescale/mx35pdk/MAINTAINERS deleted file mode 100644 index 540e943691..0000000000 --- a/board/freescale/mx35pdk/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MX35PDK BOARD -M: Stefano Babic <sbabic@denx.de> -S: Maintained -F: board/freescale/mx35pdk/ -F: include/configs/mx35pdk.h -F: configs/mx35pdk_defconfig diff --git a/board/freescale/mx35pdk/Makefile b/board/freescale/mx35pdk/Makefile deleted file mode 100644 index 6a60fad0cc..0000000000 --- a/board/freescale/mx35pdk/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> -# -# (C) Copyright 2008-2009 Freescale Semiconductor, Inc. - -obj-y := mx35pdk.o -obj-y += lowlevel_init.o diff --git a/board/freescale/mx35pdk/README b/board/freescale/mx35pdk/README deleted file mode 100644 index 6f6841f099..0000000000 --- a/board/freescale/mx35pdk/README +++ /dev/null @@ -1,114 +0,0 @@ -Overview --------------- - -mx35pdk (known als as mx35_3stack) is a development board by Freescale. -It consists of three pluggable board: - - CPU module, with CPU, RAM, flash - - Personality board, with most interfaces (USB, Network,..) - - Debug board with JTAG header. - -The board is usually delivered with redboot. This howto explains how to boot -a linux kernel and how to replace the original bootloader with U-Boot. - -The board is delivered with Redboot on the NAND flash. It is possible to -switch the boot device with the switches SW1-SW2 on the Personality board, -and with SW5-SW10 on the Debug board. - -Delivered Redboot script to start the kernel ---------------------------------------------------- - -In redboot the following script is stored: - -fis load kernel -exec -c "noinitrd console=ttymxc0,115200 root=/dev/mtdblock8 rw rootfstype=jffs2 ip=dhcp fec_mac=00:04:9F:00:E7:76" - -Kernel is taken from flash. The image is in zImage format. - -Booting from NET, rootfs on NFS: ------------------------------------ - -To change the script in redboot: - -load -r -b 0x100000 <path_to_zImage> -exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nfsroot=192.168.1.1:/opt/eldk-4.2-arm/armVFP rw ip=dhcp" - -If the ip address is not set, you can set it with : - -ip_address -l <board_ip/netmask> -h <server_ip> - -Linux partitions: ---------------------------- - -As default, the board is shipped with these partition tables for NAND -and for NOR: - -Creating 5 MTD partitions on "NAND 2GiB 3,3V 8-bit": -0x00000000-0x00100000 : "nand.bootloader" -0x00100000-0x00600000 : "nand.kernel" -0x00600000-0x06600000 : "nand.rootfs" -0x06600000-0x06e00000 : "nand.configure" -0x06e00000-0x80000000 : "nand.userfs" - -Creating 6 MTD partitions on "mxc_nor_flash.0": -0x00000000-0x00080000 : "Bootloader" -0x00080000-0x00480000 : "nor.Kernel" -0x00480000-0x02280000 : "nor.userfs" -0x02280000-0x03e80000 : "nor.rootfs" -0x01fe0000-0x01fe3000 : "FIS directory" -0x01fff000-0x04000000 : "Redboot config" - -NAND partitions can be recognized enabling in kernel CONFIG_MTD_REDBOOT_PARTS. -For this board, CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK should be set to 2. - -However, the setup in redboot is not correct and does not use the whole flash. - -Better solution is to use the kernel parameter mtdparts. -Here the resulting script to be defined in RedBoot with fconfig: - -load -r -b 0x100000 sbabic/mx35pdk/zImage.2.6.37 -exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nfsroot=192.168.1.1:/opt/eldk-4.2-arm/arm rw ip=dhcp mtdparts=mxc_nand:1m(boot),5m(linux),96m(root),8m(cfg),1938m(user);physmap-flash.0:512k(b),4m(k),30m(u),28m(r)" - -Flashing U-Boot --------------------------------- - -U-Boot should be stored on the NOR flash. - -The boot storage can be select using the switches on the personality board -(SW1-SW2) and on the DEBUG board (SW4-SW10). - -If something goes wrong flashing the bootloader, it is always possible to -recover the board booting from the other device. - -Saving U-Boot in the NOR flash ---------------------------------- - -Check the partition for boot in the NOR flash. Setting the mtdparts as reported, -the boot partition should be /dev/mtd0. - -Creating 6 MTD partitions on "mxc_nor_flash.0": -0x00000000-0x00080000 : "Bootloader" -0x00080000-0x00480000 : "nor.Kernel" -0x00480000-0x02280000 : "nor.userfs" -0x02280000-0x03e80000 : "nor.rootfs" -0x01fe0000-0x01fe3000 : "FIS directory" -0x01fff000-0x04000000 : "Redboot config" - -To erase the whole partition: -$ flash_eraseall /dev/mtd0 - -Writing U-Boot: -dd if=u-boot.bin of=/dev/mtd0 - -To boot from NOR, you have to select the switches as follows: - -Personality board - SW2 all off - SW1 all off - -Debug Board: - SW5 0 - SW6 0 - SW7 0 - SW8 1 - SW9 1 - SW10 0 diff --git a/board/freescale/mx35pdk/lowlevel_init.S b/board/freescale/mx35pdk/lowlevel_init.S deleted file mode 100644 index 5dae5597fb..0000000000 --- a/board/freescale/mx35pdk/lowlevel_init.S +++ /dev/null @@ -1,239 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> - * - * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. - */ - -#include <config.h> -#include <asm/arch/imx-regs.h> -#include <generated/asm-offsets.h> -#include "mx35pdk.h" -#include <asm/arch/lowlevel_macro.S> - -/* - * return soc version - * 0x10: TO1 - * 0x20: TO2 - * 0x30: TO3 - */ -.macro check_soc_version ret, tmp - ldr \tmp, =IIM_BASE_ADDR - ldr \ret, [\tmp, #IIM_SREV] - cmp \ret, #0x00 - moveq \tmp, #ROMPATCH_REV - ldreq \ret, [\tmp] - moveq \ret, \ret, lsl #4 - addne \ret, \ret, #0x10 -.endm - -/* CPLD on CS5 setup */ -.macro init_debug_board - ldr r0, =DBG_BASE_ADDR - ldr r1, =DBG_CSCR_U_CONFIG - str r1, [r0, #0x00] - ldr r1, =DBG_CSCR_L_CONFIG - str r1, [r0, #0x04] - ldr r1, =DBG_CSCR_A_CONFIG - str r1, [r0, #0x08] -.endm - -/* clock setup */ -.macro init_clock - ldr r0, =CCM_BASE_ADDR - - /* default CLKO to 1/32 of the ARM core*/ - ldr r1, [r0, #CLKCTL_COSR] - bic r1, r1, #0x00000FF00 - bic r1, r1, #0x0000000FF - mov r2, #0x00006C00 - add r2, r2, #0x67 - orr r1, r1, r2 - str r1, [r0, #CLKCTL_COSR] - - ldr r2, =CCM_CCMR_CONFIG - str r2, [r0, #CLKCTL_CCMR] - - check_soc_version r1, r2 - cmp r1, #CHIP_REV_2_0 - ldrhs r3, =CCM_MPLL_532_HZ - bhs 1f - ldr r2, [r0, #CLKCTL_PDR0] - tst r2, #CLKMODE_CONSUMER - ldrne r3, =CCM_MPLL_532_HZ /* consumer path*/ - ldreq r3, =CCM_MPLL_399_HZ /* auto path*/ -1: - str r3, [r0, #CLKCTL_MPCTL] - - ldr r1, =CCM_PPLL_300_HZ - str r1, [r0, #CLKCTL_PPCTL] - - ldr r1, =CCM_PDR0_CONFIG - bic r1, r1, #0x800000 - str r1, [r0, #CLKCTL_PDR0] - - ldr r1, [r0, #CLKCTL_CGR0] - orr r1, r1, #0x0C300000 - str r1, [r0, #CLKCTL_CGR0] - - ldr r1, [r0, #CLKCTL_CGR1] - orr r1, r1, #0x00000C00 - orr r1, r1, #0x00000003 - str r1, [r0, #CLKCTL_CGR1] - - ldr r1, [r0, #CLKCTL_CGR2] - orr r1, r1, #0x00C00000 - str r1, [r0, #CLKCTL_CGR2] -.endm - -.macro setup_sdram - ldr r0, =ESDCTL_BASE_ADDR - mov r3, #0x2000 - str r3, [r0, #0x0] - str r3, [r0, #0x8] - - /*ip(r12) has used to save lr register in upper calling*/ - mov fp, lr - - mov r5, #0x00 - mov r2, #0x00 - mov r1, #CSD0_BASE_ADDR - bl setup_sdram_bank - - mov r5, #0x00 - mov r2, #0x00 - mov r1, #CSD1_BASE_ADDR - bl setup_sdram_bank - - mov lr, fp - -1: - ldr r3, =ESDCTL_DELAY_LINE5 - str r3, [r0, #0x30] -.endm - -.globl lowlevel_init -lowlevel_init: - mov r10, lr - - core_init - - init_aips - - init_max - - init_m3if - - init_clock - init_debug_board - - cmp pc, #PHYS_SDRAM_1 - blo init_sdram_start - cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) - blo skip_sdram_setup - -init_sdram_start: - /*init_sdram*/ - setup_sdram - -skip_sdram_setup: - mov lr, r10 - mov pc, lr - - -/* - * r0: ESDCTL control base, r1: sdram slot base - * r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base - */ -setup_sdram_bank: - mov r3, #0xE - tst r2, #0x1 - orreq r3, r3, #0x300 /*DDR2*/ - str r3, [r0, #0x10] - bic r3, r3, #0x00A - str r3, [r0, #0x10] - beq 2f - - mov r3, #0x20000 -1: subs r3, r3, #1 - bne 1b - -2: tst r2, #0x1 - ldreq r3, =ESDCTL_DDR2_CONFIG - ldrne r3, =ESDCTL_MDDR_CONFIG - cmp r1, #CSD1_BASE_ADDR - strlo r3, [r0, #0x4] - strhs r3, [r0, #0xC] - - ldr r3, =ESDCTL_0x92220000 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - mov r3, #0xDA - ldr r4, =ESDCTL_PRECHARGE - strb r3, [r1, r4] - - tst r2, #0x1 - bne skip_set_mode - - cmp r1, #CSD1_BASE_ADDR - ldr r3, =ESDCTL_0xB2220000 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - mov r3, #0xDA - ldr r4, =ESDCTL_DDR2_EMR2 - strb r3, [r1, r4] - ldr r4, =ESDCTL_DDR2_EMR3 - strb r3, [r1, r4] - ldr r4, =ESDCTL_DDR2_EN_DLL - strb r3, [r1, r4] - ldr r4, =ESDCTL_DDR2_RESET_DLL - strb r3, [r1, r4] - - ldr r3, =ESDCTL_0x92220000 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - mov r3, #0xDA - ldr r4, =ESDCTL_PRECHARGE - strb r3, [r1, r4] - -skip_set_mode: - cmp r1, #CSD1_BASE_ADDR - ldr r3, =ESDCTL_0xA2220000 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - mov r3, #0xDA - strb r3, [r1] - strb r3, [r1] - - ldr r3, =ESDCTL_0xB2220000 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - tst r2, #0x1 - ldreq r4, =ESDCTL_DDR2_MR - ldrne r4, =ESDCTL_MDDR_MR - mov r3, #0xDA - strb r3, [r1, r4] - ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT - streqb r3, [r1, r4] - ldreq r4, =ESDCTL_DDR2_EN_DLL - ldrne r4, =ESDCTL_MDDR_EMR - strb r3, [r1, r4] - - cmp r1, #CSD1_BASE_ADDR - ldr r3, =ESDCTL_0x82228080 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - - tst r2, #0x1 - moveq r4, #0x20000 - movne r4, #0x200 -1: subs r4, r4, #1 - bne 1b - - str r3, [r1, #0x100] - ldr r4, [r1, #0x100] - cmp r3, r4 - movne r3, #1 - moveq r3, #0 - - mov pc, lr diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c deleted file mode 100644 index fc024c47db..0000000000 --- a/board/freescale/mx35pdk/mx35pdk.c +++ /dev/null @@ -1,293 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> - * - * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <init.h> -#include <net.h> -#include <asm/io.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/crm_regs.h> -#include <asm/arch/clock.h> -#include <asm/arch/iomux-mx35.h> -#include <i2c.h> -#include <power/pmic.h> -#include <fsl_pmic.h> -#include <mmc.h> -#include <fsl_esdhc_imx.h> -#include <mc9sdz60.h> -#include <mc13892.h> -#include <linux/types.h> -#include <asm/gpio.h> -#include <asm/arch/sys_proto.h> -#include <netdev.h> -#include <asm/mach-types.h> - -#ifndef CONFIG_BOARD_LATE_INIT -#error "CONFIG_BOARD_LATE_INIT must be set for this board" -#endif - -#ifndef CONFIG_BOARD_EARLY_INIT_F -#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board" -#endif - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - u32 size1, size2; - - size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); - - gd->ram_size = size1 + size2; - - return 0; -} - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - - return 0; -} - -#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE) - -static void setup_iomux_i2c(void) -{ - static const iomux_v3_cfg_t i2c1_pads[] = { - NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL), - NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL), - }; - - /* setup pins for I2C1 */ - imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads)); -} - - -static void setup_iomux_spi(void) -{ - static const iomux_v3_cfg_t spi_pads[] = { - MX35_PAD_CSPI1_MOSI__CSPI1_MOSI, - MX35_PAD_CSPI1_MISO__CSPI1_MISO, - MX35_PAD_CSPI1_SS0__CSPI1_SS0, - MX35_PAD_CSPI1_SS1__CSPI1_SS1, - MX35_PAD_CSPI1_SCLK__CSPI1_SCLK, - }; - - imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads)); -} - -#define USBOTG_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | \ - PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW) -#define USBOTG_OUT_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW) - -static void setup_iomux_usbotg(void) -{ - static const iomux_v3_cfg_t usbotg_pads[] = { - NEW_PAD_CTRL(MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR, - USBOTG_OUT_PAD_CTRL), - NEW_PAD_CTRL(MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC, - USBOTG_IN_PAD_CTRL), - }; - - /* Set up pins for USBOTG. */ - imx_iomux_v3_setup_multiple_pads(usbotg_pads, ARRAY_SIZE(usbotg_pads)); -} - -#define FEC_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW) - -static void setup_iomux_fec(void) -{ - static const iomux_v3_cfg_t fec_pads[] = { - NEW_PAD_CTRL(MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, FEC_PAD_CTRL | - PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - NEW_PAD_CTRL(MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, FEC_PAD_CTRL | - PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - NEW_PAD_CTRL(MX35_PAD_FEC_RX_DV__FEC_RX_DV, FEC_PAD_CTRL | - PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - NEW_PAD_CTRL(MX35_PAD_FEC_COL__FEC_COL, FEC_PAD_CTRL | - PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - NEW_PAD_CTRL(MX35_PAD_FEC_RDATA0__FEC_RDATA_0, FEC_PAD_CTRL | - PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - NEW_PAD_CTRL(MX35_PAD_FEC_TDATA0__FEC_TDATA_0, FEC_PAD_CTRL), - NEW_PAD_CTRL(MX35_PAD_FEC_TX_EN__FEC_TX_EN, FEC_PAD_CTRL), - NEW_PAD_CTRL(MX35_PAD_FEC_MDC__FEC_MDC, FEC_PAD_CTRL), - NEW_PAD_CTRL(MX35_PAD_FEC_MDIO__FEC_MDIO, FEC_PAD_CTRL | - PAD_CTL_HYS | PAD_CTL_PUS_22K_UP), - NEW_PAD_CTRL(MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, FEC_PAD_CTRL), - NEW_PAD_CTRL(MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, FEC_PAD_CTRL | - PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - NEW_PAD_CTRL(MX35_PAD_FEC_CRS__FEC_CRS, FEC_PAD_CTRL | - PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - NEW_PAD_CTRL(MX35_PAD_FEC_RDATA1__FEC_RDATA_1, FEC_PAD_CTRL | - PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - NEW_PAD_CTRL(MX35_PAD_FEC_TDATA1__FEC_TDATA_1, FEC_PAD_CTRL), - NEW_PAD_CTRL(MX35_PAD_FEC_RDATA2__FEC_RDATA_2, FEC_PAD_CTRL | - PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - NEW_PAD_CTRL(MX35_PAD_FEC_TDATA2__FEC_TDATA_2, FEC_PAD_CTRL), - NEW_PAD_CTRL(MX35_PAD_FEC_RDATA3__FEC_RDATA_3, FEC_PAD_CTRL | - PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - NEW_PAD_CTRL(MX35_PAD_FEC_TDATA3__FEC_TDATA_3, FEC_PAD_CTRL), - }; - - /* setup pins for FEC */ - imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); -} - -int board_early_init_f(void) -{ - struct ccm_regs *ccm = - (struct ccm_regs *)IMX_CCM_BASE; - - /* enable clocks */ - writel(readl(&ccm->cgr0) | - MXC_CCM_CGR0_EMI_MASK | - MXC_CCM_CGR0_EDIO_MASK | - MXC_CCM_CGR0_EPIT1_MASK, - &ccm->cgr0); - - writel(readl(&ccm->cgr1) | - MXC_CCM_CGR1_FEC_MASK | - MXC_CCM_CGR1_GPIO1_MASK | - MXC_CCM_CGR1_GPIO2_MASK | - MXC_CCM_CGR1_GPIO3_MASK | - MXC_CCM_CGR1_I2C1_MASK | - MXC_CCM_CGR1_I2C2_MASK | - MXC_CCM_CGR1_IPU_MASK, - &ccm->cgr1); - - /* Setup NAND */ - __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr); - - setup_iomux_i2c(); - setup_iomux_usbotg(); - setup_iomux_fec(); - setup_iomux_spi(); - - return 0; -} - -int board_init(void) -{ - gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS; /* board id for linux */ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -static inline int pmic_detect(void) -{ - unsigned int id; - struct pmic *p = pmic_get("FSL_PMIC"); - if (!p) - return -ENODEV; - - pmic_reg_read(p, REG_IDENTIFICATION, &id); - - id = (id >> 6) & 0x7; - if (id == 0x7) - return 1; - return 0; -} - -u32 get_board_rev(void) -{ - int rev; - - rev = pmic_detect(); - - return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; -} - -int board_late_init(void) -{ - u8 val; - u32 pmic_val; - struct pmic *p; - int ret; - - ret = pmic_init(I2C_0); - if (ret) - return ret; - - if (pmic_detect()) { - p = pmic_get("FSL_PMIC"); - imx_iomux_v3_setup_pad(MX35_PAD_WDOG_RST__WDOG_WDOG_B); - - pmic_reg_read(p, REG_SETTING_0, &pmic_val); - pmic_reg_write(p, REG_SETTING_0, - pmic_val | VO_1_30V | VO_1_50V); - pmic_reg_read(p, REG_MODE_0, &pmic_val); - pmic_reg_write(p, REG_MODE_0, pmic_val | VGEN3EN); - - imx_iomux_v3_setup_pad(MX35_PAD_COMPARE__GPIO1_5); - - gpio_direction_output(IMX_GPIO_NR(1, 5), 1); - } - - val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04; - mc9sdz60_reg_write(MC9SDZ60_REG_GPIO_1, val); - mdelay(200); - - val = mc9sdz60_reg_read(MC9SDZ60_REG_RESET_1) & 0x7F; - mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val); - mdelay(200); - - val |= 0x80; - mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val); - - /* Print board revision */ - printf("Board: MX35 PDK %d.0\n", ((get_board_rev() >> 8) + 1) & 0x0F); - - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_SMC911X) - int rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); - if (rc) - return rc; -#endif - return cpu_eth_init(bis); -} - -#if defined(CONFIG_FSL_ESDHC_IMX) - -struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR}; - -int board_mmc_init(struct bd_info *bis) -{ - static const iomux_v3_cfg_t sdhc1_pads[] = { - MX35_PAD_SD1_CMD__ESDHC1_CMD, - MX35_PAD_SD1_CLK__ESDHC1_CLK, - MX35_PAD_SD1_DATA0__ESDHC1_DAT0, - MX35_PAD_SD1_DATA1__ESDHC1_DAT1, - MX35_PAD_SD1_DATA2__ESDHC1_DAT2, - MX35_PAD_SD1_DATA3__ESDHC1_DAT3, - }; - - /* configure pins for SDHC1 only */ - imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads)); - - esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK); - return fsl_esdhc_initialize(bis, &esdhc_cfg); -} - -int board_mmc_getcd(struct mmc *mmc) -{ - return !(mc9sdz60_reg_read(MC9SDZ60_REG_DES_FLAG) & 0x4); -} -#endif diff --git a/board/freescale/mx35pdk/mx35pdk.h b/board/freescale/mx35pdk/mx35pdk.h deleted file mode 100644 index 0af4b88bfb..0000000000 --- a/board/freescale/mx35pdk/mx35pdk.h +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. - */ - -#ifndef __BOARD_MX35_3STACK_H -#define __BOARD_MX35_3STACK_H - -#define DBG_BASE_ADDR WEIM_CTRL_CS5 -#define DBG_CSCR_U_CONFIG 0x0000D843 -#define DBG_CSCR_L_CONFIG 0x22252521 -#define DBG_CSCR_A_CONFIG 0x22220A00 - -#define CCM_CCMR_CONFIG 0x003F4208 -#define CCM_PDR0_CONFIG 0x00801000 - -/* MEMORY SETTING */ -#define ESDCTL_0x92220000 0x92220000 -#define ESDCTL_0xA2220000 0xA2220000 -#define ESDCTL_0xB2220000 0xB2220000 -#define ESDCTL_0x82228080 0x82228080 - -#define ESDCTL_PRECHARGE 0x00000400 - -#define ESDCTL_MDDR_CONFIG 0x007FFC3F -#define ESDCTL_MDDR_MR 0x00000033 -#define ESDCTL_MDDR_EMR 0x02000000 - -#define ESDCTL_DDR2_CONFIG 0x007FFC3F -#define ESDCTL_DDR2_EMR2 0x04000000 -#define ESDCTL_DDR2_EMR3 0x06000000 -#define ESDCTL_DDR2_EN_DLL 0x02000400 -#define ESDCTL_DDR2_RESET_DLL 0x00000333 -#define ESDCTL_DDR2_MR 0x00000233 -#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780 - -#define ESDCTL_DELAY_LINE5 0x00F49F00 -#endif /* __BOARD_MX35_3STACK_H */ diff --git a/board/renesas/MigoR/Kconfig b/board/renesas/MigoR/Kconfig deleted file mode 100644 index 25b170ac07..0000000000 --- a/board/renesas/MigoR/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MIGOR - -config SYS_BOARD - default "MigoR" - -config SYS_VENDOR - default "renesas" - -config SYS_CONFIG_NAME - default "MigoR" - -endif diff --git a/board/renesas/MigoR/MAINTAINERS b/board/renesas/MigoR/MAINTAINERS deleted file mode 100644 index 21ee5e2754..0000000000 --- a/board/renesas/MigoR/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MIGOR BOARD -#M: - -S: Maintained -F: board/renesas/MigoR/ -F: include/configs/MigoR.h -F: configs/MigoR_defconfig diff --git a/board/renesas/MigoR/Makefile b/board/renesas/MigoR/Makefile deleted file mode 100644 index 944a3bfe2c..0000000000 --- a/board/renesas/MigoR/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007 -# Nobuhiro Iwamatsu <iwamatsu@nigauri.org> -# -# Copyright (C) 2007 -# Kenati Technologies, Inc. -# -# board/MigoR/Makefile -# - -obj-y := migo_r.o -extra-y += lowlevel_init.o diff --git a/board/renesas/MigoR/lowlevel_init.S b/board/renesas/MigoR/lowlevel_init.S deleted file mode 100644 index 1b494faeb0..0000000000 --- a/board/renesas/MigoR/lowlevel_init.S +++ /dev/null @@ -1,193 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2007-2008 - * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * - * Copyright (C) 2007 - * Kenati Technologies, Inc. - * - * board/MigoR/lowlevel_init.S - */ - -#include <config.h> - -#include <asm/processor.h> -#include <asm/macro.h> - -/* - * Board specific low level init code, called _very_ early in the - * startup sequence. Relocation to SDRAM has not happened yet, no - * stack is available, bss section has not been initialised, etc. - * - * (Note: As no stack is available, no subroutines can be called...). - */ - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - write32 CCR_A, CCR_D ! Address of Cache Control Register - ! Instruction Cache Invalidate - - write32 MMUCR_A, MMUCR_D ! Address of MMU Control Register - ! TI == TLB Invalidate bit - - write32 MSTPCR0_A, MSTPCR0_D ! Address of Power Control Register 0 - - write32 MSTPCR2_A, MSTPCR2_D ! Address of Power Control Register 2 - - write16 PFC_PULCR_A, PFC_PULCR_D - - write16 PFC_DRVCR_A, PFC_DRVCR_D - - write16 SBSCR_A, SBSCR_D - - write16 PSCR_A, PSCR_D - - write16 RWTCSR_A, RWTCSR_D_1 ! 0xA4520004 (Watchdog Control / Status Register) - ! 0xA507 -> timer_STOP / WDT_CLK = max - - write16 RWTCNT_A, RWTCNT_D ! 0xA4520000 (Watchdog Count Register) - ! 0x5A00 -> Clear - - write16 RWTCSR_A, RWTCSR_D_2 ! 0xA4520004 (Watchdog Control / Status Register) - ! 0xA504 -> timer_STOP / CLK = 500ms - - write32 DLLFRQ_A, DLLFRQ_D ! 20080115 - ! 20080115 - - write32 FRQCR_A, FRQCR_D ! 0xA4150000 Frequency control register - ! 20080115 - - write32 CCR_A, CCR_D_2 ! Address of Cache Control Register - ! ?? - -bsc_init: - write32 CMNCR_A, CMNCR_D - - write32 CS0BCR_A, CS0BCR_D - - write32 CS4BCR_A, CS4BCR_D - - write32 CS5ABCR_A, CS5ABCR_D - - write32 CS5BBCR_A, CS5BBCR_D - - write32 CS6ABCR_A, CS6ABCR_D - - write32 CS0WCR_A, CS0WCR_D - - write32 CS4WCR_A, CS4WCR_D - - write32 CS5AWCR_A, CS5AWCR_D - - write32 CS5BWCR_A, CS5BWCR_D - - write32 CS6AWCR_A, CS6AWCR_D - - ! SDRAM initialization - write32 SDCR_A, SDCR_D - - write32 SDWCR_A, SDWCR_D - - write32 SDPCR_A, SDPCR_D - - write32 RTCOR_A, RTCOR_D - - write32 RTCNT_A, RTCNT_D - - write32 RTCSR_A, RTCSR_D - - write32 RFCR_A, RFCR_D - - write8 SDMR3_A, SDMR3_D - - ! BL bit off (init = ON) (?!?) - - stc sr, r0 ! BL bit off(init=ON) - mov.l SR_MASK_D, r1 - and r1, r0 - ldc r0, sr - - rts - mov #0, r0 - - .align 4 - -CCR_A: .long CCR -MMUCR_A: .long MMUCR -MSTPCR0_A: .long MSTPCR0 -MSTPCR2_A: .long MSTPCR2 -PFC_PULCR_A: .long PULCR -PFC_DRVCR_A: .long DRVCR -SBSCR_A: .long SBSCR -PSCR_A: .long PSCR -RWTCSR_A: .long RWTCSR -RWTCNT_A: .long RWTCNT -FRQCR_A: .long FRQCR -PLLCR_A: .long PLLCR -DLLFRQ_A: .long DLLFRQ - -CCR_D: .long 0x00000800 -CCR_D_2: .long 0x00000103 -MMUCR_D: .long 0x00000004 -MSTPCR0_D: .long 0x00001001 -MSTPCR2_D: .long 0xffffffff -PFC_PULCR_D: .long 0x6000 -PFC_DRVCR_D: .long 0x0464 -FRQCR_D: .long 0x07033639 -PLLCR_D: .long 0x00005000 -DLLFRQ_D: .long 0x000004F6 - -CMNCR_A: .long CMNCR -CMNCR_D: .long 0x0000001B -CS0BCR_A: .long CS0BCR -CS0BCR_D: .long 0x24920400 -CS4BCR_A: .long CS4BCR -CS4BCR_D: .long 0x00003400 -CS5ABCR_A: .long CS5ABCR -CS5ABCR_D: .long 0x24920400 -CS5BBCR_A: .long CS5BBCR -CS5BBCR_D: .long 0x24920400 -CS6ABCR_A: .long CS6ABCR -CS6ABCR_D: .long 0x24920400 - -CS0WCR_A: .long CS0WCR -CS0WCR_D: .long 0x00000380 -CS4WCR_A: .long CS4WCR -CS4WCR_D: .long 0x00110080 -CS5AWCR_A: .long CS5AWCR -CS5AWCR_D: .long 0x00000300 -CS5BWCR_A: .long CS5BWCR -CS5BWCR_D: .long 0x00000300 -CS6AWCR_A: .long CS6AWCR -CS6AWCR_D: .long 0x00000300 - -SDCR_A: .long SBSC_SDCR -SDCR_D: .long 0x80160809 -SDWCR_A: .long SBSC_SDWCR -SDWCR_D: .long 0x0014450C -SDPCR_A: .long SBSC_SDPCR -SDPCR_D: .long 0x00000087 -RTCOR_A: .long SBSC_RTCOR -RTCNT_A: .long SBSC_RTCNT -RTCNT_D: .long 0xA55A0012 -RTCOR_D: .long 0xA55A001C -RTCSR_A: .long SBSC_RTCSR -RFCR_A: .long SBSC_RFCR -RFCR_D: .long 0xA55A0221 -RTCSR_D: .long 0xA55A009a -SDMR3_A: .long 0xFE581180 -SDMR3_D: .long 0x0 - -SR_MASK_D: .long 0xEFFFFF0F - - .align 2 - -SBSCR_D: .word 0x0044 -PSCR_D: .word 0x0000 -RWTCSR_D_1: .word 0xA507 -RWTCSR_D_2: .word 0xA504 -RWTCNT_D: .word 0x5A00 diff --git a/board/renesas/MigoR/migo_r.c b/board/renesas/MigoR/migo_r.c deleted file mode 100644 index f2f4c65753..0000000000 --- a/board/renesas/MigoR/migo_r.c +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2007 - * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * - * Copyright (C) 2007 - * Kenati Technologies, Inc. - * - * board/MigoR/migo_r.c - */ - -#include <common.h> -#include <init.h> -#include <net.h> -#include <netdev.h> -#include <asm/io.h> -#include <asm/processor.h> - -int checkboard(void) -{ - puts("BOARD: Renesas MigoR\n"); - return 0; -} - -int board_init(void) -{ - return 0; -} - -void led_set_state (unsigned short value) -{ -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(struct bd_info *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif diff --git a/board/renesas/r7780mp/Kconfig b/board/renesas/r7780mp/Kconfig deleted file mode 100644 index 050cc4cc0f..0000000000 --- a/board/renesas/r7780mp/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_R7780MP - -config SYS_BOARD - default "r7780mp" - -config SYS_VENDOR - default "renesas" - -config SYS_CONFIG_NAME - default "r7780mp" - -endif diff --git a/board/renesas/r7780mp/MAINTAINERS b/board/renesas/r7780mp/MAINTAINERS deleted file mode 100644 index 56ec21fd32..0000000000 --- a/board/renesas/r7780mp/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -R7780MP BOARD -M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> -M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> -S: Maintained -F: board/renesas/r7780mp/ -F: include/configs/r7780mp.h -F: configs/r7780mp_defconfig diff --git a/board/renesas/r7780mp/Makefile b/board/renesas/r7780mp/Makefile deleted file mode 100644 index 0a387db35d..0000000000 --- a/board/renesas/r7780mp/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007,2008 Nobuhiro Iwamatsu -# -# board/r7780mp/Makefile -# - -obj-y := r7780mp.o -extra-y += lowlevel_init.o diff --git a/board/renesas/r7780mp/lowlevel_init.S b/board/renesas/r7780mp/lowlevel_init.S deleted file mode 100644 index 7be1a1bf07..0000000000 --- a/board/renesas/r7780mp/lowlevel_init.S +++ /dev/null @@ -1,356 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2007,2008 Nobuhiro Iwamatsu - * - * u-boot/board/r7780mp/lowlevel_init.S - */ - -#include <config.h> -#include <asm/processor.h> -#include <asm/macro.h> - -/* - * Board specific low level init code, called _very_ early in the - * startup sequence. Relocation to SDRAM has not happened yet, no - * stack is available, bss section has not been initialised, etc. - * - * (Note: As no stack is available, no subroutines can be called...). - */ - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - - write32 CCR_A, CCR_D /* Address of Cache Control Register */ - /* Instruction Cache Invalidate */ - - write32 FRQCR_A, FRQCR_D /* Frequency control register */ - - /* pin_multi_setting */ - write32 BBG_PMMR_A, BBG_PMMR_D_PMSR1 - - write32 BBG_PMSR1_A, BBG_PMSR1_D - - write32 BBG_PMMR_A, BBG_PMMR_D_PMSR2 - - write32 BBG_PMSR2_A, BBG_PMSR2_D - - write32 BBG_PMMR_A, BBG_PMMR_D_PMSR3 - - write32 BBG_PMSR3_A, BBG_PMSR3_D - - write32 BBG_PMMR_A, BBG_PMMR_D_PMSR4 - - write32 BBG_PMSR4_A, BBG_PMSR4_D - - write32 BBG_PMMR_A, BBG_PMMR_D_PMSRG - - write32 BBG_PMSRG_A, BBG_PMSRG_D - - /* cpg_setting */ - write32 FRQCR_A, FRQCR_D - - write32 DLLCSR_A, DLLCSR_D - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - - /* wait 200us */ - mov.l REPEAT0_R3, r3 - mov #0, r2 -repeat0: - add #1, r2 - cmp/hs r3, r2 - bf repeat0 - nop - - /* bsc_setting */ - write32 MMSELR_A, MMSELR_D - - write32 BCR_A, BCR_D - - write32 CS0BCR_A, CS0BCR_D - - write32 CS1BCR_A, CS1BCR_D - - write32 CS2BCR_A, CS2BCR_D - - write32 CS4BCR_A, CS4BCR_D - - write32 CS5BCR_A, CS5BCR_D - - write32 CS6BCR_A, CS6BCR_D - - write32 CS0WCR_A, CS0WCR_D - - write32 CS1WCR_A, CS1WCR_D - - write32 CS2WCR_A, CS2WCR_D - - write32 CS4WCR_A, CS4WCR_D - - write32 CS5WCR_A, CS5WCR_D - - write32 CS6WCR_A, CS6WCR_D - - write32 CS5PCR_A, CS5PCR_D - - write32 CS6PCR_A, CS6PCR_D - - /* ddr_setting */ - /* wait 200us */ - mov.l REPEAT0_R3, r3 - mov #0, r2 -repeat1: - add #1, r2 - cmp/hs r3, r2 - bf repeat1 - nop - - mov.l MIM_U_A, r0 - mov.l MIM_U_D, r1 - synco - mov.l r1, @r0 - synco - - mov.l MIM_L_A, r0 - mov.l MIM_L_D0, r1 - synco - mov.l r1, @r0 - synco - - mov.l STR_L_A, r0 - mov.l STR_L_D, r1 - synco - mov.l r1, @r0 - synco - - mov.l SDR_L_A, r0 - mov.l SDR_L_D, r1 - synco - mov.l r1, @r0 - synco - - nop - nop - nop - nop - - mov.l SCR_L_A, r0 - mov.l SCR_L_D0, r1 - synco - mov.l r1, @r0 - synco - - mov.l SCR_L_A, r0 - mov.l SCR_L_D1, r1 - synco - mov.l r1, @r0 - synco - - nop - nop - nop - - mov.l EMRS_A, r0 - mov.l EMRS_D, r1 - synco - mov.l r1, @r0 - synco - - nop - nop - nop - - mov.l MRS1_A, r0 - mov.l MRS1_D, r1 - synco - mov.l r1, @r0 - synco - - nop - nop - nop - - mov.l SCR_L_A, r0 - mov.l SCR_L_D2, r1 - synco - mov.l r1, @r0 - synco - - nop - nop - nop - - mov.l SCR_L_A, r0 - mov.l SCR_L_D3, r1 - synco - mov.l r1, @r0 - synco - - nop - nop - nop - - mov.l SCR_L_A, r0 - mov.l SCR_L_D4, r1 - synco - mov.l r1, @r0 - synco - - nop - nop - nop - - mov.l MRS2_A, r0 - mov.l MRS2_D, r1 - synco - mov.l r1, @r0 - synco - - nop - nop - nop - - mov.l SCR_L_A, r0 - mov.l SCR_L_D5, r1 - synco - mov.l r1, @r0 - synco - - /* wait 200us */ - mov.l REPEAT0_R1, r3 - mov #0, r2 -repeat2: - add #1, r2 - cmp/hs r3, r2 - bf repeat2 - - synco - - mov.l MIM_L_A, r0 - mov.l MIM_L_D1, r1 - synco - mov.l r1, @r0 - synco - - rts - nop - .align 4 - -RWTCSR_D_1: .word 0xA507 -RWTCSR_D_2: .word 0xA507 -RWTCNT_D: .word 0x5A00 - .align 2 - -BBG_PMMR_A: .long 0xFF800010 -BBG_PMSR1_A: .long 0xFF800014 -BBG_PMSR2_A: .long 0xFF800018 -BBG_PMSR3_A: .long 0xFF80001C -BBG_PMSR4_A: .long 0xFF800020 -BBG_PMSRG_A: .long 0xFF800024 - -BBG_PMMR_D_PMSR1: .long 0xffffbffd -BBG_PMSR1_D: .long 0x00004002 -BBG_PMMR_D_PMSR2: .long 0xfc21a7ff -BBG_PMSR2_D: .long 0x03de5800 -BBG_PMMR_D_PMSR3: .long 0xfffffff8 -BBG_PMSR3_D: .long 0x00000007 -BBG_PMMR_D_PMSR4: .long 0xdffdfff9 -BBG_PMSR4_D: .long 0x20020006 -BBG_PMMR_D_PMSRG: .long 0xffffffff -BBG_PMSRG_D: .long 0x00000000 - -FRQCR_A: .long FRQCR -DLLCSR_A: .long 0xffc40010 -FRQCR_D: .long 0x40233035 -DLLCSR_D: .long 0x00000000 - -/* for DDR-SDRAM */ -MIM_U_A: .long MIM_1 -MIM_L_A: .long MIM_2 -SCR_U_A: .long SCR_1 -SCR_L_A: .long SCR_2 -STR_U_A: .long STR_1 -STR_L_A: .long STR_2 -SDR_U_A: .long SDR_1 -SDR_L_A: .long SDR_2 - -EMRS_A: .long 0xFEC02000 -MRS1_A: .long 0xFEC00B08 -MRS2_A: .long 0xFEC00308 - -MIM_U_D: .long 0x00004000 -MIM_L_D0: .long 0x03e80009 -MIM_L_D1: .long 0x03e80209 -SCR_L_D0: .long 0x3 -SCR_L_D1: .long 0x2 -SCR_L_D2: .long 0x2 -SCR_L_D3: .long 0x4 -SCR_L_D4: .long 0x4 -SCR_L_D5: .long 0x0 -STR_L_D: .long 0x000f0000 -SDR_L_D: .long 0x00000400 -EMRS_D: .long 0x0 -MRS1_D: .long 0x0 -MRS2_D: .long 0x0 - -/* Cache Controller */ -CCR_A: .long CCR -MMUCR_A: .long MMUCR -RWTCNT_A: .long WTCNT - -CCR_D: .long 0x0000090b -CCR_D_2: .long 0x00000103 -MMUCR_D: .long 0x00000004 -MSTPCR0_D: .long 0x00001001 -MSTPCR2_D: .long 0xffffffff - -/* local Bus State Controller */ -MMSELR_A: .long MMSELR -BCR_A: .long BCR -CS0BCR_A: .long CS0BCR -CS1BCR_A: .long CS1BCR -CS2BCR_A: .long CS2BCR -CS4BCR_A: .long CS4BCR -CS5BCR_A: .long CS5BCR -CS6BCR_A: .long CS6BCR -CS0WCR_A: .long CS0WCR -CS1WCR_A: .long CS1WCR -CS2WCR_A: .long CS2WCR -CS4WCR_A: .long CS4WCR -CS5WCR_A: .long CS5WCR -CS6WCR_A: .long CS6WCR -CS5PCR_A: .long CS5PCR -CS6PCR_A: .long CS6PCR - -MMSELR_D: .long 0xA5A50003 -BCR_D: .long 0x00000000 -CS0BCR_D: .long 0x77777770 -CS1BCR_D: .long 0x77777670 -CS2BCR_D: .long 0x77777770 -CS4BCR_D: .long 0x77777770 -CS5BCR_D: .long 0x77777670 -CS6BCR_D: .long 0x77777770 -CS0WCR_D: .long 0x00020006 -CS1WCR_D: .long 0x00232304 -CS2WCR_D: .long 0x7777770F -CS4WCR_D: .long 0x7777770F -CS5WCR_D: .long 0x00101006 -CS6WCR_D: .long 0x77777703 -CS5PCR_D: .long 0x77000000 -CS6PCR_D: .long 0x77000000 - -REPEAT0_R3: .long 0x00002000 -REPEAT0_R1: .long 0x0000200 diff --git a/board/renesas/r7780mp/r7780mp.c b/board/renesas/r7780mp/r7780mp.c deleted file mode 100644 index 422381ca78..0000000000 --- a/board/renesas/r7780mp/r7780mp.c +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com> - */ - -#include <common.h> -#include <ide.h> -#include <init.h> -#include <net.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/pci.h> -#include <netdev.h> -#include "r7780mp.h" - -int checkboard(void) -{ -#if defined(CONFIG_R7780MP) - puts("BOARD: Renesas Solutions R7780MP\n"); -#else - puts("BOARD: Renesas Solutions R7780RP\n"); -#endif - return 0; -} - -int board_init(void) -{ - /* SCIF Enable */ - writew(0x0, PHCR); - - return 0; -} - -void led_set_state(unsigned short value) -{ - -} - -void ide_set_reset(int idereset) -{ - /* if reset = 1 IDE reset will be asserted */ - if (idereset) { - writew(0x432, FPGA_CFCTL); -#if defined(CONFIG_R7780MP) - writew(inw(FPGA_CFPOW)|0x01, FPGA_CFPOW); -#else - writew(inw(FPGA_CFPOW)|0x02, FPGA_CFPOW); -#endif - writew(0x01, FPGA_CFCDINTCLR); - } -} - -static struct pci_controller hose; -void pci_init_board(void) -{ - pci_sh7780_init(&hose); -} - -int board_eth_init(struct bd_info *bis) -{ - /* return >= 0 if a chip is found, the board's AX88796L is n2k-based */ - return ne2k_register() + pci_eth_init(bis); -} diff --git a/board/renesas/r7780mp/r7780mp.h b/board/renesas/r7780mp/r7780mp.h deleted file mode 100644 index cce66bc4d2..0000000000 --- a/board/renesas/r7780mp/r7780mp.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2007 Nobuhiro Iwamatsu - * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com> - * - * u-boot/board/r7780mp/r7780mp.h - */ - -#ifndef _BOARD_R7780MP_R7780MP_H_ -#define _BOARD_R7780MP_R7780MP_H_ - -/* R7780MP's FPGA register map */ -#define FPGA_BASE 0xa4000000 -#define FPGA_IRLMSK (FPGA_BASE + 0x00) -#define FPGA_IRLMON (FPGA_BASE + 0x02) -#define FPGA_IRLPRI1 (FPGA_BASE + 0x04) -#define FPGA_IRLPRI2 (FPGA_BASE + 0x06) -#define FPGA_IRLPRI3 (FPGA_BASE + 0x08) -#define FPGA_IRLPRI4 (FPGA_BASE + 0x0A) -#define FPGA_RSTCTL (FPGA_BASE + 0x0C) -#define FPGA_PCIBD (FPGA_BASE + 0x0E) -#define FPGA_PCICD (FPGA_BASE + 0x10) -#define FPGA_EXTGIO (FPGA_BASE + 0x16) -#define FPGA_IVDRMON (FPGA_BASE + 0x18) -#define FPGA_IVDRCR (FPGA_BASE + 0x1A) -#define FPGA_OBLED (FPGA_BASE + 0x1C) -#define FPGA_OBSW (FPGA_BASE + 0x1E) -#define FPGA_TPCTL (FPGA_BASE + 0x100) -#define FPGA_TPDCKCTL (FPGA_BASE + 0x102) -#define FPGA_TPCLR (FPGA_BASE + 0x104) -#define FPGA_TPXPOS (FPGA_BASE + 0x106) -#define FPGA_TPYPOS (FPGA_BASE + 0x108) -#define FPGA_DBSW (FPGA_BASE + 0x200) -#define FPGA_VERSION (FPGA_BASE + 0x700) -#define FPGA_CFCTL (FPGA_BASE + 0x300) -#define FPGA_CFPOW (FPGA_BASE + 0x302) -#define FPGA_CFCDINTCLR (FPGA_BASE + 0x304) -#define FPGA_PMR (FPGA_BASE + 0x900) - -#endif /* _BOARD_R7780RP_R7780RP_H_ */ diff --git a/board/renesas/sh7752evb/Kconfig b/board/renesas/sh7752evb/Kconfig deleted file mode 100644 index 7f40888336..0000000000 --- a/board/renesas/sh7752evb/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_SH7752EVB - -config SYS_BOARD - default "sh7752evb" - -config SYS_VENDOR - default "renesas" - -config SYS_CONFIG_NAME - default "sh7752evb" - -endif diff --git a/board/renesas/sh7752evb/MAINTAINERS b/board/renesas/sh7752evb/MAINTAINERS deleted file mode 100644 index 9840477d7d..0000000000 --- a/board/renesas/sh7752evb/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -SH7752EVB BOARD -#M: - -S: Maintained -F: board/renesas/sh7752evb/ -F: include/configs/sh7752evb.h -F: configs/sh7752evb_defconfig diff --git a/board/renesas/sh7752evb/Makefile b/board/renesas/sh7752evb/Makefile deleted file mode 100644 index 658dc3bc6d..0000000000 --- a/board/renesas/sh7752evb/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2012 Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> -# - -obj-y := sh7752evb.o spi-boot.o -extra-y += lowlevel_init.o diff --git a/board/renesas/sh7752evb/lowlevel_init.S b/board/renesas/sh7752evb/lowlevel_init.S deleted file mode 100644 index 0f7b643ad8..0000000000 --- a/board/renesas/sh7752evb/lowlevel_init.S +++ /dev/null @@ -1,445 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 Renesas Solutions Corp. - */ - -#include <config.h> -#include <asm/processor.h> -#include <asm/macro.h> - -.macro or32, addr, data - mov.l \addr, r1 - mov.l \data, r0 - mov.l @r1, r2 - or r2, r0 - mov.l r0, @r1 -.endm - -.macro wait_DBCMD - mov.l DBWAIT_A, r0 - mov.l @r0, r1 -.endm - - .global lowlevel_init - .section .spiboot1.text - .align 2 - -lowlevel_init: - /*------- GPIO -------*/ - write16 PDCR_A, PDCR_D ! SPI0 - write16 PGCR_A, PGCR_D ! SPI0, GETHER MDIO gate(PTG1) - write16 PJCR_A, PJCR_D ! SCIF4 - write16 PTCR_A, PTCR_D ! STATUS - write16 PSEL1_A, PSEL1_D ! SPI0 - write16 PSEL2_A, PSEL2_D ! SPI0 - write16 PSEL5_A, PSEL5_D ! STATUS - - bra exit_gpio - nop - - .align 2 - -/*------- GPIO -------*/ -PDCR_A: .long 0xffec0006 -PGCR_A: .long 0xffec000c -PJCR_A: .long 0xffec0012 -PTCR_A: .long 0xffec0026 -PSEL1_A: .long 0xffec0072 -PSEL2_A: .long 0xffec0074 -PSEL5_A: .long 0xffec007a - -PDCR_D: .long 0x0000 -PGCR_D: .long 0x0004 -PJCR_D: .long 0x0000 -PTCR_D: .long 0x0000 -PSEL1_D: .long 0x0000 -PSEL2_D: .long 0x3000 -PSEL5_D: .long 0x0ffc - - .align 2 - -exit_gpio: - mov #0, r14 - mova 2f, r0 - mov.l PC_MASK, r1 - tst r0, r1 - bf 2f - - bra exit_pmb - nop - - .align 2 - -/* If CPU runs on SDRAM (PC=0x5???????) or not. */ -PC_MASK: .long 0x20000000 - -2: - mov #1, r14 - - mov.l EXPEVT_A, r0 - mov.l @r0, r0 - mov.l EXPEVT_POWER_ON_RESET, r1 - cmp/eq r0, r1 - bt 1f - - /* - * If EXPEVT value is manual reset or tlb multipul-hit, - * initialization of DDR3IF is not necessary. - */ - bra exit_ddr - nop - -1: - /*------- Reset -------*/ - write32 MRSTCR0_A, MRSTCR0_D - write32 MRSTCR1_A, MRSTCR1_D - - /* For Core Reset */ - mov.l DBACEN_A, r0 - mov.l @r0, r0 - cmp/eq #0, r0 - bt 3f - - /* - * If DBACEN == 1(DBSC was already enabled), we have to avoid the - * initialization of DDR3-SDRAM. - */ - bra exit_ddr - nop - -3: - /*------- DDR3IF -------*/ - /* oscillation stabilization time */ - wait_timer WAIT_OSC_TIME - - /* step 3 */ - write32 DBCMD_A, DBCMD_RSTL_VAL - wait_timer WAIT_30US - - /* step 4 */ - write32 DBCMD_A, DBCMD_PDEN_VAL - - /* step 5 */ - write32 DBKIND_A, DBKIND_D - - /* step 6 */ - write32 DBCONF_A, DBCONF_D - write32 DBTR0_A, DBTR0_D - write32 DBTR1_A, DBTR1_D - write32 DBTR2_A, DBTR2_D - write32 DBTR3_A, DBTR3_D - write32 DBTR4_A, DBTR4_D - write32 DBTR5_A, DBTR5_D - write32 DBTR6_A, DBTR6_D - write32 DBTR7_A, DBTR7_D - write32 DBTR8_A, DBTR8_D - write32 DBTR9_A, DBTR9_D - write32 DBTR10_A, DBTR10_D - write32 DBTR11_A, DBTR11_D - write32 DBTR12_A, DBTR12_D - write32 DBTR13_A, DBTR13_D - write32 DBTR14_A, DBTR14_D - write32 DBTR15_A, DBTR15_D - write32 DBTR16_A, DBTR16_D - write32 DBTR17_A, DBTR17_D - write32 DBTR18_A, DBTR18_D - write32 DBTR19_A, DBTR19_D - write32 DBRNK0_A, DBRNK0_D - - /* step 7 */ - write32 DBPDCNT3_A, DBPDCNT3_D - - /* step 8 */ - write32 DBPDCNT1_A, DBPDCNT1_D - write32 DBPDCNT2_A, DBPDCNT2_D - write32 DBPDLCK_A, DBPDLCK_D - write32 DBPDRGA_A, DBPDRGA_D - write32 DBPDRGD_A, DBPDRGD_D - - /* step 9 */ - wait_timer WAIT_30US - - /* step 10 */ - write32 DBPDCNT0_A, DBPDCNT0_D - - /* step 11 */ - wait_timer WAIT_30US - wait_timer WAIT_30US - - /* step 12 */ - write32 DBCMD_A, DBCMD_WAIT_VAL - wait_DBCMD - - /* step 13 */ - write32 DBCMD_A, DBCMD_RSTH_VAL - wait_DBCMD - - /* step 14 */ - write32 DBCMD_A, DBCMD_WAIT_VAL - write32 DBCMD_A, DBCMD_WAIT_VAL - write32 DBCMD_A, DBCMD_WAIT_VAL - write32 DBCMD_A, DBCMD_WAIT_VAL - - /* step 15 */ - write32 DBCMD_A, DBCMD_PDXT_VAL - - /* step 16 */ - write32 DBCMD_A, DBCMD_MRS2_VAL - - /* step 17 */ - write32 DBCMD_A, DBCMD_MRS3_VAL - - /* step 18 */ - write32 DBCMD_A, DBCMD_MRS1_VAL - - /* step 19 */ - write32 DBCMD_A, DBCMD_MRS0_VAL - - /* step 20 */ - write32 DBCMD_A, DBCMD_ZQCL_VAL - - write32 DBCMD_A, DBCMD_REF_VAL - write32 DBCMD_A, DBCMD_REF_VAL - wait_DBCMD - - /* step 21 */ - write32 DBADJ0_A, DBADJ0_D - write32 DBADJ1_A, DBADJ1_D - write32 DBADJ2_A, DBADJ2_D - - /* step 22 */ - write32 DBRFCNF0_A, DBRFCNF0_D - write32 DBRFCNF1_A, DBRFCNF1_D - write32 DBRFCNF2_A, DBRFCNF2_D - - /* step 23 */ - write32 DBCALCNF_A, DBCALCNF_D - - /* step 24 */ - write32 DBRFEN_A, DBRFEN_D - write32 DBCMD_A, DBCMD_SRXT_VAL - - /* step 25 */ - write32 DBACEN_A, DBACEN_D - - /* step 26 */ - wait_DBCMD - - bra exit_ddr - nop - - .align 2 - -EXPEVT_A: .long 0xff000024 -EXPEVT_POWER_ON_RESET: .long 0x00000000 - -/*------- Reset -------*/ -MRSTCR0_A: .long 0xffd50030 -MRSTCR0_D: .long 0xfe1ffe7f -MRSTCR1_A: .long 0xffd50034 -MRSTCR1_D: .long 0xfff3ffff - -/*------- DDR3IF -------*/ -DBCMD_A: .long 0xfe800018 -DBKIND_A: .long 0xfe800020 -DBCONF_A: .long 0xfe800024 -DBTR0_A: .long 0xfe800040 -DBTR1_A: .long 0xfe800044 -DBTR2_A: .long 0xfe800048 -DBTR3_A: .long 0xfe800050 -DBTR4_A: .long 0xfe800054 -DBTR5_A: .long 0xfe800058 -DBTR6_A: .long 0xfe80005c -DBTR7_A: .long 0xfe800060 -DBTR8_A: .long 0xfe800064 -DBTR9_A: .long 0xfe800068 -DBTR10_A: .long 0xfe80006c -DBTR11_A: .long 0xfe800070 -DBTR12_A: .long 0xfe800074 -DBTR13_A: .long 0xfe800078 -DBTR14_A: .long 0xfe80007c -DBTR15_A: .long 0xfe800080 -DBTR16_A: .long 0xfe800084 -DBTR17_A: .long 0xfe800088 -DBTR18_A: .long 0xfe80008c -DBTR19_A: .long 0xfe800090 -DBRNK0_A: .long 0xfe800100 -DBPDCNT0_A: .long 0xfe800200 -DBPDCNT1_A: .long 0xfe800204 -DBPDCNT2_A: .long 0xfe800208 -DBPDCNT3_A: .long 0xfe80020c -DBPDLCK_A: .long 0xfe800280 -DBPDRGA_A: .long 0xfe800290 -DBPDRGD_A: .long 0xfe8002a0 -DBADJ0_A: .long 0xfe8000c0 -DBADJ1_A: .long 0xfe8000c4 -DBADJ2_A: .long 0xfe8000c8 -DBRFCNF0_A: .long 0xfe8000e0 -DBRFCNF1_A: .long 0xfe8000e4 -DBRFCNF2_A: .long 0xfe8000e8 -DBCALCNF_A: .long 0xfe8000f4 -DBRFEN_A: .long 0xfe800014 -DBACEN_A: .long 0xfe800010 -DBWAIT_A: .long 0xfe80001c - -WAIT_OSC_TIME: .long 6000 -WAIT_30US: .long 13333 - -DBCMD_RSTL_VAL: .long 0x20000000 -DBCMD_PDEN_VAL: .long 0x1000d73c -DBCMD_WAIT_VAL: .long 0x0000d73c -DBCMD_RSTH_VAL: .long 0x2100d73c -DBCMD_PDXT_VAL: .long 0x110000c8 -DBCMD_MRS0_VAL: .long 0x28000930 -DBCMD_MRS1_VAL: .long 0x29000004 -DBCMD_MRS2_VAL: .long 0x2a000008 -DBCMD_MRS3_VAL: .long 0x2b000000 -DBCMD_ZQCL_VAL: .long 0x03000200 -DBCMD_REF_VAL: .long 0x0c000000 -DBCMD_SRXT_VAL: .long 0x19000000 -DBKIND_D: .long 0x00000007 -DBCONF_D: .long 0x0f030a01 -DBTR0_D: .long 0x00000007 -DBTR1_D: .long 0x00000006 -DBTR2_D: .long 0x00000000 -DBTR3_D: .long 0x00000007 -DBTR4_D: .long 0x00070007 -DBTR5_D: .long 0x0000001b -DBTR6_D: .long 0x00000014 -DBTR7_D: .long 0x00000005 -DBTR8_D: .long 0x00000015 -DBTR9_D: .long 0x00000006 -DBTR10_D: .long 0x00000008 -DBTR11_D: .long 0x00000007 -DBTR12_D: .long 0x0000000e -DBTR13_D: .long 0x00000056 -DBTR14_D: .long 0x00000006 -DBTR15_D: .long 0x00000004 -DBTR16_D: .long 0x00150002 -DBTR17_D: .long 0x000c0017 -DBTR18_D: .long 0x00000200 -DBTR19_D: .long 0x00000040 -DBRNK0_D: .long 0x00000001 -DBPDCNT0_D: .long 0x00000001 -DBPDCNT1_D: .long 0x00000001 -DBPDCNT2_D: .long 0x00000000 -DBPDCNT3_D: .long 0x00004010 -DBPDLCK_D: .long 0x0000a55a -DBPDRGA_D: .long 0x00000028 -DBPDRGD_D: .long 0x00017100 - -DBADJ0_D: .long 0x00000000 -DBADJ1_D: .long 0x00000000 -DBADJ2_D: .long 0x18061806 -DBRFCNF0_D: .long 0x000001ff -DBRFCNF1_D: .long 0x08001000 -DBRFCNF2_D: .long 0x00000000 -DBCALCNF_D: .long 0x0000ffff -DBRFEN_D: .long 0x00000001 -DBACEN_D: .long 0x00000001 - - .align 2 -exit_ddr: -#if defined(CONFIG_SH_32BIT) - /*------- set PMB -------*/ - write32 PASCR_A, PASCR_29BIT_D - write32 MMUCR_A, MMUCR_D - - /***************************************************************** - * ent virt phys v sz c wt - * 0 0xa0000000 0x00000000 1 128M 0 1 - * 1 0xa8000000 0x48000000 1 128M 0 1 - * 5 0x88000000 0x48000000 1 128M 1 1 - */ - write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D - write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D - write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D - write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D - write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D - write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D - - write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D - - write32 PASCR_A, PASCR_INIT - mov.l DUMMY_ADDR, r0 - icbi @r0 -#endif /* if defined(CONFIG_SH_32BIT) */ - -exit_pmb: - /* CPU is running on ILRAM? */ - mov r14, r0 - tst #1, r0 - bt 1f - - mov.l _stack_ilram, r15 - mov.l _spiboot_main, r0 -100: bsrf r0 - nop - - .align 2 -_spiboot_main: .long (spiboot_main - (100b + 4)) -_stack_ilram: .long 0xe5204000 - -1: - write32 CCR_A, CCR_D - - rts - nop - - .align 2 - -#if defined(CONFIG_SH_32BIT) -/*------- set PMB -------*/ -PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0) -PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1) -PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5) -PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2) -PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3) -PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4) -PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6) -PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7) -PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8) -PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9) -PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10) -PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11) -PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12) -PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13) -PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14) -PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15) - -PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0) -PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88) -PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8) -PMB_ADDR_NOT_USE_D: .long 0x00000000 - -PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0) -PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1) -PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5) - -/* ppn ub v s1 s0 c wt */ -PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1) -PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1) -PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1) - -PASCR_A: .long 0xff000070 -DUMMY_ADDR: .long 0xa0000000 -PASCR_29BIT_D: .long 0x00000000 -PASCR_INIT: .long 0x80000080 -MMUCR_A: .long 0xff000010 -MMUCR_D: .long 0x00000004 /* clear ITLB */ -#endif /* CONFIG_SH_32BIT */ - -CCR_A: .long CCR -CCR_D: .long CCR_CACHE_INIT diff --git a/board/renesas/sh7752evb/sh7752evb.c b/board/renesas/sh7752evb/sh7752evb.c deleted file mode 100644 index 522b4bd610..0000000000 --- a/board/renesas/sh7752evb/sh7752evb.c +++ /dev/null @@ -1,313 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012 Renesas Solutions Corp. - */ - -#include <common.h> -#include <command.h> -#include <env.h> -#include <flash.h> -#include <init.h> -#include <malloc.h> -#include <net.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/mmc.h> -#include <spi.h> -#include <spi_flash.h> -#include <linux/delay.h> - -int checkboard(void) -{ - puts("BOARD: SH7752 evaluation board (R0P7752C00000RZ)\n"); - - return 0; -} - -static void init_gpio(void) -{ - struct gpio_regs *gpio = GPIO_BASE; - struct sermux_regs *sermux = SERMUX_BASE; - - /* GPIO */ - writew(0x0000, &gpio->pacr); /* GETHER */ - writew(0x0001, &gpio->pbcr); /* INTC */ - writew(0x0000, &gpio->pccr); /* PWMU, INTC */ - writew(0xeaff, &gpio->pecr); /* GPIO */ - writew(0x0000, &gpio->pfcr); /* WDT */ - writew(0x0000, &gpio->phcr); /* SPI1 */ - writew(0x0000, &gpio->picr); /* SDHI */ - writew(0x0003, &gpio->pkcr); /* SerMux */ - writew(0x0000, &gpio->plcr); /* SerMux */ - writew(0x0000, &gpio->pmcr); /* RIIC */ - writew(0x0000, &gpio->pncr); /* USB, SGPIO */ - writew(0x0000, &gpio->pocr); /* SGPIO */ - writew(0xd555, &gpio->pqcr); /* GPIO */ - writew(0x0000, &gpio->prcr); /* RIIC */ - writew(0x0000, &gpio->pscr); /* RIIC */ - writeb(0x00, &gpio->pudr); - writew(0x5555, &gpio->pucr); /* Debug LED */ - writew(0x0000, &gpio->pvcr); /* RSPI */ - writew(0x0000, &gpio->pwcr); /* EVC */ - writew(0x0000, &gpio->pxcr); /* LBSC */ - writew(0x0000, &gpio->pycr); /* LBSC */ - writew(0x0000, &gpio->pzcr); /* eMMC */ - writew(0xfe00, &gpio->psel0); - writew(0xff00, &gpio->psel3); - writew(0x771f, &gpio->psel4); - writew(0x00ff, &gpio->psel6); - writew(0xfc00, &gpio->psel7); - - writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */ -} - -static void init_usb_phy(void) -{ - struct usb_common_regs *common0 = USB0_COMMON_BASE; - struct usb_common_regs *common1 = USB1_COMMON_BASE; - struct usb0_phy_regs *phy = USB0_PHY_BASE; - struct usb1_port_regs *port = USB1_PORT_BASE; - struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE; - - writew(0x0100, &phy->reset); /* set reset */ - /* port0 = USB0, port1 = USB1 */ - writew(0x0002, &phy->portsel); - writel(0x0001, &port->port1sel); /* port1 = Host */ - writew(0x0111, &phy->reset); /* clear reset */ - - writew(0x4000, &common0->suspmode); - writew(0x4000, &common1->suspmode); - -#if defined(__LITTLE_ENDIAN) - writel(0x00000000, &align->ehcidatac); - writel(0x00000000, &align->ohcidatac); -#endif -} - -static void init_gether_mdio(void) -{ - struct gpio_regs *gpio = GPIO_BASE; - - writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr); - writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */ -} - -static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string) -{ - struct ether_mac_regs *ether; - unsigned char mac[6]; - unsigned long val; - - string_to_enetaddr(mac_string, mac); - - if (!channel) - ether = GETHER0_MAC_BASE; - else - ether = GETHER1_MAC_BASE; - - val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3]; - writel(val, ðer->mahr); - val = (mac[4] << 8) | mac[5]; - writel(val, ðer->malr); -} - -/***************************************************************** - * This PMB must be set on this timing. The lowlevel_init is run on - * Area 0(phys 0x00000000), so we have to map it. - * - * The new PMB table is following: - * ent virt phys v sz c wt - * 0 0xa0000000 0x40000000 1 128M 0 1 - * 1 0xa8000000 0x48000000 1 128M 0 1 - * 2 0xb0000000 0x50000000 1 128M 0 1 - * 3 0xb8000000 0x58000000 1 128M 0 1 - * 4 0x80000000 0x40000000 1 128M 1 1 - * 5 0x88000000 0x48000000 1 128M 1 1 - * 6 0x90000000 0x50000000 1 128M 1 1 - * 7 0x98000000 0x58000000 1 128M 1 1 - */ -static void set_pmb_on_board_init(void) -{ - struct mmu_regs *mmu = MMU_BASE; - - /* clear ITLB */ - writel(0x00000004, &mmu->mmucr); - - /* delete PMB for SPIBOOT */ - writel(0, PMB_ADDR_BASE(0)); - writel(0, PMB_DATA_BASE(0)); - - /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */ - /* ppn ub v s1 s0 c wt */ - writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0)); - writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0)); - writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2)); - writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2)); - writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3)); - writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3)); - writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4)); - writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4)); - writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6)); - writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6)); - writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7)); - writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7)); -} - -int board_init(void) -{ - init_gpio(); - set_pmb_on_board_init(); - - init_usb_phy(); - init_gether_mdio(); - - return 0; -} - -int board_mmc_init(struct bd_info *bis) -{ - struct gpio_regs *gpio = GPIO_BASE; - - writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr); - writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */ - udelay(1); - writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */ - udelay(200); - - return mmcif_mmc_init(); -} - -static int get_sh_eth_mac_raw(unsigned char *buf, int size) -{ -#ifdef CONFIG_DEPRECATED - struct spi_flash *spi; - int ret; - - spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); - if (spi == NULL) { - printf("%s: spi_flash probe failed.\n", __func__); - return 1; - } - - ret = spi_flash_read(spi, SH7752EVB_ETHERNET_MAC_BASE, size, buf); - if (ret) { - printf("%s: spi_flash read failed.\n", __func__); - spi_flash_free(spi); - return 1; - } - spi_flash_free(spi); -#endif - - return 0; -} - -static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf) -{ - memcpy(mac_string, &buf[channel * (SH7752EVB_ETHERNET_MAC_SIZE + 1)], - SH7752EVB_ETHERNET_MAC_SIZE); - mac_string[SH7752EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */ - - return 0; -} - -static void init_ethernet_mac(void) -{ - char mac_string[64]; - char env_string[64]; - int i; - unsigned char *buf; - - buf = malloc(256); - if (!buf) { - printf("%s: malloc failed.\n", __func__); - return; - } - get_sh_eth_mac_raw(buf, 256); - - /* Gigabit Ethernet */ - for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) { - get_sh_eth_mac(i, mac_string, buf); - if (i == 0) - env_set("ethaddr", mac_string); - else { - sprintf(env_string, "eth%daddr", i); - env_set(env_string, mac_string); - } - set_mac_to_sh_giga_eth_register(i, mac_string); - } - - free(buf); -} - -int board_late_init(void) -{ - init_ethernet_mac(); - - return 0; -} - -#ifdef CONFIG_DEPRECATED -int do_write_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - int i, ret; - char mac_string[256]; - struct spi_flash *spi; - unsigned char *buf; - - if (argc != 3) { - buf = malloc(256); - if (!buf) { - printf("%s: malloc failed.\n", __func__); - return 1; - } - - get_sh_eth_mac_raw(buf, 256); - - /* print current MAC address */ - for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) { - get_sh_eth_mac(i, mac_string, buf); - printf("GETHERC ch%d = %s\n", i, mac_string); - } - free(buf); - return 0; - } - - /* new setting */ - memset(mac_string, 0xff, sizeof(mac_string)); - sprintf(mac_string, "%s\t%s", - argv[1], argv[2]); - - /* write MAC data to SPI rom */ - spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); - if (!spi) { - printf("%s: spi_flash probe failed.\n", __func__); - return 1; - } - - ret = spi_flash_erase(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI, - SH7752EVB_SPI_SECTOR_SIZE); - if (ret) { - printf("%s: spi_flash erase failed.\n", __func__); - return 1; - } - - ret = spi_flash_write(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI, - sizeof(mac_string), mac_string); - if (ret) { - printf("%s: spi_flash write failed.\n", __func__); - spi_flash_free(spi); - return 1; - } - spi_flash_free(spi); - - puts("The writing of the MAC address to SPI ROM was completed.\n"); - - return 0; -} - -U_BOOT_CMD( - write_mac, 3, 1, do_write_mac, - "write MAC address for GETHERC", - "[GETHERC ch0] [GETHERC ch1]\n" -); -#endif diff --git a/board/renesas/sh7752evb/spi-boot.c b/board/renesas/sh7752evb/spi-boot.c deleted file mode 100644 index 91565d44d7..0000000000 --- a/board/renesas/sh7752evb/spi-boot.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (C) 2012 Renesas Solutions Corp. - * - * This file is subject to the terms and conditions of the GNU Lesser - * General Public License. See the file "COPYING.LIB" in the main - * directory of this archive for more details. - */ - -#include <common.h> - -#define CONFIG_RAM_BOOT_PHYS CONFIG_SYS_TEXT_BASE -#define CONFIG_SPI_ADDR 0x00000000 -#define CONFIG_SPI_LENGTH CONFIG_SYS_MONITOR_LEN -#define CONFIG_RAM_BOOT CONFIG_SYS_TEXT_BASE - -#define SPIWDMADR 0xFE001018 -#define SPIWDMCNTR 0xFE001020 -#define SPIDMCOR 0xFE001028 -#define SPIDMINTSR 0xFE001188 -#define SPIDMINTMR 0xFE001190 - -#define SPIDMINTSR_DMEND 0x00000004 - -#define TBR 0xFE002000 -#define RBR 0xFE002000 - -#define CR1 0xFE002008 -#define CR2 0xFE002010 -#define CR3 0xFE002018 -#define CR4 0xFE002020 - -/* CR1 */ -#define SPI_TBE 0x80 -#define SPI_TBF 0x40 -#define SPI_RBE 0x20 -#define SPI_RBF 0x10 -#define SPI_PFONRD 0x08 -#define SPI_SSDB 0x04 -#define SPI_SSD 0x02 -#define SPI_SSA 0x01 - -/* CR2 */ -#define SPI_RSTF 0x80 -#define SPI_LOOPBK 0x40 -#define SPI_CPOL 0x20 -#define SPI_CPHA 0x10 -#define SPI_L1M0 0x08 - -/* CR4 */ -#define SPI_TBEI 0x80 -#define SPI_TBFI 0x40 -#define SPI_RBEI 0x20 -#define SPI_RBFI 0x10 -#define SPI_SpiS0 0x02 -#define SPI_SSS 0x01 - -#define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val -#define spi_read(addr) (*(volatile unsigned long *)(addr)) - -/* M25P80 */ -#define M25_READ 0x03 - -#define __uses_spiboot2 __attribute__((section(".spiboot2.text"))) -static void __uses_spiboot2 spi_reset(void) -{ - int timeout = 0x00100000; - - /* Make sure the last transaction is finalized */ - spi_write(0x00, CR3); - spi_write(0x02, CR1); - while (!(spi_read(CR4) & SPI_SpiS0)) { - if (timeout-- < 0) - break; - } - spi_write(0x00, CR1); - - spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */ - spi_write(spi_read(CR2) & ~SPI_RSTF, CR2); - - spi_write(0, SPIDMCOR); -} - -static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr, - unsigned long len) -{ - spi_write(M25_READ, TBR); - spi_write((addr >> 16) & 0xFF, TBR); - spi_write((addr >> 8) & 0xFF, TBR); - spi_write(addr & 0xFF, TBR); - - spi_write(SPIDMINTSR_DMEND, SPIDMINTSR); - spi_write((unsigned long)buf, SPIWDMADR); - spi_write(len & 0xFFFFFFE0, SPIWDMCNTR); - spi_write(1, SPIDMCOR); - - spi_write(0xff, CR3); - spi_write(spi_read(CR1) | SPI_SSDB, CR1); - spi_write(spi_read(CR1) | SPI_SSA, CR1); - - while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND)) - ; - - /* Nagate SP0-SS0 */ - spi_write(0, CR1); -} - -void __uses_spiboot2 spiboot_main(void) -{ - void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE; - - spi_reset(); - spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR, - CONFIG_SPI_LENGTH); - - _start(); -} diff --git a/board/renesas/sh7753evb/Kconfig b/board/renesas/sh7753evb/Kconfig deleted file mode 100644 index be889248a8..0000000000 --- a/board/renesas/sh7753evb/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_SH7753EVB - -config SYS_BOARD - default "sh7753evb" - -config SYS_VENDOR - default "renesas" - -config SYS_CONFIG_NAME - default "sh7753evb" - -endif diff --git a/board/renesas/sh7753evb/MAINTAINERS b/board/renesas/sh7753evb/MAINTAINERS deleted file mode 100644 index b6c85eedab..0000000000 --- a/board/renesas/sh7753evb/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -SH7753EVB BOARD -#M: - -S: Maintained -F: board/renesas/sh7753evb/ -F: include/configs/sh7753evb.h -F: configs/sh7753evb_defconfig diff --git a/board/renesas/sh7753evb/Makefile b/board/renesas/sh7753evb/Makefile deleted file mode 100644 index e1e099777c..0000000000 --- a/board/renesas/sh7753evb/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2012 Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> -# - -obj-y := sh7753evb.o spi-boot.o -extra-y += lowlevel_init.o diff --git a/board/renesas/sh7753evb/lowlevel_init.S b/board/renesas/sh7753evb/lowlevel_init.S deleted file mode 100644 index 901e9eb648..0000000000 --- a/board/renesas/sh7753evb/lowlevel_init.S +++ /dev/null @@ -1,414 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Renesas Solutions Corp. - */ - -#include <config.h> -#include <asm/processor.h> -#include <asm/macro.h> - -.macro or32, addr, data - mov.l \addr, r1 - mov.l \data, r0 - mov.l @r1, r2 - or r2, r0 - mov.l r0, @r1 -.endm - -.macro wait_DBCMD - mov.l DBWAIT_A, r0 - mov.l @r0, r1 -.endm - - .global lowlevel_init - .section .spiboot1.text - .align 2 - -lowlevel_init: - mov #0, r14 - mova 2f, r0 - mov.l PC_MASK, r1 - tst r0, r1 - bf 2f - - bra exit_pmb - nop - - .align 2 - -/* If CPU runs on SDRAM (PC=0x5???????) or not. */ -PC_MASK: .long 0x20000000 - -2: - mov #1, r14 - - mov.l EXPEVT_A, r0 - mov.l @r0, r0 - mov.l EXPEVT_POWER_ON_RESET, r1 - cmp/eq r0, r1 - bt 1f - - /* - * If EXPEVT value is manual reset or tlb multipul-hit, - * initialization of DBSC3 is not necessary. - */ - bra exit_ddr - nop - -1: - /*------- Reset -------*/ - write32 MRSTCR0_A, MRSTCR0_D - write32 MRSTCR1_A, MRSTCR1_D - - /* For Core Reset */ - mov.l DBACEN_A, r0 - mov.l @r0, r0 - cmp/eq #0, r0 - bt 3f - - /* - * If DBACEN == 1(DBSC was already enabled), we have to avoid the - * initialization of DDR3-SDRAM. - */ - bra exit_ddr - nop - -3: - /*------- DBSC3 -------*/ - /* oscillation stabilization time */ - wait_timer WAIT_OSC_TIME - - /* step 3 */ - write32 DBKIND_A, DBKIND_D - - /* step 4 */ - write32 DBCONF_A, DBCONF_D - write32 DBTR0_A, DBTR0_D - write32 DBTR1_A, DBTR1_D - write32 DBTR2_A, DBTR2_D - write32 DBTR3_A, DBTR3_D - write32 DBTR4_A, DBTR4_D - write32 DBTR5_A, DBTR5_D - write32 DBTR6_A, DBTR6_D - write32 DBTR7_A, DBTR7_D - write32 DBTR8_A, DBTR8_D - write32 DBTR9_A, DBTR9_D - write32 DBTR10_A, DBTR10_D - write32 DBTR11_A, DBTR11_D - write32 DBTR12_A, DBTR12_D - write32 DBTR13_A, DBTR13_D - write32 DBTR14_A, DBTR14_D - write32 DBTR15_A, DBTR15_D - write32 DBTR16_A, DBTR16_D - write32 DBTR17_A, DBTR17_D - write32 DBTR18_A, DBTR18_D - write32 DBTR19_A, DBTR19_D - write32 DBRNK0_A, DBRNK0_D - write32 DBADJ0_A, DBADJ0_D - write32 DBADJ2_A, DBADJ2_D - - /* step 5 */ - write32 DBCMD_A, DBCMD_RSTL_VAL - wait_timer WAIT_30US - - /* step 6 */ - write32 DBCMD_A, DBCMD_PDEN_VAL - - /* step 7 */ - write32 DBPDCNT3_A, DBPDCNT3_D - - /* step 8 */ - write32 DBPDCNT1_A, DBPDCNT1_D - write32 DBPDCNT2_A, DBPDCNT2_D - write32 DBPDLCK_A, DBPDLCK_D - write32 DBPDRGA_A, DBPDRGA_D - write32 DBPDRGD_A, DBPDRGD_D - - /* step 9 */ - wait_timer WAIT_30US - - /* step 10 */ - write32 DBPDCNT0_A, DBPDCNT0_D - - /* step 11 */ - wait_timer WAIT_30US - wait_timer WAIT_30US - - /* step 12 */ - write32 DBCMD_A, DBCMD_WAIT_VAL - wait_DBCMD - - /* step 13 */ - write32 DBCMD_A, DBCMD_RSTH_VAL - wait_DBCMD - - /* step 14 */ - write32 DBCMD_A, DBCMD_WAIT_VAL - write32 DBCMD_A, DBCMD_WAIT_VAL - write32 DBCMD_A, DBCMD_WAIT_VAL - write32 DBCMD_A, DBCMD_WAIT_VAL - - /* step 15 */ - write32 DBCMD_A, DBCMD_PDXT_VAL - - /* step 16 */ - write32 DBCMD_A, DBCMD_MRS2_VAL - - /* step 17 */ - write32 DBCMD_A, DBCMD_MRS3_VAL - - /* step 18 */ - write32 DBCMD_A, DBCMD_MRS1_VAL - - /* step 19 */ - write32 DBCMD_A, DBCMD_MRS0_VAL - write32 DBPDNCNF_A, DBPDNCNF_D - - /* step 20 */ - write32 DBCMD_A, DBCMD_ZQCL_VAL - - write32 DBCMD_A, DBCMD_REF_VAL - write32 DBCMD_A, DBCMD_REF_VAL - wait_DBCMD - - /* step 21 */ - write32 DBCALTR_A, DBCALTR_D - - /* step 22 */ - write32 DBRFCNF0_A, DBRFCNF0_D - write32 DBRFCNF1_A, DBRFCNF1_D - write32 DBRFCNF2_A, DBRFCNF2_D - - /* step 23 */ - write32 DBCALCNF_A, DBCALCNF_D - - /* step 24 */ - write32 DBRFEN_A, DBRFEN_D - write32 DBCMD_A, DBCMD_SRXT_VAL - - /* step 25 */ - write32 DBACEN_A, DBACEN_D - - /* step 26 */ - wait_DBCMD - - bra exit_ddr - nop - - .align 2 - -EXPEVT_A: .long 0xff000024 -EXPEVT_POWER_ON_RESET: .long 0x00000000 - -/*------- Reset -------*/ -MRSTCR0_A: .long 0xffd50030 -MRSTCR0_D: .long 0xfe1ffe7f -MRSTCR1_A: .long 0xffd50034 -MRSTCR1_D: .long 0xfff3ffff - -/*------- DBSC3 -------*/ -DBCMD_A: .long 0xfe800018 -DBKIND_A: .long 0xfe800020 -DBCONF_A: .long 0xfe800024 -DBTR0_A: .long 0xfe800040 -DBTR1_A: .long 0xfe800044 -DBTR2_A: .long 0xfe800048 -DBTR3_A: .long 0xfe800050 -DBTR4_A: .long 0xfe800054 -DBTR5_A: .long 0xfe800058 -DBTR6_A: .long 0xfe80005c -DBTR7_A: .long 0xfe800060 -DBTR8_A: .long 0xfe800064 -DBTR9_A: .long 0xfe800068 -DBTR10_A: .long 0xfe80006c -DBTR11_A: .long 0xfe800070 -DBTR12_A: .long 0xfe800074 -DBTR13_A: .long 0xfe800078 -DBTR14_A: .long 0xfe80007c -DBTR15_A: .long 0xfe800080 -DBTR16_A: .long 0xfe800084 -DBTR17_A: .long 0xfe800088 -DBTR18_A: .long 0xfe80008c -DBTR19_A: .long 0xfe800090 -DBRNK0_A: .long 0xfe800100 -DBPDCNT0_A: .long 0xfe800200 -DBPDCNT1_A: .long 0xfe800204 -DBPDCNT2_A: .long 0xfe800208 -DBPDCNT3_A: .long 0xfe80020c -DBPDLCK_A: .long 0xfe800280 -DBPDRGA_A: .long 0xfe800290 -DBPDRGD_A: .long 0xfe8002a0 -DBADJ0_A: .long 0xfe8000c0 -DBADJ2_A: .long 0xfe8000c8 -DBRFCNF0_A: .long 0xfe8000e0 -DBRFCNF1_A: .long 0xfe8000e4 -DBRFCNF2_A: .long 0xfe8000e8 -DBCALCNF_A: .long 0xfe8000f4 -DBRFEN_A: .long 0xfe800014 -DBACEN_A: .long 0xfe800010 -DBWAIT_A: .long 0xfe80001c -DBCALTR_A: .long 0xfe8000f8 -DBPDNCNF_A: .long 0xfe800180 - -WAIT_OSC_TIME: .long 6000 -WAIT_30US: .long 13333 - -DBCMD_RSTL_VAL: .long 0x20000000 -DBCMD_PDEN_VAL: .long 0x1000d73c -DBCMD_WAIT_VAL: .long 0x0000d73c -DBCMD_RSTH_VAL: .long 0x2100d73c -DBCMD_PDXT_VAL: .long 0x110000c8 -DBCMD_MRS0_VAL: .long 0x28000930 -DBCMD_MRS1_VAL: .long 0x29000004 -DBCMD_MRS2_VAL: .long 0x2a000008 -DBCMD_MRS3_VAL: .long 0x2b000000 -DBCMD_ZQCL_VAL: .long 0x03000200 -DBCMD_REF_VAL: .long 0x0c000000 -DBCMD_SRXT_VAL: .long 0x19000000 -DBKIND_D: .long 0x00000007 -DBCONF_D: .long 0x0f030a01 -DBTR0_D: .long 0x00000007 -DBTR1_D: .long 0x00000006 -DBTR2_D: .long 0x00000000 -DBTR3_D: .long 0x00000007 -DBTR4_D: .long 0x00070007 -DBTR5_D: .long 0x0000001b -DBTR6_D: .long 0x00000014 -DBTR7_D: .long 0x00000004 -DBTR8_D: .long 0x00000014 -DBTR9_D: .long 0x00000004 -DBTR10_D: .long 0x00000008 -DBTR11_D: .long 0x00000007 -DBTR12_D: .long 0x0000000e -DBTR13_D: .long 0x000000a0 -DBTR14_D: .long 0x00060006 -DBTR15_D: .long 0x00000003 -DBTR16_D: .long 0x00160002 -DBTR17_D: .long 0x000c0000 -DBTR18_D: .long 0x00000200 -DBTR19_D: .long 0x00000040 -DBRNK0_D: .long 0x00000001 -DBPDCNT0_D: .long 0x00000001 -DBPDCNT1_D: .long 0x00000001 -DBPDCNT2_D: .long 0x00000000 -DBPDCNT3_D: .long 0x00004010 -DBPDLCK_D: .long 0x0000a55a -DBPDRGA_D: .long 0x00000028 -DBPDRGD_D: .long 0x00017100 - -DBADJ0_D: .long 0x00010000 -DBADJ2_D: .long 0x18061806 -DBRFCNF0_D: .long 0x000001ff -DBRFCNF1_D: .long 0x00081040 -DBRFCNF2_D: .long 0x00000000 -DBCALCNF_D: .long 0x0000ffff -DBRFEN_D: .long 0x00000001 -DBACEN_D: .long 0x00000001 -DBCALTR_D: .long 0x08200820 -DBPDNCNF_D: .long 0x00000001 - - .align 2 -exit_ddr: -#if defined(CONFIG_SH_32BIT) - /*------- set PMB -------*/ - write32 PASCR_A, PASCR_29BIT_D - write32 MMUCR_A, MMUCR_D - - /***************************************************************** - * ent virt phys v sz c wt - * 0 0xa0000000 0x00000000 1 128M 0 1 - * 1 0xa8000000 0x48000000 1 128M 0 1 - * 5 0x88000000 0x48000000 1 128M 1 1 - */ - write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D - write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D - write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D - write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D - write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D - write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D - - write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D - - write32 PASCR_A, PASCR_INIT - mov.l DUMMY_ADDR, r0 - icbi @r0 -#endif /* if defined(CONFIG_SH_32BIT) */ - -exit_pmb: - /* CPU is running on ILRAM? */ - mov r14, r0 - tst #1, r0 - bt 1f - - mov.l _stack_ilram, r15 - mov.l _spiboot_main, r0 -100: bsrf r0 - nop - - .align 2 -_spiboot_main: .long (spiboot_main - (100b + 4)) -_stack_ilram: .long 0xe5204000 - -1: - write32 CCR_A, CCR_D - - rts - nop - - .align 2 - -#if defined(CONFIG_SH_32BIT) -/*------- set PMB -------*/ -PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0) -PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1) -PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5) -PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2) -PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3) -PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4) -PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6) -PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7) -PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8) -PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9) -PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10) -PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11) -PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12) -PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13) -PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14) -PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15) - -PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0) -PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88) -PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8) -PMB_ADDR_NOT_USE_D: .long 0x00000000 - -PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0) -PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1) -PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5) - -/* ppn ub v s1 s0 c wt */ -PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1) -PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1) -PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1) - -PASCR_A: .long 0xff000070 -DUMMY_ADDR: .long 0xa0000000 -PASCR_29BIT_D: .long 0x00000000 -PASCR_INIT: .long 0x80000080 -MMUCR_A: .long 0xff000010 -MMUCR_D: .long 0x00000004 /* clear ITLB */ -#endif /* CONFIG_SH_32BIT */ - -CCR_A: .long CCR -CCR_D: .long CCR_CACHE_INIT diff --git a/board/renesas/sh7753evb/sh7753evb.c b/board/renesas/sh7753evb/sh7753evb.c deleted file mode 100644 index f34dec1dfa..0000000000 --- a/board/renesas/sh7753evb/sh7753evb.c +++ /dev/null @@ -1,329 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012 Renesas Solutions Corp. - */ - -#include <common.h> -#include <command.h> -#include <env.h> -#include <flash.h> -#include <init.h> -#include <malloc.h> -#include <net.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/mmc.h> -#include <spi.h> -#include <spi_flash.h> -#include <linux/delay.h> - -int checkboard(void) -{ - puts("BOARD: SH7753 EVB\n"); - - return 0; -} - -static void init_gpio(void) -{ - struct gpio_regs *gpio = GPIO_BASE; - struct sermux_regs *sermux = SERMUX_BASE; - - /* GPIO */ - writew(0x0000, &gpio->pacr); /* GETHER */ - writew(0x0001, &gpio->pbcr); /* INTC */ - writew(0x0000, &gpio->pccr); /* PWMU, INTC */ - writew(0x0000, &gpio->pdcr); /* SPI0 */ - writew(0xeaff, &gpio->pecr); /* GPIO */ - writew(0x0000, &gpio->pfcr); /* WDT */ - writew(0x0004, &gpio->pgcr); /* SPI0, GETHER MDIO gate(PTG1) */ - writew(0x0000, &gpio->phcr); /* SPI1 */ - writew(0x0000, &gpio->picr); /* SDHI */ - writew(0x0000, &gpio->pjcr); /* SCIF4 */ - writew(0x0003, &gpio->pkcr); /* SerMux */ - writew(0x0000, &gpio->plcr); /* SerMux */ - writew(0x0000, &gpio->pmcr); /* RIIC */ - writew(0x0000, &gpio->pncr); /* USB, SGPIO */ - writew(0x0000, &gpio->pocr); /* SGPIO */ - writew(0xd555, &gpio->pqcr); /* GPIO */ - writew(0x0000, &gpio->prcr); /* RIIC */ - writew(0x0000, &gpio->pscr); /* RIIC */ - writew(0x0000, &gpio->ptcr); /* STATUS */ - writeb(0x00, &gpio->pudr); - writew(0x5555, &gpio->pucr); /* Debug LED */ - writew(0x0000, &gpio->pvcr); /* RSPI */ - writew(0x0000, &gpio->pwcr); /* EVC */ - writew(0x0000, &gpio->pxcr); /* LBSC */ - writew(0x0000, &gpio->pycr); /* LBSC */ - writew(0x0000, &gpio->pzcr); /* eMMC */ - writew(0xfe00, &gpio->psel0); - writew(0x0000, &gpio->psel1); - writew(0x3000, &gpio->psel2); - writew(0xff00, &gpio->psel3); - writew(0x771f, &gpio->psel4); - writew(0x0ffc, &gpio->psel5); - writew(0x00ff, &gpio->psel6); - writew(0xfc00, &gpio->psel7); - - writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */ -} - -static void init_usb_phy(void) -{ - struct usb_common_regs *common0 = USB0_COMMON_BASE; - struct usb_common_regs *common1 = USB1_COMMON_BASE; - struct usb0_phy_regs *phy = USB0_PHY_BASE; - struct usb1_port_regs *port = USB1_PORT_BASE; - struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE; - - writew(0x0100, &phy->reset); /* set reset */ - /* port0 = USB0, port1 = USB1 */ - writew(0x0002, &phy->portsel); - writel(0x0001, &port->port1sel); /* port1 = Host */ - writew(0x0111, &phy->reset); /* clear reset */ - - writew(0x4000, &common0->suspmode); - writew(0x4000, &common1->suspmode); - -#if defined(__LITTLE_ENDIAN) - writel(0x00000000, &align->ehcidatac); - writel(0x00000000, &align->ohcidatac); -#endif -} - -static void init_gether_mdio(void) -{ - struct gpio_regs *gpio = GPIO_BASE; - - writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr); - writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */ -} - -static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string) -{ - struct ether_mac_regs *ether; - unsigned char mac[6]; - unsigned long val; - - string_to_enetaddr(mac_string, mac); - - if (!channel) - ether = GETHER0_MAC_BASE; - else - ether = GETHER1_MAC_BASE; - - val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3]; - writel(val, ðer->mahr); - val = (mac[4] << 8) | mac[5]; - writel(val, ðer->malr); -} - -#if defined(CONFIG_SH_32BIT) -/***************************************************************** - * This PMB must be set on this timing. The lowlevel_init is run on - * Area 0(phys 0x00000000), so we have to map it. - * - * The new PMB table is following: - * ent virt phys v sz c wt - * 0 0xa0000000 0x40000000 1 128M 0 1 - * 1 0xa8000000 0x48000000 1 128M 0 1 - * 2 0xb0000000 0x50000000 1 128M 0 1 - * 3 0xb8000000 0x58000000 1 128M 0 1 - * 4 0x80000000 0x40000000 1 128M 1 1 - * 5 0x88000000 0x48000000 1 128M 1 1 - * 6 0x90000000 0x50000000 1 128M 1 1 - * 7 0x98000000 0x58000000 1 128M 1 1 - */ -static void set_pmb_on_board_init(void) -{ - struct mmu_regs *mmu = MMU_BASE; - - /* clear ITLB */ - writel(0x00000004, &mmu->mmucr); - - /* delete PMB for SPIBOOT */ - writel(0, PMB_ADDR_BASE(0)); - writel(0, PMB_DATA_BASE(0)); - - /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */ - /* ppn ub v s1 s0 c wt */ - writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0)); - writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0)); - writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2)); - writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2)); - writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3)); - writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3)); - writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4)); - writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4)); - writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6)); - writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6)); - writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7)); - writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7)); -} -#endif - -int board_init(void) -{ - struct gether_control_regs *gether = GETHER_CONTROL_BASE; - - init_gpio(); -#if defined(CONFIG_SH_32BIT) - set_pmb_on_board_init(); -#endif - - /* Sets TXnDLY to B'010 */ - writel(0x00000202, &gether->gbecont); - - init_usb_phy(); - init_gether_mdio(); - - return 0; -} - -int board_mmc_init(struct bd_info *bis) -{ - struct gpio_regs *gpio = GPIO_BASE; - - writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr); - writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */ - udelay(1); - writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */ - udelay(200); - - return mmcif_mmc_init(); -} - -static int get_sh_eth_mac_raw(unsigned char *buf, int size) -{ -#ifdef CONFIG_DEPRECATED - struct spi_flash *spi; - int ret; - - spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); - if (spi == NULL) { - printf("%s: spi_flash probe failed.\n", __func__); - return 1; - } - - ret = spi_flash_read(spi, SH7753EVB_ETHERNET_MAC_BASE, size, buf); - if (ret) { - printf("%s: spi_flash read failed.\n", __func__); - spi_flash_free(spi); - return 1; - } - spi_flash_free(spi); -#endif - - return 0; -} - -static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf) -{ - memcpy(mac_string, &buf[channel * (SH7753EVB_ETHERNET_MAC_SIZE + 1)], - SH7753EVB_ETHERNET_MAC_SIZE); - mac_string[SH7753EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */ - - return 0; -} - -static void init_ethernet_mac(void) -{ - char mac_string[64]; - char env_string[64]; - int i; - unsigned char *buf; - - buf = malloc(256); - if (!buf) { - printf("%s: malloc failed.\n", __func__); - return; - } - get_sh_eth_mac_raw(buf, 256); - - /* Gigabit Ethernet */ - for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) { - get_sh_eth_mac(i, mac_string, buf); - if (i == 0) - env_set("ethaddr", mac_string); - else { - sprintf(env_string, "eth%daddr", i); - env_set(env_string, mac_string); - } - set_mac_to_sh_giga_eth_register(i, mac_string); - } - - free(buf); -} - -int board_late_init(void) -{ - init_ethernet_mac(); - - return 0; -} - -#ifdef CONFIG_DEPRECATED -int do_write_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - int i, ret; - char mac_string[256]; - struct spi_flash *spi; - unsigned char *buf; - - if (argc != 3) { - buf = malloc(256); - if (!buf) { - printf("%s: malloc failed.\n", __func__); - return 1; - } - - get_sh_eth_mac_raw(buf, 256); - - /* print current MAC address */ - for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) { - get_sh_eth_mac(i, mac_string, buf); - printf("GETHERC ch%d = %s\n", i, mac_string); - } - free(buf); - return 0; - } - - /* new setting */ - memset(mac_string, 0xff, sizeof(mac_string)); - sprintf(mac_string, "%s\t%s", - argv[1], argv[2]); - - /* write MAC data to SPI rom */ - spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); - if (!spi) { - printf("%s: spi_flash probe failed.\n", __func__); - return 1; - } - - ret = spi_flash_erase(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI, - SH7753EVB_SPI_SECTOR_SIZE); - if (ret) { - printf("%s: spi_flash erase failed.\n", __func__); - return 1; - } - - ret = spi_flash_write(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI, - sizeof(mac_string), mac_string); - if (ret) { - printf("%s: spi_flash write failed.\n", __func__); - spi_flash_free(spi); - return 1; - } - spi_flash_free(spi); - - puts("The writing of the MAC address to SPI ROM was completed.\n"); - - return 0; -} - -U_BOOT_CMD( - write_mac, 3, 1, do_write_mac, - "write MAC address for GETHERC", - "[GETHERC ch0] [GETHERC ch1]\n" -); -#endif diff --git a/board/renesas/sh7753evb/spi-boot.c b/board/renesas/sh7753evb/spi-boot.c deleted file mode 100644 index 243c6f6e88..0000000000 --- a/board/renesas/sh7753evb/spi-boot.c +++ /dev/null @@ -1,133 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2013 Renesas Solutions Corp. - */ - -#include <common.h> - -#define CONFIG_SPI_ADDR 0x00000000 -#define PHYADDR(_addr) ((_addr & 0x1fffffff) | 0x40000000) -#define CONFIG_RAM_BOOT_PHYS PHYADDR(CONFIG_SYS_TEXT_BASE) - -#define SPIWDMADR 0xFE001018 -#define SPIWDMCNTR 0xFE001020 -#define SPIDMCOR 0xFE001028 -#define SPIDMINTSR 0xFE001188 -#define SPIDMINTMR 0xFE001190 - -#define SPIDMINTSR_DMEND 0x00000004 - -#define TBR 0xFE002000 -#define RBR 0xFE002000 - -#define CR1 0xFE002008 -#define CR2 0xFE002010 -#define CR3 0xFE002018 -#define CR4 0xFE002020 -#define CR7 0xFE002038 -#define CR8 0xFE002040 - -/* CR1 */ -#define SPI_TBE 0x80 -#define SPI_TBF 0x40 -#define SPI_RBE 0x20 -#define SPI_RBF 0x10 -#define SPI_PFONRD 0x08 -#define SPI_SSDB 0x04 -#define SPI_SSD 0x02 -#define SPI_SSA 0x01 - -/* CR2 */ -#define SPI_RSTF 0x80 -#define SPI_LOOPBK 0x40 -#define SPI_CPOL 0x20 -#define SPI_CPHA 0x10 -#define SPI_L1M0 0x08 - -/* CR4 */ -#define SPI_TBEI 0x80 -#define SPI_TBFI 0x40 -#define SPI_RBEI 0x20 -#define SPI_RBFI 0x10 -#define SPI_SpiS0 0x02 -#define SPI_SSS 0x01 - -/* CR7 */ -#define CR7_IDX_OR12 0x12 -#define OR12_ADDR32 0x00000001 - -#define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val -#define spi_read(addr) (*(volatile unsigned long *)(addr)) - -/* M25P80 */ -#define M25_READ 0x03 -#define M25_READ_4BYTE 0x13 - -extern void bss_start(void); - -#define __uses_spiboot2 __attribute__((section(".spiboot2.text"))) -static void __uses_spiboot2 spi_reset(void) -{ - int timeout = 0x00100000; - - /* Make sure the last transaction is finalized */ - spi_write(0x00, CR3); - spi_write(0x02, CR1); - while (!(spi_read(CR4) & SPI_SpiS0)) { - if (timeout-- < 0) - break; - } - spi_write(0x00, CR1); - - spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */ - spi_write(spi_read(CR2) & ~SPI_RSTF, CR2); - - spi_write(0, SPIDMCOR); -} - -static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr, - unsigned long len) -{ - spi_write(CR7_IDX_OR12, CR7); - if (spi_read(CR8) & OR12_ADDR32) { - /* 4-bytes address mode */ - spi_write(M25_READ_4BYTE, TBR); - spi_write((addr >> 24) & 0xFF, TBR); /* ADDR31-24 */ - } else { - /* 3-bytes address mode */ - spi_write(M25_READ, TBR); - } - spi_write((addr >> 16) & 0xFF, TBR); /* ADDR23-16 */ - spi_write((addr >> 8) & 0xFF, TBR); /* ADDR15-8 */ - spi_write(addr & 0xFF, TBR); /* ADDR7-0 */ - - spi_write(SPIDMINTSR_DMEND, SPIDMINTSR); - spi_write((unsigned long)buf, SPIWDMADR); - spi_write(len & 0xFFFFFFE0, SPIWDMCNTR); - spi_write(1, SPIDMCOR); - - spi_write(0xff, CR3); - spi_write(spi_read(CR1) | SPI_SSDB, CR1); - spi_write(spi_read(CR1) | SPI_SSA, CR1); - - while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND)) - ; - - /* Nagate SP0-SS0 */ - spi_write(0, CR1); -} - -void __uses_spiboot2 spiboot_main(void) -{ - /* - * This code rounds len up for SPIWDMCNTR. We should set it to 0 in - * lower 5-bits. - */ - void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE; - volatile unsigned long len = (bss_start - _start + 31) & 0xffffffe0; - - spi_reset(); - spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR, len); - - _start(); -} diff --git a/board/renesas/sh7757lcr/Kconfig b/board/renesas/sh7757lcr/Kconfig deleted file mode 100644 index 3fba80ddca..0000000000 --- a/board/renesas/sh7757lcr/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_SH7757LCR - -config SYS_BOARD - default "sh7757lcr" - -config SYS_VENDOR - default "renesas" - -config SYS_CONFIG_NAME - default "sh7757lcr" - -endif diff --git a/board/renesas/sh7757lcr/MAINTAINERS b/board/renesas/sh7757lcr/MAINTAINERS deleted file mode 100644 index 20aca678a6..0000000000 --- a/board/renesas/sh7757lcr/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -SH7757LCR BOARD -#M: - -S: Maintained -F: board/renesas/sh7757lcr/ -F: include/configs/sh7757lcr.h -F: configs/sh7757lcr_defconfig diff --git a/board/renesas/sh7757lcr/Makefile b/board/renesas/sh7757lcr/Makefile deleted file mode 100644 index ed3be4b6ab..0000000000 --- a/board/renesas/sh7757lcr/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2011 Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> -# - -obj-y := sh7757lcr.o spi-boot.o -extra-y += lowlevel_init.o diff --git a/board/renesas/sh7757lcr/README.sh7757lcr b/board/renesas/sh7757lcr/README.sh7757lcr deleted file mode 100644 index 9453839d2c..0000000000 --- a/board/renesas/sh7757lcr/README.sh7757lcr +++ /dev/null @@ -1,77 +0,0 @@ -======================================== -Renesas R0P7757LC0030RL board -======================================== - -This board specification: -========================= - -The R0P7757LC0030RL(board config name:sh7757lcr) has the following device: - - - SH7757 (SH-4A) - - DDR3-SDRAM 256MB (with ECC) - - SPI ROM 8MB - - 2D Graphic controller - - Ethernet controller - - eMMC 2GB - - -configuration for This board: -============================= - -You can select the configuration as follows: - - - make sh7757lcr_config - - -This board specific command: -============================ - -This board has the following its specific command: - - - sh_g200 - - write_mac - - -1. sh_g200 - -If we run this command, SH4 can control the G200. -The default setting is that SH4 cannot control the G200. - - -2. write_mac - -You can write MAC address to SPI ROM. - - Usage 1) Write MAC address - - write_mac [ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1] - - For example) - => write_mac 00:00:87:6c:21:80 00:00:87:6c:21:81 00:00:87:6c:21:82 00:00:87:6c:21:83 - *) We have to input the command as a single line - (without carriage return) - *) We have to reset after input the command. - - Usage 2) Show current data - - write_mac - - For example) - => write_mac - ETHERC ch0 = 00:00:87:6c:21:80 - ETHERC ch1 = 00:00:87:6c:21:81 - GETHERC ch0 = 00:00:87:6c:21:82 - GETHERC ch1 = 00:00:87:6c:21:83 - - -Update SPI ROM: -============================ - -1. Copy u-boot image to RAM area. -2. Probe SPI device. - => sf probe 0 - 8192 KiB M25P64 at 0:0 is now current device -3. Erase SPI ROM. - => sf erase 0 80000 -4. Write u-boot image to SPI ROM. - => sf write 0x89000000 0 80000 diff --git a/board/renesas/sh7757lcr/lowlevel_init.S b/board/renesas/sh7757lcr/lowlevel_init.S deleted file mode 100644 index ee288f807f..0000000000 --- a/board/renesas/sh7757lcr/lowlevel_init.S +++ /dev/null @@ -1,544 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Renesas Solutions Corp. - */ - -#include <config.h> -#include <asm/processor.h> -#include <asm/macro.h> - -.macro or32, addr, data - mov.l \addr, r1 - mov.l \data, r0 - mov.l @r1, r2 - or r2, r0 - mov.l r0, @r1 -.endm - -.macro wait_DBCMD - mov.l DBWAIT_A, r0 - mov.l @r0, r1 -.endm - - .global lowlevel_init - .section .spiboot1.text - .align 2 - -lowlevel_init: - - /*------- GPIO -------*/ - write8 PGDR_A, PGDR_D /* eMMC power off */ - - write16 PACR_A, PACR_D - write16 PBCR_A, PBCR_D - write16 PCCR_A, PCCR_D - write16 PDCR_A, PDCR_D - write16 PECR_A, PECR_D - write16 PFCR_A, PFCR_D - write16 PGCR_A, PGCR_D - write16 PHCR_A, PHCR_D - write16 PICR_A, PICR_D - write16 PJCR_A, PJCR_D - write16 PKCR_A, PKCR_D - write16 PLCR_A, PLCR_D - write16 PMCR_A, PMCR_D - write16 PNCR_A, PNCR_D - write16 POCR_A, POCR_D - write16 PQCR_A, PQCR_D - write16 PRCR_A, PRCR_D - write16 PSCR_A, PSCR_D - write16 PTCR_A, PTCR_D - write16 PUCR_A, PUCR_D - write16 PVCR_A, PVCR_D - write16 PWCR_A, PWCR_D - write16 PXCR_A, PXCR_D - write16 PYCR_A, PYCR_D - write16 PZCR_A, PZCR_D - write16 PSEL0_A, PSEL0_D - write16 PSEL1_A, PSEL1_D - write16 PSEL2_A, PSEL2_D - write16 PSEL3_A, PSEL3_D - write16 PSEL4_A, PSEL4_D - write16 PSEL5_A, PSEL5_D - write16 PSEL6_A, PSEL6_D - write16 PSEL7_A, PSEL7_D - write16 PSEL8_A, PSEL8_D - - bra exit_gpio - nop - - .align 4 - -/*------- GPIO -------*/ -PGDR_A: .long 0xffec0040 -PACR_A: .long 0xffec0000 -PBCR_A: .long 0xffec0002 -PCCR_A: .long 0xffec0004 -PDCR_A: .long 0xffec0006 -PECR_A: .long 0xffec0008 -PFCR_A: .long 0xffec000a -PGCR_A: .long 0xffec000c -PHCR_A: .long 0xffec000e -PICR_A: .long 0xffec0010 -PJCR_A: .long 0xffec0012 -PKCR_A: .long 0xffec0014 -PLCR_A: .long 0xffec0016 -PMCR_A: .long 0xffec0018 -PNCR_A: .long 0xffec001a -POCR_A: .long 0xffec001c -PQCR_A: .long 0xffec0020 -PRCR_A: .long 0xffec0022 -PSCR_A: .long 0xffec0024 -PTCR_A: .long 0xffec0026 -PUCR_A: .long 0xffec0028 -PVCR_A: .long 0xffec002a -PWCR_A: .long 0xffec002c -PXCR_A: .long 0xffec002e -PYCR_A: .long 0xffec0030 -PZCR_A: .long 0xffec0032 -PSEL0_A: .long 0xffec0070 -PSEL1_A: .long 0xffec0072 -PSEL2_A: .long 0xffec0074 -PSEL3_A: .long 0xffec0076 -PSEL4_A: .long 0xffec0078 -PSEL5_A: .long 0xffec007a -PSEL6_A: .long 0xffec007c -PSEL7_A: .long 0xffec0082 -PSEL8_A: .long 0xffec0084 - -PGDR_D: .long 0x80 -PACR_D: .long 0x0000 -PBCR_D: .long 0x0001 -PCCR_D: .long 0x0000 -PDCR_D: .long 0x0000 -PECR_D: .long 0x0000 -PFCR_D: .long 0x0000 -PGCR_D: .long 0x0000 -PHCR_D: .long 0x0000 -PICR_D: .long 0x0000 -PJCR_D: .long 0x0000 -PKCR_D: .long 0x0003 -PLCR_D: .long 0x0000 -PMCR_D: .long 0x0000 -PNCR_D: .long 0x0000 -POCR_D: .long 0x0000 -PQCR_D: .long 0xc000 -PRCR_D: .long 0x0000 -PSCR_D: .long 0x0000 -PTCR_D: .long 0x0000 -#if defined(CONFIG_SH7757_OFFSET_SPI) -PUCR_D: .long 0x0055 -#else -PUCR_D: .long 0x0000 -#endif -PVCR_D: .long 0x0000 -PWCR_D: .long 0x0000 -PXCR_D: .long 0x0000 -PYCR_D: .long 0x0000 -PZCR_D: .long 0x0000 -PSEL0_D: .long 0xfe00 -PSEL1_D: .long 0x0000 -PSEL2_D: .long 0x3000 -PSEL3_D: .long 0xff00 -PSEL4_D: .long 0x771f -PSEL5_D: .long 0x0ffc -PSEL6_D: .long 0x00ff -PSEL7_D: .long 0xfc00 -PSEL8_D: .long 0x0000 - - .align 2 - -exit_gpio: - mov #0, r14 - mova 2f, r0 - mov.l PC_MASK, r1 - tst r0, r1 - bf 2f - - bra exit_pmb - nop - - .align 2 - -/* If CPU runs on SDRAM, PC is 0x8???????. */ -PC_MASK: .long 0x20000000 - -2: - mov #1, r14 - - mov.l EXPEVT_A, r0 - mov.l @r0, r0 - mov.l EXPEVT_POWER_ON_RESET, r1 - cmp/eq r0, r1 - bt 1f - - /* - * If EXPEVT value is manual reset or tlb multipul-hit, - * initialization of DDR3IF is not necessary. - */ - bra exit_ddr - nop - -1: - /* For Core Reset */ - mov.l DBACEN_A, r0 - mov.l @r0, r0 - cmp/eq #0, r0 - bt 3f - - /* - * If DBACEN == 1(DBSC was already enabled), we have to avoid the - * initialization of DDR3-SDRAM. - */ - bra exit_ddr - nop - -3: - /*------- DDR3IF -------*/ - /* oscillation stabilization time */ - wait_timer WAIT_OSC_TIME - - /* step 3 */ - write32 DBCMD_A, DBCMD_RSTL_VAL - wait_timer WAIT_30US - - /* step 4 */ - write32 DBCMD_A, DBCMD_PDEN_VAL - - /* step 5 */ - write32 DBKIND_A, DBKIND_D - - /* step 6 */ - write32 DBCONF_A, DBCONF_D - write32 DBTR0_A, DBTR0_D - write32 DBTR1_A, DBTR1_D - write32 DBTR2_A, DBTR2_D - write32 DBTR3_A, DBTR3_D - write32 DBTR4_A, DBTR4_D - write32 DBTR5_A, DBTR5_D - write32 DBTR6_A, DBTR6_D - write32 DBTR7_A, DBTR7_D - write32 DBTR8_A, DBTR8_D - write32 DBTR9_A, DBTR9_D - write32 DBTR10_A, DBTR10_D - write32 DBTR11_A, DBTR11_D - write32 DBTR12_A, DBTR12_D - write32 DBTR13_A, DBTR13_D - write32 DBTR14_A, DBTR14_D - write32 DBTR15_A, DBTR15_D - write32 DBTR16_A, DBTR16_D - write32 DBTR17_A, DBTR17_D - write32 DBTR18_A, DBTR18_D - write32 DBTR19_A, DBTR19_D - write32 DBRNK0_A, DBRNK0_D - - /* step 7 */ - write32 DBPDCNT3_A, DBPDCNT3_D - - /* step 8 */ - write32 DBPDCNT1_A, DBPDCNT1_D - write32 DBPDCNT2_A, DBPDCNT2_D - write32 DBPDLCK_A, DBPDLCK_D - write32 DBPDRGA_A, DBPDRGA_D - write32 DBPDRGD_A, DBPDRGD_D - - /* step 9 */ - wait_timer WAIT_30US - - /* step 10 */ - write32 DBPDCNT0_A, DBPDCNT0_D - - /* step 11 */ - wait_timer WAIT_30US - wait_timer WAIT_30US - - /* step 12 */ - write32 DBCMD_A, DBCMD_WAIT_VAL - wait_DBCMD - - /* step 13 */ - write32 DBCMD_A, DBCMD_RSTH_VAL - wait_DBCMD - - /* step 14 */ - write32 DBCMD_A, DBCMD_WAIT_VAL - write32 DBCMD_A, DBCMD_WAIT_VAL - write32 DBCMD_A, DBCMD_WAIT_VAL - write32 DBCMD_A, DBCMD_WAIT_VAL - - /* step 15 */ - write32 DBCMD_A, DBCMD_PDXT_VAL - - /* step 16 */ - write32 DBCMD_A, DBCMD_MRS2_VAL - - /* step 17 */ - write32 DBCMD_A, DBCMD_MRS3_VAL - - /* step 18 */ - write32 DBCMD_A, DBCMD_MRS1_VAL - - /* step 19 */ - write32 DBCMD_A, DBCMD_MRS0_VAL - - /* step 20 */ - write32 DBCMD_A, DBCMD_ZQCL_VAL - - write32 DBCMD_A, DBCMD_REF_VAL - write32 DBCMD_A, DBCMD_REF_VAL - wait_DBCMD - - /* step 21 */ - write32 DBADJ0_A, DBADJ0_D - write32 DBADJ1_A, DBADJ1_D - write32 DBADJ2_A, DBADJ2_D - - /* step 22 */ - write32 DBRFCNF0_A, DBRFCNF0_D - write32 DBRFCNF1_A, DBRFCNF1_D - write32 DBRFCNF2_A, DBRFCNF2_D - - /* step 23 */ - write32 DBCALCNF_A, DBCALCNF_D - - /* step 24 */ - write32 DBRFEN_A, DBRFEN_D - write32 DBCMD_A, DBCMD_SRXT_VAL - - /* step 25 */ - write32 DBACEN_A, DBACEN_D - - /* step 26 */ - wait_DBCMD - -#if defined(CONFIG_SH7757LCR_DDR_ECC) - /* enable DDR-ECC */ - write32 ECD_ECDEN_A, ECD_ECDEN_D - write32 ECD_INTSR_A, ECD_INTSR_D - write32 ECD_SPACER_A, ECD_SPACER_D - write32 ECD_MCR_A, ECD_MCR_D -#endif - bra exit_ddr - nop - - .align 4 - -EXPEVT_A: .long 0xff000024 -EXPEVT_POWER_ON_RESET: .long 0x00000000 - -/*------- DDR3IF -------*/ -DBCMD_A: .long 0xfe800018 -DBKIND_A: .long 0xfe800020 -DBCONF_A: .long 0xfe800024 -DBTR0_A: .long 0xfe800040 -DBTR1_A: .long 0xfe800044 -DBTR2_A: .long 0xfe800048 -DBTR3_A: .long 0xfe800050 -DBTR4_A: .long 0xfe800054 -DBTR5_A: .long 0xfe800058 -DBTR6_A: .long 0xfe80005c -DBTR7_A: .long 0xfe800060 -DBTR8_A: .long 0xfe800064 -DBTR9_A: .long 0xfe800068 -DBTR10_A: .long 0xfe80006c -DBTR11_A: .long 0xfe800070 -DBTR12_A: .long 0xfe800074 -DBTR13_A: .long 0xfe800078 -DBTR14_A: .long 0xfe80007c -DBTR15_A: .long 0xfe800080 -DBTR16_A: .long 0xfe800084 -DBTR17_A: .long 0xfe800088 -DBTR18_A: .long 0xfe80008c -DBTR19_A: .long 0xfe800090 -DBRNK0_A: .long 0xfe800100 -DBPDCNT0_A: .long 0xfe800200 -DBPDCNT1_A: .long 0xfe800204 -DBPDCNT2_A: .long 0xfe800208 -DBPDCNT3_A: .long 0xfe80020c -DBPDLCK_A: .long 0xfe800280 -DBPDRGA_A: .long 0xfe800290 -DBPDRGD_A: .long 0xfe8002a0 -DBADJ0_A: .long 0xfe8000c0 -DBADJ1_A: .long 0xfe8000c4 -DBADJ2_A: .long 0xfe8000c8 -DBRFCNF0_A: .long 0xfe8000e0 -DBRFCNF1_A: .long 0xfe8000e4 -DBRFCNF2_A: .long 0xfe8000e8 -DBCALCNF_A: .long 0xfe8000f4 -DBRFEN_A: .long 0xfe800014 -DBACEN_A: .long 0xfe800010 -DBWAIT_A: .long 0xfe80001c - -WAIT_OSC_TIME: .long 6000 -WAIT_30US: .long 13333 - -DBCMD_RSTL_VAL: .long 0x20000000 -DBCMD_PDEN_VAL: .long 0x1000d73c -DBCMD_WAIT_VAL: .long 0x0000d73c -DBCMD_RSTH_VAL: .long 0x2100d73c -DBCMD_PDXT_VAL: .long 0x110000c8 -DBCMD_MRS0_VAL: .long 0x28000930 -DBCMD_MRS1_VAL: .long 0x29000004 -DBCMD_MRS2_VAL: .long 0x2a000008 -DBCMD_MRS3_VAL: .long 0x2b000000 -DBCMD_ZQCL_VAL: .long 0x03000200 -DBCMD_REF_VAL: .long 0x0c000000 -DBCMD_SRXT_VAL: .long 0x19000000 -DBKIND_D: .long 0x00000007 -DBCONF_D: .long 0x0f030a01 -DBTR0_D: .long 0x00000007 -DBTR1_D: .long 0x00000006 -DBTR2_D: .long 0x00000000 -DBTR3_D: .long 0x00000007 -DBTR4_D: .long 0x00070007 -DBTR5_D: .long 0x0000001b -DBTR6_D: .long 0x00000014 -DBTR7_D: .long 0x00000005 -DBTR8_D: .long 0x00000015 -DBTR9_D: .long 0x00000006 -DBTR10_D: .long 0x00000008 -DBTR11_D: .long 0x00000007 -DBTR12_D: .long 0x0000000e -DBTR13_D: .long 0x00000056 -DBTR14_D: .long 0x00000006 -DBTR15_D: .long 0x00000004 -DBTR16_D: .long 0x00150002 -DBTR17_D: .long 0x000c0017 -DBTR18_D: .long 0x00000200 -DBTR19_D: .long 0x00000040 -DBRNK0_D: .long 0x00000001 -DBPDCNT0_D: .long 0x00000001 -DBPDCNT1_D: .long 0x00000001 -DBPDCNT2_D: .long 0x00000000 -DBPDCNT3_D: .long 0x00004010 -DBPDLCK_D: .long 0x0000a55a -DBPDRGA_D: .long 0x00000028 -DBPDRGD_D: .long 0x00017100 - -DBADJ0_D: .long 0x00000000 -DBADJ1_D: .long 0x00000000 -DBADJ2_D: .long 0x18061806 -DBRFCNF0_D: .long 0x000001ff -DBRFCNF1_D: .long 0x08001000 -DBRFCNF2_D: .long 0x00000000 -DBCALCNF_D: .long 0x0000ffff -DBRFEN_D: .long 0x00000001 -DBACEN_D: .long 0x00000001 - -/*------- DDR-ECC -------*/ -ECD_ECDEN_A: .long 0xffc1012c -ECD_ECDEN_D: .long 0x00000001 -ECD_INTSR_A: .long 0xfe900024 -ECD_INTSR_D: .long 0xffffffff -ECD_SPACER_A: .long 0xfe900018 -ECD_SPACER_D: .long SH7757LCR_SDRAM_ECC_SETTING -ECD_MCR_A: .long 0xfe900010 -ECD_MCR_D: .long 0x00000001 - - .align 2 -exit_ddr: - -#if defined(CONFIG_SH_32BIT) - /*------- set PMB -------*/ - write32 PASCR_A, PASCR_29BIT_D - write32 MMUCR_A, MMUCR_D - - /***************************************************************** - * ent virt phys v sz c wt - * 0 0xa0000000 0x00000000 1 128M 0 1 - * 1 0xa8000000 0x48000000 1 128M 0 1 - * 5 0x88000000 0x48000000 1 128M 1 1 - */ - write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D - write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D - write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D - write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D - write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D - write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D - - write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D - - write32 PASCR_A, PASCR_INIT - mov.l DUMMY_ADDR, r0 - icbi @r0 -#endif /* if defined(CONFIG_SH_32BIT) */ - -exit_pmb: - /* CPU is running on ILRAM? */ - mov r14, r0 - tst #1, r0 - bt 1f - - mov.l _bss_start, r15 - mov.l _spiboot_main, r0 -100: bsrf r0 - nop - - .align 2 -_spiboot_main: .long (spiboot_main - (100b + 4)) -_bss_start: .long bss_start - -1: - - write32 CCR_A, CCR_D - - rts - nop - - .align 4 - -#if defined(CONFIG_SH_32BIT) -/*------- set PMB -------*/ -PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0) -PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1) -PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5) -PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2) -PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3) -PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4) -PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6) -PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7) -PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8) -PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9) -PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10) -PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11) -PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12) -PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13) -PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14) -PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15) - -PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0) -PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88) -PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8) -PMB_ADDR_NOT_USE_D: .long 0x00000000 - -PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0) -PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1) -PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5) - -/* ppn ub v s1 s0 c wt */ -PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1) -PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1) -PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1) - -PASCR_A: .long 0xff000070 -DUMMY_ADDR: .long 0xa0000000 -PASCR_29BIT_D: .long 0x00000000 -PASCR_INIT: .long 0x80000080 -MMUCR_A: .long 0xff000010 -MMUCR_D: .long 0x00000004 /* clear ITLB */ -#endif /* CONFIG_SH_32BIT */ - -CCR_A: .long CCR -CCR_D: .long CCR_CACHE_INIT diff --git a/board/renesas/sh7757lcr/sh7757lcr.c b/board/renesas/sh7757lcr/sh7757lcr.c deleted file mode 100644 index e933e3e730..0000000000 --- a/board/renesas/sh7757lcr/sh7757lcr.c +++ /dev/null @@ -1,433 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2011 Renesas Solutions Corp. - */ - -#include <common.h> -#include <command.h> -#include <env.h> -#include <flash.h> -#include <init.h> -#include <malloc.h> -#include <net.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/mmc.h> -#include <spi.h> -#include <spi_flash.h> - -int checkboard(void) -{ - puts("BOARD: R0P7757LC0030RL board\n"); - - return 0; -} - -static void init_gctrl(void) -{ - struct gctrl_regs *gctrl = GCTRL_BASE; - unsigned long graofst; - - graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24; - writel(graofst | 0x20000f00, &gctrl->gracr3); -} - -static int init_pcie_bridge_from_spi(void *buf, size_t size) -{ -#ifdef CONFIG_DEPRECATED - struct spi_flash *spi; - int ret; - unsigned long pcie_addr; - - spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); - if (!spi) { - printf("%s: spi_flash probe error.\n", __func__); - return 1; - } - - if (is_sh7757_b0()) - pcie_addr = SH7757LCR_PCIEBRG_ADDR_B0; - else - pcie_addr = SH7757LCR_PCIEBRG_ADDR; - - ret = spi_flash_read(spi, pcie_addr, size, buf); - if (ret) { - printf("%s: spi_flash read error.\n", __func__); - spi_flash_free(spi); - return 1; - } - spi_flash_free(spi); - - return 0; -#else - printf("No SPI support so no PCIe support\n"); - return 1; -#endif -} - -static void init_pcie_bridge(void) -{ - struct pciebrg_regs *pciebrg = PCIEBRG_BASE; - struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE; - int i; - unsigned char *data; - unsigned short tmp; - unsigned long pcie_size; - - if (!(readw(&pciebrg->ctrl_h8s) & 0x0001)) - return; - - if (is_sh7757_b0()) - pcie_size = SH7757LCR_PCIEBRG_SIZE_B0; - else - pcie_size = SH7757LCR_PCIEBRG_SIZE; - - data = malloc(pcie_size); - if (!data) { - printf("%s: malloc error.\n", __func__); - return; - } - if (init_pcie_bridge_from_spi(data, pcie_size)) { - free(data); - return; - } - - if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff && - data[3] == 0xff) { - free(data); - printf("%s: skipped initialization\n", __func__); - return; - } - - writew(0xa501, &pciebrg->ctrl_h8s); /* reset */ - writew(0x0000, &pciebrg->cp_ctrl); - writew(0x0000, &pciebrg->cp_addr); - - for (i = 0; i < pcie_size; i += 2) { - tmp = (data[i] << 8) | data[i + 1]; - writew(tmp, &pciebrg->cp_data); - } - - writew(0xa500, &pciebrg->ctrl_h8s); /* start */ - if (!is_sh7757_b0()) - writel(0x00000001, &pcie_setup->pbictl3); - - free(data); -} - -static void init_usb_phy(void) -{ - struct usb_common_regs *common0 = USB0_COMMON_BASE; - struct usb_common_regs *common1 = USB1_COMMON_BASE; - struct usb0_phy_regs *phy = USB0_PHY_BASE; - struct usb1_port_regs *port = USB1_PORT_BASE; - struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE; - - writew(0x0100, &phy->reset); /* set reset */ - /* port0 = USB0, port1 = USB1 */ - writew(0x0002, &phy->portsel); - writel(0x0001, &port->port1sel); /* port1 = Host */ - writew(0x0111, &phy->reset); /* clear reset */ - - writew(0x4000, &common0->suspmode); - writew(0x4000, &common1->suspmode); - -#if defined(__LITTLE_ENDIAN) - writel(0x00000000, &align->ehcidatac); - writel(0x00000000, &align->ohcidatac); -#endif -} - -static void set_mac_to_sh_eth_register(int channel, char *mac_string) -{ - struct ether_mac_regs *ether; - unsigned char mac[6]; - unsigned long val; - - string_to_enetaddr(mac_string, mac); - - if (!channel) - ether = ETHER0_MAC_BASE; - else - ether = ETHER1_MAC_BASE; - - val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3]; - writel(val, ðer->mahr); - val = (mac[4] << 8) | mac[5]; - writel(val, ðer->malr); -} - -static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string) -{ - struct ether_mac_regs *ether; - unsigned char mac[6]; - unsigned long val; - - string_to_enetaddr(mac_string, mac); - - if (!channel) - ether = GETHER0_MAC_BASE; - else - ether = GETHER1_MAC_BASE; - - val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3]; - writel(val, ðer->mahr); - val = (mac[4] << 8) | mac[5]; - writel(val, ðer->malr); -} - -/***************************************************************** - * This PMB must be set on this timing. The lowlevel_init is run on - * Area 0(phys 0x00000000), so we have to map it. - * - * The new PMB table is following: - * ent virt phys v sz c wt - * 0 0xa0000000 0x40000000 1 128M 0 1 - * 1 0xa8000000 0x48000000 1 128M 0 1 - * 2 0xb0000000 0x50000000 1 128M 0 1 - * 3 0xb8000000 0x58000000 1 128M 0 1 - * 4 0x80000000 0x40000000 1 128M 1 1 - * 5 0x88000000 0x48000000 1 128M 1 1 - * 6 0x90000000 0x50000000 1 128M 1 1 - * 7 0x98000000 0x58000000 1 128M 1 1 - */ -static void set_pmb_on_board_init(void) -{ - struct mmu_regs *mmu = MMU_BASE; - - /* clear ITLB */ - writel(0x00000004, &mmu->mmucr); - - /* delete PMB for SPIBOOT */ - writel(0, PMB_ADDR_BASE(0)); - writel(0, PMB_DATA_BASE(0)); - - /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */ - /* ppn ub v s1 s0 c wt */ - writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0)); - writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0)); - writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2)); - writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2)); - writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3)); - writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3)); - writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4)); - writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4)); - writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6)); - writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6)); - writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7)); - writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7)); -} - -int board_init(void) -{ - struct gether_control_regs *gether = GETHER_CONTROL_BASE; - - set_pmb_on_board_init(); - - /* enable RMII's MDIO (disable GRMII's MDIO) */ - writel(0x00030000, &gether->gbecont); - - init_gctrl(); - init_usb_phy(); - - return 0; -} - -int board_mmc_init(struct bd_info *bis) -{ - return mmcif_mmc_init(); -} - -static int get_sh_eth_mac_raw(unsigned char *buf, int size) -{ -#ifdef CONFIG_DEPRECATED - struct spi_flash *spi; - int ret; - - spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); - if (spi == NULL) { - printf("%s: spi_flash probe error.\n", __func__); - return 1; - } - - ret = spi_flash_read(spi, SH7757LCR_ETHERNET_MAC_BASE, size, buf); - if (ret) { - printf("%s: spi_flash read error.\n", __func__); - spi_flash_free(spi); - return 1; - } - spi_flash_free(spi); -#endif - - return 0; -} - -static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf) -{ - memcpy(mac_string, &buf[channel * (SH7757LCR_ETHERNET_MAC_SIZE + 1)], - SH7757LCR_ETHERNET_MAC_SIZE); - mac_string[SH7757LCR_ETHERNET_MAC_SIZE] = 0x00; /* terminate */ - - return 0; -} - -static void init_ethernet_mac(void) -{ - char mac_string[64]; - char env_string[64]; - int i; - unsigned char *buf; - - buf = malloc(256); - if (!buf) { - printf("%s: malloc error.\n", __func__); - return; - } - get_sh_eth_mac_raw(buf, 256); - - /* Fast Ethernet */ - for (i = 0; i < SH7757LCR_ETHERNET_NUM_CH; i++) { - get_sh_eth_mac(i, mac_string, buf); - if (i == 0) - env_set("ethaddr", mac_string); - else { - sprintf(env_string, "eth%daddr", i); - env_set(env_string, mac_string); - } - - set_mac_to_sh_eth_register(i, mac_string); - } - - /* Gigabit Ethernet */ - for (i = 0; i < SH7757LCR_GIGA_ETHERNET_NUM_CH; i++) { - get_sh_eth_mac(i + SH7757LCR_ETHERNET_NUM_CH, mac_string, buf); - sprintf(env_string, "eth%daddr", i + SH7757LCR_ETHERNET_NUM_CH); - env_set(env_string, mac_string); - - set_mac_to_sh_giga_eth_register(i, mac_string); - } - - free(buf); -} - -static void init_pcie(void) -{ - struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE; - struct pcie_system_bus_regs *pcie_sysbus = PCIE_SYSTEM_BUS_BASE; - - writel(0x00000ff2, &pcie_setup->ladmsk0); - writel(0x00000001, &pcie_setup->barmap); - writel(0xffcaa000, &pcie_setup->lad0); - writel(0x00030000, &pcie_sysbus->endictl0); - writel(0x00000003, &pcie_sysbus->endictl1); - writel(0x00000004, &pcie_setup->pbictl2); -} - -static void finish_spiboot(void) -{ - struct gctrl_regs *gctrl = GCTRL_BASE; - /* - * SH7757 B0 does not use LBSC. - * So if we set SPIBOOTCAN to 1, SH7757 can not access Area0. - * This setting is not cleared by manual reset, So we have to set it - * to 0. - */ - writel(0x00000000, &gctrl->spibootcan); -} - -int board_late_init(void) -{ - init_ethernet_mac(); - init_pcie_bridge(); - init_pcie(); - finish_spiboot(); - - return 0; -} - -int do_sh_g200(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - struct gctrl_regs *gctrl = GCTRL_BASE; - unsigned long graofst; - - writel(0xfedcba98, &gctrl->wprotect); - graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24; - writel(graofst | 0xa0000f00, &gctrl->gracr3); - - return 0; -} - -U_BOOT_CMD( - sh_g200, 1, 1, do_sh_g200, - "enable sh-g200", - "enable SH-G200 bus (disable PCIe-G200)" -); - -#ifdef CONFIG_DEPRECATED -int do_write_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - int i, ret; - char mac_string[256]; - struct spi_flash *spi; - unsigned char *buf; - - if (argc != 5) { - buf = malloc(256); - if (!buf) { - printf("%s: malloc error.\n", __func__); - return 1; - } - - get_sh_eth_mac_raw(buf, 256); - - /* print current MAC address */ - for (i = 0; i < 4; i++) { - get_sh_eth_mac(i, mac_string, buf); - if (i < 2) - printf(" ETHERC ch%d = %s\n", i, mac_string); - else - printf("GETHERC ch%d = %s\n", i-2, mac_string); - } - free(buf); - return 0; - } - - /* new setting */ - memset(mac_string, 0xff, sizeof(mac_string)); - sprintf(mac_string, "%s\t%s\t%s\t%s", - argv[1], argv[2], argv[3], argv[4]); - - /* write MAC data to SPI rom */ - spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); - if (!spi) { - printf("%s: spi_flash probe error.\n", __func__); - return 1; - } - - ret = spi_flash_erase(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI, - SH7757LCR_SPI_SECTOR_SIZE); - if (ret) { - printf("%s: spi_flash erase error.\n", __func__); - return 1; - } - - ret = spi_flash_write(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI, - sizeof(mac_string), mac_string); - if (ret) { - printf("%s: spi_flash write error.\n", __func__); - spi_flash_free(spi); - return 1; - } - spi_flash_free(spi); - - puts("The writing of the MAC address to SPI ROM was completed.\n"); - - return 0; -} - -U_BOOT_CMD( - write_mac, 5, 1, do_write_mac, - "write MAC address for ETHERC/GETHERC", - "[ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]\n" -); -#endif diff --git a/board/renesas/sh7757lcr/spi-boot.c b/board/renesas/sh7757lcr/spi-boot.c deleted file mode 100644 index 71dcf5d445..0000000000 --- a/board/renesas/sh7757lcr/spi-boot.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (C) 2011 Renesas Solutions Corp. - * - * This file is subject to the terms and conditions of the GNU Lesser - * General Public License. See the file "COPYING.LIB" in the main - * directory of this archive for more details. - */ - -#include <common.h> - -#define CONFIG_RAM_BOOT_PHYS 0x4ef80000 -#if defined(CONFIG_SH7757_OFFSET_SPI) -#define CONFIG_SPI_ADDR 0x00010000 -#else -#define CONFIG_SPI_ADDR 0x00000000 -#endif -#define CONFIG_SPI_LENGTH 0x00030000 -#define CONFIG_RAM_BOOT 0x8ef80000 - -#define SPIWDMADR 0xFE001018 -#define SPIWDMCNTR 0xFE001020 -#define SPIDMCOR 0xFE001028 -#define SPIDMINTSR 0xFE001188 -#define SPIDMINTMR 0xFE001190 - -#define SPIDMINTSR_DMEND 0x00000004 - -#define TBR 0xFE002000 -#define RBR 0xFE002000 - -#define CR1 0xFE002008 -#define CR2 0xFE002010 -#define CR3 0xFE002018 -#define CR4 0xFE002020 - -/* CR1 */ -#define SPI_TBE 0x80 -#define SPI_TBF 0x40 -#define SPI_RBE 0x20 -#define SPI_RBF 0x10 -#define SPI_PFONRD 0x08 -#define SPI_SSDB 0x04 -#define SPI_SSD 0x02 -#define SPI_SSA 0x01 - -/* CR2 */ -#define SPI_RSTF 0x80 -#define SPI_LOOPBK 0x40 -#define SPI_CPOL 0x20 -#define SPI_CPHA 0x10 -#define SPI_L1M0 0x08 - -/* CR4 */ -#define SPI_TBEI 0x80 -#define SPI_TBFI 0x40 -#define SPI_RBEI 0x20 -#define SPI_RBFI 0x10 -#define SPI_SSS 0x01 - -#define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val -#define spi_read(addr) (*(volatile unsigned long *)(addr)) - -/* M25P80 */ -#define M25_READ 0x03 - -#define __uses_spiboot2 __attribute__((section(".spiboot2.text"))) -static void __uses_spiboot2 spi_reset(void) -{ - spi_write(0xfe, CR1); - - spi_write(0, SPIDMCOR); - spi_write(0x00, CR1); - - spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */ - spi_write(spi_read(CR2) & ~SPI_RSTF, CR2); -} - -static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr, - unsigned long len) -{ - spi_write(M25_READ, TBR); - spi_write((addr >> 16) & 0xFF, TBR); - spi_write((addr >> 8) & 0xFF, TBR); - spi_write(addr & 0xFF, TBR); - - spi_write(SPIDMINTSR_DMEND, SPIDMINTSR); - spi_write((unsigned long)buf, SPIWDMADR); - spi_write(len & 0xFFFFFFE0, SPIWDMCNTR); - spi_write(1, SPIDMCOR); - - spi_write(0xff, CR3); - spi_write(spi_read(CR1) | SPI_SSDB, CR1); - spi_write(spi_read(CR1) | SPI_SSA, CR1); - - while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND)) - ; -} - -void __uses_spiboot2 spiboot_main(void) -{ - void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE; - - spi_reset(); - spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR, - CONFIG_SPI_LENGTH); - - _start(); -} diff --git a/board/renesas/sh7763rdp/Kconfig b/board/renesas/sh7763rdp/Kconfig deleted file mode 100644 index 101d2b5a32..0000000000 --- a/board/renesas/sh7763rdp/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_SH7763RDP - -config SYS_BOARD - default "sh7763rdp" - -config SYS_VENDOR - default "renesas" - -config SYS_CONFIG_NAME - default "sh7763rdp" - -endif diff --git a/board/renesas/sh7763rdp/MAINTAINERS b/board/renesas/sh7763rdp/MAINTAINERS deleted file mode 100644 index 6ee8f9f87b..0000000000 --- a/board/renesas/sh7763rdp/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -SH7763RDP BOARD -M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> -M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> -S: Maintained -F: board/renesas/sh7763rdp/ -F: include/configs/sh7763rdp.h -F: configs/sh7763rdp_defconfig diff --git a/board/renesas/sh7763rdp/Makefile b/board/renesas/sh7763rdp/Makefile deleted file mode 100644 index 0db63c5d2b..0000000000 --- a/board/renesas/sh7763rdp/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2008 Renesas Solutions Corp. -# Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> -# Copyright (C) 2007 Kenati Technologies, Inc. -# -# board/sh7763rdp/Makefile - -obj-y := sh7763rdp.o -extra-y += lowlevel_init.o diff --git a/board/renesas/sh7763rdp/lowlevel_init.S b/board/renesas/sh7763rdp/lowlevel_init.S deleted file mode 100644 index 80ef258051..0000000000 --- a/board/renesas/sh7763rdp/lowlevel_init.S +++ /dev/null @@ -1,259 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2008 Renesas Solutions Corp. - * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> - * Copyright (C) 2007 Kenati Technologies, Inc. - * - * board/sh7763rdp/lowlevel_init.S - */ - -#include <config.h> - -#include <asm/processor.h> -#include <asm/macro.h> - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - - write32 WDTCSR_A, WDTCSR_D /* Watchdog Control / Status Register */ - - write32 WDTST_A, WDTST_D /* Watchdog Stop Time Register */ - - write32 WDTBST_A, WDTBST_D /* - * 0xFFCC0008 - * Watchdog Base Stop Time Register - */ - - write32 CCR_A, CCR_CACHE_ICI_D /* Address of Cache Control Register */ - /* Instruction Cache Invalidate */ - - write32 MMUCR_A, MMU_CONTROL_TI_D /* MMU Control Register */ - /* TI == TLB Invalidate bit */ - - write32 MSTPCR0_A, MSTPCR0_D /* Address of Power Control Register 0 */ - - write32 MSTPCR1_A, MSTPCR1_D /* Address of Power Control Register 1 */ - - write32 RAMCR_A, RAMCR_D - - mov.l MMSELR_A, r1 - mov.l MMSELR_D, r0 - synco - mov.l r0, @r1 - - mov.l @r1, r2 /* execute two reads after setting MMSELR */ - mov.l @r1, r2 - synco - - /* issue memory read */ - mov.l DDRSD_START_A, r1 /* memory address to read*/ - mov.l @r1, r0 - synco - - write32 MIM8_A, MIM8_D - - write32 MIMC_A, MIMC_D1 - - write32 STRC_A, STRC_D - - write32 SDR4_A, SDR4_D - - write32 MIMC_A, MIMC_D2 - - nop - nop - nop - - write32 SCR4_A, SCR4_D3 - - write32 SCR4_A, SCR4_D2 - - write32 SDMR02000_A, SDMR02000_D - - write32 SDMR00B08_A, SDMR00B08_D - - write32 SCR4_A, SCR4_D2 - - write32 SCR4_A, SCR4_D4 - - nop - nop - nop - nop - - write32 SCR4_A, SCR4_D4 - - nop - nop - nop - nop - - write32 SDMR00308_A, SDMR00308_D - - write32 MIMC_A, MIMC_D3 - - mov.l SCR4_A, r1 - mov.l SCR4_D1, r0 - mov.l DELAY60_D, r3 - -delay_loop_60: - mov.l r0, @r1 - dt r3 - bf delay_loop_60 - nop - - write32 CCR_A, CCR_CACHE_D_2 /* Address of Cache Control Register */ - -bsc_init: - write32 BCR_A, BCR_D - - write32 CS0BCR_A, CS0BCR_D - - write32 CS1BCR_A, CS1BCR_D - - write32 CS2BCR_A, CS2BCR_D - - write32 CS4BCR_A, CS4BCR_D - - write32 CS5BCR_A, CS5BCR_D - - write32 CS6BCR_A, CS6BCR_D - - write32 CS0WCR_A, CS0WCR_D - - write32 CS1WCR_A, CS1WCR_D - - write32 CS2WCR_A, CS2WCR_D - - write32 CS4WCR_A, CS4WCR_D - - write32 CS5WCR_A, CS5WCR_D - - write32 CS6WCR_A, CS6WCR_D - - write32 CS5PCR_A, CS5PCR_D - - write32 CS6PCR_A, CS6PCR_D - - mov.l DELAY200_D, r3 - -delay_loop_200: - dt r3 - bf delay_loop_200 - nop - - write16 PSEL0_A, PSEL0_D - - write16 PSEL1_A, PSEL1_D - - write32 ICR0_A, ICR0_D - - stc sr, r0 /* BL bit off(init=ON) */ - mov.l SR_MASK_D, r1 - and r1, r0 - ldc r0, sr - - rts - nop - - .align 2 - -DELAY60_D: .long 60 -DELAY200_D: .long 17800 - -CCR_A: .long 0xFF00001C -MMUCR_A: .long 0xFF000010 -RAMCR_A: .long 0xFF000074 - -/* Low power mode control */ -MSTPCR0_A: .long 0xFFC80030 -MSTPCR1_A: .long 0xFFC80038 - -/* RWBT */ -WDTST_A: .long 0xFFCC0000 -WDTCSR_A: .long 0xFFCC0004 -WDTBST_A: .long 0xFFCC0008 - -/* BSC */ -MMSELR_A: .long 0xFE600020 -BCR_A: .long 0xFF801000 -CS0BCR_A: .long 0xFF802000 -CS1BCR_A: .long 0xFF802010 -CS2BCR_A: .long 0xFF802020 -CS4BCR_A: .long 0xFF802040 -CS5BCR_A: .long 0xFF802050 -CS6BCR_A: .long 0xFF802060 -CS0WCR_A: .long 0xFF802008 -CS1WCR_A: .long 0xFF802018 -CS2WCR_A: .long 0xFF802028 -CS4WCR_A: .long 0xFF802048 -CS5WCR_A: .long 0xFF802058 -CS6WCR_A: .long 0xFF802068 -CS5PCR_A: .long 0xFF802070 -CS6PCR_A: .long 0xFF802080 -DDRSD_START_A: .long 0xAC000000 - -/* INTC */ -ICR0_A: .long 0xFFD00000 - -/* DDR I/F */ -MIM8_A: .long 0xFE800008 -MIMC_A: .long 0xFE80000C -SCR4_A: .long 0xFE800014 -STRC_A: .long 0xFE80001C -SDR4_A: .long 0xFE800034 -SDMR00308_A: .long 0xFE900308 -SDMR00B08_A: .long 0xFE900B08 -SDMR02000_A: .long 0xFE902000 - -/* GPIO */ -PSEL0_A: .long 0xFFEF0070 -PSEL1_A: .long 0xFFEF0072 - -CCR_CACHE_ICI_D:.long 0x00000800 -CCR_CACHE_D_2: .long 0x00000103 -MMU_CONTROL_TI_D:.long 0x00000004 -RAMCR_D: .long 0x00000200 -MSTPCR0_D: .long 0x00000000 -MSTPCR1_D: .long 0x00000000 - -MMSELR_D: .long 0xa5a50000 -BCR_D: .long 0x00000000 -CS0BCR_D: .long 0x77777770 -CS1BCR_D: .long 0x77777670 -CS2BCR_D: .long 0x77777670 -CS4BCR_D: .long 0x77777670 -CS5BCR_D: .long 0x77777670 -CS6BCR_D: .long 0x77777670 -CS0WCR_D: .long 0x7777770F -CS1WCR_D: .long 0x22000002 -CS2WCR_D: .long 0x7777770F -CS4WCR_D: .long 0x7777770F -CS5WCR_D: .long 0x7777770F -CS6WCR_D: .long 0x7777770F -CS5PCR_D: .long 0x77000000 -CS6PCR_D: .long 0x77000000 -ICR0_D: .long 0x00E00000 -MIM8_D: .long 0x00000000 -MIMC_D1: .long 0x01d10008 -MIMC_D2: .long 0x01d10009 -MIMC_D3: .long 0x01d10209 -SCR4_D1: .long 0x00000001 -SCR4_D2: .long 0x00000002 -SCR4_D3: .long 0x00000003 -SCR4_D4: .long 0x00000004 -STRC_D: .long 0x000f3980 -SDR4_D: .long 0x00000300 -SDMR00308_D: .long 0x00000000 -SDMR00B08_D: .long 0x00000000 -SDMR02000_D: .long 0x00000000 -PSEL0_D: .word 0x00000001 -PSEL1_D: .word 0x00000244 -SR_MASK_D: .long 0xEFFFFF0F -WDTST_D: .long 0x5A000FFF -WDTCSR_D: .long 0xA5000000 -WDTBST_D: .long 0x55000000 diff --git a/board/renesas/sh7763rdp/sh7763rdp.c b/board/renesas/sh7763rdp/sh7763rdp.c deleted file mode 100644 index 73a53c1e5a..0000000000 --- a/board/renesas/sh7763rdp/sh7763rdp.c +++ /dev/null @@ -1,54 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2008 Renesas Solutions Corp. - * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> - * Copyright (C) 2007 Kenati Technologies, Inc. - * - * board/sh7763rdp/sh7763rdp.c - */ - -#include <common.h> -#include <init.h> -#include <asm/io.h> -#include <asm/processor.h> - -#define CPU_CMDREG 0xB1000006 -#define PDCR 0xffef0006 -#define PECR 0xffef0008 -#define PFCR 0xffef000a -#define PGCR 0xffef000c -#define PHCR 0xffef000e -#define PJCR 0xffef0012 -#define PKCR 0xffef0014 -#define PLCR 0xffef0016 -#define PMCR 0xffef0018 -#define PSEL1 0xffef0072 -#define PSEL2 0xffef0074 -#define PSEL3 0xffef0076 - -int checkboard(void) -{ - puts("BOARD: Renesas SH7763 RDP\n"); - return 0; -} - -int board_init(void) -{ - vu_short dat; - - /* Enable mode */ - writew(inw(CPU_CMDREG)|0x0001, CPU_CMDREG); - - /* GPIO Setting (eth1) */ - dat = inw(PSEL1); - writew(((dat & ~0xff00) | 0x2400), PSEL1); - writew(0, PFCR); - writew(0, PGCR); - writew(0, PHCR); - - return 0; -} - -void led_set_state(unsigned short value) -{ -} |