diff options
Diffstat (limited to 'board')
133 files changed, 2950 insertions, 4451 deletions
diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c index c028a53bcb..4df4e9b260 100644 --- a/board/Marvell/guruplug/guruplug.c +++ b/board/Marvell/guruplug/guruplug.c @@ -108,17 +108,6 @@ int board_init(void) return 0; } -int dram_init(void) -{ - int i; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = kw_sdram_bar(i); - gd->bd->bi_dram[i].size = kw_sdram_bs(i); - } - return 0; -} - #ifdef CONFIG_RESET_PHY_R void mv_phy_88e1121_init(char *name) { diff --git a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c index c959bf879e..93d1400be4 100644 --- a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c +++ b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c @@ -110,17 +110,6 @@ int board_init(void) return 0; } -int dram_init(void) -{ - int i; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = kw_sdram_bar(i); - gd->bd->bi_dram[i].size = kw_sdram_bs(i); - } - return 0; -} - #ifdef CONFIG_MV88E61XX_SWITCH void reset_phy(void) { diff --git a/board/Marvell/openrd_base/openrd_base.c b/board/Marvell/openrd_base/openrd_base.c index c00a08aeab..d006b2ddf7 100644 --- a/board/Marvell/openrd_base/openrd_base.c +++ b/board/Marvell/openrd_base/openrd_base.c @@ -113,17 +113,6 @@ int board_init(void) return 0; } -int dram_init(void) -{ - int i; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = kw_sdram_bar(i); - gd->bd->bi_dram[i].size = kw_sdram_bs(i); - } - return 0; -} - #ifdef CONFIG_RESET_PHY_R /* Configure and enable MV88E1116 PHY */ void reset_phy(void) diff --git a/board/Marvell/rd6281a/rd6281a.c b/board/Marvell/rd6281a/rd6281a.c index 8713a3cf9b..0d76146b65 100644 --- a/board/Marvell/rd6281a/rd6281a.c +++ b/board/Marvell/rd6281a/rd6281a.c @@ -109,17 +109,6 @@ int board_init(void) return 0; } -int dram_init(void) -{ - int i; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = kw_sdram_bar(i); - gd->bd->bi_dram[i].size = kw_sdram_bs(i); - } - return 0; -} - void mv_phy_88e1116_init(char *name) { u16 reg; diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c index 547126af8f..173a7b809d 100644 --- a/board/Marvell/sheevaplug/sheevaplug.c +++ b/board/Marvell/sheevaplug/sheevaplug.c @@ -108,17 +108,6 @@ int board_init(void) return 0; } -int dram_init(void) -{ - int i; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = kw_sdram_bar(i); - gd->bd->bi_dram[i].size = kw_sdram_bs(i); - } - return 0; -} - #ifdef CONFIG_RESET_PHY_R /* Configure and enable MV88E1116 PHY */ void reset_phy(void) diff --git a/board/hmi1001/Makefile b/board/a4m072/Makefile index 442e2d0df2..442e2d0df2 100644 --- a/board/hmi1001/Makefile +++ b/board/a4m072/Makefile diff --git a/board/a4m072/a4m072.c b/board/a4m072/a4m072.c new file mode 100644 index 0000000000..ae7ccbb4e9 --- /dev/null +++ b/board/a4m072/a4m072.c @@ -0,0 +1,506 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * (C) Copyright 2010 + * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc5xxx.h> +#include <pci.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <libfdt.h> +#include <netdev.h> +#include <led-display.h> +#include <linux/err.h> + +#include "mt46v32m16.h" + +#ifndef CONFIG_SYS_RAMBOOT +static void sdram_start (int hi_addr) +{ + long hi_addr_bit = hi_addr ? 0x01000000 : 0; + long control = SDRAM_CONTROL | hi_addr_bit; + + /* unlock mode register */ + out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000); + __asm__ volatile ("sync"); + + /* precharge all banks */ + out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002); + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set mode register: extended mode */ + out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE); + __asm__ volatile ("sync"); + + /* set mode register: reset DLL */ + out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000); + __asm__ volatile ("sync"); +#endif + + /* precharge all banks */ + out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002); + __asm__ volatile ("sync"); + + /* auto refresh */ + out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004); + __asm__ volatile ("sync"); + + /* set mode register */ + out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE); + __asm__ volatile ("sync"); + + /* normal operation */ + out_be32((void *)MPC5XXX_SDRAM_CTRL, control); + __asm__ volatile ("sync"); +} +#endif + +/* + * ATTENTION: Although partially referenced initdram does NOT make real use + * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE + * is something else than 0x00000000. + */ + +phys_size_t initdram (int board_type) +{ + ulong dramsize = 0; + uint svr, pvr; + +#ifndef CONFIG_SYS_RAMBOOT + ulong test1, test2; + + /* setup SDRAM chip selects */ + out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); /* 2GB at 0x0 */ + out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */ + __asm__ volatile ("sync"); + + /* setup config registers */ + out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1); + out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2); + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set tap delay */ + out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY); + __asm__ volatile ("sync"); +#endif + + /* find RAM size using SDRAM CS0 only */ + sdram_start(0); + test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); + sdram_start(1); + test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else { + dramsize = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize < (1 << 20)) { + dramsize = 0; + } + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) { + out_be32((void *)MPC5XXX_SDRAM_CS0CFG, + 0x13 + __builtin_ffs(dramsize >> 20) - 1); + } else { + out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */ + } + +#else /* CONFIG_SYS_RAMBOOT */ + + /* retrieve size of memory connected to SDRAM CS0 */ + dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF; + if (dramsize >= 0x13) { + dramsize = (1 << (dramsize - 0x13)) << 20; + } else { + dramsize = 0; + } + +#endif /* CONFIG_SYS_RAMBOOT */ + + /* + * On MPC5200B we need to set the special configuration delay in the + * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM + * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: + * + * "The SDelay should be written to a value of 0x00000004. It is + * required to account for changes caused by normal wafer processing + * parameters." + */ + svr = get_svr(); + pvr = get_pvr(); + if ((SVR_MJREV(svr) >= 2) && + (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { + + out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04); + __asm__ volatile ("sync"); + } + + return dramsize; +} + +int checkboard (void) +{ + puts ("Board: A4M072\n"); + return 0; +} + +#ifdef CONFIG_PCI +static struct pci_controller hose; + +extern void pci_mpc5xxx_init(struct pci_controller *); + +void pci_init_board(void) +{ + pci_mpc5xxx_init(&hose); +} +#endif + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void +ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +} +#endif + +int board_eth_init(bd_t *bis) +{ + int rv, num_if = 0; + + /* Initialize TSECs first */ + if ((rv = cpu_eth_init(bis)) >= 0) + num_if += rv; + else + printf("ERROR: failed to initialize FEC.\n"); + + if ((rv = pci_eth_init(bis)) >= 0) + num_if += rv; + else + printf("ERROR: failed to initialize PCI Ethernet.\n"); + + return num_if; +} +/* + * Miscellaneous late-boot configurations + * + * Initialize EEPROM write-protect GPIO pin. + */ +int misc_init_r(void) +{ +#if defined(CONFIG_SYS_EEPROM_WREN) + /* Enable GPIO pin */ + setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_SYS_EEPROM_WP); + /* Set direction, output */ + setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_SYS_EEPROM_WP); + /* De-assert write enable */ + setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP); +#endif + return 0; +} +#if defined(CONFIG_SYS_EEPROM_WREN) +/* Input: <dev_addr> I2C address of EEPROM device to enable. + * <state> -1: deliver current state + * 0: disable write + * 1: enable write + * Returns: -1: wrong device address + * 0: dis-/en- able done + * 0/1: current state if <state> was -1. + */ +int eeprom_write_enable (unsigned dev_addr, int state) +{ + if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { + return -1; + } else { + switch (state) { + case 1: + /* Enable write access */ + clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP); + state = 0; + break; + case 0: + /* Disable write access */ + setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP); + state = 0; + break; + default: + /* Read current status back. */ + state = (0 == (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) & + CONFIG_SYS_EEPROM_WP)); + break; + } + } + return state; +} +#endif + +#ifdef CONFIG_CMD_DISPLAY +#define DISPLAY_BUF_SIZE 2 +static u8 display_buf[DISPLAY_BUF_SIZE]; +static u8 display_putc_pos; +static u8 display_out_pos; + +static u8 display_dot_enable; + +void display_set(int cmd) { + + if (cmd & DISPLAY_CLEAR) { + display_buf[0] = display_buf[1] = 0; + } + + if (cmd & DISPLAY_HOME) { + display_putc_pos = 0; + } + + if (cmd & DISPLAY_MARK) { + display_dot_enable = 1; + } else { + display_dot_enable = 0; + } +} + +#define SEG_A (1<<0) +#define SEG_B (1<<1) +#define SEG_C (1<<2) +#define SEG_D (1<<3) +#define SEG_E (1<<4) +#define SEG_F (1<<5) +#define SEG_G (1<<6) +#define SEG_P (1<<7) +#define SEG__ 0 + +/* + * +- A -+ + * | | + * F B + * | | + * +- G -+ + * | | + * E C + * | | + * +- D -+ P + * + * 0..9 index 0..9 + * A..Z index 10..35 + * - index 36 + * _ index 37 + */ + +#define SYMBOL_DASH (36) +#define SYMBOL_UNDERLINE (37) + +static u8 display_char2seg7_tbl[]= +{ + SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* 0 */ + SEG_B | SEG_C, /* 1 */ + SEG_A | SEG_B | SEG_D | SEG_E | SEG_G, /* 2 */ + SEG_A | SEG_B | SEG_C | SEG_D | SEG_G, /* 3 */ + SEG_B | SEG_C | SEG_F | SEG_G, /* 4 */ + SEG_A | SEG_C | SEG_D | SEG_F | SEG_G, /* 5 */ + SEG_A | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* 6 */ + SEG_A | SEG_B | SEG_C, /* 7 */ + SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* 8 */ + SEG_A | SEG_B | SEG_C | SEG_D | SEG_F | SEG_G, /* 9 */ + SEG_A | SEG_B | SEG_C | SEG_E | SEG_F | SEG_G, /* A */ + SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* b */ + SEG_A | SEG_D | SEG_E | SEG_F, /* C */ + SEG_B | SEG_C | SEG_D | SEG_E | SEG_G, /* d */ + SEG_A | SEG_D | SEG_E | SEG_F | SEG_G, /* E */ + SEG_A | SEG_E | SEG_F | SEG_G, /* F */ + SEG_A | SEG_B | SEG_C | SEG_D | SEG_F | SEG_G, /* g */ + SEG_B | SEG_C | SEG_E | SEG_F | SEG_G, /* H */ + SEG_E | SEG_F, /* I */ + SEG_B | SEG_C | SEG_D | SEG_E, /* J */ + SEG_A, /* K - special 1 */ + SEG_D | SEG_E | SEG_F, /* L */ + SEG_B, /* m - special 2 */ + SEG_C | SEG_E | SEG_G, /* n */ + SEG_C | SEG_D | SEG_E | SEG_G, /* o */ + SEG_A | SEG_B | SEG_E | SEG_F | SEG_G, /* P */ + SEG_A | SEG_B | SEG_C | SEG_F | SEG_G, /* q */ + SEG_E | SEG_G, /* r */ + SEG_A | SEG_C | SEG_D | SEG_F | SEG_G, /* S */ + SEG_D | SEG_E | SEG_F | SEG_G, /* t */ + SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* U */ + SEG_C | SEG_D | SEG_E | SEG_F, /* V */ + SEG_C, /* w - special 3 */ + SEG_B | SEG_C | SEG_E | SEG_F | SEG_G, /* X */ + SEG_B | SEG_C | SEG_D | SEG_F | SEG_G, /* Y */ + SEG_A | SEG_B | SEG_D | SEG_E | SEG_G, /* Z */ + SEG_G, /* - */ + SEG_D /* _ */ +}; + +/* Convert char to the LED segments representation */ +static u8 display_char2seg7(char c) +{ + u8 val = 0; + + if (c >= '0' && c <= '9') + c -= '0'; + else if (c >= 'a' && c <= 'z') + c -= 'a' - 10; + else if (c >= 'A' && c <= 'Z') + c -= 'A' - 10; + else if (c == '-') + c = SYMBOL_DASH; + else if ((c == '_') || (c == '.')) + c = SYMBOL_UNDERLINE; + else + c = ' '; /* display unsupported symbols as space */ + + if (c != ' ') + val = display_char2seg7_tbl[(int)c]; + + /* Handle DP LED here */ + if (display_dot_enable) { + val |= SEG_P; + } + + return val; +} + +static inline int display_putc_nomark(char c) +{ + if (display_putc_pos >= DISPLAY_BUF_SIZE) + return -1; + + display_buf[display_putc_pos++] = display_char2seg7(c); + /* one-symbol message should be steady */ + if (display_putc_pos == 1) + display_buf[display_putc_pos] = display_char2seg7(c); + + return c; +} + +int display_putc(char c) +{ + /* Mark the codes from the "display" command with the DP LED */ + display_set(DISPLAY_MARK); + return display_putc_nomark(c); +} + +/* + * Flush current symbol to the LED display hardware + */ +static inline void display_flush(void) +{ + u32 val = display_buf[display_out_pos]; + + val |= (val << 8) | (val << 16) | (val << 24); + out_be32((void *)CONFIG_SYS_DISP_CHR_RAM, val); +} + +/* + * Output contents of the software display buffer to the LED display every 0.5s + */ +void board_show_activity(ulong timestamp) +{ + static ulong last; + static u8 once; + + if (!once || (timestamp - last >= (CONFIG_SYS_HZ / 2))) { + display_flush(); + display_out_pos ^= 1; + last = timestamp; + once = 1; + } +} + +/* + * Empty fake function + */ +void show_activity(int arg) +{ +} +#endif +#if defined (CONFIG_SHOW_BOOT_PROGRESS) +static int a4m072_status2code(int status, char *buf) +{ + char c = 0; + + if (((status > 0) && (status <= 8)) || + ((status >= 100) && (status <= 108)) || + ((status < 0) && (status >= -9)) || + (status == -100) || (status == -101) || + ((status <= -103) && (status >= -113))) { + c = '5'; + } else if (((status >= 9) && (status <= 14)) || + ((status >= 120) && (status <= 123)) || + ((status >= 125) && (status <= 129)) || + ((status >= -13) && (status <= -10)) || + (status == -120) || (status == -122) || + ((status <= -124) && (status >= -127)) || + (status == -129)) { + c = '8'; + } else if (status == 15) { + c = '9'; + } else if ((status <= -30) && (status >= -32)) { + c = 'A'; + } else if (((status <= -35) && (status >= -40)) || + ((status <= -42) && (status >= -51)) || + ((status <= -53) && (status >= -58)) || + (status == -64) || + ((status <= -80) && (status >= -83)) || + (status == -130) || (status == -140) || + (status == -150)) { + c = 'B'; + } + + if (c == 0) + return -EINVAL; + + buf[0] = (status < 0) ? '-' : c; + buf[1] = c; + + return 0; +} + +void show_boot_progress(int status) +{ + char buf[2]; + + if (a4m072_status2code(status, buf) < 0) + return; + + display_set(0); /* Clear DP Led */ + display_putc_nomark(buf[0]); + display_putc_nomark(buf[1]); + display_set(DISPLAY_HOME); + display_out_pos = 0; /* reset output position */ + + /* we want to flush status 15 now */ + if (status == 15) + display_flush(); +} +#endif diff --git a/board/a4m072/config.mk b/board/a4m072/config.mk new file mode 100644 index 0000000000..c6ba51d960 --- /dev/null +++ b/board/a4m072/config.mk @@ -0,0 +1,39 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# a4m072 board: +# +# Valid values for TEXT_BASE is: +# +# 0xFE000000 boot low +# + +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +## Standard: boot low +TEXT_BASE = 0xFE000000 +endif + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/a4m072/mt46v32m16.h b/board/a4m072/mt46v32m16.h new file mode 100644 index 0000000000..d7561fbee4 --- /dev/null +++ b/board/a4m072/mt46v32m16.h @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 1 /* is DDR */ + +#if defined(CONFIG_MPC5200) +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40010000 +#define SDRAM_CONTROL 0x704f0f00 +#define SDRAM_CONFIG1 0x73722930 +#define SDRAM_CONFIG2 0x47770000 +#define SDRAM_TAPDELAY 0x10000000 + +#else +#error CONFIG_MPC5200 not defined +#endif diff --git a/board/amcc/bluestone/Makefile b/board/amcc/bluestone/Makefile new file mode 100644 index 0000000000..41751c870b --- /dev/null +++ b/board/amcc/bluestone/Makefile @@ -0,0 +1,52 @@ +# +# Copyright (c) 2010, Applied Micro Circuits Corporation +# Author: Tirumala R Marri <tmarri@apm.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o +SOBJS := init.o + +COBJS := $(COBJS-y) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/amcc/bluestone/bluestone.c b/board/amcc/bluestone/bluestone.c new file mode 100644 index 0000000000..fe8929c389 --- /dev/null +++ b/board/amcc/bluestone/bluestone.c @@ -0,0 +1,111 @@ +/* + * Bluestone board support + * + * Copyright (c) 2010, Applied Micro Circuits Corporation + * Author: Tirumala R Marri <tmarri@apm.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/apm821xx.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <i2c.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/mmu.h> +#include <asm/ppc4xx-gpio.h> + +int board_early_init_f(void) +{ + /* + * Setup the interrupt controller polarities, triggers, etc. + */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ + mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + mtdcr(UIC2ER, 0x00000000); /* disable all */ + mtdcr(UIC2CR, 0x00000000); /* all non-critical */ + mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + + mtdcr(UIC3SR, 0xffffffff); /* clear all */ + mtdcr(UIC3ER, 0x00000000); /* disable all */ + mtdcr(UIC3CR, 0x00000000); /* all non-critical */ + mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC3SR, 0xffffffff); /* clear all */ + + /* + * Configure PFC (Pin Function Control) registers + * UART0: 2 pins + */ + mtsdr(SDR0_PFC1, 0x0000000); + + return 0; +} + +int checkboard(void) +{ + char *s = getenv("serial#"); + + puts("Board: Bluestone Evaluation Board"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return 0; +} + +int misc_init_r(void) +{ + u32 sdr0_srst1 = 0; + + /* Setup PLB4-AHB bridge based on the system address map */ + mtdcr(AHB_TOP, 0x8000004B); + mtdcr(AHB_BOT, 0x8000004B); + + /* + * The AHB Bridge core is held in reset after power-on or reset + * so enable it now + */ + mfsdr(SDR0_SRST1, sdr0_srst1); + sdr0_srst1 &= ~SDR0_SRST1_AHB; + mtsdr(SDR0_SRST1, sdr0_srst1); + + return 0; +} diff --git a/board/amcc/bluestone/config.mk b/board/amcc/bluestone/config.mk new file mode 100644 index 0000000000..e2194e4e00 --- /dev/null +++ b/board/amcc/bluestone/config.mk @@ -0,0 +1,40 @@ +# +# Copyright (c) 2010, Applied Micro Circuits Corporation +# Author: Tirumala R Marri <tmarri@apm.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# Applied Micro APM821XX Evaluation board. +# + +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +TEXT_BASE = 0xFFFA0000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 +endif diff --git a/board/amcc/bluestone/init.S b/board/amcc/bluestone/init.S new file mode 100644 index 0000000000..e969fcfd90 --- /dev/null +++ b/board/amcc/bluestone/init.S @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2010, Applied Micro Circuits Corporation + * Author: Tirumala R Marri <tmarri@apm.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <ppc_asm.tmpl> +#include <config.h> +#include <asm/mmu.h> +#include <asm/ppc4xx.h> + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + + /* TLB 0 */ + tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, + 4, AC_RWX | SA_G) + + /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ + tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, + 0, AC_RWX | SA_G) + + /* TLB-entry for OCM */ + tlbentry(CONFIG_SYS_OCM_BASE, SZ_64K, 0x00040000, 4, + AC_RWX | SA_I) + + /* TLB-entry for Local Configuration registers => peripherals */ + tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K, + CONFIG_SYS_PERIPHERAL_BASE, 4, AC_RWX | SA_IG) + tlbtab_end diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index b26cadb6bb..faa3720df3 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -34,16 +34,16 @@ extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH ch DECLARE_GLOBAL_DATA_PTR; - struct board_bcsr { - u8 board_id; - u8 cpld_rev; - u8 led_user; - u8 board_status; - u8 reset_ctrl; - u8 flash_ctrl; - u8 eth_ctrl; - u8 usb_ctrl; - u8 irq_ctrl; +struct board_bcsr { + u8 board_id; + u8 cpld_rev; + u8 led_user; + u8 board_status; + u8 reset_ctrl; + u8 flash_ctrl; + u8 eth_ctrl; + u8 usb_ctrl; + u8 irq_ctrl; }; #define BOARD_CANYONLANDS_PCIE 1 @@ -195,16 +195,6 @@ int board_early_init_f(void) mtdcr(AHB_TOP, 0x8000004B); mtdcr(AHB_BOT, 0x8000004B); - if (pvr_460ex()) { - /* - * Configure USB-STP pins as alternate and not GPIO - * It seems to be neccessary to configure the STP pins as GPIO - * input at powerup (perhaps while USB reset is asserted). So - * we configure those pins to their "real" function now. - */ - gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); - gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); - } #endif return 0; @@ -222,6 +212,15 @@ int usb_board_init(void) val &= ~(BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST); out_8(&bcsr_data->usb_ctrl, val); + /* + * Configure USB-STP pins as alternate and not GPIO + * It seems to be neccessary to configure the STP pins as GPIO + * input at powerup (perhaps while USB reset is asserted). So + * we configure those pins to their "real" function now. + */ + gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); + gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); + return 0; } @@ -236,6 +235,10 @@ int usb_board_stop(void) val |= (BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST); out_8(&bcsr_data->usb_ctrl, val); + /* Reconfigure USB-STP pins as input */ + gpio_config(16, GPIO_IN , GPIO_SEL, GPIO_OUT_0); + gpio_config(19, GPIO_IN , GPIO_SEL, GPIO_OUT_0); + return 0; } diff --git a/board/armltd/integrator/split_by_variant.sh b/board/armltd/integrator/split_by_variant.sh index 702b436c8e..d869dd2b75 100755 --- a/board/armltd/integrator/split_by_variant.sh +++ b/board/armltd/integrator/split_by_variant.sh @@ -10,12 +10,12 @@ then # --------------------------------------------------------- # Set the platform defines # --------------------------------------------------------- -echo -n "/* Integrator configuration implied " > ${config_file} -echo " by Makefile target */" >> ${config_file} -echo -n "#define CONFIG_INTEGRATOR" >> ${config_file} -echo " /* Integrator board */" >> ${config_file} -echo -n "#define CONFIG_ARCH_INTEGRATOR" >> ${config_file} -echo " 1 /* Integrator/AP */" >> ${config_file} +cat > ${config_file} << _EOF +/* Integrator configuration implied by Makefile target */ +#define CONFIG_INTEGRATOR /* Integrator board */ +#define CONFIG_ARCH_INTEGRATOR 1 /* Integrator/AP */ +_EOF + # --------------------------------------------------------- # Set the core module defines according to Core Module # --------------------------------------------------------- @@ -50,37 +50,37 @@ else ap720t_config) cpu="arm720t" - echo -n "#define CONFIG_CM720T" >> ${config_file} - echo " 1 /* CPU core is ARM720T */ " >> ${config_file} + echo "#define CONFIG_CM720T 1 /* CPU core is ARM720T */" \ + >> ${config_file} variant="Core module CM720T" ;; ap922_XA10_config) cpu="arm_intcm" variant="unported core module CM922T_XA10" - echo -n "#define CONFIG_CM922T_XA10" >> ${config_file} - echo " 1 /* CPU core is ARM922T_XA10 */" >> ${config_file} + echo "#define CONFIG_CM922T_XA10 1 /* CPU core is ARM922T_XA10 */" \ + >> ${config_file} ;; ap920t_config) cpu="arm920t" variant="Core module CM920T" - echo -n "#define CONFIG_CM920T" >> ${config_file} - echo " 1 /* CPU core is ARM920T */" >> ${config_file} + echo "#define CONFIG_CM920T 1 /* CPU core is ARM920T */" \ + >> ${config_file} ;; ap926ejs_config) cpu="arm926ejs" variant="Core module CM926EJ-S" - echo -n "#define CONFIG_CM926EJ_S" >> ${config_file} - echo " 1 /* CPU core is ARM926EJ-S */ " >> ${config_file} + echo "#define CONFIG_CM926EJ_S 1 /* CPU core is ARM926EJ-S */" \ + >> ${config_file} ;; ap946es_config) cpu="arm946es" variant="Core module CM946E-S" - echo -n "#define CONFIG_CM946E_S" >> ${config_file} - echo " 1 /* CPU core is ARM946E-S */ " >> ${config_file} + echo "#define CONFIG_CM946E_S 1 /* CPU core is ARM946E-S */" \ + >> ${config_file} ;; *) @@ -94,33 +94,26 @@ fi case "$cpu" in arm_intcm) - echo "/* Core module undefined/not ported */" >> ${config_file} - echo "#define CONFIG_ARM_INTCM 1" >> ${config_file} - echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM" >> ${config_file} - echo -n " /* CM may not have " >> ${config_file} - echo "multiple SSRAM mapping */" >> ${config_file} - echo -n "#undef CONFIG_CM_SPD_DETECT " >> ${config_file} - echo -n " /* CM may not support SPD " >> ${config_file} - echo "query */" >> ${config_file} - echo -n "#undef CONFIG_CM_REMAP " >> ${config_file} - echo -n " /* CM may not support " >> ${config_file} - echo "remapping */" >> ${config_file} - echo -n "#undef CONFIG_CM_INIT " >> ${config_file} - echo -n " /* CM may not have " >> ${config_file} - echo "initialization reg */" >> ${config_file} - echo -n "#undef CONFIG_CM_TCRAM " >> ${config_file} - echo " /* CM may not have TCRAM */" >> ${config_file} - echo -n " /* May not be processor " >> ${config_file} - echo "without cache support */" >> ${config_file} - echo "#define CONFIG_SYS_NO_ICACHE 1" >> ${config_file} - echo "#define CONFIG_SYS_NO_DCACHE 1" >> ${config_file} + cat >> ${config_file} << _EOF +/* Core module undefined/not ported */ +#define CONFIG_ARM_INTCM 1 +#undef CONFIG_CM_MULTIPLE_SSRAM /* CM may not have multiple SSRAM mapping */ +#undef CONFIG_CM_SPD_DETECT /* CM may not support SPD query */ +#undef CONFIG_CM_REMAP /* CM may not support remapping */ +#undef CONFIG_CM_INIT /* CM may not have initialization reg */ +#undef CONFIG_CM_TCRAM /* CM may not have TCRAM */ +/* May not be processor without cache support */ +#define CONFIG_SYS_NO_ICACHE 1 +#define CONFIG_SYS_NO_DCACHE 1 +_EOF ;; arm720t) - echo -n " /* May not be processor " >> ${config_file} - echo "without cache support */" >> ${config_file} - echo "#define CONFIG_SYS_NO_ICACHE 1" >> ${config_file} - echo "#define CONFIG_SYS_NO_DCACHE 1" >> ${config_file} + cat >> ${config_file} << _EOF +/* May not be processor without cache support */ +#define CONFIG_SYS_NO_ICACHE 1 +#define CONFIG_SYS_NO_DCACHE 1 +_EOF ;; esac @@ -129,12 +122,11 @@ else # --------------------------------------------------------- # Set the platform defines # --------------------------------------------------------- -echo -n "/* Integrator configuration implied " > ${config_file} -echo " by Makefile target */" >> ${config_file} -echo -n "#define CONFIG_INTEGRATOR" >> ${config_file} -echo " /* Integrator board */" >> ${config_file} -echo -n "#define CONFIG_ARCH_CINTEGRATOR" >> ${config_file} -echo " 1 /* Integrator/CP */" >> ${config_file} +cat >> ${config_file} << _EOF +/* Integrator configuration implied by Makefile target */ +#define CONFIG_INTEGRATOR /* Integrator board */ +#define CONFIG_ARCH_CINTEGRATOR 1 /* Integrator/CP */ +_EOF cpu="arm_intcm" variant="unknown core module" @@ -163,37 +155,37 @@ else cp922_XA10_config) cpu="arm_intcm" variant="unported core module CM922T_XA10" - echo -n "#define CONFIG_CM922T_XA10" >> ${config_file} - echo " 1 /* CPU core is ARM922T_XA10 */" >> ${config_file} + echo "#define CONFIG_CM922T_XA10 1 /* CPU core is ARM922T_XA10 */" \ + >> ${config_file} ;; cp920t_config) cpu="arm920t" variant="Core module CM920T" - echo -n "#define CONFIG_CM920T" >> ${config_file} - echo " 1 /* CPU core is ARM920T */" >> ${config_file} + echo "#define CONFIG_CM920T 1 /* CPU core is ARM920T */" \ + >> ${config_file} ;; cp926ejs_config) cpu="arm926ejs" variant="Core module CM926EJ-S" - echo -n "#define CONFIG_CM926EJ_S" >> ${config_file} - echo " 1 /* CPU core is ARM926EJ-S */ " >> ${config_file} + echo "#define CONFIG_CM926EJ_S 1 /* CPU core is ARM926EJ-S */" \ + >> ${config_file} ;; cp946es_config) cpu="arm946es" variant="Core module CM946E-S" - echo -n "#define CONFIG_CM946E_S" >> ${config_file} - echo " 1 /* CPU core is ARM946E-S */ " >> ${config_file} + echo "#define CONFIG_CM946E_S 1 /* CPU core is ARM946E-S */" \ + >> ${config_file} ;; cp1136_config) cpu="arm1136" variant="Core module CM1136EJF-S" - echo -n "#define CONFIG_CM1136EJF_S" >> ${config_file} - echo " 1 /* CPU core is ARM1136JF-S */ " >> ${config_file} + echo "#define CONFIG_CM1136EJF_S 1 /* CPU core is ARM1136JF-S */" \ + >> ${config_file} ;; *) @@ -208,22 +200,15 @@ fi if [ "$cpu" = "arm_intcm" ] then - echo "/* Core module undefined/not ported */" >> ${config_file} - echo "#define CONFIG_ARM_INTCM 1" >> ${config_file} - echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM" >> ${config_file} - echo -n " /* CM may not have " >> ${config_file} - echo "multiple SSRAM mapping */" >> ${config_file} - echo -n "#undef CONFIG_CM_SPD_DETECT " >> ${config_file} - echo -n " /* CM may not support SPD " >> ${config_file} - echo "query */" >> ${config_file} - echo -n "#undef CONFIG_CM_REMAP " >> ${config_file} - echo -n " /* CM may not support " >> ${config_file} - echo "remapping */" >> ${config_file} - echo -n "#undef CONFIG_CM_INIT " >> ${config_file} - echo -n " /* CM may not have " >> ${config_file} - echo "initialization reg */" >> ${config_file} - echo -n "#undef CONFIG_CM_TCRAM " >> ${config_file} - echo " /* CM may not have TCRAM */" >> ${config_file} + cat >> ${config_file} << _EOF +/* Core module undefined/not ported */ +#define CONFIG_ARM_INTCM 1 +#undef CONFIG_CM_MULTIPLE_SSRAM /* CM may not have multiple SSRAM mapping */ +#undef CONFIG_CM_SPD_DETECT /* CM may not support SPD query */ +#undef CONFIG_CM_REMAP /* CM may not support remapping */ +#undef CONFIG_CM_INIT /* CM may not have initialization reg */ +#undef CONFIG_CM_TCRAM /* CM may not have TCRAM */ +_EOF fi fi # ap diff --git a/board/siemens/CCM/Makefile b/board/armltd/vexpress/Makefile index c5695f98cb..ee5c0d87ac 100644 --- a/board/siemens/CCM/Makefile +++ b/board/armltd/vexpress/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,21 +23,14 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -$(shell mkdir -p $(obj)../../tqc/tqm8xx) -endif - LIB = $(obj)lib$(BOARD).a -COBJS = ccm.o flash.o fpga_ccm.o ../common/fpga.o \ - ../../tqc/tqm8xx/load_sernum_ethaddr.o +COBJS := ca9x4_ct_vxp.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(OBJS) +$(LIB): $(obj).depend $(OBJS) $(AR) $(ARFLAGS) $@ $(OBJS) clean: diff --git a/board/armltd/vexpress/ca9x4_ct_vxp.c b/board/armltd/vexpress/ca9x4_ct_vxp.c new file mode 100644 index 0000000000..48dfc8c435 --- /dev/null +++ b/board/armltd/vexpress/ca9x4_ct_vxp.c @@ -0,0 +1,220 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> + * + * (C) Copyright 2003 + * Texas Instruments, <www.ti.com> + * Kshitij Gupta <Kshitij@ti.com> + * + * (C) Copyright 2004 + * ARM Ltd. + * Philippe Robin, <philippe.robin@arm.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm/arch/systimer.h> +#include <asm/arch/sysctrl.h> +#include <asm/arch/wdt.h> + +static ulong timestamp; +static ulong lastdec; + +static struct wdt *wdt_base = (struct wdt *)WDT_BASE; +static struct systimer *systimer_base = (struct systimer *)SYSTIMER_BASE; +static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE; + +static void flash__init(void); +static void vexpress_timer_init(void); +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_SHOW_BOOT_PROGRESS) +void show_boot_progress(int progress) +{ + printf("Boot reached stage %d\n", progress); +} +#endif + +static inline void delay(ulong loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b" : "=r" (loops) : "0" (loops)); +} + +int board_init(void) +{ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + gd->bd->bi_arch_number = MACH_TYPE_VEXPRESS; + gd->flags = 0; + + icache_enable(); + flash__init(); + vexpress_timer_init(); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return rc; +} + +static void flash__init(void) +{ + /* Setup the sytem control register to allow writing to flash */ + writel(readl(&sysctrl_base->scflashctrl) | VEXPRESS_FLASHPROG_FLVPPEN, + &sysctrl_base->scflashctrl); +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = get_ram_size(PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = get_ram_size(PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); +} + +int timer_init(void) +{ + return 0; +} + +/* + * Start timer: + * Setup a 32 bit timer, running at 1KHz + * Versatile Express Motherboard provides 1 MHz timer + */ +static void vexpress_timer_init(void) +{ + /* + * Set clock frequency in system controller: + * VEXPRESS_REFCLK is 32KHz + * VEXPRESS_TIMCLK is 1MHz + */ + writel(SP810_TIMER0_ENSEL | SP810_TIMER1_ENSEL | + SP810_TIMER2_ENSEL | SP810_TIMER3_ENSEL | + readl(&sysctrl_base->scctrl), &sysctrl_base->scctrl); + + /* + * Set Timer0 to be: + * Enabled, free running, no interrupt, 32-bit, wrapping + */ + writel(SYSTIMER_RELOAD, &systimer_base->timer0load); + writel(SYSTIMER_RELOAD, &systimer_base->timer0value); + writel(SYSTIMER_EN | SYSTIMER_32BIT | \ + readl(&systimer_base->timer0control), \ + &systimer_base->timer0control); + + reset_timer_masked(); +} + +/* Use the ARM Watchdog System to cause reset */ +void reset_cpu(ulong addr) +{ + writeb(WDT_EN, &wdt_base->wdogcontrol); + writel(WDT_RESET_LOAD, &wdt_base->wdogload); + while (1) + ; +} + +/* + * Delay x useconds AND perserve advance timstamp value + * assumes timer is ticking at 1 msec + */ +void udelay(ulong usec) +{ + ulong tmo, tmp; + + tmo = usec / 1000; + tmp = get_timer(0); /* get current timestamp */ + + /* + * If setting this forward will roll time stamp then + * reset "advancing" timestamp to 0 and set lastdec value + * otherwise set the advancing stamp to the wake up time + */ + if ((tmo + tmp + 1) < tmp) + reset_timer_masked(); + else + tmo += tmp; + + while (get_timer_masked() < tmo) + ; /* loop till wakeup event */ +} + +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +void reset_timer_masked(void) +{ + lastdec = readl(&systimer_base->timer0value) / 1000; + timestamp = 0; +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer_masked(void) +{ + ulong now = readl(&systimer_base->timer0value) / 1000; + + if (lastdec >= now) { /* normal mode (non roll) */ + timestamp += lastdec - now; + } else { /* count down timer overflowed */ + /* + * nts = ts + ld - now + * ts = old stamp, ld = time before passing through - 1 + * now = amount of time after passing though - 1 + * nts = new "advancing time stamp" + */ + timestamp += lastdec + SYSTIMER_RELOAD - now; + } + lastdec = now; + + return timestamp; +} + +void lowlevel_init(void) +{ +} + +ulong get_board_rev(void){ + return readl((u32 *)SYS_ID); +} diff --git a/board/siemens/CCM/config.mk b/board/armltd/vexpress/config.mk index 9c72c79d3b..2d797d7151 100644 --- a/board/siemens/CCM/config.mk +++ b/board/armltd/vexpress/config.mk @@ -1,7 +1,4 @@ # -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# # See file CREDITS for list of people who contributed to this # project. # @@ -12,7 +9,7 @@ # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License @@ -20,9 +17,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # - -# -# TQM8xxL boards +# Linux-Kernel is expected to be at 0x60008000 # - -TEXT_BASE = 0x40000000 +TEXT_BASE = 0x60800000 +LDSCRIPT := $(SRCTREE)/board/armltd/vexpress/u-boot.lds diff --git a/board/armltd/vexpress/u-boot.lds b/board/armltd/vexpress/u-boot.lds new file mode 100644 index 0000000000..5ac62f2c24 --- /dev/null +++ b/board/armltd/vexpress/u-boot.lds @@ -0,0 +1,65 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + . = ALIGN(4); + .text : + { + arch/arm/cpu/armv7/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata))) } + + . = ALIGN(4); + .data : { *(.data) + __datarel_start = .; + *(.data.rel) + __datarelrolocal_start = .; + *(.data.rel.ro.local) + __datarellocal_start = .; + *(.data.rel.local) + __datarelro_start = .; + *(.data.rel.ro) + } + + __got_start = .; + . = ALIGN(4); + .got : { *(.got) } + __got_end = .; + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/bct-brettl2/Makefile b/board/bct-brettl2/Makefile new file mode 100644 index 0000000000..cf99d29f1c --- /dev/null +++ b/board/bct-brettl2/Makefile @@ -0,0 +1,51 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o gpio_cfi_flash.o cled.o +COBJS-$(CONFIG_BFIN_MAC) += smsc9303.o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend diff --git a/board/bct-brettl2/bct-brettl2.c b/board/bct-brettl2/bct-brettl2.c new file mode 100644 index 0000000000..de5b9ff0e7 --- /dev/null +++ b/board/bct-brettl2/bct-brettl2.c @@ -0,0 +1,123 @@ +/* + * U-boot - main board file for BCT brettl2 + * + * Copyright (c) 2010 BCT Electronic GmbH + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <config.h> +#include <command.h> +#include <asm/blackfin.h> +#include <asm/portmux.h> +#include <asm/gpio.h> +#include <asm/net.h> +#include <net.h> +#include <netdev.h> +#include <miiphy.h> + +#include "../cm-bf537e/gpio_cfi_flash.h" +#include "smsc9303.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + printf("Board: bct-brettl2 board\n"); + printf(" Support: http://www.bct-electronic.com/\n"); + return 0; +} + +#ifdef CONFIG_BFIN_MAC +static void board_init_enetaddr(uchar *mac_addr) +{ + puts("Warning: Generating 'random' MAC address\n"); + bfin_gen_rand_mac(mac_addr); + eth_setenv_enetaddr("ethaddr", mac_addr); +} + +int board_eth_init(bd_t *bis) +{ + int retry = 3; + int ret; + + ret = bfin_EMAC_initialize(bis); + + uchar enetaddr[6]; + if (eth_getenv_enetaddr("ethaddr", enetaddr)) { + printf("setting MAC %pM\n", enetaddr); + } + puts(" "); + + puts("initialize SMSC LAN9303i ethernet switch\n"); + + while (retry-- > 0) { + if (init_smsc9303i_mii()) + return ret; + } + + return ret; +} +#endif + +static void init_tlv320aic31(void) +{ + puts("Audio: setup TIMER0 to enable 16.384 MHz clock for tlv320aic31\n"); + peripheral_request(P_TMR0, "tlv320aic31 clock"); + bfin_write_TIMER0_CONFIG(0x020d); + bfin_write_TIMER0_PERIOD(0x0008); + bfin_write_TIMER0_WIDTH(0x0008/2); + bfin_write_TIMER_ENABLE(bfin_read_TIMER_ENABLE() | 1); + SSYNC(); + udelay(10000); + + puts(" resetting tlv320aic31\n"); + + gpio_request(GPIO_PF2, "tlv320aic31"); + gpio_direction_output(GPIO_PF2, 0); + udelay(10000); + gpio_direction_output(GPIO_PF2, 1); + udelay(10000); + gpio_free(GPIO_PF2); +} + +static void init_mute_pin(void) +{ + printf(" unmute class D amplifier\n"); + + gpio_request(GPIO_PF5, "mute"); + gpio_direction_output(GPIO_PF5, 1); + gpio_free(GPIO_PF5); +} + +/* sometimes LEDs (speech, status) are still on after reboot, turn 'em off */ +static void turn_leds_off(void) +{ + printf(" turn LEDs off\n"); + + gpio_request(GPIO_PF6, "led"); + gpio_direction_output(GPIO_PF6, 0); + gpio_free(GPIO_PF6); + + gpio_request(GPIO_PF15, "led"); + gpio_direction_output(GPIO_PF15, 0); + gpio_free(GPIO_PF15); +} + +/* miscellaneous platform dependent initialisations */ +int misc_init_r(void) +{ +#ifdef CONFIG_BFIN_MAC + uchar enetaddr[6]; + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) + board_init_enetaddr(enetaddr); +#endif + + gpio_cfi_flash_init(); + init_tlv320aic31(); + init_mute_pin(); + turn_leds_off(); + + return 0; +} diff --git a/board/bct-brettl2/cled.c b/board/bct-brettl2/cled.c new file mode 100644 index 0000000000..9e73c57b87 --- /dev/null +++ b/board/bct-brettl2/cled.c @@ -0,0 +1,32 @@ +/* + * cled.c - control color led + * + * Copyright (c) 2010 BCT Electronic GmbH + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <command.h> +#include <asm/blackfin.h> +#include <asm/io.h> + +int do_cled(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + ulong addr = 0x20000000 + 0x200000; // AMS2 + uchar data; + + if (argc < 2) + return cmd_usage(cmdtp); + + data = simple_strtoul(argv[1], NULL, 10); + outb(data, addr); + + printf("cled, write %02x\n", data); + + return 0; +} + +U_BOOT_CMD(cled, 2, 0, do_cled, + "set/clear color LED", + ""); diff --git a/board/bct-brettl2/config.mk b/board/bct-brettl2/config.mk new file mode 100644 index 0000000000..dfd94569e1 --- /dev/null +++ b/board/bct-brettl2/config.mk @@ -0,0 +1,35 @@ +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# This is not actually used for Blackfin boards so do not change it +#TEXT_BASE = do-not-use-me + +CONFIG_BFIN_CPU = bf536-0.3 + +CFLAGS_lib += -O2 +CFLAGS_lib/lzma += -O2 + +# Set some default LDR flags based on boot mode. +LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/bct-brettl2/gpio_cfi_flash.c b/board/bct-brettl2/gpio_cfi_flash.c new file mode 100644 index 0000000000..b385c7fc0e --- /dev/null +++ b/board/bct-brettl2/gpio_cfi_flash.c @@ -0,0 +1,4 @@ +#define GPIO_PIN_1 GPIO_PG5 +#define GPIO_PIN_2 GPIO_PG6 +#define GPIO_PIN_3 GPIO_PG7 +#include "../cm-bf537e/gpio_cfi_flash.c" diff --git a/board/bct-brettl2/smsc9303.c b/board/bct-brettl2/smsc9303.c new file mode 100644 index 0000000000..15eea7a484 --- /dev/null +++ b/board/bct-brettl2/smsc9303.c @@ -0,0 +1,176 @@ +/* + * smsc9303.c - routines to initialize SMSC 9303 switch + * + * Copyright (c) 2010 BCT Electronic GmbH + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <config.h> +#include <miiphy.h> + +#include <asm/blackfin.h> +#include <asm/gpio.h> + +static int smc9303i_write_mii(unsigned char addr, unsigned char reg, unsigned short data) +{ + const char *devname = miiphy_get_current_dev(); + + if (!devname) + return 0; + + if (miiphy_write(devname, addr, reg, data) != 0) + return 0; + + return 1; +} + +static int smc9303i_write_reg(unsigned short reg, unsigned int data) +{ + const char *devname = miiphy_get_current_dev(); + unsigned char mii_addr = 0x10 | (reg >> 6); + unsigned char mii_reg = (reg & 0x3c) >> 1; + + if (!devname) + return 0; + + if (miiphy_write(devname, mii_addr, mii_reg|0, data & 0xffff) != 0) + return 0; + + if (miiphy_write(devname, mii_addr, mii_reg|1, data >> 16) != 0) + return 0; + + return 1; +} + +static int smc9303i_read_reg(unsigned short reg, unsigned int *data) +{ + const char *devname = miiphy_get_current_dev(); + unsigned char mii_addr = 0x10 | (reg >> 6); + unsigned char mii_reg = (reg & 0x3c) >> 1; + unsigned short tmp1, tmp2; + + if (!devname) + return 0; + + if (miiphy_read(devname, mii_addr, mii_reg|0, &tmp1) != 0) + return 0; + + if (miiphy_read(devname, mii_addr, mii_reg|1, &tmp2) != 0) + return 0; + + *data = (tmp2 << 16) | tmp1; + + return 1; +} + +#if 0 +static int smc9303i_read_mii(unsigned char addr, unsigned char reg, unsigned short *data) +{ + const char *devname = miiphy_get_current_dev(); + + if (!devname) + return 0; + + if (miiphy_read(devname, addr, reg, data) != 0) + return 0; + + return 1; +} +#endif + +typedef struct { + unsigned short reg; + unsigned int value; +} smsc9303i_config_entry1_t; + +static const smsc9303i_config_entry1_t smsc9303i_config_table1[] = +{ + {0x1a0, 0x00000006}, /* Port 1 Manual Flow Control Register */ + {0x1a4, 0x00000006}, /* Port 2 Manual Flow Control Register */ + {0x1a8, 0x00000006}, /* Port 0 Manual Flow Control Register */ +}; + +typedef struct +{ + unsigned char addr; + unsigned char reg; + unsigned short value; +} smsc9303i_config_entry2_t; + +static const smsc9303i_config_entry2_t smsc9303i_config_table2[] = +{ + {0x01, 0x00, 0x0100}, /* Port0 PHY Basic Control Register */ + {0x02, 0x00, 0x1100}, /* Port1 PHY Basic Control Register */ + {0x03, 0x00, 0x1100}, /* Port2 PHY Basic Control Register */ + + {0x01, 0x04, 0x0001}, /* Port0 PHY Auto-Negotiation Advertisement Register */ + {0x02, 0x04, 0x2de1}, /* Port1 PHY Auto-Negotiation Advertisement Register */ + {0x03, 0x04, 0x2de1}, /* Port2 PHY Auto-Negotiation Advertisement Register */ + + {0x01, 0x11, 0x0000}, /* Port0 PHY Mode Control/Status Register */ + {0x02, 0x11, 0x0000}, /* Port1 PHY Mode Control/Status Register */ + {0x03, 0x11, 0x0000}, /* Port2 PHY Mode Control/Status Register */ + + {0x01, 0x12, 0x0021}, /* Port0 PHY Special Modes Register */ + {0x02, 0x12, 0x00e2}, /* Port1 PHY Special Modes Register */ + {0x03, 0x12, 0x00e3}, /* Port2 PHY Special Modes Register */ + {0x01, 0x1b, 0x0000}, /* Port0 PHY Special Control/Status Indication Register */ + {0x02, 0x1b, 0x0000}, /* Port1 PHY Special Control/Status Indication Register */ + {0x03, 0x1b, 0x0000}, /* Port2 PHY Special Control/Status Indication Register */ + {0x01, 0x1e, 0x0000}, /* Port0 PHY Interrupt Source Flags Register */ + {0x02, 0x1e, 0x0000}, /* Port1 PHY Interrupt Source Flags Register */ + {0x03, 0x1e, 0x0000}, /* Port2 PHY Interrupt Source Flags Register */ +}; + +int init_smsc9303i_mii(void) +{ + unsigned int data; + unsigned int i; + + printf(" reset SMSC LAN9303i\n"); + + gpio_request(GPIO_PG10, "smsc9303"); + gpio_direction_output(GPIO_PG10, 0); + udelay(10000); + gpio_direction_output(GPIO_PG10, 1); + udelay(10000); + + gpio_free(GPIO_PG10); + +#if defined(CONFIG_MII_INIT) + mii_init(); +#endif + + printf(" write SMSC LAN9303i configuration\n"); + + if (!smc9303i_read_reg(0x50, &data)) + return 0; + + if ((data >> 16) != 0x9303) { + /* chip id not found */ + printf(" error identifying SMSC LAN9303i\n"); + return 0; + } + + for (i = 0; i < ARRAY_SIZE(smsc9303i_config_table1); i++) { + const smsc9303i_config_entry1_t *entry = &smsc9303i_config_table1[i]; + + if (!smc9303i_write_reg(entry->reg, entry->value)) { + printf(" error writing SMSC LAN9303i configuration\n"); + return 0; + } + } + + for (i = 0; i < ARRAY_SIZE(smsc9303i_config_table2); i++) { + const smsc9303i_config_entry2_t *entry = &smsc9303i_config_table2[i]; + + if (!smc9303i_write_mii(entry->addr, entry->reg, entry->value)) { + printf(" error writing SMSC LAN9303i configuration\n"); + return 0; + } + } + + return 1; +} diff --git a/board/bct-brettl2/smsc9303.h b/board/bct-brettl2/smsc9303.h new file mode 100644 index 0000000000..a4ba40ef73 --- /dev/null +++ b/board/bct-brettl2/smsc9303.h @@ -0,0 +1,9 @@ +/* + * smsc9303.h - routines to initialize SMSC 9303 switch + * + * Copyright (c) 2010 BCT Electronic GmbH + * + * Licensed under the GPL-2 or later. + */ + +int init_smsc9303i_mii(void); diff --git a/board/bf518f-ezbrd/config.mk b/board/bf518f-ezbrd/config.mk index 3f9d41f371..30b92a3c43 100644 --- a/board/bf518f-ezbrd/config.mk +++ b/board/bf518f-ezbrd/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf518-0.0 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/bf526-ezbrd/config.mk b/board/bf526-ezbrd/config.mk index 3f9d41f371..aaf4541feb 100644 --- a/board/bf526-ezbrd/config.mk +++ b/board/bf526-ezbrd/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf526-0.0 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/bf527-ad7160-eval/bf527-ad7160-eval.c b/board/bf527-ad7160-eval/bf527-ad7160-eval.c index b06d5ab2e8..ea405b639d 100644 --- a/board/bf527-ad7160-eval/bf527-ad7160-eval.c +++ b/board/bf527-ad7160-eval/bf527-ad7160-eval.c @@ -20,6 +20,6 @@ int checkboard(void) int misc_init_r(void) { /* CLKIN Buffer Output Enable */ - *pVR_CTL |= CLKBUFOE; + bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE); return 0; } diff --git a/board/bf527-ad7160-eval/config.mk b/board/bf527-ad7160-eval/config.mk index 3f9d41f371..9784810af7 100644 --- a/board/bf527-ad7160-eval/config.mk +++ b/board/bf527-ad7160-eval/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf527-0.2 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/bf527-ezkit/config.mk b/board/bf527-ezkit/config.mk index 3f9d41f371..78eebff324 100644 --- a/board/bf527-ezkit/config.mk +++ b/board/bf527-ezkit/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf527-0.0 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/bf527-ezkit/video.c b/board/bf527-ezkit/video.c index 51bdf02041..87e7658b4d 100644 --- a/board/bf527-ezkit/video.c +++ b/board/bf527-ezkit/video.c @@ -162,12 +162,12 @@ static int lq035q1_control(unsigned char reg, unsigned short value) /* enable and disable PPI functions */ void EnablePPI(void) { - *pPPI_CONTROL |= PORT_EN; + bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN); } void DisablePPI(void) { - *pPPI_CONTROL &= ~PORT_EN; + bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() & ~PORT_EN); } void Init_Ports(void) @@ -182,119 +182,123 @@ void Init_Ports(void) void Init_PPI(void) { - *pPPI_DELAY = H_START; - *pPPI_COUNT = (H_ACTPIX-1); - *pPPI_FRAME = V_LINES; + bfin_write_PPI_DELAY(H_START); + bfin_write_PPI_COUNT(H_ACTPIX - 1); + bfin_write_PPI_FRAME(V_LINES); /* PPI control, to be replaced with definitions */ - *pPPI_CONTROL = PPI_TX_MODE | /* output mode , PORT_DIR */ + bfin_write_PPI_CONTROL( + PPI_TX_MODE | /* output mode , PORT_DIR */ PPI_XFER_TYPE_11 | /* sync mode XFR_TYPE */ PPI_PORT_CFG_01 | /* two frame sync PORT_CFG */ PPI_PACK_EN | /* packing enabled PACK_EN */ - PPI_POLS_1; /* faling edge syncs POLS */ + PPI_POLS_1 /* faling edge syncs POLS */ + ); } void Init_DMA(void *dst) { - *pDMA0_START_ADDR = dst; + bfin_write_DMA0_START_ADDR(dst); /* X count */ - *pDMA0_X_COUNT = H_ACTPIX / 2; - *pDMA0_X_MODIFY = DMA_BUS_SIZE / 8; + bfin_write_DMA0_X_COUNT(H_ACTPIX / 2); + bfin_write_DMA0_X_MODIFY(DMA_BUS_SIZE / 8); /* Y count */ - *pDMA0_Y_COUNT = V_LINES; - *pDMA0_Y_MODIFY = DMA_BUS_SIZE / 8; + bfin_write_DMA0_Y_COUNT(V_LINES); + bfin_write_DMA0_Y_MODIFY(DMA_BUS_SIZE / 8); /* DMA Config */ - *pDMA0_CONFIG = + bfin_write_DMA0_CONFIG( WDSIZE_16 | /* 16 bit DMA */ DMA2D | /* 2D DMA */ - FLOW_AUTO; /* autobuffer mode */ + FLOW_AUTO /* autobuffer mode */ + ); } - void EnableDMA(void) { - *pDMA0_CONFIG |= DMAEN; + bfin_write_DMA0_CONFIG(bfin_read_DMA0_CONFIG() | DMAEN); } void DisableDMA(void) { - *pDMA0_CONFIG &= ~DMAEN; + bfin_write_DMA0_CONFIG(bfin_read_DMA0_CONFIG() & ~DMAEN); } - /* Init TIMER0 as Frame Sync 1 generator */ void InitTIMER0(void) { - *pTIMER_DISABLE |= TIMDIS0; /* disable Timer */ + bfin_write_TIMER_DISABLE(TIMDIS0); /* disable Timer */ SSYNC(); - *pTIMER_STATUS |= TIMIL0 | TOVF_ERR0 | TRUN0; /* clear status */ + bfin_write_TIMER_STATUS(TIMIL0 | TOVF_ERR0 | TRUN0); /* clear status */ SSYNC(); - *pTIMER0_PERIOD = H_PERIOD; + bfin_write_TIMER0_PERIOD(H_PERIOD); SSYNC(); - *pTIMER0_WIDTH = H_PULSE; + bfin_write_TIMER0_WIDTH(H_PULSE); SSYNC(); - *pTIMER0_CONFIG = PWM_OUT | + bfin_write_TIMER0_CONFIG( + PWM_OUT | PERIOD_CNT | TIN_SEL | CLK_SEL | - EMU_RUN; + EMU_RUN + ); SSYNC(); } void EnableTIMER0(void) { - *pTIMER_ENABLE |= TIMEN0; + bfin_write_TIMER_ENABLE(TIMEN0); SSYNC(); } void DisableTIMER0(void) { - *pTIMER_DISABLE |= TIMDIS0; + bfin_write_TIMER_DISABLE(TIMDIS0); SSYNC(); } void InitTIMER1(void) { - *pTIMER_DISABLE |= TIMDIS1; /* disable Timer */ + bfin_write_TIMER_DISABLE(TIMDIS1); /* disable Timer */ SSYNC(); - *pTIMER_STATUS |= TIMIL1 | TOVF_ERR1 | TRUN1; /* clear status */ + bfin_write_TIMER_STATUS(TIMIL1 | TOVF_ERR1 | TRUN1); /* clear status */ SSYNC(); - - *pTIMER1_PERIOD = V_PERIOD; + bfin_write_TIMER1_PERIOD(V_PERIOD); SSYNC(); - *pTIMER1_WIDTH = V_PULSE; + bfin_write_TIMER1_WIDTH(V_PULSE); SSYNC(); - *pTIMER1_CONFIG = PWM_OUT | + bfin_write_TIMER1_CONFIG( + PWM_OUT | PERIOD_CNT | TIN_SEL | CLK_SEL | - EMU_RUN; + EMU_RUN + ); SSYNC(); } void EnableTIMER1(void) { - *pTIMER_ENABLE |= TIMEN1; + bfin_write_TIMER_ENABLE(TIMEN1); SSYNC(); } void DisableTIMER1(void) { - *pTIMER_DISABLE |= TIMDIS1; + bfin_write_TIMER_DISABLE(TIMDIS1); SSYNC(); } void EnableTIMER12(void) { - *pTIMER_ENABLE |= TIMEN1 | TIMEN0; + bfin_write_TIMER_ENABLE(TIMEN1 | TIMEN0); SSYNC(); } diff --git a/board/bf527-sdp/Makefile b/board/bf527-sdp/Makefile new file mode 100644 index 0000000000..f2bd2c247d --- /dev/null +++ b/board/bf527-sdp/Makefile @@ -0,0 +1,54 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/bf527-sdp/bf527-sdp.c b/board/bf527-sdp/bf527-sdp.c new file mode 100644 index 0000000000..504869d72a --- /dev/null +++ b/board/bf527-sdp/bf527-sdp.c @@ -0,0 +1,32 @@ +/* + * U-boot - main board file + * + * Copyright (c) 2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <asm/blackfin.h> +#include <asm/gpio.h> +#include <asm/mach-common/bits/pll.h> + +int checkboard(void) +{ + printf("Board: ADI BF527 SDP board\n"); + printf(" Support: http://blackfin.uclinux.org/\n"); + + /* Enable access to parallel flash */ + gpio_request(GPIO_PG0, "parallel-flash"); + gpio_direction_output(GPIO_PG0, 0); + + return 0; +} + +int misc_init_r(void) +{ + /* CLKIN Buffer Output Enable */ + bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE); + + return 0; +} diff --git a/board/bf527-sdp/config.mk b/board/bf527-sdp/config.mk new file mode 100644 index 0000000000..744e7a5d0d --- /dev/null +++ b/board/bf527-sdp/config.mk @@ -0,0 +1,36 @@ +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# This is not actually used for Blackfin boards so do not change it +#TEXT_BASE = do-not-use-me + +CONFIG_BFIN_CPU = bf527-0.2 + +CFLAGS_lib_generic += -O2 +CFLAGS_lzma += -O2 + +# Set some default LDR flags based on boot mode. +LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 6 +LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/bf533-ezkit/config.mk b/board/bf533-ezkit/config.mk index bc046f129f..60ec6b6c14 100644 --- a/board/bf533-ezkit/config.mk +++ b/board/bf533-ezkit/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf533-0.3 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/bf533-stamp/config.mk b/board/bf533-stamp/config.mk index bc046f129f..60ec6b6c14 100644 --- a/board/bf533-stamp/config.mk +++ b/board/bf533-stamp/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf533-0.3 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/bf537-minotaur/config.mk b/board/bf537-minotaur/config.mk index d8308433b0..59e9a9c447 100644 --- a/board/bf537-minotaur/config.mk +++ b/board/bf537-minotaur/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf537-0.2 + # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6 LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/bf537-pnav/config.mk b/board/bf537-pnav/config.mk index eaa09ff795..ce8ef3b499 100644 --- a/board/bf537-pnav/config.mk +++ b/board/bf537-pnav/config.mk @@ -26,5 +26,7 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf537-0.2 + # Set some default LDR flags based on boot mode. LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/bf537-srv1/config.mk b/board/bf537-srv1/config.mk index d8308433b0..59e9a9c447 100644 --- a/board/bf537-srv1/config.mk +++ b/board/bf537-srv1/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf537-0.2 + # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6 LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/bf537-stamp/config.mk b/board/bf537-stamp/config.mk index 5766829115..3bac0adf3b 100644 --- a/board/bf537-stamp/config.mk +++ b/board/bf537-stamp/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf537-0.2 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/bf537-stamp/post-memory.c b/board/bf537-stamp/post-memory.c index 4daea627ef..49022dc930 100644 --- a/board/bf537-stamp/post-memory.c +++ b/board/bf537-stamp/post-memory.c @@ -97,19 +97,19 @@ void post_init_uart(int sclk) for (divisor = 0; sclk > 0; divisor++) sclk -= 57600 * 16; - *pPORTF_FER = 0x000F; - *pPORTH_FER = 0xFFFF; + bfin_write_PORTF_FER(0x000F); + bfin_write_PORTH_FER(0xFFFF); - *pUART_GCTL = 0x00; - *pUART_LCR = 0x83; + bfin_write_UART_GCTL(0x00); + bfin_write_UART_LCR(0x83); SSYNC(); - *pUART_DLL = (divisor & 0xFF); + bfin_write_UART_DLL(divisor & 0xFF); SSYNC(); - *pUART_DLH = ((divisor >> 8) & 0xFF); + bfin_write_UART_DLH((divisor >> 8) & 0xFF); SSYNC(); - *pUART_LCR = 0x03; + bfin_write_UART_LCR(0x03); SSYNC(); - *pUART_GCTL = 0x01; + bfin_write_UART_GCTL(0x01); SSYNC(); } @@ -121,8 +121,8 @@ void post_out_buff(char *buff) ; i = 0; while ((buff[i] != '\0') && (i != 100)) { - while (!(*pUART_LSR & 0x20)) ; - *pUART_THR = buff[i]; + while (!(bfin_read_pUART_LSR() & 0x20)) ; + bfin_write_UART_THR(buff[i]); SSYNC(); i++; } @@ -138,15 +138,15 @@ int post_key_pressed(void) int i, n; unsigned short value; - *pPORTF_FER &= ~PF5; - *pPORTFIO_DIR &= ~PF5; - *pPORTFIO_INEN |= PF5; + bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~PF5); + bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() & ~PF5); + bfin_write_PORTFIO_INEN(bfin_read_PORTFIO_INEN() | PF5); SSYNC(); post_out_buff("########Press SW10 to enter Memory POST########: 3\0"); for (i = 0; i < KEY_LOOP; i++) { - value = *pPORTFIO & PF5; - if (*pUART0_RBR == 0x0D) { + value = bfin_read_PORTFIO() & PF5; + if (bfin_read_UART0_RBR() == 0x0D) { value = 0; goto key_pressed; } @@ -158,8 +158,8 @@ int post_key_pressed(void) post_out_buff("\b2\0"); for (i = 0; i < KEY_LOOP; i++) { - value = *pPORTFIO & PF5; - if (*pUART0_RBR == 0x0D) { + value = bfin_read_PORTFIO() & PF5; + if (bfin_read_UART0_RBR() == 0x0D) { value = 0; goto key_pressed; } @@ -171,8 +171,8 @@ int post_key_pressed(void) post_out_buff("\b1\0"); for (i = 0; i < KEY_LOOP; i++) { - value = *pPORTFIO & PF5; - if (*pUART0_RBR == 0x0D) { + value = bfin_read_PORTFIO() & PF5; + if (bfin_read_UART0_RBR() == 0x0D) { value = 0; goto key_pressed; } @@ -193,13 +193,13 @@ int post_key_pressed(void) void post_init_pll(int mult, int div) { - *pSIC_IWR = 0x01; - *pPLL_CTL = (mult << 9); - *pPLL_DIV = div; + bfin_write_SIC_IWR(0x01); + bfin_write_PLL_CTL((mult << 9)); + bfin_write_PLL_DIV(div); asm("CLI R2;"); asm("IDLE;"); asm("STI R2;"); - while (!(*pPLL_STAT & 0x20)) ; + while (!(bfin_read_PLL_STAT() & 0x20)) ; } int post_init_sdram(int sclk) @@ -302,15 +302,15 @@ int post_init_sdram(int sclk) SSYNC(); - *pEBIU_SDGCTL |= 0x1000000; + bfin_write_EBIU_SDGCTL(bfin_write_EBIU_SDGCTL() | 0x1000000); /* Set the SDRAM Refresh Rate control register based on SSCLK value */ - *pEBIU_SDRRC = mem_SDRRC; + bfin_write_EBIU_SDRRC(mem_SDRRC); /* SDRAM Memory Bank Control Register */ - *pEBIU_SDBCTL = mem_SDBCTL; + bfin_write_EBIU_SDBCTL(mem_SDBCTL); /* SDRAM Memory Global Control Register */ - *pEBIU_SDGCTL = mem_SDGCTL; + bfin_write_EBIU_SDGCTL(mem_SDGCTL); SSYNC(); return mem_SDRRC; } diff --git a/board/bf537-stamp/post.c b/board/bf537-stamp/post.c index c546ab6cb6..60eed5f68a 100644 --- a/board/bf537-stamp/post.c +++ b/board/bf537-stamp/post.c @@ -12,6 +12,7 @@ #include <config.h> #include <command.h> #include <asm/blackfin.h> +#include <asm/gpio.h> /* Using sw10-PF5 as the hotkey */ int post_hotkeys_pressed(void) @@ -20,14 +21,13 @@ int post_hotkeys_pressed(void) int i; unsigned short value; - *pPORTF_FER &= ~PF5; - *pPORTFIO_DIR &= ~PF5; - *pPORTFIO_INEN |= PF5; + gpio_request(GPIO_PF5, "post"); + gpio_direction_input(GPIO_PF5); printf("########Press SW10 to enter Memory POST########: %2d ", delay); while (delay--) { for (i = 0; i < 100; i++) { - value = *pPORTFIO & PF5; + value = gpio_get_value(GPIO_PF5); if (value != 0) { break; } @@ -43,6 +43,8 @@ int post_hotkeys_pressed(void) printf("Hotkey has been pressed, Enter POST . . . . . .\n"); return 1; } + + gpio_free(GPIO_PF5); } int uart_post_test(int flags) @@ -106,34 +108,24 @@ int flash_post_test(int flags) ****************************************************/ int led_post_test(int flags) { - *pPORTF_FER &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11); - *pPORTFIO_DIR |= PF6 | PF7 | PF8 | PF9 | PF10 | PF11; - *pPORTFIO_INEN &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11); - *pPORTFIO &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11); - udelay(1000000); - printf("LED1 on"); - *pPORTFIO |= PF6; - udelay(1000000); - printf("\b\b\b\b\b\b\b"); - printf("LED2 on"); - *pPORTFIO |= PF7; - udelay(1000000); - printf("\b\b\b\b\b\b\b"); - printf("LED3 on"); - *pPORTFIO |= PF8; - udelay(1000000); - printf("\b\b\b\b\b\b\b"); - printf("LED4 on"); - *pPORTFIO |= PF9; - udelay(1000000); - printf("\b\b\b\b\b\b\b"); - printf("LED5 on"); - *pPORTFIO |= PF10; - udelay(1000000); - printf("\b\b\b\b\b\b\b"); - printf("lED6 on"); - *pPORTFIO |= PF11; - printf("\b\b\b\b\b\b\b "); + unsigned int leds[] = { + GPIO_PF6, GPIO_PF7, GPIO_PF8, + GPIO_PF9, GPIO_PF10, GPIO_PF11, + }; + int i; + + for (i = 0; i < ARRAY_SIZE(leds); ++i) { + gpio_request(leds[i], "post"); + gpio_direction_output(leds[i], 0); + + printf("LED%i on", i + 1); + gpio_set_value(leds[i], 1); + udelay(1000000); + printf("\b\b\b\b\b\b\b"); + + gpio_free(leds[i]); + } + return 0; } @@ -143,88 +135,40 @@ int led_post_test(int flags) ************************************************/ int button_post_test(int flags) { + unsigned int buttons[] = { + GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, + }; + unsigned int sws[] = { 13, 12, 11, 10, }; int i, delay = 5; unsigned short value = 0; int result = 0; - *pPORTF_FER &= ~(PF5 | PF4 | PF3 | PF2); - *pPORTFIO_DIR &= ~(PF5 | PF4 | PF3 | PF2); - *pPORTFIO_INEN |= (PF5 | PF4 | PF3 | PF2); + for (i = 0; i < ARRAY_SIZE(buttons); ++i) { + gpio_request(buttons[i], "post"); + gpio_direction_input(buttons[i]); - printf("\n--------Press SW10: %2d ", delay); - while (delay--) { - for (i = 0; i < 100; i++) { - value = *pPORTFIO & PF5; - if (value != 0) { - break; + delay = 5; + printf("\n--------Press SW%i: %2d ", sws[i], delay); + while (delay--) { + for (i = 0; i < 100; i++) { + value = gpio_get_value(buttons[i]); + if (value != 0) + break; + udelay(10000); } - udelay(10000); + printf("\b\b\b%2d ", delay); } - printf("\b\b\b%2d ", delay); - } - if (value != 0) - printf("\b\bOK"); - else { - result = -1; - printf("\b\bfailed"); - } - - delay = 5; - printf("\n--------Press SW11: %2d ", delay); - while (delay--) { - for (i = 0; i < 100; i++) { - value = *pPORTFIO & PF4; - if (value != 0) { - break; - } - udelay(10000); + if (value != 0) + puts("\b\bOK"); + else { + result = -1; + puts("\b\bfailed"); } - printf("\b\b\b%2d ", delay); - } - if (value != 0) - printf("\b\bOK"); - else { - result = -1; - printf("\b\bfailed"); - } - delay = 5; - printf("\n--------Press SW12: %2d ", delay); - while (delay--) { - for (i = 0; i < 100; i++) { - value = *pPORTFIO & PF3; - if (value != 0) { - break; - } - udelay(10000); - } - printf("\b\b\b%2d ", delay); - } - if (value != 0) - printf("\b\bOK"); - else { - result = -1; - printf("\b\bfailed"); + gpio_free(buttons[i]); } - delay = 5; - printf("\n--------Press SW13: %2d ", delay); - while (delay--) { - for (i = 0; i < 100; i++) { - value = *pPORTFIO & PF2; - if (value != 0) { - break; - } - udelay(10000); - } - printf("\b\b\b%2d ", delay); - } - if (value != 0) - printf("\b\bOK"); - else { - result = -1; - printf("\b\bfailed"); - } - printf("\n"); + puts("\n"); + return result; } diff --git a/board/bf538f-ezkit/config.mk b/board/bf538f-ezkit/config.mk index bc046f129f..170a2d56db 100644 --- a/board/bf538f-ezkit/config.mk +++ b/board/bf538f-ezkit/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf538-0.4 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/bf548-ezkit/config.mk b/board/bf548-ezkit/config.mk index ce96c0d479..ec3c28e0b7 100644 --- a/board/bf548-ezkit/config.mk +++ b/board/bf548-ezkit/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf548-0.0 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/bf548-ezkit/video.c b/board/bf548-ezkit/video.c index cde877aa0c..9bcf935568 100644 --- a/board/bf548-ezkit/video.c +++ b/board/bf548-ezkit/video.c @@ -153,24 +153,25 @@ void Init_DMA(void *dst) { #if defined(CONFIG_DEB_DMA_URGENT) - *pEBIU_DDRQUE |= DEB2_URGENT; + bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | DEB2_URGENT); #endif - *pDMA12_START_ADDR = dst; + bfin_write_DMA12_START_ADDR(dst); /* X count */ - *pDMA12_X_COUNT = (LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE; - *pDMA12_X_MODIFY = DMA_BUS_SIZE / 8; + bfin_write_DMA12_X_COUNT((LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE); + bfin_write_DMA12_X_MODIFY(DMA_BUS_SIZE / 8); /* Y count */ - *pDMA12_Y_COUNT = LCD_Y_RES; - *pDMA12_Y_MODIFY = DMA_BUS_SIZE / 8; + bfin_write_DMA12_Y_COUNT(LCD_Y_RES); + bfin_write_DMA12_Y_MODIFY(DMA_BUS_SIZE / 8); /* DMA Config */ - *pDMA12_CONFIG = + bfin_write_DMA12_CONFIG( WDSIZE_32 | /* 32 bit DMA */ DMA2D | /* 2D DMA */ - FLOW_AUTO; /* autobuffer mode */ + FLOW_AUTO /* autobuffer mode */ + ); } void Init_Ports(void) @@ -194,12 +195,12 @@ void Init_Ports(void) void EnableDMA(void) { - *pDMA12_CONFIG |= DMAEN; + bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() | DMAEN); } void DisableDMA(void) { - *pDMA12_CONFIG &= ~DMAEN; + bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() & ~DMAEN); } /* enable and disable PPI functions */ diff --git a/board/bf561-acvilon/config.mk b/board/bf561-acvilon/config.mk index a90b193388..221de6524f 100644 --- a/board/bf561-acvilon/config.mk +++ b/board/bf561-acvilon/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf561-0.5 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/bf561-ezkit/config.mk b/board/bf561-ezkit/config.mk index a90b193388..ff19190a26 100644 --- a/board/bf561-ezkit/config.mk +++ b/board/bf561-ezkit/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf561-0.3 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/blackstamp/config.mk b/board/blackstamp/config.mk index eaa09ff795..5035cb9c58 100644 --- a/board/blackstamp/config.mk +++ b/board/blackstamp/config.mk @@ -26,5 +26,7 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf532-0.5 + # Set some default LDR flags based on boot mode. LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/blackvme/Makefile b/board/blackvme/Makefile new file mode 100644 index 0000000000..f2bd2c247d --- /dev/null +++ b/board/blackvme/Makefile @@ -0,0 +1,54 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/blackvme/blackvme.c b/board/blackvme/blackvme.c new file mode 100644 index 0000000000..eccdaf3a48 --- /dev/null +++ b/board/blackvme/blackvme.c @@ -0,0 +1,31 @@ +/* U-boot - blackvme.c board specific routines + * (c) Wojtek Skulski 2010 info@skutek.com + * Board info: http://www.skutek.com + * Copyright (c) 2005-2009 Analog Devices Inc. + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <netdev.h> + +int checkboard(void) +{ + printf("Board: BlackVME\n"); + printf("Support: http://www.skutek.com/\n"); + return 0; +} + +#ifdef CONFIG_DRIVER_AX88180 +/* + * The ax88180 driver had to be patched to work around a bug + * in Marvell 88E1111 B2 silicon. E-mail me for explanations. + */ +int board_eth_init(bd_t *bis) +{ + return ax88180_initialize(bis); +} +#endif /* CONFIG_DRIVER_AX88180 */ diff --git a/board/siemens/pcu_e/config.mk b/board/blackvme/config.mk index 10f37734ae..8d0fe3934d 100644 --- a/board/siemens/pcu_e/config.mk +++ b/board/blackvme/config.mk @@ -1,4 +1,6 @@ # +# Copyright (c) 2005-2008 Analog Device Inc. +# # (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # @@ -21,8 +23,10 @@ # MA 02111-1307 USA # -# -# Siemens PCU E Boards -# +# This is not actually used for Blackfin boards so do not change it +#TEXT_BASE = do-not-use-me + +CONFIG_BFIN_CPU = bf561-0.5 -TEXT_BASE = 0xFFF00000 +# Set some default LDR flags based on boot mode. +LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/cm-bf527/cm-bf527.c b/board/cm-bf527/cm-bf527.c index b6815b1ccd..a5f70a4f83 100644 --- a/board/cm-bf527/cm-bf527.c +++ b/board/cm-bf527/cm-bf527.c @@ -13,7 +13,7 @@ #include <asm/blackfin.h> #include <asm/net.h> #include <asm/mach-common/bits/otp.h> -#include "gpio_cfi_flash.h" +#include "../cm-bf537e/gpio_cfi_flash.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/cm-bf527/config.mk b/board/cm-bf527/config.mk index 3f9d41f371..78eebff324 100644 --- a/board/cm-bf527/config.mk +++ b/board/cm-bf527/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf527-0.0 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/cm-bf527/gpio_cfi_flash.c b/board/cm-bf527/gpio_cfi_flash.c index f8ccc078ec..6e62fff230 100644 --- a/board/cm-bf527/gpio_cfi_flash.c +++ b/board/cm-bf527/gpio_cfi_flash.c @@ -1,60 +1,3 @@ -/* - * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support - * - * Copyright (c) 2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <common.h> -#include <asm/blackfin.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include "gpio_cfi_flash.h" - -#define GPIO_PIN_1 GPIO_PH9 -#define GPIO_MASK_1 (1 << 21) -#define GPIO_PIN_2 GPIO_PG11 -#define GPIO_MASK_2 (1 << 22) -#define GPIO_MASK (GPIO_MASK_1 | GPIO_MASK_2) - -void *gpio_cfi_flash_swizzle(void *vaddr) -{ - unsigned long addr = (unsigned long)vaddr; - - gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1); - -#ifdef GPIO_MASK_2 - gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2); -#endif - - SSYNC(); - - return (void *)(addr & ~GPIO_MASK); -} - -#define __raw_writeq(value, addr) *(volatile u64 *)addr = value -#define __raw_readq(addr) *(volatile u64 *)addr - -#define MAKE_FLASH(size, sfx) \ -void flash_write##size(u##size value, void *addr) \ -{ \ - __raw_write##sfx(value, gpio_cfi_flash_swizzle(addr)); \ -} \ -u##size flash_read##size(void *addr) \ -{ \ - return __raw_read##sfx(gpio_cfi_flash_swizzle(addr)); \ -} -MAKE_FLASH(8, b) /* flash_write8() flash_read8() */ -MAKE_FLASH(16, w) /* flash_write16() flash_read16() */ -MAKE_FLASH(32, l) /* flash_write32() flash_read32() */ -MAKE_FLASH(64, q) /* flash_write64() flash_read64() */ - -void gpio_cfi_flash_init(void) -{ - gpio_request(GPIO_PIN_1, "gpio_cfi_flash"); -#ifdef GPIO_MASK_2 - gpio_request(GPIO_PIN_2, "gpio_cfi_flash"); -#endif - gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE); -} +#define GPIO_PIN_1 GPIO_PH9 +#define GPIO_PIN_2 GPIO_PG11 +#include "../cm-bf537e/gpio_cfi_flash.c" diff --git a/board/cm-bf527/gpio_cfi_flash.h b/board/cm-bf527/gpio_cfi_flash.h deleted file mode 100644 index 5211e972ad..0000000000 --- a/board/cm-bf527/gpio_cfi_flash.h +++ /dev/null @@ -1,10 +0,0 @@ -/* - * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support - * - * Copyright (c) 2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -void *gpio_cfi_flash_swizzle(void *vaddr); -void gpio_cfi_flash_init(void); diff --git a/board/cm-bf533/config.mk b/board/cm-bf533/config.mk index bc046f129f..60ec6b6c14 100644 --- a/board/cm-bf533/config.mk +++ b/board/cm-bf533/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf533-0.3 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/cm-bf537e/config.mk b/board/cm-bf537e/config.mk index bc046f129f..1281da4bef 100644 --- a/board/cm-bf537e/config.mk +++ b/board/cm-bf537e/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf537-0.2 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/cm-bf537e/gpio_cfi_flash.c b/board/cm-bf537e/gpio_cfi_flash.c index 79ee844135..1075cc4112 100644 --- a/board/cm-bf537e/gpio_cfi_flash.c +++ b/board/cm-bf537e/gpio_cfi_flash.c @@ -1,7 +1,7 @@ /* * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support * - * Copyright (c) 2009 Analog Devices Inc. + * Copyright (c) 2009-2010 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ @@ -12,9 +12,22 @@ #include <asm/io.h> #include "gpio_cfi_flash.h" +/* Allow this driver to be shared among boards */ +#ifndef GPIO_PIN_1 #define GPIO_PIN_1 GPIO_PF4 +#endif #define GPIO_MASK_1 (1 << 21) -#define GPIO_MASK (GPIO_MASK_1) +#ifndef GPIO_PIN_2 +#define GPIO_MASK_2 (0) +#else +#define GPIO_MASK_2 (1 << 22) +#endif +#ifndef GPIO_PIN_3 +#define GPIO_MASK_3 (0) +#else +#define GPIO_MASK_3 (1 << 23) +#endif +#define GPIO_MASK (GPIO_MASK_1 | GPIO_MASK_2 | GPIO_MASK_3) void *gpio_cfi_flash_swizzle(void *vaddr) { @@ -22,11 +35,16 @@ void *gpio_cfi_flash_swizzle(void *vaddr) gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1); -#ifdef GPIO_MASK_2 +#ifdef GPIO_PIN_2 gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2); #endif +#ifdef GPIO_PIN_3 + gpio_set_value(GPIO_PIN_3, addr & GPIO_MASK_3); +#endif + SSYNC(); + udelay(1); return (void *)(addr & ~GPIO_MASK); } @@ -51,8 +69,13 @@ MAKE_FLASH(64, q) /* flash_write64() flash_read64() */ void gpio_cfi_flash_init(void) { gpio_request(GPIO_PIN_1, "gpio_cfi_flash"); -#ifdef GPIO_MASK_2 + gpio_direction_output(GPIO_PIN_1, 0); +#ifdef GPIO_PIN_2 gpio_request(GPIO_PIN_2, "gpio_cfi_flash"); + gpio_direction_output(GPIO_PIN_2, 0); +#endif +#ifdef GPIO_PIN_3 + gpio_request(GPIO_PIN_3, "gpio_cfi_flash"); + gpio_direction_output(GPIO_PIN_3, 0); #endif - gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE); } diff --git a/board/cm-bf537u/cm-bf537u.c b/board/cm-bf537u/cm-bf537u.c index 92fa5a0993..4b7e8642c9 100644 --- a/board/cm-bf537u/cm-bf537u.c +++ b/board/cm-bf537u/cm-bf537u.c @@ -13,7 +13,7 @@ #include <netdev.h> #include <asm/blackfin.h> #include <asm/net.h> -#include "gpio_cfi_flash.h" +#include "../cm-bf537e/gpio_cfi_flash.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/cm-bf537u/config.mk b/board/cm-bf537u/config.mk index bc046f129f..1281da4bef 100644 --- a/board/cm-bf537u/config.mk +++ b/board/cm-bf537u/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf537-0.2 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/cm-bf537u/gpio_cfi_flash.c b/board/cm-bf537u/gpio_cfi_flash.c index 416c689500..ef5ea8b793 100644 --- a/board/cm-bf537u/gpio_cfi_flash.c +++ b/board/cm-bf537u/gpio_cfi_flash.c @@ -1,58 +1,2 @@ -/* - * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support - * - * Copyright (c) 2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <common.h> -#include <asm/blackfin.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include "gpio_cfi_flash.h" - -#define GPIO_PIN_1 GPIO_PH0 -#define GPIO_MASK_1 (1 << 21) -#define GPIO_MASK (GPIO_MASK_1) - -void *gpio_cfi_flash_swizzle(void *vaddr) -{ - unsigned long addr = (unsigned long)vaddr; - - gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1); - -#ifdef GPIO_MASK_2 - gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2); -#endif - - SSYNC(); - - return (void *)(addr & ~GPIO_MASK); -} - -#define __raw_writeq(value, addr) *(volatile u64 *)addr = value -#define __raw_readq(addr) *(volatile u64 *)addr - -#define MAKE_FLASH(size, sfx) \ -void flash_write##size(u##size value, void *addr) \ -{ \ - __raw_write##sfx(value, gpio_cfi_flash_swizzle(addr)); \ -} \ -u##size flash_read##size(void *addr) \ -{ \ - return __raw_read##sfx(gpio_cfi_flash_swizzle(addr)); \ -} -MAKE_FLASH(8, b) /* flash_write8() flash_read8() */ -MAKE_FLASH(16, w) /* flash_write16() flash_read16() */ -MAKE_FLASH(32, l) /* flash_write32() flash_read32() */ -MAKE_FLASH(64, q) /* flash_write64() flash_read64() */ - -void gpio_cfi_flash_init(void) -{ - gpio_request(GPIO_PIN_1, "gpio_cfi_flash"); -#ifdef GPIO_MASK_2 - gpio_request(GPIO_PIN_2, "gpio_cfi_flash"); -#endif - gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE); -} +#define GPIO_PIN_1 GPIO_PH0 +#include "../cm-bf537e/gpio_cfi_flash.c" diff --git a/board/cm-bf537u/gpio_cfi_flash.h b/board/cm-bf537u/gpio_cfi_flash.h deleted file mode 100644 index 5211e972ad..0000000000 --- a/board/cm-bf537u/gpio_cfi_flash.h +++ /dev/null @@ -1,10 +0,0 @@ -/* - * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support - * - * Copyright (c) 2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -void *gpio_cfi_flash_swizzle(void *vaddr); -void gpio_cfi_flash_init(void); diff --git a/board/cm-bf548/config.mk b/board/cm-bf548/config.mk index f071a39d75..bce60e5baa 100644 --- a/board/cm-bf548/config.mk +++ b/board/cm-bf548/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf548-0.0 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/cm-bf548/video.c b/board/cm-bf548/video.c index c501697404..4703098149 100644 --- a/board/cm-bf548/video.c +++ b/board/cm-bf548/video.c @@ -153,25 +153,26 @@ void Init_PPI(void) void Init_DMA(void *dst) { - #if defined(CONFIG_DEB_DMA_URGENT) - *pEBIU_DDRQUE |= DEB2_URGENT; + bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | DEB2_URGENT); #endif - *pDMA12_START_ADDR = dst; + bfin_write_DMA12_START_ADDR(dst); /* X count */ - *pDMA12_X_COUNT = (LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE; - *pDMA12_X_MODIFY = DMA_BUS_SIZE / 8; + bfin_write_DMA12_X_COUNT((LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE); + bfin_write_DMA12_X_MODIFY(DMA_BUS_SIZE / 8); /* Y count */ - *pDMA12_Y_COUNT = LCD_Y_RES; - *pDMA12_Y_MODIFY = DMA_BUS_SIZE / 8; + bfin_write_DMA12_Y_COUNT(LCD_Y_RES); + bfin_write_DMA12_Y_MODIFY(DMA_BUS_SIZE / 8); /* DMA Config */ - *pDMA12_CONFIG = WDSIZE_32 | /* 32 bit DMA */ + bfin_write_DMA12_CONFIG( + WDSIZE_32 | /* 32 bit DMA */ DMA2D | /* 2D DMA */ - FLOW_AUTO; /* autobuffer mode */ + FLOW_AUTO /* autobuffer mode */ + ); } void Init_Ports(void) @@ -195,12 +196,12 @@ void Init_Ports(void) void EnableDMA(void) { - *pDMA12_CONFIG |= DMAEN; + bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() | DMAEN); } void DisableDMA(void) { - *pDMA12_CONFIG &= ~DMAEN; + bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() & ~DMAEN); } /* enable and disable PPI functions */ diff --git a/board/cm-bf561/config.mk b/board/cm-bf561/config.mk index a90b193388..ff19190a26 100644 --- a/board/cm-bf561/config.mk +++ b/board/cm-bf561/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf561-0.3 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/davedenx/aria/aria.c b/board/davedenx/aria/aria.c index f17df60c20..31b079b1c3 100644 --- a/board/davedenx/aria/aria.c +++ b/board/davedenx/aria/aria.c @@ -119,11 +119,6 @@ int misc_init_r(void) tmp & 0x000000FF ); -#ifdef CONFIG_FSL_DIU_FB -# if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)) - mpc5121_diu_init(); -# endif -#endif return 0; } diff --git a/board/davinci/common/misc.c b/board/davinci/common/misc.c index 86a875eeaa..b60a46e96d 100644 --- a/board/davinci/common/misc.c +++ b/board/davinci/common/misc.c @@ -85,45 +85,22 @@ err: return 0; } -/* If there is a MAC address in the environment, and if it is not identical to - * the MAC address in the EEPROM, then a warning is printed and the MAC address - * from the environment is used. - * +/* * If there is no MAC address in the environment, then it will be initialized * (silently) from the value in the EEPROM. */ -void dv_configure_mac_address(uint8_t *rom_enetaddr) +void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr) { - int i; - u_int8_t env_enetaddr[6]; - char *tmp = getenv("ethaddr"); - char *end; - - /* Read Ethernet MAC address from the U-Boot environment. - * If it is not defined, env_enetaddr[] will be cleared. */ - for (i = 0; i < 6; i++) { - env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; - if (tmp) - tmp = (*end) ? end+1 : end; - } - - /* Check if EEPROM and U-Boot environment MAC addresses match. */ - if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6) != 0 && - memcmp(env_enetaddr, rom_enetaddr, 6) != 0) { - printf("Warning: MAC addresses don't match:\n"); - printf(" EEPROM MAC address: %pM\n", rom_enetaddr); - printf(" \"ethaddr\" value: %pM\n", env_enetaddr) ; - debug("### Using MAC address from environment\n"); - } - if (!tmp) { - char ethaddr[20]; + uint8_t env_enetaddr[6]; + eth_getenv_enetaddr_by_index(0, env_enetaddr); + if (!memcmp(env_enetaddr, "\0\0\0\0\0\0", 6)) { /* There is no MAC address in the environment, so we initialize * it from the value in the EEPROM. */ - sprintf(ethaddr, "%pM", rom_enetaddr) ; - debug("### Setting environment from EEPROM MAC address = \"%s\"\n", - ethaddr); - setenv("ethaddr", ethaddr); + debug("### Setting environment from EEPROM MAC address = " + "\"%pM\"\n", + env_enetaddr); + eth_setenv_enetaddr("ethaddr", rom_enetaddr); } } diff --git a/board/davinci/common/misc.h b/board/davinci/common/misc.h index 329c369763..a6ac3b9a56 100644 --- a/board/davinci/common/misc.h +++ b/board/davinci/common/misc.h @@ -46,7 +46,7 @@ struct pinmux_resource { } int dvevm_read_mac_address(uint8_t *buf); -void dv_configure_mac_address(uint8_t *rom_enetaddr); +void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr); int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins); int davinci_configure_pin_mux_items(const struct pinmux_resource *item, int n_items); diff --git a/board/davinci/da8xxevm/da830evm.c b/board/davinci/da8xxevm/da830evm.c index 6baa8603f1..8a9f9884d6 100644 --- a/board/davinci/da8xxevm/da830evm.c +++ b/board/davinci/da8xxevm/da830evm.c @@ -196,19 +196,17 @@ int board_eth_init(bd_t *bis) { u_int8_t mac_addr[6]; u_int8_t switch_start_cmd[2] = { 0x01, 0x23 }; + struct eth_device *dev; /* Read Ethernet MAC address from EEPROM */ if (dvevm_read_mac_address(mac_addr)) /* set address env if not already set */ - dv_configure_mac_address(mac_addr); + davinci_sync_env_enetaddr(mac_addr); /* read the address back from env */ if (!eth_getenv_enetaddr("ethaddr", mac_addr)) return -1; - /* provide the resulting addr to the driver */ - davinci_eth_set_mac_addr(mac_addr); - /* enable the Ethernet switch in the 3 port PHY */ if (i2c_write(PHY_SW_I2C_ADDR, 0, 0, switch_start_cmd, sizeof(switch_start_cmd))) { @@ -222,6 +220,12 @@ int board_eth_init(bd_t *bis) return -1; } + dev = eth_get_dev(); + + /* provide the resulting addr to the driver */ + memcpy(dev->enetaddr, mac_addr, 6); + dev->write_hwaddr(dev); + return 0; } #endif /* CONFIG_DRIVER_TI_EMAC */ diff --git a/board/davinci/dm365evm/dm365evm.c b/board/davinci/dm365evm/dm365evm.c index 290eb99749..85dbe2a9c3 100644 --- a/board/davinci/dm365evm/dm365evm.c +++ b/board/davinci/dm365evm/dm365evm.c @@ -68,7 +68,7 @@ int board_eth_init(bd_t *bis) /* Read Ethernet MAC address from EEPROM */ if (dvevm_read_mac_address(eeprom_enetaddr)) - dv_configure_mac_address(eeprom_enetaddr); + davinci_sync_env_enetaddr(eeprom_enetaddr); davinci_emac_initialize(); diff --git a/board/davinci/dvevm/dvevm.c b/board/davinci/dvevm/dvevm.c index 98937a9620..073c21a8cc 100644 --- a/board/davinci/dvevm/dvevm.c +++ b/board/davinci/dvevm/dvevm.c @@ -71,7 +71,7 @@ int misc_init_r(void) /* Read Ethernet MAC address from EEPROM if available. */ if (dvevm_read_mac_address(eeprom_enetaddr)) - dv_configure_mac_address(eeprom_enetaddr); + davinci_sync_env_enetaddr(eeprom_enetaddr); i2c_read(0x39, 0x00, 1, &video_mode, 1); diff --git a/board/davinci/sffsdr/sffsdr.c b/board/davinci/sffsdr/sffsdr.c index c24b9e188c..657cf2b0d9 100644 --- a/board/davinci/sffsdr/sffsdr.c +++ b/board/davinci/sffsdr/sffsdr.c @@ -141,7 +141,7 @@ int misc_init_r(void) /* Read Ethernet MAC address from EEPROM if available. */ if (sffsdr_read_mac_address(eeprom_enetaddr)) - dv_configure_mac_address(eeprom_enetaddr); + davinci_sync_env_enetaddr(eeprom_enetaddr); return(0); } diff --git a/board/davinci/sonata/sonata.c b/board/davinci/sonata/sonata.c index 817970aeaa..1dc42c4087 100644 --- a/board/davinci/sonata/sonata.c +++ b/board/davinci/sonata/sonata.c @@ -70,7 +70,7 @@ int misc_init_r(void) /* Read Ethernet MAC address from EEPROM if available. */ if (dvevm_read_mac_address(eeprom_enetaddr)) - dv_configure_mac_address(eeprom_enetaddr); + davinci_sync_env_enetaddr(eeprom_enetaddr); return(0); } diff --git a/board/eNET/eNET_start.S b/board/eNET/eNET_start.S index 1b07d622f7..137fe41b4b 100644 --- a/board/eNET/eNET_start.S +++ b/board/eNET/eNET_start.S @@ -27,19 +27,7 @@ .globl early_board_init early_board_init: /* No 32-bit board specific initialisation */ - jmp *%ebp /* return to caller */ - -.globl show_boot_progress_asm -show_boot_progress_asm: - - movb %al, %dl /* Create Working Copy */ - andb $0x80, %dl /* Mask in only Error bit */ - shrb $0x02, %dl /* Shift Error bit to Error LED */ - andb $0x0f, %al /* Mask out 'Error' bit */ - orb %dl, %al /* Mask in ERR LED */ - movw $LED_LATCH_ADDRESS, %dx - outb %al, %dx - jmp *%ebp /* return to caller */ + jmp early_board_init_ret .globl cpu_halt_asm cpu_halt_asm: diff --git a/board/eNET/eNET_start16.S b/board/eNET/eNET_start16.S index af2c132156..06cfd558d1 100644 --- a/board/eNET/eNET_start16.S +++ b/board/eNET/eNET_start16.S @@ -65,8 +65,7 @@ board_init16: movl $0x000000cb, %eax outl %eax, %dx - /* the return address is stored in bp */ - jmp *%bp + jmp board_init16_ret .section .bios, "ax" .code16 diff --git a/board/eNET/u-boot.lds b/board/eNET/u-boot.lds index 7b0ffaa6cc..b414079bc1 100644 --- a/board/eNET/u-boot.lds +++ b/board/eNET/u-boot.lds @@ -27,66 +27,62 @@ ENTRY(_start) SECTIONS { - . = 0x06000000; /* Location of bootcode in flash */ - _i386boot_text_start = .; - .text : { *(.text); } + . = TEXT_BASE; /* Location of bootcode in flash */ + __text_start = .; + .text : { *(.text*); } . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - _i386boot_text_size = SIZEOF(.text) + SIZEOF(.rodata); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } . = ALIGN(4); + __u_boot_cmd_end = .; - .data : { *(.data) } . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - .interp : { *(.interp) } . = ALIGN(4); + .data : { *(.data*) } - .dynsym : { *(.dynsym) } . = ALIGN(4); + .dynsym : { *(.dynsym*) } - .dynstr : { *(.dynstr) } . = ALIGN(4); + .hash : { *(.hash*) } - .hash : { *(.hash) } . = ALIGN(4); + .got : { *(.got*) } - .got : { *(.got) } . = ALIGN(4); + __data_end = .; - .got.plt : { *(.got.plt) } . = ALIGN(4); - - .dynamic (NOLOAD) : { *(.dynamic) } + __bss_start = ABSOLUTE(.); + .bss (NOLOAD) : { *(.bss) } . = ALIGN(4); + __bss_end = ABSOLUTE(.); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } . = ALIGN(4); - __u_boot_cmd_end = .; - _i386boot_cmd_start = LOADADDR(.u_boot_cmd); - - _i386boot_rel_dyn_start = .; + __rel_dyn_start = .; .rel.dyn : { *(.rel.dyn) } - _i386boot_rel_dyn_end = .; + __rel_dyn_end = .; - . = ALIGN(4); - _i386boot_bss_start = ABSOLUTE(.); - .bss (NOLOAD) : { *(.bss) } - _i386boot_bss_size = SIZEOF(.bss); + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } /* 16bit realmode trampoline code */ - .realmode 0x7c0 : AT ( LOADADDR(.rel.dyn) + SIZEOF(.rel.dyn) ) { *(.realmode) } + .realmode 0x7c0 : AT ( LOADADDR(.rel.dyn) + SIZEOF(.rel.dyn) ) { KEEP(*(.realmode)) } - _i386boot_realmode = LOADADDR(.realmode); - _i386boot_realmode_size = SIZEOF(.realmode); + __realmode_start = LOADADDR(.realmode); + __realmode_size = SIZEOF(.realmode); /* 16bit BIOS emulation code (just enough to boot Linux) */ - .bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { *(.bios) } + .bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { KEEP(*(.bios)) } - _i386boot_bios = LOADADDR(.bios); - _i386boot_bios_size = SIZEOF(.bios); + __bios_start = LOADADDR(.bios); + __bios_size = SIZEOF(.bios); /* The load addresses below assumes that the flash * will be mapped so that 0x387f0000 == 0xffff0000 @@ -98,12 +94,11 @@ SECTIONS * The fff0 offset of resetvec is important, however. */ . = 0xfffffe00; - .start32 : AT (0x0603fe00) { *(.start32); } + .start32 : AT (TEXT_BASE + 0x3fe00) { KEEP(*(.start32)); } . = 0xf800; - .start16 : AT (0x0603f800) { *(.start16); } + .start16 : AT (TEXT_BASE + 0x3f800) { KEEP(*(.start16)); } . = 0xfff0; - .resetvec : AT (0x0603fff0) { *(.resetvec); } - _i386boot_end = (LOADADDR(.resetvec) + SIZEOF(.resetvec) ); + .resetvec : AT (TEXT_BASE + 0x3fff0) { KEEP(*(.resetvec)); } } diff --git a/board/freescale/common/fsl_diu_fb.c b/board/freescale/common/fsl_diu_fb.c index 394b71f32f..35ed938bef 100644 --- a/board/freescale/common/fsl_diu_fb.c +++ b/board/freescale/common/fsl_diu_fb.c @@ -28,7 +28,7 @@ #include <malloc.h> #include <asm/io.h> -#include "fsl_diu_fb.h" +#include <fsl_diu_fb.h> struct fb_videomode { const char *name; /* optional */ @@ -472,3 +472,42 @@ static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align) buf->offset = 0; return 0; } + +#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) +#include <stdio_dev.h> +#include <video_fb.h> +/* + * The Graphic Device + */ +static GraphicDevice ctfb; + +void *video_hw_init(void) +{ + struct fb_info *info; + + if (platform_diu_init(&ctfb.winSizeX, &ctfb.winSizeY) < 0) + return NULL; + + /* fill in Graphic device struct */ + sprintf(ctfb.modeIdent, "%ix%ix%i %ikHz %iHz", + ctfb.winSizeX, ctfb.winSizeY, 32, 64, 60); + + ctfb.frameAdrs = (unsigned int)fsl_fb_open(&info); + ctfb.plnSizeX = ctfb.winSizeX; + ctfb.plnSizeY = ctfb.winSizeY; + + ctfb.gdfBytesPP = 4; + ctfb.gdfIndex = GDF_32BIT_X888RGB; + + ctfb.isaBase = 0; + ctfb.pciBase = 0; + ctfb.memSize = info->screen_size; + + /* Cursor Start Address */ + ctfb.dprBase = 0; + ctfb.vprBase = 0; + ctfb.cprBase = 0; + + return &ctfb; +} +#endif /* defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) */ diff --git a/board/freescale/common/fsl_diu_fb.h b/board/freescale/common/fsl_diu_fb.h deleted file mode 100644 index 3a5fc9ff82..0000000000 --- a/board/freescale/common/fsl_diu_fb.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright 2007 Freescale Semiconductor, Inc. - * York Sun <yorksun@freescale.com> - * - * FSL DIU Framebuffer driver - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -struct fb_var_screeninfo { - unsigned int xres; /* visible resolution */ - unsigned int yres; - - unsigned int bits_per_pixel; /* guess what */ - - /* Timing: All values in pixclocks, except pixclock (of course) */ - unsigned int pixclock; /* pixel clock in ps (pico seconds) */ - unsigned int left_margin; /* time from sync to picture */ - unsigned int right_margin; /* time from picture to sync */ - unsigned int upper_margin; /* time from sync to picture */ - unsigned int lower_margin; - unsigned int hsync_len; /* length of horizontal sync */ - unsigned int vsync_len; /* length of vertical sync */ - unsigned int sync; /* see FB_SYNC_* */ - unsigned int vmode; /* see FB_VMODE_* */ - unsigned int rotate; /* angle we rotate counter clockwise */ -}; - -struct fb_info { - struct fb_var_screeninfo var; /* Current var */ - unsigned long smem_start; /* Start of frame buffer mem */ - /* (physical address) */ - unsigned int smem_len; /* Length of frame buffer mem */ - unsigned int type; /* see FB_TYPE_* */ - unsigned int line_length; /* length of a line in bytes */ - - char *screen_base; - unsigned long screen_size; -}; - - -extern char *fsl_fb_open(struct fb_info **info); -int fsl_diu_init(int xres, unsigned int pixel_format, int gamma_fix); diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index 3929ad0aac..11dfd84fe6 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -28,13 +28,21 @@ #include <i2c.h> #include <linux/ctype.h> +#ifdef CONFIG_SYS_I2C_EEPROM_CCID #include "../common/eeprom.h" +#define MAX_NUM_PORTS 8 +#endif -#if !defined(CONFIG_SYS_I2C_EEPROM_CCID) && !defined(CONFIG_SYS_I2C_EEPROM_NXID) -#error "Please define either CONFIG_SYS_I2C_EEPROM_CCID or CONFIG_SYS_I2C_EEPROM_NXID" +#ifdef CONFIG_SYS_I2C_EEPROM_NXID +#define MAX_NUM_PORTS 8 +#define NXID_VERSION 0 #endif -#define MAX_NUM_PORTS 8 /* This value must be 8 as defined in doc */ +#ifdef CONFIG_SYS_I2C_EEPROM_NXID_1 +#define CONFIG_SYS_I2C_EEPROM_NXID +#define MAX_NUM_PORTS 23 +#define NXID_VERSION 1 +#endif /** * static eeprom: EEPROM layout for CCID or NXID formats @@ -68,8 +76,8 @@ static struct __attribute__ ((__packed__)) eeprom { u8 res_1[21]; /* 0x2b - 0x3f Reserved */ u8 mac_count; /* 0x40 Number of MAC addresses */ u8 mac_flag; /* 0x41 MAC table flags */ - u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - 0x71 MAC addresses */ - u32 crc; /* 0x72 CRC32 checksum */ + u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - x MAC addresses */ + u32 crc; /* x+1 CRC32 checksum */ #endif } e; @@ -204,7 +212,7 @@ static void update_crc(void) */ static int prog_eeprom(void) { - int ret = 0; /* shut up gcc */ + int ret = 0; int i; void *p; #ifdef CONFIG_SYS_EEPROM_BUS_NUM @@ -225,6 +233,11 @@ static int prog_eeprom(void) i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); #endif + /* + * The AT24C02 datasheet says that data can only be written in page + * mode, which means 8 bytes at a time, and it takes up to 5ms to + * complete a given write. + */ for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) { ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, p, min((sizeof(e) - i), 8)); @@ -233,12 +246,23 @@ static int prog_eeprom(void) udelay(5000); /* 5ms write cycle timing */ } + if (!ret) { + /* Verify the write by reading back the EEPROM and comparing */ + struct eeprom e2; + + ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (void *)&e2, sizeof(e2)); + if (!ret && memcmp(&e, &e2, sizeof(e))) + ret = -1; + } + #ifdef CONFIG_SYS_EEPROM_BUS_NUM i2c_set_bus_num(bus); #endif if (ret) { printf("Programming failed.\n"); + has_been_read = 0; return -1; } @@ -300,7 +324,7 @@ static void set_mac_address(unsigned int index, const char *string) char *p = (char *) string; unsigned int i; - if (!string) { + if ((index >= MAX_NUM_PORTS) || !string) { printf("Usage: mac <n> XX:XX:XX:XX:XX:XX\n"); return; } @@ -333,7 +357,7 @@ int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (cmd == 'i') { #ifdef CONFIG_SYS_I2C_EEPROM_NXID memcpy(e.id, "NXID", sizeof(e.id)); - e.version = 0; + e.version = NXID_VERSION; #else memcpy(e.id, "CCID", sizeof(e.id)); #endif @@ -382,8 +406,8 @@ int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) e.mac_count = simple_strtoul(argv[2], NULL, 16); update_crc(); break; - case '0' ... '7': /* "mac 0" through "mac 7" */ - set_mac_address(cmd - '0', argv[2]); + case '0' ... '9': /* "mac 0" through "mac 22" */ + set_mac_address(simple_strtoul(argv[1], NULL, 10), argv[2]); break; case 'h': /* help */ default: diff --git a/board/freescale/corenet_ds/pci.c b/board/freescale/corenet_ds/pci.c index 2994e366c2..e1bca1984c 100644 --- a/board/freescale/corenet_ds/pci.c +++ b/board/freescale/corenet_ds/pci.c @@ -40,10 +40,14 @@ static struct pci_controller pcie2_hose; static struct pci_controller pcie3_hose; #endif +#ifdef CONFIG_PCIE4 +static struct pci_controller pcie4_hose; +#endif + void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - struct fsl_pci_info pci_info[3]; + struct fsl_pci_info pci_info[4]; u32 devdisr; int first_free_busno = 0; int num = 0; @@ -119,6 +123,28 @@ void pci_init_board(void) #else setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE3); /* disable */ #endif + +#ifdef CONFIG_PCIE4 + pcie_configured = is_serdes_configured(PCIE4); + + if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE4)) { + set_next_law(CONFIG_SYS_PCIE4_MEM_PHYS, LAW_SIZE_512M, + LAW_TRGT_IF_PCIE_4); + set_next_law(CONFIG_SYS_PCIE4_IO_PHYS, LAW_SIZE_64K, + LAW_TRGT_IF_PCIE_4); + SET_STD_PCIE_INFO(pci_info[num], 4); + pcie_ep = fsl_setup_hose(&pcie4_hose, pci_info[num].regs); + printf(" PCIE4 connected to as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie4_hose, first_free_busno); + } else { + printf (" PCIE4: disabled\n"); + } +#else + setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE4); /* disable */ +#endif } void pci_of_setup(void *blob, bd_t *bd) diff --git a/board/freescale/mpc8569mds/ddr.c b/board/freescale/mpc8569mds/ddr.c index e938788f07..e3f5b4aa21 100644 --- a/board/freescale/mpc8569mds/ddr.c +++ b/board/freescale/mpc8569mds/ddr.c @@ -77,8 +77,18 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->write_data_delay = 2; /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed + * Enable half drive strength */ - popts->half_strength_driver_enable = 0; + popts->half_strength_driver_enable = 1; + + /* Write leveling override */ + popts->wrlvl_en = 1; + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xa; + popts->wrlvl_start = 0x4; + + /* Rtt and Rtt_W override */ + popts->rtt_override = 1; + popts->rtt_override_value = DDR3_RTT_60_OHM; + popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */ } diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index 01b7dcb70c..795e5654e8 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -27,6 +27,7 @@ #include <pci.h> #include <asm/processor.h> #include <asm/mmu.h> +#include <asm/cache.h> #include <asm/immap_85xx.h> #include <asm/fsl_pci.h> #include <asm/fsl_ddr_sdram.h> @@ -211,6 +212,31 @@ int board_early_init_f (void) return 0; } +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_NAND_BASE; + const u8 flash_esel = 0; + + /* + * Remap Boot flash to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE, /* tlb, epn, rpn */ + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ + 0, flash_esel, /* ts, esel */ + BOOKE_PAGESZ_64M, 1); /* tsize, iprot */ + + return 0; +} + int checkboard (void) { printf ("Board: 8569 MDS\n"); diff --git a/board/freescale/mpc8569mds/tlb.c b/board/freescale/mpc8569mds/tlb.c index 73dcc3e66c..f852fc35c3 100644 --- a/board/freescale/mpc8569mds/tlb.c +++ b/board/freescale/mpc8569mds/tlb.c @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2009-2010 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -46,15 +46,20 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 Initializations */ /* - * TLBe 0: 64M Non-cacheable, guarded + * TLBe 0: 64M write-through, guarded * Out of reset this entry is only 4K. - * 0xfc000000 256K NAND FLASH (CS3) - * 0xfe000000 32M NOR FLASH (CS0) + * 0xfc000000 32MB NAND FLASH (CS3) + * 0xfe000000 32MB NOR FLASH (CS0) */ +#ifdef CONFIG_NAND_SPL SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#else + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, 0, 0, BOOKE_PAGESZ_64M, 1), - +#endif /* * TLBe 1: 256KB Non-cacheable, guarded * 0xf8000000 32K BCSR diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c index 960c8eda7d..81e53e734f 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c @@ -26,17 +26,7 @@ #include <common.h> #include <command.h> #include <asm/io.h> - -#ifdef CONFIG_FSL_DIU_FB - -#include "../common/fsl_diu_fb.h" - -#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) -#include <stdio_dev.h> -#include <video_fb.h> -#endif - -static int xres, yres; +#include <fsl_diu_fb.h> void diu_set_pixel_clock(unsigned int pixclock) { @@ -59,7 +49,7 @@ void diu_set_pixel_clock(unsigned int pixclock) debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *guts_clkdvdr); } -int mpc8610hpcd_diu_init(void) +int platform_diu_init(unsigned int *xres, unsigned int *yres) { char *monitor_port; int gamma_fix; @@ -73,8 +63,8 @@ int mpc8610hpcd_diu_init(void) monitor_port = getenv("monitor"); if (!strncmp(monitor_port, "0", 1)) { /* 0 - DVI */ - xres = 1280; - yres = 1024; + *xres = 1280; + *yres = 1024; if (pixis_arch == 0x01) pixel_format = 0x88882317; else @@ -83,68 +73,26 @@ int mpc8610hpcd_diu_init(void) out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x08); } else if (!strncmp(monitor_port, "1", 1)) { /* 1 - Single link LVDS */ - xres = 1024; - yres = 768; + *xres = 1024; + *yres = 768; pixel_format = 0x88883316; gamma_fix = 0; out_8(pixis_base + PIXIS_BRDCFG0, (tmp_val & 0xf7) | 0x10); } else if (!strncmp(monitor_port, "2", 1)) { /* 2 - Double link LVDS */ - xres = 1280; - yres = 1024; + *xres = 1280; + *yres = 1024; pixel_format = 0x88883316; gamma_fix = 1; out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xe7); } else { /* DVI */ - xres = 1280; - yres = 1024; + *xres = 1280; + *yres = 1024; pixel_format = 0x88882317; gamma_fix = 0; out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x08); } - return fsl_diu_init(xres, pixel_format, gamma_fix); -} - -#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) - -/* - * The Graphic Device - */ -static GraphicDevice ctfb; - -void *video_hw_init(void) -{ - struct fb_info *info; - - if (mpc8610hpcd_diu_init() < 0) - return NULL; - - /* fill in Graphic device struct */ - sprintf(ctfb.modeIdent, "%ix%ix%i %ikHz %iHz", xres, yres, 32, 64, 60); - - ctfb.frameAdrs = (unsigned int)fsl_fb_open(&info); - ctfb.winSizeX = xres; - ctfb.winSizeY = yres; - ctfb.plnSizeX = ctfb.winSizeX; - ctfb.plnSizeY = ctfb.winSizeY; - - ctfb.gdfBytesPP = 4; - ctfb.gdfIndex = GDF_32BIT_X888RGB; - - ctfb.isaBase = 0; - ctfb.pciBase = 0; - ctfb.memSize = info->screen_size; - - /* Cursor Start Address */ - ctfb.dprBase = 0; - ctfb.vprBase = 0; - ctfb.cprBase = 0; - - return &ctfb; + return fsl_diu_init(*xres, pixel_format, gamma_fix); } - -#endif /* defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) */ - -#endif /* CONFIG_FSL_DIU_FB */ diff --git a/board/freescale/p1022ds/Makefile b/board/freescale/p1022ds/Makefile index 8ede2d6055..678eb2ae06 100644 --- a/board/freescale/p1022ds/Makefile +++ b/board/freescale/p1022ds/Makefile @@ -16,6 +16,8 @@ COBJS-y += ddr.o COBJS-y += law.o COBJS-y += tlb.o +COBJS-$(CONFIG_FSL_DIU_FB) += diu.o + SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/freescale/p1022ds/diu.c b/board/freescale/p1022ds/diu.c new file mode 100644 index 0000000000..12b40a01ed --- /dev/null +++ b/board/freescale/p1022ds/diu.c @@ -0,0 +1,304 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * Authors: Timur Tabi <timur@freescale.com> + * + * FSL DIU Framebuffer driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include <common.h> +#include <command.h> +#include <asm/io.h> +#include <stdio_dev.h> +#include <video_fb.h> +#include "../common/ngpixis.h" +#include <fsl_diu_fb.h> + +/* The CTL register is called 'csr' in the ngpixis_t structure */ +#define PX_CTL_ALTACC 0x80 + +#define PX_BRDCFG0_ELBC_SPI_MASK 0xc0 +#define PX_BRDCFG0_ELBC_SPI_ELBC 0x00 +#define PX_BRDCFG0_ELBC_SPI_NULL 0xc0 +#define PX_BRDCFG0_ELBC_DIU 0x02 + +#define PX_BRDCFG1_DVIEN 0x80 +#define PX_BRDCFG1_DFPEN 0x40 +#define PX_BRDCFG1_BACKLIGHT 0x20 + +#define PMUXCR_ELBCDIU_MASK 0xc0000000 +#define PMUXCR_ELBCDIU_NOR16 0x80000000 + +/* + * DIU Area Descriptor + * + * Note that we need to byte-swap the value before it's written to the AD + * register. So even though the registers don't look like they're in the same + * bit positions as they are on the MPC8610, the same value is written to the + * AD register on the MPC8610 and on the P1022. + */ +#define AD_BYTE_F 0x10000000 +#define AD_ALPHA_C_SHIFT 25 +#define AD_BLUE_C_SHIFT 23 +#define AD_GREEN_C_SHIFT 21 +#define AD_RED_C_SHIFT 19 +#define AD_PIXEL_S_SHIFT 16 +#define AD_COMP_3_SHIFT 12 +#define AD_COMP_2_SHIFT 8 +#define AD_COMP_1_SHIFT 4 +#define AD_COMP_0_SHIFT 0 + +/* + * Variables used by the DIU/LBC switching code. It's safe to makes these + * global, because the DIU requires DDR, so we'll only run this code after + * relocation. + */ +static u8 px_brdcfg0; +static u32 pmuxcr; +static void *lbc_lcs0_ba; +static void *lbc_lcs1_ba; + +void diu_set_pixel_clock(unsigned int pixclock) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + unsigned long speed_ccb, temp; + u32 pixval; + + speed_ccb = get_bus_freq(0); + temp = 1000000000 / pixclock; + temp *= 1000; + pixval = speed_ccb / temp; + debug("DIU pixval = %lu\n", pixval); + + /* Modify PXCLK in GUTS CLKDVDR */ + temp = in_be32(&gur->clkdvdr) & 0x2000FFFF; + out_be32(&gur->clkdvdr, temp); /* turn off clock */ + out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16)); +} + +int platform_diu_init(unsigned int *xres, unsigned int *yres) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + char *monitor_port; + u32 pixel_format; + u8 temp; + + /* Save the LBC LCS0 and LCS1 addresses for the DIU mux functions */ + lbc_lcs0_ba = (void *)(get_lbc_br(0) & get_lbc_or(0) & 0xFFFF8000); + lbc_lcs1_ba = (void *)(get_lbc_br(1) & get_lbc_or(1) & 0xFFFF8000); + + pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) | + (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) | + (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) | + (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) | + (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT)); + + temp = in_8(&pixis->brdcfg1); + + monitor_port = getenv("monitor"); + if (!strncmp(monitor_port, "1", 1)) { /* 1 - Single link LVDS */ + *xres = 1024; + *yres = 768; + /* Enable the DFP port, disable the DVI and the backlight */ + temp &= ~(PX_BRDCFG1_DVIEN | PX_BRDCFG1_BACKLIGHT); + temp |= PX_BRDCFG1_DFPEN; + } else { /* DVI */ + *xres = 1280; + *yres = 1024; + /* Enable the DVI port, disable the DFP and the backlight */ + temp &= ~(PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT); + temp |= PX_BRDCFG1_DVIEN; + } + + out_8(&pixis->brdcfg1, temp); + + /* + * Enable PIXIS indirect access mode. This is a hack that allows us to + * access PIXIS registers even when the LBC pins have been muxed to the + * DIU. + */ + setbits_8(&pixis->csr, PX_CTL_ALTACC); + + /* + * Route the LAD pins to the DIU. This will disable access to the eLBC, + * which means we won't be able to read/write any NOR flash addresses! + */ + out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0)); + px_brdcfg0 = in_8(lbc_lcs1_ba); + out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU); + + /* Setting PMUXCR to switch to DVI from ELBC */ + clrsetbits_be32(&gur->pmuxcr, + PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_NOR16); + pmuxcr = in_be32(&gur->pmuxcr); + + return fsl_diu_init(*xres, pixel_format, 0); +} + +#ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS + +/* + * set_mux_to_lbc - disable the DIU so that we can read/write to elbc + * + * On the Freescale P1022, the DIU video signal and the LBC address/data lines + * share the same pins, which means that when the DIU is active (e.g. the + * console is on the DVI display), NOR flash cannot be accessed. So we use the + * weak accessor feature of the CFI flash code to temporarily switch the pin + * mux from DIU to LBC whenever we want to read or write flash. This has a + * significant performance penalty, but it's the only way to make it work. + * + * There are two muxes: one on the chip, and one on the board. The chip mux + * controls whether the pins are used for the DIU or the LBC, and it is + * set via PMUXCR. The board mux controls whether those signals go to + * the video connector or the NOR flash chips, and it is set via the ngPIXIS. + */ +static int set_mux_to_lbc(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Switch the muxes only if they're currently set to DIU mode */ + if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) == + PMUXCR_ELBCDIU_NOR16) { + /* + * In DIU mode, the PIXIS can only be accessed indirectly + * since we can't read/write the LBC directly. + */ + + /* Set the board mux to LBC. This will disable the display. */ + out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0)); + px_brdcfg0 = in_8(lbc_lcs1_ba); + out_8(lbc_lcs1_ba, (px_brdcfg0 & ~(PX_BRDCFG0_ELBC_SPI_MASK + | PX_BRDCFG0_ELBC_DIU)) | PX_BRDCFG0_ELBC_SPI_ELBC); + + /* Disable indirect PIXIS mode */ + out_8(lbc_lcs0_ba, offsetof(ngpixis_t, csr)); + clrbits_8(lbc_lcs1_ba, PX_CTL_ALTACC); + + /* Set the chip mux to LBC mode, so that writes go to flash. */ + out_be32(&gur->pmuxcr, (pmuxcr & ~PMUXCR_ELBCDIU_MASK) | + PMUXCR_ELBCDIU_NOR16); + in_be32(&gur->pmuxcr); + + return 1; + } + + return 0; +} + +/* + * set_mux_to_diu - re-enable the DIU muxing + * + * This function restores the chip and board muxing to point to the DIU. + */ +static void set_mux_to_diu(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Enable indirect PIXIS mode */ + setbits_8(&pixis->csr, PX_CTL_ALTACC); + + /* Set the board mux to DIU. This will enable the display. */ + out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0)); + out_8(lbc_lcs1_ba, px_brdcfg0); + in_8(lbc_lcs1_ba); + + /* Set the chip mux to DIU mode. */ + out_be32(&gur->pmuxcr, pmuxcr); + in_be32(&gur->pmuxcr); +} + +void flash_write8(u8 value, void *addr) +{ + int sw = set_mux_to_lbc(); + + __raw_writeb(value, addr); + if (sw) + set_mux_to_diu(); +} + +void flash_write16(u16 value, void *addr) +{ + int sw = set_mux_to_lbc(); + + __raw_writew(value, addr); + if (sw) + set_mux_to_diu(); +} + +void flash_write32(u32 value, void *addr) +{ + int sw = set_mux_to_lbc(); + + __raw_writel(value, addr); + if (sw) + set_mux_to_diu(); +} + +void flash_write64(u64 value, void *addr) +{ + int sw = set_mux_to_lbc(); + + /* There is no __raw_writeq(), so do the write manually */ + *(volatile u64 *)addr = value; + if (sw) + set_mux_to_diu(); +} + +u8 flash_read8(void *addr) +{ + u8 ret; + + int sw = set_mux_to_lbc(); + + ret = __raw_readb(addr); + if (sw) + set_mux_to_diu(); + + return ret; +} + +u16 flash_read16(void *addr) +{ + u16 ret; + + int sw = set_mux_to_lbc(); + + ret = __raw_readw(addr); + if (sw) + set_mux_to_diu(); + + return ret; +} + +u32 flash_read32(void *addr) +{ + u32 ret; + + int sw = set_mux_to_lbc(); + + ret = __raw_readl(addr); + if (sw) + set_mux_to_diu(); + + return ret; +} + +u64 flash_read64(void *addr) +{ + u64 ret; + + int sw = set_mux_to_lbc(); + + /* There is no __raw_readq(), so do the read manually */ + ret = *(volatile u64 *)addr; + if (sw) + set_mux_to_diu(); + + return ret; +} + +#endif diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index 5cdee9ff70..ee93e8b815 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -27,6 +27,7 @@ #include <asm/mp.h> #include <netdev.h> #include <i2c.h> +#include <hwconfig.h> #include "../common/ngpixis.h" @@ -90,34 +91,58 @@ phys_size_t initdram(int board_type) #define CONFIG_TFP410_I2C_ADDR 0x38 +/* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */ +#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK 0x0c +#define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK 0x03 + +/* Route the I2C1 pins to the SSI port instead. */ +#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI 0x08 + +/* Choose the 12.288Mhz codec reference clock */ +#define CONFIG_PIXIS_BRDCFG1_AUDCLK_12 0x02 + +/* Choose the 11.2896Mhz codec reference clock */ +#define CONFIG_PIXIS_BRDCFG1_AUDCLK_11 0x01 + int misc_init_r(void) { u8 temp; + const char *audclk; + size_t arglen; - /* Enable the TFP410 Encoder */ + /* For DVI, enable the TFP410 Encoder. */ temp = 0xBF; if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0) return -1; - - /* Verify if enabled */ - temp = 0; if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0) return -1; - debug("DVI Encoder Read: 0x%02x\n", temp); temp = 0x10; if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0) return -1; - - /* Verify if enabled */ - temp = 0; if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0) return -1; - debug("DVI Encoder Read: 0x%02x\n",temp); + /* + * Enable the reference clock for the WM8776 codec, and route the MUX + * pins for SSI. The default is the 12.288 MHz clock + */ + + temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK | + CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK); + temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI; + + audclk = hwconfig_arg("audclk", &arglen); + /* Check the first two chars only */ + if (audclk && (strncmp(audclk, "11", 2) == 0)) + temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11; + else + temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12; + out_8(&pixis->brdcfg1, temp); + return 0; } @@ -310,6 +335,27 @@ int board_eth_init(bd_t *bis) } #ifdef CONFIG_OF_BOARD_SETUP +/** + * ft_codec_setup - fix up the clock-frequency property of the codec node + * + * Update the clock-frequency property based on the value of the 'audclk' + * hwconfig option. If audclk is not specified, then default to 12.288MHz. + */ +static void ft_codec_setup(void *blob, const char *compatible) +{ + const char *audclk; + size_t arglen; + u32 freq; + + audclk = hwconfig_arg("audclk", &arglen); + if (audclk && (strncmp(audclk, "11", 2) == 0)) + freq = 11289600; + else + freq = 12288000; + + do_fixup_by_compat_u32(blob, compatible, "clock-frequency", freq, 1); +} + void ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; @@ -327,6 +373,9 @@ void ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_FSL_SGMII_RISER fsl_sgmii_riser_fdt_fixup(blob); #endif + + /* Update the WM8776 node's clock frequency property */ + ft_codec_setup(blob, "wlf,wm8776"); } #endif diff --git a/board/ibf-dsp561/config.mk b/board/ibf-dsp561/config.mk index 77c888b3bd..1fec4d020d 100644 --- a/board/ibf-dsp561/config.mk +++ b/board/ibf-dsp561/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf561-0.5 + # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/ip04/config.mk b/board/ip04/config.mk index 5766829115..683101b827 100644 --- a/board/ip04/config.mk +++ b/board/ip04/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf532-0.5 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/lwmon5/kbd.c b/board/lwmon5/kbd.c index 0e26b890b2..5231c7a5c6 100644 --- a/board/lwmon5/kbd.c +++ b/board/lwmon5/kbd.c @@ -45,6 +45,10 @@ static int compare_magic (uchar *kbd_data, uchar *str); /*--------------------- Local macros and constants --------------------*/ #define _NOT_USED_ 0xFFFFFFFF +/*------------------------- dspic io expander -----------------------*/ +#define DSPIC_PON_STATUS_REG 0x80A +#define DSPIC_PON_INV_STATUS_REG 0x80C +#define DSPIC_PON_KEY_REG 0x810 /*------------------------- Keyboard controller -----------------------*/ /* command codes */ #define KEYBD_CMD_READ_KEYS 0x01 @@ -75,6 +79,7 @@ static int compare_magic (uchar *kbd_data, uchar *str); /* maximum number of "magic" key codes that can be assigned */ static uchar kbd_addr = CONFIG_SYS_I2C_KEYBD_ADDR; +static uchar dspic_addr = CONFIG_SYS_I2C_DSPIC_IO_ADDR; static uchar *key_match (uchar *); @@ -167,6 +172,23 @@ static void kbd_init (void) } } + +/* Read a register from the dsPIC. */ +int _dspic_read(ushort reg, ushort *data) +{ + uchar buf[sizeof(*data)]; + int rval; + + if (i2c_read(dspic_addr, reg, 2, buf, 2)) + return -1; + + rval = i2c_read(dspic_addr, reg, sizeof(reg), buf, sizeof(*data)); + *data = (buf[0] << 8) | buf[1]; + + return rval; +} + + /*********************************************************************** F* Function: int misc_init_r (void) P*A*Z* * @@ -197,6 +219,7 @@ int misc_init_r_kbd (void) uchar kbd_init_status = gd->kbd_status >> 8; uchar kbd_status = gd->kbd_status; uchar val; + ushort data, inv_data; char *str; int i; @@ -231,9 +254,31 @@ int misc_init_r_kbd (void) i2c_write (kbd_addr, 0, 0, &val, 1); i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); + /* read out start key from bse01 received via can */ + _dspic_read(DSPIC_PON_STATUS_REG, &data); + /* check highbyte from status register */ + if (data > 0xFF) { + _dspic_read(DSPIC_PON_INV_STATUS_REG, &inv_data); + + /* check inverse data */ + if ((data+inv_data) == 0xFFFF) { + /* don't overwrite local key */ + if (kbd_data[1] == 0) { + /* read key value */ + _dspic_read(DSPIC_PON_KEY_REG, &data); + str = (char *)&data; + /* swap bytes */ + kbd_data[1] = str[1]; + kbd_data[2] = str[0]; + printf("CAN received startkey: 0x%X\n", data); + } + } + } + for (i = 0; i < KEYBD_DATALEN; ++i) { sprintf (keybd_env + i + i, "%02X", kbd_data[i]); } + setenv ("keybd", keybd_env); str = strdup ((char *)key_match (kbd_data)); /* decode keys */ diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index 9622b70d27..dd275bf777 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 + * (C) Copyright 2007-2010 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * This program is free software; you can redistribute it and/or @@ -24,10 +24,13 @@ #include <asm/processor.h> #include <asm/ppc4xx-gpio.h> #include <asm/io.h> +#include <post.h> +#include <flash.h> +#include <mtd/cfi_flash.h> DECLARE_GLOBAL_DATA_PTR; -extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ +static phys_addr_t lwmon5_cfi_flash_bank_addr[2] = CONFIG_SYS_FLASH_BANKS_LIST; ulong flash_get_size(ulong base, int banknum); int misc_init_r_kbd(void); @@ -97,16 +100,18 @@ int board_early_init_f(void) gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1); #if CONFIG_POST & CONFIG_SYS_POST_BSPEC1 - gpio_write_bit(CONFIG_SYS_GPIO_HIGHSIDE, 1); + /* enable the LSB transmitter */ + gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1); + /* enable the CAN transmitter */ + gpio_write_bit(CONFIG_SYS_GPIO_CAN_ENABLE, 1); reg = 0; /* reuse as counter */ out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR, in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) & ~CONFIG_SYS_DSPIC_TEST_MASK); - while (!gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) { + while (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) { udelay(1000); } - gpio_write_bit(CONFIG_SYS_GPIO_HIGHSIDE, 0); if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) { /* set "boot error" flag */ out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR, @@ -135,9 +140,61 @@ int board_early_init_f(void) return 0; } -/*---------------------------------------------------------------------------+ - | misc_init_r. - +---------------------------------------------------------------------------*/ +/* + * Override weak default with board specific version + */ +phys_addr_t cfi_flash_bank_addr(int bank) +{ + return lwmon5_cfi_flash_bank_addr[bank]; +} + +/* + * Override the weak default mapping function with a board specific one + */ +u32 flash_get_bank_size(int cs, int idx) +{ + return flash_info[idx].size; +} + +int board_early_init_r(void) +{ + u32 val0, val1; + + /* + * lwmon5 is manufactured in 2 different board versions: + * The lwmon5a board has 64MiB NOR flash instead of the + * 128MiB of the original lwmon5. Unfortunately the CFI driver + * will report 2 banks of 64MiB even for the smaller flash + * chip, since the bank is mirrored. To fix this, we bring + * one bank into CFI query mode and read its response. This + * enables us to detect the real number of flash devices/ + * banks which will be used later on by the common CFI driver. + */ + + /* Put bank 0 into CFI command mode and read */ + out_be32((void *)CONFIG_SYS_FLASH0, 0x00980098); + val0 = in_be32((void *)CONFIG_SYS_FLASH0 + FLASH_OFFSET_CFI_RESP); + val1 = in_be32((void *)CONFIG_SYS_FLASH1 + FLASH_OFFSET_CFI_RESP); + + /* Reset flash again out of query mode */ + out_be32((void *)CONFIG_SYS_FLASH0, 0x00f000f0); + + /* When not identical, we have 2 different flash devices/banks */ + if (val0 != val1) + return 0; + + /* + * Now we're sure that we're running on a LWMON5a board with + * only 64MiB NOR flash in one bank: + * + * Set flash base address and bank count for CFI driver probing. + */ + cfi_flash_num_flash_banks = 1; + lwmon5_cfi_flash_bank_addr[0] = CONFIG_SYS_FLASH0; + + return 0; +} + int misc_init_r(void) { u32 pbcr; @@ -145,7 +202,7 @@ int misc_init_r(void) u32 reg; unsigned long usb2d0cr = 0; unsigned long usb2phy0cr, usb2h0cr = 0; - unsigned long sdr0_pfc1; + unsigned long sdr0_pfc1, sdr0_srst; /* * FLASH stuff... @@ -158,32 +215,7 @@ int misc_init_r(void) gd->bd->bi_flashoffset = 0; mfebc(PB0CR, pbcr); - switch (gd->bd->bi_flashsize) { - case 1 << 20: - size_val = 0; - break; - case 2 << 20: - size_val = 1; - break; - case 4 << 20: - size_val = 2; - break; - case 8 << 20: - size_val = 3; - break; - case 16 << 20: - size_val = 4; - break; - case 32 << 20: - size_val = 5; - break; - case 64 << 20: - size_val = 6; - break; - case 128 << 20: - size_val = 7; - break; - } + size_val = ffs(gd->bd->bi_flashsize) - 21; pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); mtebc(PB0CR, pbcr); @@ -193,53 +225,92 @@ int misc_init_r(void) flash_get_size(gd->bd->bi_flashstart, 0); /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - -CONFIG_SYS_MONITOR_LEN, - 0xffffffff, - &flash_info[1]); + flash_protect(FLAG_PROTECT_SET, -CONFIG_SYS_MONITOR_LEN, 0xffffffff, + &flash_info[cfi_flash_num_flash_banks - 1]); /* Env protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1, - &flash_info[1]); + flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + 2 * CONFIG_ENV_SECT_SIZE - 1, + &flash_info[cfi_flash_num_flash_banks - 1]); /* * USB suff... */ + + /* Reset USB */ + /* Reset of USB2PHY0 must be active at least 10 us */ + mtsdr(SDR0_SRST0, SDR0_SRST0_USB2H | SDR0_SRST0_USB2D); + udelay(2000); + + mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY | SDR0_SRST1_USB2HUTMI | + SDR0_SRST1_USB2HPHY | SDR0_SRST1_OPBA2 | + SDR0_SRST1_PLB42OPB1 | SDR0_SRST1_OPB2PLB40); + udelay(2000); + + /* Errata CHIP_6 */ + + /* 1. Set internal PHY configuration */ /* SDR Setting */ mfsdr(SDR0_PFC1, sdr0_pfc1); mfsdr(SDR0_USB0, usb2d0cr); mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); mfsdr(SDR0_USB2H0CR, usb2h0cr); - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/ - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/ - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ - - /* An 8-bit/60MHz interface is the only possible alternative - when connecting the Device to the PHY */ - usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; - usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ + + /* + * An 8-bit/60MHz interface is the only possible alternative + * when connecting the Device to the PHY + */ + usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK; + usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/ mtsdr(SDR0_PFC1, sdr0_pfc1); mtsdr(SDR0_USB0, usb2d0cr); mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); mtsdr(SDR0_USB2H0CR, usb2h0cr); + /* 2. De-assert internal PHY reset */ + mfsdr(SDR0_SRST1, sdr0_srst); + sdr0_srst = sdr0_srst & ~SDR0_SRST1_USB20PHY; + mtsdr(SDR0_SRST1, sdr0_srst); + + /* 3. Wait for more than 1 ms */ + udelay(2000); + + /* 4. De-assert USB 2.0 Host main reset */ + mfsdr(SDR0_SRST0, sdr0_srst); + sdr0_srst = sdr0_srst &~ SDR0_SRST0_USB2H; + mtsdr(SDR0_SRST0, sdr0_srst); + udelay(1000); + + /* 5. De-assert reset of OPB2 cores */ + mfsdr(SDR0_SRST1, sdr0_srst); + sdr0_srst = sdr0_srst &~ SDR0_SRST1_PLB42OPB1; + sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPB2PLB40; + sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPBA2; + mtsdr(SDR0_SRST1, sdr0_srst); + udelay(1000); + + /* 6. Set EHCI Configure FLAG */ + + /* 7. Reassert internal PHY reset: */ + mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY); + udelay(1000); + /* * Clear resets */ - udelay (1000); mtsdr(SDR0_SRST1, 0x00000000); - udelay (1000); mtsdr(SDR0_SRST0, 0x00000000); printf("USB: Host(int phy) Device(ext phy)\n"); @@ -264,7 +335,7 @@ int checkboard(void) { char *s = getenv("serial#"); - printf("Board: lwmon5"); + puts("Board: lwmon5"); if (s != NULL) { puts(", serial# "); @@ -331,34 +402,33 @@ U_BOOT_CMD( extern GraphicDevice mb862xx; -static const gdc_regs init_regs [] = -{ - {0x0100, 0x00000f00}, - {0x0020, 0x801401df}, - {0x0024, 0x00000000}, - {0x0028, 0x00000000}, - {0x002c, 0x00000000}, - {0x0110, 0x00000000}, - {0x0114, 0x00000000}, - {0x0118, 0x01df0280}, - {0x0004, 0x031f0000}, - {0x0008, 0x027f027f}, - {0x000c, 0x015f028f}, - {0x0010, 0x020c0000}, - {0x0014, 0x01df01ea}, - {0x0018, 0x00000000}, - {0x001c, 0x01e00280}, - {0x0100, 0x80010f00}, - {0x0, 0x0} +static const gdc_regs init_regs [] = { + { 0x0100, 0x00000f00 }, + { 0x0020, 0x801401df }, + { 0x0024, 0x00000000 }, + { 0x0028, 0x00000000 }, + { 0x002c, 0x00000000 }, + { 0x0110, 0x00000000 }, + { 0x0114, 0x00000000 }, + { 0x0118, 0x01df0280 }, + { 0x0004, 0x031f0000 }, + { 0x0008, 0x027f027f }, + { 0x000c, 0x015f028f }, + { 0x0010, 0x020c0000 }, + { 0x0014, 0x01df01ea }, + { 0x0018, 0x00000000 }, + { 0x001c, 0x01e00280 }, + { 0x0100, 0x80010f00 }, + { 0x0, 0x0 } }; -const gdc_regs *board_get_regs (void) +const gdc_regs *board_get_regs(void) { return init_regs; } /* Returns Lime base address */ -unsigned int board_video_init (void) +unsigned int board_video_init(void) { /* * Reset Lime controller @@ -375,7 +445,7 @@ unsigned int board_video_init (void) return CONFIG_SYS_LIME_BASE_0; } -#define DEFAULT_BRIGHTNESS 0x64 +#define DEFAULT_BRIGHTNESS 0x64 static void board_backlight_brightness(int brightness) { @@ -390,7 +460,7 @@ static void board_backlight_brightness(int brightness) } } -void board_backlight_switch (int flag) +void board_backlight_switch(int flag) { char * param; int rc; @@ -410,15 +480,14 @@ void board_backlight_switch (int flag) /* * Return text to be printed besides the logo. */ -void video_get_info_str (int line_number, char *info) +void video_get_info_str(int line_number, char *info) { - if (line_number == 1) { - strcpy (info, " Board: Lwmon5 (Liebherr Elektronik GmbH)"); - } else { + if (line_number == 1) + strcpy(info, " Board: Lwmon5 (Liebherr Elektronik GmbH)"); + else info [0] = '\0'; - } } -#endif +#endif /* CONFIG_CONSOLE_EXTRA_INFO */ #endif /* CONFIG_VIDEO */ void board_reset(void) diff --git a/board/uc101/Makefile b/board/manroland/hmi1001/Makefile index 442e2d0df2..442e2d0df2 100644 --- a/board/uc101/Makefile +++ b/board/manroland/hmi1001/Makefile diff --git a/board/hmi1001/config.mk b/board/manroland/hmi1001/config.mk index 8ccf33e15c..8ccf33e15c 100644 --- a/board/hmi1001/config.mk +++ b/board/manroland/hmi1001/config.mk diff --git a/board/hmi1001/hmi1001.c b/board/manroland/hmi1001/hmi1001.c index 9cbed4b8c5..9cbed4b8c5 100644 --- a/board/hmi1001/hmi1001.c +++ b/board/manroland/hmi1001/hmi1001.c diff --git a/board/mucmc52/Makefile b/board/manroland/mucmc52/Makefile index 721c0164b2..721c0164b2 100644 --- a/board/mucmc52/Makefile +++ b/board/manroland/mucmc52/Makefile diff --git a/board/mucmc52/config.mk b/board/manroland/mucmc52/config.mk index 6850728331..6850728331 100644 --- a/board/mucmc52/config.mk +++ b/board/manroland/mucmc52/config.mk diff --git a/board/mucmc52/mucmc52.c b/board/manroland/mucmc52/mucmc52.c index 66973f09d1..66973f09d1 100644 --- a/board/mucmc52/mucmc52.c +++ b/board/manroland/mucmc52/mucmc52.c diff --git a/board/uc100/Makefile b/board/manroland/uc100/Makefile index 92ee091f68..92ee091f68 100644 --- a/board/uc100/Makefile +++ b/board/manroland/uc100/Makefile diff --git a/board/uc100/config.mk b/board/manroland/uc100/config.mk index a65a8ba2c7..a65a8ba2c7 100644 --- a/board/uc100/config.mk +++ b/board/manroland/uc100/config.mk diff --git a/board/uc100/pcmcia.c b/board/manroland/uc100/pcmcia.c index ad256783ce..ad256783ce 100644 --- a/board/uc100/pcmcia.c +++ b/board/manroland/uc100/pcmcia.c diff --git a/board/uc100/u-boot.lds b/board/manroland/uc100/u-boot.lds index 0d8f605946..0d8f605946 100644 --- a/board/uc100/u-boot.lds +++ b/board/manroland/uc100/u-boot.lds diff --git a/board/uc100/u-boot.lds.debug b/board/manroland/uc100/u-boot.lds.debug index a7caa8d90a..a7caa8d90a 100644 --- a/board/uc100/u-boot.lds.debug +++ b/board/manroland/uc100/u-boot.lds.debug diff --git a/board/uc100/uc100.c b/board/manroland/uc100/uc100.c index bdee4de366..bdee4de366 100644 --- a/board/uc100/uc100.c +++ b/board/manroland/uc100/uc100.c diff --git a/board/siemens/pcu_e/Makefile b/board/manroland/uc101/Makefile index dcb1907032..442e2d0df2 100644 --- a/board/siemens/pcu_e/Makefile +++ b/board/manroland/uc101/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2003-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o +COBJS := $(BOARD).o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) @@ -34,6 +34,12 @@ SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(obj).depend $(OBJS) $(AR) $(ARFLAGS) $@ $(OBJS) +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + ######################################################################### # defines $(obj).depend target diff --git a/board/uc101/config.mk b/board/manroland/uc101/config.mk index 8ccf33e15c..8ccf33e15c 100644 --- a/board/uc101/config.mk +++ b/board/manroland/uc101/config.mk diff --git a/board/uc101/uc101.c b/board/manroland/uc101/uc101.c index c7dfb7bad1..c7dfb7bad1 100644 --- a/board/uc101/uc101.c +++ b/board/manroland/uc101/uc101.c diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c index 624c7088ac..d3300ed681 100644 --- a/board/mpl/common/common_util.c +++ b/board/mpl/common/common_util.c @@ -430,12 +430,12 @@ void check_env(void) int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - ulong size,src,ld_addr; + ulong ld_addr; int result; #if !defined(CONFIG_PATI) + ulong size = IMAGE_SIZE; + ulong src = MULTI_PURPOSE_SOCKET_ADDR; backup_t back; - src = MULTI_PURPOSE_SOCKET_ADDR; - size = IMAGE_SIZE; #endif if (strcmp(argv[1], "flash") == 0) @@ -480,30 +480,6 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } #endif /* #if !defined(CONFIG_PATI) */ } - if (strcmp(argv[1], "mem") == 0) - { - result=0; - if(argc==3) - { - result = (int)simple_strtol(argv[2], NULL, 16); - } - src=(unsigned long)&result; - src-=CONFIG_SYS_MEMTEST_START; - src-=(100*1024); /* - 100k */ - src&=0xfff00000; - size=0; - do { - size++; - printf("\n\nPass %ld\n",size); - mem_test(CONFIG_SYS_MEMTEST_START,src,1); - if(ctrlc()) - break; - if(result>0) - result--; - - }while(result); - return 0; - } #if !defined(CONFIG_PATI) if (strcmp(argv[1], "clearenvvalues") == 0) { diff --git a/board/mpl/common/memtst.c b/board/mpl/common/memtst.c deleted file mode 100644 index 9c08065992..0000000000 --- a/board/mpl/common/memtst.c +++ /dev/null @@ -1,565 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -/* NOT Used yet... - add following code to PIP405.c : -int testdram (void) -{ - unsigned char s[32]; - int i; - - i = getenv_f("testmem", s, 32); - if (i != 0) { - i = (int) simple_strtoul (s, NULL, 10); - if ((i > 0) && (i < 0xf)) { - printf ("testing "); - i = mem_test (0, ramsize, i); - if (i > 0) - printf ("ERROR "); - else - printf ("Ok "); - } - } - return (1); -} -*/ - - -#include <common.h> -#include <asm/processor.h> -#include <asm/ppc4xx-i2c.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define FALSE 0 -#define TRUE 1 - -#define TEST_QUIET 8 -#define TEST_SHOW_PROG 4 -#define TEST_SHOW_ERR 2 -#define TEST_SHOW_ALL 1 - -#define TESTPAT1 0xAA55AA55 -#define TESTPAT2 0x55AA55AA -#define TEST_PASSED 0 -#define TEST_FAILED 1 -#define MEGABYTE (1024*1024) - - -typedef struct { - volatile unsigned long pat1; - volatile unsigned long pat2; -} RAM_MEMTEST_PATTERN2; - -typedef struct { - volatile unsigned long addr; -} RAM_MEMTEST_ADDRLINE; - -static __inline unsigned long Swap_32 (unsigned long val) -{ - return (((val << 16) & 0xFFFF0000) | ((val >> 16) & 0x0000FFFF)); -} - -void testm_puts (int quiet, char *buf) -{ - if ((quiet & TEST_SHOW_ALL) == TEST_SHOW_ALL) - puts (buf); -} - - -void Write_Error (int mode, unsigned long addr, unsigned long expected, - unsigned long actual) -{ - - char dispbuf[64]; - - sprintf (dispbuf, "\n ERROR @ 0x%08lX: (exp: 0x%08lX act: 0x%08lX) ", - addr, expected, actual); - testm_puts (((mode & TEST_SHOW_ERR) == - TEST_SHOW_ERR) ? TEST_SHOW_ALL : mode, dispbuf); -} - - -/* - * fills the memblock of <size> bytes from <startaddr> with pat1 and pat2 - */ - - -void RAM_MemTest_WritePattern2 (unsigned long startaddr, - unsigned long size, unsigned long pat1, - unsigned long pat2) -{ - RAM_MEMTEST_PATTERN2 *p, *pe; - - p = (RAM_MEMTEST_PATTERN2 *) startaddr; - pe = (RAM_MEMTEST_PATTERN2 *) (startaddr + size); - - while (p < pe) { - p->pat1 = pat1; - p->pat2 = pat2; - p++; - } /* endwhile */ -} - -/* - * checks the memblock of <size> bytes from <startaddr> with pat1 and pat2 - * returns the address of the first error or NULL if all is well - */ - -void *RAM_MemTest_CheckPattern2 (int mode, unsigned long startaddr, - unsigned long size, unsigned long pat1, - unsigned long pat2) -{ - RAM_MEMTEST_PATTERN2 *p, *pe; - unsigned long actual1, actual2; - - p = (RAM_MEMTEST_PATTERN2 *) startaddr; - pe = (RAM_MEMTEST_PATTERN2 *) (startaddr + size); - - while (p < pe) { - actual1 = p->pat1; - actual2 = p->pat2; - - if (actual1 != pat1) { - Write_Error (mode, (unsigned long) &(p->pat1), pat1, actual1); - return ((void *) &(p->pat1)); - } - /* endif */ - if (actual2 != pat2) { - Write_Error (mode, (unsigned long) &(p->pat2), pat2, actual2); - return ((void *) &(p->pat2)); - } - /* endif */ - p++; - } /* endwhile */ - - return (NULL); -} - -/* - * fills the memblock of <size> bytes from <startaddr> with the address - */ - -void RAM_MemTest_WriteAddrLine (unsigned long startaddr, - unsigned long size, int swapped) -{ - RAM_MEMTEST_ADDRLINE *p, *pe; - - p = (RAM_MEMTEST_ADDRLINE *) startaddr; - pe = (RAM_MEMTEST_ADDRLINE *) (startaddr + size); - - if (!swapped) { - while (p < pe) { - p->addr = (unsigned long) p; - p++; - } /* endwhile */ - } else { - while (p < pe) { - p->addr = Swap_32 ((unsigned long) p); - p++; - } /* endwhile */ - } /* endif */ -} - -/* - * checks the memblock of <size> bytes from <startaddr> - * returns the address of the error or NULL if all is well - */ - -void *RAM_MemTest_CheckAddrLine (int mode, unsigned long startaddr, - unsigned long size, int swapped) -{ - RAM_MEMTEST_ADDRLINE *p, *pe; - unsigned long actual, expected; - - p = (RAM_MEMTEST_ADDRLINE *) startaddr; - pe = (RAM_MEMTEST_ADDRLINE *) (startaddr + size); - - if (!swapped) { - while (p < pe) { - actual = p->addr; - expected = (unsigned long) p; - if (actual != expected) { - Write_Error (mode, (unsigned long) &(p->addr), expected, - actual); - return ((void *) &(p->addr)); - } /* endif */ - p++; - } /* endwhile */ - } else { - while (p < pe) { - actual = p->addr; - expected = Swap_32 ((unsigned long) p); - if (actual != expected) { - Write_Error (mode, (unsigned long) &(p->addr), expected, - actual); - return ((void *) &(p->addr)); - } /* endif */ - p++; - } /* endwhile */ - } /* endif */ - - return (NULL); -} - -/* - * checks the memblock of <size> bytes from <startaddr+size> - * returns the address of the error or NULL if all is well - */ - -void *RAM_MemTest_CheckAddrLineReverse (int mode, unsigned long startaddr, - unsigned long size, int swapped) -{ - RAM_MEMTEST_ADDRLINE *p, *pe; - unsigned long actual, expected; - - p = (RAM_MEMTEST_ADDRLINE *) (startaddr + size - sizeof (p->addr)); - pe = (RAM_MEMTEST_ADDRLINE *) startaddr; - - if (!swapped) { - while (p > pe) { - actual = p->addr; - expected = (unsigned long) p; - if (actual != expected) { - Write_Error (mode, (unsigned long) &(p->addr), expected, - actual); - return ((void *) &(p->addr)); - } /* endif */ - p--; - } /* endwhile */ - } else { - while (p > pe) { - actual = p->addr; - expected = Swap_32 ((unsigned long) p); - if (actual != expected) { - Write_Error (mode, (unsigned long) &(p->addr), expected, - actual); - return ((void *) &(p->addr)); - } /* endif */ - p--; - } /* endwhile */ - } /* endif */ - - return (NULL); -} - -/* - * fills the memblock of <size> bytes from <startaddr> with walking bit pattern - */ - -void RAM_MemTest_WriteWalkBit (unsigned long startaddr, unsigned long size) -{ - volatile unsigned long *p, *pe; - unsigned long i; - - p = (unsigned long *) startaddr; - pe = (unsigned long *) (startaddr + size); - i = 0; - - while (p < pe) { - *p = 1UL << i; - i = (i + 1 + (((unsigned long) p) >> 7)) % 32; - p++; - } /* endwhile */ -} - -/* - * checks the memblock of <size> bytes from <startaddr> - * returns the address of the error or NULL if all is well - */ - -void *RAM_MemTest_CheckWalkBit (int mode, unsigned long startaddr, - unsigned long size) -{ - volatile unsigned long *p, *pe; - unsigned long actual, expected; - unsigned long i; - - p = (unsigned long *) startaddr; - pe = (unsigned long *) (startaddr + size); - i = 0; - - while (p < pe) { - actual = *p; - expected = (1UL << i); - if (actual != expected) { - Write_Error (mode, (unsigned long) p, expected, actual); - return ((void *) p); - } /* endif */ - i = (i + 1 + (((unsigned long) p) >> 7)) % 32; - p++; - } /* endwhile */ - - return (NULL); -} - -/* - * fills the memblock of <size> bytes from <startaddr> with "random" pattern - */ - -void RAM_MemTest_WriteRandomPattern (unsigned long startaddr, - unsigned long size, - unsigned long *pat) -{ - unsigned long i, p; - - p = *pat; - - for (i = 0; i < (size / 4); i++) { - *(unsigned long *) (startaddr + i * 4) = p; - if ((p % 2) > 0) { - p ^= i; - p >>= 1; - p |= 0x80000000; - } else { - p ^= ~i; - p >>= 1; - } /* endif */ - } /* endfor */ - *pat = p; -} - -/* - * checks the memblock of <size> bytes from <startaddr> - * returns the address of the error or NULL if all is well - */ - -void *RAM_MemTest_CheckRandomPattern (int mode, unsigned long startaddr, - unsigned long size, - unsigned long *pat) -{ - void *perr = NULL; - unsigned long i, p, p1; - - p = *pat; - - for (i = 0; i < (size / 4); i++) { - p1 = *(unsigned long *) (startaddr + i * 4); - if (p1 != p) { - if (perr == NULL) { - Write_Error (mode, startaddr + i * 4, p, p1); - perr = (void *) (startaddr + i * 4); - } /* endif */ - } - /* endif */ - if ((p % 2) > 0) { - p ^= i; - p >>= 1; - p |= 0x80000000; - } else { - p ^= ~i; - p >>= 1; - } /* endif */ - } /* endfor */ - - *pat = p; - return (perr); -} - - -void RAM_MemTest_WriteData1 (unsigned long startaddr, unsigned long size, - unsigned long *pat) -{ - RAM_MemTest_WritePattern2 (startaddr, size, TESTPAT1, TESTPAT2); -} - -void *RAM_MemTest_CheckData1 (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat) -{ - return (RAM_MemTest_CheckPattern2 - (mode, startaddr, size, TESTPAT1, TESTPAT2)); -} - -void RAM_MemTest_WriteData2 (unsigned long startaddr, unsigned long size, - unsigned long *pat) -{ - RAM_MemTest_WritePattern2 (startaddr, size, TESTPAT2, TESTPAT1); -} - -void *RAM_MemTest_CheckData2 (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat) -{ - return (RAM_MemTest_CheckPattern2 - (mode, startaddr, size, TESTPAT2, TESTPAT1)); -} - -void RAM_MemTest_WriteAddr1 (unsigned long startaddr, unsigned long size, - unsigned long *pat) -{ - RAM_MemTest_WriteAddrLine (startaddr, size, FALSE); -} - -void *RAM_MemTest_Check1Addr1 (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat) -{ - return (RAM_MemTest_CheckAddrLine (mode, startaddr, size, FALSE)); -} - -void *RAM_MemTest_Check2Addr1 (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat) -{ - return (RAM_MemTest_CheckAddrLineReverse - (mode, startaddr, size, FALSE)); -} - -void RAM_MemTest_WriteAddr2 (unsigned long startaddr, unsigned long size, - unsigned long *pat) -{ - RAM_MemTest_WriteAddrLine (startaddr, size, TRUE); -} - -void *RAM_MemTest_Check1Addr2 (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat) -{ - return (RAM_MemTest_CheckAddrLine (mode, startaddr, size, TRUE)); -} - -void *RAM_MemTest_Check2Addr2 (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat) -{ - return (RAM_MemTest_CheckAddrLineReverse - (mode, startaddr, size, TRUE)); -} - - -typedef struct { - void (*test_write) (unsigned long startaddr, unsigned long size, - unsigned long *pat); - char *test_write_desc; - void *(*test_check1) (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat); - void *(*test_check2) (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat); -} RAM_MEMTEST_FUNC; - - -#define TEST_STAGES 5 -static RAM_MEMTEST_FUNC test_stage[TEST_STAGES] = { - {RAM_MemTest_WriteData1, "data test 1...\n", RAM_MemTest_CheckData1, - NULL}, - {RAM_MemTest_WriteData2, "data test 2...\n", RAM_MemTest_CheckData2, - NULL}, - {RAM_MemTest_WriteAddr1, "address line test...\n", - RAM_MemTest_Check1Addr1, RAM_MemTest_Check2Addr1}, - {RAM_MemTest_WriteAddr2, "address line test (swapped)...\n", - RAM_MemTest_Check1Addr2, RAM_MemTest_Check2Addr2}, - {RAM_MemTest_WriteRandomPattern, "random data test...\n", - RAM_MemTest_CheckRandomPattern, NULL} -}; - - -int mem_test (unsigned long start, unsigned long ramsize, int quiet) -{ - unsigned long errors, stage; - unsigned long startaddr, size, i; - const unsigned long blocksize = 0x80000; /* check in 512KB blocks */ - unsigned long *perr; - unsigned long rdatapat; - char dispbuf[80]; - int status = TEST_PASSED; - int prog = 0; - - errors = 0; - startaddr = start; - size = ramsize; - if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) { - prog++; - printf ("."); - } - sprintf (dispbuf, "\nMemory Test: addr = 0x%lx size = 0x%lx\n", - startaddr, size); - testm_puts (quiet, dispbuf); - for (stage = 0; stage < TEST_STAGES; stage++) { - sprintf (dispbuf, test_stage[stage].test_write_desc); - testm_puts (quiet, dispbuf); - /* fill SDRAM */ - rdatapat = 0x12345678; - sprintf (dispbuf, "writing block: "); - testm_puts (quiet, dispbuf); - for (i = 0; i < size; i += blocksize) { - sprintf (dispbuf, "%04lX\b\b\b\b", i / blocksize); - testm_puts (quiet, dispbuf); - test_stage[stage].test_write (startaddr + i, blocksize, - &rdatapat); - } /* endfor */ - sprintf (dispbuf, "\n"); - testm_puts (quiet, dispbuf); - if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) { - prog++; - printf ("."); - } - /* check SDRAM */ - rdatapat = 0x12345678; - sprintf (dispbuf, "checking block: "); - testm_puts (quiet, dispbuf); - for (i = 0; i < size; i += blocksize) { - sprintf (dispbuf, "%04lX\b\b\b\b", i / blocksize); - testm_puts (quiet, dispbuf); - if ((perr = - test_stage[stage].test_check1 (quiet, startaddr + i, - blocksize, - &rdatapat)) != NULL) { - status = TEST_FAILED; - } /* endif */ - } /* endfor */ - sprintf (dispbuf, "\n"); - testm_puts (quiet, dispbuf); - if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) { - prog++; - printf ("."); - } - if (test_stage[stage].test_check2 != NULL) { - /* check2 SDRAM */ - sprintf (dispbuf, "2nd checking block: "); - rdatapat = 0x12345678; - testm_puts (quiet, dispbuf); - for (i = 0; i < size; i += blocksize) { - sprintf (dispbuf, "%04lX\b\b\b\b", i / blocksize); - testm_puts (quiet, dispbuf); - if ((perr = - test_stage[stage].test_check2 (quiet, startaddr + i, - blocksize, - &rdatapat)) != NULL) { - status = TEST_FAILED; - } /* endif */ - } /* endfor */ - sprintf (dispbuf, "\n"); - testm_puts (quiet, dispbuf); - if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) { - prog++; - printf ("."); - } - } - - } /* next stage */ - if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) { - while (prog-- > 0) - printf ("\b \b"); - } - - if (status == TEST_FAILED) - errors++; - - return (errors); -} diff --git a/board/mpl/mip405/Makefile b/board/mpl/mip405/Makefile index 18a8d8656c..21e3cdaeca 100644 --- a/board/mpl/mip405/Makefile +++ b/board/mpl/mip405/Makefile @@ -29,7 +29,7 @@ endif LIB = $(obj)lib$(BOARD).a COBJS = $(BOARD).o ../common/flash.o cmd_mip405.o ../common/pci.o \ - ../common/usb_uhci.o ../common/memtst.o ../common/common_util.o + ../common/usb_uhci.o ../common/common_util.o SOBJS = init.o diff --git a/board/mpl/mip405/cmd_mip405.c b/board/mpl/mip405/cmd_mip405.c index 8ddb54db1c..f7cc37b849 100644 --- a/board/mpl/mip405/cmd_mip405.c +++ b/board/mpl/mip405/cmd_mip405.c @@ -59,8 +59,7 @@ U_BOOT_CMD( "flash mem [SrcAddr] - updates U-Boot with image in memory\n" "mip405 flash mps - updates U-Boot with image from MPS\n" "mip405 info - displays board information\n" - "mip405 led <on> - switches LED on (on=1) or off (on=0)\n" - "mip405 mem [cnt] - Memory Test <cnt>-times, <cnt> = -1 loop forever" + "mip405 led <on> - switches LED on (on=1) or off (on=0)" ); /* ------------------------------------------------------------------------- */ diff --git a/board/mpl/pati/Makefile b/board/mpl/pati/Makefile index adeba69ee0..9f38d706ce 100644 --- a/board/mpl/pati/Makefile +++ b/board/mpl/pati/Makefile @@ -28,7 +28,7 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS := pati.o ../common/flash.o ../common/memtst.o cmd_pati.o ../common/common_util.o +COBJS := pati.o ../common/flash.o cmd_pati.o ../common/common_util.o #### cmd_pati.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/mpl/pip405/Makefile b/board/mpl/pip405/Makefile index 774b59f84e..fb39ec3ec3 100644 --- a/board/mpl/pip405/Makefile +++ b/board/mpl/pip405/Makefile @@ -32,7 +32,7 @@ COBJS = $(BOARD).o \ ../common/flash.o cmd_pip405.o ../common/pci.o \ ../common/isa.o ../common/kbd.o \ ../common/usb_uhci.o \ - ../common/memtst.o ../common/common_util.o + ../common/common_util.o SOBJS = init.o diff --git a/board/mpl/vcma9/Makefile b/board/mpl/vcma9/Makefile index 10bcb3b0a7..3f629fc099 100644 --- a/board/mpl/vcma9/Makefile +++ b/board/mpl/vcma9/Makefile @@ -29,7 +29,7 @@ endif LIB = $(obj)lib$(BOARD).a COBJS := vcma9.o flash.o cmd_vcma9.o -COBJS += ../common/common_util.o ../common/memtst.o +COBJS += ../common/common_util.o SOBJS := lowlevel_init.o diff --git a/board/pdm360ng/pdm360ng.c b/board/pdm360ng/pdm360ng.c index e3abeb8ef1..2082ad48a2 100644 --- a/board/pdm360ng/pdm360ng.c +++ b/board/pdm360ng/pdm360ng.c @@ -237,9 +237,6 @@ int misc_init_r(void) #endif #ifdef CONFIG_FSL_DIU_FB -# if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)) - mpc5121_diu_init(); -#endif #if defined(CONFIG_SERIAL_MULTI) set_lcd_brightness(0); #endif @@ -518,6 +515,46 @@ struct node_info nodes[] = { }; #endif +#if defined(CONFIG_VIDEO) +/* + * EDID block has been generated using Phoenix EDID Designer 1.3. + * This tool creates a text file containing: + * + * EDID BYTES: + * 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F + * ------------------------------------------------ + * 00 | 00 FF FF FF FF FF FF 00 42 C9 34 12 01 00 00 00 + * 10 | 0A 0C 01 03 80 98 5B 78 CA 7E 50 A0 58 4E 96 25 + * 20 | 1E 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 + * 30 | 01 01 01 01 01 01 80 0C 20 00 31 E0 2D 10 2A 80 + * 40 | 12 08 30 E4 10 00 00 18 00 00 00 FD 00 38 3C 1F + * 50 | 3C 04 0A 20 20 20 20 20 20 20 00 00 00 FF 00 50 + * 60 | 4D 30 37 30 57 4C 33 0A 0A 0A 0A 0A 00 00 00 FF + * 70 | 00 41 30 30 30 30 30 30 30 30 30 30 30 31 00 D4 + * + * Then this data has been manually converted to the char + * array below. + */ +static unsigned char edid_buf[128] = { + 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, + 0x42, 0xC9, 0x34, 0x12, 0x01, 0x00, 0x00, 0x00, + 0x0A, 0x0C, 0x01, 0x03, 0x80, 0x98, 0x5B, 0x78, + 0xCA, 0x7E, 0x50, 0xA0, 0x58, 0x4E, 0x96, 0x25, + 0x1E, 0x50, 0x54, 0x00, 0x00, 0x00, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x80, 0x0C, + 0x20, 0x00, 0x31, 0xE0, 0x2D, 0x10, 0x2A, 0x80, + 0x12, 0x08, 0x30, 0xE4, 0x10, 0x00, 0x00, 0x18, + 0x00, 0x00, 0x00, 0xFD, 0x00, 0x38, 0x3C, 0x1F, + 0x3C, 0x04, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x50, + 0x4D, 0x30, 0x37, 0x30, 0x57, 0x4C, 0x33, 0x0A, + 0x0A, 0x0A, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0xFF, + 0x00, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, + 0x30, 0x30, 0x30, 0x30, 0x30, 0x31, 0x00, 0xD4, +}; +#endif + void ft_board_setup(void *blob, bd_t *bd) { u32 val[8]; @@ -528,6 +565,9 @@ void ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_FDT_FIXUP_PARTITIONS fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); #endif +#if defined(CONFIG_VIDEO) + fdt_add_edid(blob, "fsl,mpc5121-diu", edid_buf); +#endif /* Fixup NOR FLASH mapping */ val[i++] = 0; /* chip select number */ diff --git a/board/ppmc7xx/ppmc7xx.c b/board/ppmc7xx/ppmc7xx.c index 0cad897349..5e7427f370 100644 --- a/board/ppmc7xx/ppmc7xx.c +++ b/board/ppmc7xx/ppmc7xx.c @@ -19,8 +19,7 @@ /* Function prototypes */ -extern void unlock_ram_in_cache( void ); -extern void _start_warm(void); +extern void _start(void); /* @@ -97,8 +96,8 @@ void do_reset( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] ) icache_disable(); dcache_disable(); - /* Jump to warm start (in RAM) */ - _start_warm(); + /* Jump to cold reset point (in RAM) */ + _start(); /* Should never get here */ while(1); diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index e41c84c763..4dc0237b9e 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -96,7 +96,6 @@ static void pm9263_nand_hw_init(void) static void pm9263_macb_hw_init(void) { at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; - at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; /* * PB27 enables the 50MHz oscillator for Ethernet PHY diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c index 3b4d9a3459..f3d48f233e 100644 --- a/board/ronetix/pm9g45/pm9g45.c +++ b/board/ronetix/pm9g45/pm9g45.c @@ -96,7 +96,6 @@ static void pm9g45_nand_hw_init(void) static void pm9g45_macb_hw_init(void) { at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; - at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; /* * PD2 enables the 50MHz oscillator for Ethernet PHY diff --git a/board/siemens/CCM/ccm.c b/board/siemens/CCM/ccm.c deleted file mode 100644 index e91ceb079a..0000000000 --- a/board/siemens/CCM/ccm.c +++ /dev/null @@ -1,408 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <mpc8xx.h> -#include <commproc.h> -#include <command.h> - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); -void can_driver_enable (void); -void can_driver_disable (void); - -int fpga_init(void); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = -{ - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00, - 0x1FF5FC47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */ - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - * Always return 1 (no second DRAM bank since based on TQM8xxL module) - */ - -int checkboard (void) -{ - unsigned char *s; - unsigned char buf[64]; - - s = (getenv_f("serial#", (char *)&buf, sizeof(buf)) > 0) ? buf : NULL; - - puts ("Board: Siemens CCM"); - - if (s) { - puts (" ("); - - for (; *s; ++s) { - if (*s == ' ') - break; - putc (*s); - } - putc (')'); - } - - putc ('\n'); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * If Power-On-Reset switch off the Red and Green LED: At reset, the - * data direction registers are cleared and must therefore be restored. - */ -#define RSR_CSRS 0x08000000 - -int power_on_reset(void) -{ - /* Test Reset Status Register */ - return ((volatile immap_t *)CONFIG_SYS_IMMR)->im_clkrst.car_rsr & RSR_CSRS ? 0:1; -} - -#define PB_LED_GREEN 0x10000 /* red LED is on PB.15 */ -#define PB_LED_RED 0x20000 /* red LED is on PB.14 */ -#define PB_LEDS (PB_LED_GREEN | PB_LED_RED); - -static void init_leds (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - - immap->im_cpm.cp_pbpar &= ~PB_LEDS; - immap->im_cpm.cp_pbodr &= ~PB_LEDS; - immap->im_cpm.cp_pbdir |= PB_LEDS; - /* Check stop reset status */ - if (power_on_reset()) { - immap->im_cpm.cp_pbdat &= ~PB_LEDS; - } -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size8, size9; - long int size = 0; - unsigned long reg; - - upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; - - memctl->memc_mar = 0x00000088; - - /* - * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at - * preliminary addresses - these have to be modified after the - * SDRAM size has been determined. - */ - memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; - memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; - - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay(200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */ - udelay(1); - memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */ - udelay(1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size = size9; -/* debug ("SDRAM in 9 column mode: %ld MB\n", size >> 20); */ - } else { /* back to 8 columns */ - size = size8; - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; - udelay(500); -/* debug ("SDRAM in 8 column mode: %ld MB\n", size >> 20); */ - } - - udelay (1000); - - /* - * Adjust refresh rate depending on SDRAM type - * For types > 128 MBit leave it at the current (fast) rate - */ - if (size < 0x02000000) { - /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; - udelay(1000); - } - - /* - * Final mapping - */ - - memctl->memc_or2 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - - can_driver_enable (); - init_leds (); - - udelay(10000); - - return (size); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Warning - both the PUMA load mode and the CAN driver use UPM B, - * so make sure only one of both is active. - */ -void can_driver_enable (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - /* Initialize MBMR */ - memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */ - - /* Initialize UPMB for CAN: single read */ - memctl->memc_mdr = 0xFFFFC004; - memctl->memc_mcr = 0x0100 | UPMB; - - memctl->memc_mdr = 0x0FFFD004; - memctl->memc_mcr = 0x0101 | UPMB; - - memctl->memc_mdr = 0x0FFFC000; - memctl->memc_mcr = 0x0102 | UPMB; - - memctl->memc_mdr = 0x3FFFC004; - memctl->memc_mcr = 0x0103 | UPMB; - - memctl->memc_mdr = 0xFFFFDC05; - memctl->memc_mcr = 0x0104 | UPMB; - - /* Initialize UPMB for CAN: single write */ - memctl->memc_mdr = 0xFFFCC004; - memctl->memc_mcr = 0x0118 | UPMB; - - memctl->memc_mdr = 0xCFFCD004; - memctl->memc_mcr = 0x0119 | UPMB; - - memctl->memc_mdr = 0x0FFCC000; - memctl->memc_mcr = 0x011A | UPMB; - - memctl->memc_mdr = 0x7FFCC004; - memctl->memc_mcr = 0x011B | UPMB; - - memctl->memc_mdr = 0xFFFDCC05; - memctl->memc_mcr = 0x011C | UPMB; - - /* Initialize OR3 / BR3 for CAN Bus Controller */ - memctl->memc_or3 = CONFIG_SYS_OR3_CAN; - memctl->memc_br3 = CONFIG_SYS_BR3_CAN; -} - -void can_driver_disable (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - /* Reset OR3 / BR3 to disable CAN Bus Controller */ - memctl->memc_br3 = 0; - memctl->memc_or3 = 0; - - memctl->memc_mbmr = 0; -} - - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, long int maxsize) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} - -/* ------------------------------------------------------------------------- */ - -#define ETH_CFG_BITS (CONFIG_SYS_PB_ETH_CFG1 | CONFIG_SYS_PB_ETH_CFG2 | CONFIG_SYS_PB_ETH_CFG3 ) - -#define ETH_ALL_BITS (ETH_CFG_BITS | CONFIG_SYS_PB_ETH_POWERDOWN) - -void reset_phy(void) -{ - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - ulong value; - - /* Configure all needed port pins for GPIO */ -#ifdef CONFIG_SYS_ETH_MDDIS_VALUE - immr->im_ioport.iop_padat |= CONFIG_SYS_PA_ETH_MDDIS; -#else - immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET); /* Set low */ -#endif - immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET); /* GPIO */ - immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET); /* active output */ - immr->im_ioport.iop_padir |= CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET; /* output */ - - immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */ - immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */ - - value = immr->im_cpm.cp_pbdat; - - /* Assert Powerdown and Reset signals */ - value |= CONFIG_SYS_PB_ETH_POWERDOWN; - - /* PHY configuration includes MDDIS and CFG1 ... CFG3 */ -#ifdef CONFIG_SYS_ETH_CFG1_VALUE - value |= CONFIG_SYS_PB_ETH_CFG1; -#else - value &= ~(CONFIG_SYS_PB_ETH_CFG1); -#endif -#ifdef CONFIG_SYS_ETH_CFG2_VALUE - value |= CONFIG_SYS_PB_ETH_CFG2; -#else - value &= ~(CONFIG_SYS_PB_ETH_CFG2); -#endif -#ifdef CONFIG_SYS_ETH_CFG3_VALUE - value |= CONFIG_SYS_PB_ETH_CFG3; -#else - value &= ~(CONFIG_SYS_PB_ETH_CFG3); -#endif - - /* Drive output signals to initial state */ - immr->im_cpm.cp_pbdat = value; - immr->im_cpm.cp_pbdir |= ETH_ALL_BITS; - udelay (10000); - - /* De-assert Ethernet Powerdown */ - immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* Enable PHY power */ - udelay (10000); - - /* de-assert RESET signal of PHY */ - immr->im_ioport.iop_padat |= CONFIG_SYS_PA_ETH_RESET; - udelay (1000); -} - - -int misc_init_r (void) -{ - fpga_init(); - return (0); -} -/* ------------------------------------------------------------------------- */ diff --git a/board/siemens/CCM/flash.c b/board/siemens/CCM/flash.c deleted file mode 100644 index ad1ed793de..0000000000 --- a/board/siemens/CCM/flash.c +++ /dev/null @@ -1,553 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <mpc8xx.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } - - size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]); - - if (size_b1 > size_b0) { - printf ("## ERROR: " - "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1<<20, - size_b0, size_b0<<20 - ); - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - return (0); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - if (size_b1) { - memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); - memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) | - BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0), - &flash_info[1]); - - flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[1]); -#endif - } else { - memctl->memc_br1 = 0; /* invalidate bank */ - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - return (size_b0 + size_b1); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } - -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; - - value = addr[0]; - - switch (value) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - switch (value) { - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0x00F000F0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x00300030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); - while ((addr[0] & 0x00800080) != 0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; - addr[0] = 0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/siemens/CCM/fpga_ccm.c b/board/siemens/CCM/fpga_ccm.c deleted file mode 100644 index 50b08abce7..0000000000 --- a/board/siemens/CCM/fpga_ccm.c +++ /dev/null @@ -1,169 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include <common.h> -#include <mpc8xx.h> -#include <commproc.h> -#include <common.h> - -#include "../common/fpga.h" - -fpga_t fpga_list[] = { - { "PUMA" , PUMA_CONF_BASE , - CONFIG_SYS_PC_PUMA_INIT , CONFIG_SYS_PC_PUMA_PROG , CONFIG_SYS_PC_PUMA_DONE } -}; -int fpga_count = sizeof(fpga_list) / sizeof(fpga_t); - -void can_driver_enable (void); -void can_driver_disable (void); - -#define _NOT_USED_ 0xFFFFFFFF - -/* - * PUMA access using UPM B - */ -const uint puma_table[] = -{ - /* - * Single Read. (Offset 0 in UPM RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, - /* - * Precharge and MRS - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Read. (Offset 8 in UPM RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPM RAM) - */ - 0x0FFCF804, 0x0FFCF400, 0x3FFDFC47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPM RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPM RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPM RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - - -ulong fpga_control (fpga_t* fpga, int cmd) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - - switch (cmd) { - case FPGA_INIT_IS_HIGH: - immr->im_ioport.iop_pcdir &= ~fpga->init_mask; /* input */ - return (immr->im_ioport.iop_pcdat & fpga->init_mask) ? 1:0; - - case FPGA_INIT_SET_LOW: - immr->im_ioport.iop_pcdir |= fpga->init_mask; /* output */ - immr->im_ioport.iop_pcdat &= ~fpga->init_mask; - break; - - case FPGA_INIT_SET_HIGH: - immr->im_ioport.iop_pcdir |= fpga->init_mask; /* output */ - immr->im_ioport.iop_pcdat |= fpga->init_mask; - break; - - case FPGA_PROG_SET_LOW: - immr->im_ioport.iop_pcdat &= ~fpga->prog_mask; - break; - - case FPGA_PROG_SET_HIGH: - immr->im_ioport.iop_pcdat |= fpga->prog_mask; - break; - - case FPGA_DONE_IS_HIGH: - return (immr->im_ioport.iop_pcdat & fpga->done_mask) ? 1:0; - - case FPGA_READ_MODE: - /* disable FPGA in memory controller */ - memctl->memc_br4 = 0; - memctl->memc_or4 = PUMA_CONF_OR_READ; - memctl->memc_br4 = PUMA_CONF_BR_READ; - - /* (re-) enable CAN drivers */ - can_driver_enable (); - - break; - - case FPGA_LOAD_MODE: - /* disable FPGA in memory controller */ - memctl->memc_br4 = 0; - /* - * We must disable the CAN drivers first because - * they use UPM B, too. - */ - can_driver_disable (); - /* - * Configure UPMB for FPGA - */ - upmconfig(UPMB,(uint *)puma_table,sizeof(puma_table)/sizeof(uint)); - memctl->memc_or4 = PUMA_CONF_OR_LOAD; - memctl->memc_br4 = PUMA_CONF_BR_LOAD; - break; - - case FPGA_GET_ID: - return *(volatile ulong *)fpga->conf_base; - - case FPGA_INIT_PORTS: - immr->im_ioport.iop_pcpar &= ~fpga->init_mask; /* INIT I/O */ - immr->im_ioport.iop_pcso &= ~fpga->init_mask; - immr->im_ioport.iop_pcdir &= ~fpga->init_mask; - - immr->im_ioport.iop_pcpar &= ~fpga->prog_mask; /* PROG Output */ - immr->im_ioport.iop_pcso &= ~fpga->prog_mask; - immr->im_ioport.iop_pcdir |= fpga->prog_mask; - - immr->im_ioport.iop_pcpar &= ~fpga->done_mask; /* DONE Input */ - immr->im_ioport.iop_pcso &= ~fpga->done_mask; - immr->im_ioport.iop_pcdir &= ~fpga->done_mask; - - break; - - } - return 0; -} diff --git a/board/siemens/CCM/u-boot.lds b/board/siemens/CCM/u-boot.lds deleted file mode 100644 index 36dd55dee4..0000000000 --- a/board/siemens/CCM/u-boot.lds +++ /dev/null @@ -1,138 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - arch/powerpc/lib/ppcstring.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - lib/zlib.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(4); - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/siemens/CCM/u-boot.lds.debug b/board/siemens/CCM/u-boot.lds.debug deleted file mode 100644 index 7e066b11e5..0000000000 --- a/board/siemens/CCM/u-boot.lds.debug +++ /dev/null @@ -1,135 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) -/* - . = env_offset; - common/env_embedded.o(.text) -*/ - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/siemens/pcu_e/flash.c b/board/siemens/pcu_e/flash.c deleted file mode 100644 index 3ce7bb329a..0000000000 --- a/board/siemens/pcu_e/flash.c +++ /dev/null @@ -1,700 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <mpc8xx.h> - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -/*---------------------------------------------------------------------*/ -#undef DEBUG_FLASH - -#ifdef DEBUG_FLASH -#define DEBUGF(fmt,args...) printf(fmt ,##args) -#else -#define DEBUGF(fmt,args...) -#endif -/*---------------------------------------------------------------------*/ - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_data (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - * - * The PCU E uses an address map where flash banks are aligned top - * down, so that the "first" flash bank ends at top of memory, and - * the monitor entry point is at address (0xFFF00100). The second - * flash bank is mapped immediately below bank 0. - * - * This is NOT in conformance to the "official" memory map! - * - */ - -#define PCU_MONITOR_BASE ( (flash_info[0].start[0] + flash_info[0].size - 1) \ - - (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE) ) - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long base, size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - /* - * Warning: - * - * Since the PCU E memory map assigns flash banks top down, - * we swap the numbering later if both banks are equipped, - * so they look like a contiguous area of memory. - */ - DEBUGF("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM); - - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } - - DEBUGF("## Get flash bank 2 size @ 0x%08x\n",FLASH_BASE6_PRELIM); - size_b1 = flash_get_size((vu_long *)FLASH_BASE6_PRELIM, &flash_info[1]); - - DEBUGF("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n", size_b0, size_b1); - - if (size_b1 > size_b0) { - printf ("## ERROR: " - "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1<<20, - size_b0, size_b0<<20 - ); - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - return (0); - } - - DEBUGF ("## Before remap: " - "BR0: 0x%08x OR0: 0x%08x " - "BR6: 0x%08x OR6: 0x%08x\n", - memctl->memc_br0, memctl->memc_or0, - memctl->memc_br6, memctl->memc_or6); - - /* Remap FLASH according to real size */ - base = 0 - size_b0; - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (base & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V; - - DEBUGF("## BR0: 0x%08x OR0: 0x%08x\n", - memctl->memc_br0, memctl->memc_or0); - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)base, &flash_info[0]); - base = 0 - size_b0; - - flash_info[0].size = size_b0; - - flash_get_offsets (base, &flash_info[0]); - - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - PCU_MONITOR_BASE, - PCU_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif - - if (size_b1) { - flash_info_t tmp_info; - - memctl->memc_or6 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); - memctl->memc_br6 = ((base - size_b1) & BR_BA_MSK) | - BR_PS_16 | BR_MS_GPCM | BR_V; - - DEBUGF("## New BR6: 0x%08x OR6: 0x%08x\n", - memctl->memc_br6, memctl->memc_or6); - - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(base - size_b1), - &flash_info[1]); - base -= size_b1; - - flash_get_offsets (base, &flash_info[1]); - - flash_info[1].size = size_b1; - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, - &flash_info[1]); -#endif - /* - * Swap bank numbers so that addresses are in ascending order - */ - tmp_info = flash_info[0]; - flash_info[0] = flash_info[1]; - flash_info[1] = tmp_info; - } else { - memctl->memc_br1 = 0; /* invalidate bank */ - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - - DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1); - - return (size_b0 + size_b1); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - short n; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD) { - return; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AMDL322T: - case FLASH_AMDL323T: - case FLASH_AMDL324T: - /* set sector offsets for top boot block type */ - - base += info->size; - i = info->sector_count; - for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */ - base -= 8 << 10; - --i; - info->start[i] = base; - } - while (i > 0) { /* 64k regular sectors */ - base -= 64 << 10; - --i; - info->start[i] = base; - } - return; - case FLASH_AMDL322B: - case FLASH_AMDL323B: - case FLASH_AMDL324B: - /* set sector offsets for bottom boot block type */ - for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */ - info->start[i] = base; - base += 8 << 10; - } - while (base < info->size) { /* 64k regular sectors */ - info->start[i] = base; - base += 64 << 10; - ++i; - } - return; - case FLASH_AMDL640: - /* set sector offsets for dual boot block type */ - for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */ - info->start[i] = base; - base += 8 << 10; - } - n = info->sector_count - 8; - while (i < n) { /* 64k regular sectors */ - info->start[i] = base; - base += 64 << 10; - ++i; - } - while (i < info->sector_count) { /* 8 x 8k boot sectors */ - info->start[i] = base; - base += 8 << 10; - ++i; - } - return; - default: - return; - } - /* NOTREACHED */ -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AMDL322B: printf ("AM29DL322B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AMDL322T: printf ("AM29DL322T (32 Mbit, top boot sector)\n"); - break; - case FLASH_AMDL323B: printf ("AM29DL323B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AMDL323T: printf ("AM29DL323T (32 Mbit, top boot sector)\n"); - break; - case FLASH_AMDL324B: printf ("AM29DL324B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AMDL324T: printf ("AM29DL324T (32 Mbit, top boot sector)\n"); - break; - case FLASH_AMDL640: printf ("AM29DL640D (64 Mbit, dual boot sector)\n"); - break; - default: printf ("Unknown Chip Type 0x%lX\n", - info->flash_id); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ushort value; - vu_short *saddr = (vu_short *)addr; - - /* Write auto select command: read Manufacturer ID */ - saddr[0x0555] = 0x00AA; - saddr[0x02AA] = 0x0055; - saddr[0x0555] = 0x0090; - - value = saddr[0]; - - DEBUGF("Manuf. ID @ 0x%08lx: 0x%04x\n", (ulong)addr, value); - - switch (value) { - case (AMD_MANUFACT & 0xFFFF): - info->flash_id = FLASH_MAN_AMD; - break; - case (FUJ_MANUFACT & 0xFFFF): - info->flash_id = FLASH_MAN_FUJ; - break; - default: - DEBUGF("Unknown Manufacturer ID\n"); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = saddr[1]; /* device ID */ - - DEBUGF("Device ID @ 0x%08lx: 0x%04x\n", (ulong)(&addr[1]), value); - - switch (value) { - - case (AMD_ID_DL322T & 0xFFFF): - info->flash_id += FLASH_AMDL322T; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 8 MB */ - - case (AMD_ID_DL322B & 0xFFFF): - info->flash_id += FLASH_AMDL322B; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 8 MB */ - - case (AMD_ID_DL323T & 0xFFFF): - info->flash_id += FLASH_AMDL323T; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 8 MB */ - - case (AMD_ID_DL323B & 0xFFFF): - info->flash_id += FLASH_AMDL323B; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 8 MB */ - - case (AMD_ID_DL324T & 0xFFFF): - info->flash_id += FLASH_AMDL324T; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 8 MB */ - - case (AMD_ID_DL324B & 0xFFFF): - info->flash_id += FLASH_AMDL324B; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 8 MB */ - case (AMD_ID_DL640 & 0xFFFF): - info->flash_id += FLASH_AMDL640; - info->sector_count = 142; - info->size = 0x00800000; - break; - default: - DEBUGF("Unknown Device ID\n"); - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - flash_get_offsets ((ulong)addr, info); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { -#if 0 - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - saddr = (vu_short *)(info->start[i]); - info->protect[i] = saddr[2] & 1; -#else - info->protect[i] =0; -#endif - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - saddr = (vu_short *)info->start[0]; - *saddr = 0x00F0; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_short *addr = (vu_short*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - addr[0x0555] = 0x0080; - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_short*)(info->start[sect]); - addr[0] = 0x0030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_short*)(info->start[l_sect]); - while ((addr[0] & 0x0080) != 0x0080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_short *)info->start[0]; - addr[0] = 0x00F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -#define FLASH_WIDTH 2 /* flash bus width in bytes */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~(FLASH_WIDTH-1)); /* get lower FLASH_WIDTH aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<FLASH_WIDTH && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<FLASH_WIDTH; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_data(info, wp, data)) != 0) { - return (rc); - } - wp += FLASH_WIDTH; - } - - /* - * handle FLASH_WIDTH aligned part - */ - while (cnt >= FLASH_WIDTH) { - data = 0; - for (i=0; i<FLASH_WIDTH; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data(info, wp, data)) != 0) { - return (rc); - } - wp += FLASH_WIDTH; - cnt -= FLASH_WIDTH; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<FLASH_WIDTH && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<FLASH_WIDTH; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_data(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, ulong dest, ulong data) -{ - vu_short *addr = (vu_short*)(info->start[0]); - vu_short *sdest = (vu_short *)dest; - ushort sdata = (ushort)data; - ushort sval; - ulong start, passed; - int flag, rc; - - /* Check if Flash is (sufficiently) erased */ - if ((*sdest & sdata) != sdata) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - addr[0x0555] = 0x00A0; - -#ifdef WORKAROUND_FOR_BROKEN_HARDWARE - /* work around the timeout bugs */ - udelay(20); -#endif - - *sdest = sdata; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - rc = 0; - /* data polling for D7 */ - start = get_timer (0); - - for (passed=0; passed < CONFIG_SYS_FLASH_WRITE_TOUT; passed=get_timer(start)) { - - sval = *sdest; - - if ((sval & 0x0080) == (sdata & 0x0080)) - break; - - if ((sval & 0x0020) == 0) /* DQ5: Timeout? */ - continue; - - sval = *sdest; - - if ((sval & 0x0080) != (sdata & 0x0080)) - rc = 1; - - break; - } - - if (rc) { - DEBUGF ("Program cycle failed @ addr 0x%08lX: val %04X data %04X\n", - dest, sval, sdata); - } - - if (passed >= CONFIG_SYS_FLASH_WRITE_TOUT) { - DEBUGF ("Timeout @ addr 0x%08lX: val %04X data %04X\n", - dest, sval, sdata); - rc = 1; - } - - /* reset to read mode */ - addr = (vu_short *)info->start[0]; - addr[0] = 0x00F0; /* reset bank */ - - return (rc); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/siemens/pcu_e/pcu_e.c b/board/siemens/pcu_e/pcu_e.c deleted file mode 100644 index 97952844f9..0000000000 --- a/board/siemens/pcu_e/pcu_e.c +++ /dev/null @@ -1,562 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <mpc8xx.h> -#include <commproc.h> -#include <i2c.h> -#include <command.h> - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); -static void puma_status (void); -static void puma_set_mode (int mode); -static int puma_init_done (void); -static void puma_load (ulong addr, ulong len); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -/* - * 50 MHz SDRAM access using UPM A - */ -const uint sdram_table[] = { - /* - * Single Read. (Offset 0 in UPM RAM) - */ - 0x1f0dfc04, 0xeeafbc04, 0x11af7c04, 0xefbeec00, - 0x1ffddc47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPM RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1ffddc35, 0xefceac34, 0x1f3d5c35, /* last */ - /* - * Burst Read. (Offset 8 in UPM RAM) - */ - 0x1f0dfc04, 0xeeafbc04, 0x10af7c04, 0xf0affc00, - 0xf0affc00, 0xf1affc00, 0xefbeec00, 0x1ffddc47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Single Write. (Offset 18 in UPM RAM) - */ - 0x1f0dfc04, 0xeeafac00, 0x01be4c04, 0x1ffddc47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPM RAM) - */ - 0x1f0dfc04, 0xeeafac00, 0x10af5c00, 0xf0affc00, - 0xf0affc00, 0xe1beec04, 0x1ffddc47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPM RAM) - */ - 0x1ffd7c84, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc84, 0xfffffc07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPM RAM) - */ - 0x7ffffc07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - -/* - * PUMA access using UPM B - */ -const uint puma_table[] = { - /* - * Single Read. (Offset 0 in UPM RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, - /* - * Precharge and MRS - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Read. (Offset 8 in UPM RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPM RAM) - */ - 0x0ffff804, 0x0ffff400, 0x3ffffc47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPM RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPM RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPM RAM) - */ - 0x7ffffc07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - */ - -int checkboard (void) -{ - puts ("Board: Siemens PCU E\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - long int size_b0, reg; - int i; - - /* - * Configure UPMA for SDRAM - */ - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - /* burst length=4, burst type=sequential, CAS latency=2 */ - memctl->memc_mar = 0x00000088; - - /* - * Map controller bank 2 to the SDRAM bank at preliminary address. - */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM; - memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM; -#else /* XXX */ - memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; - memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; -#endif /* XXX */ - - /* initialize memory address register */ - memctl->memc_mamr = CONFIG_SYS_MAMR; /* refresh not enabled yet */ - - /* mode initialization (offset 5) */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - udelay (200); /* 0x8000A105 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x05); -#else /* XXX */ - udelay (200); /* 0x80004105 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x05); -#endif /* XXX */ - - /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - udelay (1); /* 0x8000A830 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (8) | MCR_MAD (0x30); -#else /* XXX */ - udelay (1); /* 0x80004830 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (8) | MCR_MAD (0x30); -#endif /* XXX */ - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - udelay (1); /* 0x8000A106 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x06); -#else /* XXX */ - udelay (1); /* 0x80004106 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x06); -#endif /* XXX */ - - reg = memctl->memc_mamr; - reg &= ~MAMR_TLFA_MSK; /* switch timer loop ... */ - reg |= MAMR_TLFA_4X; /* ... to 4x */ - reg |= MAMR_PTAE; /* enable refresh */ - memctl->memc_mamr = reg; - - udelay (200); - - /* Need at least 10 DRAM accesses to stabilize */ - for (i = 0; i < 10; ++i) { -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - volatile unsigned long *addr = - (volatile unsigned long *) SDRAM_BASE5_PRELIM; -#else /* XXX */ - volatile unsigned long *addr = - (volatile unsigned long *) SDRAM_BASE2_PRELIM; -#endif /* XXX */ - unsigned long val; - - val = *(addr + i); - *(addr + i) = val; - } - - /* - * Check Bank 0 Memory Size for re-configuration - */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - size_b0 = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE); -#else /* XXX */ - size_b0 = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); -#endif /* XXX */ - - memctl->memc_mamr = CONFIG_SYS_MAMR | MAMR_PTAE; - - /* - * Final mapping: - */ - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - memctl->memc_or5 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING; - memctl->memc_br5 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; -#else /* XXX */ - memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING; - memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; -#endif /* XXX */ - udelay (1000); - - /* - * Configure UPMB for PUMA - */ - upmconfig (UPMB, (uint *) puma_table, - sizeof (puma_table) / sizeof (uint)); - - return (size_b0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size (base, maxsize)); -} - -/* ------------------------------------------------------------------------- */ - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define ETH_CFG_BITS (CONFIG_SYS_PB_ETH_CFG1 | CONFIG_SYS_PB_ETH_CFG2 | CONFIG_SYS_PB_ETH_CFG3 ) -#else /* XXX */ -#define ETH_CFG_BITS (CONFIG_SYS_PB_ETH_MDDIS | CONFIG_SYS_PB_ETH_CFG1 | \ - CONFIG_SYS_PB_ETH_CFG2 | CONFIG_SYS_PB_ETH_CFG3 ) -#endif /* XXX */ - -#define ETH_ALL_BITS (ETH_CFG_BITS | CONFIG_SYS_PB_ETH_POWERDOWN | CONFIG_SYS_PB_ETH_RESET) - -void reset_phy (void) -{ - immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - ulong value; - - /* Configure all needed port pins for GPIO */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -# ifdef CONFIG_SYS_ETH_MDDIS_VALUE - immr->im_ioport.iop_padat |= CONFIG_SYS_PA_ETH_MDDIS; -# else - immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_ETH_MDDIS); /* Set low */ -# endif - immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_ETH_MDDIS); /* GPIO */ - immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_ETH_MDDIS); /* active output */ - immr->im_ioport.iop_padir |= CONFIG_SYS_PA_ETH_MDDIS; /* output */ -#endif /* XXX */ - immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */ - immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */ - - value = immr->im_cpm.cp_pbdat; - - /* Assert Powerdown and Reset signals */ - value |= CONFIG_SYS_PB_ETH_POWERDOWN; - value &= ~(CONFIG_SYS_PB_ETH_RESET); - - /* PHY configuration includes MDDIS and CFG1 ... CFG3 */ -#if !PCU_E_WITH_SWAPPED_CS -# ifdef CONFIG_SYS_ETH_MDDIS_VALUE - value |= CONFIG_SYS_PB_ETH_MDDIS; -# else - value &= ~(CONFIG_SYS_PB_ETH_MDDIS); -# endif -#endif -#ifdef CONFIG_SYS_ETH_CFG1_VALUE - value |= CONFIG_SYS_PB_ETH_CFG1; -#else - value &= ~(CONFIG_SYS_PB_ETH_CFG1); -#endif -#ifdef CONFIG_SYS_ETH_CFG2_VALUE - value |= CONFIG_SYS_PB_ETH_CFG2; -#else - value &= ~(CONFIG_SYS_PB_ETH_CFG2); -#endif -#ifdef CONFIG_SYS_ETH_CFG3_VALUE - value |= CONFIG_SYS_PB_ETH_CFG3; -#else - value &= ~(CONFIG_SYS_PB_ETH_CFG3); -#endif - - /* Drive output signals to initial state */ - immr->im_cpm.cp_pbdat = value; - immr->im_cpm.cp_pbdir |= ETH_ALL_BITS; - udelay (10000); - - /* De-assert Ethernet Powerdown */ - immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* Enable PHY power */ - udelay (10000); - - /* de-assert RESET signal of PHY */ - immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_ETH_RESET; - udelay (1000); -} - -/*----------------------------------------------------------------------- - * Board Special Commands: access functions for "PUMA" FPGA - */ -#if defined(CONFIG_CMD_BSP) - -#define PUMA_READ_MODE 0 -#define PUMA_LOAD_MODE 1 - -int do_puma (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - ulong addr, len; - - switch (argc) { - case 2: /* PUMA reset */ - if (strncmp (argv[1], "stat", 4) == 0) { /* Reset */ - puma_status (); - return 0; - } - break; - case 4: /* PUMA load addr len */ - if (strcmp (argv[1], "load") != 0) - break; - - addr = simple_strtoul (argv[2], NULL, 16); - len = simple_strtoul (argv[3], NULL, 16); - - printf ("PUMA load: addr %08lX len %ld (0x%lX): ", - addr, len, len); - puma_load (addr, len); - - return 0; - default: - break; - } - return cmd_usage(cmdtp); -} - -U_BOOT_CMD (puma, 4, 1, do_puma, - "access PUMA FPGA", - "status - print PUMA status\n" - "puma load addr len - load PUMA configuration data" -); -#endif - -/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ - -static void puma_set_mode (int mode) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - - /* disable PUMA in memory controller */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - memctl->memc_br3 = 0; -#else /* XXX */ - memctl->memc_br4 = 0; -#endif /* XXX */ - - switch (mode) { - case PUMA_READ_MODE: -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - memctl->memc_or3 = PUMA_CONF_OR_READ; - memctl->memc_br3 = PUMA_CONF_BR_READ; -#else /* XXX */ - memctl->memc_or4 = PUMA_CONF_OR_READ; - memctl->memc_br4 = PUMA_CONF_BR_READ; -#endif /* XXX */ - break; - case PUMA_LOAD_MODE: -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - memctl->memc_or3 = PUMA_CONF_OR_LOAD; - memctl->memc_br3 = PUMA_CONF_BR_LOAD; -#else /* XXX */ - memctl->memc_or4 = PUMA_CONF_OR_READ; - memctl->memc_br4 = PUMA_CONF_BR_READ; -#endif /* XXX */ - break; - } -} - -/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ - -#define PUMA_INIT_TIMEOUT 1000 /* max. 1000 ms = 1 second */ - -static void puma_load (ulong addr, ulong len) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile uchar *fpga_addr = (volatile uchar *) PUMA_CONF_BASE; /* XXX ??? */ - uchar *data = (uchar *) addr; - int i; - - /* align length */ - if (len & 1) - ++len; - - /* Reset FPGA */ - immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_PUMA_INIT); /* make input */ - immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_PUMA_INIT); - immr->im_ioport.iop_pcdir &= ~(CONFIG_SYS_PC_PUMA_INIT); - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_PUMA_PROG); /* GPIO */ - immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_PUMA_PROG); /* active output */ - immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_PUMA_PROG); /* Set low */ - immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_PUMA_PROG; /* output */ -#else - immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_PUMA_PROG); /* GPIO */ - immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_PUMA_PROG); /* Set low */ - immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_PUMA_PROG); /* active output */ - immr->im_ioport.iop_padir |= CONFIG_SYS_PA_PUMA_PROG; /* output */ -#endif /* XXX */ - udelay (100); - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_PUMA_PROG; /* release reset */ -#else - immr->im_ioport.iop_padat |= CONFIG_SYS_PA_PUMA_PROG; /* release reset */ -#endif /* XXX */ - - /* wait until INIT indicates completion of reset */ - for (i = 0; i < PUMA_INIT_TIMEOUT; ++i) { - udelay (1000); - if (immr->im_ioport.iop_pcdat & CONFIG_SYS_PC_PUMA_INIT) - break; - } - if (i == PUMA_INIT_TIMEOUT) { - printf ("*** PUMA init timeout ***\n"); - return; - } - - puma_set_mode (PUMA_LOAD_MODE); - - while (len--) - *fpga_addr = *data++; - - puma_set_mode (PUMA_READ_MODE); - - puma_status (); -} - -/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ - -static void puma_status (void) -{ - /* Check state */ - printf ("PUMA initialization is %scomplete\n", - puma_init_done ()? "" : "NOT "); -} - -/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ - -static int puma_init_done (void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - /* make sure pin is GPIO input */ - immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_PUMA_DONE); - immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_PUMA_DONE); - immr->im_ioport.iop_pcdir &= ~(CONFIG_SYS_PC_PUMA_DONE); - - return (immr->im_ioport.iop_pcdat & CONFIG_SYS_PC_PUMA_DONE) ? 1 : 0; -} - -/* ------------------------------------------------------------------------- */ - -int misc_init_r (void) -{ - ulong addr = 0; - ulong len = 0; - char *s; - - printf ("PUMA: "); - if (puma_init_done ()) { - printf ("initialized\n"); - return 0; - } - - if ((s = getenv ("puma_addr")) != NULL) - addr = simple_strtoul (s, NULL, 16); - - if ((s = getenv ("puma_len")) != NULL) - len = simple_strtoul (s, NULL, 16); - - if ((!addr) || (!len)) { - printf ("net list undefined\n"); - return 0; - } - - printf ("loading... "); - - puma_load (addr, len); - return (0); -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/siemens/pcu_e/u-boot.lds b/board/siemens/pcu_e/u-boot.lds deleted file mode 100644 index b871958f1b..0000000000 --- a/board/siemens/pcu_e/u-boot.lds +++ /dev/null @@ -1,127 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/env_embedded.o(.text) - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(4); - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/siemens/pcu_e/u-boot.lds.debug b/board/siemens/pcu_e/u-boot.lds.debug deleted file mode 100644 index 131ad23c77..0000000000 --- a/board/siemens/pcu_e/u-boot.lds.debug +++ /dev/null @@ -1,136 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - arch/powerpc/lib/extable.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/tcm-bf518/config.mk b/board/tcm-bf518/config.mk index 3f9d41f371..30b92a3c43 100644 --- a/board/tcm-bf518/config.mk +++ b/board/tcm-bf518/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf518-0.0 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/tcm-bf537/config.mk b/board/tcm-bf537/config.mk index bc046f129f..1281da4bef 100644 --- a/board/tcm-bf537/config.mk +++ b/board/tcm-bf537/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf537-0.2 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/tcm-bf537/gpio_cfi_flash.c b/board/tcm-bf537/gpio_cfi_flash.c index 08ea7af1fe..c4fef9f5e7 100644 --- a/board/tcm-bf537/gpio_cfi_flash.c +++ b/board/tcm-bf537/gpio_cfi_flash.c @@ -1,60 +1,3 @@ -/* - * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support - * - * Copyright (c) 2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <common.h> -#include <asm/blackfin.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include "gpio_cfi_flash.h" - -#define GPIO_PIN_1 GPIO_PF4 -#define GPIO_MASK_1 (1 << 21) -#define GPIO_PIN_2 GPIO_PF5 -#define GPIO_MASK_2 (1 << 22) -#define GPIO_MASK (GPIO_MASK_1 | GPIO_MASK_2) - -void *gpio_cfi_flash_swizzle(void *vaddr) -{ - unsigned long addr = (unsigned long)vaddr; - - gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1); - -#ifdef GPIO_MASK_2 - gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2); -#endif - - SSYNC(); - - return (void *)(addr & ~GPIO_MASK); -} - -#define __raw_writeq(value, addr) *(volatile u64 *)addr = value -#define __raw_readq(addr) *(volatile u64 *)addr - -#define MAKE_FLASH(size, sfx) \ -void flash_write##size(u##size value, void *addr) \ -{ \ - __raw_write##sfx(value, gpio_cfi_flash_swizzle(addr)); \ -} \ -u##size flash_read##size(void *addr) \ -{ \ - return __raw_read##sfx(gpio_cfi_flash_swizzle(addr)); \ -} -MAKE_FLASH(8, b) /* flash_write8() flash_read8() */ -MAKE_FLASH(16, w) /* flash_write16() flash_read16() */ -MAKE_FLASH(32, l) /* flash_write32() flash_read32() */ -MAKE_FLASH(64, q) /* flash_write64() flash_read64() */ - -void gpio_cfi_flash_init(void) -{ - gpio_request(GPIO_PIN_1, "gpio_cfi_flash"); -#ifdef GPIO_MASK_2 - gpio_request(GPIO_PIN_2, "gpio_cfi_flash"); -#endif - gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE); -} +#define GPIO_PIN_1 GPIO_PF4 +#define GPIO_PIN_2 GPIO_PF5 +#include "../cm-bf537e/gpio_cfi_flash.c" diff --git a/board/tcm-bf537/gpio_cfi_flash.h b/board/tcm-bf537/gpio_cfi_flash.h deleted file mode 100644 index 5211e972ad..0000000000 --- a/board/tcm-bf537/gpio_cfi_flash.h +++ /dev/null @@ -1,10 +0,0 @@ -/* - * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support - * - * Copyright (c) 2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -void *gpio_cfi_flash_swizzle(void *vaddr); -void gpio_cfi_flash_init(void); diff --git a/board/tcm-bf537/tcm-bf537.c b/board/tcm-bf537/tcm-bf537.c index 60742dfea5..04d6bdbd3e 100644 --- a/board/tcm-bf537/tcm-bf537.c +++ b/board/tcm-bf537/tcm-bf537.c @@ -13,7 +13,7 @@ #include <netdev.h> #include <asm/blackfin.h> #include <asm/net.h> -#include "gpio_cfi_flash.h" +#include "../cm-bf537e/gpio_cfi_flash.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c index 838f1315b3..744384c1d3 100644 --- a/board/xilinx/microblaze-generic/microblaze-generic.c +++ b/board/xilinx/microblaze-generic/microblaze-generic.c @@ -27,6 +27,7 @@ #include <common.h> #include <config.h> +#include <netdev.h> #include <asm/microblaze_intc.h> #include <asm/asm.h> @@ -66,3 +67,15 @@ int fsl_init2 (void) { return 0; } #endif + +int board_eth_init(bd_t *bis) +{ + /* + * This board either has PCI NICs or uses the CPU's TSECs + * pci_eth_init() will return 0 if no NICs found, so in that case + * returning -1 will force cpu_eth_init() to be called. + */ +#ifdef CONFIG_XILINX_EMACLITE + return xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR); +#endif +} |