diff options
Diffstat (limited to 'board/sc520_cdp')
| -rw-r--r-- | board/sc520_cdp/Makefile | 4 | ||||
| -rw-r--r-- | board/sc520_cdp/flash.c | 251 | ||||
| -rw-r--r-- | board/sc520_cdp/flash_old.c | 126 | ||||
| -rw-r--r-- | board/sc520_cdp/sc520_cdp.c | 286 | ||||
| -rw-r--r-- | board/sc520_cdp/sc520_cdp_asm.S | 13 | ||||
| -rw-r--r-- | board/sc520_cdp/sc520_cdp_asm16.S | 47 | ||||
| -rw-r--r-- | board/sc520_cdp/u-boot.lds | 57 |
7 files changed, 389 insertions, 395 deletions
diff --git a/board/sc520_cdp/Makefile b/board/sc520_cdp/Makefile index 0f50393468..f9a36f9f42 100644 --- a/board/sc520_cdp/Makefile +++ b/board/sc520_cdp/Makefile @@ -25,11 +25,11 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS := sc520_cdp.o flash.o +OBJS := sc520_cdp.o flash.o SOBJS := sc520_cdp_asm.o sc520_cdp_asm16.o $(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $^ + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/sc520_cdp/flash.c b/board/sc520_cdp/flash.c index 1ebb32e2e9..a4d37e5087 100644 --- a/board/sc520_cdp/flash.c +++ b/board/sc520_cdp/flash.c @@ -1,7 +1,7 @@ /* * (C) Copyright 2002, 2003 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * + * * (C) Copyright 2002 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> * Alex Zuepke <azu@sysgo.de> @@ -55,122 +55,121 @@ flash_info_t flash_info[SC520_MAX_FLASH_BANKS]; static u32 _probe_flash(u32 addr, u32 bw, int il) { u32 result=0; - + /* First do an unlock cycle for the benefit of * devices that need it */ - + switch (bw) { - + case 1: *(volatile u8*)(addr+0x5555) = 0xaa; *(volatile u8*)(addr+0x2aaa) = 0x55; *(volatile u8*)(addr+0x5555) = 0x90; - + /* Read vendor */ result = *(volatile u8*)addr; result <<= 16; - + /* Read device */ result |= *(volatile u8*)(addr+2); - + /* Return device to data mode */ *(volatile u8*)addr = 0xff; - *(volatile u8*)(addr+0x5555), 0xf0; + *(volatile u8*)(addr+0x5555), 0xf0; break; - + case 2: *(volatile u16*)(addr+0xaaaa) = 0xaaaa; *(volatile u16*)(addr+0x5554) = 0x5555; - + /* Issue identification command */ if (il == 2) { *(volatile u16*)(addr+0xaaaa) = 0x9090; - + /* Read vendor */ result = *(volatile u8*)addr; result <<= 16; - + /* Read device */ result |= *(volatile u8*)(addr+2); - + /* Return device to data mode */ *(volatile u16*)addr = 0xffff; - *(volatile u16*)(addr+0xaaaa), 0xf0f0; - + *(volatile u16*)(addr+0xaaaa), 0xf0f0; + } else { *(volatile u8*)(addr+0xaaaa) = 0x90; /* Read vendor */ result = *(volatile u16*)addr; result <<= 16; - + /* Read device */ result |= *(volatile u16*)(addr+2); - + /* Return device to data mode */ *(volatile u8*)addr = 0xff; - *(volatile u8*)(addr+0xaaaa), 0xf0; + *(volatile u8*)(addr+0xaaaa), 0xf0; } - + break; - + case 4: *(volatile u32*)(addr+0x5554) = 0xaaaaaaaa; *(volatile u32*)(addr+0xaaa8) = 0x55555555; - + switch (il) { case 1: /* Issue identification command */ *(volatile u8*)(addr+0x5554) = 0x90; - + /* Read vendor */ result = *(volatile u16*)addr; result <<= 16; - + /* Read device */ result |= *(volatile u16*)(addr+4); - + /* Return device to data mode */ *(volatile u8*)addr = 0xff; - *(volatile u8*)(addr+0x5554), 0xf0; + *(volatile u8*)(addr+0x5554), 0xf0; break; - + case 2: /* Issue identification command */ *(volatile u32*)(addr + 0x5554) = 0x00900090; - + /* Read vendor */ result = *(volatile u16*)addr; result <<= 16; - + /* Read device */ result |= *(volatile u16*)(addr+4); - + /* Return device to data mode */ *(volatile u32*)addr = 0x00ff00ff; - *(volatile u32*)(addr+0x5554), 0x00f000f0; + *(volatile u32*)(addr+0x5554), 0x00f000f0; break; - + case 4: /* Issue identification command */ *(volatile u32*)(addr+0x5554) = 0x90909090; - + /* Read vendor */ result = *(volatile u8*)addr; result <<= 16; - + /* Read device */ result |= *(volatile u8*)(addr+4); - + /* Return device to data mode */ *(volatile u32*)addr = 0xffffffff; - *(volatile u32*)(addr+0x5554), 0xf0f0f0f0; + *(volatile u32*)(addr+0x5554), 0xf0f0f0f0; break; } break; } - - - + + return result; } @@ -180,36 +179,36 @@ asm ("_probe_flash_end:\n" static int identify_flash(unsigned address, int width) { - int is; + int is; int device; - int vendor; + int vendor; int size; unsigned res; - + u32 (*_probe_flash_ptr)(u32 a, u32 bw, int il); - - size = (unsigned)&_probe_flash_end - (unsigned)_probe_flash; - + + size = (unsigned)&_probe_flash_end - (unsigned)_probe_flash; + if (size > PROBE_BUFFER_SIZE) { printf("_probe_flash() routine too large (%d) %p - %p\n", size, &_probe_flash_end, _probe_flash); return 0; } - + memcpy(buffer, _probe_flash, size); _probe_flash_ptr = (void*)buffer; - + is = disable_interrupts(); res = _probe_flash_ptr(address, width, 1); if (is) { enable_interrupts(); } - - - vendor = res >> 16; + + + vendor = res >> 16; device = res & 0xffff; - - + + return res; } @@ -217,12 +216,12 @@ ulong flash_init(void) { int i, j; ulong size = 0; - + for (i = 0; i < SC520_MAX_FLASH_BANKS; i++) { unsigned id; ulong flashbase = 0; - int sectsize = 0; - + int sectsize = 0; + memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); switch (i) { case 0: @@ -237,7 +236,7 @@ ulong flash_init(void) default: panic("configured to many flash banks!\n"); } - + id = identify_flash(flashbase, 4); switch (id & 0x00ff00ff) { case 0x000100c8: @@ -245,31 +244,31 @@ ulong flash_init(void) flash_info[i].flash_id = (AMD_MANUFACT & FLASH_VENDMASK) | (AMD_ID_LV016B & FLASH_TYPEMASK); - + flash_info[i].size = AMD29LV016B_SIZE*4; flash_info[i].sector_count = AMD29LV016B_SECTORS; sectsize = (AMD29LV016B_SIZE*4)/AMD29LV016B_SECTORS; printf("Bank %d: 4 x AMD 29LV017B\n", i); break; - - + + default: printf("Bank %d have unknown flash %08x\n", i, id); flash_info[i].flash_id = FLASH_UNKNOWN; continue; } - + for (j = 0; j < flash_info[i].sector_count; j++) { flash_info[i].start[j] = flashbase + j * sectsize; } size += flash_info[i].size; - + flash_protect(FLAG_PROTECT_CLEAR, flash_info[i].start[0], flash_info[i].start[0] + flash_info[i].size - 1, &flash_info[i]); } - + /* * Protect monitor and environment sectors */ @@ -282,7 +281,7 @@ ulong flash_init(void) CFG_ENV_ADDR, CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); -#endif +#endif return size; } @@ -291,9 +290,9 @@ ulong flash_init(void) void flash_print_info(flash_info_t *info) { int i; - + switch (info->flash_id & FLASH_VENDMASK) { - + case (AMD_MANUFACT & FLASH_VENDMASK): printf("AMD: "); switch (info->flash_id & FLASH_TYPEMASK) { @@ -305,17 +304,17 @@ void flash_print_info(flash_info_t *info) goto done; break; } - + break; default: printf("Unknown Vendor "); break; } - - + + printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); - + printf(" Sector Start Addresses:"); for (i = 0; i < info->sector_count; i++) { if ((i % 5) == 0) { @@ -325,7 +324,7 @@ void flash_print_info(flash_info_t *info) info->protect[i] ? " (RO)" : " "); } printf ("\n"); - + done: } @@ -339,7 +338,7 @@ void flash_print_info(flash_info_t *info) unsigned milli=0; \ \ micro = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \ - \ + \ for (;;) { \ \ milli += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \ @@ -349,12 +348,12 @@ void flash_print_info(flash_info_t *info) break; \ } \ } \ -} while (0) +} while (0) static u32 _amd_erase_flash(u32 addr, u32 sector) { unsigned elapsed; - + /* Issue erase */ *(volatile u32*)(addr + 0x5554) = 0xAAAAAAAA; *(volatile u32*)(addr + 0xaaa8) = 0x55555555; @@ -364,21 +363,21 @@ static u32 _amd_erase_flash(u32 addr, u32 sector) *(volatile u32*)(addr + 0xaaa8) = 0x55555555; /* Sector erase command comes last */ *(volatile u32*)(addr + sector) = 0x30303030; - + elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */ elapsed = 0; __udelay(50); while (((*(volatile u32*)(addr + sector)) & 0x80808080) != 0x80808080) { - + elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); if (elapsed > ((CFG_FLASH_ERASE_TOUT/CFG_HZ) * 1000)) { *(volatile u32*)(addr) = 0xf0f0f0f0; - return 1; + return 1; } } - + *(volatile u32*)(addr) = 0xf0f0f0f0; - + return 0; } @@ -392,7 +391,7 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) int prot; int sect; unsigned size; - + if ((s_first < 0) || (s_first > s_last)) { if (info->flash_id == FLASH_UNKNOWN) { printf("- missing\n"); @@ -401,66 +400,66 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) } return 1; } - + if ((info->flash_id & FLASH_VENDMASK) == (AMD_MANUFACT & FLASH_VENDMASK)) { - size = (unsigned)&_amd_erase_flash_end - (unsigned)_amd_erase_flash; - + size = (unsigned)&_amd_erase_flash_end - (unsigned)_amd_erase_flash; + if (size > PROBE_BUFFER_SIZE) { printf("_amd_erase_flash() routine too large (%d) %p - %p\n", size, &_amd_erase_flash_end, _amd_erase_flash); return 0; } - + memcpy(buffer, _amd_erase_flash, size); _erase_flash_ptr = (void*)buffer; - + } else { printf ("Can't erase unknown flash type - aborted\n"); return 1; } - + prot = 0; for (sect=s_first; sect<=s_last; ++sect) { if (info->protect[sect]) { prot++; } } - + if (prot) { printf ("- Warning: %d protected sectors will not be erased!\n", prot); } else { printf ("\n"); } - - + + /* Start erase on unprotected sectors */ for (sect = s_first; sect<=s_last; sect++) { - + if (info->protect[sect] == 0) { /* not protected */ int res; int flag; - + /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); - + res = _erase_flash_ptr(info->start[0], info->start[sect]-info->start[0]); - + /* re-enable interrupts if necessary */ if (flag) { enable_interrupts(); } - - + + if (res) { printf("Erase timed out, sector %d\n", sect); return res; } - - putc('.'); - } + + putc('.'); + } } - + return 0; } @@ -476,33 +475,33 @@ static int _amd_write_word(unsigned start, unsigned dest, unsigned data) volatile u32 *dest2 = (u32*)dest; volatile u32 *data2 = (u32*)&data; unsigned elapsed; - + /* Check if Flash is (sufficiently) erased */ if ((*((volatile u32*)dest) & (u32)data) != (u32)data) { return 2; } - + addr2[0x5554] = 0xAAAAAAAA; addr2[0xaaa8] = 0x55555555; addr2[0x5554] = 0xA0A0A0A0; - + dest2[0] = data; - + elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */ elapsed = 0; - + /* data polling for D7 */ while ((dest2[0] & 0x80808080) != (data2[0] & 0x80808080)) { elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); if (elapsed > ((CFG_FLASH_WRITE_TOUT/CFG_HZ) * 1000)) { addr2[0] = 0xf0f0f0f0; - return 1; + return 1; } } - + addr2[0] = 0xf0f0f0f0; - + return 0; } @@ -511,8 +510,6 @@ asm ("_amd_write_word_end:\n" ".long 0\n"); - - /*----------------------------------------------------------------------- * Copy memory to flash, returns: * 0 - OK @@ -528,19 +525,19 @@ int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) int flag; u32 (*_write_word_ptr)(unsigned start, unsigned dest, unsigned data); unsigned size; - + if ((info->flash_id & FLASH_VENDMASK) == (AMD_MANUFACT & FLASH_VENDMASK)) { - size = (unsigned)&_amd_write_word_end - (unsigned)_amd_write_word; - + size = (unsigned)&_amd_write_word_end - (unsigned)_amd_write_word; + if (size > PROBE_BUFFER_SIZE) { printf("_amd_write_word() routine too large (%d) %p - %p\n", size, &_amd_write_word_end, _amd_write_word); return 0; } - + memcpy(buffer, _amd_write_word, size); _write_word_ptr = (void*)buffer; - + } else { printf ("Can't program unknown flash type - aborted\n"); return 3; @@ -548,7 +545,7 @@ int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) wp = (addr & ~3); /* get lower word aligned address */ - + /* * handle unaligned start bytes @@ -566,12 +563,12 @@ int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) for (; cnt==0 && i<4; ++i, ++cp) { data |= (*(uchar *)cp) << (8*i); } - + /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); - + rc = _write_word_ptr(info->start[0], wp, data); - + /* re-enable interrupts if necessary */ if (flag) { enable_interrupts(); @@ -581,22 +578,22 @@ int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) } wp += 4; } - + /* * handle word aligned part */ while (cnt >= 4) { data = 0; - + for (i=0; i<4; ++i) { data |= *src++ << (8*i); } - + /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); rc = _write_word_ptr(info->start[0], wp, data); - + /* re-enable interrupts if necessary */ if (flag) { enable_interrupts(); @@ -607,11 +604,11 @@ int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) wp += 4; cnt -= 4; } - + if (cnt == 0) { return 0; } - + /* * handle unaligned tail bytes */ @@ -620,7 +617,7 @@ int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) data |= *src++ << (8*i); --cnt; } - + for (; i<4; ++i, ++cp) { data |= (*(uchar *)cp) << (8*i); } @@ -629,14 +626,12 @@ int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) flag = disable_interrupts(); rc = _write_word_ptr(info->start[0], wp, data); - + /* re-enable interrupts if necessary */ if (flag) { enable_interrupts(); } - - return rc; - -} + return rc; +} diff --git a/board/sc520_cdp/flash_old.c b/board/sc520_cdp/flash_old.c index d4204a8ced..416b01d2a5 100644 --- a/board/sc520_cdp/flash_old.c +++ b/board/sc520_cdp/flash_old.c @@ -1,7 +1,7 @@ /* * (C) Copyright 2002 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * + * * (C) Copyright 2002 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> * Alex Zuepke <azu@sysgo.de> @@ -67,22 +67,22 @@ ulong flash_init(void) { int i, j; ulong size = 0; - + for (i = 0; i < SC520_MAX_FLASH_BANKS; i++) { ulong flashbase = 0; - int sectsize = 0; + int sectsize = 0; if (i==0 || i==2) { - /* FixMe: this assumes that bank 0 and 2 + /* FixMe: this assumes that bank 0 and 2 * are mapped to the two 8Mb banks */ flash_info[i].flash_id = (AMD_MANUFACT & FLASH_VENDMASK) | (AMD_ID_LV016B & FLASH_TYPEMASK); - + flash_info[i].size = AMD29LV016_SIZE*4; flash_info[i].sector_count = AMD29LV016_SECTORS; sectsize = (AMD29LV016_SIZE*4)/AMD29LV016_SECTORS; } else { - /* FixMe: this assumes that bank1 is unmapped + /* FixMe: this assumes that bank1 is unmapped * (or mapped to the same flash bank as BOOTCS) */ flash_info[i].flash_id = 0; flash_info[i].size = 0; @@ -103,14 +103,14 @@ ulong flash_init(void) default: panic("configured to many flash banks!\n"); } - + for (j = 0; j < flash_info[i].sector_count; j++) { flash_info[i].start[j] = sectsize; flash_info[i].start[j] = flashbase + j * sectsize; } size += flash_info[i].size; } - + /* * Protect monitor and environment sectors */ @@ -118,7 +118,7 @@ ulong flash_init(void) i386boot_start-SC520_FLASH_BANK0_BASE, i386boot_end-SC520_FLASH_BANK0_BASE, &flash_info[0]); - + #ifdef CFG_ENV_ADDR flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, @@ -142,7 +142,7 @@ void flash_print_info(flash_info_t *info) printf("Unknown Vendor "); break; } - + switch (info->flash_id & FLASH_TYPEMASK) { case (AMD_ID_LV016B & FLASH_TYPEMASK): printf("4x Amd29LV016B (16Mbit)\n"); @@ -152,10 +152,10 @@ void flash_print_info(flash_info_t *info) goto done; break; } - + printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); - + printf(" Sector Start Addresses:"); for (i = 0; i < info->sector_count; i++) { if ((i % 5) == 0) { @@ -165,7 +165,7 @@ void flash_print_info(flash_info_t *info) info->protect[i] ? " (RO)" : " "); } printf ("\n"); - + done: } @@ -180,20 +180,20 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) int chip1, chip2; /* first look for protection bits */ - + if (info->flash_id == FLASH_UNKNOWN) { return ERR_UNKNOWN_FLASH_TYPE; } - + if ((s_first < 0) || (s_first > s_last)) { return ERR_INVAL; } - + if ((info->flash_id & FLASH_VENDMASK) != (AMD_MANUFACT & FLASH_VENDMASK)) { return ERR_UNKNOWN_FLASH_VENDOR; } - + prot = 0; for (sect=s_first; sect<=s_last; ++sect) { if (info->protect[sect]) { @@ -203,7 +203,7 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) if (prot) { return ERR_PROTECTED; } - + /* * Disable interrupts which might cause a timeout * here. Remember that our exception vectors are @@ -212,77 +212,77 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) * chip is in programming mode. */ iflag = disable_interrupts(); - + /* Start erase on unprotected sectors */ for (sect = s_first; sect<=s_last && !ctrlc(); sect++) { printf("Erasing sector %2d ... ", sect); - + /* arm simple, non interrupt dependent timer */ reset_timer(); - - if (info->protect[sect] == 0) { + + if (info->protect[sect] == 0) { /* not protected */ ulong addr = info->start[sect]; - + writel(CMD_UNLOCK1, addr + 1); writel(CMD_UNLOCK2, addr + 2); writel(CMD_ERASE_SETUP, addr + 1); - + writel(CMD_UNLOCK1, addr + 1); writel(CMD_UNLOCK2, addr + 2); writel(CMD_ERASE_CONFIRM, addr); - + /* wait until flash is ready */ chip1 = chip2 = 0; - + do { result = readl(addr); - + /* check timeout */ if (get_timer(0) > CFG_FLASH_ERASE_TOUT) { writel(CMD_READ_ARRAY, addr + 1); chip1 = TMO; break; } - + if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE) { chip1 = READY; } - + if (!chip1 && (result & 0xFFFF) & BIT_PROGRAM_ERROR) { chip1 = ERR; } - + if (!chip2 && (result >> 16) & BIT_ERASE_DONE) { chip2 = READY; } - + if (!chip2 && (result >> 16) & BIT_PROGRAM_ERROR) { chip2 = ERR; } - + } while (!chip1 || !chip2); - + writel(CMD_READ_ARRAY, addr + 1); - + if (chip1 == ERR || chip2 == ERR) { rc = ERR_PROG_ERROR; goto outahere; } - + if (chip1 == TMO) { rc = ERR_TIMOUT; goto outahere; } - + printf("ok.\n"); } else { /* it was protected */ - + printf("protected!\n"); } } - + if (ctrlc()) { printf("User Interrupt!\n"); } @@ -290,11 +290,11 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) outahere: /* allow flash to settle - wait 10 ms */ udelay(10000); - + if (iflag) { enable_interrupts(); } - + return rc; } @@ -309,7 +309,7 @@ volatile static int write_word(flash_info_t *info, ulong dest, ulong data) int rc = ERR_OK; int iflag; int chip1, chip2; - + /* * Check if Flash is (sufficiently) erased */ @@ -317,7 +317,7 @@ volatile static int write_word(flash_info_t *info, ulong dest, ulong data) if ((result & data) != data) { return ERR_NOT_ERASED; } - + /* * Disable interrupts which might cause a timeout * here. Remember that our exception vectors are @@ -332,61 +332,61 @@ volatile static int write_word(flash_info_t *info, ulong dest, ulong data) writel(CMD_UNLOCK_BYPASS, addr + 1); writel(addr, CMD_PROGRAM); writel(addr, data); - + /* arm simple, non interrupt dependent timer */ reset_timer(); - + /* wait until flash is ready */ chip1 = chip2 = 0; do { result = readl(addr); - + /* check timeout */ if (get_timer(0) > CFG_FLASH_ERASE_TOUT) { chip1 = ERR | TMO; break; } - + if (!chip1 && ((result & 0x80) == (data & 0x80))) { chip1 = READY; } - + if (!chip1 && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) { result = readl(addr); - + if ((result & 0x80) == (data & 0x80)) { chip1 = READY; } else { chip1 = ERR; } } - + if (!chip2 && ((result & (0x80 << 16)) == (data & (0x80 << 16)))) { chip2 = READY; } - + if (!chip2 && ((result >> 16) & BIT_PROGRAM_ERROR)) { result = readl(addr); - + if ((result & (0x80 << 16)) == (data & (0x80 << 16))) { chip2 = READY; } else { chip2 = ERR; } } - + } while (!chip1 || !chip2); - + writel(CMD_READ_ARRAY, addr); - + if (chip1 == ERR || chip2 == ERR || readl(addr) != data) { rc = ERR_PROG_ERROR; } - + if (iflag) { enable_interrupts(); } - + return rc; } @@ -399,9 +399,9 @@ int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) ulong cp, wp, data; int l; int i, rc; - + wp = (addr & ~3); /* get lower word aligned address */ - + /* * handle unaligned start bytes */ @@ -418,13 +418,13 @@ int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) for (; cnt==0 && i<4; ++i, ++cp) { data = (data >> 8) | (*(uchar *)cp << 24); } - + if ((rc = write_word(info, wp, data)) != 0) { return rc; } wp += 4; } - + /* * handle word aligned part */ @@ -437,11 +437,11 @@ int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) wp += 4; cnt -= 4; } - + if (cnt == 0) { return ERR_OK; } - + /* * handle unaligned tail bytes */ @@ -453,6 +453,6 @@ int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) for (; i<4; ++i, ++cp) { data = (data >> 8) | (*(uchar *)cp << 24); } - + return write_word(info, wp, data); } diff --git a/board/sc520_cdp/sc520_cdp.c b/board/sc520_cdp/sc520_cdp.c index 50a49e601a..0fc836c629 100644 --- a/board/sc520_cdp/sc520_cdp.c +++ b/board/sc520_cdp/sc520_cdp.c @@ -1,5 +1,5 @@ /* - * + * * (C) Copyright 2002 * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>. * @@ -40,11 +40,11 @@ /* ------------------------------------------------------------------------- */ - -/* + +/* * Theory: * We first set up all IRQs to be non-pci, edge triggered, - * when we later enumerate the pci bus and pci_sc520_fixup_irq() gets + * when we later enumerate the pci bus and pci_sc520_fixup_irq() gets * called we reallocate irqs to the pci bus with sc520_pci_set_irq() * as needed. Whe choose the irqs to gram from a configurable list * inside pci_sc520_fixup_irq() (If this list contains stupid irq's @@ -54,48 +54,48 @@ static void irq_init(void) { /* disable global interrupt mode */ - write_mmcr_byte(SC520_PICICR, 0x40); - + write_mmcr_byte(SC520_PICICR, 0x40); + /* set all irqs to edge */ write_mmcr_byte(SC520_MPICMODE, 0x00); write_mmcr_byte(SC520_SL1PICMODE, 0x00); write_mmcr_byte(SC520_SL2PICMODE, 0x00); - - /* active low polarity on PIC interrupt pins, + + /* active low polarity on PIC interrupt pins, * active high polarity on all other irq pins */ write_mmcr_word(SC520_INTPINPOL, 0x0000); /* set irq number mapping */ - write_mmcr_byte(SC520_GPTMR0MAP, SC520_IRQ_DISABLED); /* disable GP timer 0 INT */ + write_mmcr_byte(SC520_GPTMR0MAP, SC520_IRQ_DISABLED); /* disable GP timer 0 INT */ write_mmcr_byte(SC520_GPTMR1MAP, SC520_IRQ_DISABLED); /* disable GP timer 1 INT */ write_mmcr_byte(SC520_GPTMR2MAP, SC520_IRQ_DISABLED); /* disable GP timer 2 INT */ - write_mmcr_byte(SC520_PIT0MAP, SC520_IRQ0); /* Set PIT timer 0 INT to IRQ0 */ + write_mmcr_byte(SC520_PIT0MAP, SC520_IRQ0); /* Set PIT timer 0 INT to IRQ0 */ write_mmcr_byte(SC520_PIT1MAP, SC520_IRQ_DISABLED); /* disable PIT timer 1 INT */ write_mmcr_byte(SC520_PIT2MAP, SC520_IRQ_DISABLED); /* disable PIT timer 2 INT */ write_mmcr_byte(SC520_PCIINTAMAP, SC520_IRQ_DISABLED); /* disable PCI INT A */ write_mmcr_byte(SC520_PCIINTBMAP, SC520_IRQ_DISABLED); /* disable PCI INT B */ write_mmcr_byte(SC520_PCIINTCMAP, SC520_IRQ_DISABLED); /* disable PCI INT C */ write_mmcr_byte(SC520_PCIINTDMAP, SC520_IRQ_DISABLED); /* disable PCI INT D */ - write_mmcr_byte(SC520_DMABCINTMAP, SC520_IRQ_DISABLED); /* disable DMA INT */ + write_mmcr_byte(SC520_DMABCINTMAP, SC520_IRQ_DISABLED); /* disable DMA INT */ write_mmcr_byte(SC520_SSIMAP, SC520_IRQ_DISABLED); /* disable Synchronius serial INT */ write_mmcr_byte(SC520_WDTMAP, SC520_IRQ_DISABLED); /* disable Watchdog INT */ write_mmcr_byte(SC520_RTCMAP, SC520_IRQ8); /* Set RTC int to 8 */ write_mmcr_byte(SC520_WPVMAP, SC520_IRQ_DISABLED); /* disable write protect INT */ write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1); /* Set ICE Debug Serielport INT to IRQ1 */ write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13); /* Set FP error INT to IRQ13 */ - + if (CFG_USE_SIO_UART) { write_mmcr_byte(SC520_UART1MAP, SC520_IRQ_DISABLED); /* disable internal UART1 INT */ write_mmcr_byte(SC520_UART2MAP, SC520_IRQ_DISABLED); /* disable internal UART2 INT */ - write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ3); /* Set GPIRQ3 (ISA IRQ3) to IRQ3 */ + write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ3); /* Set GPIRQ3 (ISA IRQ3) to IRQ3 */ write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ4); /* Set GPIRQ4 (ISA IRQ4) to IRQ4 */ } else { write_mmcr_byte(SC520_UART1MAP, SC520_IRQ4); /* Set internal UART2 INT to IRQ4 */ write_mmcr_byte(SC520_UART2MAP, SC520_IRQ3); /* Set internal UART2 INT to IRQ3 */ - write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ3 (ISA IRQ3) */ + write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ3 (ISA IRQ3) */ write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ4 (ISA IRQ4) */ } - + write_mmcr_byte(SC520_GP1IMAP, SC520_IRQ1); /* Set GPIRQ1 (SIO IRQ1) to IRQ1 */ write_mmcr_byte(SC520_GP5IMAP, SC520_IRQ5); /* Set GPIRQ5 (ISA IRQ5) to IRQ5 */ write_mmcr_byte(SC520_GP6IMAP, SC520_IRQ6); /* Set GPIRQ6 (ISA IRQ6) to IRQ6 */ @@ -104,14 +104,14 @@ static void irq_init(void) write_mmcr_byte(SC520_GP9IMAP, SC520_IRQ9); /* Set GPIRQ9 (ISA IRQ2) to IRQ9 */ write_mmcr_byte(SC520_GP0IMAP, SC520_IRQ11); /* Set GPIRQ0 (ISA IRQ11) to IRQ10 */ write_mmcr_byte(SC520_GP2IMAP, SC520_IRQ12); /* Set GPIRQ2 (ISA IRQ12) to IRQ12 */ - write_mmcr_byte(SC520_GP10IMAP,SC520_IRQ14); /* Set GPIRQ10 (ISA IRQ14) to IRQ14 */ - + write_mmcr_byte(SC520_GP10IMAP,SC520_IRQ14); /* Set GPIRQ10 (ISA IRQ14) to IRQ14 */ + write_mmcr_word(SC520_PCIHOSTMAP, 0x11f); /* Map PCI hostbridge INT to NMI */ write_mmcr_word(SC520_ECCMAP, 0x100); /* Map SDRAM ECC failure INT to NMI */ - + } - + /* PCI stuff */ static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev) { @@ -125,64 +125,63 @@ static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev) CFG_FORTH_PCI_IRQ }; static int next_irq_index=0; - - char tmp_pin; + + char tmp_pin; int pin; - + pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin); pin = tmp_pin; - + pin-=1; /* pci config space use 1-based numbering */ if (-1 == pin) { return; /* device use no irq */ } - - - + + /* map device number + pin to a pin on the sc520 */ switch (PCI_DEV(dev)) { case 20: pin+=SC520_PCI_INTA; break; - + case 19: pin+=SC520_PCI_INTB; break; - + case 18: pin+=SC520_PCI_INTC; break; - + case 17: pin+=SC520_PCI_INTD; break; - - default: + + default: return; } - + pin&=3; /* wrap around */ - + if (sc520_pci_ints[pin] == -1) { - /* re-route one interrupt for us */ + /* re-route one interrupt for us */ if (next_irq_index > 3) { return; } - if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) { + if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) { return; } next_irq_index++; } - + if (-1 != sc520_pci_ints[pin]) { - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, sc520_pci_ints[pin]); } - PRINTF("fixup_irq: device %d pin %c irq %d\n", + PRINTF("fixup_irq: device %d pin %c irq %d\n", PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]); } - + static struct pci_controller sc520_cdp_hose = { fixup_irq: pci_sc520_cdp_fixup_irq, }; @@ -201,7 +200,7 @@ static void silence_uart(int port) void setup_ali_sio(int uart_primary) { ali512x_init(); - + ali512x_set_fdc(ALI_ENABLED, 0x3f2, 6, 0); ali512x_set_pp(ALI_ENABLED, 0x278, 7, 3); ali512x_set_uart(ALI_ENABLED, ALI_UART1, uart_primary?0x3f8:0x3e8, 4); @@ -209,21 +208,21 @@ void setup_ali_sio(int uart_primary) ali512x_set_rtc(ALI_DISABLED, 0, 0); ali512x_set_kbc(ALI_ENABLED, 1, 12); ali512x_set_cio(ALI_ENABLED); - + /* IrDa pins */ ali512x_cio_function(12, 1, 0, 0); ali512x_cio_function(13, 1, 0, 0); - + /* SSI chip select pins */ ali512x_cio_function(14, 0, 0, 0); /* SSI_CS */ - ali512x_cio_function(15, 0, 0, 0); /* SSI_MV */ + ali512x_cio_function(15, 0, 0, 0); /* SSI_MV */ ali512x_cio_function(16, 0, 0, 0); /* SSI_SPI# */ /* Board REV pins */ ali512x_cio_function(20, 0, 0, 1); ali512x_cio_function(21, 0, 0, 1); ali512x_cio_function(22, 0, 0, 1); - ali512x_cio_function(23, 0, 0, 1); + ali512x_cio_function(23, 0, 0, 1); } @@ -232,54 +231,53 @@ static void bus_init(void) { /* set up the GP IO pins */ - write_mmcr_word(SC520_PIOPFS31_16, 0xf7ff); /* set the GPIO pin function 31-16 reg */ + write_mmcr_word(SC520_PIOPFS31_16, 0xf7ff); /* set the GPIO pin function 31-16 reg */ write_mmcr_word(SC520_PIOPFS15_0, 0xffff); /* set the GPIO pin function 15-0 reg */ - write_mmcr_byte(SC520_CSPFS, 0xf8); /* set the CS pin function reg */ + write_mmcr_byte(SC520_CSPFS, 0xf8); /* set the CS pin function reg */ write_mmcr_byte(SC520_CLKSEL, 0x70); - - write_mmcr_byte(SC520_GPCSRT, 1); /* set the GP CS offset */ + + write_mmcr_byte(SC520_GPCSRT, 1); /* set the GP CS offset */ write_mmcr_byte(SC520_GPCSPW, 3); /* set the GP CS pulse width */ write_mmcr_byte(SC520_GPCSOFF, 1); /* set the GP CS offset */ write_mmcr_byte(SC520_GPRDW, 3); /* set the RD pulse width */ write_mmcr_byte(SC520_GPRDOFF, 1); /* set the GP RD offset */ - write_mmcr_byte(SC520_GPWRW, 3); /* set the GP WR pulse width */ + write_mmcr_byte(SC520_GPWRW, 3); /* set the GP WR pulse width */ write_mmcr_byte(SC520_GPWROFF, 1); /* set the GP WR offset */ - write_mmcr_word(SC520_BOOTCSCTL, 0x1823); /* set up timing of BOOTCS */ + write_mmcr_word(SC520_BOOTCSCTL, 0x1823); /* set up timing of BOOTCS */ write_mmcr_word(SC520_ROMCS1CTL, 0x1823); /* set up timing of ROMCS1 */ - write_mmcr_word(SC520_ROMCS2CTL, 0x1823); /* set up timing of ROMCS2 */ - + write_mmcr_word(SC520_ROMCS2CTL, 0x1823); /* set up timing of ROMCS2 */ + /* adjust the memory map: * by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM * and 256MB to 1G-128k (0x1000000 - 0x37ffffff) is mapped to PCI mmio - * we need to map 1G-128k - 1G (0x38000000 - 0x3fffffff) to CS1 */ - - - + * we need to map 1G-128k - 1G (0x38000000 - 0x3fffffff) to CS1 */ + + /* SRAM = GPCS3 128k @ d0000-effff*/ - write_mmcr_long(SC520_PAR2, 0x4e00400d); - + write_mmcr_long(SC520_PAR2, 0x4e00400d); + /* IDE0 = GPCS6 1f0-1f7 */ - write_mmcr_long(SC520_PAR3, 0x380801f0); + write_mmcr_long(SC520_PAR3, 0x380801f0); /* IDE1 = GPCS7 3f6 */ - write_mmcr_long(SC520_PAR4, 0x3c0003f6); + write_mmcr_long(SC520_PAR4, 0x3c0003f6); /* bootcs */ - write_mmcr_long(SC520_PAR12, 0x8bffe800); + write_mmcr_long(SC520_PAR12, 0x8bffe800); /* romcs2 */ - write_mmcr_long(SC520_PAR13, 0xcbfff000); + write_mmcr_long(SC520_PAR13, 0xcbfff000); /* romcs1 */ - write_mmcr_long(SC520_PAR14, 0xabfff800); + write_mmcr_long(SC520_PAR14, 0xabfff800); /* 680 LEDS */ - write_mmcr_long(SC520_PAR15, 0x30000640); - + write_mmcr_long(SC520_PAR15, 0x30000640); + write_mmcr_byte(SC520_ADDDECCTL, 0); - - asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */ + + asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */ if (CFG_USE_SIO_UART) { - write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) | UART2_DIS|UART1_DIS); + write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) | UART2_DIS|UART1_DIS); setup_ali_sio(1); } else { write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS)); @@ -321,21 +319,21 @@ static void bus_init(void) * PAR15 Port 0x680 LED display */ -/* +/* * This function should map a chunk of size bytes * of the system address space to the ISA bus - * + * * The function will return the memory address * as seen by the host (which may very will be the * same as the bus address) */ -u32 isa_map_rom(u32 bus_addr, int size) +u32 isa_map_rom(u32 bus_addr, int size) { u32 par; - - PRINTF("isa_map_rom asked to map %d bytes at %x\n", + + PRINTF("isa_map_rom asked to map %d bytes at %x\n", size, bus_addr); - + par = size; if (par < 0x80000) { par = 0x80000; @@ -346,12 +344,12 @@ u32 isa_map_rom(u32 bus_addr, int size) par <<= 18; par |= (bus_addr>>12); par |= 0x50000000; - + PRINTF ("setting PAR11 to %x\n", par); - + /* Map rom 0x10000 with PAR1 */ write_mmcr_long(SC520_PAR11, par); - + return bus_addr; } @@ -372,19 +370,19 @@ void isa_unmap_rom(u32 addr) #ifdef CONFIG_PCI #define PCI_ROM_TEMP_SPACE 0x10000 -/* +/* * This function should map a chunk of size bytes * of the system address space to the PCI bus, * suitable to map PCI ROMS (bus address < 16M) * the function will return the host memory address * which should be converted into a bus address - * before used to configure the PCI rom address + * before used to configure the PCI rom address * decoder */ -u32 pci_get_rom_window(struct pci_controller *hose, int size) +u32 pci_get_rom_window(struct pci_controller *hose, int size) { u32 par; - + par = size; if (par < 0x80000) { par = 0x80000; @@ -395,12 +393,12 @@ u32 pci_get_rom_window(struct pci_controller *hose, int size) par <<= 14; par |= (PCI_ROM_TEMP_SPACE>>16); par |= 0x72000000; - + PRINTF ("setting PAR1 to %x\n", par); - + /* Map rom 0x10000 with PAR1 */ write_mmcr_long(SC520_PAR1, par); - + return PCI_ROM_TEMP_SPACE; } @@ -417,61 +415,61 @@ void pci_remove_rom_window(struct pci_controller *hose, u32 addr) return; } PRINTF(" not ours\n"); - + } /* * This function is called in order to provide acces to the - * legacy video I/O ports on the PCI bus. - * After this function accesses to I/O ports 0x3b0-0x3bb and + * legacy video I/O ports on the PCI bus. + * After this function accesses to I/O ports 0x3b0-0x3bb and * 0x3c0-0x3df shuld result in transactions on the PCI bus. - * + * */ int pci_enable_legacy_video_ports(struct pci_controller *hose) { /* Map video memory to 0xa0000*/ write_mmcr_long(SC520_PAR0, 0x7200400a); - + /* forward all I/O accesses to PCI */ - write_mmcr_byte(SC520_ADDDECCTL, - read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI); - - + write_mmcr_byte(SC520_ADDDECCTL, + read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI); + + /* so we map away all io ports to pci (only way to access pci io * below 0x400. But then we have to map back the portions that we dont * use so that the generate cycles on the GPIO bus where the sio and - * ISA slots are connected, this requre the use of several PAR registers + * ISA slots are connected, this requre the use of several PAR registers */ - + /* bring 0x100 - 0x1ef back to ISA using PAR5 */ - write_mmcr_long(SC520_PAR5, 0x30ef0100); - + write_mmcr_long(SC520_PAR5, 0x30ef0100); + /* IDE use 1f0-1f7 */ - + /* bring 0x1f8 - 0x2f7 back to ISA using PAR6 */ - write_mmcr_long(SC520_PAR6, 0x30ff01f8); - + write_mmcr_long(SC520_PAR6, 0x30ff01f8); + /* com2 use 2f8-2ff */ - + /* bring 0x300 - 0x3af back to ISA using PAR7 */ - write_mmcr_long(SC520_PAR7, 0x30af0300); - + write_mmcr_long(SC520_PAR7, 0x30af0300); + /* vga use 3b0-3bb */ - + /* bring 0x3bc - 0x3bf back to ISA using PAR8 */ - write_mmcr_long(SC520_PAR8, 0x300303bc); - + write_mmcr_long(SC520_PAR8, 0x300303bc); + /* vga use 3c0-3df */ - + /* bring 0x3e0 - 0x3f5 back to ISA using PAR9 */ - write_mmcr_long(SC520_PAR9, 0x301503e0); - + write_mmcr_long(SC520_PAR9, 0x301503e0); + /* ide use 3f6 */ - + /* bring 0x3f7 back to ISA using PAR10 */ - write_mmcr_long(SC520_PAR10, 0x300003f7); - - /* com1 use 3f8-3ff */ + write_mmcr_long(SC520_PAR10, 0x300003f7); + + /* com1 use 3f8-3ff */ return 0; } @@ -484,20 +482,20 @@ int pci_enable_legacy_video_ports(struct pci_controller *hose) int board_init(void) { DECLARE_GLOBAL_DATA_PTR; - - init_sc520(); + + init_sc520(); bus_init(); irq_init(); - + /* max drive current on SDRAM */ write_mmcr_word(SC520_DSCTL, 0x0100); - + /* enter debug mode after next reset (only if jumper is also set) */ write_mmcr_byte(SC520_RESCFG, 0x08); /* configure the software timer to 33.333MHz */ write_mmcr_byte(SC520_SWTMRCFG, 0); gd->bus_clk = 33333000; - + return 0; } @@ -518,98 +516,96 @@ int last_stage_init(void) { int minor; int major; - + major = minor = 0; major |= ali512x_cio_in(23)?2:0; major |= ali512x_cio_in(22)?1:0; minor |= ali512x_cio_in(21)?2:0; minor |= ali512x_cio_in(20)?1:0; - + printf("AMD SC520 CDP revision %d.%d\n", major, minor); - + return 0; } - -void ssi_chip_select(int dev) +void ssi_chip_select(int dev) { - + /* Spunk board: SPI EEPROM is active-low, MW EEPROM and AUX are active high */ switch (dev) { case 1: /* SPI EEPROM */ ali512x_cio_out(16, 0); break; - + case 2: /* MW EEPROM */ ali512x_cio_out(15, 1); break; - - case 3: /* AUX */ + + case 3: /* AUX */ ali512x_cio_out(14, 1); break; - + case 0: ali512x_cio_out(16, 1); ali512x_cio_out(15, 0); ali512x_cio_out(14, 0); break; - + default: printf("Illegal SSI device requested: %d\n", dev); } } -void spi_init_f(void) +void spi_init_f(void) { #ifdef CONFIG_SC520_CDP_USE_SPI - spi_eeprom_probe(1); -#endif + spi_eeprom_probe(1); +#endif #ifdef CONFIG_SC520_CDP_USE_MW mw_eeprom_probe(2); -#endif +#endif } -ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len) +ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len) { int offset; int i; ssize_t res; - + offset = 0; for (i=0;i<alen;i++) { offset <<= 8; offset |= addr[i]; } - + #ifdef CONFIG_SC520_CDP_USE_SPI - res = spi_eeprom_read(1, offset, buffer, len); -#endif + res = spi_eeprom_read(1, offset, buffer, len); +#endif #ifdef CONFIG_SC520_CDP_USE_MW res = mw_eeprom_read(2, offset, buffer, len); -#endif +#endif return res; } -ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len) +ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len) { int offset; int i; ssize_t res; - + offset = 0; for (i=0;i<alen;i++) { offset <<= 8; offset |= addr[i]; } - + #ifdef CONFIG_SC520_CDP_USE_SPI res = spi_eeprom_write(1, offset, buffer, len); -#endif +#endif #ifdef CONFIG_SC520_CDP_USE_MW res = mw_eeprom_write(2, offset, buffer, len); -#endif +#endif return res; } - diff --git a/board/sc520_cdp/sc520_cdp_asm.S b/board/sc520_cdp/sc520_cdp_asm.S index 1e255fab2e..be7b2bb482 100644 --- a/board/sc520_cdp/sc520_cdp_asm.S +++ b/board/sc520_cdp/sc520_cdp_asm.S @@ -23,7 +23,7 @@ /* now setup the General purpose bus to give us access to the LEDs. * We can then use the leds to display status information. - */ + */ sc520_cdp_registers: /* size offset value */ @@ -45,12 +45,12 @@ sc520_cdp_registers: /* board early intialization */ .globl early_board_init early_board_init: - movl $sc520_cdp_registers,%esi -init_loop: - movl $0xfffef000,%edi /* MMCR base to edi */ + movl $sc520_cdp_registers,%esi +init_loop: + movl $0xfffef000,%edi /* MMCR base to edi */ movw (%esi), %bx /* load sizer to bx */ cmpw $0, %bx /* if sie is 0 we're done */ - je done + je done xorl %edx,%edx movw 2(%esi), %dx /* load MMCR offset to dx */ addl %edx, %edi /* add offset to base in edi */ @@ -61,7 +61,7 @@ init_loop: je word /* word op? */ movl %eax, (%edi) /* must be long, then */ jmp next -byte: movb %al,(%edi) +byte: movb %al,(%edi) jmp next word: movw %ax,(%edi) next: addl $8, %esi /* advance esi */ @@ -83,4 +83,3 @@ __show_boot_progress: movw $0x680, %dx out %al, %dx jmp *%ebp - diff --git a/board/sc520_cdp/sc520_cdp_asm16.S b/board/sc520_cdp/sc520_cdp_asm16.S index 0e0b0c028a..a3e700a626 100644 --- a/board/sc520_cdp/sc520_cdp_asm16.S +++ b/board/sc520_cdp/sc520_cdp_asm16.S @@ -34,32 +34,32 @@ board_init16: /* Alias MMCR to 0xdf000 */ movw $0xfffc, %dx - movl $0x800df0cb, %eax - outl %eax, %dx - + movl $0x800df0cb, %eax + outl %eax, %dx + /* Set ds to point to MMCR alias */ - movw $0xdf00, %ax - movw %ax, %ds - - /* Map the entire flash at 0x38000000 + movw $0xdf00, %ax + movw %ax, %ds + + /* Map the entire flash at 0x38000000 * (with BOOTCS and PAR14, use 0xabfff800 for ROMCS1) */ movl $0xc0, %edi - movl $0x8bfff800, %eax - movl %eax, (%di) + movl $0x8bfff800, %eax + movl %eax, (%di) /* Disable SDRAM write buffer */ movw $0x40,%di - xorw %ax,%ax - movb %al, (%di) + xorw %ax,%ax + movb %al, (%di) /* Disabe MMCR alias */ movw $0xfffc, %dx - movl $0x000000cb, %eax - outl %eax, %dx - + movl $0x000000cb, %eax + outl %eax, %dx + /* the return address is tored in bp */ jmp *%bp - + .section .bios, "ax" .code16 @@ -67,18 +67,17 @@ board_init16: realmode_reset: /* Alias MMCR to 0xdf000 */ movw $0xfffc, %dx - movl $0x800df0cb, %eax - outl %eax, %dx - + movl $0x800df0cb, %eax + outl %eax, %dx + /* Set ds to point to MMCR alias */ - movw $0xdf00, %ax - movw %ax, %ds - + movw $0xdf00, %ax + movw %ax, %ds + /* issue software reset thorugh MMCR */ movl $0xd72, %edi - movb $0x01, %al - movb %al, (%di) + movb $0x01, %al + movb %al, (%di) 1: hlt jmp 1 - diff --git a/board/sc520_cdp/u-boot.lds b/board/sc520_cdp/u-boot.lds index fbab9b85f2..1944a74aaa 100644 --- a/board/sc520_cdp/u-boot.lds +++ b/board/sc520_cdp/u-boot.lds @@ -26,60 +26,65 @@ OUTPUT_ARCH(i386) ENTRY(_start) SECTIONS -{ +{ . = 0x387c0000; /* Where bootcode in the flash is mapped */ .text : { *(.text); } - - . = ALIGN(4); - .rodata : { *(.rodata) } - . = 0x400000; /* Ram data segment to use */ + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = 0x400000; /* Ram data segment to use */ _i386boot_romdata_dest = ABSOLUTE(.); - .data : AT ( LOADADDR(.rodata) + SIZEOF(.rodata) ) { *(.data) } - _i386boot_romdata_start = LOADADDR(.data); + .data : AT ( LOADADDR(.rodata) + SIZEOF(.rodata) ) { *(.data) } + _i386boot_romdata_start = LOADADDR(.data); - . = ALIGN(4); - .got : AT ( LOADADDR(.data) + SIZEOF(.data) ) { *(.got) } - _i386boot_romdata_size = SIZEOF(.data) + SIZEOF(.got); + . = ALIGN(4); + .got : AT ( LOADADDR(.data) + SIZEOF(.data) ) { *(.got) } + _i386boot_romdata_size = SIZEOF(.data) + SIZEOF(.got); - . = ALIGN(4); + . = ALIGN(4); _i386boot_bss_start = ABSOLUTE(.); - .bss : { *(.bss) } + .bss : { *(.bss) } _i386boot_bss_size = SIZEOF(.bss); - - + + /* 16bit realmode trampoline code */ .realmode 0x7c0 : AT ( LOADADDR(.got) + SIZEOF(.got) ) { *(.realmode) } - + _i386boot_realmode = LOADADDR(.realmode); _i386boot_realmode_size = SIZEOF(.realmode); - + /* 16bit BIOS emulation code (just enough to boot Linux) */ .bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { *(.bios) } - + _i386boot_bios = LOADADDR(.bios); _i386boot_bios_size = SIZEOF(.bios); - + + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + /* The load addresses below assumes that the flash * will be mapped so that 0x387f0000 == 0xffff0000 * at reset time * - * The fe00 and ff00 offsets of the start32 and start16 + * The fe00 and ff00 offsets of the start32 and start16 * segments are arbitrary, the just have to be mapped * at reset and the code have to fit. * The fff0 offset of reset is important, however. */ - - + + . = 0xfffffe00; - .start32 : AT (0x387ffe00) { *(.start32); } - + .start32 : AT (0x387ffe00) { *(.start32); } + . = 0xff00; - .start16 : AT (0x387fff00) { *(.start16); } - + .start16 : AT (0x387fff00) { *(.start16); } + . = 0xfff0; - .reset : AT (0x387ffff0) { *(.reset); } + .reset : AT (0x387ffff0) { *(.reset); } _i386boot_end = (LOADADDR(.reset) + SIZEOF(.reset) ); } |