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-rw-r--r--board/mx1ads/mx1ads.c44
-rw-r--r--board/mx1ads/syncflash.c42
-rw-r--r--board/mx1ads/u-boot.lds3
3 files changed, 34 insertions, 55 deletions
diff --git a/board/mx1ads/mx1ads.c b/board/mx1ads/mx1ads.c
index 453e4bb0a0..661fbab0ab 100644
--- a/board/mx1ads/mx1ads.c
+++ b/board/mx1ads/mx1ads.c
@@ -23,9 +23,9 @@
* MA 02111-1307 USA
*/
-
#include <common.h>
-#include <mc9328.h>
+/*#include <mc9328.h>*/
+#include <asm/arch-arm920t/imx-regs.h>
/* ------------------------------------------------------------------------- */
@@ -67,7 +67,6 @@ static inline void delay (unsigned long loops) {
* Miscellaneous platform dependent initialisations
*/
-
void SetAsynchMode(void) {
__asm__ (
"mrc p15,0,r0,c1,c0,0 \n"
@@ -85,42 +84,34 @@ int board_init (void) {
volatile unsigned int tmp;
- mc9328sid = MX1_SIDR;
+ mc9328sid = SIDR;
- MX1_GPCR = 0x000003AB; /* I/O pad driving strength */
+ GPCR = 0x000003AB; /* I/O pad driving strength */
/* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */
/* MX1_CS1L = 0x11110601; */
- MX1_MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */
-
-/* MX1_MPCTL0 = 0x003f1437; */ /* setting for 192 MHz MCU PLL CLK */
+ MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */
/* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and
* BCLK divider to 2 (i.e. BCLK to 48 MHz)
*/
- MX1_CSCR = 0xAF000403;
+ CSCR = 0xAF000403;
- MX1_CSCR |= 0x00200000; /* Trigger the restart bit(bit 21) */
- MX1_CSCR &= 0xFFFF7FFF; /* Program PRESC bit(bit 15) to 0 to divide-by-1 */
+ CSCR |= 0x00200000; /* Trigger the restart bit(bit 21) */
+ CSCR &= 0xFFFF7FFF; /* Program PRESC bit(bit 15) to 0 to divide-by-1 */
/* setup cs4 for cs8900 ethernet */
- MX1_CS4U = 0x00000F00; /* Initialize CS4 for CS8900 ethernet */
- MX1_CS4L = 0x00001501;
+ CS4U = 0x00000F00; /* Initialize CS4 for CS8900 ethernet */
+ CS4L = 0x00001501;
- MX1_GIUS_A &= 0xFF3FFFFF;
- MX1_GPR_A &= 0xFF3FFFFF;
+ GIUS(0) &= 0xFF3FFFFF;
+ GPR(0) &= 0xFF3FFFFF;
tmp = *(unsigned int *)(0x1500000C);
tmp = *(unsigned int *)(0x1500000C);
-/* setup timer 1 as system timer */
-
- MX1_TPRER1 = 0x1f; /* divide by 32 */
- MX1_TCTL1 = 0x19; /* clock in from 32k Osc. */
-
-
SetAsynchMode();
gd->bd->bi_arch_number = 160; /* Arch number of MX1ADS Board */
@@ -131,19 +122,19 @@ int board_init (void) {
dcache_enable();
/* set PERCLKs */
- MX1_PCDR = 0x00000055; /* set PERCLKS */
+ PCDR = 0x00000055; /* set PERCLKS */
/* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes
* PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place
* all sources selected as normal interrupt
*/
- MX1_INTTYPEH = 0;
- MX1_INTTYPEL = 0;
+/* MX1_INTTYPEH = 0;
+ MX1_INTTYPEL = 0;
+*/
return 0;
}
-
int board_late_init(void) {
setenv("stdout", "serial");
@@ -163,13 +154,10 @@ int board_late_init(void) {
default :
printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n",mc9328sid);
break;
-
}
-
return 0;
}
-
int dram_init (void) {
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/mx1ads/syncflash.c b/board/mx1ads/syncflash.c
index 09fc0f86e4..eb7fde5071 100644
--- a/board/mx1ads/syncflash.c
+++ b/board/mx1ads/syncflash.c
@@ -24,7 +24,8 @@
*/
#include <common.h>
-#include <mc9328.h>
+/*#include <mc9328.h>*/
+#include <asm/arch/imx-regs.h>
typedef unsigned long * p_u32;
@@ -33,27 +34,26 @@ typedef unsigned long * p_u32;
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/* Following Setting is for CSD1 */
-#define SFCTL 0x00221004
-#define reg_SFCTL __REG(SFCTL)
+#define SFCTL 0x00221004
+#define reg_SFCTL __REG(SFCTL)
-#define SYNCFLASH_A10 (0x00100000)
+#define SYNCFLASH_A10 (0x00100000)
-#define CMD_NORMAL (0x81020300) /* Normal Mode */
-#define CMD_PREC (CMD_NORMAL + 0x10000000) /* Precharge Command */
-#define CMD_AUTO (CMD_NORMAL + 0x20000000) /* Auto Refresh Command */
-#define CMD_LMR (CMD_NORMAL + 0x30000000) /* Load Mode Register Command */
-#define CMD_LCR (CMD_NORMAL + 0x60000000) /* LCR Command */
-#define CMD_PROGRAM (CMD_NORMAL + 0x70000000)
+#define CMD_NORMAL (0x81020300) /* Normal Mode */
+#define CMD_PREC (CMD_NORMAL + 0x10000000) /* Precharge Command */
+#define CMD_AUTO (CMD_NORMAL + 0x20000000) /* Auto Refresh Command */
+#define CMD_LMR (CMD_NORMAL + 0x30000000) /* Load Mode Register Command */
+#define CMD_LCR (CMD_NORMAL + 0x60000000) /* LCR Command */
+#define CMD_PROGRAM (CMD_NORMAL + 0x70000000)
-#define MODE_REG_VAL (CFG_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */
+#define MODE_REG_VAL (CFG_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */
/* LCR Command */
-#define LCR_READSTATUS (0x0001C000) /* 0x70 */
-#define LCR_ERASE_CONFIRM (0x00008000) /* 0x20 */
-#define LCR_ERASE_NVMODE (0x0000C000) /* 0x30 */
-#define LCR_PROG_NVMODE (0x00028000) /* 0xA0 */
-#define LCR_SR_CLEAR (0x00014000) /* 0x50 */
-
+#define LCR_READSTATUS (0x0001C000) /* 0x70 */
+#define LCR_ERASE_CONFIRM (0x00008000) /* 0x20 */
+#define LCR_ERASE_NVMODE (0x0000C000) /* 0x30 */
+#define LCR_PROG_NVMODE (0x00028000) /* 0xA0 */
+#define LCR_SR_CLEAR (0x00014000) /* 0x50 */
/* Get Status register */
u32 SF_SR(void) {
@@ -82,7 +82,6 @@ u8 SF_Ready(void) {
if ((tmp & 0x00000080) && (tmp & 0x0000001C)) {
printf ("SyncFlash Error code %08x\n",tmp);
-
};
if (tmp == 0x00800080) /* Test Bit 7 of SR */
@@ -98,7 +97,6 @@ void SF_PrechargeAll(void) {
reg_SFCTL = CMD_PREC; /* Set Precharge Command */
tmp = __REG(CFG_FLASH_BASE + SYNCFLASH_A10); /* Issue Precharge All Command */
-
}
/* set SyncFlash to normal mode */
@@ -128,7 +126,6 @@ void SF_Erase(u32 RowAddress) {
while(!SF_Ready());
}
-
void SF_NvmodeErase(void) {
SF_PrechargeAll();
@@ -149,10 +146,8 @@ void SF_NvmodeWrite(void) {
reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */
__REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0; /* Confirm not needed */
-
}
-
/****************************************************************************************/
ulong flash_init(void) {
@@ -195,7 +190,6 @@ ulong flash_init(void) {
return FLASH_BANK_SIZE;
}
-
void flash_print_info (flash_info_t *info) {
int i;
@@ -209,7 +203,6 @@ void flash_print_info (flash_info_t *info) {
break;
}
-
switch (info->flash_id & FLASH_TYPEMASK) {
case (FLASH_MT28S4M16LC & FLASH_TYPEMASK):
printf("2x FLASH_MT28S4M16LC (16MB Total)\n");
@@ -236,7 +229,6 @@ void flash_print_info (flash_info_t *info) {
printf ("\n");
}
-
/*-----------------------------------------------------------------------*/
int flash_erase (flash_info_t *info, int s_first, int s_last) {
diff --git a/board/mx1ads/u-boot.lds b/board/mx1ads/u-boot.lds
index 53743cdb80..649216abda 100644
--- a/board/mx1ads/u-boot.lds
+++ b/board/mx1ads/u-boot.lds
@@ -23,7 +23,6 @@
* MA 02111-1307 USA
*/
-
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
@@ -34,7 +33,7 @@ SECTIONS
. = ALIGN(4);
.text :
{
- cpu/mc9328/start.o (.text)
+ cpu/arm920t/start.o (.text)
*(.text)
}
generated by cgit (git 2.34.1) at 2024-11-19 09:21:40 +0000