diff options
Diffstat (limited to 'board/freescale')
47 files changed, 0 insertions, 3850 deletions
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 04e04a6358..114b7ba8f9 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -48,7 +48,6 @@ obj-$(CONFIG_TARGET_MPC8548CDS) += cds_pci_ft.o obj-$(CONFIG_TARGET_MPC8555CDS) += cds_pci_ft.o obj-$(CONFIG_TARGET_MPC8536DS) += ics307_clk.o -obj-$(CONFIG_TARGET_MPC8572DS) += ics307_clk.o obj-$(CONFIG_TARGET_P1022DS) += ics307_clk.o obj-$(CONFIG_P2020DS) += ics307_clk.o obj-$(CONFIG_TARGET_P3041DS) += ics307_clk.o diff --git a/board/freescale/common/pixis.h b/board/freescale/common/pixis.h index 40053c45bb..f19e85cb1c 100644 --- a/board/freescale/common/pixis.h +++ b/board/freescale/common/pixis.h @@ -44,117 +44,6 @@ typedef struct pixis { u8 vtempmax[2]; u8 res2[4]; } __attribute__ ((packed)) pixis_t; - -#elif defined(CONFIG_TARGET_MPC8544DS) -typedef struct pixis { - u8 id; - u8 ver; - u8 pver; - u8 csr; - u8 rst; - u8 pwr; - u8 aux1; - u8 spd; - u8 res[8]; - u8 vctl; - u8 vstat; - u8 vcfgen0; - u8 vcfgen1; - u8 vcore0; - u8 res1; - u8 vboot; - u8 vspeed[2]; - u8 vclkh; - u8 vclkl; - u8 watch; - u8 led; - u8 vspeed2; - u8 res2[34]; -} __attribute__ ((packed)) pixis_t; - -#elif defined(CONFIG_TARGET_MPC8572DS) -typedef struct pixis { - u8 id; - u8 ver; - u8 pver; - u8 csr; - u8 rst; - u8 pwr1; - u8 aux1; - u8 spd; - u8 aux2; - u8 res[7]; - u8 vctl; - u8 vstat; - u8 vcfgen0; - u8 vcfgen1; - u8 vcore0; - u8 res1; - u8 vboot; - u8 vspeed[3]; - u8 res2[2]; - u8 sclk[3]; - u8 dclk[3]; - u8 res3[2]; - u8 watch; - u8 led; - u8 res4[25]; -} __attribute__ ((packed)) pixis_t; - -#elif defined(CONFIG_TARGET_MPC8610HPCD) -typedef struct pixis { - u8 id; - u8 ver; /* also called arch */ - u8 pver; - u8 csr; - u8 rst; - u8 pwr; - u8 aux; - u8 spd; - u8 brdcfg0; - u8 brdcfg1; - u8 res[4]; - u8 led; - u8 serno; - u8 vctl; - u8 vstat; - u8 vcfgen0; - u8 vcfgen1; - u8 vcore0; - u8 res1; - u8 vboot; - u8 vspeed[2]; - u8 res2; - u8 sclk[3]; - u8 res3; - u8 watch; - u8 res4[33]; -} __attribute__ ((packed)) pixis_t; - -#elif defined(CONFIG_TARGET_MPC8641HPCN) -typedef struct pixis { - u8 id; - u8 ver; - u8 pver; - u8 csr; - u8 rst; - u8 pwr; - u8 aux; - u8 spd; - u8 res[8]; - u8 vctl; - u8 vstat; - u8 vcfgen0; - u8 vcfgen1; - u8 vcore0; - u8 res1; - u8 vboot; - u8 vspeed[2]; - u8 vclkh; - u8 vclkl; - u8 watch; - u8 res3[36]; -} __attribute__ ((packed)) pixis_t; #else #error Need to define pixis_t for this board #endif diff --git a/board/freescale/ls2080a/Kconfig b/board/freescale/ls2080a/Kconfig deleted file mode 100644 index b5033511b5..0000000000 --- a/board/freescale/ls2080a/Kconfig +++ /dev/null @@ -1,35 +0,0 @@ -if TARGET_LS2080A_EMU - -config SYS_BOARD - default "ls2080a" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "fsl-layerscape" - -config SYS_CONFIG_NAME - default "ls2080a_emu" - -source "board/freescale/common/Kconfig" - -endif - -if TARGET_LS2080A_SIMU - -config SYS_BOARD - default "ls2080a" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "fsl-layerscape" - -config SYS_CONFIG_NAME - default "ls2080a_simu" - -source "board/freescale/common/Kconfig" - -endif diff --git a/board/freescale/ls2080a/MAINTAINERS b/board/freescale/ls2080a/MAINTAINERS deleted file mode 100644 index e0e4e3f83e..0000000000 --- a/board/freescale/ls2080a/MAINTAINERS +++ /dev/null @@ -1,9 +0,0 @@ -LS2080A BOARD -M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> -M: Priyanka Jain <priyanka.jain@nxp.com> -S: Maintained -F: board/freescale/ls2080a/ -F: include/configs/ls2080a_emu.h -F: configs/ls2080a_emu_defconfig -F: include/configs/ls2080a_simu.h -F: configs/ls2080a_simu_defconfig diff --git a/board/freescale/ls2080a/Makefile b/board/freescale/ls2080a/Makefile deleted file mode 100644 index 87e26d9770..0000000000 --- a/board/freescale/ls2080a/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2014-15 Freescale Semiconductor - -obj-y += ls2080a.o -obj-y += ddr.o diff --git a/board/freescale/ls2080a/README b/board/freescale/ls2080a/README deleted file mode 100644 index 646cc02693..0000000000 --- a/board/freescale/ls2080a/README +++ /dev/null @@ -1,27 +0,0 @@ -Freescale ls2080a_emu - -This is a emulator target with limited peripherals. - -Memory map from core's view - -0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom -0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR -0x00_1800_0000 .. 0x00_181F_FFFF OCRAM -0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1 -0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1 -0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2 -0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2 - -Other addresses are either reserved, or not used directly by U-Boot. -This list should be updated when more addresses are used. - -Booting Linux flavors which do not support 48-bit VA (< Linux 3.18) -------------------------------------------------------------------- -One needs to use appropriate bootargs to boot Linux flavors which do -not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown -below: - -=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram - earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m - hugepages=16 mem=2048M' - diff --git a/board/freescale/ls2080a/ddr.c b/board/freescale/ls2080a/ddr.c deleted file mode 100644 index 29d7bd1c5e..0000000000 --- a/board/freescale/ls2080a/ddr.c +++ /dev/null @@ -1,172 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> -#include <log.h> -#include <asm/arch/soc.h> -#include <asm/arch/clock.h> -#include <asm/global_data.h> -#include "ddr.h" - -DECLARE_GLOBAL_DATA_PTR; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - - if (ctrl_num > 3) { - printf("Not supported controller number %d\n", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - /* - * we use identical timing for all slots. If needed, change the code - * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; - */ - if (popts->registered_dimm_en) - pbsp = rdimms[ctrl_num]; - else - pbsp = udimms[ctrl_num]; - - - /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks && - (pdimm->rank_density >> 30) >= pbsp->rank_gb) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found for data rate %lu MT/s\n" - "Trying to use the highest speed (%u) parameters\n", - ddr_freq, pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - } else { - panic("DIMM is not supported by this board"); - } -found: - debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" - "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n", - pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, - pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, - pbsp->wrlvl_ctl_3); -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR - if (ctrl_num == CONFIG_DP_DDR_CTRL) { - /* force DDR bus width to 32 bits */ - popts->data_bus_width = 1; - popts->otf_burst_chop_en = 0; - popts->burst_length = DDR_BL8; - popts->bstopre = 0; /* enable auto precharge */ - } -#endif - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 1; - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - - /* - * Rtt and Rtt_WR override - */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - -#ifdef CONFIG_SYS_FSL_DDR4 - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | - DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ -#else - /* DHC_EN =1, ODT = 75 Ohm */ - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); -#endif -} - -#ifdef CONFIG_SYS_DDR_RAW_TIMING -dimm_params_t ddr_raw_timing = { - .n_ranks = 2, - .rank_density = 1073741824u, - .capacity = 2147483648, - .primary_sdram_width = 64, - .ec_sdram_width = 0, - .registered_dimm = 0, - .mirrored_dimm = 0, - .n_row_addr = 14, - .n_col_addr = 10, - .n_banks_per_sdram_device = 8, - .edc_config = 0, - .burst_lengths_bitmask = 0x0c, - - .tckmin_x_ps = 937, - .caslat_x = 0x6FC << 4, /* 14,13,11,10,9,8,7,6 */ - .taa_ps = 13090, - .twr_ps = 15000, - .trcd_ps = 13090, - .trrd_ps = 5000, - .trp_ps = 13090, - .tras_ps = 33000, - .trc_ps = 46090, - .trfc_ps = 160000, - .twtr_ps = 7500, - .trtp_ps = 7500, - .refresh_rate_ps = 7800000, - .tfaw_ps = 25000, -}; - -int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, - unsigned int controller_number, - unsigned int dimm_number) -{ - const char dimm_model[] = "Fixed DDR on board"; - - if (((controller_number == 0) && (dimm_number == 0)) || - ((controller_number == 1) && (dimm_number == 0))) { - memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); - memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); - } - - return 0; -} -#endif - -int fsl_initdram(void) -{ - puts("Initializing DDR...."); - - puts("using SPD\n"); - gd->ram_size = fsl_ddr_sdram(); - - return 0; -} diff --git a/board/freescale/ls2080a/ddr.h b/board/freescale/ls2080a/ddr.h deleted file mode 100644 index d21b926558..0000000000 --- a/board/freescale/ls2080a/ddr.h +++ /dev/null @@ -1,85 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __DDR_H__ -#define __DDR_H__ -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 rank_gb; - u32 clk_adjust; - u32 wrlvl_start; - u32 wrlvl_ctl_2; - u32 wrlvl_ctl_3; -}; - -/* - * These tables contain all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ - -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ - {2, 2140, 0, 4, 4, 0x0, 0x0}, - {1, 2140, 0, 4, 4, 0x0, 0x0}, - {} -}; - -/* DP-DDR DIMM */ -static const struct board_specific_parameters udimm2[] = { - /* - * memory controller 2 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ - {2, 2140, 0, 4, 4, 0x0, 0x0}, - {1, 2140, 0, 4, 4, 0x0, 0x0}, - {} -}; - -static const struct board_specific_parameters rdimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ - {4, 2140, 0, 5, 4, 0x0, 0x0}, - {2, 2140, 0, 5, 4, 0x0, 0x0}, - {1, 2140, 0, 4, 4, 0x0, 0x0}, - {} -}; - -/* DP-DDR DIMM */ -static const struct board_specific_parameters rdimm2[] = { - /* - * memory controller 2 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ - {4, 2140, 0, 5, 4, 0x0, 0x0}, - {2, 2140, 0, 5, 4, 0x0, 0x0}, - {1, 2140, 0, 4, 4, 0x0, 0x0}, - {} -}; - -static const struct board_specific_parameters *udimms[] = { - udimm0, - udimm0, - udimm2, -}; - -static const struct board_specific_parameters *rdimms[] = { - rdimm0, - rdimm0, - rdimm2, -}; - - -#endif diff --git a/board/freescale/ls2080a/ls2080a.c b/board/freescale/ls2080a/ls2080a.c deleted file mode 100644 index 48437a52e4..0000000000 --- a/board/freescale/ls2080a/ls2080a.c +++ /dev/null @@ -1,148 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor - */ -#include <common.h> -#include <init.h> -#include <malloc.h> -#include <errno.h> -#include <net.h> -#include <netdev.h> -#include <fsl_ifc.h> -#include <fsl_ddr.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <fdt_support.h> -#include <linux/libfdt.h> -#include <fsl-mc/fsl_mc.h> -#include <env_internal.h> -#include <asm/arch/soc.h> - -DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - init_final_memctl_regs(); - -#ifdef CONFIG_ENV_IS_NOWHERE - gd->env_addr = (ulong)&default_environment[0]; -#endif - - return 0; -} - -int board_early_init_f(void) -{ - fsl_lsch3_early_init_f(); - return 0; -} - -void detail_board_ddr_info(void) -{ - puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); - print_ddr_info(0); -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR - if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { - puts("\nDP-DDR "); - print_size(gd->bd->bi_dram[2].size, ""); - print_ddr_info(CONFIG_DP_DDR_CTRL); - } -#endif -} - -int board_eth_init(struct bd_info *bis) -{ - int error = 0; - -#ifdef CONFIG_SMC91111 - error = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) - error = cpu_eth_init(bis); -#endif - return error; -} - -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) -void fdt_fixup_board_enet(void *fdt) -{ - int offset; - - offset = fdt_path_offset(fdt, "/soc/fsl-mc"); - - /* - * TODO: Remove this when backward compatibility - * with old DT node (/fsl-mc) is no longer needed. - */ - if (offset < 0) - offset = fdt_path_offset(fdt, "/fsl-mc"); - - if (offset < 0) { - printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", - __func__, offset); - return; - } - - if (get_mc_boot_status() == 0 && - (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) - fdt_status_okay(fdt, offset); - else - fdt_status_fail(fdt, offset); -} - -void board_quiesce_devices(void) -{ - fsl_mc_ldpaa_exit(gd->bd); -} -#endif - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, struct bd_info *bd) -{ - u64 base[CONFIG_NR_DRAM_BANKS]; - u64 size[CONFIG_NR_DRAM_BANKS]; - - ft_cpu_setup(blob, bd); - - /* fixup DT for the two GPP DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; - -#ifdef CONFIG_RESV_RAM - /* reduce size if reserved memory is within this bank */ - if (gd->arch.resv_ram >= base[0] && - gd->arch.resv_ram < base[0] + size[0]) - size[0] = gd->arch.resv_ram - base[0]; - else if (gd->arch.resv_ram >= base[1] && - gd->arch.resv_ram < base[1] + size[1]) - size[1] = gd->arch.resv_ram - base[1]; -#endif - - fdt_fixup_memory_banks(blob, base, size, 2); - - fdt_fsl_mc_fixup_iommu_map_entry(blob); - -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) - fdt_fixup_board_enet(blob); -#endif - - return 0; -} -#endif - -#if defined(CONFIG_RESET_PHY_R) -void reset_phy(void) -{ -} -#endif - -#ifdef CONFIG_TFABOOT -void *env_sf_get_env_addr(void) -{ - return (void *)(CONFIG_SYS_FSL_QSPI_BASE1 + CONFIG_ENV_OFFSET); -} -#endif diff --git a/board/freescale/mpc8544ds/Kconfig b/board/freescale/mpc8544ds/Kconfig deleted file mode 100644 index c3e25b89a0..0000000000 --- a/board/freescale/mpc8544ds/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC8544DS - -config SYS_BOARD - default "mpc8544ds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8544DS" - -endif diff --git a/board/freescale/mpc8544ds/MAINTAINERS b/board/freescale/mpc8544ds/MAINTAINERS deleted file mode 100644 index 74e7249e47..0000000000 --- a/board/freescale/mpc8544ds/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MPC8544DS BOARD -M: Priyanka Jain <priyanka.jain@nxp.com> -S: Maintained -F: board/freescale/mpc8544ds/ -F: include/configs/MPC8544DS.h -F: configs/MPC8544DS_defconfig diff --git a/board/freescale/mpc8544ds/Makefile b/board/freescale/mpc8544ds/Makefile deleted file mode 100644 index 1693ae8433..0000000000 --- a/board/freescale/mpc8544ds/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2007 Freescale Semiconductor, Inc. -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y += mpc8544ds.o -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/mpc8544ds/README b/board/freescale/mpc8544ds/README deleted file mode 100644 index b49c3c07c4..0000000000 --- a/board/freescale/mpc8544ds/README +++ /dev/null @@ -1,122 +0,0 @@ -Overview --------- -The MPC8544DS system is similar to the 85xx CDS systems such -as the MPC8548CDS due to the similar E500 core. However, it -is placed on the same board as the 8641 HPCN system. - - -Flash Banks ------------ -Like the 85xx CDS systems, the 8544 DS board has two flash banks. -They are both present on boot, but there locations can be swapped -using the dip-switch SW10, bit 2. - -However, unlike the CDS systems, but similar to the 8641 HPCN -board, a runtime reset through the FPGA can also affect a swap -on the flash bank mappings for the next reset cycle. - -Irrespective of the switch SW10[2], booting is always from the -boot bank at 0xfff8_0000. - - -Memory Map ----------- - -0xff80_0000 - 0xffbf_ffff Alternate bank 4MB -0xffc0_0000 - 0xffff_ffff Boot bank 4MB - -0xffb8_0000 Alternate image start 512KB -0xfff8_0000 Boot image start 512KB - - -Flashing Images ---------------- - -For example, to place a new image in the alternate flash bank -and then reset with that new image temporarily, use this: - - tftp 1000000 u-boot.bin.8544ds - erase ffb80000 ffbfffff - cp.b 1000000 ffb80000 80000 - pixis_reset altbank - - -To overwrite the image in the boot flash bank: - - tftp 1000000 u-boot.bin.8544ds - protect off all - erase fff80000 ffffffff - cp.b 1000000 fff80000 80000 - -Other example U-Boot image and flash manipulations examples -can be found in the README.mpc85xxcds file as well. - - -The pixis_reset command ------------------------ -A new command, "pixis_reset", is introduced to reset mpc8641hpcn board -using the FPGA sequencer. When the board restarts, it has the option -of using either the current or alternate flash bank as the boot -image, with or without the watchdog timer enabled, and finally with -or without frequency changes. - -Usage is; - - pixis_reset - pixis_reset altbank - pixis_reset altbank wd - pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> - pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> - -Examples; - - /* reset to current bank, like "reset" command */ - pixis_reset - - /* reset board but use the to alternate flash bank */ - pixis_reset altbank - - /* reset board, use alternate flash bank with watchdog timer enabled*/ - pixis_reset altbank wd - - /* reset board to alternate bank with frequency changed. - * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio - */ - pixis-reset altbank cf 40 2.5 10 - -Valid clock choices are in the 8641 Reference Manuals. - - -Using the Device Tree Source File ---------------------------------- -To create the DTB (Device Tree Binary) image file, -use a command similar to this: - - dtc -b 0 -f -I dts -O dtb mpc8544ds.dts > mpc8544ds.dtb - -Likely, that .dts file will come from here; - - linux-2.6/arch/powerpc/boot/dts/mpc8544ds.dts - -After placing the DTB file in your TFTP disk area, -you can download that dtb file using a command like: - - tftp 900000 mpc8544ds.dtb - -Burn it to flash if you want. - - -Booting Linux -------------- - -Place a linux uImage in the TFTP disk area too. - - tftp 1000000 uImage.8544 - tftp 900000 mpc8544ds.dtb - bootm 1000000 - 900000 - -Watch your ethact, netdev and bootargs U-Boot environment variables. -You may want to do something like this too: - - setenv ethact eTSEC3 - setenv netdev eth1 diff --git a/board/freescale/mpc8544ds/ddr.c b/board/freescale/mpc8544ds/ddr.c deleted file mode 100644 index c4d985347b..0000000000 --- a/board/freescale/mpc8544ds/ddr.c +++ /dev/null @@ -1,56 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2008 Freescale Semiconductor, Inc. - */ - -#include <common.h> - -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for clock adjust: - * - number of chips on bus - * - position of slot - * - DDR1 vs. DDR2? - * - ??? - * - * This needs to be determined on a board-by-board basis. - * 0110 3/4 cycle late - * 0111 7/8 cycle late - */ - popts->clk_adjust = 7; - - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 10; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; - - /* 2T timing enable */ - popts->twot_en = 1; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/freescale/mpc8544ds/law.c b/board/freescale/mpc8544ds/law.c deleted file mode 100644 index 52cec7fbb5..0000000000 --- a/board/freescale/mpc8544ds/law.c +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2008, 2010 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_LBC_NONCACHE_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c deleted file mode 100644 index 30ed708365..0000000000 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ /dev/null @@ -1,321 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2007,2009-2010 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <command.h> -#include <init.h> -#include <net.h> -#include <pci.h> -#include <asm/processor.h> -#include <asm/mmu.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_pci.h> -#include <fsl_ddr_sdram.h> -#include <asm/fsl_serdes.h> -#include <asm/io.h> -#include <miiphy.h> -#include <linux/libfdt.h> -#include <fdt_support.h> -#include <fsl_mdio.h> -#include <tsec.h> -#include <netdev.h> - -#include "../common/sgmii_riser.h" - -int checkboard (void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); - u8 vboot; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - if ((uint)&gur->porpllsr != 0xe00e0000) { - printf("immap size error %lx\n",(ulong)&gur->porpllsr); - } - printf ("Board: MPC8544DS, Sys ID: 0x%02x, " - "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", - in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), - in_8(pixis_base + PIXIS_PVER)); - - vboot = in_8(pixis_base + PIXIS_VBOOT); - if (vboot & PIXIS_VBOOT_FMAP) - printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6)); - else - puts ("Promjet\n"); - - lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ - lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ - ecm->eedr = 0xffffffff; /* Clear ecm errors */ - ecm->eeer = 0xffffffff; /* Enable ecm errors */ - - return 0; -} - -#ifdef CONFIG_PCI1 -static struct pci_controller pci1_hose; -#endif - -#ifdef CONFIG_PCIE3 -static struct pci_controller pcie3_hose; -#endif - -void pci_init_board(void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - struct fsl_pci_info pci_info; - u32 devdisr, pordevsr, io_sel; - u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; - int first_free_busno = 0; - - int pcie_ep, pcie_configured; - - devdisr = in_be32(&gur->devdisr); - pordevsr = in_be32(&gur->pordevsr); - porpllsr = in_be32(&gur->porpllsr); - io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - - debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); - - puts("\n"); - -#ifdef CONFIG_PCIE3 - pcie_configured = is_serdes_configured(PCIE3); - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ - /* contains both PCIE3 MEM & IO space */ - set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M, - LAW_TRGT_IF_PCIE_3); - SET_STD_PCIE_INFO(pci_info, 3); - pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info.regs); - - /* outbound memory */ - pci_set_region(&pcie3_hose.regions[0], - CONFIG_SYS_PCIE3_MEM_BUS2, - CONFIG_SYS_PCIE3_MEM_PHYS2, - CONFIG_SYS_PCIE3_MEM_SIZE2, - PCI_REGION_MEM); - - pcie3_hose.region_count = 1; - - printf("PCIE3: connected to ULI as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info.regs); - first_free_busno = fsl_pci_init_port(&pci_info, - &pcie3_hose, first_free_busno); - - /* - * Activate ULI1575 legacy chip by performing a fake - * memory access. Needed to make ULI RTC work. - */ - in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS); - } else { - printf("PCIE3: disabled\n"); - } - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ -#endif - -#ifdef CONFIG_PCIE1 - SET_STD_PCIE_INFO(pci_info, 1); - first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE1, &pci_info); -#else - setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */ -#endif - -#ifdef CONFIG_PCIE2 - SET_STD_PCIE_INFO(pci_info, 2); - first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE2, &pci_info); -#else - setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */ -#endif - -#ifdef CONFIG_PCI1 - pci_speed = 66666000; - pci_32 = 1; - pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; - pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; - - if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { - SET_STD_PCI_INFO(pci_info, 1); - set_next_law(pci_info.mem_phys, - law_size_bits(pci_info.mem_size), pci_info.law); - set_next_law(pci_info.io_phys, - law_size_bits(pci_info.io_size), pci_info.law); - - pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); - printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", - (pci_32) ? 32 : 64, - (pci_speed == 33333000) ? "33" : - (pci_speed == 66666000) ? "66" : "unknown", - pci_clk_sel ? "sync" : "async", - pci_agent ? "agent" : "host", - pci_arb ? "arbiter" : "external-arbiter", - pci_info.regs); - - first_free_busno = fsl_pci_init_port(&pci_info, - &pci1_hose, first_free_busno); - } else { - printf("PCI: disabled\n"); - } - - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ -#endif -} - -int last_stage_init(void) -{ - return 0; -} - - -unsigned long -get_board_sys_clk(ulong dummy) -{ - u8 i, go_bit, rd_clks; - ulong val = 0; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - go_bit = in_8(pixis_base + PIXIS_VCTL); - go_bit &= 0x01; - - rd_clks = in_8(pixis_base + PIXIS_VCFGEN0); - rd_clks &= 0x1C; - - /* - * Only if both go bit and the SCLK bit in VCFGEN0 are set - * should we be using the AUX register. Remember, we also set the - * GO bit to boot from the alternate bank on the on-board flash - */ - - if (go_bit) { - if (rd_clks == 0x1c) - i = in_8(pixis_base + PIXIS_AUX); - else - i = in_8(pixis_base + PIXIS_SPD); - } else { - i = in_8(pixis_base + PIXIS_SPD); - } - - i &= 0x07; - - switch (i) { - case 0: - val = 33333333; - break; - case 1: - val = 40000000; - break; - case 2: - val = 50000000; - break; - case 3: - val = 66666666; - break; - case 4: - val = 83000000; - break; - case 5: - val = 100000000; - break; - case 6: - val = 133333333; - break; - case 7: - val = 166666666; - break; - } - - return val; -} - - -#define MIIM_CIS8204_SLED_CON 0x1b -#define MIIM_CIS8204_SLEDCON_INIT 0x1115 -/* - * Hack to write all 4 PHYs with the LED values - */ -int board_phy_config(struct phy_device *phydev) -{ - static int do_once; - uint phyid; - struct mii_dev *bus = phydev->bus; - - if (phydev->drv->config) - phydev->drv->config(phydev); - if (do_once) - return 0; - - for (phyid = 0; phyid < 4; phyid++) - bus->write(bus, phyid, MDIO_DEVAD_NONE, MIIM_CIS8204_SLED_CON, - MIIM_CIS8204_SLEDCON_INIT); - - do_once = 1; - - return 0; -} - - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_TSEC_ENET - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[2]; - int num = 0; - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - if (is_serdes_configured(SGMII_TSEC1)) { - puts("eTSEC1 is in sgmii mode.\n"); - tsec_info[num].flags |= TSEC_SGMII; - } - num++; -#endif -#ifdef CONFIG_TSEC3 - SET_STD_TSEC_INFO(tsec_info[num], 3); - if (is_serdes_configured(SGMII_TSEC3)) { - puts("eTSEC3 is in sgmii mode.\n"); - tsec_info[num].flags |= TSEC_SGMII; - } - num++; -#endif - - if (!num) { - printf("No TSECs initialized\n"); - - return 0; - } - - if (is_serdes_configured(SGMII_TSEC1) || - is_serdes_configured(SGMII_TSEC3)) { - fsl_sgmii_riser_init(tsec_info, num); - } - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - fsl_pq_mdio_init(bis, &mdio_info); - - tsec_eth_init(bis, tsec_info, num); -#endif - return pci_eth_init(bis); -} - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - ft_cpu_setup(blob, bd); - - FT_FSL_PCI_SETUP; - -#ifdef CONFIG_FSL_SGMII_RISER - fsl_sgmii_riser_fdt_fixup(blob); -#endif - - return 0; -} -#endif diff --git a/board/freescale/mpc8544ds/tlb.c b/board/freescale/mpc8544ds/tlb.c deleted file mode 100644 index 7bd462934a..0000000000 --- a/board/freescale/mpc8544ds/tlb.c +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - /* - * TLB 0: 64M Non-cacheable, guarded - * 0xfc000000 64M Covers FLASH at 0xFE800000 and 0xFF800000 - * Out of reset this entry is only 4K. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_BOOT_BLOCK, CONFIG_SYS_BOOT_BLOCK, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_64M, 1), - /* - * TLB 1: 1G Non-cacheable, guarded - * 0x80000000 1G PCIE 8,9,a,b - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE_VIRT, CONFIG_SYS_PCIE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_1G, 1), - - /* - * TLB 2: 256M Non-cacheable, guarded - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT, CONFIG_SYS_PCI_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 3: 256M Non-cacheable, guarded - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT + 0x10000000, CONFIG_SYS_PCI_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 4: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe100_0000 255M PCI IO range - */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xf8000000 64M PIXIS 0xF8000000 - 0xFBFFFFFF - */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_NONCACHE_BASE, CONFIG_SYS_LBC_NONCACHE_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_64M, 1), -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8572ds/Kconfig b/board/freescale/mpc8572ds/Kconfig deleted file mode 100644 index 38132cf3fe..0000000000 --- a/board/freescale/mpc8572ds/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC8572DS - -config SYS_BOARD - default "mpc8572ds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8572DS" - -endif diff --git a/board/freescale/mpc8572ds/MAINTAINERS b/board/freescale/mpc8572ds/MAINTAINERS deleted file mode 100644 index d7e9b1f41f..0000000000 --- a/board/freescale/mpc8572ds/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -MPC8572DS BOARD -M: Priyanka Jain <priyanka.jain@nxp.com> -S: Maintained -F: board/freescale/mpc8572ds/ -F: include/configs/MPC8572DS.h -F: configs/MPC8572DS_defconfig -F: configs/MPC8572DS_36BIT_defconfig diff --git a/board/freescale/mpc8572ds/Makefile b/board/freescale/mpc8572ds/Makefile deleted file mode 100644 index 5318e3be72..0000000000 --- a/board/freescale/mpc8572ds/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2007 Freescale Semiconductor, Inc. -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y += mpc8572ds.o -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/mpc8572ds/README b/board/freescale/mpc8572ds/README deleted file mode 100644 index f1ffdd1730..0000000000 --- a/board/freescale/mpc8572ds/README +++ /dev/null @@ -1,166 +0,0 @@ -Overview --------- -MPC8572DS is a high-performance computing, evaluation and development platform -supporting the mpc8572 PowerTM processor. - -Building U-Boot ------------ - make MPC8572DS_config - make - -Flash Banks ------------ -MPC8572DS board has two flash banks. They are both present on boot, but their -locations can be swapped using the dip-switch SW9[1:2]. - -Booting is always from the boot bank at 0xec00_0000. - - -Memory Map ----------- - -0xe800_0000 - 0xebff_ffff Alternate bank 64MB -0xec00_0000 - 0xefff_ffff Boot bank 64MB - -0xebf8_0000 - 0xebff_ffff Alternate U-Boot address 512KB -0xeff8_0000 - 0xefff_ffff Boot U-Boot address 512KB - - -Flashing Images ---------------- - -To place a new U-Boot image in the alternate flash bank and then reset with that - new image temporarily, use this: - - tftp 1000000 u-boot.bin - erase ebf80000 ebffffff - cp.b 1000000 ebf80000 80000 - pixis_reset altbank - - -To program the image in the boot flash bank: - - tftp 1000000 u-boot.bin - protect off all - erase eff80000 ffffffff - cp.b 1000000 eff80000 80000 - - -The pixis_reset command ------------------------ -The command - "pixis_reset", is introduced to reset mpc8572ds board -using the FPGA sequencer. When the board restarts, it has the option -of using either the current or alternate flash bank as the boot -image, with or without the watchdog timer enabled, and finally with -or without frequency changes. - -Usage is; - - pixis_reset - pixis_reset altbank - pixis_reset altbank wd - pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> - pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> - -Examples: - - /* reset to current bank, like "reset" command */ - pixis_reset - - /* reset board but use the to alternate flash bank */ - pixis_reset altbank - - -Using the Device Tree Source File ---------------------------------- -To create the DTB (Device Tree Binary) image file, -use a command similar to this: - - dtc -b 0 -f -I dts -O dtb mpc8572ds.dts > mpc8572ds.dtb - -Likely, that .dts file will come from here; - - linux-2.6/arch/powerpc/boot/dts/mpc8572ds.dts - - -Booting Linux -------------- - -Place a linux uImage in the TFTP disk area. - - tftp 1000000 uImage.8572 - tftp c00000 mpc8572ds.dtb - bootm 1000000 - c00000 - - -Implementing AMP(Asymmetric MultiProcessing) -------------- -1. Build kernel image for core0: - - a. $ make 85xx/mpc8572_ds_defconfig - - b. $ make menuconfig - - un-select "Processor support"->"Symetric multi-processing support" - - c. $ make uImage - - d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0 - -2. Build kernel image for core1: - - a. $ make 85xx/mpc8572_ds_defconfig - - b. $ make menuconfig - - Un-select "Processor support"->"Symetric multi-processing support" - - Select "Advanced setup" -> " Prompt for advanced kernel - configuration options" - - Select "Set physical address where the kernel is loaded" and - set it to 0x20000000, assuming core1 will start from 512MB. - - Select "Set custom page offset address" - - Select "Set custom kernel base address" - - Select "Set maximum low memory" - - "Exit" and save the selection. - - c. $ make uImage - - d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1 - -3. Create dtb for core0: - - $ dtc -I dts -O dtb -f -b 0 arch/powerpc/boot/dts/mpc8572ds_core0.dts > /tftpboot/mpc8572ds_core0.dtb - -4. Create dtb for core1: - - $ dtc -I dts -O dtb -f -b 1 arch/powerpc/boot/dts/mpc8572ds_core1.dts > /tftpboot/mpc8572ds_core1.dtb - -5. Bring up two cores separately: - - a. Power on the board, under U-Boot prompt: - => setenv <serverip> - => setenv <ipaddr> - => setenv bootargs root=/dev/ram rw console=ttyS0,115200 - b. Bring up core1's kernel first: - => setenv bootm_low 0x20000000 - => setenv bootm_size 0x10000000 - => tftp 21000000 8572/uImage.core1 - => tftp 22000000 8572/ramdiskfile - => tftp 20c00000 8572/mpc8572ds_core1.dtb - => interrupts off - => bootm start 21000000 22000000 20c00000 - => bootm loados - => bootm ramdisk - => bootm fdt - => fdt boardsetup - => fdt chosen $initrd_start $initrd_end - => bootm prep - => cpu 1 release $bootm_low - $fdtaddr - - c. Bring up core0's kernel(on the same U-Boot console): - => setenv bootm_low 0 - => setenv bootm_size 0x20000000 - => tftp 1000000 8572/uImage.core0 - => tftp 2000000 8572/ramdiskfile - => tftp c00000 8572/mpc8572ds_core0.dtb - => bootm 1000000 2000000 c00000 - -Please note only core0 will run U-Boot, core1 starts kernel directly after -"cpu release" command is issued. diff --git a/board/freescale/mpc8572ds/ddr.c b/board/freescale/mpc8572ds/ddr.c deleted file mode 100644 index 11ca08d1a0..0000000000 --- a/board/freescale/mpc8572ds/ddr.c +++ /dev/null @@ -1,166 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2008 Freescale Semiconductor, Inc. - */ - -#include <common.h> - -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> - -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 clk_adjust; - u32 cpo; - u32 write_data_delay; - u32 force_2t; -}; - -/* - * This table contains all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - * - * For DDR2 DIMM, all combinations of clk_adjust and write_data_delay have been - * tested. For RDIMM, clk_adjust = 4 and write_data_delay = 3 is optimized for - * all clocks from 400MT/s to 800MT/s, verified with Kingston KVR800D2D8P6/2G. - * For UDIMM, clk_adjust = 8 and write_delay = 5 is optimized for all clocks - * from 400MT/s to 800MT/s, verified with Micron MT18HTF25672AY-800E1. - * - * CPO value doesn't matter if workaround for errata 111 and 134 enabled. - */ -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| clk| cpo|wrdata|2T - * ranks| mhz|adjst| | delay| - */ - {2, 333, 8, 7, 5, 0}, - {2, 400, 8, 9, 5, 0}, - {2, 549, 8, 11, 5, 0}, - {2, 680, 8, 10, 5, 0}, - {2, 850, 8, 12, 5, 1}, - {1, 333, 6, 7, 3, 0}, - {1, 400, 6, 9, 3, 0}, - {1, 549, 6, 11, 3, 0}, - {1, 680, 1, 10, 5, 0}, - {1, 850, 1, 12, 5, 0}, - {} -}; - -static const struct board_specific_parameters udimm1[] = { - /* - * memory controller 1 - * num| hi| clk| cpo|wrdata|2T - * ranks| mhz|adjst| | delay| - */ - {2, 333, 8, 7, 5, 0}, - {2, 400, 8, 9, 5, 0}, - {2, 549, 8, 11, 5, 0}, - {2, 680, 8, 11, 5, 0}, - {2, 850, 8, 13, 5, 1}, - {1, 333, 6, 7, 3, 0}, - {1, 400, 6, 9, 3, 0}, - {1, 549, 6, 11, 3, 0}, - {1, 680, 1, 11, 6, 0}, - {1, 850, 1, 13, 6, 0}, - {} -}; - -static const struct board_specific_parameters *udimms[] = { - udimm0, - udimm1, -}; - -static const struct board_specific_parameters rdimm0[] = { - /* - * memory controller 0 - * num| hi| clk| cpo|wrdata|2T - * ranks| mhz|adjst| | delay| - */ - {2, 333, 4, 7, 3, 0}, - {2, 400, 4, 9, 3, 0}, - {2, 549, 4, 11, 3, 0}, - {2, 680, 4, 10, 3, 0}, - {2, 850, 4, 12, 3, 1}, - {} -}; - -static const struct board_specific_parameters rdimm1[] = { - /* - * memory controller 1 - * num| hi| clk| cpo|wrdata|2T - * ranks| mhz|adjst| | delay| - */ - {2, 333, 4, 7, 3, 0}, - {2, 400, 4, 9, 3, 0}, - {2, 549, 4, 11, 3, 0}, - {2, 680, 4, 11, 3, 0}, - {2, 850, 4, 13, 3, 1}, - {} -}; - -static const struct board_specific_parameters *rdimms[] = { - rdimm0, - rdimm1, -}; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - - if (ctrl_num > 1) { - printf("Wrong parameter for controller number %d", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - if (popts->registered_dimm_en) - pbsp = rdimms[ctrl_num]; - else - pbsp = udimms[ctrl_num]; - - /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = - pbsp->write_data_delay; - popts->twot_en = pbsp->force_2t; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found " - "for data rate %lu MT/s!\n" - "Trying to use the highest speed (%u) parameters\n", - ddr_freq, pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp->clk_adjust; - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = pbsp->write_data_delay; - popts->twot_en = pbsp->force_2t; - } else { - panic("DIMM is not supported by this board"); - } - -found: - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/freescale/mpc8572ds/law.c b/board/freescale/mpc8572ds/law.c deleted file mode 100644 index 10d1572c5d..0000000000 --- a/board/freescale/mpc8572ds/law.c +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2008, 2010 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c deleted file mode 100644 index 97e73533ab..0000000000 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ /dev/null @@ -1,260 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2007-2011 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <command.h> -#include <env.h> -#include <image.h> -#include <init.h> -#include <log.h> -#include <net.h> -#include <pci.h> -#include <asm/processor.h> -#include <asm/mmu.h> -#include <asm/cache.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_pci.h> -#include <fsl_ddr_sdram.h> -#include <asm/io.h> -#include <asm/fsl_serdes.h> -#include <miiphy.h> -#include <linux/delay.h> -#include <linux/libfdt.h> -#include <fdt_support.h> -#include <tsec.h> -#include <fsl_mdio.h> -#include <netdev.h> - -#include "../common/sgmii_riser.h" - -int checkboard (void) -{ - u8 vboot; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - printf("Board: MPC8572DS Sys ID: 0x%02x, " - "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", - in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), - in_8(pixis_base + PIXIS_PVER)); - - vboot = in_8(pixis_base + PIXIS_VBOOT); - switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) { - case PIXIS_VBOOT_LBMAP_NOR0: - puts ("vBank: 0\n"); - break; - case PIXIS_VBOOT_LBMAP_PJET: - puts ("Promjet\n"); - break; - case PIXIS_VBOOT_LBMAP_NAND: - puts ("NAND\n"); - break; - case PIXIS_VBOOT_LBMAP_NOR1: - puts ("vBank: 1\n"); - break; - } - - return 0; -} - - -#if !defined(CONFIG_SPD_EEPROM) -/* - * Fixed sdram init -- doesn't use serial presence detect. - */ - -phys_size_t fixed_sdram (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - struct ccsr_ddr __iomem *ddr = &immap->im_ddr; - uint d_init; - - ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; - ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; - - ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; - ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; - ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; - ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; - ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; - ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; - -#if defined (CONFIG_DDR_ECC) - ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; - ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; - ddr->err_sbe = CONFIG_SYS_DDR_SBE; -#endif - asm("sync;isync"); - - udelay(500); - - ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; - -#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - d_init = 1; - debug("DDR - 1st controller: memory initializing\n"); - /* - * Poll until memory is initialized. - * 512 Meg at 400 might hit this 200 times or so. - */ - while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { - udelay(1000); - } - debug("DDR: memory initialized\n\n"); - asm("sync; isync"); - udelay(500); -#endif - - return 512 * 1024 * 1024; -} - -#endif - -#ifdef CONFIG_PCI -void pci_init_board(void) -{ - struct pci_controller *hose; - - fsl_pcie_init_board(0); - - hose = find_hose_by_cfg_addr((void *)(CONFIG_SYS_PCIE3_ADDR)); - - if (hose) { - u32 temp32; - u8 uli_busno = hose->first_busno + 2; - - /* - * Activate ULI1575 legacy chip by performing a fake - * memory access. Needed to make ULI RTC work. - * Device 1d has the first on-board memory BAR. - */ - pci_hose_read_config_dword(hose, PCI_BDF(uli_busno, 0x1d, 0), - PCI_BASE_ADDRESS_1, &temp32); - - if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) { - void *p = pci_mem_to_virt(PCI_BDF(uli_busno, 0x1d, 0), - temp32, 4, 0); - debug(" uli1572 read to %p\n", p); - in_be32(p); - } - } -} -#endif - -int board_early_init_r(void) -{ - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - int flash_esel = find_tlb_idx((void *)flashbase, 1); - - /* - * Remap Boot flash + PROMJET region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - if (flash_esel == -1) { - /* very unlikely unless something is messed up */ - puts("Error: Could not find TLB for FLASH BASE\n"); - flash_esel = 2; /* give our best effort to continue */ - } else { - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); - } - - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ - 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ - - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_TSEC_ENET - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[4]; - int num = 0; - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - if (is_serdes_configured(SGMII_TSEC1)) { - puts("eTSEC1 is in sgmii mode.\n"); - tsec_info[num].flags |= TSEC_SGMII; - } - num++; -#endif -#ifdef CONFIG_TSEC2 - SET_STD_TSEC_INFO(tsec_info[num], 2); - if (is_serdes_configured(SGMII_TSEC2)) { - puts("eTSEC2 is in sgmii mode.\n"); - tsec_info[num].flags |= TSEC_SGMII; - } - num++; -#endif -#ifdef CONFIG_TSEC3 - SET_STD_TSEC_INFO(tsec_info[num], 3); - if (is_serdes_configured(SGMII_TSEC3)) { - puts("eTSEC3 is in sgmii mode.\n"); - tsec_info[num].flags |= TSEC_SGMII; - } - num++; -#endif -#ifdef CONFIG_TSEC4 - SET_STD_TSEC_INFO(tsec_info[num], 4); - if (is_serdes_configured(SGMII_TSEC4)) { - puts("eTSEC4 is in sgmii mode.\n"); - tsec_info[num].flags |= TSEC_SGMII; - } - num++; -#endif - - if (!num) { - printf("No TSECs initialized\n"); - - return 0; - } - -#ifdef CONFIG_FSL_SGMII_RISER - fsl_sgmii_riser_init(tsec_info, num); -#endif - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - fsl_pq_mdio_init(bis, &mdio_info); - - tsec_eth_init(bis, tsec_info, num); -#endif - - return pci_eth_init(bis); -} - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = env_get_bootm_low(); - size = env_get_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - - FT_FSL_PCI_SETUP; - -#ifdef CONFIG_FSL_SGMII_RISER - fsl_sgmii_riser_fdt_fixup(blob); -#endif - - return 0; -} -#endif diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c deleted file mode 100644 index 99b136b042..0000000000 --- a/board/freescale/mpc8572ds/tlb.c +++ /dev/null @@ -1,87 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2008-2010 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 1), - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_1M, 1), - - /* W**G* - Flash/promjet, localbus */ - /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - -#ifndef CONFIG_NAND_SPL - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_1G, 1), - - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_256K, 1), -#endif - - /* *I*G - NAND */ - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_1M, 1), - - SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_4K, 1), - -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) - /* *I*G - L2SRAM */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, - CONFIG_SYS_INIT_L2_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 9, BOOKE_PAGESZ_256K, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, - CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_256K, 1), -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8610hpcd/Kconfig b/board/freescale/mpc8610hpcd/Kconfig deleted file mode 100644 index 8f713beaa8..0000000000 --- a/board/freescale/mpc8610hpcd/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC8610HPCD - -config SYS_BOARD - default "mpc8610hpcd" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8610HPCD" - -endif diff --git a/board/freescale/mpc8610hpcd/MAINTAINERS b/board/freescale/mpc8610hpcd/MAINTAINERS deleted file mode 100644 index 9b1e0cd4e5..0000000000 --- a/board/freescale/mpc8610hpcd/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MPC8610HPCD BOARD -M: Priyanka Jain <priyanka.jain@nxp.com> -S: Maintained -F: board/freescale/mpc8610hpcd/ -F: include/configs/MPC8610HPCD.h -F: configs/MPC8610HPCD_defconfig diff --git a/board/freescale/mpc8610hpcd/Makefile b/board/freescale/mpc8610hpcd/Makefile deleted file mode 100644 index 3a02a06416..0000000000 --- a/board/freescale/mpc8610hpcd/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# Copyright 2007 Freescale Semiconductor, Inc. - -obj-y += mpc8610hpcd.o -obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o -obj-y += law.o -obj-$(CONFIG_FSL_DIU_FB) += mpc8610hpcd_diu.o diff --git a/board/freescale/mpc8610hpcd/README b/board/freescale/mpc8610hpcd/README deleted file mode 100644 index 066e625d48..0000000000 --- a/board/freescale/mpc8610hpcd/README +++ /dev/null @@ -1,73 +0,0 @@ -Freescale MPC8610HPCD board -=========================== - - -Building U-Boot ---------------- - - $ make MPC8610HPCD_config - Configuring for MPC8610HPCD board... - - $ make - - -Flashing U-Boot ---------------- -The flash is 128M starting at 0xF800_0000. - -The alternate image is at 0xFBF0_0000 -The boot image is at 0xFFF0_0000. - - -To Flash U-Boot into the booting bank: - - tftp 1000000 u-boot.bin - protect off all - erase fff00000 +$filesize - cp.b 1000000 fff00000 $filesize - - -To Flash U-Boot into the alternate bank - - tftp 1000000 u-boot.bin - erase fbf00000 +$filesize - cp.b 1000000 fbf00000 $filesize - - -pixis_reset command -------------------- -A new command, "pixis_reset", is introduced to reset mpc8610hpcd board -using the FPGA sequencer. When the board restarts, it has the option -of using either the current or alternate flash bank as the boot -image, with or without the watchdog timer enabled, and finally with -or without frequency changes. - -Usage is; - - pixis_reset - pixis_reset altbank - pixis_reset altbank wd - pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> - pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> - -Examples; - - /* reset to current bank, like "reset" command */ - pixis_reset - - /* reset board but use the to alternate flash bank */ - pixis_reset altbank - - /* reset board, use alternate flash bank with watchdog timer enabled*/ - pixis_reset altbank wd - - /* reset board to alternate bank with frequency changed. - * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio - */ - pixis-reset altbank cf 40 2.5 10 - - -DIP Switch Settings -------------------- -To manually switch the flash banks using the DIP switch -settings, toggle both SW6:1 and SW6:2. diff --git a/board/freescale/mpc8610hpcd/ddr.c b/board/freescale/mpc8610hpcd/ddr.c deleted file mode 100644 index c4d985347b..0000000000 --- a/board/freescale/mpc8610hpcd/ddr.c +++ /dev/null @@ -1,56 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2008 Freescale Semiconductor, Inc. - */ - -#include <common.h> - -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for clock adjust: - * - number of chips on bus - * - position of slot - * - DDR1 vs. DDR2? - * - ??? - * - * This needs to be determined on a board-by-board basis. - * 0110 3/4 cycle late - * 0111 7/8 cycle late - */ - popts->clk_adjust = 7; - - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 10; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; - - /* 2T timing enable */ - popts->twot_en = 1; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/freescale/mpc8610hpcd/law.c b/board/freescale/mpc8610hpcd/law.c deleted file mode 100644 index 7bf5e6815d..0000000000 --- a/board/freescale/mpc8610hpcd/law.c +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2008,2010 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -struct law_entry law_table[] = { -#if !defined(CONFIG_SPD_EEPROM) - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR_1), -#endif - SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c deleted file mode 100644 index 74b0e45b4f..0000000000 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ /dev/null @@ -1,336 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2007,2009-2011 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <command.h> -#include <init.h> -#include <log.h> -#include <net.h> -#include <pci.h> -#include <asm/global_data.h> -#include <asm/processor.h> -#include <asm/immap_86xx.h> -#include <asm/fsl_pci.h> -#include <fsl_ddr_sdram.h> -#include <asm/fsl_serdes.h> -#include <i2c.h> -#include <asm/io.h> -#include <linux/delay.h> -#include <linux/libfdt.h> -#include <fdt_support.h> -#include <spd_sdram.h> -#include <netdev.h> - -DECLARE_GLOBAL_DATA_PTR; - -void sdram_init(void); -phys_size_t fixed_sdram(void); -int mpc8610hpcd_diu_init(void); - - -/* called before any console output */ -int board_early_init_f(void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; - - gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */ - - return 0; -} - -int misc_init_r(void) -{ - u8 tmp_val, version; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - /*Do not use 8259PIC*/ - tmp_val = in_8(pixis_base + PIXIS_BRDCFG0); - out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80); - - /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/ - version = in_8(pixis_base + PIXIS_PVER); - if(version >= 0x07) { - tmp_val = in_8(pixis_base + PIXIS_BRDCFG0); - out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf); - } - - /* Using this for DIU init before the driver in linux takes over - * Enable the TFP410 Encoder (I2C address 0x38) - */ - - tmp_val = 0xBF; - i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); - /* Verify if enabled */ - tmp_val = 0; - i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); - debug("DVI Encoder Read: 0x%02x\n", tmp_val); - - tmp_val = 0x10; - i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); - /* Verify if enabled */ - tmp_val = 0; - i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); - debug("DVI Encoder Read: 0x%02x\n", tmp_val); - - return 0; -} - -int checkboard(void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - printf ("Board: MPC8610HPCD, Sys ID: 0x%02x, " - "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", - in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), - in_8(pixis_base + PIXIS_PVER)); - - /* - * The MPC8610 HPCD workbook says that LBMAP=11 is the "normal" boot - * bank and LBMAP=00 is the alternate bank. However, the pixis - * altbank code can only set bits, not clear them, so we treat 00 as - * the normal bank and 11 as the alternate. - */ - switch (in_8(pixis_base + PIXIS_VBOOT) & 0xC0) { - case 0: - puts("vBank: Standard\n"); - break; - case 0x40: - puts("Promjet\n"); - break; - case 0x80: - puts("NAND\n"); - break; - case 0xC0: - puts("vBank: Alternate\n"); - break; - } - - mcm->abcr |= 0x00010000; /* 0 */ - mcm->hpmr3 = 0x80000008; /* 4c */ - mcm->hpmr0 = 0; - mcm->hpmr1 = 0; - mcm->hpmr2 = 0; - mcm->hpmr4 = 0; - mcm->hpmr5 = 0; - - return 0; -} - - -int dram_init(void) -{ - phys_size_t dram_size = 0; - -#if defined(CONFIG_SPD_EEPROM) - dram_size = fsl_ddr_sdram(); -#else - dram_size = fixed_sdram(); -#endif - - setup_ddr_bat(dram_size); - - debug(" DDR: "); - gd->ram_size = dram_size; - - return 0; -} - - -#if !defined(CONFIG_SPD_EEPROM) -/* - * Fixed sdram init -- doesn't use serial presence detect. - */ - -phys_size_t fixed_sdram(void) -{ -#if !defined(CONFIG_SYS_RAMBOOT) - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - struct ccsr_ddr __iomem *ddr = &immap->im_ddr1; - uint d_init; - - ddr->cs0_bnds = 0x0000001f; - ddr->cs0_config = 0x80010202; - - ddr->timing_cfg_3 = 0x00000000; - ddr->timing_cfg_0 = 0x00260802; - ddr->timing_cfg_1 = 0x3935d322; - ddr->timing_cfg_2 = 0x14904cc8; - ddr->sdram_mode = 0x00480432; - ddr->sdram_mode_2 = 0x00000000; - ddr->sdram_interval = 0x06180fff; /* 0x06180100; */ - ddr->sdram_data_init = 0xDEADBEEF; - ddr->sdram_clk_cntl = 0x03800000; - ddr->sdram_cfg_2 = 0x04400010; - -#if defined(CONFIG_DDR_ECC) - ddr->err_int_en = 0x0000000d; - ddr->err_disable = 0x00000000; - ddr->err_sbe = 0x00010000; -#endif - asm("sync;isync"); - - udelay(500); - - ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/ - - -#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - d_init = 1; - debug("DDR - 1st controller: memory initializing\n"); - /* - * Poll until memory is initialized. - * 512 Meg at 400 might hit this 200 times or so. - */ - while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) - udelay(1000); - - debug("DDR: memory initialized\n\n"); - asm("sync; isync"); - udelay(500); -#endif - - return 512 * 1024 * 1024; -#endif - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; -} - -#endif - -#if defined(CONFIG_PCI) -/* - * Initialize PCI Devices, report devices found. - */ - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_fsl86xxads_config_table[] = { - {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} }, - {} -}; -#endif - - -static struct pci_controller pci1_hose; -#endif /* CONFIG_PCI */ - -void pci_init_board(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; - volatile ccsr_gur_t *gur = &immap->im_gur; - struct fsl_pci_info pci_info; - u32 devdisr; - int first_free_busno; - int pci_agent; - - devdisr = in_be32(&gur->devdisr); - - first_free_busno = fsl_pcie_init_board(0); - -#ifdef CONFIG_PCI1 - if (!(devdisr & MPC86xx_DEVDISR_PCI1)) { - SET_STD_PCI_INFO(pci_info, 1); - set_next_law(pci_info.mem_phys, - law_size_bits(pci_info.mem_size), pci_info.law); - set_next_law(pci_info.io_phys, - law_size_bits(pci_info.io_size), pci_info.law); - - pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); - printf("PCI: connected to PCI slots as %s" \ - " (base address %lx)\n", - pci_agent ? "Agent" : "Host", - pci_info.regs); -#ifndef CONFIG_PCI_PNP - pci1_hose.config_table = pci_mpc86xxcts_config_table; -#endif - first_free_busno = fsl_pci_init_port(&pci_info, - &pci1_hose, first_free_busno); - } else { - printf("PCI: disabled\n"); - } - - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */ -#endif - - fsl_pcie_init_board(first_free_busno); -} - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - ft_cpu_setup(blob, bd); - - FT_FSL_PCI_SETUP; - - return 0; -} -#endif - -/* - * get_board_sys_clk - * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ - */ - -unsigned long -get_board_sys_clk(ulong dummy) -{ - u8 i; - ulong val = 0; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - i = in_8(pixis_base + PIXIS_SPD); - i &= 0x07; - - switch (i) { - case 0: - val = 33333000; - break; - case 1: - val = 39999600; - break; - case 2: - val = 49999500; - break; - case 3: - val = 66666000; - break; - case 4: - val = 83332500; - break; - case 5: - val = 99999000; - break; - case 6: - val = 133332000; - break; - case 7: - val = 166665000; - break; - } - - return val; -} - -int board_eth_init(struct bd_info *bis) -{ - return pci_eth_init(bis); -} - -void board_reset(void) -{ - u8 *pixis_base = (u8 *)PIXIS_BASE; - - out_8(pixis_base + PIXIS_RST, 0); - - while (1) - ; -} diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c deleted file mode 100644 index 9b96d0d33f..0000000000 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2007-2011 Freescale Semiconductor, Inc. - * Authors: York Sun <yorksun@freescale.com> - * Timur Tabi <timur@freescale.com> - * - * FSL DIU Framebuffer driver - */ - -#include <common.h> -#include <clock_legacy.h> -#include <command.h> -#include <log.h> -#include <asm/io.h> -#include <fsl_diu_fb.h> -#include "../common/pixis.h" - -#define PX_BRDCFG0_DLINK 0x10 -#define PX_BRDCFG0_DVISEL 0x08 - -void diu_set_pixel_clock(unsigned int pixclock) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; - volatile unsigned int *guts_clkdvdr = &gur->clkdvdr; - unsigned long speed_ccb, temp, pixval; - - speed_ccb = get_bus_freq(0); - temp = 1000000000/pixclock; - temp *= 1000; - pixval = speed_ccb / temp; - debug("DIU pixval = %lu\n", pixval); - - /* Modify PXCLK in GUTS CLKDVDR */ - debug("DIU: Current value of CLKDVDR = 0x%08x\n", *guts_clkdvdr); - temp = *guts_clkdvdr & 0x2000FFFF; - *guts_clkdvdr = temp; /* turn off clock */ - *guts_clkdvdr = temp | 0x80000000 | ((pixval & 0x1F) << 16); - debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *guts_clkdvdr); -} - -int platform_diu_init(unsigned int xres, unsigned int yres, const char *port) -{ - const char *name; - int gamma_fix = 0; - u32 pixel_format = 0x88883316; - u8 temp; - - temp = in_8(&pixis->brdcfg0); - - if (strncmp(port, "dlvds", 5) == 0) { - /* Dual link LVDS */ - gamma_fix = 1; - temp &= ~(PX_BRDCFG0_DLINK | PX_BRDCFG0_DVISEL); - name = "Dual-Link LVDS"; - } else if (strncmp(port, "lvds", 4) == 0) { - /* Single link LVDS */ - temp = (temp & ~PX_BRDCFG0_DVISEL) | PX_BRDCFG0_DLINK; - name = "Single-Link LVDS"; - } else { - /* DVI */ - if (in_8(&pixis->ver) == 1) /* Board version */ - pixel_format = 0x88882317; - temp |= PX_BRDCFG0_DVISEL; - name = "DVI"; - } - - printf("DIU: Switching to %s monitor @ %ux%u\n", name, xres, yres); - out_8(&pixis->brdcfg0, temp); - - return fsl_diu_init(xres, yres, pixel_format, gamma_fix); -} diff --git a/board/freescale/mpc8641hpcn/Kconfig b/board/freescale/mpc8641hpcn/Kconfig deleted file mode 100644 index ae45d63337..0000000000 --- a/board/freescale/mpc8641hpcn/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC8641HPCN - -config SYS_BOARD - default "mpc8641hpcn" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8641HPCN" - -endif diff --git a/board/freescale/mpc8641hpcn/MAINTAINERS b/board/freescale/mpc8641hpcn/MAINTAINERS deleted file mode 100644 index c957218767..0000000000 --- a/board/freescale/mpc8641hpcn/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -MPC8641HPCN BOARD -M: Priyanka Jain <priyanka.jain@nxp.com> -S: Maintained -F: board/freescale/mpc8641hpcn/ -F: include/configs/MPC8641HPCN.h -F: configs/MPC8641HPCN_defconfig -F: configs/MPC8641HPCN_36BIT_defconfig diff --git a/board/freescale/mpc8641hpcn/Makefile b/board/freescale/mpc8641hpcn/Makefile deleted file mode 100644 index 86b87193dd..0000000000 --- a/board/freescale/mpc8641hpcn/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y += mpc8641hpcn.o -obj-y += law.o -obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o diff --git a/board/freescale/mpc8641hpcn/README b/board/freescale/mpc8641hpcn/README deleted file mode 100644 index 77909a8383..0000000000 --- a/board/freescale/mpc8641hpcn/README +++ /dev/null @@ -1,186 +0,0 @@ -Freescale MPC8641HPCN board -=========================== - -Created 05/24/2006 Haiying Wang -------------------------------- - -1. Building U-Boot ------------------- -The 86xx HPCN code base is known to compile using: - Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3 - - $ make MPC8641HPCN_config - Configuring for MPC8641HPCN board... - - $ make - - -2. Switch and Jumper Setting ----------------------------- -Jumpers: - J14 Pins 1-2 (near plcc32 socket) - -Switches: - SW1(1-5) = 01100 CONFIG_SYS_COREPLL = 01000 :: CORE = 2:1 - 01100 :: CORE = 2.5:1 - 10000 :: CORE = 3:1 - 11100 :: CORE = 3.5:1 - 10100 :: CORE = 4:1 - 01110 :: CORE = 4.5:1 - SW1(6-8) = 001 CONFIG_SYS_SYSCLK = 000 :: SYSCLK = 33MHz - 001 :: SYSCLK = 40MHz - - SW2(1-4) = 1100 CONFIG_SYS_CCBPLL = 0010 :: 2X - 0100 :: 4X - 0110 :: 6X - 1000 :: 8X - 1010 :: 10X - 1100 :: 12X - 1110 :: 14X - 0000 :: 16X - SW2(5-8) = 1110 CONFIG_SYS_BOOTLOC = 1110 :: boot 16-bit localbus - - SW3(1-7) = 0011000 CONFIG_SYS_VID = 0011000 :: VCORE = 1.2V - 0100000 :: VCORE = 1.11V - SW3(8) = 0 VCC_PLAT = 0 :: VCC_PLAT = 1.2V - 1 :: VCC_PLAT = 1.0V - - SW4(1-2) = 11 CONFIG_SYS_HOSTMODE = 11 :: both prots host/root - SW4(3-4) = 11 CONFIG_SYS_BOOTSEQ = 11 :: no boot seq - SW4(5-8) = 0011 CONFIG_SYS_IOPORT = 0011 :: both PEX - - SW5(1) = 1 CONFIG_SYS_FLASHMAP = 1 :: boot from flash - 0 :: boot from PromJet - SW5(2) = 1 CONFIG_SYS_FLASHBANK = 1 :: swap upper/lower - halves (virtual banks) - 0 :: normal - SW5(3) = 0 CONFIG_SYS_FLASHWP = 0 :: not protected - SW5(4) = 0 CONFIG_SYS_PORTDIV = 1 :: 2:1 for PD4 - 1:1 for PD6 - SW5(5-6) = 11 CONFIG_SYS_PIXISOPT = 11 :: s/w determined - SW5(7-8) = 11 CONFIG_SYS_LADOPT = 11 :: s/w determined - - SW6(1) = 1 CONFIG_SYS_CPUBOOT = 1 :: no boot holdoff - SW6(2) = 1 CONFIG_SYS_BOOTADDR = 1 :: no traslation - SW6(3-5) = 000 CONFIG_SYS_REFCLKSEL = 000 :: 100MHZ - SW6(6) = 1 CONFIG_SYS_SERROM_ADDR= 1 :: - SW6(7) = 1 CONFIG_SYS_MEMDEBUG = 1 :: - SW6(8) = 1 CONFIG_SYS_DDRDEBUG = 1 :: - - SW8(1) = 1 ACZ_SYNC = 1 :: 48MHz on TP49 - SW8(2) = 1 ACB_SYNC = 1 :: THRMTRIP disabled - SW8(3) = 1 ACZ_SDOUT = 1 :: p4 mode - SW8(4) = 1 ACB_SDOUT = 1 :: PATA freq. = 133MHz - SW8(5) = 0 SUSLED = 0 :: SouthBridge Mode - SW8(6) = 0 SPREAD = 0 :: REFCLK SSCG Disabled - SW8(7) = 1 ACPWR = 1 :: non-battery - SW8(8) = 0 CONFIG_SYS_IDWP = 0 :: write enable - - -3. Flash U-Boot ---------------- -The flash range 0xEF800000 to 0xEFFFFFFF can be divided into 2 halves. -It is possible to use either half to boot using U-Boot. Switch 5 bit 2 -is used for this purpose. - -0xEF800000 to 0xEFBFFFFF - 4MB -0xEFC00000 to 0xEFFFFFFF - 4MB -When this bit is 0, U-Boot is at 0xEFF00000. -When this bit is 1, U-Boot is at 0xEFB00000. - -Use the above mentioned flash commands to program the other half, and -use switch 5, bit 2 to alternate between the halves. Note: The booting -version of U-Boot will always be at 0xEFF00000. - -To Flash U-Boot into the booting bank (0xEFC00000 - 0xEFFFFFFF): - - tftp 1000000 u-boot.bin - protect off all - erase eff00000 +$filesize - cp.b 1000000 eff00000 $filesize - -or use tftpflash command: - run tftpflash - -To Flash U-Boot into the alternative bank (0xEF800000 - 0xEFBFFFFF): - - tftp 1000000 u-boot.bin - erase efb00000 +$filesize - cp.b 1000000 efb00000 $filesize - - -4. Memory Map -------------- -NOTE: RIO and PCI are mutually exclusive, so they share an address - -For 32-bit U-Boot, devices are mapped so that the virtual address == -the physical address, and the map looks liks this: - - Memory Range Device Size - ------------ ------ ---- - 0x0000_0000 0x7fff_ffff DDR 2G - 0x8000_0000 0x9fff_ffff RIO MEM 512M - 0x8000_0000 0x9fff_ffff PCI1/PEX1 MEM 512M - 0xa000_0000 0xbfff_ffff PCI2/PEX2 MEM 512M - 0xffe0_0000 0xffef_ffff CCSR 1M - 0xffdf_0000 0xffdf_7fff PIXIS 8K - 0xffdf_8000 0xffdf_ffff CF 8K - 0xf840_0000 0xf840_3fff Stack space 32K - 0xffc0_0000 0xffc0_ffff PCI1/PEX1 IO 64K - 0xffc1_0000 0xffc1_ffff PCI2/PEX2 IO 64K - 0xef80_0000 0xefff_ffff Flash 8M - -For 36-bit-enabled U-Boot, the virtual map is the same as for 32-bit. -However, the physical map is altered to reside in 36-bit space, as follows. -Addresses are no longer mapped with VA == PA. All accesses from -software use the VA; the PA is only used for setting up windows -and mappings. Note that with the exception of PCI MEM and RIO, the low - 32 bits are the same as the VA above; only the top 4 bits vary: - - Memory Range Device Size - ------------ ------ ---- - 0x0_0000_0000 0x0_7fff_ffff DDR 2G - 0xc_0000_0000 0xc_1fff_ffff RIO MEM 512M - 0xc_0000_0000 0xc_1fff_ffff PCI1/PEX1 MEM 512M - 0xc_2000_0000 0xc_3fff_ffff PCI2/PEX2 MEM 512M - 0xf_ffe0_0000 0xf_ffef_ffff CCSR 1M - 0xf_ffdf_0000 0xf_ffdf_7fff PIXIS 8K - 0xf_ffdf_8000 0xf_ffdf_ffff CF 8K - 0x0_f840_0000 0xf_f840_3fff Stack space 32K - 0xf_ffc0_0000 0xf_ffc0_ffff PCI1/PEX1 IO 64K - 0xf_ffc1_0000 0xf_ffc1_ffff PCI2/PEX2 IO 64K - 0xf_ef80_0000 0xf_efff_ffff Flash 8M - -5. pixis_reset command --------------------- -A new command, "pixis_reset", is introduced to reset mpc8641hpcn board -using the FPGA sequencer. When the board restarts, it has the option -of using either the current or alternate flash bank as the boot -image, with or without the watchdog timer enabled, and finally with -or without frequency changes. - -Usage is; - - pixis_reset - pixis_reset altbank - pixis_reset altbank wd - pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> - pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> - -Examples; - - /* reset to current bank, like "reset" command */ - pixis_reset - - /* reset board but use the to alternate flash bank */ - pixis_reset altbank - - /* reset board, use alternate flash bank with watchdog timer enabled*/ - pixis_reset altbank wd - - /* reset board to alternate bank with frequency changed. - * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio - */ - pixis-reset altbank cf 40 2.5 10 - -Valid clock choices are in the 8641 Reference Manuals. diff --git a/board/freescale/mpc8641hpcn/ddr.c b/board/freescale/mpc8641hpcn/ddr.c deleted file mode 100644 index df7e3eceed..0000000000 --- a/board/freescale/mpc8641hpcn/ddr.c +++ /dev/null @@ -1,107 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2008,2011 Freescale Semiconductor, Inc. - */ - -#include <common.h> - -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> - -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 clk_adjust; - u32 cpo; - u32 write_data_delay; -}; - -/* - * This table contains all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ -const struct board_specific_parameters dimm0[] = { - /* - * memory controller 0 - * num| hi| clk| cpo|wrdata|2T - * ranks| mhz|adjst| | delay| - */ - {4, 333, 7, 7, 3}, - {4, 549, 7, 9, 3}, - {4, 650, 7, 10, 4}, - {2, 333, 7, 7, 3}, - {2, 549, 7, 9, 3}, - {2, 650, 7, 10, 4}, - {1, 333, 7, 7, 3}, - {1, 549, 7, 9, 3}, - {1, 650, 7, 10, 4}, - {} -}; - -/* - * The two slots have slightly different timing. The center values are good - * for both slots. We use identical speed tables for them. In future use, if - * DIMMs have fewer center values that require two separated tables, copy the - * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start. - */ -const struct board_specific_parameters *dimms[] = { - dimm0, - dimm0, -}; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - unsigned int i; - ulong ddr_freq; - - if (ctrl_num > 1) { - printf("Wrong parameter for controller number %d", ctrl_num); - return; - } - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (pdimm[i].n_ranks) - break; - } - if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) /* no DIMM */ - return; - - pbsp = dimms[ctrl_num]; - - /* Get clk_adjust, cpo, write_data_delay, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm[i].n_ranks) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = - pbsp->write_data_delay; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found " - "for data rate %lu MT/s!\n" - "Trying to use the highest speed (%u) parameters\n", - ddr_freq, pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->cpo_override = pbsp_highest->cpo; - popts->write_data_delay = pbsp_highest->write_data_delay; - } else { - panic("DIMM is not supported by this board"); - } - -found: - /* 2T timing enable */ - popts->twot_en = 1; -} diff --git a/board/freescale/mpc8641hpcn/law.c b/board/freescale/mpc8641hpcn/law.c deleted file mode 100644 index b73d660883..0000000000 --- a/board/freescale/mpc8641hpcn/law.c +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2008,2010-2011 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * if PCI (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT) - * 0x8000_0000 0x9fff_ffff PCIE1 MEM 512M - * 0xa000_0000 0xbfff_ffff PCIE2 MEM 512M - * else if RIO (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT) - * 0x8000_0000 0x9fff_ffff RapidIO 512M - * endif - * (prepend 0xf_0000_0000 if CONFIG_PHYS_64BIT) - * 0xffc0_0000 0xffc0_ffff PCIE1 IO 64K - * 0xffc1_0000 0xffc1_ffff PCIE2 IO 64K - * 0xffe0_0000 0xffef_ffff CCSRBAR 1M - * 0xffdf_0000 0xffe0_0000 PIXIS, CF 64K - * 0xef80_0000 0xefff_ffff FLASH (boot bank) 8M - * - * Notes: - * CCSRBAR doesn't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -struct law_entry law_table[] = { -#if !defined(CONFIG_SPD_EEPROM) - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1), -#endif - SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c deleted file mode 100644 index b30b86364d..0000000000 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ /dev/null @@ -1,248 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2006, 2007, 2010-2011 Freescale Semiconductor. - */ - -#include <common.h> -#include <init.h> -#include <log.h> -#include <net.h> -#include <pci.h> -#include <asm/global_data.h> -#include <asm/processor.h> -#include <asm/immap_86xx.h> -#include <asm/fsl_pci.h> -#include <fsl_ddr_sdram.h> -#include <asm/fsl_serdes.h> -#include <asm/io.h> -#include <linux/delay.h> -#include <linux/libfdt.h> -#include <fdt_support.h> -#include <netdev.h> - -DECLARE_GLOBAL_DATA_PTR; - -phys_size_t fixed_sdram(void); - -int checkboard(void) -{ - u8 vboot; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, " - "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", - in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), - in_8(pixis_base + PIXIS_PVER)); - - vboot = in_8(pixis_base + PIXIS_VBOOT); - if (vboot & PIXIS_VBOOT_FMAP) - printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6)); - else - puts ("Promjet\n"); - - return 0; -} - -int dram_init(void) -{ - phys_size_t dram_size = 0; - -#if defined(CONFIG_SPD_EEPROM) - dram_size = fsl_ddr_sdram(); -#else - dram_size = fixed_sdram(); -#endif - - setup_ddr_bat(dram_size); - - debug(" DDR: "); - gd->ram_size = dram_size; - - return 0; -} - - -#if !defined(CONFIG_SPD_EEPROM) -/* - * Fixed sdram init -- doesn't use serial presence detect. - */ -phys_size_t -fixed_sdram(void) -{ -#if !defined(CONFIG_SYS_RAMBOOT) - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - struct ccsr_ddr __iomem *ddr = &immap->im_ddr1; - - ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; - ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; - ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; - ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; - ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; - ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; - ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; - ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL; - ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS; - -#if defined (CONFIG_DDR_ECC) - ddr->err_disable = 0x0000008D; - ddr->err_sbe = 0x00ff0000; -#endif - asm("sync;isync"); - - udelay(500); - -#if defined (CONFIG_DDR_ECC) - /* Enable ECC checking */ - ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); -#else - ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; - ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; -#endif - asm("sync; isync"); - - udelay(500); -#endif - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; -} -#endif /* !defined(CONFIG_SPD_EEPROM) */ - -void pci_init_board(void) -{ - fsl_pcie_init_board(0); - -#ifdef CONFIG_PCIE1 - /* - * Activate ULI1575 legacy chip by performing a fake - * memory access. Needed to make ULI RTC work. - */ - in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT - + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000))); -#endif /* CONFIG_PCIE1 */ -} - - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - int off; - u64 *tmp; - int addrcells; - - ft_cpu_setup(blob, bd); - - FT_FSL_PCI_SETUP; - - /* - * Warn if it looks like the device tree doesn't match u-boot. - * This is just an estimation, based on the location of CCSR, - * which is defined by the "reg" property in the soc node. - */ - off = fdt_path_offset(blob, "/soc8641"); - addrcells = fdt_address_cells(blob, 0); - tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL); - - if (tmp) { - u64 addr; - - if (addrcells == 1) - addr = *(u32 *)tmp; - else - addr = *tmp; - - if (addr != CONFIG_SYS_CCSRBAR_PHYS) - printf("WARNING: The CCSRBAR address in your .dts " - "does not match the address of the CCSR " - "in u-boot. This means your .dts might " - "be old.\n"); - } - - return 0; -} -#endif - - -/* - * get_board_sys_clk - * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ - */ - -unsigned long -get_board_sys_clk(ulong dummy) -{ - u8 i, go_bit, rd_clks; - ulong val = 0; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - go_bit = in_8(pixis_base + PIXIS_VCTL); - go_bit &= 0x01; - - rd_clks = in_8(pixis_base + PIXIS_VCFGEN0); - rd_clks &= 0x1C; - - /* - * Only if both go bit and the SCLK bit in VCFGEN0 are set - * should we be using the AUX register. Remember, we also set the - * GO bit to boot from the alternate bank on the on-board flash - */ - - if (go_bit) { - if (rd_clks == 0x1c) - i = in_8(pixis_base + PIXIS_AUX); - else - i = in_8(pixis_base + PIXIS_SPD); - } else { - i = in_8(pixis_base + PIXIS_SPD); - } - - i &= 0x07; - - switch (i) { - case 0: - val = 33000000; - break; - case 1: - val = 40000000; - break; - case 2: - val = 50000000; - break; - case 3: - val = 66000000; - break; - case 4: - val = 83000000; - break; - case 5: - val = 100000000; - break; - case 6: - val = 134000000; - break; - case 7: - val = 166000000; - break; - } - - return val; -} - -int board_eth_init(struct bd_info *bis) -{ - /* Initialize TSECs */ - cpu_eth_init(bis); - return pci_eth_init(bis); -} - -void board_reset(void) -{ - u8 *pixis_base = (u8 *)PIXIS_BASE; - - out_8(pixis_base + PIXIS_RST, 0); - - while (1) - ; -} diff --git a/board/freescale/mx35pdk/Kconfig b/board/freescale/mx35pdk/Kconfig deleted file mode 100644 index 021d19e551..0000000000 --- a/board/freescale/mx35pdk/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_MX35PDK - -config SYS_BOARD - default "mx35pdk" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "mx35" - -config SYS_CONFIG_NAME - default "mx35pdk" - -endif diff --git a/board/freescale/mx35pdk/MAINTAINERS b/board/freescale/mx35pdk/MAINTAINERS deleted file mode 100644 index 540e943691..0000000000 --- a/board/freescale/mx35pdk/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MX35PDK BOARD -M: Stefano Babic <sbabic@denx.de> -S: Maintained -F: board/freescale/mx35pdk/ -F: include/configs/mx35pdk.h -F: configs/mx35pdk_defconfig diff --git a/board/freescale/mx35pdk/Makefile b/board/freescale/mx35pdk/Makefile deleted file mode 100644 index 6a60fad0cc..0000000000 --- a/board/freescale/mx35pdk/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> -# -# (C) Copyright 2008-2009 Freescale Semiconductor, Inc. - -obj-y := mx35pdk.o -obj-y += lowlevel_init.o diff --git a/board/freescale/mx35pdk/README b/board/freescale/mx35pdk/README deleted file mode 100644 index 6f6841f099..0000000000 --- a/board/freescale/mx35pdk/README +++ /dev/null @@ -1,114 +0,0 @@ -Overview --------------- - -mx35pdk (known als as mx35_3stack) is a development board by Freescale. -It consists of three pluggable board: - - CPU module, with CPU, RAM, flash - - Personality board, with most interfaces (USB, Network,..) - - Debug board with JTAG header. - -The board is usually delivered with redboot. This howto explains how to boot -a linux kernel and how to replace the original bootloader with U-Boot. - -The board is delivered with Redboot on the NAND flash. It is possible to -switch the boot device with the switches SW1-SW2 on the Personality board, -and with SW5-SW10 on the Debug board. - -Delivered Redboot script to start the kernel ---------------------------------------------------- - -In redboot the following script is stored: - -fis load kernel -exec -c "noinitrd console=ttymxc0,115200 root=/dev/mtdblock8 rw rootfstype=jffs2 ip=dhcp fec_mac=00:04:9F:00:E7:76" - -Kernel is taken from flash. The image is in zImage format. - -Booting from NET, rootfs on NFS: ------------------------------------ - -To change the script in redboot: - -load -r -b 0x100000 <path_to_zImage> -exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nfsroot=192.168.1.1:/opt/eldk-4.2-arm/armVFP rw ip=dhcp" - -If the ip address is not set, you can set it with : - -ip_address -l <board_ip/netmask> -h <server_ip> - -Linux partitions: ---------------------------- - -As default, the board is shipped with these partition tables for NAND -and for NOR: - -Creating 5 MTD partitions on "NAND 2GiB 3,3V 8-bit": -0x00000000-0x00100000 : "nand.bootloader" -0x00100000-0x00600000 : "nand.kernel" -0x00600000-0x06600000 : "nand.rootfs" -0x06600000-0x06e00000 : "nand.configure" -0x06e00000-0x80000000 : "nand.userfs" - -Creating 6 MTD partitions on "mxc_nor_flash.0": -0x00000000-0x00080000 : "Bootloader" -0x00080000-0x00480000 : "nor.Kernel" -0x00480000-0x02280000 : "nor.userfs" -0x02280000-0x03e80000 : "nor.rootfs" -0x01fe0000-0x01fe3000 : "FIS directory" -0x01fff000-0x04000000 : "Redboot config" - -NAND partitions can be recognized enabling in kernel CONFIG_MTD_REDBOOT_PARTS. -For this board, CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK should be set to 2. - -However, the setup in redboot is not correct and does not use the whole flash. - -Better solution is to use the kernel parameter mtdparts. -Here the resulting script to be defined in RedBoot with fconfig: - -load -r -b 0x100000 sbabic/mx35pdk/zImage.2.6.37 -exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nfsroot=192.168.1.1:/opt/eldk-4.2-arm/arm rw ip=dhcp mtdparts=mxc_nand:1m(boot),5m(linux),96m(root),8m(cfg),1938m(user);physmap-flash.0:512k(b),4m(k),30m(u),28m(r)" - -Flashing U-Boot --------------------------------- - -U-Boot should be stored on the NOR flash. - -The boot storage can be select using the switches on the personality board -(SW1-SW2) and on the DEBUG board (SW4-SW10). - -If something goes wrong flashing the bootloader, it is always possible to -recover the board booting from the other device. - -Saving U-Boot in the NOR flash ---------------------------------- - -Check the partition for boot in the NOR flash. Setting the mtdparts as reported, -the boot partition should be /dev/mtd0. - -Creating 6 MTD partitions on "mxc_nor_flash.0": -0x00000000-0x00080000 : "Bootloader" -0x00080000-0x00480000 : "nor.Kernel" -0x00480000-0x02280000 : "nor.userfs" -0x02280000-0x03e80000 : "nor.rootfs" -0x01fe0000-0x01fe3000 : "FIS directory" -0x01fff000-0x04000000 : "Redboot config" - -To erase the whole partition: -$ flash_eraseall /dev/mtd0 - -Writing U-Boot: -dd if=u-boot.bin of=/dev/mtd0 - -To boot from NOR, you have to select the switches as follows: - -Personality board - SW2 all off - SW1 all off - -Debug Board: - SW5 0 - SW6 0 - SW7 0 - SW8 1 - SW9 1 - SW10 0 diff --git a/board/freescale/mx35pdk/lowlevel_init.S b/board/freescale/mx35pdk/lowlevel_init.S deleted file mode 100644 index 5dae5597fb..0000000000 --- a/board/freescale/mx35pdk/lowlevel_init.S +++ /dev/null @@ -1,239 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> - * - * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. - */ - -#include <config.h> -#include <asm/arch/imx-regs.h> -#include <generated/asm-offsets.h> -#include "mx35pdk.h" -#include <asm/arch/lowlevel_macro.S> - -/* - * return soc version - * 0x10: TO1 - * 0x20: TO2 - * 0x30: TO3 - */ -.macro check_soc_version ret, tmp - ldr \tmp, =IIM_BASE_ADDR - ldr \ret, [\tmp, #IIM_SREV] - cmp \ret, #0x00 - moveq \tmp, #ROMPATCH_REV - ldreq \ret, [\tmp] - moveq \ret, \ret, lsl #4 - addne \ret, \ret, #0x10 -.endm - -/* CPLD on CS5 setup */ -.macro init_debug_board - ldr r0, =DBG_BASE_ADDR - ldr r1, =DBG_CSCR_U_CONFIG - str r1, [r0, #0x00] - ldr r1, =DBG_CSCR_L_CONFIG - str r1, [r0, #0x04] - ldr r1, =DBG_CSCR_A_CONFIG - str r1, [r0, #0x08] -.endm - -/* clock setup */ -.macro init_clock - ldr r0, =CCM_BASE_ADDR - - /* default CLKO to 1/32 of the ARM core*/ - ldr r1, [r0, #CLKCTL_COSR] - bic r1, r1, #0x00000FF00 - bic r1, r1, #0x0000000FF - mov r2, #0x00006C00 - add r2, r2, #0x67 - orr r1, r1, r2 - str r1, [r0, #CLKCTL_COSR] - - ldr r2, =CCM_CCMR_CONFIG - str r2, [r0, #CLKCTL_CCMR] - - check_soc_version r1, r2 - cmp r1, #CHIP_REV_2_0 - ldrhs r3, =CCM_MPLL_532_HZ - bhs 1f - ldr r2, [r0, #CLKCTL_PDR0] - tst r2, #CLKMODE_CONSUMER - ldrne r3, =CCM_MPLL_532_HZ /* consumer path*/ - ldreq r3, =CCM_MPLL_399_HZ /* auto path*/ -1: - str r3, [r0, #CLKCTL_MPCTL] - - ldr r1, =CCM_PPLL_300_HZ - str r1, [r0, #CLKCTL_PPCTL] - - ldr r1, =CCM_PDR0_CONFIG - bic r1, r1, #0x800000 - str r1, [r0, #CLKCTL_PDR0] - - ldr r1, [r0, #CLKCTL_CGR0] - orr r1, r1, #0x0C300000 - str r1, [r0, #CLKCTL_CGR0] - - ldr r1, [r0, #CLKCTL_CGR1] - orr r1, r1, #0x00000C00 - orr r1, r1, #0x00000003 - str r1, [r0, #CLKCTL_CGR1] - - ldr r1, [r0, #CLKCTL_CGR2] - orr r1, r1, #0x00C00000 - str r1, [r0, #CLKCTL_CGR2] -.endm - -.macro setup_sdram - ldr r0, =ESDCTL_BASE_ADDR - mov r3, #0x2000 - str r3, [r0, #0x0] - str r3, [r0, #0x8] - - /*ip(r12) has used to save lr register in upper calling*/ - mov fp, lr - - mov r5, #0x00 - mov r2, #0x00 - mov r1, #CSD0_BASE_ADDR - bl setup_sdram_bank - - mov r5, #0x00 - mov r2, #0x00 - mov r1, #CSD1_BASE_ADDR - bl setup_sdram_bank - - mov lr, fp - -1: - ldr r3, =ESDCTL_DELAY_LINE5 - str r3, [r0, #0x30] -.endm - -.globl lowlevel_init -lowlevel_init: - mov r10, lr - - core_init - - init_aips - - init_max - - init_m3if - - init_clock - init_debug_board - - cmp pc, #PHYS_SDRAM_1 - blo init_sdram_start - cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) - blo skip_sdram_setup - -init_sdram_start: - /*init_sdram*/ - setup_sdram - -skip_sdram_setup: - mov lr, r10 - mov pc, lr - - -/* - * r0: ESDCTL control base, r1: sdram slot base - * r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base - */ -setup_sdram_bank: - mov r3, #0xE - tst r2, #0x1 - orreq r3, r3, #0x300 /*DDR2*/ - str r3, [r0, #0x10] - bic r3, r3, #0x00A - str r3, [r0, #0x10] - beq 2f - - mov r3, #0x20000 -1: subs r3, r3, #1 - bne 1b - -2: tst r2, #0x1 - ldreq r3, =ESDCTL_DDR2_CONFIG - ldrne r3, =ESDCTL_MDDR_CONFIG - cmp r1, #CSD1_BASE_ADDR - strlo r3, [r0, #0x4] - strhs r3, [r0, #0xC] - - ldr r3, =ESDCTL_0x92220000 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - mov r3, #0xDA - ldr r4, =ESDCTL_PRECHARGE - strb r3, [r1, r4] - - tst r2, #0x1 - bne skip_set_mode - - cmp r1, #CSD1_BASE_ADDR - ldr r3, =ESDCTL_0xB2220000 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - mov r3, #0xDA - ldr r4, =ESDCTL_DDR2_EMR2 - strb r3, [r1, r4] - ldr r4, =ESDCTL_DDR2_EMR3 - strb r3, [r1, r4] - ldr r4, =ESDCTL_DDR2_EN_DLL - strb r3, [r1, r4] - ldr r4, =ESDCTL_DDR2_RESET_DLL - strb r3, [r1, r4] - - ldr r3, =ESDCTL_0x92220000 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - mov r3, #0xDA - ldr r4, =ESDCTL_PRECHARGE - strb r3, [r1, r4] - -skip_set_mode: - cmp r1, #CSD1_BASE_ADDR - ldr r3, =ESDCTL_0xA2220000 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - mov r3, #0xDA - strb r3, [r1] - strb r3, [r1] - - ldr r3, =ESDCTL_0xB2220000 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - tst r2, #0x1 - ldreq r4, =ESDCTL_DDR2_MR - ldrne r4, =ESDCTL_MDDR_MR - mov r3, #0xDA - strb r3, [r1, r4] - ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT - streqb r3, [r1, r4] - ldreq r4, =ESDCTL_DDR2_EN_DLL - ldrne r4, =ESDCTL_MDDR_EMR - strb r3, [r1, r4] - - cmp r1, #CSD1_BASE_ADDR - ldr r3, =ESDCTL_0x82228080 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - - tst r2, #0x1 - moveq r4, #0x20000 - movne r4, #0x200 -1: subs r4, r4, #1 - bne 1b - - str r3, [r1, #0x100] - ldr r4, [r1, #0x100] - cmp r3, r4 - movne r3, #1 - moveq r3, #0 - - mov pc, lr diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c deleted file mode 100644 index 4039d9f049..0000000000 --- a/board/freescale/mx35pdk/mx35pdk.c +++ /dev/null @@ -1,294 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> - * - * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <init.h> -#include <net.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/crm_regs.h> -#include <asm/arch/clock.h> -#include <asm/arch/iomux-mx35.h> -#include <i2c.h> -#include <power/pmic.h> -#include <fsl_pmic.h> -#include <mmc.h> -#include <fsl_esdhc_imx.h> -#include <mc9sdz60.h> -#include <mc13892.h> -#include <linux/types.h> -#include <asm/gpio.h> -#include <asm/arch/sys_proto.h> -#include <netdev.h> -#include <asm/mach-types.h> - -#ifndef CONFIG_BOARD_LATE_INIT -#error "CONFIG_BOARD_LATE_INIT must be set for this board" -#endif - -#ifndef CONFIG_BOARD_EARLY_INIT_F -#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board" -#endif - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - u32 size1, size2; - - size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); - - gd->ram_size = size1 + size2; - - return 0; -} - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - - return 0; -} - -#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE) - -static void setup_iomux_i2c(void) -{ - static const iomux_v3_cfg_t i2c1_pads[] = { - NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL), - NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL), - }; - - /* setup pins for I2C1 */ - imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads)); -} - - -static void setup_iomux_spi(void) -{ - static const iomux_v3_cfg_t spi_pads[] = { - MX35_PAD_CSPI1_MOSI__CSPI1_MOSI, - MX35_PAD_CSPI1_MISO__CSPI1_MISO, - MX35_PAD_CSPI1_SS0__CSPI1_SS0, - MX35_PAD_CSPI1_SS1__CSPI1_SS1, - MX35_PAD_CSPI1_SCLK__CSPI1_SCLK, - }; - - imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads)); -} - -#define USBOTG_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | \ - PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW) -#define USBOTG_OUT_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW) - -static void setup_iomux_usbotg(void) -{ - static const iomux_v3_cfg_t usbotg_pads[] = { - NEW_PAD_CTRL(MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR, - USBOTG_OUT_PAD_CTRL), - NEW_PAD_CTRL(MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC, - USBOTG_IN_PAD_CTRL), - }; - - /* Set up pins for USBOTG. */ - imx_iomux_v3_setup_multiple_pads(usbotg_pads, ARRAY_SIZE(usbotg_pads)); -} - -#define FEC_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW) - -static void setup_iomux_fec(void) -{ - static const iomux_v3_cfg_t fec_pads[] = { - NEW_PAD_CTRL(MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, FEC_PAD_CTRL | - PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - NEW_PAD_CTRL(MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, FEC_PAD_CTRL | - PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - NEW_PAD_CTRL(MX35_PAD_FEC_RX_DV__FEC_RX_DV, FEC_PAD_CTRL | - PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - NEW_PAD_CTRL(MX35_PAD_FEC_COL__FEC_COL, FEC_PAD_CTRL | - PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - NEW_PAD_CTRL(MX35_PAD_FEC_RDATA0__FEC_RDATA_0, FEC_PAD_CTRL | - PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - NEW_PAD_CTRL(MX35_PAD_FEC_TDATA0__FEC_TDATA_0, FEC_PAD_CTRL), - NEW_PAD_CTRL(MX35_PAD_FEC_TX_EN__FEC_TX_EN, FEC_PAD_CTRL), - NEW_PAD_CTRL(MX35_PAD_FEC_MDC__FEC_MDC, FEC_PAD_CTRL), - NEW_PAD_CTRL(MX35_PAD_FEC_MDIO__FEC_MDIO, FEC_PAD_CTRL | - PAD_CTL_HYS | PAD_CTL_PUS_22K_UP), - NEW_PAD_CTRL(MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, FEC_PAD_CTRL), - NEW_PAD_CTRL(MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, FEC_PAD_CTRL | - PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - NEW_PAD_CTRL(MX35_PAD_FEC_CRS__FEC_CRS, FEC_PAD_CTRL | - PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - NEW_PAD_CTRL(MX35_PAD_FEC_RDATA1__FEC_RDATA_1, FEC_PAD_CTRL | - PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - NEW_PAD_CTRL(MX35_PAD_FEC_TDATA1__FEC_TDATA_1, FEC_PAD_CTRL), - NEW_PAD_CTRL(MX35_PAD_FEC_RDATA2__FEC_RDATA_2, FEC_PAD_CTRL | - PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - NEW_PAD_CTRL(MX35_PAD_FEC_TDATA2__FEC_TDATA_2, FEC_PAD_CTRL), - NEW_PAD_CTRL(MX35_PAD_FEC_RDATA3__FEC_RDATA_3, FEC_PAD_CTRL | - PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - NEW_PAD_CTRL(MX35_PAD_FEC_TDATA3__FEC_TDATA_3, FEC_PAD_CTRL), - }; - - /* setup pins for FEC */ - imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); -} - -int board_early_init_f(void) -{ - struct ccm_regs *ccm = - (struct ccm_regs *)IMX_CCM_BASE; - - /* enable clocks */ - writel(readl(&ccm->cgr0) | - MXC_CCM_CGR0_EMI_MASK | - MXC_CCM_CGR0_EDIO_MASK | - MXC_CCM_CGR0_EPIT1_MASK, - &ccm->cgr0); - - writel(readl(&ccm->cgr1) | - MXC_CCM_CGR1_FEC_MASK | - MXC_CCM_CGR1_GPIO1_MASK | - MXC_CCM_CGR1_GPIO2_MASK | - MXC_CCM_CGR1_GPIO3_MASK | - MXC_CCM_CGR1_I2C1_MASK | - MXC_CCM_CGR1_I2C2_MASK | - MXC_CCM_CGR1_IPU_MASK, - &ccm->cgr1); - - /* Setup NAND */ - __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr); - - setup_iomux_i2c(); - setup_iomux_usbotg(); - setup_iomux_fec(); - setup_iomux_spi(); - - return 0; -} - -int board_init(void) -{ - gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS; /* board id for linux */ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -static inline int pmic_detect(void) -{ - unsigned int id; - struct pmic *p = pmic_get("FSL_PMIC"); - if (!p) - return -ENODEV; - - pmic_reg_read(p, REG_IDENTIFICATION, &id); - - id = (id >> 6) & 0x7; - if (id == 0x7) - return 1; - return 0; -} - -u32 get_board_rev(void) -{ - int rev; - - rev = pmic_detect(); - - return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; -} - -int board_late_init(void) -{ - u8 val; - u32 pmic_val; - struct pmic *p; - int ret; - - ret = pmic_init(I2C_0); - if (ret) - return ret; - - if (pmic_detect()) { - p = pmic_get("FSL_PMIC"); - imx_iomux_v3_setup_pad(MX35_PAD_WDOG_RST__WDOG_WDOG_B); - - pmic_reg_read(p, REG_SETTING_0, &pmic_val); - pmic_reg_write(p, REG_SETTING_0, - pmic_val | VO_1_30V | VO_1_50V); - pmic_reg_read(p, REG_MODE_0, &pmic_val); - pmic_reg_write(p, REG_MODE_0, pmic_val | VGEN3EN); - - imx_iomux_v3_setup_pad(MX35_PAD_COMPARE__GPIO1_5); - - gpio_direction_output(IMX_GPIO_NR(1, 5), 1); - } - - val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04; - mc9sdz60_reg_write(MC9SDZ60_REG_GPIO_1, val); - mdelay(200); - - val = mc9sdz60_reg_read(MC9SDZ60_REG_RESET_1) & 0x7F; - mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val); - mdelay(200); - - val |= 0x80; - mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val); - - /* Print board revision */ - printf("Board: MX35 PDK %d.0\n", ((get_board_rev() >> 8) + 1) & 0x0F); - - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_SMC911X) - int rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); - if (rc) - return rc; -#endif - return cpu_eth_init(bis); -} - -#if defined(CONFIG_FSL_ESDHC_IMX) - -struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR}; - -int board_mmc_init(struct bd_info *bis) -{ - static const iomux_v3_cfg_t sdhc1_pads[] = { - MX35_PAD_SD1_CMD__ESDHC1_CMD, - MX35_PAD_SD1_CLK__ESDHC1_CLK, - MX35_PAD_SD1_DATA0__ESDHC1_DAT0, - MX35_PAD_SD1_DATA1__ESDHC1_DAT1, - MX35_PAD_SD1_DATA2__ESDHC1_DAT2, - MX35_PAD_SD1_DATA3__ESDHC1_DAT3, - }; - - /* configure pins for SDHC1 only */ - imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads)); - - esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK); - return fsl_esdhc_initialize(bis, &esdhc_cfg); -} - -int board_mmc_getcd(struct mmc *mmc) -{ - return !(mc9sdz60_reg_read(MC9SDZ60_REG_DES_FLAG) & 0x4); -} -#endif diff --git a/board/freescale/mx35pdk/mx35pdk.h b/board/freescale/mx35pdk/mx35pdk.h deleted file mode 100644 index 0af4b88bfb..0000000000 --- a/board/freescale/mx35pdk/mx35pdk.h +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. - */ - -#ifndef __BOARD_MX35_3STACK_H -#define __BOARD_MX35_3STACK_H - -#define DBG_BASE_ADDR WEIM_CTRL_CS5 -#define DBG_CSCR_U_CONFIG 0x0000D843 -#define DBG_CSCR_L_CONFIG 0x22252521 -#define DBG_CSCR_A_CONFIG 0x22220A00 - -#define CCM_CCMR_CONFIG 0x003F4208 -#define CCM_PDR0_CONFIG 0x00801000 - -/* MEMORY SETTING */ -#define ESDCTL_0x92220000 0x92220000 -#define ESDCTL_0xA2220000 0xA2220000 -#define ESDCTL_0xB2220000 0xB2220000 -#define ESDCTL_0x82228080 0x82228080 - -#define ESDCTL_PRECHARGE 0x00000400 - -#define ESDCTL_MDDR_CONFIG 0x007FFC3F -#define ESDCTL_MDDR_MR 0x00000033 -#define ESDCTL_MDDR_EMR 0x02000000 - -#define ESDCTL_DDR2_CONFIG 0x007FFC3F -#define ESDCTL_DDR2_EMR2 0x04000000 -#define ESDCTL_DDR2_EMR3 0x06000000 -#define ESDCTL_DDR2_EN_DLL 0x02000400 -#define ESDCTL_DDR2_RESET_DLL 0x00000333 -#define ESDCTL_DDR2_MR 0x00000233 -#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780 - -#define ESDCTL_DELAY_LINE5 0x00F49F00 -#endif /* __BOARD_MX35_3STACK_H */ |