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diff --git a/board/freescale/bsc9132qds/README b/board/freescale/bsc9132qds/README deleted file mode 100644 index ede95d41da..0000000000 --- a/board/freescale/bsc9132qds/README +++ /dev/null @@ -1,150 +0,0 @@ -Overview --------- - The BSC9132 is a highly integrated device that targets the evolving - Microcell, Picocell, and Enterprise-Femto base station market subsegments. - - The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850 - core technologies with MAPLE-B2P baseband acceleration processing elements - to address the need for a high performance, low cost, integrated solution - that handles all required processing layers without the need for an - external device except for an RF transceiver or, in a Micro base station - configuration, a host device that handles the L3/L4 and handover between - sectors. - - The BSC9132 SoC includes the following function and features: - - Power Architecture subsystem including two e500 processors with - 512-Kbyte shared L2 cache - - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2 - cache - - 32 Kbyte of shared M3 memory - - The Multi Accelerator Platform Engine for Pico BaseStation Baseband - Processing (MAPLE-B2P) - - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including - ECC), up to 1333 MHz data rate - - Dedicated security engine featuring trusted boot - - Two DMA controllers - - OCNDMA with four bidirectional channels - - SysDMA with sixteen bidirectional channels - - Interfaces - - Four-lane SerDes PHY - - PCI Express controller complies with the PEX Specification-Rev 2.0 - - Two Common Public Radio Interface (CPRI) controller lanes - - High-speed USB 2.0 host and device controller with ULPI interface - - Enhanced secure digital (SD/MMC) host controller (eSDHC) - - Antenna interface controller (AIC), supporting four industry - standard JESD207/four custom ADI RF interfaces - - ADI lanes support both full duplex FDD support & half duplex TDD - - Universal Subscriber Identity Module (USIM) interface that - facilitates communication to SIM cards or Eurochip pre-paid phone - cards - - Two DUART, two eSPI, and two I2C controllers - - Integrated Flash memory controller (IFC) - - GPIO - - Sixteen 32-bit timers - -The SC3850 core subsystem consists of the following: - - 32 KB, 8-way, level 1 instruction cache (L1 ICache) - - 32 KB, 8-way, level 1 data cache (L1 DCache) - - 512 KB, 8-way, level 2 unified instruction/data cache (L2 cache/M2 memory) - - Memory management unit (MMU) - - Global interrupt controller ( GIC) - - Debug and profiling unit (DPU) - - Two 32-bit quad timers - -BSC9132QDS board Overview -------------------------- - 2Gbyte DDR3 (on board DDR), Dual Ranki - 32Mbyte 16bit NOR flash - 128Mbyte 2K page size NAND Flash - 256 Kbit M24256 I2C EEPROM - 128 Mbit SPI Flash memory - SD slot - USB-ULPI - eTSEC1: Connected to SGMII PHY - eTSEC2: Connected to SGMII PHY - PCIe - CPRI - SerDes - I2C RTC - DUART interface: supports one UARTs up to 115200 bps for console display - -Frequency Combinations Supported --------------------------------- -Core MHz/CCB MHz/DDR(MT/s) -1. CPU0/CPU1/CCB/DDR: 1000MHz/1000MHz/500MHz/800MHz - (SYSCLK = 100MHz, DDRCLK = 100MHz) -2. CPU0/CPU1/CCB/DDR: 1200MHz/1200MHz/600MHz/1330MHz - (SYSCLK = 100MHz, DDRCLK = 133MHz) - -Boot Methods Supported ------------------------ -1. NOR Flash -2. NAND Flash -3. SD Card -4. SPI flash - -Default Boot Method --------------------- -NOR boot - -Building U-Boot --------------- -To build the U-Boot for BSC9132QDS: -1. NOR Flash - make BSC9132QDS_NOR_DDRCLK100 : For 100MHZ DDR CLK - make BSC9132QDS_NOR_DDRCLK133 : For 133MHZ DDR CLK -2. NAND Flash : It is currently not supported -3. SPI Flash - make BSC9132QDS_SPIFLASH_DDRCLK100 : For 100MHZ DDR CLK - make BSC9132QDS_SPIFLASH_DDRCLK133 : For 133MHZ DDR CLK -4. SD Card - make BSC9132QDS_SDCARD_DDRCLK100 : For 100MHZ DDR CLK - make BSC9132QDS_SDCARD_DDRCLK133 : For 133MHZ DDR CLK - -Memory map ------------ - 0x0000_0000 0x7FFF_FFFF DDR 2G cacheable - 0x8000_0000 0x8FFF_FFFF NOR Flash 256M - 0x9000_0000 0x9FFF_FFFF PCIe Memory 256M - 0xA000_0000 0xA7FF_FFFF DSP core1 L2 space 128M - 0xB000_0000 0xB0FF_FFFF DSP core0 M2 space 16M - 0xB100_0000 0xB1FF_FFFF DSP core1 M2 space 16M - 0xC000_0000 0xC000_7FFF M3 Memory 32K - 0xC001_0000 0xC001_FFFF PCI Express I/O 64K - 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M - 0xC1F0_0000 0xC1F7_FFFF PA SRAM Region 0 512K - 0xC1F8_0000 0xC1FB_FFFF PA SRAM Region 1 512K - 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K - 0xFEE0_0000 0xFEE0_0FFF DSP Boot ROM 4K - 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M - 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M - 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND Buffer 8M - -Flashing Images ---------------- -To place a new U-Boot image in the NAND flash and then boot -with that new image temporarily, use this: - tftp 1000000 u-boot-nand.bin - nand erase 0 100000 - nand write 1000000 0 100000 - reset - -Using the Device Tree Source File ---------------------------------- -To create the DTB (Device Tree Binary) image file, -use a command similar to this: - - dtc -b 0 -f -I dts -O dtb bsc9132qds.dts > bsc9132qds.dtb - -Likely, that .dts file will come from here; - - linux-2.6/arch/powerpc/boot/dts/bsc9132qds.dts - -Booting Linux -------------- -Place a linux uImage in the TFTP disk area. - - tftp 1000000 uImage - tftp 2000000 rootfs.ext2.gz.uboot - tftp c00000 bsc9132qds.dtb - bootm 1000000 2000000 c00000 |