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-rw-r--r--arch/mips/dts/mrvl,cn73xx.dtsi10
-rw-r--r--arch/mips/dts/mrvl,octeon-ebb7304.dts2
2 files changed, 11 insertions, 1 deletions
diff --git a/arch/mips/dts/mrvl,cn73xx.dtsi b/arch/mips/dts/mrvl,cn73xx.dtsi
index 4c7b6e4160..7c0a8d73f0 100644
--- a/arch/mips/dts/mrvl,cn73xx.dtsi
+++ b/arch/mips/dts/mrvl,cn73xx.dtsi
@@ -5,6 +5,8 @@
/dts-v1/;
+#include <dt-bindings/clock/octeon-clock.h>
+
/ {
#address-cells = <2>;
#size-cells = <2>;
@@ -38,6 +40,12 @@
#size-cells = <1>;
};
+ clk: clock {
+ compatible = "mrvl,octeon-clk";
+ #clock-cells = <1>;
+ u-boot,dm-pre-reloc;
+ };
+
gpio: gpio-controller@1070000000800 {
#gpio-cells = <2>;
compatible = "cavium,octeon-7890-gpio";
@@ -95,6 +103,7 @@
/* INT_ST, INT_TS, INT_CORE */
interrupts = <0x0b000 1>, <0x0b001 1>, <0x0b002 1>;
clock-frequency = <100000>;
+ clocks = <&clk OCTEON_CLK_IO>;
};
i2c1: i2c@1180000001200 {
@@ -105,6 +114,7 @@
/* INT_ST, INT_TS, INT_CORE */
interrupts = <0x0b100 1>, <0x0b101 1>, <0x0b102 1>;
clock-frequency = <100000>;
+ clocks = <&clk OCTEON_CLK_IO>;
};
};
};
diff --git a/arch/mips/dts/mrvl,octeon-ebb7304.dts b/arch/mips/dts/mrvl,octeon-ebb7304.dts
index 096e5c8f66..c229aa5fc0 100644
--- a/arch/mips/dts/mrvl,octeon-ebb7304.dts
+++ b/arch/mips/dts/mrvl,octeon-ebb7304.dts
@@ -5,7 +5,7 @@
/dts-v1/;
-/include/ "mrvl,cn73xx.dtsi"
+#include "mrvl,cn73xx.dtsi"
/ {
model = "cavium,ebb7304";