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-rw-r--r--arch/x86/cpu/baytrail/fsp_configs.c35
-rw-r--r--arch/x86/dts/bayleybay.dts17
-rw-r--r--arch/x86/dts/baytrail_som-db5800-som-6867.dts15
-rw-r--r--arch/x86/dts/conga-qeval20-qa3-e3845.dts29
-rw-r--r--arch/x86/dts/dfi-bt700.dtsi29
-rw-r--r--arch/x86/dts/minnowmax.dts29
-rw-r--r--arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h77
7 files changed, 159 insertions, 72 deletions
diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c
index 977d5fe706..c48ac07385 100644
--- a/arch/x86/cpu/baytrail/fsp_configs.c
+++ b/arch/x86/cpu/baytrail/fsp_configs.c
@@ -148,10 +148,10 @@ void update_fsp_configs(struct fsp_config_data *config,
fsp_upd->mrc_init_tseg_size = fdtdec_get_int(blob, node,
"fsp,mrc-init-tseg-size",
- 1);
+ MRC_INIT_TSEG_SIZE_1MB);
fsp_upd->mrc_init_mmio_size = fdtdec_get_int(blob, node,
"fsp,mrc-init-mmio-size",
- 0x800);
+ MRC_INIT_MMIO_SIZE_2048MB);
fsp_upd->mrc_init_spd_addr1 = fdtdec_get_int(blob, node,
"fsp,mrc-init-spd-addr1",
0xa0);
@@ -159,7 +159,8 @@ void update_fsp_configs(struct fsp_config_data *config,
"fsp,mrc-init-spd-addr2",
0xa2);
fsp_upd->emmc_boot_mode = fdtdec_get_int(blob, node,
- "fsp,emmc-boot-mode", 2);
+ "fsp,emmc-boot-mode",
+ EMMC_BOOT_MODE_EMMC41);
fsp_upd->enable_sdio = fdtdec_get_bool(blob, node, "fsp,enable-sdio");
fsp_upd->enable_sdcard = fdtdec_get_bool(blob, node,
"fsp,enable-sdcard");
@@ -169,7 +170,8 @@ void update_fsp_configs(struct fsp_config_data *config,
"fsp,enable-hsuart1");
fsp_upd->enable_spi = fdtdec_get_bool(blob, node, "fsp,enable-spi");
fsp_upd->enable_sata = fdtdec_get_bool(blob, node, "fsp,enable-sata");
- fsp_upd->sata_mode = fdtdec_get_int(blob, node, "fsp,sata-mode", 1);
+ fsp_upd->sata_mode = fdtdec_get_int(blob, node, "fsp,sata-mode",
+ SATA_MODE_AHCI);
fsp_upd->enable_azalia = fdtdec_get_bool(blob, node,
"fsp,enable-azalia");
fsp_upd->enable_xhci = fdtdec_get_bool(blob, node, "fsp,enable-xhci");
@@ -189,10 +191,11 @@ void update_fsp_configs(struct fsp_config_data *config,
fsp_upd->enable_pwm1 = fdtdec_get_bool(blob, node, "fsp,enable-pwm1");
fsp_upd->enable_hsi = fdtdec_get_bool(blob, node, "fsp,enable-hsi");
fsp_upd->igd_dvmt50_pre_alloc = fdtdec_get_int(blob, node,
- "fsp,igd-dvmt50-pre-alloc", 2);
+ "fsp,igd-dvmt50-pre-alloc", IGD_DVMT50_PRE_ALLOC_64MB);
fsp_upd->aperture_size = fdtdec_get_int(blob, node, "fsp,aperture-size",
- 2);
- fsp_upd->gtt_size = fdtdec_get_int(blob, node, "fsp,gtt-size", 2);
+ APERTURE_SIZE_256MB);
+ fsp_upd->gtt_size = fdtdec_get_int(blob, node, "fsp,gtt-size",
+ GTT_SIZE_2MB);
fsp_upd->mrc_debug_msg = fdtdec_get_bool(blob, node,
"fsp,mrc-debug-msg");
fsp_upd->isp_enable = fdtdec_get_bool(blob, node, "fsp,isp-enable");
@@ -203,7 +206,7 @@ void update_fsp_configs(struct fsp_config_data *config,
fsp_upd->txe_uma_enable = fdtdec_get_bool(blob, node,
"fsp,txe-uma-enable");
fsp_upd->os_selection = fdtdec_get_int(blob, node, "fsp,os-selection",
- 4);
+ OS_SELECTION_LINUX);
fsp_upd->emmc45_ddr50_enabled = fdtdec_get_bool(blob, node,
"fsp,emmc45-ddr50-enabled");
fsp_upd->emmc45_hs200_enabled = fdtdec_get_bool(blob, node,
@@ -224,30 +227,32 @@ void update_fsp_configs(struct fsp_config_data *config,
} else {
mem->dram_speed = fdtdec_get_int(blob, node,
"fsp,dram-speed",
- 0x02);
+ DRAM_SPEED_1333MTS);
mem->dram_type = fdtdec_get_int(blob, node,
- "fsp,dram-type", 0x01);
+ "fsp,dram-type",
+ DRAM_TYPE_DDR3L);
mem->dimm_0_enable = fdtdec_get_bool(blob, node,
"fsp,dimm-0-enable");
mem->dimm_1_enable = fdtdec_get_bool(blob, node,
"fsp,dimm-1-enable");
mem->dimm_width = fdtdec_get_int(blob, node,
"fsp,dimm-width",
- 0x00);
+ DIMM_WIDTH_X8);
mem->dimm_density = fdtdec_get_int(blob, node,
"fsp,dimm-density",
- 0x01);
+ DIMM_DENSITY_2GBIT);
mem->dimm_bus_width = fdtdec_get_int(blob, node,
- "fsp,dimm-bus-width", 0x03);
+ "fsp,dimm-bus-width",
+ DIMM_BUS_WIDTH_64BITS);
mem->dimm_sides = fdtdec_get_int(blob, node,
"fsp,dimm-sides",
- 0x00);
+ DIMM_SIDES_1RANKS);
mem->dimm_tcl = fdtdec_get_int(blob, node,
"fsp,dimm-tcl", 0x09);
mem->dimm_trpt_rcd = fdtdec_get_int(blob, node,
"fsp,dimm-trpt-rcd", 0x09);
mem->dimm_twr = fdtdec_get_int(blob, node,
- "fsp,dimm-twr", 0x0A);
+ "fsp,dimm-twr", 0x0a);
mem->dimm_twtr = fdtdec_get_int(blob, node,
"fsp,dimm-twtr", 0x05);
mem->dimm_trrd = fdtdec_get_int(blob, node,
diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index 1916991077..a577b9371b 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -6,6 +6,7 @@
/dts-v1/;
+#include <asm/arch-baytrail/fsp/fsp_configs.h>
#include <dt-bindings/gpio/x86-gpio.h>
#include <dt-bindings/interrupt-router/intel-irq.h>
@@ -236,17 +237,17 @@
fsp {
compatible = "intel,baytrail-fsp";
- fsp,mrc-init-tseg-size = <1>;
- fsp,mrc-init-mmio-size = <0x800>;
+ fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
+ fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
fsp,mrc-init-spd-addr1 = <0xa0>;
fsp,mrc-init-spd-addr2 = <0xa2>;
- fsp,emmc-boot-mode = <1>;
+ fsp,emmc-boot-mode = <EMMC_BOOT_MODE_AUTO>;
fsp,enable-sdio;
fsp,enable-sdcard;
fsp,enable-hsuart1;
fsp,enable-spi;
fsp,enable-sata;
- fsp,sata-mode = <1>;
+ fsp,sata-mode = <SATA_MODE_AHCI>;
fsp,enable-lpe;
fsp,lpss-sio-enable-pci-mode;
fsp,enable-dma0;
@@ -260,11 +261,11 @@
fsp,enable-i2c6;
fsp,enable-pwm0;
fsp,enable-pwm1;
- fsp,igd-dvmt50-pre-alloc = <2>;
- fsp,aperture-size = <2>;
- fsp,gtt-size = <2>;
+ fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
+ fsp,aperture-size = <APERTURE_SIZE_256MB>;
+ fsp,gtt-size = <GTT_SIZE_2MB>;
fsp,scc-enable-pci-mode;
- fsp,os-selection = <4>;
+ fsp,os-selection = <OS_SELECTION_LINUX>;
fsp,emmc45-ddr50-enabled;
fsp,emmc45-retune-timer-value = <8>;
fsp,enable-igd;
diff --git a/arch/x86/dts/baytrail_som-db5800-som-6867.dts b/arch/x86/dts/baytrail_som-db5800-som-6867.dts
index 61af6366e0..3fc36f19c3 100644
--- a/arch/x86/dts/baytrail_som-db5800-som-6867.dts
+++ b/arch/x86/dts/baytrail_som-db5800-som-6867.dts
@@ -7,6 +7,7 @@
/dts-v1/;
+#include <asm/arch-baytrail/fsp/fsp_configs.h>
#include <dt-bindings/gpio/x86-gpio.h>
#include <dt-bindings/interrupt-router/intel-irq.h>
@@ -259,13 +260,13 @@
fsp {
compatible = "intel,baytrail-fsp";
- fsp,mrc-init-tseg-size = <1>;
- fsp,mrc-init-mmio-size = <0x800>;
+ fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
+ fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
fsp,mrc-init-spd-addr1 = <0xa0>;
fsp,mrc-init-spd-addr2 = <0xa2>;
fsp,enable-spi;
fsp,enable-sata;
- fsp,sata-mode = <1>;
+ fsp,sata-mode = <SATA_MODE_AHCI>;
fsp,enable-azalia;
fsp,lpss-sio-enable-pci-mode;
fsp,enable-dma0;
@@ -279,11 +280,11 @@
fsp,enable-i2c6;
fsp,enable-pwm0;
fsp,enable-pwm1;
- fsp,igd-dvmt50-pre-alloc = <2>;
- fsp,aperture-size = <2>;
- fsp,gtt-size = <2>;
+ fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
+ fsp,aperture-size = <APERTURE_SIZE_256MB>;
+ fsp,gtt-size = <GTT_SIZE_2MB>;
fsp,scc-enable-pci-mode;
- fsp,os-selection = <4>;
+ fsp,os-selection = <OS_SELECTION_LINUX>;
fsp,enable-igd;
};
diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
index 904197a101..369cea6b58 100644
--- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts
+++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
@@ -7,6 +7,7 @@
/dts-v1/;
+#include <asm/arch-baytrail/fsp/fsp_configs.h>
#include <dt-bindings/gpio/x86-gpio.h>
#include <dt-bindings/interrupt-router/intel-irq.h>
@@ -246,42 +247,42 @@
fsp {
compatible = "intel,baytrail-fsp";
- fsp,mrc-init-tseg-size = <1>;
- fsp,mrc-init-mmio-size = <0x800>;
+ fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
+ fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
fsp,mrc-init-spd-addr1 = <0xa0>;
fsp,mrc-init-spd-addr2 = <0xa2>;
- fsp,emmc-boot-mode = <1>;
+ fsp,emmc-boot-mode = <EMMC_BOOT_MODE_AUTO>;
fsp,enable-sdio;
fsp,enable-sdcard;
fsp,enable-hsuart1;
fsp,enable-spi;
fsp,enable-sata;
- fsp,sata-mode = <1>;
+ fsp,sata-mode = <SATA_MODE_AHCI>;
fsp,enable-lpe;
fsp,lpss-sio-enable-pci-mode;
fsp,enable-dma0;
fsp,enable-dma1;
fsp,enable-pwm0;
fsp,enable-pwm1;
- fsp,igd-dvmt50-pre-alloc = <2>;
- fsp,aperture-size = <2>;
- fsp,gtt-size = <2>;
+ fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
+ fsp,aperture-size = <APERTURE_SIZE_256MB>;
+ fsp,gtt-size = <GTT_SIZE_2MB>;
fsp,scc-enable-pci-mode;
- fsp,os-selection = <4>;
+ fsp,os-selection = <OS_SELECTION_LINUX>;
fsp,emmc45-ddr50-enabled;
fsp,emmc45-retune-timer-value = <8>;
fsp,enable-igd;
fsp,enable-memory-down;
fsp,memory-down-params {
compatible = "intel,baytrail-fsp-mdp";
- fsp,dram-speed = <2>; /* 2=1333MHz */
- fsp,dram-type = <1>; /* 1=DDR3L */
+ fsp,dram-speed = <DRAM_SPEED_1333MTS>;
+ fsp,dram-type = <DRAM_TYPE_DDR3L>;
fsp,dimm-0-enable;
fsp,dimm-1-enable;
- fsp,dimm-width = <1>; /* 1=x16, 2=x32 */
- fsp,dimm-density = <2>; /* 2=4Gbit */
- fsp,dimm-bus-width = <3>; /* 3=64bits */
- fsp,dimm-sides = <0>; /* 0=1 ranks -> 0x2b */
+ fsp,dimm-width = <DIMM_WIDTH_X16>;
+ fsp,dimm-density = <DIMM_DENSITY_4GBIT>;
+ fsp,dimm-bus-width = <DIMM_BUS_WIDTH_64BITS>;
+ fsp,dimm-sides = <DIMM_SIDES_1RANKS>;
/* These following values might need a re-visit */
fsp,dimm-tcl = <8>;
diff --git a/arch/x86/dts/dfi-bt700.dtsi b/arch/x86/dts/dfi-bt700.dtsi
index a369e7322e..33f2a9c7a2 100644
--- a/arch/x86/dts/dfi-bt700.dtsi
+++ b/arch/x86/dts/dfi-bt700.dtsi
@@ -5,6 +5,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <asm/arch-baytrail/fsp/fsp_configs.h>
#include <dt-bindings/gpio/x86-gpio.h>
#include <dt-bindings/interrupt-router/intel-irq.h>
@@ -248,18 +249,18 @@
fsp {
compatible = "intel,baytrail-fsp";
- fsp,mrc-init-tseg-size = <1>;
- fsp,mrc-init-mmio-size = <0x800>;
+ fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
+ fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
fsp,mrc-init-spd-addr1 = <0xa0>;
fsp,mrc-init-spd-addr2 = <0xa2>;
- fsp,emmc-boot-mode = <1>;
+ fsp,emmc-boot-mode = <EMMC_BOOT_MODE_AUTO>;
fsp,enable-sdio;
fsp,enable-sdcard;
fsp,enable-hsuart0;
fsp,enable-hsuart1;
fsp,enable-spi;
fsp,enable-sata;
- fsp,sata-mode = <1>;
+ fsp,sata-mode = <SATA_MODE_AHCI>;
fsp,enable-lpe;
fsp,lpss-sio-enable-pci-mode;
fsp,enable-dma0;
@@ -273,24 +274,24 @@
fsp,enable-i2c6;
fsp,enable-pwm0;
fsp,enable-pwm1;
- fsp,igd-dvmt50-pre-alloc = <2>;
- fsp,aperture-size = <2>;
- fsp,gtt-size = <2>;
+ fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
+ fsp,aperture-size = <APERTURE_SIZE_256MB>;
+ fsp,gtt-size = <GTT_SIZE_2MB>;
fsp,scc-enable-pci-mode;
- fsp,os-selection = <4>;
+ fsp,os-selection = <OS_SELECTION_LINUX>;
fsp,emmc45-ddr50-enabled;
fsp,emmc45-retune-timer-value = <8>;
fsp,enable-igd;
fsp,enable-memory-down;
fsp,memory-down-params {
compatible = "intel,baytrail-fsp-mdp";
- fsp,dram-speed = <2>; /* 2=1333MHz */
- fsp,dram-type = <1>; /* 1=DDR3L */
+ fsp,dram-speed = <DRAM_SPEED_1333MTS>;
+ fsp,dram-type = <DRAM_TYPE_DDR3L>;
fsp,dimm-0-enable;
- fsp,dimm-width = <1>; /* 1=x16, 2=x32 */
- fsp,dimm-density = <3>; /* 3=8Gbit */
- fsp,dimm-bus-width = <3>; /* 3=64bits */
- fsp,dimm-sides = <0>; /* 0=1 ranks -> 0x2b */
+ fsp,dimm-width = <DIMM_WIDTH_X16>;
+ fsp,dimm-density = <DIMM_DENSITY_8GBIT>;
+ fsp,dimm-bus-width = <DIMM_BUS_WIDTH_64BITS>;
+ fsp,dimm-sides = <DIMM_SIDES_1RANKS>;
/* These following values might need a re-visit */
fsp,dimm-tcl = <8>;
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 75d27610d4..a4e2fa211c 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -6,6 +6,7 @@
/dts-v1/;
+#include <asm/arch-baytrail/fsp/fsp_configs.h>
#include <dt-bindings/gpio/x86-gpio.h>
#include <dt-bindings/interrupt-router/intel-irq.h>
@@ -260,17 +261,17 @@
fsp {
compatible = "intel,baytrail-fsp";
- fsp,mrc-init-tseg-size = <1>;
- fsp,mrc-init-mmio-size = <0x800>;
+ fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
+ fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
fsp,mrc-init-spd-addr1 = <0xa0>;
fsp,mrc-init-spd-addr2 = <0xa2>;
- fsp,emmc-boot-mode = <1>;
+ fsp,emmc-boot-mode = <EMMC_BOOT_MODE_AUTO>;
fsp,enable-sdio;
fsp,enable-sdcard;
fsp,enable-hsuart1;
fsp,enable-spi;
fsp,enable-sata;
- fsp,sata-mode = <1>;
+ fsp,sata-mode = <SATA_MODE_AHCI>;
fsp,enable-lpe;
fsp,lpss-sio-enable-pci-mode;
fsp,enable-dma0;
@@ -284,24 +285,24 @@
fsp,enable-i2c6;
fsp,enable-pwm0;
fsp,enable-pwm1;
- fsp,igd-dvmt50-pre-alloc = <2>;
- fsp,aperture-size = <2>;
- fsp,gtt-size = <2>;
+ fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
+ fsp,aperture-size = <APERTURE_SIZE_256MB>;
+ fsp,gtt-size = <GTT_SIZE_2MB>;
fsp,scc-enable-pci-mode;
- fsp,os-selection = <4>;
+ fsp,os-selection = <OS_SELECTION_LINUX>;
fsp,emmc45-ddr50-enabled;
fsp,emmc45-retune-timer-value = <8>;
fsp,enable-igd;
fsp,enable-memory-down;
fsp,memory-down-params {
compatible = "intel,baytrail-fsp-mdp";
- fsp,dram-speed = <1>;
- fsp,dram-type = <1>;
+ fsp,dram-speed = <DRAM_SPEED_1066MTS>;
+ fsp,dram-type = <DRAM_TYPE_DDR3L>;
fsp,dimm-0-enable;
- fsp,dimm-width = <1>;
- fsp,dimm-density = <2>;
- fsp,dimm-bus-width = <3>;
- fsp,dimm-sides = <0>;
+ fsp,dimm-width = <DIMM_WIDTH_X16>;
+ fsp,dimm-density = <DIMM_DENSITY_4GBIT>;
+ fsp,dimm-bus-width = <DIMM_BUS_WIDTH_64BITS>;
+ fsp,dimm-sides = <DIMM_SIDES_1RANKS>;
fsp,dimm-tcl = <0xb>;
fsp,dimm-trpt-rcd = <0xb>;
fsp,dimm-twr = <0xc>;
diff --git a/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h b/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h
index e539890c33..382cb79700 100644
--- a/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h
+++ b/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h
@@ -7,6 +7,7 @@
#ifndef __FSP_CONFIGS_H__
#define __FSP_CONFIGS_H__
+#ifndef __ASSEMBLY__
struct fsp_config_data {
struct fsp_cfg_common common;
struct upd_region fsp_upd;
@@ -15,5 +16,81 @@ struct fsp_config_data {
struct fspinit_rtbuf {
struct common_buf common; /* FSP common runtime data structure */
};
+#endif
+
+/* FSP user configuration settings */
+
+#define MRC_INIT_TSEG_SIZE_1MB 1
+#define MRC_INIT_TSEG_SIZE_2MB 2
+#define MRC_INIT_TSEG_SIZE_4MB 4
+#define MRC_INIT_TSEG_SIZE_8MB 8
+
+#define MRC_INIT_MMIO_SIZE_1024MB 0x400
+#define MRC_INIT_MMIO_SIZE_1536MB 0x600
+#define MRC_INIT_MMIO_SIZE_2048MB 0x800
+
+#define EMMC_BOOT_MODE_DISABLED 0
+#define EMMC_BOOT_MODE_AUTO 1
+#define EMMC_BOOT_MODE_EMMC41 2
+#define EMMC_BOOT_MODE_EMCC45 3
+
+#define SATA_MODE_IDE 0
+#define SATA_MODE_AHCI 1
+
+#define IGD_DVMT50_PRE_ALLOC_32MB 0x01
+#define IGD_DVMT50_PRE_ALLOC_64MB 0x02
+#define IGD_DVMT50_PRE_ALLOC_96MB 0x03
+#define IGD_DVMT50_PRE_ALLOC_128MB 0x04
+#define IGD_DVMT50_PRE_ALLOC_160MB 0x05
+#define IGD_DVMT50_PRE_ALLOC_192MB 0x06
+#define IGD_DVMT50_PRE_ALLOC_224MB 0x07
+#define IGD_DVMT50_PRE_ALLOC_256MB 0x08
+#define IGD_DVMT50_PRE_ALLOC_288MB 0x09
+#define IGD_DVMT50_PRE_ALLOC_320MB 0x0a
+#define IGD_DVMT50_PRE_ALLOC_352MB 0x0b
+#define IGD_DVMT50_PRE_ALLOC_384MB 0x0c
+#define IGD_DVMT50_PRE_ALLOC_416MB 0x0d
+#define IGD_DVMT50_PRE_ALLOC_448MB 0x0e
+#define IGD_DVMT50_PRE_ALLOC_480MB 0x0f
+#define IGD_DVMT50_PRE_ALLOC_512MB 0x10
+
+#define APERTURE_SIZE_128MB 1
+#define APERTURE_SIZE_256MB 2
+#define APERTURE_SIZE_512MB 3
+
+#define GTT_SIZE_1MB 1
+#define GTT_SIZE_2MB 2
+
+#define OS_SELECTION_ANDROID 1
+#define OS_SELECTION_LINUX 4
+
+#define DRAM_SPEED_800MTS 0
+#define DRAM_SPEED_1066MTS 1
+#define DRAM_SPEED_1333MTS 2
+#define DRAM_SPEED_1600MTS 3
+
+#define DRAM_TYPE_DDR3 0
+#define DRAM_TYPE_DDR3L 1
+#define DRAM_TYPE_DDR3ECC 2
+#define DRAM_TYPE_LPDDR2 4
+#define DRAM_TYPE_LPDDR3 5
+#define DRAM_TYPE_DDR4 6
+
+#define DIMM_WIDTH_X8 0
+#define DIMM_WIDTH_X16 1
+#define DIMM_WIDTH_X32 2
+
+#define DIMM_DENSITY_1GBIT 0
+#define DIMM_DENSITY_2GBIT 1
+#define DIMM_DENSITY_4GBIT 2
+#define DIMM_DENSITY_8GBIT 3
+
+#define DIMM_BUS_WIDTH_8BITS 0
+#define DIMM_BUS_WIDTH_16BITS 1
+#define DIMM_BUS_WIDTH_32BITS 2
+#define DIMM_BUS_WIDTH_64BITS 3
+
+#define DIMM_SIDES_1RANKS 0
+#define DIMM_SIDES_2RANKS 1
#endif /* __FSP_CONFIGS_H__ */
generated by cgit (git 2.34.1) at 2024-12-26 05:09:46 +0000