diff options
Diffstat (limited to 'arch/arm')
43 files changed, 190 insertions, 109 deletions
diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c index 97d4473a68..61c38b17cb 100644 --- a/arch/arm/cpu/armv8/cpu-dt.c +++ b/arch/arm/cpu/armv8/cpu-dt.c @@ -9,7 +9,7 @@ #include <asm/system.h> #include <asm/armv8/sec_firmware.h> -#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) int psci_update_dt(void *fdt) { /* diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 3a04dce56f..7f29aa4725 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -26,7 +26,7 @@ #endif #include <fsl_sec.h> #include <asm/arch-fsl-layerscape/soc.h> -#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) #include <asm/armv8/sec_firmware.h> #endif #include <asm/arch/speed.h> @@ -81,7 +81,7 @@ void ft_fixup_cpu(void *blob) "device_type", "cpu", 4); } -#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \ +#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) && \ defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI) int node; u32 psci_ver; @@ -383,7 +383,7 @@ static void fdt_fixup_msi(void *blob) } #endif -#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) /* Remove JR node used by SEC firmware */ void fdt_fixup_remove_jr(void *blob) { @@ -490,7 +490,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) else { ccsr_sec_t __iomem *sec; -#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) fdt_fixup_remove_jr(blob); fdt_fixup_kaslr(blob); #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index a519f6ed67..d8803738f1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -192,6 +192,7 @@ ENTRY(lowlevel_init) #endif /* Initialize GIC Secure Bank Status */ +#if !defined(CONFIG_SPL_BUILD) #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) branch_if_slave x0, 1f bl get_gic_offset @@ -205,6 +206,7 @@ ENTRY(lowlevel_init) bl gic_init_secure_percpu #endif #endif +#endif 100: branch_if_master x0, x1, 2f diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c index 1ddb267093..2285296ea0 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c @@ -16,7 +16,7 @@ #elif defined(CONFIG_FSL_LSCH2) #include <asm/arch/immap_lsch2.h> #endif -#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) #include <asm/armv8/sec_firmware.h> #endif #ifdef CONFIG_CHAIN_OF_TRUST diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi index e63684c334..9b4e0298a7 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi @@ -16,7 +16,7 @@ ethernet3 = &enetc6; }; - binman { + binman: binman { filename = "u-boot.rom"; pad-byte = <0xff>; @@ -80,21 +80,18 @@ conf-1 { description = "fsl-ls1028a-kontron-sl28"; firmware = "uboot"; - loadables = "uboot"; fdt = "fdt-1"; }; conf-2 { description = "fsl-ls1028a-kontron-sl28-var3"; firmware = "uboot"; - loadables = "uboot"; fdt = "fdt-2"; }; conf-3 { description = "fsl-ls1028a-kontron-sl28-var4"; firmware = "uboot"; - loadables = "uboot"; fdt = "fdt-3"; }; }; @@ -102,6 +99,81 @@ }; }; +#ifdef CONFIG_SL28_SPL_LOADS_ATF_BL31 +&binman { + fit { + images { + bl31 { + description = "ARM Trusted Firmware (bl31)"; + type = "firmware"; + arch = "arm"; + os = "arm-trusted-firmware"; + compression = "none"; + load = <CONFIG_SL28_BL31_ENTRY_ADDR>; + entry = <CONFIG_SL28_BL31_ENTRY_ADDR>; + + blob-ext { + filename = "bl31.bin"; + }; + }; + }; + + configurations { + conf-1 { + firmware = "bl31"; + loadables = "uboot"; + }; + + conf-2 { + firmware = "bl31"; + loadables = "uboot"; + }; + + conf-3 { + firmware = "bl31"; + loadables = "uboot"; + }; + }; + }; +}; +#endif + +#ifdef CONFIG_SL28_SPL_LOADS_OPTEE_BL32 +&binman { + fit { + images { + bl32 { + description = "OP-TEE Trusted OS (bl32)"; + type = "firmware"; + arch = "arm"; + os = "tee"; + compression = "none"; + load = <CONFIG_SL28_BL32_ENTRY_ADDR>; + entry = <CONFIG_SL28_BL32_ENTRY_ADDR>; + + blob-ext { + filename = "tee.bin"; + }; + }; + }; + + configurations { + conf-1 { + loadables = "uboot", "bl32"; + }; + + conf-2 { + loadables = "uboot", "bl32"; + }; + + conf-3 { + loadables = "uboot", "bl32"; + }; + }; + }; +}; +#endif + &i2c0 { rtc: rtc@32 { }; diff --git a/arch/arm/include/asm/arch-hi6220/gpio.h b/arch/arm/include/asm/arch-hi6220/gpio.h index c5ee359a3a..12717a96aa 100644 --- a/arch/arm/include/asm/arch-hi6220/gpio.h +++ b/arch/arm/include/asm/arch-hi6220/gpio.h @@ -18,7 +18,7 @@ struct gpio_bank { }; /* Information about a GPIO bank */ -struct hikey_gpio_platdata { +struct hikey_gpio_plat { int bank_index; ulong base; /* address of registers in physical memory */ }; diff --git a/arch/arm/include/asm/arch-imx8/power-domain.h b/arch/arm/include/asm/arch-imx8/power-domain.h index 1396008877..1db86a1209 100644 --- a/arch/arm/include/asm/arch-imx8/power-domain.h +++ b/arch/arm/include/asm/arch-imx8/power-domain.h @@ -8,7 +8,7 @@ #include <asm/arch/sci/types.h> -struct imx8_power_domain_platdata { +struct imx8_power_domain_plat { sc_rsrc_t resource_id; }; diff --git a/arch/arm/include/asm/arch-imx8m/power-domain.h b/arch/arm/include/asm/arch-imx8m/power-domain.h index 0f94945894..7a833e564b 100644 --- a/arch/arm/include/asm/arch-imx8m/power-domain.h +++ b/arch/arm/include/asm/arch-imx8m/power-domain.h @@ -6,7 +6,7 @@ #ifndef _ASM_ARCH_IMX8M_POWER_DOMAIN_H #define _ASM_ARCH_IMX8M_POWER_DOMAIN_H -struct imx8m_power_domain_platdata { +struct imx8m_power_domain_plat { int resource_id; int has_pd; struct power_domain pd; diff --git a/arch/arm/include/asm/arch-vf610/gpio.h b/arch/arm/include/asm/arch-vf610/gpio.h index 9bfdf16873..0b9e10f51e 100644 --- a/arch/arm/include/asm/arch-vf610/gpio.h +++ b/arch/arm/include/asm/arch-vf610/gpio.h @@ -20,7 +20,7 @@ struct vybrid_gpio_regs { u32 gpio_pdir; }; -struct vybrid_gpio_platdata { +struct vybrid_gpio_plat { unsigned int chip; u32 base; const char *port_name; diff --git a/arch/arm/include/asm/mach-imx/mxc_i2c.h b/arch/arm/include/asm/mach-imx/mxc_i2c.h index 81fd981444..c016aa7474 100644 --- a/arch/arm/include/asm/mach-imx/mxc_i2c.h +++ b/arch/arm/include/asm/mach-imx/mxc_i2c.h @@ -42,7 +42,7 @@ struct mxc_i2c_bus { /* * board file can use this index to locate which i2c_pads_info is for * i2c_idle_bus. When pinmux is implement, this entry can be - * discarded. Here we do not use dev->seq, because we do not want to + * discarded. Here we do not use dev_seq(dev), because we do not want to * export device to board file. */ int index; diff --git a/arch/arm/include/asm/omap_gpio.h b/arch/arm/include/asm/omap_gpio.h index 151afa8f44..4084210021 100644 --- a/arch/arm/include/asm/omap_gpio.h +++ b/arch/arm/include/asm/omap_gpio.h @@ -25,7 +25,7 @@ #if CONFIG_IS_ENABLED(DM_GPIO) /* Information about a GPIO bank */ -struct omap_gpio_platdata { +struct omap_gpio_plat { int bank_index; ulong base; /* address of registers in physical memory */ const char *port_name; diff --git a/arch/arm/include/asm/omap_i2c.h b/arch/arm/include/asm/omap_i2c.h index a6975401da..ec7a145f17 100644 --- a/arch/arm/include/asm/omap_i2c.h +++ b/arch/arm/include/asm/omap_i2c.h @@ -6,7 +6,7 @@ #ifdef CONFIG_DM_I2C /* Information about a GPIO bank */ -struct omap_i2c_platdata { +struct omap_i2c_plat { ulong base; /* address of registers in physical memory */ int speed; int ip_rev; diff --git a/arch/arm/include/asm/omap_musb.h b/arch/arm/include/asm/omap_musb.h index b40ea005be..614c93def8 100644 --- a/arch/arm/include/asm/omap_musb.h +++ b/arch/arm/include/asm/omap_musb.h @@ -23,7 +23,7 @@ struct omap_musb_board_data { enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI}; -struct ti_musb_platdata { +struct ti_musb_plat { void *base; void *ctrl_mod_base; struct musb_hdrc_platform_data plat; diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c index 02a49a8e10..fe46a7d7c9 100644 --- a/arch/arm/lib/bootm-fdt.c +++ b/arch/arm/lib/bootm-fdt.c @@ -63,7 +63,7 @@ int arch_fixup_fdt(void *blob) #endif #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV8_PSCI) || \ - defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI) + CONFIG_IS_ENABLED(SEC_FIRMWARE_ARMV8_PSCI) ret = psci_update_dt(blob); if (ret) return ret; diff --git a/arch/arm/lib/psci-dt.c b/arch/arm/lib/psci-dt.c index 0ed29a43f1..903b335704 100644 --- a/arch/arm/lib/psci-dt.c +++ b/arch/arm/lib/psci-dt.c @@ -10,7 +10,7 @@ #include <linux/sizes.h> #include <linux/kernel.h> #include <asm/psci.h> -#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) #include <asm/armv8/sec_firmware.h> #endif @@ -64,7 +64,7 @@ int fdt_psci(void *fdt) return nodeoff; init_psci_node: -#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) psci_ver = sec_firmware_support_psci_version(); #elif defined(CONFIG_ARMV7_PSCI_1_0) || defined(CONFIG_ARMV8_PSCI) psci_ver = ARM_PSCI_VER_1_0; @@ -85,7 +85,7 @@ init_psci_node: return tmp; } -#ifndef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#if !CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) /* * The Secure firmware framework isn't able to support PSCI version 0.1. */ diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c index 8122d2f98e..9d787197f3 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c @@ -213,7 +213,7 @@ void at91_sdram_hw_init(void) } /* Platform data for the GPIOs */ -static const struct at91_port_platdata at91sam9260_plat[] = { +static const struct at91_port_plat at91sam9260_plat[] = { { ATMEL_BASE_PIOA, "PA" }, { ATMEL_BASE_PIOB, "PB" }, { ATMEL_BASE_PIOC, "PC" }, diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c index 08ca3edd78..f503553b92 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c @@ -167,7 +167,7 @@ void at91_mci_hw_init(void) #endif /* Platform data for the GPIOs */ -static const struct at91_port_platdata at91sam9260_plat[] = { +static const struct at91_port_plat at91sam9260_plat[] = { { ATMEL_BASE_PIOA, "PA" }, { ATMEL_BASE_PIOB, "PB" }, { ATMEL_BASE_PIOC, "PC" }, diff --git a/arch/arm/mach-at91/include/mach/atmel_serial.h b/arch/arm/mach-at91/include/mach/atmel_serial.h index c53a509ff8..5d14269364 100644 --- a/arch/arm/mach-at91/include/mach/atmel_serial.h +++ b/arch/arm/mach-at91/include/mach/atmel_serial.h @@ -7,7 +7,7 @@ #define _ATMEL_SERIAL_H /* Information about a serial port */ -struct atmel_serial_platdata { +struct atmel_serial_plat { uint32_t base_addr; }; diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h index 575c6436ad..c1aef798b1 100644 --- a/arch/arm/mach-at91/include/mach/gpio.h +++ b/arch/arm/mach-at91/include/mach/gpio.h @@ -253,7 +253,7 @@ static inline unsigned at91_gpio_to_pin(unsigned gpio) } /* Platform data for each GPIO port */ -struct at91_port_platdata { +struct at91_port_plat { uint32_t base_addr; const char *bank_name; }; diff --git a/arch/arm/mach-bcm283x/include/mach/gpio.h b/arch/arm/mach-bcm283x/include/mach/gpio.h index 3263de9a35..4aeb48eeb2 100644 --- a/arch/arm/mach-bcm283x/include/mach/gpio.h +++ b/arch/arm/mach-bcm283x/include/mach/gpio.h @@ -52,11 +52,11 @@ struct bcm2835_gpio_regs { }; /** - * struct bcm2835_gpio_platdata - GPIO platform description + * struct bcm2835_gpio_plat - GPIO platform description * * @base: Base address of GPIO controller */ -struct bcm2835_gpio_platdata { +struct bcm2835_gpio_plat { unsigned long base; }; diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index f43a2460f9..1649f6d948 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -46,7 +46,7 @@ static const struct imx_thermal_plat imx6_thermal_plat = { U_BOOT_DEVICE(imx6_thermal) = { .name = "imx_thermal", - .platdata = &imx6_thermal_plat, + .plat = &imx6_thermal_plat, }; #endif diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index d0385b36e4..13593994f1 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -62,7 +62,7 @@ static const struct imx_thermal_plat imx7_thermal_plat = { U_BOOT_DEVICE(imx7_thermal) = { .name = "imx_thermal", - .platdata = &imx7_thermal_plat, + .plat = &imx7_thermal_plat, }; #endif diff --git a/arch/arm/mach-ipq40xx/clock-ipq4019.c b/arch/arm/mach-ipq40xx/clock-ipq4019.c index 31ae9719e8..c1d5c4ecdd 100644 --- a/arch/arm/mach-ipq40xx/clock-ipq4019.c +++ b/arch/arm/mach-ipq40xx/clock-ipq4019.c @@ -8,8 +8,8 @@ * */ -#include <common.h> #include <clk-uclass.h> +#include <common.h> #include <dm.h> #include <errno.h> @@ -25,9 +25,8 @@ ulong msm_set_rate(struct clk *clk, ulong rate) case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/ /* This clock is already initialized by SBL1 */ return 0; - break; default: - return 0; + return -EINVAL; } } @@ -35,7 +34,7 @@ static int msm_clk_probe(struct udevice *dev) { struct msm_clk_priv *priv = dev_get_priv(dev); - priv->base = devfdt_get_addr(dev); + priv->base = dev_read_addr(dev); if (priv->base == FDT_ADDR_T_NONE) return -EINVAL; @@ -53,13 +52,19 @@ static int msm_enable(struct clk *clk) case GCC_BLSP1_QUP1_SPI_APPS_CLK: /*SPI1*/ /* This clock is already initialized by SBL1 */ return 0; - break; case GCC_PRNG_AHB_CLK: /*PRNG*/ /* This clock is already initialized by SBL1 */ return 0; - break; - default: + case GCC_USB3_MASTER_CLK: + case GCC_USB3_SLEEP_CLK: + case GCC_USB3_MOCK_UTMI_CLK: + case GCC_USB2_MASTER_CLK: + case GCC_USB2_SLEEP_CLK: + case GCC_USB2_MOCK_UTMI_CLK: + /* These clocks is already initialized by SBL1 */ return 0; + default: + return -EINVAL; } } @@ -78,6 +83,6 @@ U_BOOT_DRIVER(clk_msm) = { .id = UCLASS_CLK, .of_match = msm_clk_ids, .ops = &msm_clk_ops, - .priv_auto_alloc_size = sizeof(struct msm_clk_priv), + .priv_auto = sizeof(struct msm_clk_priv), .probe = msm_clk_probe, }; diff --git a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c b/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c index 64b8b049fa..c51a75ee94 100644 --- a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c +++ b/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c @@ -131,7 +131,7 @@ U_BOOT_DRIVER(pinctrl_snapdraon) = { .name = "pinctrl_msm", .id = UCLASS_PINCTRL, .of_match = msm_pinctrl_ids, - .priv_auto_alloc_size = sizeof(struct msm_pinctrl_priv), + .priv_auto = sizeof(struct msm_pinctrl_priv), .ops = &msm_pinctrl_ops, .probe = msm_pinctrl_probe, }; diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c index 603834e507..0fed5aec59 100644 --- a/arch/arm/mach-k3/am6_init.c +++ b/arch/arm/mach-k3/am6_init.c @@ -208,7 +208,7 @@ void board_init_f(ulong dummy) * firmware (SYSFW) image for various purposes and SYSFW depends on us * to initialize its pin settings. */ - ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, true, &dev); + ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev); if (!ret) pinctrl_select_state(dev, "default"); diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c index a36e4ed603..0201690f93 100644 --- a/arch/arm/mach-k3/j721e_init.c +++ b/arch/arm/mach-k3/j721e_init.c @@ -167,7 +167,7 @@ void board_init_f(ulong dummy) * firmware (SYSFW) image for various purposes and SYSFW depends on us * to initialize its pin settings. */ - ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, true, &dev); + ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev); if (!ret) pinctrl_select_state(dev, "default"); diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c index 78c158c63f..708d9c8508 100644 --- a/arch/arm/mach-k3/sysfw-loader.c +++ b/arch/arm/mach-k3/sysfw-loader.c @@ -223,7 +223,7 @@ static void *k3_sysfw_get_spi_addr(void) int ret; ret = uclass_find_device_by_seq(UCLASS_SPI, CONFIG_SF_DEFAULT_BUS, - true, &dev); + &dev); if (ret) return NULL; diff --git a/arch/arm/mach-lpc32xx/devices.c b/arch/arm/mach-lpc32xx/devices.c index 7e7646a2e1..04e026a8b7 100644 --- a/arch/arm/mach-lpc32xx/devices.c +++ b/arch/arm/mach-lpc32xx/devices.c @@ -43,7 +43,7 @@ void lpc32xx_uart_init(unsigned int uart_id) } #if !CONFIG_IS_ENABLED(OF_CONTROL) -static const struct ns16550_platdata lpc32xx_uart[] = { +static const struct ns16550_plat lpc32xx_uart[] = { { .base = UART3_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, { .base = UART4_BASE, .reg_shift = 2, @@ -55,7 +55,7 @@ static const struct ns16550_platdata lpc32xx_uart[] = { }; #if defined(CONFIG_LPC32XX_HSUART) -static const struct lpc32xx_hsuart_platdata lpc32xx_hsuart[] = { +static const struct lpc32xx_hsuart_plat lpc32xx_hsuart[] = { { HS_UART1_BASE, }, { HS_UART2_BASE, }, { HS_UART7_BASE, }, diff --git a/arch/arm/mach-nexell/include/mach/display.h b/arch/arm/mach-nexell/include/mach/display.h index b167e63a5a..b0ee912605 100644 --- a/arch/arm/mach-nexell/include/mach/display.h +++ b/arch/arm/mach-nexell/include/mach/display.h @@ -212,7 +212,7 @@ struct dp_hdmi_dev { }; /* platform data for the driver model */ -struct nx_display_platdata { +struct nx_display_plat { int module; struct dp_sync_info sync; struct dp_ctrl_info ctrl; @@ -267,7 +267,7 @@ int dp_plane_wait_vsync(int module, int layer, int fps); #if defined CONFIG_SPL_BUILD || \ (!defined(CONFIG_DM) && !defined(CONFIG_OF_CONTROL)) -int nx_display_probe(struct nx_display_platdata *plat); +int nx_display_probe(struct nx_display_plat *plat); #endif #endif diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index 2888390d24..b5f2b75e24 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -80,7 +80,7 @@ int dram_init_banksize(void) } #if !CONFIG_IS_ENABLED(OF_CONTROL) -static const struct ns16550_platdata am33xx_serial[] = { +static const struct ns16550_plat am33xx_serial[] = { { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, # ifdef CONFIG_SYS_NS16550_COM2 @@ -113,7 +113,7 @@ U_BOOT_DEVICES(am33xx_uarts) = { }; #ifdef CONFIG_DM_I2C -static const struct omap_i2c_platdata am33xx_i2c[] = { +static const struct omap_i2c_plat am33xx_i2c[] = { { I2C_BASE1, 100000, OMAP_I2C_REV_V2}, { I2C_BASE2, 100000, OMAP_I2C_REV_V2}, { I2C_BASE3, 100000, OMAP_I2C_REV_V2}, @@ -127,7 +127,7 @@ U_BOOT_DEVICES(am33xx_i2c) = { #endif #if CONFIG_IS_ENABLED(DM_GPIO) -static const struct omap_gpio_platdata am33xx_gpio[] = { +static const struct omap_gpio_plat am33xx_gpio[] = { { 0, AM33XX_GPIO0_BASE }, { 1, AM33XX_GPIO1_BASE }, { 2, AM33XX_GPIO2_BASE }, @@ -157,7 +157,7 @@ static const struct omap3_spi_plat omap3_spi_pdata = { U_BOOT_DEVICE(am33xx_spi) = { .name = "omap3_spi", - .platdata = &omap3_spi_pdata, + .plat = &omap3_spi_pdata, }; #endif #endif @@ -214,7 +214,7 @@ static struct musb_hdrc_config musb_config = { }; #if CONFIG_IS_ENABLED(DM_USB) && !CONFIG_IS_ENABLED(OF_CONTROL) -static struct ti_musb_platdata usb0 = { +static struct ti_musb_plat usb0 = { .base = (void *)USB0_OTG_BASE, .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl0, .plat = { @@ -224,7 +224,7 @@ static struct ti_musb_platdata usb0 = { }, }; -static struct ti_musb_platdata usb1 = { +static struct ti_musb_plat usb1 = { .base = (void *)USB1_OTG_BASE, .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl1, .plat = { diff --git a/arch/arm/mach-omap2/omap3/board.c b/arch/arm/mach-omap2/omap3/board.c index f08c8ab43a..6ffedd1769 100644 --- a/arch/arm/mach-omap2/omap3/board.c +++ b/arch/arm/mach-omap2/omap3/board.c @@ -38,7 +38,7 @@ static void omap3_invalidate_l2_cache_secure(void); #if CONFIG_IS_ENABLED(DM_GPIO) #if !CONFIG_IS_ENABLED(OF_CONTROL) /* Manually initialize GPIO banks when OF_CONTROL doesn't */ -static const struct omap_gpio_platdata omap34xx_gpio[] = { +static const struct omap_gpio_plat omap34xx_gpio[] = { { 0, OMAP34XX_GPIO1_BASE }, { 1, OMAP34XX_GPIO2_BASE }, { 2, OMAP34XX_GPIO3_BASE }, diff --git a/arch/arm/mach-qemu/Kconfig b/arch/arm/mach-qemu/Kconfig index 588d2d3102..186c3582eb 100644 --- a/arch/arm/mach-qemu/Kconfig +++ b/arch/arm/mach-qemu/Kconfig @@ -16,12 +16,14 @@ choice config TARGET_QEMU_ARM_32BIT bool "ARMv7-A, 32bit" select ARCH_SUPPORT_PSCI + select BOARD_LATE_INIT select CPU_V7A select SYS_ARCH_TIMER config TARGET_QEMU_ARM_64BIT bool "ARMv8, 64bit" select ARM64 + select BOARD_LATE_INIT endchoice diff --git a/arch/arm/mach-rockchip/px30/syscon_px30.c b/arch/arm/mach-rockchip/px30/syscon_px30.c index 4672bdbf00..37e88f5ccb 100644 --- a/arch/arm/mach-rockchip/px30/syscon_px30.c +++ b/arch/arm/mach-rockchip/px30/syscon_px30.c @@ -23,7 +23,7 @@ U_BOOT_DRIVER(syscon_px30) = { }; #if CONFIG_IS_ENABLED(OF_PLATDATA) -static int px30_syscon_bind_of_platdata(struct udevice *dev) +static int px30_syscon_bind_of_plat(struct udevice *dev) { dev->driver_data = dev->driver->of_match->data; debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data); @@ -35,20 +35,20 @@ U_BOOT_DRIVER(rockchip_px30_pmu) = { .name = "rockchip_px30_pmu", .id = UCLASS_SYSCON, .of_match = px30_syscon_ids, - .bind = px30_syscon_bind_of_platdata, + .bind = px30_syscon_bind_of_plat, }; U_BOOT_DRIVER(rockchip_px30_pmugrf) = { .name = "rockchip_px30_pmugrf", .id = UCLASS_SYSCON, .of_match = px30_syscon_ids + 1, - .bind = px30_syscon_bind_of_platdata, + .bind = px30_syscon_bind_of_plat, }; U_BOOT_DRIVER(rockchip_px30_grf) = { .name = "rockchip_px30_grf", .id = UCLASS_SYSCON, .of_match = px30_syscon_ids + 2, - .bind = px30_syscon_bind_of_platdata, + .bind = px30_syscon_bind_of_plat, }; #endif diff --git a/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c b/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c index ea7d7b5b1a..917ff37c0f 100644 --- a/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c +++ b/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c @@ -24,7 +24,7 @@ U_BOOT_DRIVER(syscon_rk3188) = { }; #if CONFIG_IS_ENABLED(OF_PLATDATA) -static int rk3188_syscon_bind_of_platdata(struct udevice *dev) +static int rk3188_syscon_bind_of_plat(struct udevice *dev) { dev->driver_data = dev->driver->of_match->data; debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data); @@ -36,20 +36,20 @@ U_BOOT_DRIVER(rockchip_rk3188_noc) = { .name = "rockchip_rk3188_noc", .id = UCLASS_SYSCON, .of_match = rk3188_syscon_ids, - .bind = rk3188_syscon_bind_of_platdata, + .bind = rk3188_syscon_bind_of_plat, }; U_BOOT_DRIVER(rockchip_rk3188_grf) = { .name = "rockchip_rk3188_grf", .id = UCLASS_SYSCON, .of_match = rk3188_syscon_ids + 1, - .bind = rk3188_syscon_bind_of_platdata, + .bind = rk3188_syscon_bind_of_plat, }; U_BOOT_DRIVER(rockchip_rk3188_pmu) = { .name = "rockchip_rk3188_pmu", .id = UCLASS_SYSCON, .of_match = rk3188_syscon_ids + 2, - .bind = rk3188_syscon_bind_of_platdata, + .bind = rk3188_syscon_bind_of_plat, }; #endif diff --git a/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c b/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c index e3da0a0194..9c1ae880c7 100644 --- a/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c @@ -25,7 +25,7 @@ U_BOOT_DRIVER(syscon_rk3288) = { }; #if CONFIG_IS_ENABLED(OF_PLATDATA) -static int rk3288_syscon_bind_of_platdata(struct udevice *dev) +static int rk3288_syscon_bind_of_plat(struct udevice *dev) { dev->driver_data = dev->driver->of_match->data; debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data); @@ -37,27 +37,27 @@ U_BOOT_DRIVER(rockchip_rk3288_noc) = { .name = "rockchip_rk3288_noc", .id = UCLASS_SYSCON, .of_match = rk3288_syscon_ids, - .bind = rk3288_syscon_bind_of_platdata, + .bind = rk3288_syscon_bind_of_plat, }; U_BOOT_DRIVER(rockchip_rk3288_grf) = { .name = "rockchip_rk3288_grf", .id = UCLASS_SYSCON, .of_match = rk3288_syscon_ids + 1, - .bind = rk3288_syscon_bind_of_platdata, + .bind = rk3288_syscon_bind_of_plat, }; U_BOOT_DRIVER(rockchip_rk3288_sgrf) = { .name = "rockchip_rk3288_sgrf", .id = UCLASS_SYSCON, .of_match = rk3288_syscon_ids + 2, - .bind = rk3288_syscon_bind_of_platdata, + .bind = rk3288_syscon_bind_of_plat, }; U_BOOT_DRIVER(rockchip_rk3288_pmu) = { .name = "rockchip_rk3288_pmu", .id = UCLASS_SYSCON, .of_match = rk3288_syscon_ids + 3, - .bind = rk3288_syscon_bind_of_platdata, + .bind = rk3288_syscon_bind_of_plat, }; #endif diff --git a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c index cba0dda3e8..dc2d831dd8 100644 --- a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c @@ -30,7 +30,7 @@ U_BOOT_DRIVER(syscon_rk3368) = { }; #if CONFIG_IS_ENABLED(OF_PLATDATA) -static int rk3368_syscon_bind_of_platdata(struct udevice *dev) +static int rk3368_syscon_bind_of_plat(struct udevice *dev) { dev->driver_data = dev->driver->of_match->data; debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data); @@ -42,27 +42,27 @@ U_BOOT_DRIVER(rockchip_rk3368_grf) = { .name = "rockchip_rk3368_grf", .id = UCLASS_SYSCON, .of_match = rk3368_syscon_ids, - .bind = rk3368_syscon_bind_of_platdata, + .bind = rk3368_syscon_bind_of_plat, }; U_BOOT_DRIVER(rockchip_rk3368_pmugrf) = { .name = "rockchip_rk3368_pmugrf", .id = UCLASS_SYSCON, .of_match = rk3368_syscon_ids + 1, - .bind = rk3368_syscon_bind_of_platdata, + .bind = rk3368_syscon_bind_of_plat, }; U_BOOT_DRIVER(rockchip_rk3368_msch) = { .name = "rockchip_rk3368_msch", .id = UCLASS_SYSCON, .of_match = rk3368_syscon_ids + 2, - .bind = rk3368_syscon_bind_of_platdata, + .bind = rk3368_syscon_bind_of_plat, }; U_BOOT_DRIVER(rockchip_rk3368_sgrf) = { .name = "rockchip_rk3368_sgrf", .id = UCLASS_SYSCON, .of_match = rk3368_syscon_ids + 3, - .bind = rk3368_syscon_bind_of_platdata, + .bind = rk3368_syscon_bind_of_plat, }; #endif diff --git a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c index 690cbe7f27..b360ca7dde 100644 --- a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c @@ -28,7 +28,7 @@ U_BOOT_DRIVER(syscon_rk3399) = { }; #if CONFIG_IS_ENABLED(OF_PLATDATA) -static int rk3399_syscon_bind_of_platdata(struct udevice *dev) +static int rk3399_syscon_bind_of_plat(struct udevice *dev) { dev->driver_data = dev->driver->of_match->data; debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data); @@ -40,34 +40,34 @@ U_BOOT_DRIVER(rockchip_rk3399_grf) = { .name = "rockchip_rk3399_grf", .id = UCLASS_SYSCON, .of_match = rk3399_syscon_ids, - .bind = rk3399_syscon_bind_of_platdata, + .bind = rk3399_syscon_bind_of_plat, }; U_BOOT_DRIVER(rockchip_rk3399_pmugrf) = { .name = "rockchip_rk3399_pmugrf", .id = UCLASS_SYSCON, .of_match = rk3399_syscon_ids + 1, - .bind = rk3399_syscon_bind_of_platdata, + .bind = rk3399_syscon_bind_of_plat, }; U_BOOT_DRIVER(rockchip_rk3399_pmusgrf) = { .name = "rockchip_rk3399_pmusgrf", .id = UCLASS_SYSCON, .of_match = rk3399_syscon_ids + 2, - .bind = rk3399_syscon_bind_of_platdata, + .bind = rk3399_syscon_bind_of_plat, }; U_BOOT_DRIVER(rockchip_rk3399_cic) = { .name = "rockchip_rk3399_cic", .id = UCLASS_SYSCON, .of_match = rk3399_syscon_ids + 3, - .bind = rk3399_syscon_bind_of_platdata, + .bind = rk3399_syscon_bind_of_plat, }; U_BOOT_DRIVER(rockchip_rk3399_pmu) = { .name = "rockchip_rk3399_pmu", .id = UCLASS_SYSCON, .of_match = rk3399_syscon_ids + 4, - .bind = rk3399_syscon_bind_of_platdata, + .bind = rk3399_syscon_bind_of_plat, }; #endif diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c index 94673f34c9..8ccd5afb56 100644 --- a/arch/arm/mach-rockchip/spl-boot-order.c +++ b/arch/arm/mach-rockchip/spl-boot-order.c @@ -46,7 +46,7 @@ static int spl_node_to_boot_device(int node) dev; device_find_next_child(&dev)) { if (device_get_uclass_id(dev) == UCLASS_BLK) { - desc = dev_get_uclass_platdata(dev); + desc = dev_get_uclass_plat(dev); break; } } @@ -99,7 +99,7 @@ __weak const char *board_spl_was_booted_from(void) void board_boot_order(u32 *spl_boot_list) { - /* In case of no fdt (or only platdata), use spl_boot_device() */ + /* In case of no fdt (or only plat), use spl_boot_device() */ if (!CONFIG_IS_ENABLED(OF_CONTROL) || CONFIG_IS_ENABLED(OF_PLATDATA)) { spl_boot_list[0] = spl_boot_device(); return; diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c b/arch/arm/mach-snapdragon/clock-snapdragon.c index 69d65c82e3..fbe0b5212f 100644 --- a/arch/arm/mach-snapdragon/clock-snapdragon.c +++ b/arch/arm/mach-snapdragon/clock-snapdragon.c @@ -143,6 +143,6 @@ U_BOOT_DRIVER(clk_msm) = { .id = UCLASS_CLK, .of_match = msm_clk_ids, .ops = &msm_clk_ops, - .priv_auto_alloc_size = sizeof(struct msm_clk_priv), + .priv_auto = sizeof(struct msm_clk_priv), .probe = msm_clk_probe, }; diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c index 4c2af21308..e6b87c3573 100644 --- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c @@ -123,7 +123,7 @@ U_BOOT_DRIVER(pinctrl_snapdraon) = { .name = "pinctrl_msm", .id = UCLASS_PINCTRL, .of_match = msm_pinctrl_ids, - .priv_auto_alloc_size = sizeof(struct msm_pinctrl_priv), + .priv_auto = sizeof(struct msm_pinctrl_priv), .ops = &msm_pinctrl_ops, .probe = msm_pinctrl_probe, }; diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c index a9b9bd0902..85a9e6f84e 100644 --- a/arch/arm/mach-stm32mp/bsec.c +++ b/arch/arm/mach-stm32mp/bsec.c @@ -280,13 +280,13 @@ static int bsec_program_otp(long base, u32 val, u32 otp) } /* BSEC MISC driver *******************************************************/ -struct stm32mp_bsec_platdata { +struct stm32mp_bsec_plat { u32 base; }; static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp) { - struct stm32mp_bsec_platdata *plat; + struct stm32mp_bsec_plat *plat; u32 tmp_data = 0; int ret; @@ -295,7 +295,7 @@ static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp) STM32_SMC_READ_OTP, otp, 0, val); - plat = dev_get_platdata(dev); + plat = dev_get_plat(dev); /* read current shadow value */ ret = bsec_read_shadow(plat->base, &tmp_data, otp); @@ -319,21 +319,21 @@ static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp) static int stm32mp_bsec_read_shadow(struct udevice *dev, u32 *val, u32 otp) { - struct stm32mp_bsec_platdata *plat; + struct stm32mp_bsec_plat *plat; if (IS_ENABLED(CONFIG_TFABOOT)) return stm32_smc(STM32_SMC_BSEC, STM32_SMC_READ_SHADOW, otp, 0, val); - plat = dev_get_platdata(dev); + plat = dev_get_plat(dev); return bsec_read_shadow(plat->base, val, otp); } static int stm32mp_bsec_read_lock(struct udevice *dev, u32 *val, u32 otp) { - struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev); + struct stm32mp_bsec_plat *plat = dev_get_plat(dev); /* return OTP permanent write lock status */ *val = bsec_read_lock(plat->base + BSEC_WRLOCK_OFF, otp); @@ -343,14 +343,14 @@ static int stm32mp_bsec_read_lock(struct udevice *dev, u32 *val, u32 otp) static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp) { - struct stm32mp_bsec_platdata *plat; + struct stm32mp_bsec_plat *plat; if (IS_ENABLED(CONFIG_TFABOOT)) return stm32_smc_exec(STM32_SMC_BSEC, STM32_SMC_PROG_OTP, otp, val); - plat = dev_get_platdata(dev); + plat = dev_get_plat(dev); return bsec_program_otp(plat->base, val, otp); @@ -358,14 +358,14 @@ static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp) static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp) { - struct stm32mp_bsec_platdata *plat; + struct stm32mp_bsec_plat *plat; if (IS_ENABLED(CONFIG_TFABOOT)) return stm32_smc_exec(STM32_SMC_BSEC, STM32_SMC_WRITE_SHADOW, otp, val); - plat = dev_get_platdata(dev); + plat = dev_get_plat(dev); return bsec_write_shadow(plat->base, val, otp); } @@ -473,9 +473,9 @@ static const struct misc_ops stm32mp_bsec_ops = { .write = stm32mp_bsec_write, }; -static int stm32mp_bsec_ofdata_to_platdata(struct udevice *dev) +static int stm32mp_bsec_of_to_plat(struct udevice *dev) { - struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev); + struct stm32mp_bsec_plat *plat = dev_get_plat(dev); plat->base = (u32)dev_read_addr_ptr(dev); @@ -485,7 +485,7 @@ static int stm32mp_bsec_ofdata_to_platdata(struct udevice *dev) static int stm32mp_bsec_probe(struct udevice *dev) { int otp; - struct stm32mp_bsec_platdata *plat; + struct stm32mp_bsec_plat *plat; /* * update unlocked shadow for OTP cleared by the rom code @@ -493,7 +493,7 @@ static int stm32mp_bsec_probe(struct udevice *dev) */ if (!IS_ENABLED(CONFIG_TFABOOT) && !IS_ENABLED(CONFIG_SPL_BUILD)) { - plat = dev_get_platdata(dev); + plat = dev_get_plat(dev); for (otp = 57; otp <= BSEC_OTP_MAX_VALUE; otp++) if (!bsec_read_SR_lock(plat->base, otp)) @@ -512,8 +512,8 @@ U_BOOT_DRIVER(stm32mp_bsec) = { .name = "stm32mp_bsec", .id = UCLASS_MISC, .of_match = stm32mp_bsec_ids, - .ofdata_to_platdata = stm32mp_bsec_ofdata_to_platdata, - .platdata_auto_alloc_size = sizeof(struct stm32mp_bsec_platdata), + .of_to_plat = stm32mp_bsec_of_to_plat, + .plat_auto = sizeof(struct stm32mp_bsec_plat), .ops = &stm32mp_bsec_ops, .probe = stm32mp_bsec_probe, }; @@ -521,7 +521,7 @@ U_BOOT_DRIVER(stm32mp_bsec) = { bool bsec_dbgswenable(void) { struct udevice *dev; - struct stm32mp_bsec_platdata *plat; + struct stm32mp_bsec_plat *plat; int ret; ret = uclass_get_device_by_driver(UCLASS_MISC, @@ -531,7 +531,7 @@ bool bsec_dbgswenable(void) return false; } - plat = dev_get_platdata(dev); + plat = dev_get_plat(dev); if (readl(plat->base + BSEC_DENABLE_OFF) & BSEC_DENABLE_DBGSWENABLE) return true; diff --git a/arch/arm/mach-stm32mp/pwr_regulator.c b/arch/arm/mach-stm32mp/pwr_regulator.c index 900dee4c38..74a5df5948 100644 --- a/arch/arm/mach-stm32mp/pwr_regulator.c +++ b/arch/arm/mach-stm32mp/pwr_regulator.c @@ -59,7 +59,7 @@ static int stm32mp_pwr_read(struct udevice *dev, uint reg, uint8_t *buff, return 0; } -static int stm32mp_pwr_ofdata_to_platdata(struct udevice *dev) +static int stm32mp_pwr_of_to_plat(struct udevice *dev) { struct stm32mp_pwr_priv *priv = dev_get_priv(dev); @@ -103,8 +103,8 @@ U_BOOT_DRIVER(stm32mp_pwr_pmic) = { .of_match = stm32mp_pwr_ids, .bind = stm32mp_pwr_bind, .ops = &stm32mp_pwr_ops, - .ofdata_to_platdata = stm32mp_pwr_ofdata_to_platdata, - .priv_auto_alloc_size = sizeof(struct stm32mp_pwr_priv), + .of_to_plat = stm32mp_pwr_of_to_plat, + .priv_auto = sizeof(struct stm32mp_pwr_priv), }; static const struct stm32mp_pwr_reg_info stm32mp_pwr_reg11 = { @@ -135,9 +135,9 @@ static const struct stm32mp_pwr_reg_info *stm32mp_pwr_reg_infos[] = { static int stm32mp_pwr_regulator_probe(struct udevice *dev) { const struct stm32mp_pwr_reg_info **p = stm32mp_pwr_reg_infos; - struct dm_regulator_uclass_platdata *uc_pdata; + struct dm_regulator_uclass_plat *uc_pdata; - uc_pdata = dev_get_uclass_platdata(dev); + uc_pdata = dev_get_uclass_plat(dev); while (*p) { int rc; @@ -172,9 +172,9 @@ static int stm32mp_pwr_regulator_probe(struct udevice *dev) static int stm32mp_pwr_regulator_set_value(struct udevice *dev, int uV) { - struct dm_regulator_uclass_platdata *uc_pdata; + struct dm_regulator_uclass_plat *uc_pdata; - uc_pdata = dev_get_uclass_platdata(dev); + uc_pdata = dev_get_uclass_plat(dev); if (!uc_pdata) return -ENXIO; @@ -188,9 +188,9 @@ static int stm32mp_pwr_regulator_set_value(struct udevice *dev, int uV) static int stm32mp_pwr_regulator_get_value(struct udevice *dev) { - struct dm_regulator_uclass_platdata *uc_pdata; + struct dm_regulator_uclass_plat *uc_pdata; - uc_pdata = dev_get_uclass_platdata(dev); + uc_pdata = dev_get_uclass_plat(dev); if (!uc_pdata) return -ENXIO; diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index 03faacbd57..bf01aa5ee8 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -257,7 +257,7 @@ void board_init_uart_f(void) } #if !CONFIG_IS_ENABLED(OF_CONTROL) -static struct ns16550_platdata ns16550_com1_pdata = { +static struct ns16550_plat ns16550_com1_pdata = { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK, |