diff options
Diffstat (limited to 'arch/arm/dts/uniphier-ph1-sld3.dtsi')
| -rw-r--r-- | arch/arm/dts/uniphier-ph1-sld3.dtsi | 94 |
1 files changed, 69 insertions, 25 deletions
diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi index 6a95541311..a554b086e8 100644 --- a/arch/arm/dts/uniphier-ph1-sld3.dtsi +++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi @@ -42,12 +42,6 @@ clock-frequency = <50000000>; }; - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <36864000>; - }; - iobus_clk: iobus_clk { #clock-cells = <0>; compatible = "fixed-clock"; @@ -90,7 +84,8 @@ status = "disabled"; reg = <0x54006800 0x40>; interrupts = <0 33 4>; - clocks = <&uart_clk>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; clock-frequency = <36864000>; }; @@ -99,7 +94,8 @@ status = "disabled"; reg = <0x54006900 0x40>; interrupts = <0 35 4>; - clocks = <&uart_clk>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; clock-frequency = <36864000>; }; @@ -108,7 +104,8 @@ status = "disabled"; reg = <0x54006a00 0x40>; interrupts = <0 37 4>; - clocks = <&uart_clk>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; clock-frequency = <36864000>; }; @@ -231,6 +228,8 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <0 41 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; clocks = <&iobus_clk>; clock-frequency = <100000>; }; @@ -291,12 +290,22 @@ reg = <0x59801000 0x400>; }; - mio: mioctrl@59810000 { - compatible = "socionext,ph1-sld3-mioctrl"; + mioctrl@59810000 { + compatible = "socionext,uniphier-mioctrl", + "simple-mfd", "syscon"; reg = <0x59810000 0x800>; - #clock-cells = <1>; - clock-names = "stdmac", "ehci"; - clocks = <&sysctrl 10>, <&sysctrl 18>; + u-boot,dm-pre-reloc; + + mio_clk: clock { + compatible = "socionext,uniphier-sld3-mio-clock"; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + mio_rst: reset { + compatible = "socionext,uniphier-sld3-mio-reset"; + #reset-cells = <1>; + }; }; emmc: sdhc@5a400000 { @@ -304,7 +313,10 @@ status = "disabled"; reg = <0x5a400000 0x200>; interrupts = <0 78 4>; - clocks = <&mio 1>; + pinctrl-names = "default", "1.8v"; + pinctrl-0 = <&pinctrl_emmc>; + pinctrl-1 = <&pinctrl_emmc_1v8>; + clocks = <&mio_clk 1>; bus-width = <8>; non-removable; }; @@ -314,7 +326,10 @@ status = "disabled"; reg = <0x5a500000 0x200>; interrupts = <0 76 4>; - clocks = <&mio 0>; + pinctrl-names = "default", "1.8v"; + pinctrl-0 = <&pinctrl_sd>; + pinctrl-1 = <&pinctrl_sd_1v8>; + clocks = <&mio_clk 0>; bus-width = <4>; }; @@ -323,7 +338,9 @@ status = "disabled"; reg = <0x5a800100 0x100>; interrupts = <0 80 4>; - clocks = <&mio 3>, <&mio 6>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + clocks = <&mio_clk 3>, <&mio_clk 6>; }; usb1: usb@5a810100 { @@ -331,7 +348,9 @@ status = "disabled"; reg = <0x5a810100 0x100>; interrupts = <0 81 4>; - clocks = <&mio 4>, <&mio 6>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + clocks = <&mio_clk 4>, <&mio_clk 6>; }; usb2: usb@5a820100 { @@ -339,7 +358,9 @@ status = "disabled"; reg = <0x5a820100 0x100>; interrupts = <0 82 4>; - clocks = <&mio 5>, <&mio 6>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + clocks = <&mio_clk 5>, <&mio_clk 6>; }; usb3: usb@5a830100 { @@ -347,7 +368,20 @@ status = "disabled"; reg = <0x5a830100 0x100>; interrupts = <0 83 4>; - clocks = <&mio 7>, <&mio 6>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3>; + clocks = <&mio_clk 7>, <&mio_clk 6>; + }; + + soc-glue@5f800000 { + compatible = "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + u-boot,dm-pre-reloc; + + pinctrl: pinctrl { + compatible = "socionext,uniphier-sld3-pinctrl"; + u-boot,dm-pre-reloc; + }; }; aidet@f1830000 { @@ -355,12 +389,20 @@ reg = <0xf1830000 0x200>; }; - sysctrl: sysctrl@f1840000 { - compatible = "socionext,ph1-sld3-sysctrl"; + sysctrl@f1840000 { + compatible = "socionext,uniphier-sysctrl", + "simple-mfd", "syscon"; reg = <0xf1840000 0x4000>; - #clock-cells = <1>; - clock-names = "ref"; - clocks = <&refclk>; + + sys_clk: clock { + compatible = "socionext,uniphier-sld3-clock"; + #clock-cells = <1>; + }; + + sys_rst: reset { + compatible = "socionext,uniphier-sld3-reset"; + #reset-cells = <1>; + }; }; nand: nand@f8000000 { @@ -370,3 +412,5 @@ }; }; }; + +/include/ "uniphier-pinctrl.dtsi" |