diff options
369 files changed, 11360 insertions, 6493 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index ea21d59f1e..6147a4ffaf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -210,6 +210,7 @@ S: Maintained F: arch/arm/mach-snapdragon/ F: drivers/gpio/msm_gpio.c F: drivers/mmc/msm_sdhci.c +F: drivers/phy/msm8916-usbh-phy.c F: drivers/serial/serial_msm.c F: drivers/smem/msm_smem.c F: drivers/usb/host/ehci-msm.c @@ -440,6 +441,12 @@ F: cmd/log.c F: test/log/log_test.c F: test/py/tests/test_log.py +MALI DISPLAY PROCESSORS +M: Liviu Dudau <liviu.dudau@foss.arm.com> +S: Supported +T: git git://github.com/ARM-software/u-boot.git +F: drivers/video/mali_dp.c + MICROBLAZE M: Michal Simek <monstr@monstr.eu> S: Maintained @@ -589,6 +596,11 @@ S: Maintained F: drivers/spmi/ F: include/spmi/ +TDA19988 HDMI ENCODER +M: Liviu Dudau <liviu.dudau@foss.arm.com> +S: Maintained +F: drivers/video/tda19988.c + TI SYSTEM SECURITY M: Andrew F. Davis <afd@ti.com> S: Supported @@ -636,6 +648,7 @@ T: git git://git.denx.de/u-boot-video.git F: drivers/video/ F: common/lcd*.c F: include/lcd*.h +F: include/video*.h X86 M: Simon Glass <sjg@chromium.org> @@ -861,6 +861,10 @@ ifneq ($(CONFIG_SYS_INIT_SP_BSS_OFFSET),) ALL-y += init_sp_bss_offset_check endif +ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy) +ALL-y += u-boot-with-dtb.bin +endif + LDFLAGS_u-boot += $(LDFLAGS_FINAL) # Avoid 'Not enough room for program headers' error on binutils 2.28 onwards. @@ -983,7 +987,8 @@ spl/u-boot-spl.srec: spl/u-boot-spl FORCE $(call if_changed,objcopy) OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \ - $(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) + $(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \ + $(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),-R .bootpg -R .resetvec) OBJCOPYFLAGS_u-boot-spl.hex = $(OBJCOPYFLAGS_u-boot.hex) @@ -1207,6 +1212,18 @@ u-boot-with-spl.sfp: spl/u-boot-spl.sfp u-boot.img FORCE $(call if_changed,socboot) endif +ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy) +u-boot-with-dtb.bin: u-boot.bin u-boot.dtb \ + $(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR), u-boot-br.bin) FORCE + $(call if_changed,binman) + +ifeq ($(CONFIG_MPC85XX_HAVE_RESET_VECTOR),y) +OBJCOPYFLAGS_u-boot-br.bin := -O binary -j .bootpg -j .resetvec +u-boot-br.bin: u-boot FORCE + $(call if_changed,objcopy) +endif +endif + # x86 uses a large ROM. We fill it with 0xff, put the 16-bit stuff (including # reset vector) at the top, Intel ME descriptor at the bottom, and U-Boot in # the middle. This is handled by binman based on an image description in the @@ -1301,8 +1318,12 @@ spl/u-boot-spl.pbl: spl/u-boot-spl.bin FORCE ifeq ($(ARCH),arm) UBOOT_BINLOAD := u-boot.img else +ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy) +UBOOT_BINLOAD := u-boot-with-dtb.bin +else UBOOT_BINLOAD := u-boot.bin endif +endif OBJCOPYFLAGS_u-boot-with-spl-pbl.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \ --gap-fill=0xff diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile index f8300c7775..0c1596f330 100644 --- a/arch/arm/cpu/armv7/ls102xa/Makefile +++ b/arch/arm/cpu/armv7/ls102xa/Makefile @@ -10,7 +10,6 @@ obj-y += timer.o obj-y += fsl_epu.o obj-y += soc.o -obj-$(CONFIG_SCSI_AHCI_PLAT) += ls102xa_sata.o obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o obj-$(CONFIG_SPL) += spl.o diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c index af413f8622..bb169aaaf4 100644 --- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c +++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c @@ -73,6 +73,7 @@ static void __secure ls1_deepsleep_irq_cfg(void) * read, that is why we don't read it from register ippdexpcr1 itself. */ ippdexpcr1 = in_le32(&scfg->sparecr[7]); + out_be32(&rcpm->ippdexpcr1, ippdexpcr1); if (ippdexpcr0 & RCPM_IPPDEXPCR0_ETSEC) pmcintecr |= SCFG_PMCINTECR_ETSECRXG0 | @@ -192,6 +193,9 @@ static void __secure ls1_deep_sleep(u32 entry_point) setbits_be32(&scfg->dpslpcr, SCFG_DPSLPCR_WDRR_EN); setbits_be32(&gur->crstsr, DCFG_CRSTSR_WDRFR); + /* Disable QE */ + setbits_be32(&gur->devdisr, CCSR_DEVDISR1_QE); + ls1_deepsleep_irq_cfg(); psci_v7_flush_dcache_all(); diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c deleted file mode 100644 index c9fe7522fb..0000000000 --- a/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ -#include <common.h> -#include <asm/io.h> -#include <asm/arch/immap_ls102xa.h> -#include <ahci.h> -#include <scsi.h> - -/* port register default value */ -#define AHCI_PORT_PHY_1_CFG 0xa003fffe -#define AHCI_PORT_PHY_2_CFG 0x28183414 -#define AHCI_PORT_PHY_3_CFG 0x0e080e06 -#define AHCI_PORT_PHY_4_CFG 0x064a080b -#define AHCI_PORT_PHY_5_CFG 0x2aa86470 -#define AHCI_PORT_TRANS_CFG 0x08000029 - -#define SATA_ECC_REG_ADDR 0x20220520 -#define SATA_ECC_DISABLE 0x00020000 - -int ls1021a_sata_init(void) -{ - struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR; - -#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 - out_le32((void *)SATA_ECC_REG_ADDR, SATA_ECC_DISABLE); -#endif - - out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); - out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG); - out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG); - out_le32(&ccsr_ahci->pp4c, AHCI_PORT_PHY_4_CFG); - out_le32(&ccsr_ahci->pp5c, AHCI_PORT_PHY_5_CFG); - out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); - - ahci_init((void __iomem *)AHCI_BASE_ADDR); - scsi_scan(false); - - return 0; -} diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index 5d6f68aad6..91fdbad8be 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -29,6 +29,7 @@ endif ifneq ($(CONFIG_ARCH_LS1043A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o obj-$(CONFIG_ARMV8_PSCI) += ls1043a_psci.o +obj-y += icid.o ls1043_ids.o endif ifneq ($(CONFIG_ARCH_LS1012A),) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index 653c6dddca..bc268e207c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -192,6 +192,16 @@ int get_dspi_freq(ulong dummy) return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV; } +#ifdef CONFIG_FSL_ESDHC +int get_sdhc_freq(ulong dummy) +{ + if (!gd->arch.sdhc_clk) + get_clocks(); + + return gd->arch.sdhc_clk; +} +#endif + int get_serial_clock(void) { return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV; @@ -202,6 +212,10 @@ unsigned int mxc_get_clock(enum mxc_clock clk) switch (clk) { case MXC_I2C_CLK: return get_i2c_freq(0); +#if defined(CONFIG_FSL_ESDHC) + case MXC_ESDHC_CLK: + return get_sdhc_freq(0); +#endif case MXC_DSPI_CLK: return get_dspi_freq(0); default: diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c new file mode 100644 index 0000000000..0e8649427e --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <common.h> +#include <asm/arch-fsl-layerscape/immap_lsch2.h> +#include <asm/arch-fsl-layerscape/fsl_icid.h> +#include <asm/arch-fsl-layerscape/fsl_portals.h> +#include <fsl_sec.h> + +#ifdef CONFIG_SYS_DPAA_QBMAN +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), +}; +#endif + +struct icid_id_table icid_tbl[] = { +#ifdef CONFIG_SYS_DPAA_QBMAN + SET_QMAN_ICID(FSL_DPAA1_STREAM_ID_START), + SET_BMAN_ICID(FSL_DPAA1_STREAM_ID_START + 1), +#endif + + SET_SDHC_ICID(FSL_SDHC_STREAM_ID), + + SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID), + SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID), + SET_USB_ICID(3, "snps,dwc3", FSL_USB3_STREAM_ID), + + SET_SATA_ICID("fsl,ls1043a-ahci", FSL_SATA_STREAM_ID), + SET_QDMA_ICID("fsl,ls1043a-qdma", FSL_QDMA_STREAM_ID), + SET_EDMA_ICID(FSL_EDMA_STREAM_ID), + SET_ETR_ICID(FSL_ETR_STREAM_ID), + SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID), + SET_QE_ICID(FSL_QE_STREAM_ID), +#ifdef CONFIG_FSL_CAAM + SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_START + 2), + SET_SEC_JR_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 3), + SET_SEC_JR_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 4), + SET_SEC_JR_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 5), + SET_SEC_JR_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 6), + SET_SEC_RTIC_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 7), + SET_SEC_RTIC_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 8), + SET_SEC_RTIC_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 9), + SET_SEC_RTIC_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 10), + SET_SEC_DECO_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 11), + SET_SEC_DECO_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 12), +#endif +}; + +int icid_tbl_sz = ARRAY_SIZE(icid_tbl); + +#ifdef CONFIG_SYS_DPAA_FMAN +struct fman_icid_id_table fman_icid_tbl[] = { + /* port id, icid */ + SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x03, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x04, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x05, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x06, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x07, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x08, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x09, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x0a, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x0b, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x0c, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x0d, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x28, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x29, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x2a, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x2b, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x2c, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x2d, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x10, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x11, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x30, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x31, FSL_DPAA1_STREAM_ID_END), +}; + +int fman_icid_tbl_sz = ARRAY_SIZE(fman_icid_tbl); +#endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c index a31c4d93ab..d391f93041 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c @@ -99,7 +99,7 @@ int ppa_init(void) cnt = DIV_ROUND_UP(fdt_header_len, 512); debug("%s: MMC read PPA FIT header: dev # %u, block # %u, count %u\n", __func__, dev, blk, cnt); - ret = mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, fitp); + ret = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, fitp); if (ret != cnt) { free(fitp); printf("MMC/SD read of PPA FIT header at offset 0x%x failed\n", @@ -123,7 +123,7 @@ int ppa_init(void) blk = CONFIG_SYS_LS_PPA_ESBC_ADDR >> 9; cnt = DIV_ROUND_UP(CONFIG_LS_PPA_ESBC_HDR_SIZE, 512); - ret = mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, ppa_hdr_ddr); + ret = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, ppa_hdr_ddr); if (ret != cnt) { free(ppa_hdr_ddr); printf("MMC/SD read of PPA header failed\n"); @@ -149,8 +149,7 @@ int ppa_init(void) cnt = DIV_ROUND_UP(fw_length, 512); debug("%s: MMC read PPA FIT image: dev # %u, block # %u, count %u\n", __func__, dev, blk, cnt); - ret = mmc->block_dev.block_read(&mmc->block_dev, - blk, cnt, ppa_fit_addr); + ret = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, ppa_fit_addr); if (ret != cnt) { free(ppa_fit_addr); printf("MMC/SD read of PPA FIT header at offset 0x%x failed\n", diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 3f15cb08ff..54fb0745f9 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -634,7 +634,7 @@ void fsl_lsch2_early_init_f(void) erratum_a008997(); erratum_a009007(); -#ifdef CONFIG_ARCH_LS1046A +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) set_icids(); #endif } diff --git a/arch/arm/dts/am3517-evm-u-boot.dtsi b/arch/arm/dts/am3517-evm-u-boot.dtsi index c02beaad77..59df819f9d 100644 --- a/arch/arm/dts/am3517-evm-u-boot.dtsi +++ b/arch/arm/dts/am3517-evm-u-boot.dtsi @@ -10,10 +10,6 @@ }; }; -&mmc1 { - cd-inverted; -}; - &uart1 { reg-shift = <2>; }; diff --git a/arch/arm/dts/at91-sama5d27_som1_ek.dts b/arch/arm/dts/at91-sama5d27_som1_ek.dts index 5e62d4af71..4cd6db66fe 100644 --- a/arch/arm/dts/at91-sama5d27_som1_ek.dts +++ b/arch/arm/dts/at91-sama5d27_som1_ek.dts @@ -54,6 +54,18 @@ stdout-path = &uart1; }; + onewire_tm: onewire { + gpios = <&pioA 17 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_onewire_tm_default>; + status = "okay"; + + w1_eeprom: w1_eeprom@0 { + compatible = "maxim,ds24b33"; + status = "okay"; + }; + }; + ahb { usb1: ohci@00400000 { num-ports = <3>; @@ -208,6 +220,11 @@ pinmux = <PIN_PA31__GPIO>; bias-disable; }; + + pinctrl_onewire_tm_default: onewire_tm_default { + pinmux = <PIN_PA17__GPIO>; + bias-pull-up; + }; }; }; }; diff --git a/arch/arm/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/dts/at91-sama5d2_ptc_ek.dts index ab5ab21895..068a117585 100644 --- a/arch/arm/dts/at91-sama5d2_ptc_ek.dts +++ b/arch/arm/dts/at91-sama5d2_ptc_ek.dts @@ -56,6 +56,18 @@ stdout-path = &uart0; }; + onewire_tm: onewire { + gpios = <&pioA PIN_PB31 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_onewire_tm_default>; + status = "okay"; + + w1_eeprom: w1_eeprom@0 { + compatible = "maxim,ds24b33"; + status = "okay"; + }; + }; + ahb { usb0: gadget@00300000 { atmel,vbus-gpio = <&pioA PIN_PA27 GPIO_ACTIVE_HIGH>; @@ -208,6 +220,11 @@ pinmux = <PIN_PB11__GPIO>; bias-disable; }; + + pinctrl_onewire_tm_default: onewire_tm_default { + pinmux = <PIN_PB31__GPIO>; + bias-pull-up; + }; }; }; }; diff --git a/arch/arm/dts/at91-sama5d2_xplained.dts b/arch/arm/dts/at91-sama5d2_xplained.dts index 01326a1ee0..33064b390a 100644 --- a/arch/arm/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/dts/at91-sama5d2_xplained.dts @@ -11,6 +11,18 @@ stdout-path = &uart1; }; + onewire_tm: onewire { + gpios = <&pioA PIN_PB0 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_onewire_tm_default>; + status = "okay"; + + w1_eeprom: w1_eeprom@0 { + compatible = "maxim,ds24b33"; + status = "okay"; + }; + }; + ahb { usb1: ohci@00400000 { num-ports = <3>; @@ -270,6 +282,11 @@ pinmux = <PIN_PA31__GPIO>; bias-disable; }; + + pinctrl_onewire_tm_default: onewire_tm_default { + pinmux = <PIN_PB0__GPIO>; + bias-pull-up; + }; }; }; }; diff --git a/arch/arm/dts/at91-sama5d3_xplained.dts b/arch/arm/dts/at91-sama5d3_xplained.dts index 69597102fb..20fba5f067 100644 --- a/arch/arm/dts/at91-sama5d3_xplained.dts +++ b/arch/arm/dts/at91-sama5d3_xplained.dts @@ -36,6 +36,18 @@ }; }; + onewire_tm: onewire { + gpios = <&pioE 23 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_onewire_tm_default>; + status = "okay"; + + w1_eeprom: w1_eeprom@0 { + compatible = "maxim,ds24b33"; + status = "okay"; + }; + }; + ahb { apb { mmc0: mmc@f0000000 { @@ -243,6 +255,11 @@ atmel,pins = <AT91_PIOE 9 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; /* PE9, conflicts with A9 */ }; + + pinctrl_onewire_tm_default: onewire_tm_default { + atmel,pins = + <AT91_PIOE 23 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; + }; }; }; }; diff --git a/arch/arm/dts/at91-sama5d4_xplained.dts b/arch/arm/dts/at91-sama5d4_xplained.dts index ea35dc21b6..58a0e60d18 100644 --- a/arch/arm/dts/at91-sama5d4_xplained.dts +++ b/arch/arm/dts/at91-sama5d4_xplained.dts @@ -58,6 +58,18 @@ stdout-path = &usart3; }; + onewire_tm: onewire { + gpios = <&pioE 15 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_onewire_tm_default>; + status = "okay"; + + w1_eeprom: w1_eeprom@0 { + compatible = "maxim,ds24b33"; + status = "okay"; + }; + }; + memory { reg = <0x20000000 0x20000000>; }; @@ -199,6 +211,10 @@ atmel,pins = <AT91_PIOE 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; }; + pinctrl_onewire_tm_default: onewire_tm_default { + atmel,pins = + <AT91_PIOE 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; + }; }; }; }; diff --git a/arch/arm/dts/axp209.dtsi b/arch/arm/dts/axp209.dtsi index 675bb0f308..0d9ff12bdf 100644 --- a/arch/arm/dts/axp209.dtsi +++ b/arch/arm/dts/axp209.dtsi @@ -53,12 +53,27 @@ interrupt-controller; #interrupt-cells = <1>; + ac_power_supply: ac-power-supply { + compatible = "x-powers,axp202-ac-power-supply"; + status = "disabled"; + }; + + axp_adc: adc { + compatible = "x-powers,axp209-adc"; + #io-channel-cells = <1>; + }; + axp_gpio: gpio { compatible = "x-powers,axp209-gpio"; gpio-controller; #gpio-cells = <2>; }; + battery_power_supply: battery-power-supply { + compatible = "x-powers,axp209-battery-power-supply"; + status = "disabled"; + }; + regulators { /* Default work frequency for buck regulators */ x-powers,dcdc-freq = <1500>; @@ -97,7 +112,7 @@ }; }; - usb_power_supply: usb_power_supply { + usb_power_supply: usb-power-supply { compatible = "x-powers,axp202-usb-power-supply"; status = "disabled"; }; diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts index f4f7c350ec..fa348bc621 100644 --- a/arch/arm/dts/dragonboard410c.dts +++ b/arch/arm/dts/dragonboard410c.dts @@ -18,6 +18,10 @@ #address-cells = <0x2>; #size-cells = <0x2>; + aliases { + usb0 = "/soc/ehci@78d9000"; + }; + memory { device_type = "memory"; reg = <0 0x80000000 0 0x3da00000>; @@ -93,6 +97,13 @@ ehci@78d9000 { compatible = "qcom,ehci-host"; reg = <0x78d9000 0x400>; + phys = <&ehci_phy>; + }; + + ehci_phy: ehci_phy@78d9000 { + compatible = "qcom,apq8016-usbphy"; + reg = <0x78d9000 0x400>; + #phy-cells = <0>; }; sdhci@07824000 { diff --git a/arch/arm/dts/fsl-ls1043a-qds.dtsi b/arch/arm/dts/fsl-ls1043a-qds.dtsi index addb9abfb9..3841aee11e 100644 --- a/arch/arm/dts/fsl-ls1043a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1043a-qds.dtsi @@ -174,3 +174,7 @@ &lpuart0 { status = "okay"; }; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi index ff401222ff..bb70992f9e 100644 --- a/arch/arm/dts/fsl-ls1043a.dtsi +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -70,6 +70,14 @@ status = "disabled"; }; + esdhc: esdhc@1560000 { + compatible = "fsl,esdhc"; + reg = <0x0 0x1560000 0x0 0x10000>; + interrupts = <0 62 0x4>; + big-endian; + bus-width = <4>; + }; + ifc: ifc@1530000 { compatible = "fsl,ifc", "simple-bus"; reg = <0x0 0x1530000 0x0 0x10000>; @@ -279,5 +287,13 @@ ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; + + sata: sata@3200000 { + compatible = "fsl,ls1043a-ahci"; + reg = <0x0 0x3200000 0x0 0x10000>; + interrupts = <0 69 4>; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index 4acbaf78e8..7687d12091 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -70,6 +70,14 @@ status = "disabled"; }; + esdhc: esdhc@1560000 { + compatible = "fsl,esdhc"; + reg = <0x0 0x1560000 0x0 0x10000>; + interrupts = <0 62 0x4>; + big-endian; + bus-width = <4>; + }; + ifc: ifc@1530000 { compatible = "fsl,ifc", "simple-bus"; reg = <0x0 0x1530000 0x0 0x10000>; diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 077caf3cc2..72d755a18c 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -74,6 +74,15 @@ reg-names = "QuadSPI", "QuadSPI-memory"; num-cs = <4>; }; + + esdhc: esdhc@2140000 { + compatible = "fsl,esdhc"; + reg = <0x0 0x2140000 0x0 0x10000>; + interrupts = <0 28 0x4>; /* Level high type */ + little-endian; + bus-width = <4>; + }; + ifc: ifc@1530000 { compatible = "fsl,ifc", "simple-bus"; reg = <0x0 0x2240000 0x0 0x20000>; diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi index b0f85170b0..2d537ae606 100644 --- a/arch/arm/dts/fsl-ls2080a.dtsi +++ b/arch/arm/dts/fsl-ls2080a.dtsi @@ -75,6 +75,14 @@ num-cs = <4>; }; + esdhc: esdhc@0 { + compatible = "fsl,esdhc"; + reg = <0x0 0x2140000 0x0 0x10000>; + interrupts = <0 28 0x4>; /* Level high type */ + little-endian; + bus-width = <4>; + }; + usb0: usb3@3100000 { compatible = "fsl,layerscape-dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; diff --git a/arch/arm/dts/ls1021a-qds.dtsi b/arch/arm/dts/ls1021a-qds.dtsi index fb1af1568b..47c128f16f 100644 --- a/arch/arm/dts/ls1021a-qds.dtsi +++ b/arch/arm/dts/ls1021a-qds.dtsi @@ -212,3 +212,7 @@ &uart1 { status = "okay"; }; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/ls1021a-twr.dtsi b/arch/arm/dts/ls1021a-twr.dtsi index 63f2079ed3..14e0ceafe7 100644 --- a/arch/arm/dts/ls1021a-twr.dtsi +++ b/arch/arm/dts/ls1021a-twr.dtsi @@ -103,3 +103,7 @@ &uart1 { status = "okay"; }; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi index 5b3fc6ad44..7670a39617 100644 --- a/arch/arm/dts/ls1021a.dtsi +++ b/arch/arm/dts/ls1021a.dtsi @@ -96,7 +96,6 @@ sdhci,auto-cmd12; big-endian; bus-width = <4>; - status = "disabled"; }; scfg: scfg@1570000 { @@ -404,5 +403,12 @@ ranges = <0x81000000 0x0 0x00000000 0x34020000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x38000000 0x38000000 0x0 0x08000000>; /* non-prefetchable memory */ }; + + sata: sata@3200000 { + compatible = "fsl,ls1021a-ahci"; + reg = <0x3200000 0x10000>; + interrupts = <0 101 4>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/dts/omap3-beagle-u-boot.dtsi b/arch/arm/dts/omap3-beagle-u-boot.dtsi index 094f9557b7..41beaf0900 100644 --- a/arch/arm/dts/omap3-beagle-u-boot.dtsi +++ b/arch/arm/dts/omap3-beagle-u-boot.dtsi @@ -11,10 +11,6 @@ }; }; -&mmc1 { - cd-inverted; -}; - &uart1 { reg-shift = <2>; }; diff --git a/arch/arm/dts/omap3-beagle-xm-ab-u-boot.dtsi b/arch/arm/dts/omap3-beagle-xm-ab-u-boot.dtsi index 094f9557b7..41beaf0900 100644 --- a/arch/arm/dts/omap3-beagle-xm-ab-u-boot.dtsi +++ b/arch/arm/dts/omap3-beagle-xm-ab-u-boot.dtsi @@ -11,10 +11,6 @@ }; }; -&mmc1 { - cd-inverted; -}; - &uart1 { reg-shift = <2>; }; diff --git a/arch/arm/dts/omap3-beagle-xm-u-boot.dtsi b/arch/arm/dts/omap3-beagle-xm-u-boot.dtsi index 094f9557b7..41beaf0900 100644 --- a/arch/arm/dts/omap3-beagle-xm-u-boot.dtsi +++ b/arch/arm/dts/omap3-beagle-xm-u-boot.dtsi @@ -11,10 +11,6 @@ }; }; -&mmc1 { - cd-inverted; -}; - &uart1 { reg-shift = <2>; }; diff --git a/arch/arm/dts/omap3-evm-37xx-u-boot.dtsi b/arch/arm/dts/omap3-evm-37xx-u-boot.dtsi index b09ce0efb5..de411316d8 100644 --- a/arch/arm/dts/omap3-evm-37xx-u-boot.dtsi +++ b/arch/arm/dts/omap3-evm-37xx-u-boot.dtsi @@ -11,10 +11,6 @@ }; }; -&mmc1 { - cd-inverted; -}; - &uart1 { reg-shift = <2>; }; diff --git a/arch/arm/dts/omap3-evm-u-boot.dtsi b/arch/arm/dts/omap3-evm-u-boot.dtsi index b09ce0efb5..de411316d8 100644 --- a/arch/arm/dts/omap3-evm-u-boot.dtsi +++ b/arch/arm/dts/omap3-evm-u-boot.dtsi @@ -11,10 +11,6 @@ }; }; -&mmc1 { - cd-inverted; -}; - &uart1 { reg-shift = <2>; }; diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi index 6645a55364..830251a539 100644 --- a/arch/arm/dts/sama5d2.dtsi +++ b/arch/arm/dts/sama5d2.dtsi @@ -769,4 +769,9 @@ }; }; }; + + onewire_tm: onewire { + compatible = "w1-gpio"; + status = "disabled"; + }; }; diff --git a/arch/arm/dts/sama5d3.dtsi b/arch/arm/dts/sama5d3.dtsi index ba707b0ddf..7db66c5d50 100644 --- a/arch/arm/dts/sama5d3.dtsi +++ b/arch/arm/dts/sama5d3.dtsi @@ -1534,4 +1534,9 @@ }; }; }; + + onewire_tm: onewire { + compatible = "w1-gpio"; + status = "disabled"; + }; }; diff --git a/arch/arm/dts/sama5d4.dtsi b/arch/arm/dts/sama5d4.dtsi index 8072b8a4f2..8875d7ba76 100644 --- a/arch/arm/dts/sama5d4.dtsi +++ b/arch/arm/dts/sama5d4.dtsi @@ -1913,4 +1913,9 @@ }; }; }; + + onewire_tm: onewire { + compatible = "w1-gpio"; + status = "disabled"; + }; }; diff --git a/arch/arm/dts/sun4i-a10-a1000.dts b/arch/arm/dts/sun4i-a10-a1000.dts index 39e368ec34..6c254ec4c8 100644 --- a/arch/arm/dts/sun4i-a10-a1000.dts +++ b/arch/arm/dts/sun4i-a10-a1000.dts @@ -47,7 +47,6 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Mele A1000"; @@ -63,8 +62,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_a1000>; red { label = "a1000:red:usr"; @@ -80,8 +77,6 @@ reg_emac_3v3: emac-3v3 { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&emac_power_pin_a1000>; regulator-name = "emac-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -117,6 +112,10 @@ status = "okay"; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + &ehci0 { status = "okay"; }; @@ -126,8 +125,6 @@ }; &emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; phy = <&phy1>; status = "okay"; }; @@ -137,8 +134,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -153,7 +148,7 @@ &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pins>; status = "okay"; }; @@ -167,12 +162,9 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; @@ -184,20 +176,31 @@ status = "okay"; }; -&pio { - emac_power_pin_a1000: emac_power_pin@0 { - allwinner,pins = "PH15"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; +#include "axp209.dtsi" - led_pins_a1000: led_pins@0 { - allwinner,pins = "PH10", "PH20"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; }; ®_usb1_vbus { @@ -210,13 +213,13 @@ &spdif { pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pins_a>; + pinctrl-0 = <&spdif_tx_pin>; status = "okay"; }; &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/dts/sun4i-a10-ba10-tvbox.dts b/arch/arm/dts/sun4i-a10-ba10-tvbox.dts index f3cb297fd1..38a2c41349 100644 --- a/arch/arm/dts/sun4i-a10-ba10-tvbox.dts +++ b/arch/arm/dts/sun4i-a10-ba10-tvbox.dts @@ -68,8 +68,6 @@ }; &emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; phy = <&phy1>; status = "okay"; }; @@ -79,8 +77,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -95,7 +91,7 @@ &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pins>; status = "okay"; }; @@ -108,12 +104,9 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; @@ -121,20 +114,10 @@ status = "okay"; }; -&ohci1 { - status = "okay"; -}; - &otg_sram { status = "okay"; }; -&pio { - usb2_vbus_pin_a: usb2_vbus_pin@0 { - allwinner,pins = "PH12"; - }; -}; - ®_usb0_vbus { regulator-boot-on; status = "okay"; @@ -151,7 +134,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts b/arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts index 023b03efa5..cf7b392dff 100644 --- a/arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts +++ b/arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts @@ -65,8 +65,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -80,14 +78,10 @@ }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; status = "okay"; }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; status = "okay"; ft5306de4: touchscreen@38 { @@ -104,21 +98,21 @@ vref-supply = <®_vcc3v0>; status = "okay"; - button@800 { + button-800 { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; channel = <0>; voltage = <800000>; }; - button@1000 { + button-1000 { label = "Volume Down"; linux,code = <KEY_VOLUMEDOWN>; channel = <0>; voltage = <1000000>; }; - button@1200 { + button-1200 { label = "Back"; linux,code = <KEY_BACK>; channel = <0>; @@ -127,12 +121,9 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; @@ -141,18 +132,16 @@ }; &pio { - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + usb0_id_detect_pin: usb0-id-detect-pin { + pins = "PH4"; + function = "gpio_in"; + bias-pull-up; }; - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PH5"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; + usb0_vbus_detect_pin: usb0-vbus-detect-pin { + pins = "PH5"; + function = "gpio_in"; + bias-pull-down; }; }; @@ -166,7 +155,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/dts/sun4i-a10-cubieboard.dts b/arch/arm/dts/sun4i-a10-cubieboard.dts index 710e2ef516..197a1f2b75 100644 --- a/arch/arm/dts/sun4i-a10-cubieboard.dts +++ b/arch/arm/dts/sun4i-a10-cubieboard.dts @@ -46,7 +46,6 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Cubietech Cubieboard"; @@ -60,6 +59,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -91,6 +101,10 @@ cpu-supply = <®_dcdc2>; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -100,8 +114,6 @@ }; &emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; phy = <&phy1>; status = "okay"; }; @@ -110,9 +122,17 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -122,14 +142,12 @@ }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; status = "okay"; }; &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pins>; status = "okay"; }; @@ -142,12 +160,9 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; @@ -164,18 +179,16 @@ }; &pio { - led_pins_cubieboard: led_pins@0 { - allwinner,pins = "PH20", "PH21"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_20_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + led_pins_cubieboard: led-pins { + pins = "PH20", "PH21"; + function = "gpio_out"; + drive-strength = <20>; }; - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + usb0_id_detect_pin: usb0-id-detect-pin { + pins = "PH4"; + function = "gpio_in"; + bias-pull-up; }; }; @@ -185,6 +198,10 @@ #include "axp209.dtsi" +&ac_power_supply { + status = "okay"; +}; + ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; @@ -220,14 +237,14 @@ &spi0 { pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>, - <&spi0_cs0_pins_a>; + pinctrl-0 = <&spi0_pi_pins>, + <&spi0_cs0_pi_pin>; status = "okay"; }; &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts b/arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts index 893497e397..896e27a087 100644 --- a/arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts +++ b/arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts @@ -46,7 +46,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> #include <dt-bindings/pwm/pwm.h> / { @@ -59,8 +58,6 @@ backlight: backlight { compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&bl_en_pin_dsrv9703c>; pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; default-brightness-level = <8>; @@ -78,10 +75,8 @@ max-microvolt = <3000000>; }; - reg_motor: reg_motor { + reg_motor: reg-motor { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&motor_pins>; regulator-name = "vcc-motor"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; @@ -91,8 +86,6 @@ }; &codec { - pinctrl-names = "default"; - pinctrl-0 = <&codec_pa_pin>; allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */ status = "okay"; }; @@ -106,8 +99,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -119,15 +110,11 @@ #include "axp209.dtsi" &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; /* pull-ups and devices require AXP209 LDO3 */ status = "failed"; }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; status = "okay"; ft5406ee8: touchscreen@38 { @@ -135,8 +122,6 @@ reg = <0x38>; interrupt-parent = <&pio>; interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&touchscreen_pins>; reset-gpios = <&pio 1 13 GPIO_ACTIVE_LOW>; touchscreen-size-x = <1024>; touchscreen-size-y = <768>; @@ -147,14 +132,14 @@ vref-supply = <®_ldo2>; status = "okay"; - button@400 { + button-400 { label = "Volume Down"; linux,code = <KEY_VOLUMEDOWN>; channel = <0>; voltage = <400000>; }; - button@800 { + button-800 { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; channel = <0>; @@ -163,12 +148,9 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; @@ -177,52 +159,22 @@ }; &pio { - bl_en_pin_dsrv9703c: bl_en_pin@0 { - allwinner,pins = "PH7"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - codec_pa_pin: codec_pa_pin@0 { - allwinner,pins = "PH15"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - motor_pins: motor_pins@0 { - allwinner,pins = "PB3"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - touchscreen_pins: touchscreen_pins@0 { - allwinner,pins = "PB13"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + usb0_id_detect_pin: usb0-id-detect-pin { + pins = "PH4"; + function = "gpio_in"; + bias-pull-up; }; - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PH5"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; + usb0_vbus_detect_pin: usb0-vbus-detect-pin { + pins = "PH5"; + function = "gpio_in"; + bias-pull-down; }; }; &pwm { pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins_a>; + pinctrl-0 = <&pwm0_pin>; status = "okay"; }; @@ -261,7 +213,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/dts/sun4i-a10-gemei-g9.dts b/arch/arm/dts/sun4i-a10-gemei-g9.dts index ac64781a0a..ea7a59dcf8 100644 --- a/arch/arm/dts/sun4i-a10-gemei-g9.dts +++ b/arch/arm/dts/sun4i-a10-gemei-g9.dts @@ -72,8 +72,6 @@ */ &codec { /* PH15 controls power to external amplifier (ft2012q) */ - pinctrl-names = "default"; - pinctrl-0 = <&codec_pa_pin>; allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -91,8 +89,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -104,8 +100,6 @@ #include "axp209.dtsi" &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; status = "okay"; /* Accelerometer */ @@ -122,21 +116,21 @@ status = "okay"; - button@158 { + button-158 { label = "Volume Down"; linux,code = <KEY_VOLUMEDOWN>; channel = <0>; voltage = <158730>; }; - button@349 { + button-349 { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; channel = <0>; voltage = <349206>; }; - button@1142 { + button-1142 { label = "Esc"; linux,code = <KEY_ESC>; channel = <0>; @@ -145,24 +139,12 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH01 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH01 */ status = "okay"; }; -&pio { - codec_pa_pin: codec_pa_pin@0 { - allwinner,pins = "PH15"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; -}; - ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; @@ -199,7 +181,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/dts/sun4i-a10-hackberry.dts b/arch/arm/dts/sun4i-a10-hackberry.dts index 6de83a6187..cc988ccd5c 100644 --- a/arch/arm/dts/sun4i-a10-hackberry.dts +++ b/arch/arm/dts/sun4i-a10-hackberry.dts @@ -47,7 +47,6 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Miniand Hackberry"; @@ -81,8 +80,6 @@ }; &emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; phy = <&phy0>; status = "okay"; }; @@ -93,7 +90,7 @@ &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pins>; status = "okay"; }; @@ -107,12 +104,9 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; @@ -124,31 +118,11 @@ status = "okay"; }; -&pio { - pinctrl-names = "default"; - pinctrl-0 = <&hackberry_hogs>; - - hackberry_hogs: hogs@0 { - allwinner,pins = "PH19"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - usb2_vbus_pin_hackberry: usb2_vbus_pin@0 { - allwinner,pins = "PH12"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; -}; - ®_usb1_vbus { status = "okay"; }; ®_usb2_vbus { - pinctrl-0 = <&usb2_vbus_pin_hackberry>; gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -161,6 +135,6 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/dts/sun4i-a10-hyundai-a7hd.dts b/arch/arm/dts/sun4i-a10-hyundai-a7hd.dts index 9103864fef..f63767cddd 100644 --- a/arch/arm/dts/sun4i-a10-hyundai-a7hd.dts +++ b/arch/arm/dts/sun4i-a10-hyundai-a7hd.dts @@ -63,8 +63,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -78,12 +76,9 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; @@ -92,18 +87,16 @@ }; &pio { - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + usb0_id_detect_pin: usb0-id-detect-pin { + pins = "PH4"; + function = "gpio_in"; + bias-pull-up; }; - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PH5"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; + usb0_vbus_detect_pin: usb0-vbus-detect-pin { + pins = "PH5"; + function = "gpio_in"; + bias-pull-down; }; }; @@ -118,14 +111,10 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; -&usb2_vbus_pin_a { - allwinner,pins = "PH6"; -}; - &usb_otg { dr_mode = "otg"; status = "okay"; diff --git a/arch/arm/dts/sun4i-a10-inet-3f.dts b/arch/arm/dts/sun4i-a10-inet-3f.dts index f815b83157..9aa8469a0c 100644 --- a/arch/arm/dts/sun4i-a10-inet-3f.dts +++ b/arch/arm/dts/sun4i-a10-inet-3f.dts @@ -23,6 +23,6 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/dts/sun4i-a10-inet-3w.dts b/arch/arm/dts/sun4i-a10-inet-3w.dts index d0267ceee9..33232e94ed 100644 --- a/arch/arm/dts/sun4i-a10-inet-3w.dts +++ b/arch/arm/dts/sun4i-a10-inet-3w.dts @@ -23,6 +23,6 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/dts/sun4i-a10-inet1.dts b/arch/arm/dts/sun4i-a10-inet1.dts index e09053bf5e..26d0c1d6a0 100644 --- a/arch/arm/dts/sun4i-a10-inet1.dts +++ b/arch/arm/dts/sun4i-a10-inet1.dts @@ -46,7 +46,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> #include <dt-bindings/pwm/pwm.h> / { @@ -59,8 +58,6 @@ backlight: backlight { compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&bl_en_pin_inet>; pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; default-brightness-level = <8>; @@ -89,8 +86,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -102,8 +97,6 @@ #include "axp209.dtsi" &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; status = "okay"; /* Accelerometer */ @@ -116,8 +109,6 @@ }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; status = "okay"; ft5x: touchscreen@38 { @@ -125,8 +116,6 @@ reg = <0x38>; interrupt-parent = <&pio>; interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&touchscreen_wake_pin>; wake-gpios = <&pio 1 13 GPIO_ACTIVE_HIGH>; /* PB13 */ touchscreen-size-x = <600>; touchscreen-size-y = <1024>; @@ -138,21 +127,21 @@ vref-supply = <®_ldo2>; status = "okay"; - button@200 { + button-200 { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; channel = <0>; voltage = <200000>; }; - button@1000 { + button-1000 { label = "Volume Down"; linux,code = <KEY_VOLUMEDOWN>; channel = <0>; voltage = <1000000>; }; - button@1200 { + button-1200 { label = "Home"; linux,code = <KEY_HOMEPAGE>; channel = <0>; @@ -161,12 +150,9 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; @@ -179,38 +165,22 @@ }; &pio { - bl_en_pin_inet: bl_en_pin@0 { - allwinner,pins = "PH7"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - touchscreen_wake_pin: touchscreen_wake_pin@0 { - allwinner,pins = "PB13"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + usb0_id_detect_pin: usb0-id-detect-pin { + pins = "PH4"; + function = "gpio_in"; + bias-pull-up; }; - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PH5"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; + usb0_vbus_detect_pin: usb0-vbus-detect-pin { + pins = "PH5"; + function = "gpio_in"; + bias-pull-down; }; }; &pwm { pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins_a>; + pinctrl-0 = <&pwm0_pin>; status = "okay"; }; @@ -253,7 +223,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/dts/sun4i-a10-inet97fv2.dts b/arch/arm/dts/sun4i-a10-inet97fv2.dts index 04b0d2d1ae..5d096528e7 100644 --- a/arch/arm/dts/sun4i-a10-inet97fv2.dts +++ b/arch/arm/dts/sun4i-a10-inet97fv2.dts @@ -72,8 +72,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -85,14 +83,10 @@ #include "axp209.dtsi" &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; status = "okay"; }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; status = "okay"; ft5406ee8: touchscreen@38 { @@ -109,35 +103,35 @@ vref-supply = <®_ldo2>; status = "okay"; - button@200 { + button-200 { label = "Menu"; linux,code = <KEY_MENU>; channel = <0>; voltage = <200000>; }; - button@600 { + button-600 { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; channel = <0>; voltage = <600000>; }; - button@800 { + button-800 { label = "Volume Down"; linux,code = <KEY_VOLUMEDOWN>; channel = <0>; voltage = <800000>; }; - button@1000 { + button-1000 { label = "Home"; linux,code = <KEY_HOMEPAGE>; channel = <0>; voltage = <1000000>; }; - button@1200 { + button-1200 { label = "Esc"; linux,code = <KEY_ESC>; channel = <0>; @@ -146,12 +140,9 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; @@ -160,18 +151,16 @@ }; &pio { - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + usb0_id_detect_pin: usb0-id-detect-pin { + pins = "PH4"; + function = "gpio_in"; + bias-pull-up; }; - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PH5"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; + usb0_vbus_detect_pin: usb0-vbus-detect-pin { + pins = "PH5"; + function = "gpio_in"; + bias-pull-down; }; }; @@ -210,7 +199,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/dts/sun4i-a10-inet9f-rev03.dts b/arch/arm/dts/sun4i-a10-inet9f-rev03.dts index bba4f9cf9b..221acd10f6 100644 --- a/arch/arm/dts/sun4i-a10-inet9f-rev03.dts +++ b/arch/arm/dts/sun4i-a10-inet9f-rev03.dts @@ -46,7 +46,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "iNet-9F Rev 03"; @@ -60,7 +59,7 @@ stdout-path = "serial0:115200n8"; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys-polled"; pinctrl-names = "default"; pinctrl-0 = <&key_pins_inet9f>; @@ -68,7 +67,7 @@ #size-cells = <0>; poll-interval = <20>; - button@0 { + left-joystick-left { label = "Left Joystick Left"; linux,code = <ABS_X>; linux,input-type = <EV_ABS>; @@ -76,7 +75,7 @@ gpios = <&pio 0 6 GPIO_ACTIVE_LOW>; /* PA6 */ }; - button@1 { + left-joystick-right { label = "Left Joystick Right"; linux,code = <ABS_X>; linux,input-type = <EV_ABS>; @@ -84,7 +83,7 @@ gpios = <&pio 0 5 GPIO_ACTIVE_LOW>; /* PA5 */ }; - button@2 { + left-joystick-up { label = "Left Joystick Up"; linux,code = <ABS_Y>; linux,input-type = <EV_ABS>; @@ -92,7 +91,7 @@ gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ }; - button@3 { + left-joystick-down { label = "Left Joystick Down"; linux,code = <ABS_Y>; linux,input-type = <EV_ABS>; @@ -100,7 +99,7 @@ gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */ }; - button@4 { + right-joystick-left { label = "Right Joystick Left"; linux,code = <ABS_Z>; linux,input-type = <EV_ABS>; @@ -108,7 +107,7 @@ gpios = <&pio 0 1 GPIO_ACTIVE_LOW>; /* PA1 */ }; - button@5 { + right-joystick-right { label = "Right Joystick Right"; linux,code = <ABS_Z>; linux,input-type = <EV_ABS>; @@ -116,7 +115,7 @@ gpios = <&pio 0 0 GPIO_ACTIVE_LOW>; /* PA0 */ }; - button@6 { + right-joystick-up { label = "Right Joystick Up"; linux,code = <ABS_RZ>; linux,input-type = <EV_ABS>; @@ -124,7 +123,7 @@ gpios = <&pio 0 3 GPIO_ACTIVE_LOW>; /* PA3 */ }; - button@7 { + right-joystick-down { label = "Right Joystick Down"; linux,code = <ABS_RZ>; linux,input-type = <EV_ABS>; @@ -132,7 +131,7 @@ gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */ }; - button@8 { + dpad-left { label = "DPad Left"; linux,code = <ABS_HAT0X>; linux,input-type = <EV_ABS>; @@ -140,7 +139,7 @@ gpios = <&pio 7 23 GPIO_ACTIVE_LOW>; /* PH23 */ }; - button@9 { + dpad-right { label = "DPad Right"; linux,code = <ABS_HAT0X>; linux,input-type = <EV_ABS>; @@ -148,7 +147,7 @@ gpios = <&pio 7 24 GPIO_ACTIVE_LOW>; /* PH24 */ }; - button@10 { + dpad-up { label = "DPad Up"; linux,code = <ABS_HAT0Y>; linux,input-type = <EV_ABS>; @@ -156,7 +155,7 @@ gpios = <&pio 7 25 GPIO_ACTIVE_LOW>; /* PH25 */ }; - button@11 { + dpad-down { label = "DPad Down"; linux,code = <ABS_HAT0Y>; linux,input-type = <EV_ABS>; @@ -164,49 +163,49 @@ gpios = <&pio 7 26 GPIO_ACTIVE_LOW>; /* PH26 */ }; - button@12 { + x { label = "Button X"; linux,code = <BTN_X>; gpios = <&pio 0 16 GPIO_ACTIVE_LOW>; /* PA16 */ }; - button@13 { + y { label = "Button Y"; linux,code = <BTN_Y>; gpios = <&pio 0 14 GPIO_ACTIVE_LOW>; /* PA14 */ }; - button@14 { + a { label = "Button A"; linux,code = <BTN_A>; gpios = <&pio 0 17 GPIO_ACTIVE_LOW>; /* PA17 */ }; - button@15 { + b { label = "Button B"; linux,code = <BTN_B>; gpios = <&pio 0 15 GPIO_ACTIVE_LOW>; /* PA15 */ }; - button@16 { + select { label = "Select Button"; linux,code = <BTN_SELECT>; gpios = <&pio 0 11 GPIO_ACTIVE_LOW>; /* PA11 */ }; - button@17 { + start { label = "Start Button"; linux,code = <BTN_START>; gpios = <&pio 0 12 GPIO_ACTIVE_LOW>; /* PA12 */ }; - button@18 { + top-left { label = "Top Left Button"; linux,code = <BTN_TL>; gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */ }; - button@19 { + top-right { label = "Top Right Button"; linux,code = <BTN_TR>; gpios = <&pio 0 13 GPIO_ACTIVE_LOW>; /* PA13 */ @@ -223,8 +222,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -236,8 +233,6 @@ #include "axp209.dtsi" &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; status = "okay"; /* Accelerometer */ @@ -250,8 +245,6 @@ }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; status = "okay"; ft5406ee8: touchscreen@38 { @@ -268,35 +261,35 @@ vref-supply = <®_ldo2>; status = "okay"; - button@200 { + button-200 { label = "Menu"; linux,code = <KEY_MENU>; channel = <0>; voltage = <200000>; }; - button@600 { + button-600 { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; channel = <0>; voltage = <600000>; }; - button@800 { + button-800 { label = "Volume Down"; linux,code = <KEY_VOLUMEDOWN>; channel = <0>; voltage = <800000>; }; - button@1000 { + button-1000 { label = "Home"; linux,code = <KEY_HOMEPAGE>; channel = <0>; voltage = <1000000>; }; - button@1200 { + button-1200 { label = "Esc"; linux,code = <KEY_ESC>; channel = <0>; @@ -305,12 +298,9 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; @@ -319,29 +309,26 @@ }; &pio { - key_pins_inet9f: key_pins@0 { - allwinner,pins = "PA0", "PA1", "PA3", "PA4", - "PA5", "PA6", "PA8", "PA9", - "PA11", "PA12", "PA13", - "PA14", "PA15", "PA16", "PA17", - "PH22", "PH23", "PH24", "PH25", "PH26"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + key_pins_inet9f: key-pins { + pins = "PA0", "PA1", "PA3", "PA4", + "PA5", "PA6", "PA8", "PA9", + "PA11", "PA12", "PA13", + "PA14", "PA15", "PA16", "PA17", + "PH22", "PH23", "PH24", "PH25", "PH26"; + function = "gpio_in"; + bias-pull-up; }; - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + usb0_id_detect_pin: usb0-id-detect-pin { + pins = "PH4"; + function = "gpio_in"; + bias-pull-up; }; - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PH5"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; + usb0_vbus_detect_pin: usb0-vbus-detect-pin { + pins = "PH5"; + function = "gpio_in"; + bias-pull-down; }; }; @@ -380,7 +367,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/dts/sun4i-a10-itead-iteaduino-plus.dts b/arch/arm/dts/sun4i-a10-itead-iteaduino-plus.dts index 4e798f014c..80ecd78247 100644 --- a/arch/arm/dts/sun4i-a10-itead-iteaduino-plus.dts +++ b/arch/arm/dts/sun4i-a10-itead-iteaduino-plus.dts @@ -57,7 +57,7 @@ &emac { pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; + pinctrl-0 = <&emac_pins>; phy = <&phy1>; status = "okay"; }; @@ -67,6 +67,9 @@ }; &i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + axp209: pmic@34 { interrupts = <0>; }; @@ -74,19 +77,19 @@ &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; + pinctrl-0 = <&i2c1_pins>; status = "okay"; }; &i2c2 { pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; + pinctrl-0 = <&i2c2_pins>; status = "okay"; }; &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pins>; status = "okay"; }; @@ -100,11 +103,10 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; @@ -114,7 +116,11 @@ &spi0 { pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>, - <&spi0_cs0_pins_a>; + pinctrl-0 = <&spi0_pi_pins>, + <&spi0_cs0_pi_pin>; status = "okay"; }; + +&uart0 { + pinctrl-0 = <&uart0_pb_pins>; +}; diff --git a/arch/arm/dts/sun4i-a10-jesurun-q5.dts b/arch/arm/dts/sun4i-a10-jesurun-q5.dts index e28f080b1f..247fa27ef7 100644 --- a/arch/arm/dts/sun4i-a10-jesurun-q5.dts +++ b/arch/arm/dts/sun4i-a10-jesurun-q5.dts @@ -47,7 +47,6 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Jesurun Q5"; @@ -63,8 +62,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_q5>; green { label = "q5:green:usr"; @@ -75,8 +72,6 @@ reg_emac_3v3: emac-3v3 { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&emac_power_pin_q5>; regulator-name = "emac-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -99,8 +94,6 @@ }; &emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; phy = <&phy1>; status = "okay"; }; @@ -110,8 +103,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -126,7 +117,7 @@ &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pins>; status = "okay"; }; @@ -140,12 +131,9 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; @@ -161,22 +149,6 @@ status = "okay"; }; -&pio { - emac_power_pin_q5: emac_power_pin@0 { - allwinner,pins = "PH19"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - led_pins_q5: led_pins@0 { - allwinner,pins = "PH20"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; -}; - ®_usb0_vbus { regulator-boot-on; status = "okay"; @@ -192,7 +164,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/dts/sun4i-a10-marsboard.dts b/arch/arm/dts/sun4i-a10-marsboard.dts index 8e50723dbe..0dbf695765 100644 --- a/arch/arm/dts/sun4i-a10-marsboard.dts +++ b/arch/arm/dts/sun4i-a10-marsboard.dts @@ -46,7 +46,6 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "HAOYU Electronics Marsboard A10"; @@ -62,8 +61,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_marsboard>; red1 { label = "marsboard:red1:usr"; @@ -108,27 +105,19 @@ }; &emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; phy = <&phy1>; status = "okay"; }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; status = "okay"; }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; status = "okay"; }; @@ -141,12 +130,9 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; @@ -163,18 +149,10 @@ }; &pio { - led_pins_marsboard: led_pins@0 { - allwinner,pins = "PB5", "PB6", "PB7", "PB8"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + usb0_id_detect_pin: usb0-id-detect-pin { + pins = "PH4"; + function = "gpio_in"; + bias-pull-up; }; }; @@ -188,14 +166,14 @@ &spi0 { pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>, - <&spi0_cs0_pins_a>; + pinctrl-0 = <&spi0_pi_pins>, + <&spi0_cs0_pi_pin>; status = "okay"; }; &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/dts/sun4i-a10-mini-xplus.dts b/arch/arm/dts/sun4i-a10-mini-xplus.dts index a7dd86d30f..f9d74e2103 100644 --- a/arch/arm/dts/sun4i-a10-mini-xplus.dts +++ b/arch/arm/dts/sun4i-a10-mini-xplus.dts @@ -47,7 +47,6 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "PineRiver Mini X-Plus"; @@ -71,8 +70,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -87,22 +84,19 @@ &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pins>; status = "okay"; }; -&ir0_rx_pins_a { +&ir0_rx_pins { /* The ir receiver is not always populated */ - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + bias-pull-up; }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; @@ -133,7 +127,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/dts/sun4i-a10-mk802.dts b/arch/arm/dts/sun4i-a10-mk802.dts index ee46ea8548..059fe9c5d0 100644 --- a/arch/arm/dts/sun4i-a10-mk802.dts +++ b/arch/arm/dts/sun4i-a10-mk802.dts @@ -44,7 +44,6 @@ #include "sun4i-a10.dtsi" #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "MK802"; @@ -57,12 +56,27 @@ chosen { stdout-path = "serial0:115200n8"; }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; }; &codec { status = "okay"; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -71,13 +85,20 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; @@ -89,29 +110,6 @@ status = "okay"; }; -&pio { - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PH5"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - usb2_vbus_pin_mk802: usb2_vbus_pin@0 { - allwinner,pins = "PH12"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; -}; - ®_usb0_vbus { status = "okay"; }; @@ -121,14 +119,13 @@ }; ®_usb2_vbus { - pinctrl-0 = <&usb2_vbus_pin_mk802>; gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */ status = "okay"; }; &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; @@ -138,8 +135,6 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; diff --git a/arch/arm/dts/sun4i-a10-mk802ii.dts b/arch/arm/dts/sun4i-a10-mk802ii.dts index c861fa7e35..17dcdf0311 100644 --- a/arch/arm/dts/sun4i-a10-mk802ii.dts +++ b/arch/arm/dts/sun4i-a10-mk802ii.dts @@ -67,8 +67,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -82,12 +80,9 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; @@ -105,7 +100,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/dts/sun4i-a10-olinuxino-lime.dts index b350448c72..b74a614965 100644 --- a/arch/arm/dts/sun4i-a10-olinuxino-lime.dts +++ b/arch/arm/dts/sun4i-a10-olinuxino-lime.dts @@ -45,7 +45,6 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Olimex A10-OLinuXino-LIME"; @@ -59,6 +58,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -87,7 +97,10 @@ 864000 1300000 624000 1250000 >; - cooling-max-level = <2>; +}; + +&de { + status = "okay"; }; &ehci0 { @@ -99,8 +112,6 @@ }; &emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; phy = <&phy1>; status = "okay"; }; @@ -109,9 +120,17 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -125,8 +144,6 @@ }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; status = "okay"; eeprom: eeprom@50 { @@ -145,12 +162,9 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; @@ -167,37 +181,26 @@ }; &pio { - ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 { - allwinner,pins = "PC3"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - led_pins_olinuxinolime: led_pins@0 { - allwinner,pins = "PH2"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_20_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + led_pins_olinuxinolime: led-pin { + pins = "PH2"; + function = "gpio_out"; + drive-strength = <20>; }; - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + usb0_id_detect_pin: usb0-id-detect-pin { + pins = "PH4"; + function = "gpio_in"; + bias-pull-up; }; - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PH5"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; + usb0_vbus_detect_pin: usb0-vbus-detect-pin { + pins = "PH5"; + function = "gpio_in"; + bias-pull-down; }; }; ®_ahci_5v { - pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>; gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -216,7 +219,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/dts/sun4i-a10-pcduino.dts b/arch/arm/dts/sun4i-a10-pcduino.dts index 39034aa8e1..b97a0f2f20 100644 --- a/arch/arm/dts/sun4i-a10-pcduino.dts +++ b/arch/arm/dts/sun4i-a10-pcduino.dts @@ -47,7 +47,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "LinkSprite pcDuino"; @@ -63,8 +62,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_pcduino>; tx { label = "pcduino:green:tx"; @@ -77,26 +74,24 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&key_pins_pcduino>; #address-cells = <1>; #size-cells = <0>; - button@0 { + back { label = "Key Back"; linux,code = <KEY_BACK>; gpios = <&pio 7 17 GPIO_ACTIVE_LOW>; }; - button@1 { + home { label = "Key Home"; linux,code = <KEY_HOME>; gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; }; - button@2 { + menu { label = "Key Menu"; linux,code = <KEY_MENU>; gpios = <&pio 7 19 GPIO_ACTIVE_LOW>; @@ -117,8 +112,6 @@ }; &emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; phy = <&phy1>; status = "okay"; }; @@ -128,8 +121,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -147,12 +138,9 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; @@ -169,25 +157,10 @@ }; &pio { - led_pins_pcduino: led_pins@0 { - allwinner,pins = "PH15", "PH16"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - key_pins_pcduino: key_pins@0 { - allwinner,pins = "PH17", "PH18", "PH19"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + usb0_id_detect_pin: usb0-id-detect-pin { + pins = "PH4"; + function = "gpio_in"; + bias-pull-up; }; }; @@ -220,7 +193,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/dts/sun4i-a10-pcduino2.dts b/arch/arm/dts/sun4i-a10-pcduino2.dts index de483a1bf3..bc4f128965 100644 --- a/arch/arm/dts/sun4i-a10-pcduino2.dts +++ b/arch/arm/dts/sun4i-a10-pcduino2.dts @@ -55,18 +55,7 @@ compatible = "linksprite,a10-pcduino2", "allwinner,sun4i-a10"; }; -&pio { - usb2_vbus_pin_pcduino2: usb2_vbus_pin@0 { - allwinner,pins = "PD2"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; -}; - ®_usb2_vbus { - pinctrl-names = "default"; - pinctrl-0 = <&usb2_vbus_pin_pcduino2>; gpio = <&pio 3 2 GPIO_ACTIVE_HIGH>; status = "okay"; }; diff --git a/arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts b/arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts index ea90634e48..84b25be1ac 100644 --- a/arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts +++ b/arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts @@ -46,7 +46,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> #include <dt-bindings/pwm/pwm.h> / { @@ -59,8 +58,6 @@ backlight: backlight { compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&bl_en_pin_protab>; pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; default-brightness-level = <8>; @@ -73,8 +70,6 @@ }; &codec { - pinctrl-names = "default"; - pinctrl-0 = <&codec_pa_pin>; allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */ status = "okay"; }; @@ -88,8 +83,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { @@ -101,27 +94,14 @@ #include "axp209.dtsi" &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - - /* Accelerometer */ - bma250@18 { - compatible = "bosch,bma250"; - reg = <0x18>; - interrupt-parent = <&pio>; - interrupts = <7 0 IRQ_TYPE_EDGE_RISING>; /* PH0 / EINT0 */ - }; + /* pull-ups and devices require AXP209 LDO3 */ + status = "failed"; }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; status = "okay"; - pixcir_ts@5c { - pinctrl-names = "default"; - pinctrl-0 = <&touchscreen_pins>; + touchscreen@5c { compatible = "pixcir,pixcir_tangoc"; reg = <0x5c>; interrupt-parent = <&pio>; @@ -140,14 +120,14 @@ vref-supply = <®_ldo2>; status = "okay"; - button@400 { + button-400 { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; channel = <0>; voltage = <400000>; }; - button@800 { + button-800 { label = "Volume Down"; linux,code = <KEY_VOLUMEDOWN>; channel = <0>; @@ -156,12 +136,9 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; @@ -170,45 +147,22 @@ }; &pio { - bl_en_pin_protab: bl_en_pin@0 { - allwinner,pins = "PH7"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + usb0_id_detect_pin: usb0-id-detect-pin { + pins = "PH4"; + function = "gpio_in"; + bias-pull-up; }; - codec_pa_pin: codec_pa_pin@0 { - allwinner,pins = "PH15"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - touchscreen_pins: touchscreen_pins@0 { - allwinner,pins = "PA5", "PB13"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PH5"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; + usb0_vbus_detect_pin: usb0-vbus-detect-pin { + pins = "PH5"; + function = "gpio_in"; + bias-pull-down; }; }; &pwm { pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins_a>; + pinctrl-0 = <&pwm0_pin>; status = "okay"; }; @@ -237,17 +191,6 @@ regulator-name = "avcc"; }; -®_ldo3 { - /* - * We need to always power the camera sensor, otherwhise all access - * to i2c1 is blocked. - */ - regulator-always-on; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "vdd-csi"; -}; - ®_usb0_vbus { status = "okay"; }; @@ -258,7 +201,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/dts/sun4i-a10.dtsi b/arch/arm/dts/sun4i-a10.dtsi index 7e7dfc2b43..3a1c6b45c9 100644 --- a/arch/arm/dts/sun4i-a10.dtsi +++ b/arch/arm/dts/sun4i-a10.dtsi @@ -41,15 +41,14 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton.dtsi" - #include <dt-bindings/thermal/thermal.h> - -#include <dt-bindings/clock/sun4i-a10-pll2.h> #include <dt-bindings/dma/sun4i-a10.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> +#include <dt-bindings/clock/sun4i-a10-ccu.h> +#include <dt-bindings/reset/sun4i-a10-ccu.h> / { + #address-cells = <1>; + #size-cells = <1>; interrupt-parent = <&intc>; aliases { @@ -61,46 +60,48 @@ #size-cells = <1>; ranges; - framebuffer@0 { + framebuffer-lcd0-hdmi { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&ahb_gates 36>, <&ahb_gates 43>, - <&ahb_gates 44>, <&de_be0_clk>, - <&tcon0_ch1_clk>, <&dram_gates 26>; + clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, + <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, + <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>; status = "disabled"; }; - framebuffer@1 { + framebuffer-fe0-lcd0-hdmi { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi"; - clocks = <&ahb_gates 36>, <&ahb_gates 43>, - <&ahb_gates 44>, <&ahb_gates 46>, - <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch1_clk>, - <&dram_gates 25>, <&dram_gates 26>; + clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, + <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>, + <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>, + <&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>, + <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; status = "disabled"; }; - framebuffer@2 { + framebuffer-fe0-lcd0 { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_fe0-de_be0-lcd0"; - clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&ahb_gates 46>, - <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>, - <&dram_gates 25>, <&dram_gates 26>; + clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>, + <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_BE0>, + <&ccu CLK_DE_FE0>, <&ccu CLK_TCON0_CH0>, + <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; status = "disabled"; }; - framebuffer@3 { + framebuffer-fe0-lcd0-tve0 { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0"; - clocks = <&ahb_gates 34>, <&ahb_gates 36>, - <&ahb_gates 44>, <&ahb_gates 46>, - <&de_be0_clk>, <&de_fe0_clk>, - <&tcon0_ch1_clk>, <&dram_gates 5>, - <&dram_gates 25>, <&dram_gates 26>; + clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>, + <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>, + <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>, + <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_TVE0>, + <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; status = "disabled"; }; }; @@ -112,7 +113,7 @@ device_type = "cpu"; compatible = "arm,cortex-a8"; reg = <0x0>; - clocks = <&cpu>; + clocks = <&ccu CLK_CPU>; clock-latency = <244144>; /* 8 32k periods */ operating-points = < /* kHz uV */ @@ -122,13 +123,11 @@ 624000 1250000 >; #cooling-cells = <2>; - cooling-min-level = <0>; - cooling-max-level = <3>; }; }; thermal-zones { - cpu_thermal { + cpu-thermal { /* milliseconds */ polling-delay-passive = <250>; polling-delay = <1000>; @@ -142,14 +141,14 @@ }; trips { - cpu_alert0: cpu_alert0 { + cpu_alert0: cpu-alert0 { /* milliCelsius */ temperature = <850000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit: cpu_crit { + cpu_crit: cpu-crit { /* milliCelsius */ temperature = <100000>; hysteresis = <2000>; @@ -159,532 +158,46 @@ }; }; - memory { - reg = <0x40000000 0x80000000>; - }; - clocks { #address-cells = <1>; #size-cells = <1>; ranges; - /* - * This is a dummy clock, to be used as placeholder on - * other mux clocks when a specific parent clock is not - * yet implemented. It should be dropped when the driver - * is complete. - */ - dummy: dummy { + osc24M: clk-24M { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - osc24M: clk@01c20050 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-osc-clk"; - reg = <0x01c20050 0x4>; clock-frequency = <24000000>; clock-output-names = "osc24M"; }; - osc3M: osc3M_clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - clocks = <&osc24M>; - clock-output-names = "osc3M"; - }; - - osc32k: clk@0 { + osc32k: clk-32k { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; clock-output-names = "osc32k"; }; + }; - pll1: clk@01c20000 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll1-clk"; - reg = <0x01c20000 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll1"; - }; - - pll2: clk@01c20008 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll2-clk"; - reg = <0x01c20008 0x8>; - clocks = <&osc24M>; - clock-output-names = "pll2-1x", "pll2-2x", - "pll2-4x", "pll2-8x"; - }; - - pll3: clk@01c20010 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll3-clk"; - reg = <0x01c20010 0x4>; - clocks = <&osc3M>; - clock-output-names = "pll3"; - }; - - pll3x2: pll3x2_clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <2>; - clocks = <&pll3>; - clock-output-names = "pll3-2x"; - }; - - pll4: clk@01c20018 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll1-clk"; - reg = <0x01c20018 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll4"; - }; - - pll5: clk@01c20020 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll5-clk"; - reg = <0x01c20020 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll5_ddr", "pll5_other"; - }; - - pll6: clk@01c20028 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll6-clk"; - reg = <0x01c20028 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll6_sata", "pll6_other", "pll6"; - }; - - pll7: clk@01c20030 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll3-clk"; - reg = <0x01c20030 0x4>; - clocks = <&osc3M>; - clock-output-names = "pll7"; - }; - - pll7x2: pll7x2_clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <2>; - clocks = <&pll7>; - clock-output-names = "pll7-2x"; - }; - - /* dummy is 200M */ - cpu: cpu@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-cpu-clk"; - reg = <0x01c20054 0x4>; - clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; - clock-output-names = "cpu"; - }; - - axi: axi@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-axi-clk"; - reg = <0x01c20054 0x4>; - clocks = <&cpu>; - clock-output-names = "axi"; - }; - - axi_gates: clk@01c2005c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-axi-gates-clk"; - reg = <0x01c2005c 0x4>; - clocks = <&axi>; - clock-indices = <0>; - clock-output-names = "axi_dram"; - }; - - ahb: ahb@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-ahb-clk"; - reg = <0x01c20054 0x4>; - clocks = <&axi>; - clock-output-names = "ahb"; - }; - - ahb_gates: clk@01c20060 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-ahb-gates-clk"; - reg = <0x01c20060 0x8>; - clocks = <&ahb>; - clock-indices = <0>, <1>, - <2>, <3>, - <4>, <5>, <6>, - <7>, <8>, <9>, - <10>, <11>, <12>, - <13>, <14>, <16>, - <17>, <18>, <20>, - <21>, <22>, <23>, - <24>, <25>, <26>, - <32>, <33>, <34>, - <35>, <36>, <37>, - <40>, <41>, <43>, - <44>, <45>, - <46>, <47>, - <50>, <52>; - clock-output-names = "ahb_usb0", "ahb_ehci0", - "ahb_ohci0", "ahb_ehci1", - "ahb_ohci1", "ahb_ss", "ahb_dma", - "ahb_bist", "ahb_mmc0", "ahb_mmc1", - "ahb_mmc2", "ahb_mmc3", "ahb_ms", - "ahb_nand", "ahb_sdram", "ahb_ace", - "ahb_emac", "ahb_ts", "ahb_spi0", - "ahb_spi1", "ahb_spi2", "ahb_spi3", - "ahb_pata", "ahb_sata", "ahb_gps", - "ahb_ve", "ahb_tvd", "ahb_tve0", - "ahb_tve1", "ahb_lcd0", "ahb_lcd1", - "ahb_csi0", "ahb_csi1", "ahb_hdmi", - "ahb_de_be0", "ahb_de_be1", - "ahb_de_fe0", "ahb_de_fe1", - "ahb_mp", "ahb_mali400"; - }; - - apb0: apb0@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb0-clk"; - reg = <0x01c20054 0x4>; - clocks = <&ahb>; - clock-output-names = "apb0"; - }; - - apb0_gates: clk@01c20068 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-apb0-gates-clk"; - reg = <0x01c20068 0x4>; - clocks = <&apb0>; - clock-indices = <0>, <1>, - <2>, <3>, - <5>, <6>, - <7>, <10>; - clock-output-names = "apb0_codec", "apb0_spdif", - "apb0_ac97", "apb0_iis", - "apb0_pio", "apb0_ir0", - "apb0_ir1", "apb0_keypad"; - }; - - apb1: clk@01c20058 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb1-clk"; - reg = <0x01c20058 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&osc32k>; - clock-output-names = "apb1"; - }; - - apb1_gates: clk@01c2006c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-apb1-gates-clk"; - reg = <0x01c2006c 0x4>; - clocks = <&apb1>; - clock-indices = <0>, <1>, - <2>, <4>, - <5>, <6>, - <7>, <16>, - <17>, <18>, - <19>, <20>, - <21>, <22>, - <23>; - clock-output-names = "apb1_i2c0", "apb1_i2c1", - "apb1_i2c2", "apb1_can", - "apb1_scr", "apb1_ps20", - "apb1_ps21", "apb1_uart0", - "apb1_uart1", "apb1_uart2", - "apb1_uart3", "apb1_uart4", - "apb1_uart5", "apb1_uart6", - "apb1_uart7"; - }; - - nand_clk: clk@01c20080 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20080 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "nand"; - }; - - ms_clk: clk@01c20084 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20084 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ms"; - }; - - mmc0_clk: clk@01c20088 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20088 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc0", - "mmc0_output", - "mmc0_sample"; - }; - - mmc1_clk: clk@01c2008c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c2008c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc1", - "mmc1_output", - "mmc1_sample"; - }; - - mmc2_clk: clk@01c20090 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20090 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc2", - "mmc2_output", - "mmc2_sample"; - }; - - mmc3_clk: clk@01c20094 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20094 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc3", - "mmc3_output", - "mmc3_sample"; - }; - - ts_clk: clk@01c20098 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20098 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ts"; - }; - - ss_clk: clk@01c2009c { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c2009c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ss"; - }; - - spi0_clk: clk@01c200a0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a0 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi0"; - }; - - spi1_clk: clk@01c200a4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a4 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi1"; - }; - - spi2_clk: clk@01c200a8 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a8 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi2"; - }; - - pata_clk: clk@01c200ac { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200ac 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "pata"; - }; - - ir0_clk: clk@01c200b0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200b0 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ir0"; - }; - - ir1_clk: clk@01c200b4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200b4 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ir1"; - }; - - spdif_clk: clk@01c200c0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod1-clk"; - reg = <0x01c200c0 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_8X>, - <&pll2 SUN4I_A10_PLL2_4X>, - <&pll2 SUN4I_A10_PLL2_2X>, - <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "spdif"; - }; - - usb_clk: clk@01c200cc { - #clock-cells = <1>; - #reset-cells = <1>; - compatible = "allwinner,sun4i-a10-usb-clk"; - reg = <0x01c200cc 0x4>; - clocks = <&pll6 1>; - clock-output-names = "usb_ohci0", "usb_ohci1", - "usb_phy"; - }; - - spi3_clk: clk@01c200d4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200d4 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi3"; - }; - - dram_gates: clk@01c20100 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-dram-gates-clk"; - reg = <0x01c20100 0x4>; - clocks = <&pll5 0>; - clock-indices = <0>, - <1>, <2>, - <3>, - <4>, - <5>, <6>, - <15>, - <24>, <25>, - <26>, <27>, - <28>, <29>; - clock-output-names = "dram_ve", - "dram_csi0", "dram_csi1", - "dram_ts", - "dram_tvd", - "dram_tve0", "dram_tve1", - "dram_output", - "dram_de_fe1", "dram_de_fe0", - "dram_de_be0", "dram_de_be1", - "dram_de_mp", "dram_ace"; - }; - - de_be0_clk: clk@01c20104 { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c20104 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-be0"; - }; - - de_be1_clk: clk@01c20108 { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c20108 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-be1"; - }; - - de_fe0_clk: clk@01c2010c { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c2010c 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-fe0"; - }; - - de_fe1_clk: clk@01c20110 { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c20110 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-fe1"; - }; - - - tcon0_ch0_clk: clk@01c20118 { - #clock-cells = <0>; - #reset-cells = <1>; - compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; - reg = <0x01c20118 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon0-ch0-sclk"; - - }; - - tcon1_ch0_clk: clk@01c2011c { - #clock-cells = <0>; - #reset-cells = <1>; - compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; - reg = <0x01c2011c 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon1-ch0-sclk"; - - }; - - tcon0_ch1_clk: clk@01c2012c { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; - reg = <0x01c2012c 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon0-ch1-sclk"; - - }; - - tcon1_ch1_clk: clk@01c20130 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; - reg = <0x01c20130 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon1-ch1-sclk"; - - }; - - ve_clk: clk@01c2013c { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-ve-clk"; - reg = <0x01c2013c 0x4>; - clocks = <&pll4>; - clock-output-names = "ve"; - }; - - codec_clk: clk@01c20140 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-codec-clk"; - reg = <0x01c20140 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "codec"; - }; + de: display-engine { + compatible = "allwinner,sun4i-a10-display-engine"; + allwinner,pipelines = <&fe0>, <&fe1>; + status = "disabled"; }; - soc@01c00000 { + soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; - sram-controller@01c00000 { + sram-controller@1c00000 { compatible = "allwinner,sun4i-a10-sram-controller"; reg = <0x01c00000 0x30>; #address-cells = <1>; #size-cells = <1>; ranges; - sram_a: sram@00000000 { + sram_a: sram@0 { compatible = "mmio-sram"; reg = <0x00000000 0xc000>; #address-cells = <1>; @@ -698,14 +211,14 @@ }; }; - sram_d: sram@00010000 { + sram_d: sram@10000 { compatible = "mmio-sram"; reg = <0x00010000 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x00010000 0x1000>; - otg_sram: sram-section@0000 { + otg_sram: sram-section@0 { compatible = "allwinner,sun4i-a10-sram-d"; reg = <0x0000 0x1000>; status = "disabled"; @@ -713,19 +226,19 @@ }; }; - dma: dma-controller@01c02000 { + dma: dma-controller@1c02000 { compatible = "allwinner,sun4i-a10-dma"; reg = <0x01c02000 0x1000>; interrupts = <27>; - clocks = <&ahb_gates 6>; + clocks = <&ccu CLK_AHB_DMA>; #dma-cells = <2>; }; - nfc: nand@01c03000 { + nfc: nand@1c03000 { compatible = "allwinner,sun4i-a10-nand"; reg = <0x01c03000 0x1000>; interrupts = <37>; - clocks = <&ahb_gates 13>, <&nand_clk>; + clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 3>; dma-names = "rxtx"; @@ -734,11 +247,11 @@ #size-cells = <0>; }; - spi0: spi@01c05000 { + spi0: spi@1c05000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c05000 0x1000>; interrupts = <10>; - clocks = <&ahb_gates 20>, <&spi0_clk>; + clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 27>, <&dma SUN4I_DMA_DEDICATED 26>; @@ -748,30 +261,34 @@ #size-cells = <0>; }; - spi1: spi@01c06000 { + spi1: spi@1c06000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c06000 0x1000>; interrupts = <11>; - clocks = <&ahb_gates 21>, <&spi1_clk>; + clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 9>, <&dma SUN4I_DMA_DEDICATED 8>; dma-names = "rx", "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - emac: ethernet@01c0b000 { + emac: ethernet@1c0b000 { compatible = "allwinner,sun4i-a10-emac"; reg = <0x01c0b000 0x1000>; interrupts = <55>; - clocks = <&ahb_gates 17>; + clocks = <&ccu CLK_AHB_EMAC>; allwinner,sram = <&emac_sram 1>; + pinctrl-names = "default"; + pinctrl-0 = <&emac_pins>; status = "disabled"; }; - mdio: mdio@01c0b080 { + mdio: mdio@1c0b080 { compatible = "allwinner,sun4i-a10-mdio"; reg = <0x01c0b080 0x14>; status = "disabled"; @@ -779,78 +296,154 @@ #size-cells = <0>; }; - mmc0: mmc@01c0f000 { + tcon0: lcd-controller@1c0c000 { + compatible = "allwinner,sun4i-a10-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = <44>; + resets = <&ccu RST_TCON0>; + reset-names = "lcd"; + clocks = <&ccu CLK_AHB_LCD0>, + <&ccu CLK_TCON0_CH0>, + <&ccu CLK_TCON0_CH1>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1"; + clock-output-names = "tcon0-pixel-clock"; + dmas = <&dma SUN4I_DMA_DEDICATED 14>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon0_in_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_out_tcon0>; + }; + + tcon0_in_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon0_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_tcon0>; + allwinner,tcon-channel = <1>; + }; + }; + }; + }; + + tcon1: lcd-controller@1c0d000 { + compatible = "allwinner,sun4i-a10-tcon"; + reg = <0x01c0d000 0x1000>; + interrupts = <45>; + resets = <&ccu RST_TCON1>; + reset-names = "lcd"; + clocks = <&ccu CLK_AHB_LCD1>, + <&ccu CLK_TCON1_CH0>, + <&ccu CLK_TCON1_CH1>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1"; + clock-output-names = "tcon1-pixel-clock"; + dmas = <&dma SUN4I_DMA_DEDICATED 15>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon1_in_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_out_tcon1>; + }; + + tcon1_in_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_out_tcon1>; + }; + }; + + tcon1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon1_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_tcon1>; + allwinner,tcon-channel = <1>; + }; + }; + }; + }; + + mmc0: mmc@1c0f000 { compatible = "allwinner,sun4i-a10-mmc"; reg = <0x01c0f000 0x1000>; - clocks = <&ahb_gates 8>, - <&mmc0_clk 0>, - <&mmc0_clk 1>, - <&mmc0_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; + clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>; + clock-names = "ahb", "mmc"; interrupts = <32>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - mmc1: mmc@01c10000 { + mmc1: mmc@1c10000 { compatible = "allwinner,sun4i-a10-mmc"; reg = <0x01c10000 0x1000>; - clocks = <&ahb_gates 9>, - <&mmc1_clk 0>, - <&mmc1_clk 1>, - <&mmc1_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; + clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>; + clock-names = "ahb", "mmc"; interrupts = <33>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - mmc2: mmc@01c11000 { + mmc2: mmc@1c11000 { compatible = "allwinner,sun4i-a10-mmc"; reg = <0x01c11000 0x1000>; - clocks = <&ahb_gates 10>, - <&mmc2_clk 0>, - <&mmc2_clk 1>, - <&mmc2_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; + clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>; + clock-names = "ahb", "mmc"; interrupts = <34>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - mmc3: mmc@01c12000 { + mmc3: mmc@1c12000 { compatible = "allwinner,sun4i-a10-mmc"; reg = <0x01c12000 0x1000>; - clocks = <&ahb_gates 11>, - <&mmc3_clk 0>, - <&mmc3_clk 1>, - <&mmc3_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; + clocks = <&ccu CLK_AHB_MMC3>, <&ccu CLK_MMC3>; + clock-names = "ahb", "mmc"; interrupts = <35>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - usb_otg: usb@01c13000 { + usb_otg: usb@1c13000 { compatible = "allwinner,sun4i-a10-musb"; reg = <0x01c13000 0x0400>; - clocks = <&ahb_gates 0>; + clocks = <&ccu CLK_AHB_OTG>; interrupts = <38>; interrupt-names = "mc"; phys = <&usbphy 0>; @@ -860,51 +453,95 @@ status = "disabled"; }; - usbphy: phy@01c13400 { + usbphy: phy@1c13400 { #phy-cells = <1>; compatible = "allwinner,sun4i-a10-usb-phy"; reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; reg-names = "phy_ctrl", "pmu1", "pmu2"; - clocks = <&usb_clk 8>; + clocks = <&ccu CLK_USB_PHY>; clock-names = "usb_phy"; - resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>, + <&ccu RST_USB_PHY2>; reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; status = "disabled"; }; - ehci0: usb@01c14000 { + ehci0: usb@1c14000 { compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; reg = <0x01c14000 0x100>; interrupts = <39>; - clocks = <&ahb_gates 1>; + clocks = <&ccu CLK_AHB_EHCI0>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; }; - ohci0: usb@01c14400 { + ohci0: usb@1c14400 { compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; reg = <0x01c14400 0x100>; interrupts = <64>; - clocks = <&usb_clk 6>, <&ahb_gates 2>; + clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; }; - crypto: crypto-engine@01c15000 { + crypto: crypto-engine@1c15000 { compatible = "allwinner,sun4i-a10-crypto"; reg = <0x01c15000 0x1000>; interrupts = <86>; - clocks = <&ahb_gates 5>, <&ss_clk>; + clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>; clock-names = "ahb", "mod"; }; - spi2: spi@01c17000 { + hdmi: hdmi@1c16000 { + compatible = "allwinner,sun4i-a10-hdmi"; + reg = <0x01c16000 0x1000>; + interrupts = <58>; + clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>, + <&ccu CLK_PLL_VIDEO0_2X>, + <&ccu CLK_PLL_VIDEO1_2X>; + clock-names = "ahb", "mod", "pll-0", "pll-1"; + dmas = <&dma SUN4I_DMA_NORMAL 16>, + <&dma SUN4I_DMA_NORMAL 16>, + <&dma SUN4I_DMA_DEDICATED 24>; + dma-names = "ddc-tx", "ddc-rx", "audio-tx"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + hdmi_in_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_hdmi>; + }; + + hdmi_in_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + + spi2: spi@1c17000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c17000 0x1000>; interrupts = <12>; - clocks = <&ahb_gates 22>, <&spi2_clk>; + clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 29>, <&dma SUN4I_DMA_DEDICATED 28>; @@ -914,39 +551,39 @@ #size-cells = <0>; }; - ahci: sata@01c18000 { + ahci: sata@1c18000 { compatible = "allwinner,sun4i-a10-ahci"; reg = <0x01c18000 0x1000>; interrupts = <56>; - clocks = <&pll6 0>, <&ahb_gates 25>; + clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>; status = "disabled"; }; - ehci1: usb@01c1c000 { + ehci1: usb@1c1c000 { compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; reg = <0x01c1c000 0x100>; interrupts = <40>; - clocks = <&ahb_gates 3>; + clocks = <&ccu CLK_AHB_EHCI1>; phys = <&usbphy 2>; phy-names = "usb"; status = "disabled"; }; - ohci1: usb@01c1c400 { + ohci1: usb@1c1c400 { compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; reg = <0x01c1c400 0x100>; interrupts = <65>; - clocks = <&usb_clk 7>, <&ahb_gates 4>; + clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>; phys = <&usbphy 2>; phy-names = "usb"; status = "disabled"; }; - spi3: spi@01c1f000 { + spi3: spi@1c1f000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c1f000 0x1000>; interrupts = <50>; - clocks = <&ahb_gates 23>, <&spi3_clk>; + clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 31>, <&dma SUN4I_DMA_DEDICATED 30>; @@ -956,230 +593,191 @@ #size-cells = <0>; }; - intc: interrupt-controller@01c20400 { + ccu: clock@1c20000 { + compatible = "allwinner,sun4i-a10-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + intc: interrupt-controller@1c20400 { compatible = "allwinner,sun4i-a10-ic"; reg = <0x01c20400 0x400>; interrupt-controller; #interrupt-cells = <1>; }; - pio: pinctrl@01c20800 { + pio: pinctrl@1c20800 { compatible = "allwinner,sun4i-a10-pinctrl"; reg = <0x01c20800 0x400>; interrupts = <28>; - clocks = <&apb0_gates 5>; + clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; #interrupt-cells = <3>; #gpio-cells = <3>; - emac_pins_a: emac0@0 { - allwinner,pins = "PA0", "PA1", "PA2", - "PA3", "PA4", "PA5", "PA6", - "PA7", "PA8", "PA9", "PA10", - "PA11", "PA12", "PA13", "PA14", - "PA15", "PA16"; - allwinner,function = "emac"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + can0_ph_pins: can0-ph-pins { + pins = "PH20", "PH21"; + function = "can"; }; - i2c0_pins_a: i2c0@0 { - allwinner,pins = "PB0", "PB1"; - allwinner,function = "i2c0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + emac_pins: emac0-pins { + pins = "PA0", "PA1", "PA2", + "PA3", "PA4", "PA5", "PA6", + "PA7", "PA8", "PA9", "PA10", + "PA11", "PA12", "PA13", "PA14", + "PA15", "PA16"; + function = "emac"; }; - i2c1_pins_a: i2c1@0 { - allwinner,pins = "PB18", "PB19"; - allwinner,function = "i2c1"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + i2c0_pins: i2c0-pins { + pins = "PB0", "PB1"; + function = "i2c0"; }; - i2c2_pins_a: i2c2@0 { - allwinner,pins = "PB20", "PB21"; - allwinner,function = "i2c2"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + i2c1_pins: i2c1-pins { + pins = "PB18", "PB19"; + function = "i2c1"; }; - ir0_rx_pins_a: ir0@0 { - allwinner,pins = "PB4"; - allwinner,function = "ir0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + i2c2_pins: i2c2-pins { + pins = "PB20", "PB21"; + function = "i2c2"; }; - ir0_tx_pins_a: ir0@1 { - allwinner,pins = "PB3"; - allwinner,function = "ir0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + ir0_rx_pins: ir0-rx-pin { + pins = "PB4"; + function = "ir0"; }; - ir1_rx_pins_a: ir1@0 { - allwinner,pins = "PB23"; - allwinner,function = "ir1"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + ir0_tx_pins: ir0-tx-pin { + pins = "PB3"; + function = "ir0"; }; - ir1_tx_pins_a: ir1@1 { - allwinner,pins = "PB22"; - allwinner,function = "ir1"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + ir1_rx_pins: ir1-rx-pin { + pins = "PB23"; + function = "ir1"; }; - mmc0_pins_a: mmc0@0 { - allwinner,pins = "PF0", "PF1", "PF2", - "PF3", "PF4", "PF5"; - allwinner,function = "mmc0"; - allwinner,drive = <SUN4I_PINCTRL_30_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + ir1_tx_pins: ir1-tx-pin { + pins = "PB22"; + function = "ir1"; }; - mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { - allwinner,pins = "PH1"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", + "PF3", "PF4", "PF5"; + function = "mmc0"; + drive-strength = <30>; + bias-pull-up; }; - ps20_pins_a: ps20@0 { - allwinner,pins = "PI20", "PI21"; - allwinner,function = "ps2"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + ps2_ch0_pins: ps2-ch0-pins { + pins = "PI20", "PI21"; + function = "ps2"; }; - ps21_pins_a: ps21@0 { - allwinner,pins = "PH12", "PH13"; - allwinner,function = "ps2"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + ps2_ch1_ph_pins: ps2-ch1-ph-pins { + pins = "PH12", "PH13"; + function = "ps2"; }; - pwm0_pins_a: pwm0@0 { - allwinner,pins = "PB2"; - allwinner,function = "pwm"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pwm0_pin: pwm0-pin { + pins = "PB2"; + function = "pwm"; }; - pwm1_pins_a: pwm1@0 { - allwinner,pins = "PI3"; - allwinner,function = "pwm"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pwm1_pin: pwm1-pin { + pins = "PI3"; + function = "pwm"; }; - spdif_tx_pins_a: spdif@0 { - allwinner,pins = "PB13"; - allwinner,function = "spdif"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + spdif_tx_pin: spdif-tx-pin { + pins = "PB13"; + function = "spdif"; + bias-pull-up; }; - spi0_pins_a: spi0@0 { - allwinner,pins = "PI11", "PI12", "PI13"; - allwinner,function = "spi0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + spi0_pi_pins: spi0-pi-pins { + pins = "PI11", "PI12", "PI13"; + function = "spi0"; }; - spi0_cs0_pins_a: spi0_cs0@0 { - allwinner,pins = "PI10"; - allwinner,function = "spi0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + spi0_cs0_pi_pin: spi0-cs0-pi-pin { + pins = "PI10"; + function = "spi0"; }; - spi1_pins_a: spi1@0 { - allwinner,pins = "PI17", "PI18", "PI19"; - allwinner,function = "spi1"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + spi1_pins: spi1-pins { + pins = "PI17", "PI18", "PI19"; + function = "spi1"; }; - spi1_cs0_pins_a: spi1_cs0@0 { - allwinner,pins = "PI16"; - allwinner,function = "spi1"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + spi1_cs0_pin: spi1-cs0-pin { + pins = "PI16"; + function = "spi1"; }; - spi2_pins_a: spi2@0 { - allwinner,pins = "PC20", "PC21", "PC22"; - allwinner,function = "spi2"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + spi2_pb_pins: spi2-pb-pins { + pins = "PB15", "PB16", "PB17"; + function = "spi2"; }; - spi2_pins_b: spi2@1 { - allwinner,pins = "PB15", "PB16", "PB17"; - allwinner,function = "spi2"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + spi2_pc_pins: spi2-pc-pins { + pins = "PC20", "PC21", "PC22"; + function = "spi2"; }; - spi2_cs0_pins_a: spi2_cs0@0 { - allwinner,pins = "PC19"; - allwinner,function = "spi2"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + spi2_cs0_pb_pin: spi2-cs0-pb-pin { + pins = "PB14"; + function = "spi2"; }; - spi2_cs0_pins_b: spi2_cs0@1 { - allwinner,pins = "PB14"; - allwinner,function = "spi2"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + spi2_cs0_pc_pins: spi2-cs0-pc-pin { + pins = "PC19"; + function = "spi2"; }; - uart0_pins_a: uart0@0 { - allwinner,pins = "PB22", "PB23"; - allwinner,function = "uart0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + uart0_pb_pins: uart0-pb-pins { + pins = "PB22", "PB23"; + function = "uart0"; }; - uart0_pins_b: uart0@1 { - allwinner,pins = "PF2", "PF4"; - allwinner,function = "uart0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + uart0_pf_pins: uart0-pf-pins { + pins = "PF2", "PF4"; + function = "uart0"; }; - uart1_pins_a: uart1@0 { - allwinner,pins = "PA10", "PA11"; - allwinner,function = "uart1"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + uart1_pins: uart1-pins { + pins = "PA10", "PA11"; + function = "uart1"; }; }; - timer@01c20c00 { + timer@1c20c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0x90>; interrupts = <22>; clocks = <&osc24M>; }; - wdt: watchdog@01c20c90 { + wdt: watchdog@1c20c90 { compatible = "allwinner,sun4i-a10-wdt"; reg = <0x01c20c90 0x10>; }; - rtc: rtc@01c20d00 { + rtc: rtc@1c20d00 { compatible = "allwinner,sun4i-a10-rtc"; reg = <0x01c20d00 0x20>; interrupts = <24>; }; - pwm: pwm@01c20e00 { + pwm: pwm@1c20e00 { compatible = "allwinner,sun4i-a10-pwm"; reg = <0x01c20e00 0xc>; clocks = <&osc24M>; @@ -1187,12 +785,12 @@ status = "disabled"; }; - spdif: spdif@01c21000 { + spdif: spdif@1c21000 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-spdif"; reg = <0x01c21000 0x400>; interrupts = <13>; - clocks = <&apb0_gates 1>, <&spdif_clk>; + clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>; clock-names = "apb", "spdif"; dmas = <&dma SUN4I_DMA_NORMAL 2>, <&dma SUN4I_DMA_NORMAL 2>; @@ -1200,37 +798,50 @@ status = "disabled"; }; - ir0: ir@01c21800 { + ir0: ir@1c21800 { compatible = "allwinner,sun4i-a10-ir"; - clocks = <&apb0_gates 6>, <&ir0_clk>; + clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>; clock-names = "apb", "ir"; interrupts = <5>; reg = <0x01c21800 0x40>; status = "disabled"; }; - ir1: ir@01c21c00 { + ir1: ir@1c21c00 { compatible = "allwinner,sun4i-a10-ir"; - clocks = <&apb0_gates 7>, <&ir1_clk>; + clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>; clock-names = "apb", "ir"; interrupts = <6>; reg = <0x01c21c00 0x40>; status = "disabled"; }; - lradc: lradc@01c22800 { + i2s0: i2s@1c22400 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun4i-a10-i2s"; + reg = <0x01c22400 0x400>; + interrupts = <16>; + clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>; + clock-names = "apb", "mod"; + dmas = <&dma SUN4I_DMA_NORMAL 3>, + <&dma SUN4I_DMA_NORMAL 3>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lradc: lradc@1c22800 { compatible = "allwinner,sun4i-a10-lradc-keys"; reg = <0x01c22800 0x100>; interrupts = <31>; status = "disabled"; }; - codec: codec@01c22c00 { + codec: codec@1c22c00 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-codec"; reg = <0x01c22c00 0x40>; interrupts = <30>; - clocks = <&apb0_gates 0>, <&codec_clk>; + clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>; clock-names = "apb", "codec"; dmas = <&dma SUN4I_DMA_NORMAL 19>, <&dma SUN4I_DMA_NORMAL 19>; @@ -1238,142 +849,316 @@ status = "disabled"; }; - sid: eeprom@01c23800 { + sid: eeprom@1c23800 { compatible = "allwinner,sun4i-a10-sid"; reg = <0x01c23800 0x10>; }; - rtp: rtp@01c25000 { + rtp: rtp@1c25000 { compatible = "allwinner,sun4i-a10-ts"; reg = <0x01c25000 0x100>; interrupts = <29>; #thermal-sensor-cells = <0>; }; - uart0: serial@01c28000 { + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; interrupts = <1>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 16>; + clocks = <&ccu CLK_APB1_UART0>; status = "disabled"; }; - uart1: serial@01c28400 { + uart1: serial@1c28400 { compatible = "snps,dw-apb-uart"; reg = <0x01c28400 0x400>; interrupts = <2>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 17>; + clocks = <&ccu CLK_APB1_UART1>; status = "disabled"; }; - uart2: serial@01c28800 { + uart2: serial@1c28800 { compatible = "snps,dw-apb-uart"; reg = <0x01c28800 0x400>; interrupts = <3>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 18>; + clocks = <&ccu CLK_APB1_UART2>; status = "disabled"; }; - uart3: serial@01c28c00 { + uart3: serial@1c28c00 { compatible = "snps,dw-apb-uart"; reg = <0x01c28c00 0x400>; interrupts = <4>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 19>; + clocks = <&ccu CLK_APB1_UART3>; status = "disabled"; }; - uart4: serial@01c29000 { + uart4: serial@1c29000 { compatible = "snps,dw-apb-uart"; reg = <0x01c29000 0x400>; interrupts = <17>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 20>; + clocks = <&ccu CLK_APB1_UART4>; status = "disabled"; }; - uart5: serial@01c29400 { + uart5: serial@1c29400 { compatible = "snps,dw-apb-uart"; reg = <0x01c29400 0x400>; interrupts = <18>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 21>; + clocks = <&ccu CLK_APB1_UART5>; status = "disabled"; }; - uart6: serial@01c29800 { + uart6: serial@1c29800 { compatible = "snps,dw-apb-uart"; reg = <0x01c29800 0x400>; interrupts = <19>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 22>; + clocks = <&ccu CLK_APB1_UART6>; status = "disabled"; }; - uart7: serial@01c29c00 { + uart7: serial@1c29c00 { compatible = "snps,dw-apb-uart"; reg = <0x01c29c00 0x400>; interrupts = <20>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 23>; + clocks = <&ccu CLK_APB1_UART7>; status = "disabled"; }; - i2c0: i2c@01c2ac00 { + ps20: ps2@1c2a000 { + compatible = "allwinner,sun4i-a10-ps2"; + reg = <0x01c2a000 0x400>; + interrupts = <62>; + clocks = <&ccu CLK_APB1_PS20>; + status = "disabled"; + }; + + ps21: ps2@1c2a400 { + compatible = "allwinner,sun4i-a10-ps2"; + reg = <0x01c2a400 0x400>; + interrupts = <63>; + clocks = <&ccu CLK_APB1_PS21>; + status = "disabled"; + }; + + i2c0: i2c@1c2ac00 { compatible = "allwinner,sun4i-a10-i2c"; reg = <0x01c2ac00 0x400>; interrupts = <7>; - clocks = <&apb1_gates 0>; + clocks = <&ccu CLK_APB1_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - i2c1: i2c@01c2b000 { + i2c1: i2c@1c2b000 { compatible = "allwinner,sun4i-a10-i2c"; reg = <0x01c2b000 0x400>; interrupts = <8>; - clocks = <&apb1_gates 1>; + clocks = <&ccu CLK_APB1_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - i2c2: i2c@01c2b400 { + i2c2: i2c@1c2b400 { compatible = "allwinner,sun4i-a10-i2c"; reg = <0x01c2b400 0x400>; interrupts = <9>; - clocks = <&apb1_gates 2>; + clocks = <&ccu CLK_APB1_I2C2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - ps20: ps2@01c2a000 { - compatible = "allwinner,sun4i-a10-ps2"; - reg = <0x01c2a000 0x400>; - interrupts = <62>; - clocks = <&apb1_gates 6>; + can0: can@1c2bc00 { + compatible = "allwinner,sun4i-a10-can"; + reg = <0x01c2bc00 0x400>; + interrupts = <26>; + clocks = <&ccu CLK_APB1_CAN>; status = "disabled"; }; - ps21: ps2@01c2a400 { - compatible = "allwinner,sun4i-a10-ps2"; - reg = <0x01c2a400 0x400>; - interrupts = <63>; - clocks = <&apb1_gates 7>; - status = "disabled"; + fe0: display-frontend@1e00000 { + compatible = "allwinner,sun4i-a10-display-frontend"; + reg = <0x01e00000 0x20000>; + interrupts = <47>; + clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>, + <&ccu CLK_DRAM_DE_FE0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_FE0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe0_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe0>; + }; + + fe0_out_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_in_fe0>; + }; + }; + }; + }; + + fe1: display-frontend@1e20000 { + compatible = "allwinner,sun4i-a10-display-frontend"; + reg = <0x01e20000 0x20000>; + interrupts = <48>; + clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>, + <&ccu CLK_DRAM_DE_FE1>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_FE1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe1_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe1>; + }; + + fe1_out_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_in_fe1>; + }; + }; + }; + }; + + be1: display-backend@1e40000 { + compatible = "allwinner,sun4i-a10-display-backend"; + reg = <0x01e40000 0x10000>; + interrupts = <48>; + clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>, + <&ccu CLK_DRAM_DE_BE1>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_BE1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be1_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be1>; + }; + + be1_in_fe1: endpoint@1 { + reg = <1>; + remote-endpoint = <&fe1_out_be1>; + }; + }; + + be1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be1_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_be1>; + }; + + be1_out_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_in_be1>; + }; + }; + }; + }; + + be0: display-backend@1e60000 { + compatible = "allwinner,sun4i-a10-display-backend"; + reg = <0x01e60000 0x10000>; + interrupts = <47>; + clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, + <&ccu CLK_DRAM_DE_BE0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_BE0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be0_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be0>; + }; + + be0_in_fe1: endpoint@1 { + reg = <1>; + remote-endpoint = <&fe1_out_be0>; + }; + }; + + be0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_be0>; + }; + + be0_out_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_in_be0>; + }; + }; + }; }; }; }; diff --git a/arch/arm/dts/sun5i-a10s-auxtek-t003.dts b/arch/arm/dts/sun5i-a10s-auxtek-t003.dts index d4ad021823..39504d720e 100644 --- a/arch/arm/dts/sun5i-a10s-auxtek-t003.dts +++ b/arch/arm/dts/sun5i-a10s-auxtek-t003.dts @@ -44,7 +44,6 @@ #include "sun5i-a10s.dtsi" #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Auxtek t003 A10s hdmi tv-stick"; @@ -94,8 +93,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_t003>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - cd-inverted; + cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ status = "okay"; }; @@ -109,17 +107,15 @@ &pio { mmc0_cd_pin_t003: mmc0_cd_pin@0 { - allwinner,pins = "PG1"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PG1"; + function = "gpio_in"; + bias-pull-up; }; led_pins_t003: led_pins@0 { - allwinner,pins = "PB2"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_20_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PB2"; + function = "gpio_out"; + drive-strength = <20>; }; }; @@ -139,14 +135,6 @@ status = "okay"; }; -&usb0_vbus_pin_a { - allwinner,pins = "PG13"; -}; - -&usb1_vbus_pin_a { - allwinner,pins = "PB10"; -}; - &usb_otg { dr_mode = "host"; status = "okay"; diff --git a/arch/arm/dts/sun5i-a10s-auxtek-t004.dts b/arch/arm/dts/sun5i-a10s-auxtek-t004.dts index a790ec8adb..8d4fb93312 100644 --- a/arch/arm/dts/sun5i-a10s-auxtek-t004.dts +++ b/arch/arm/dts/sun5i-a10s-auxtek-t004.dts @@ -44,7 +44,6 @@ #include "sun5i-a10s.dtsi" #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Auxtek t004 A10s hdmi tv-stick"; @@ -105,8 +104,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_t004>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - cd-inverted; + cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ status = "okay"; }; @@ -124,26 +122,32 @@ status = "okay"; }; +&otg_sram { + status = "okay"; +}; + &pio { + usb0_id_detect_pin: usb0_id_detect_pin@0 { + pins = "PG12"; + function = "gpio_in"; + bias-pull-up; + }; + mmc0_cd_pin_t004: mmc0_cd_pin@0 { - allwinner,pins = "PG1"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PG1"; + function = "gpio_in"; + bias-pull-up; }; mmc1_vcc_en_pin_t004: mmc1_vcc_en_pin@0 { - allwinner,pins = "PB18"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PB18"; + function = "gpio_out"; }; led_pins_t004: led_pins@0 { - allwinner,pins = "PB2"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_20_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PB2"; + function = "gpio_out"; + drive-strength = <20>; }; }; @@ -158,11 +162,15 @@ status = "okay"; }; -&usb1_vbus_pin_a { - allwinner,pins = "PG13"; +&usb_otg { + dr_mode = "otg"; + status = "okay"; }; &usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>; + usb0_id_det-gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; }; diff --git a/arch/arm/dts/sun5i-a10s-mk802.dts b/arch/arm/dts/sun5i-a10s-mk802.dts index 23b0114eb4..dd7fd5c3d7 100644 --- a/arch/arm/dts/sun5i-a10s-mk802.dts +++ b/arch/arm/dts/sun5i-a10s-mk802.dts @@ -92,8 +92,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_mk802>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - cd-inverted; + cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ status = "okay"; }; @@ -116,24 +115,19 @@ &pio { led_pins_mk802: led_pins@0 { - allwinner,pins = "PB2"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PB2"; + function = "gpio_out"; }; mmc0_cd_pin_mk802: mmc0_cd_pin@0 { - allwinner,pins = "PG1"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PG1"; + function = "gpio_in"; + bias-pull-up; }; usb1_vbus_pin_mk802: usb1_vbus_pin@0 { - allwinner,pins = "PB10"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PB10"; + function = "gpio_out"; }; }; @@ -150,7 +144,7 @@ }; &usb_otg { - dr_mode = "otg"; + dr_mode = "peripheral"; status = "okay"; }; diff --git a/arch/arm/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/dts/sun5i-a10s-olinuxino-micro.dts index aef91476f9..2c902ed2c8 100644 --- a/arch/arm/dts/sun5i-a10s-olinuxino-micro.dts +++ b/arch/arm/dts/sun5i-a10s-olinuxino-micro.dts @@ -48,7 +48,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Olimex A10s-Olinuxino Micro"; @@ -64,6 +63,17 @@ stdout-path = "serial0:115200n8"; }; + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -77,13 +87,17 @@ }; }; +&be0 { + status = "okay"; +}; + &ehci0 { status = "okay"; }; &emac { pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; + pinctrl-0 = <&emac_pins_b>; phy = <&phy1>; status = "okay"; }; @@ -92,6 +106,16 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; @@ -177,8 +201,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino_micro>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - cd-inverted; + cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ status = "okay"; }; @@ -187,8 +210,7 @@ pinctrl-0 = <&mmc1_pins_a>, <&mmc1_cd_pin_olinuxino_micro>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ - cd-inverted; + cd-gpios = <&pio 6 13 GPIO_ACTIVE_LOW>; /* PG13 */ status = "okay"; }; @@ -202,38 +224,32 @@ &pio { mmc0_cd_pin_olinuxino_micro: mmc0_cd_pin@0 { - allwinner,pins = "PG1"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PG1"; + function = "gpio_in"; + bias-pull-up; }; mmc1_cd_pin_olinuxino_micro: mmc1_cd_pin@0 { - allwinner,pins = "PG13"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PG13"; + function = "gpio_in"; + bias-pull-up; }; led_pins_olinuxino: led_pins@0 { - allwinner,pins = "PE3"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_20_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PE3"; + function = "gpio_out"; + drive-strength = <20>; }; usb1_vbus_pin_olinuxino_m: usb1_vbus_pin@0 { - allwinner,pins = "PB10"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PB10"; + function = "gpio_out"; }; usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PG12"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PG12"; + function = "gpio_in"; + bias-pull-up; }; }; @@ -250,8 +266,12 @@ &spi2 { pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>, - <&spi2_cs0_pins_a>; + pinctrl-0 = <&spi2_pins_b>, + <&spi2_cs0_pins_b>; + status = "okay"; +}; + +&tcon0 { status = "okay"; }; @@ -263,7 +283,7 @@ &uart2 { pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins_a>; + pinctrl-0 = <&uart2_pins_b>; status = "okay"; }; @@ -278,10 +298,6 @@ status = "okay"; }; -&usb0_vbus_pin_a { - allwinner,pins = "PG11"; -}; - &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>; diff --git a/arch/arm/dts/sun5i-a10s-r7-tv-dongle.dts b/arch/arm/dts/sun5i-a10s-r7-tv-dongle.dts index 3b057983c7..034853d1c0 100644 --- a/arch/arm/dts/sun5i-a10s-r7-tv-dongle.dts +++ b/arch/arm/dts/sun5i-a10s-r7-tv-dongle.dts @@ -45,7 +45,6 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "R7 A10s hdmi tv-stick"; @@ -81,8 +80,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_r7>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - cd-inverted; + cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ status = "okay"; }; @@ -101,24 +99,20 @@ &pio { mmc0_cd_pin_r7: mmc0_cd_pin@0 { - allwinner,pins = "PG1"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PG1"; + function = "gpio_in"; + bias-pull-up; }; led_pins_r7: led_pins@0 { - allwinner,pins = "PB2"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_20_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PB2"; + function = "gpio_out"; + drive-strength = <20>; }; usb1_vbus_pin_r7: usb1_vbus_pin@0 { - allwinner,pins = "PG13"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PG13"; + function = "gpio_out"; }; }; diff --git a/arch/arm/dts/sun5i-a10s-wobo-i5.dts b/arch/arm/dts/sun5i-a10s-wobo-i5.dts index b5de75f4c7..3f68ef5d92 100644 --- a/arch/arm/dts/sun5i-a10s-wobo-i5.dts +++ b/arch/arm/dts/sun5i-a10s-wobo-i5.dts @@ -46,7 +46,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "A10s-Wobo i5"; @@ -95,7 +94,7 @@ &emac { pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_b>; + pinctrl-0 = <&emac_pins_a>; phy = <&phy1>; status = "okay"; }; @@ -131,8 +130,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_wobo_i5>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ - cd-inverted; + cd-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 */ status = "okay"; }; @@ -146,24 +144,19 @@ &pio { led_pins_wobo_i5: led_pins@0 { - allwinner,pins = "PB2"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PB2"; + function = "gpio_out"; }; mmc0_cd_pin_wobo_i5: mmc0_cd_pin@0 { - allwinner,pins = "PB3"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PB3"; + function = "gpio_in"; + bias-pull-up; }; emac_power_pin_wobo: emac_power_pin@0 { - allwinner,pins = "PA02"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PA02"; + function = "gpio_out"; }; }; @@ -222,10 +215,6 @@ status = "okay"; }; -&usb1_vbus_pin_a { - allwinner,pins = "PG12"; -}; - &usbphy { usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; diff --git a/arch/arm/dts/sun5i-a10s.dtsi b/arch/arm/dts/sun5i-a10s.dtsi index c41a2ba34d..316cb8b294 100644 --- a/arch/arm/dts/sun5i-a10s.dtsi +++ b/arch/arm/dts/sun5i-a10s.dtsi @@ -47,7 +47,6 @@ #include "sun5i.dtsi" #include <dt-bindings/dma/sun4i-a10.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { interrupt-parent = <&intc>; @@ -61,207 +60,118 @@ #size-cells = <1>; ranges; - framebuffer@0 { + framebuffer@2 { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>, - <&ahb_gates 43>, <&ahb_gates 44>; - status = "disabled"; - }; - - framebuffer@1 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0"; - clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>, - <&ahb_gates 44>; + clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_HDMI>, + <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DRAM_DE_BE>, + <&ccu CLK_DE_BE>, <&ccu CLK_HDMI>; status = "disabled"; }; + }; - framebuffer@2 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0-tve0"; - clocks = <&pll3>, <&pll5 1>, <&ahb_gates 34>, - <&ahb_gates 36>, <&ahb_gates 44>; - status = "disabled"; - }; + display-engine { + compatible = "allwinner,sun5i-a10s-display-engine"; + allwinner,pipelines = <&fe0>; }; - clocks { - ahb_gates: clk@01c20060 { - #clock-cells = <1>; - compatible = "allwinner,sun5i-a10s-ahb-gates-clk"; - reg = <0x01c20060 0x8>; - clocks = <&ahb>; - clock-indices = <0>, <1>, - <2>, <5>, <6>, - <7>, <8>, <9>, - <10>, <13>, - <14>, <17>, <18>, - <20>, <21>, <22>, - <26>, <28>, <32>, - <34>, <36>, <40>, - <43>, <44>, - <46>, <51>, - <52>; - clock-output-names = "ahb_usbotg", "ahb_ehci", - "ahb_ohci", "ahb_ss", "ahb_dma", - "ahb_bist", "ahb_mmc0", "ahb_mmc1", - "ahb_mmc2", "ahb_nand", - "ahb_sdram", "ahb_emac", "ahb_ts", - "ahb_spi0", "ahb_spi1", "ahb_spi2", - "ahb_gps", "ahb_stimer", "ahb_ve", - "ahb_tve", "ahb_lcd", "ahb_csi", - "ahb_hdmi", "ahb_de_be", - "ahb_de_fe", "ahb_iep", - "ahb_mali400"; - }; + soc@1c00000 { + hdmi: hdmi@1c16000 { + compatible = "allwinner,sun5i-a10s-hdmi"; + reg = <0x01c16000 0x1000>; + interrupts = <58>; + clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>, + <&ccu CLK_PLL_VIDEO0_2X>, + <&ccu CLK_PLL_VIDEO1_2X>; + clock-names = "ahb", "mod", "pll-0", "pll-1"; + dmas = <&dma SUN4I_DMA_NORMAL 16>, + <&dma SUN4I_DMA_NORMAL 16>, + <&dma SUN4I_DMA_DEDICATED 24>; + dma-names = "ddc-tx", "ddc-rx", "audio-tx"; + status = "disabled"; - apb0_gates: clk@01c20068 { - #clock-cells = <1>; - compatible = "allwinner,sun5i-a10s-apb0-gates-clk"; - reg = <0x01c20068 0x4>; - clocks = <&apb0>; - clock-indices = <0>, <3>, - <5>, <6>, - <10>; - clock-output-names = "apb0_codec", "apb0_iis", - "apb0_pio", "apb0_ir", - "apb0_keypad"; - }; + ports { + #address-cells = <1>; + #size-cells = <0>; - apb1_gates: clk@01c2006c { - #clock-cells = <1>; - compatible = "allwinner,sun5i-a10s-apb1-gates-clk"; - reg = <0x01c2006c 0x4>; - clocks = <&apb1>; - clock-indices = <0>, <1>, - <2>, <16>, - <17>, <18>, - <19>; - clock-output-names = "apb1_i2c0", "apb1_i2c1", - "apb1_i2c2", "apb1_uart0", - "apb1_uart1", "apb1_uart2", - "apb1_uart3"; - }; - }; + hdmi_in: port@0 { + reg = <0>; - soc@01c00000 { - emac: ethernet@01c0b000 { - compatible = "allwinner,sun4i-a10-emac"; - reg = <0x01c0b000 0x1000>; - interrupts = <55>; - clocks = <&ahb_gates 17>; - allwinner,sram = <&emac_sram 1>; - status = "disabled"; - }; + hdmi_in_tcon0: endpoint { + remote-endpoint = <&tcon0_out_hdmi>; + }; + }; - mdio: mdio@01c0b080 { - compatible = "allwinner,sun4i-a10-mdio"; - reg = <0x01c0b080 0x14>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; + hdmi_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; }; - pwm: pwm@01c20e00 { + pwm: pwm@1c20e00 { compatible = "allwinner,sun5i-a10s-pwm"; reg = <0x01c20e00 0xc>; - clocks = <&osc24M>; + clocks = <&ccu CLK_HOSC>; #pwm-cells = <3>; status = "disabled"; }; - - uart0: serial@01c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = <1>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 16>; - status = "disabled"; - }; - - uart2: serial@01c28800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28800 0x400>; - interrupts = <3>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 18>; - status = "disabled"; - }; }; }; +&ccu { + compatible = "allwinner,sun5i-a10s-ccu"; +}; + &pio { compatible = "allwinner,sun5i-a10s-pinctrl"; uart0_pins_a: uart0@0 { - allwinner,pins = "PB19", "PB20"; - allwinner,function = "uart0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PB19", "PB20"; + function = "uart0"; }; - uart2_pins_a: uart2@0 { - allwinner,pins = "PC18", "PC19"; - allwinner,function = "uart2"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + uart2_pins_b: uart2@1 { + pins = "PC18", "PC19"; + function = "uart2"; }; - emac_pins_a: emac0@0 { - allwinner,pins = "PA0", "PA1", "PA2", + emac_pins_b: emac0@1 { + pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", "PA8", "PA9", "PA10", "PA11", "PA12", "PA13", "PA14", "PA15", "PA16"; - allwinner,function = "emac"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - emac_pins_b: emac0@1 { - allwinner,pins = "PD6", "PD7", "PD10", - "PD11", "PD12", "PD13", "PD14", - "PD15", "PD18", "PD19", "PD20", - "PD21", "PD22", "PD23", "PD24", - "PD25", "PD26", "PD27"; - allwinner,function = "emac"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + function = "emac"; }; mmc1_pins_a: mmc1@0 { - allwinner,pins = "PG3", "PG4", "PG5", + pins = "PG3", "PG4", "PG5", "PG6", "PG7", "PG8"; - allwinner,function = "mmc1"; - allwinner,drive = <SUN4I_PINCTRL_30_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + function = "mmc1"; + drive-strength = <30>; }; - spi2_pins_a: spi2@0 { - allwinner,pins = "PB12", "PB13", "PB14"; - allwinner,function = "spi2"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + spi2_pins_b: spi2@1 { + pins = "PB12", "PB13", "PB14"; + function = "spi2"; }; - spi2_cs0_pins_a: spi2_cs0@0 { - allwinner,pins = "PB11"; - allwinner,function = "spi2"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + spi2_cs0_pins_b: spi2_cs0@1 { + pins = "PB11"; + function = "spi2"; }; }; &sram_a { - emac_sram: sram-section@8000 { - compatible = "allwinner,sun4i-a10-sram-a3-a4"; - reg = <0x8000 0x4000>; - status = "disabled"; +}; + +&tcon0_out { + tcon0_out_hdmi: endpoint@2 { + reg = <2>; + remote-endpoint = <&hdmi_in_tcon0>; + allwinner,tcon-channel = <1>; }; }; diff --git a/arch/arm/dts/sun5i-a13-empire-electronix-d709.dts b/arch/arm/dts/sun5i-a13-empire-electronix-d709.dts index 6efbba6d40..378214d831 100644 --- a/arch/arm/dts/sun5i-a13-empire-electronix-d709.dts +++ b/arch/arm/dts/sun5i-a13-empire-electronix-d709.dts @@ -46,7 +46,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> #include <dt-bindings/pwm/pwm.h> / { @@ -126,8 +125,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_d709>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ - cd-inverted; + cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ status = "okay"; }; @@ -137,24 +135,21 @@ &pio { mmc0_cd_pin_d709: mmc0_cd_pin@0 { - allwinner,pins = "PG0"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PG0"; + function = "gpio_in"; + bias-pull-up; }; usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PG1"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; + pins = "PG1"; + function = "gpio_in"; + bias-pull-down; }; usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PG2"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PG2"; + function = "gpio_in"; + bias-pull-up; }; }; @@ -211,10 +206,6 @@ status = "okay"; }; -&usb0_vbus_pin_a { - allwinner,pins = "PG12"; -}; - &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; diff --git a/arch/arm/dts/sun5i-a13-hsg-h702.dts b/arch/arm/dts/sun5i-a13-hsg-h702.dts index 3724b98806..7ee0c3f6d7 100644 --- a/arch/arm/dts/sun5i-a13-hsg-h702.dts +++ b/arch/arm/dts/sun5i-a13-hsg-h702.dts @@ -46,7 +46,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "HSG H702"; @@ -121,8 +120,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_h702>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ - cd-inverted; + cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ status = "okay"; }; @@ -136,24 +134,20 @@ &pio { mmc0_cd_pin_h702: mmc0_cd_pin@0 { - allwinner,pins = "PG0"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PG0"; + function = "gpio_in"; + bias-pull-up; }; usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PG2"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PG2"; + function = "gpio_in"; + bias-pull-up; }; usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PG1"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PG1"; + function = "gpio_in"; }; }; @@ -191,7 +185,6 @@ }; ®_usb0_vbus { - pinctrl-0 = <&usb0_vbus_pin_a>; gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ status = "okay"; }; @@ -207,10 +200,6 @@ status = "okay"; }; -&usb0_vbus_pin_a { - allwinner,pins = "PG12"; -}; - &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; diff --git a/arch/arm/dts/sun5i-a13-inet-98v-rev2.dts b/arch/arm/dts/sun5i-a13-inet-98v-rev2.dts index 1b11ec95ae..439ae3b537 100644 --- a/arch/arm/dts/sun5i-a13-inet-98v-rev2.dts +++ b/arch/arm/dts/sun5i-a13-inet-98v-rev2.dts @@ -42,171 +42,9 @@ /dts-v1/; #include "sun5i-a13.dtsi" -#include "sunxi-common-regulators.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> +#include "sun5i-reference-design-tablet.dtsi" / { model = "INet-98V Rev 02"; compatible = "primux,inet98v-rev2", "allwinner,sun5i-a13"; - - aliases { - serial0 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button@200 { - label = "Volume Up"; - linux,code = <KEY_VOLUMEUP>; - channel = <0>; - voltage = <200000>; - }; - - button@400 { - label = "Volume Down"; - linux,code = <KEY_VOLUMEDOWN>; - channel = <0>; - voltage = <400000>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_inet98fv2>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ - cd-inverted; - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - mmc0_cd_pin_inet98fv2: mmc0_cd_pin@0 { - allwinner,pins = "PG0"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PG1"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PG2"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; - }; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-pll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_usb0_vbus { - gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_b>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb0_vbus_pin_a { - allwinner,pins = "PG12"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_ldo3>; - status = "okay"; }; diff --git a/arch/arm/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/dts/sun5i-a13-olinuxino-micro.dts index 081329e2b8..aa4b34fd91 100644 --- a/arch/arm/dts/sun5i-a13-olinuxino-micro.dts +++ b/arch/arm/dts/sun5i-a13-olinuxino-micro.dts @@ -46,7 +46,6 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Olimex A13-Olinuxino Micro"; @@ -100,8 +99,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxinom>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ - cd-inverted; + cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ status = "okay"; }; @@ -115,45 +113,37 @@ &pio { mmc0_cd_pin_olinuxinom: mmc0_cd_pin@0 { - allwinner,pins = "PG0"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PG0"; + function = "gpio_in"; + bias-pull-up; }; led_pins_olinuxinom: led_pins@0 { - allwinner,pins = "PG9"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_20_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PG9"; + function = "gpio_out"; + drive-strength = <20>; }; usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PG2"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PG2"; + function = "gpio_in"; + bias-pull-up; }; usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PG1"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; + pins = "PG1"; + function = "gpio_in"; + bias-pull-down; }; usb0_vbus_pin_olinuxinom: usb0_vbus_pin@0 { - allwinner,pins = "PG12"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PG12"; + function = "gpio_out"; }; usb1_vbus_pin_olinuxinom: usb1_vbus_pin@0 { - allwinner,pins = "PG11"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PG11"; + function = "gpio_out"; }; }; diff --git a/arch/arm/dts/sun5i-a13-olinuxino.dts b/arch/arm/dts/sun5i-a13-olinuxino.dts index b3c234c65e..437ad913a3 100644 --- a/arch/arm/dts/sun5i-a13-olinuxino.dts +++ b/arch/arm/dts/sun5i-a13-olinuxino.dts @@ -48,7 +48,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Olimex A13-Olinuxino"; @@ -72,6 +71,51 @@ default-state = "on"; }; }; + + bridge { + compatible = "dumb-vga-dac"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vga_bridge_in: endpoint { + remote-endpoint = <&tcon0_out_vga>; + }; + }; + + port@1 { + reg = <1>; + + vga_bridge_out: endpoint { + remote-endpoint = <&vga_con_in>; + }; + }; + }; + }; + + vga { + compatible = "vga-connector"; + + port { + vga_con_in: endpoint { + remote-endpoint = <&vga_bridge_out>; + }; + }; + }; +}; + +&be0 { + status = "okay"; +}; + +&codec { + status = "okay"; }; &ehci0 { @@ -150,8 +194,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ - cd-inverted; + cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ status = "okay"; }; @@ -165,38 +208,32 @@ &pio { mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 { - allwinner,pins = "PG0"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PG0"; + function = "gpio_in"; + bias-pull-up; }; led_pins_olinuxino: led_pins@0 { - allwinner,pins = "PG9"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_20_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PG9"; + function = "gpio_out"; + drive-strength = <20>; }; usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PG2"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PG2"; + function = "gpio_in"; + bias-pull-up; }; usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PG1"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; + pins = "PG1"; + function = "gpio_in"; + bias-pull-down; }; usb1_vbus_pin_olinuxino: usb1_vbus_pin@0 { - allwinner,pins = "PG11"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PG11"; + function = "gpio_out"; }; }; @@ -211,6 +248,19 @@ status = "okay"; }; +&tcon0 { + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rgb666_pins>; + status = "okay"; +}; + +&tcon0_out { + tcon0_out_vga: endpoint@0 { + reg = <0>; + remote-endpoint = <&vga_bridge_in>; + }; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins_b>; @@ -222,10 +272,6 @@ status = "okay"; }; -&usb0_vbus_pin_a { - allwinner,pins = "PG12"; -}; - &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; diff --git a/arch/arm/dts/sun5i-a13-utoo-p66.dts b/arch/arm/dts/sun5i-a13-utoo-p66.dts index a8b0bcc045..bfdd38d6bf 100644 --- a/arch/arm/dts/sun5i-a13-utoo-p66.dts +++ b/arch/arm/dts/sun5i-a13-utoo-p66.dts @@ -80,23 +80,7 @@ }; &codec_pa_pin { - allwinner,pins = "PG3"; -}; - -&i2c1 { - icn8318: touchscreen@40 { - compatible = "chipone,icn8318"; - reg = <0x40>; - interrupt-parent = <&pio>; - interrupts = <6 9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */ - pinctrl-names = "default"; - pinctrl-0 = <&ts_wake_pin_p66>; - wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - touchscreen-inverted-x; - touchscreen-swapped-x-y; - }; + pins = "PG3"; }; &mmc2 { @@ -116,30 +100,35 @@ &pio { i2c_lcd_pins: i2c_lcd_pin@0 { - allwinner,pins = "PG10", "PG12"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; - }; - - ts_wake_pin_p66: ts_wake_pin@0 { - allwinner,pins = "PB3"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PG10", "PG12"; + function = "gpio_out"; + bias-pull-up; }; - }; ®_usb0_vbus { gpio = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ }; +&touchscreen { + compatible = "chipone,icn8318"; + reg = <0x40>; + /* The P66 uses a different EINT then the reference design */ + interrupts = <6 9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */ + /* The icn8318 binding expects wake-gpios instead of power-gpios */ + wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-swapped-x-y; + status = "okay"; +}; + &uart1 { /* The P66 uses the uart pins as gpios */ status = "disabled"; }; &usb0_vbus_pin_a { - allwinner,pins = "PB4"; + pins = "PB4"; }; diff --git a/arch/arm/dts/sun5i-a13.dtsi b/arch/arm/dts/sun5i-a13.dtsi index e012890e0c..b1d8277655 100644 --- a/arch/arm/dts/sun5i-a13.dtsi +++ b/arch/arm/dts/sun5i-a13.dtsi @@ -46,27 +46,11 @@ #include "sun5i.dtsi" -#include <dt-bindings/pinctrl/sun4i-a10.h> #include <dt-bindings/thermal/thermal.h> / { interrupt-parent = <&intc>; - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - framebuffer@0 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0"; - clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&de_be_clk>, - <&tcon_ch0_clk>, <&dram_gates 26>; - status = "disabled"; - }; - }; - thermal-zones { cpu_thermal { /* milliseconds */ @@ -84,7 +68,7 @@ trips { cpu_alert0: cpu_alert0 { /* milliCelsius */ - temperature = <850000>; + temperature = <85000>; hysteresis = <2000>; type = "passive"; }; @@ -99,237 +83,27 @@ }; }; - clocks { - ahb_gates: clk@01c20060 { - #clock-cells = <1>; - compatible = "allwinner,sun5i-a13-ahb-gates-clk"; - reg = <0x01c20060 0x8>; - clocks = <&ahb>; - clock-indices = <0>, <1>, - <2>, <5>, <6>, - <7>, <8>, <9>, - <10>, <13>, - <14>, <20>, - <21>, <22>, - <28>, <32>, <34>, - <36>, <40>, <44>, - <46>, <51>, - <52>; - clock-output-names = "ahb_usbotg", "ahb_ehci", - "ahb_ohci", "ahb_ss", "ahb_dma", - "ahb_bist", "ahb_mmc0", "ahb_mmc1", - "ahb_mmc2", "ahb_nand", - "ahb_sdram", "ahb_spi0", - "ahb_spi1", "ahb_spi2", - "ahb_stimer", "ahb_ve", "ahb_tve", - "ahb_lcd", "ahb_csi", "ahb_de_be", - "ahb_de_fe", "ahb_iep", - "ahb_mali400"; - }; - - apb0_gates: clk@01c20068 { - #clock-cells = <1>; - compatible = "allwinner,sun5i-a13-apb0-gates-clk"; - reg = <0x01c20068 0x4>; - clocks = <&apb0>; - clock-indices = <0>, <5>, - <6>; - clock-output-names = "apb0_codec", "apb0_pio", - "apb0_ir"; - }; - - apb1_gates: clk@01c2006c { - #clock-cells = <1>; - compatible = "allwinner,sun5i-a13-apb1-gates-clk"; - reg = <0x01c2006c 0x4>; - clocks = <&apb1>; - clock-indices = <0>, <1>, - <2>, <17>, - <19>; - clock-output-names = "apb1_i2c0", "apb1_i2c1", - "apb1_i2c2", "apb1_uart1", - "apb1_uart3"; - }; - - dram_gates: clk@01c20100 { - #clock-cells = <1>; - compatible = "allwinner,sun5i-a13-dram-gates-clk", - "allwinner,sun4i-a10-gates-clk"; - reg = <0x01c20100 0x4>; - clocks = <&pll5 0>; - clock-indices = <0>, - <1>, - <25>, - <26>, - <29>, - <31>; - clock-output-names = "dram_ve", - "dram_csi", - "dram_de_fe", - "dram_de_be", - "dram_ace", - "dram_iep"; - }; - - de_be_clk: clk@01c20104 { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c20104 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-be"; - }; - - de_fe_clk: clk@01c2010c { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c2010c 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-fe"; - }; - - tcon_ch0_clk: clk@01c20118 { - #clock-cells = <0>; - #reset-cells = <1>; - compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; - reg = <0x01c20118 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon-ch0-sclk"; - }; - - tcon_ch1_clk: clk@01c2012c { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; - reg = <0x01c2012c 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon-ch1-sclk"; - }; - }; - display-engine { compatible = "allwinner,sun5i-a13-display-engine"; allwinner,pipelines = <&fe0>; }; - soc@01c00000 { - tcon0: lcd-controller@01c0c000 { - compatible = "allwinner,sun5i-a13-tcon"; - reg = <0x01c0c000 0x1000>; - interrupts = <44>; - resets = <&tcon_ch0_clk 1>; - reset-names = "lcd"; - clocks = <&ahb_gates 36>, - <&tcon_ch0_clk>, - <&tcon_ch1_clk>; - clock-names = "ahb", - "tcon-ch0", - "tcon-ch1"; - clock-output-names = "tcon-pixel-clock"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon0_in_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - }; - }; - - pwm: pwm@01c20e00 { + soc@1c00000 { + pwm: pwm@1c20e00 { compatible = "allwinner,sun5i-a13-pwm"; reg = <0x01c20e00 0xc>; - clocks = <&osc24M>; + clocks = <&ccu CLK_HOSC>; #pwm-cells = <3>; status = "disabled"; }; - fe0: display-frontend@01e00000 { - compatible = "allwinner,sun5i-a13-display-frontend"; - reg = <0x01e00000 0x20000>; - interrupts = <47>; - clocks = <&ahb_gates 46>, <&de_fe_clk>, - <&dram_gates 25>; - clock-names = "ahb", "mod", - "ram"; - resets = <&de_fe_clk>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - fe0_out_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_in_fe0>; - }; - }; - }; - }; - - be0: display-backend@01e60000 { - compatible = "allwinner,sun5i-a13-display-backend"; - reg = <0x01e60000 0x10000>; - clocks = <&ahb_gates 44>, <&de_be_clk>, - <&dram_gates 26>; - clock-names = "ahb", "mod", - "ram"; - resets = <&de_be_clk>; - status = "disabled"; - - assigned-clocks = <&de_be_clk>; - assigned-clock-rates = <300000000>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - be0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - be0_in_fe0: endpoint@0 { - reg = <0>; - remote-endpoint = <&fe0_out_be0>; - }; - }; - - be0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - be0_out_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_in_be0>; - }; - }; - }; - }; }; }; +&ccu { + compatible = "allwinner,sun5i-a13-ccu"; +}; + &cpu0 { clock-latency = <244144>; /* 8 32k periods */ operating-points = < @@ -342,34 +116,8 @@ 432000 1200000 >; #cooling-cells = <2>; - cooling-min-level = <0>; - cooling-max-level = <5>; }; &pio { compatible = "allwinner,sun5i-a13-pinctrl"; - - lcd_rgb666_pins: lcd_rgb666@0 { - allwinner,pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", - "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", - "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", - "PD24", "PD25", "PD26", "PD27"; - allwinner,function = "lcd0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - uart1_pins_a: uart1@0 { - allwinner,pins = "PE10", "PE11"; - allwinner,function = "uart1"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - uart1_pins_b: uart1@1 { - allwinner,pins = "PG3", "PG4"; - allwinner,function = "uart1"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; }; diff --git a/arch/arm/dts/sun5i-gr8-chip-pro.dts b/arch/arm/dts/sun5i-gr8-chip-pro.dts index 92a2dc6250..c55b11a4d3 100644 --- a/arch/arm/dts/sun5i-gr8-chip-pro.dts +++ b/arch/arm/dts/sun5i-gr8-chip-pro.dts @@ -159,23 +159,19 @@ &pio { usb0_id_pin_chip_pro: usb0-id-pin@0 { - allwinner,pins = "PG2"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PG2"; + function = "gpio_in"; }; wifi_reg_on_pin_chip_pro: wifi-reg-on-pin@0 { - allwinner,pins = "PB10"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PB10"; + function = "gpio_out"; }; }; &pwm { pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins_a>, <&pwm1_pins>; + pinctrl-0 = <&pwm0_pins>, <&pwm1_pins>; status = "disabled"; }; @@ -224,7 +220,7 @@ &uart1 { pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_a>, <&uart1_cts_rts_pins_a>; + pinctrl-0 = <&uart1_pins_b>, <&uart1_cts_rts_pins_a>; status = "okay"; }; diff --git a/arch/arm/dts/sun5i-gr8.dtsi b/arch/arm/dts/sun5i-gr8.dtsi index ea86d4d58d..ef0b7446a9 100644 --- a/arch/arm/dts/sun5i-gr8.dtsi +++ b/arch/arm/dts/sun5i-gr8.dtsi @@ -42,901 +42,33 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include <dt-bindings/clock/sun4i-a10-pll2.h> +#include "sun5i.dtsi" + +#include <dt-bindings/clock/sun5i-ccu.h> #include <dt-bindings/dma/sun4i-a10.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> +#include <dt-bindings/reset/sun5i-ccu.h> / { - interrupt-parent = <&intc>; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a8"; - reg = <0x0>; - clocks = <&cpu>; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * This is a dummy clock, to be used as placeholder on - * other mux clocks when a specific parent clock is not - * yet implemented. It should be dropped when the driver - * is complete. - */ - dummy: dummy { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - osc24M: clk@01c20050 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-osc-clk"; - reg = <0x01c20050 0x4>; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; - }; - - osc3M: osc3M-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - clocks = <&osc24M>; - clock-output-names = "osc3M"; - }; - - osc32k: clk@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "osc32k"; - }; - - pll1: clk@01c20000 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll1-clk"; - reg = <0x01c20000 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll1"; - }; - - pll2: clk@01c20008 { - #clock-cells = <1>; - compatible = "allwinner,sun5i-a13-pll2-clk"; - reg = <0x01c20008 0x8>; - clocks = <&osc24M>; - clock-output-names = "pll2-1x", "pll2-2x", - "pll2-4x", "pll2-8x"; - }; - - pll3: clk@01c20010 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll3-clk"; - reg = <0x01c20010 0x4>; - clocks = <&osc3M>; - clock-output-names = "pll3"; - }; - - pll3x2: pll3x2-clk { - compatible = "allwinner,sun4i-a10-pll3-2x-clk"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <2>; - clocks = <&pll3>; - clock-output-names = "pll3-2x"; - }; - - pll4: clk@01c20018 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll1-clk"; - reg = <0x01c20018 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll4"; - }; - - pll5: clk@01c20020 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll5-clk"; - reg = <0x01c20020 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll5_ddr", "pll5_other"; - }; - - pll6: clk@01c20028 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll6-clk"; - reg = <0x01c20028 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll6_sata", "pll6_other", "pll6"; - }; - - pll7: clk@01c20030 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll3-clk"; - reg = <0x01c20030 0x4>; - clocks = <&osc3M>; - clock-output-names = "pll7"; - }; - - pll7x2: pll7x2-clk { - compatible = "allwinner,sun4i-a10-pll3-2x-clk"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <2>; - clocks = <&pll7>; - clock-output-names = "pll7-2x"; - }; - - /* dummy is 200M */ - cpu: cpu@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-cpu-clk"; - reg = <0x01c20054 0x4>; - clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; - clock-output-names = "cpu"; - }; - - axi: axi@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-axi-clk"; - reg = <0x01c20054 0x4>; - clocks = <&cpu>; - clock-output-names = "axi"; - }; - - ahb: ahb@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun5i-a13-ahb-clk"; - reg = <0x01c20054 0x4>; - clocks = <&axi>, <&cpu>, <&pll6 1>; - clock-output-names = "ahb"; - /* - * Use PLL6 as parent, instead of CPU/AXI - * which has rate changes due to cpufreq - */ - assigned-clocks = <&ahb>; - assigned-clock-parents = <&pll6 1>; - }; - - apb0: apb0@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb0-clk"; - reg = <0x01c20054 0x4>; - clocks = <&ahb>; - clock-output-names = "apb0"; - }; - - apb1: clk@01c20058 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb1-clk"; - reg = <0x01c20058 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&osc32k>; - clock-output-names = "apb1"; - }; - - axi_gates: clk@01c2005c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-gates-clk"; - reg = <0x01c2005c 0x4>; - clocks = <&axi>; - clock-indices = <0>; - clock-output-names = "axi_dram"; - }; - - ahb_gates: clk@01c20060 { - #clock-cells = <1>; - compatible = "allwinner,sun5i-a13-ahb-gates-clk"; - reg = <0x01c20060 0x8>; - clocks = <&ahb>; - clock-indices = <0>, <1>, - <2>, <5>, <6>, - <7>, <8>, <9>, - <10>, <13>, - <14>, <17>, <20>, - <21>, <22>, - <28>, <32>, <34>, - <36>, <40>, <44>, - <46>, <51>, - <52>; - clock-output-names = "ahb_usbotg", "ahb_ehci", - "ahb_ohci", "ahb_ss", "ahb_dma", - "ahb_bist", "ahb_mmc0", "ahb_mmc1", - "ahb_mmc2", "ahb_nand", - "ahb_sdram", "ahb_emac", "ahb_spi0", - "ahb_spi1", "ahb_spi2", - "ahb_hstimer", "ahb_ve", "ahb_tve", - "ahb_lcd", "ahb_csi", "ahb_de_be", - "ahb_de_fe", "ahb_iep", - "ahb_mali400"; - }; - - apb0_gates: clk@01c20068 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-gates-clk"; - reg = <0x01c20068 0x4>; - clocks = <&apb0>; - clock-indices = <0>, <3>, - <5>, <6>; - clock-output-names = "apb0_codec", "apb0_i2s0", - "apb0_pio", "apb0_ir"; - }; - - apb1_gates: clk@01c2006c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-gates-clk"; - reg = <0x01c2006c 0x4>; - clocks = <&apb1>; - clock-indices = <0>, <1>, - <2>, <17>, - <18>, <19>; - clock-output-names = "apb1_i2c0", "apb1_i2c1", - "apb1_i2c2", "apb1_uart1", - "apb1_uart2", "apb1_uart3"; - }; - - nand_clk: clk@01c20080 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20080 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "nand"; - }; - - ms_clk: clk@01c20084 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20084 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ms"; - }; - - mmc0_clk: clk@01c20088 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20088 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc0", - "mmc0_output", - "mmc0_sample"; - }; - - mmc1_clk: clk@01c2008c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c2008c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc1", - "mmc1_output", - "mmc1_sample"; - }; - - mmc2_clk: clk@01c20090 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20090 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc2", - "mmc2_output", - "mmc2_sample"; - }; - - ts_clk: clk@01c20098 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20098 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ts"; - }; - - ss_clk: clk@01c2009c { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c2009c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ss"; - }; - - spi0_clk: clk@01c200a0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a0 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi0"; - }; - - spi1_clk: clk@01c200a4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a4 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi1"; - }; - - spi2_clk: clk@01c200a8 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a8 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi2"; - }; - - ir0_clk: clk@01c200b0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200b0 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ir0"; - }; - - i2s0_clk: clk@01c200b8 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod1-clk"; - reg = <0x01c200b8 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_8X>, - <&pll2 SUN4I_A10_PLL2_4X>, - <&pll2 SUN4I_A10_PLL2_2X>, - <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "i2s0"; - }; - - spdif_clk: clk@01c200c0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod1-clk"; - reg = <0x01c200c0 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_8X>, - <&pll2 SUN4I_A10_PLL2_4X>, - <&pll2 SUN4I_A10_PLL2_2X>, - <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "spdif"; - }; - - usb_clk: clk@01c200cc { - #clock-cells = <1>; - #reset-cells = <1>; - compatible = "allwinner,sun5i-a13-usb-clk"; - reg = <0x01c200cc 0x4>; - clocks = <&pll6 1>; - clock-output-names = "usb_ohci0", "usb_phy"; - }; - - dram_gates: clk@01c20100 { - #clock-cells = <1>; - compatible = "nextthing,gr8-dram-gates-clk", - "allwinner,sun4i-a10-gates-clk"; - reg = <0x01c20100 0x4>; - clocks = <&pll5 0>; - clock-indices = <0>, - <1>, - <25>, - <26>, - <29>, - <31>; - clock-output-names = "dram_ve", - "dram_csi", - "dram_de_fe", - "dram_de_be", - "dram_ace", - "dram_iep"; - }; - - de_be_clk: clk@01c20104 { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c20104 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-be"; - }; - - de_fe_clk: clk@01c2010c { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c2010c 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-fe"; - }; - - tcon_ch0_clk: clk@01c20118 { - #clock-cells = <0>; - #reset-cells = <1>; - compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; - reg = <0x01c20118 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon-ch0-sclk"; - }; - - tcon_ch1_clk: clk@01c2012c { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; - reg = <0x01c2012c 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon-ch1-sclk"; - }; - - codec_clk: clk@01c20140 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-codec-clk"; - reg = <0x01c20140 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "codec"; - }; - - mbus_clk: clk@01c2015c { - #clock-cells = <0>; - compatible = "allwinner,sun5i-a13-mbus-clk"; - reg = <0x01c2015c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mbus"; - }; - }; - display-engine { compatible = "allwinner,sun5i-a13-display-engine"; allwinner,pipelines = <&fe0>; }; - soc@01c00000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram-controller@01c00000 { - compatible = "allwinner,sun4i-a10-sram-controller"; - reg = <0x01c00000 0x30>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram_a: sram@00000000 { - compatible = "mmio-sram"; - reg = <0x00000000 0xc000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00000000 0xc000>; - }; - - sram_d: sram@00010000 { - compatible = "mmio-sram"; - reg = <0x00010000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00010000 0x1000>; - - otg_sram: sram-section@0000 { - compatible = "allwinner,sun4i-a10-sram-d"; - reg = <0x0000 0x1000>; - status = "disabled"; - }; - }; - }; - - dma: dma-controller@01c02000 { - compatible = "allwinner,sun4i-a10-dma"; - reg = <0x01c02000 0x1000>; - interrupts = <27>; - clocks = <&ahb_gates 6>; - #dma-cells = <2>; - }; - - nfc: nand@01c03000 { - compatible = "allwinner,sun4i-a10-nand"; - reg = <0x01c03000 0x1000>; - interrupts = <37>; - clocks = <&ahb_gates 13>, <&nand_clk>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 3>; - dma-names = "rxtx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi0: spi@01c05000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c05000 0x1000>; - interrupts = <10>; - clocks = <&ahb_gates 20>, <&spi0_clk>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 27>, - <&dma SUN4I_DMA_DEDICATED 26>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@01c06000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c06000 0x1000>; - interrupts = <11>; - clocks = <&ahb_gates 21>, <&spi1_clk>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 9>, - <&dma SUN4I_DMA_DEDICATED 8>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - tve0: tv-encoder@01c0a000 { - compatible = "allwinner,sun4i-a10-tv-encoder"; - reg = <0x01c0a000 0x1000>; - clocks = <&ahb_gates 34>; - resets = <&tcon_ch0_clk 0>; - status = "disabled"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - tve0_in_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_out_tve0>; - }; - }; - }; - - tcon0: lcd-controller@01c0c000 { - compatible = "allwinner,sun5i-a13-tcon"; - reg = <0x01c0c000 0x1000>; - interrupts = <44>; - resets = <&tcon_ch0_clk 1>; - reset-names = "lcd"; - clocks = <&ahb_gates 36>, - <&tcon_ch0_clk>, - <&tcon_ch1_clk>; - clock-names = "ahb", - "tcon-ch0", - "tcon-ch1"; - clock-output-names = "tcon-pixel-clock"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon0_in_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon0_out_tve0: endpoint@1 { - reg = <1>; - remote-endpoint = <&tve0_in_tcon0>; - }; - }; - }; - }; - - mmc0: mmc@01c0f000 { - compatible = "allwinner,sun5i-a13-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ahb_gates 8>, - <&mmc0_clk 0>, - <&mmc0_clk 1>, - <&mmc0_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - interrupts = <32>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@01c10000 { - compatible = "allwinner,sun5i-a13-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&ahb_gates 9>, - <&mmc1_clk 0>, - <&mmc1_clk 1>, - <&mmc1_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - interrupts = <33>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@01c11000 { - compatible = "allwinner,sun5i-a13-mmc"; - reg = <0x01c11000 0x1000>; - clocks = <&ahb_gates 10>, - <&mmc2_clk 0>, - <&mmc2_clk 1>, - <&mmc2_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - interrupts = <34>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - usb_otg: usb@01c13000 { - compatible = "allwinner,sun4i-a10-musb"; - reg = <0x01c13000 0x0400>; - clocks = <&ahb_gates 0>; - interrupts = <38>; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - allwinner,sram = <&otg_sram 1>; - status = "disabled"; - - dr_mode = "otg"; - }; - - usbphy: phy@01c13400 { - #phy-cells = <1>; - compatible = "allwinner,sun5i-a13-usb-phy"; - reg = <0x01c13400 0x10 0x01c14800 0x4>; - reg-names = "phy_ctrl", "pmu1"; - clocks = <&usb_clk 8>; - clock-names = "usb_phy"; - resets = <&usb_clk 0>, <&usb_clk 1>; - reset-names = "usb0_reset", "usb1_reset"; - status = "disabled"; - }; - - ehci0: usb@01c14000 { - compatible = "allwinner,sun5i-a13-ehci", "generic-ehci"; - reg = <0x01c14000 0x100>; - interrupts = <39>; - clocks = <&ahb_gates 1>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@01c14400 { - compatible = "allwinner,sun5i-a13-ohci", "generic-ohci"; - reg = <0x01c14400 0x100>; - interrupts = <40>; - clocks = <&usb_clk 6>, <&ahb_gates 2>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - spi2: spi@01c17000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c17000 0x1000>; - interrupts = <12>; - clocks = <&ahb_gates 22>, <&spi2_clk>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 29>, - <&dma SUN4I_DMA_DEDICATED 28>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - intc: interrupt-controller@01c20400 { - compatible = "allwinner,sun4i-a10-ic"; - reg = <0x01c20400 0x400>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - pio: pinctrl@01c20800 { - compatible = "nextthing,gr8-pinctrl"; - reg = <0x01c20800 0x400>; - interrupts = <28>; - clocks = <&apb0_gates 5>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - i2c0_pins_a: i2c0@0 { - allwinner,pins = "PB0", "PB1"; - allwinner,function = "i2c0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - i2c1_pins_a: i2c1@0 { - allwinner,pins = "PB15", "PB16"; - allwinner,function = "i2c1"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - i2c2_pins_a: i2c2@0 { - allwinner,pins = "PB17", "PB18"; - allwinner,function = "i2c2"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - i2s0_data_pins_a: i2s0-data@0 { - allwinner,pins = "PB6", "PB7", "PB8", "PB9"; - allwinner,function = "i2s0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - i2s0_mclk_pins_a: i2s0-mclk@0 { - allwinner,pins = "PB5"; - allwinner,function = "i2s0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - ir0_rx_pins_a: ir0@0 { - allwinner,pins = "PB4"; - allwinner,function = "ir0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - lcd_rgb666_pins: lcd-rgb666@0 { - allwinner,pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", - "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", - "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", - "PD24", "PD25", "PD26", "PD27"; - allwinner,function = "lcd0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - mmc0_pins_a: mmc0@0 { - allwinner,pins = "PF0", "PF1", "PF2", "PF3", - "PF4", "PF5"; - allwinner,function = "mmc0"; - allwinner,drive = <SUN4I_PINCTRL_30_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - nand_pins_a: nand-base0@0 { - allwinner,pins = "PC0", "PC1", "PC2", - "PC5", "PC8", "PC9", "PC10", - "PC11", "PC12", "PC13", "PC14", - "PC15"; - allwinner,function = "nand0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - nand_cs0_pins_a: nand-cs@0 { - allwinner,pins = "PC4"; - allwinner,function = "nand0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - nand_rb0_pins_a: nand-rb@0 { - allwinner,pins = "PC6"; - allwinner,function = "nand0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - pwm0_pins_a: pwm0@0 { - allwinner,pins = "PB2"; - allwinner,function = "pwm0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - pwm1_pins: pwm1 { - allwinner,pins = "PG13"; - allwinner,function = "pwm1"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - spdif_tx_pins_a: spdif@0 { - allwinner,pins = "PB10"; - allwinner,function = "spdif"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; - }; - - uart1_pins_a: uart1@1 { - allwinner,pins = "PG3", "PG4"; - allwinner,function = "uart1"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - uart1_cts_rts_pins_a: uart1-cts-rts@0 { - allwinner,pins = "PG5", "PG6"; - allwinner,function = "uart1"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - uart2_pins_a: uart2@1 { - allwinner,pins = "PD2", "PD3"; - allwinner,function = "uart2"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - uart2_cts_rts_pins_a: uart2-cts-rts@0 { - allwinner,pins = "PD4", "PD5"; - allwinner,function = "uart2"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - uart3_pins_a: uart3@1 { - allwinner,pins = "PG9", "PG10"; - allwinner,function = "uart3"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - uart3_cts_rts_pins_a: uart3-cts-rts@0 { - allwinner,pins = "PG11", "PG12"; - allwinner,function = "uart3"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - }; - - pwm: pwm@01c20e00 { + soc@1c00000 { + pwm: pwm@1c20e00 { compatible = "allwinner,sun5i-a10s-pwm"; reg = <0x01c20e00 0xc>; - clocks = <&osc24M>; + clocks = <&ccu CLK_HOSC>; #pwm-cells = <3>; status = "disabled"; }; - timer@01c20c00 { - compatible = "allwinner,sun4i-a10-timer"; - reg = <0x01c20c00 0x90>; - interrupts = <22>; - clocks = <&osc24M>; - }; - - wdt: watchdog@01c20c90 { - compatible = "allwinner,sun4i-a10-wdt"; - reg = <0x01c20c90 0x10>; - }; - - spdif: spdif@01c21000 { + spdif: spdif@1c21000 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-spdif"; reg = <0x01c21000 0x400>; interrupts = <13>; - clocks = <&apb0_gates 1>, <&spdif_clk>; + clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>; clock-names = "apb", "spdif"; dmas = <&dma SUN4I_DMA_NORMAL 2>, <&dma SUN4I_DMA_NORMAL 2>; @@ -944,189 +76,51 @@ status = "disabled"; }; - ir0: ir@01c21800 { - compatible = "allwinner,sun4i-a10-ir"; - clocks = <&apb0_gates 6>, <&ir0_clk>; - clock-names = "apb", "ir"; - interrupts = <5>; - reg = <0x01c21800 0x40>; - status = "disabled"; - }; - - i2s0: i2s@01c22400 { + i2s0: i2s@1c22400 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-i2s"; reg = <0x01c22400 0x400>; interrupts = <16>; - clocks = <&apb0_gates 3>, <&i2s0_clk>; + clocks = <&ccu CLK_APB0_I2S>, <&ccu CLK_I2S>; clock-names = "apb", "mod"; dmas = <&dma SUN4I_DMA_NORMAL 3>, <&dma SUN4I_DMA_NORMAL 3>; dma-names = "rx", "tx"; status = "disabled"; }; + }; +}; - lradc: lradc@01c22800 { - compatible = "allwinner,sun4i-a10-lradc-keys"; - reg = <0x01c22800 0x100>; - interrupts = <31>; - status = "disabled"; - }; - - codec: codec@01c22c00 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-codec"; - reg = <0x01c22c00 0x40>; - interrupts = <30>; - clocks = <&apb0_gates 0>, <&codec_clk>; - clock-names = "apb", "codec"; - dmas = <&dma SUN4I_DMA_NORMAL 19>, - <&dma SUN4I_DMA_NORMAL 19>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - rtp: rtp@01c25000 { - compatible = "allwinner,sun5i-a13-ts"; - reg = <0x01c25000 0x100>; - interrupts = <29>; - #thermal-sensor-cells = <0>; - }; - - uart1: serial@01c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = <2>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 17>; - status = "disabled"; - }; - - uart2: serial@01c28800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28800 0x400>; - interrupts = <3>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 18>; - status = "disabled"; - }; - - uart3: serial@01c28c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28c00 0x400>; - interrupts = <4>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 19>; - status = "disabled"; - }; - - i2c0: i2c@01c2ac00 { - compatible = "allwinner,sun4i-a10-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = <7>; - clocks = <&apb1_gates 0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@01c2b000 { - compatible = "allwinner,sun4i-a10-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = <8>; - clocks = <&apb1_gates 1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@01c2b400 { - compatible = "allwinner,sun4i-a10-i2c"; - reg = <0x01c2b400 0x400>; - interrupts = <9>; - clocks = <&apb1_gates 2>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - timer@01c60000 { - compatible = "allwinner,sun5i-a13-hstimer"; - reg = <0x01c60000 0x1000>; - interrupts = <82>, <83>; - clocks = <&ahb_gates 28>; - }; - - fe0: display-frontend@01e00000 { - compatible = "allwinner,sun5i-a13-display-frontend"; - reg = <0x01e00000 0x20000>; - interrupts = <47>; - clocks = <&ahb_gates 46>, <&de_fe_clk>, - <&dram_gates 25>; - clock-names = "ahb", "mod", - "ram"; - resets = <&de_fe_clk>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - fe0_out_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_in_fe0>; - }; - }; - }; - }; - - be0: display-backend@01e60000 { - compatible = "allwinner,sun5i-a13-display-backend"; - reg = <0x01e60000 0x10000>; - clocks = <&ahb_gates 44>, <&de_be_clk>, - <&dram_gates 26>; - clock-names = "ahb", "mod", - "ram"; - resets = <&de_be_clk>; - status = "disabled"; +&ccu { + compatible = "nextthing,gr8-ccu"; +}; - assigned-clocks = <&de_be_clk>; - assigned-clock-rates = <300000000>; +&pio { + compatible = "nextthing,gr8-pinctrl"; - ports { - #address-cells = <1>; - #size-cells = <0>; + i2s0_data_pins_a: i2s0-data@0 { + pins = "PB6", "PB7", "PB8", "PB9"; + function = "i2s0"; + }; - be0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; + i2s0_mclk_pins_a: i2s0-mclk@0 { + pins = "PB5"; + function = "i2s0"; + }; - be0_in_fe0: endpoint@0 { - reg = <0>; - remote-endpoint = <&fe0_out_be0>; - }; - }; + pwm1_pins: pwm1 { + pins = "PG13"; + function = "pwm1"; + }; - be0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; + spdif_tx_pins_a: spdif@0 { + pins = "PB10"; + function = "spdif"; + bias-pull-up; + }; - be0_out_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_in_be0>; - }; - }; - }; - }; + uart1_cts_rts_pins_a: uart1-cts-rts@0 { + pins = "PG5", "PG6"; + function = "uart1"; }; }; diff --git a/arch/arm/dts/sun5i-r8-chip.dts b/arch/arm/dts/sun5i-r8-chip.dts index 7a8cc27279..879a4b0f3b 100644 --- a/arch/arm/dts/sun5i-r8-chip.dts +++ b/arch/arm/dts/sun5i-r8-chip.dts @@ -56,25 +56,39 @@ aliases { i2c0 = &i2c0; + i2c1 = &i2c1; i2c2 = &i2c2; serial0 = &uart1; serial1 = &uart3; + spi0 = &spi2; }; chosen { stdout-path = "serial0:115200n8"; }; - wifi_reg_on: wifi_reg_on { - compatible = "regulator-fixed"; + leds { + compatible = "gpio-leds"; + + status { + label = "chip:white:status"; + gpios = <&axp_gpio 2 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + mmc0_pwrseq: mmc0_pwrseq { + compatible = "mmc-pwrseq-simple"; pinctrl-names = "default"; pinctrl-0 = <&chip_wifi_reg_on_pin>; + reset-gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; /* PC19 */ + }; - regulator-name = "wifi-reg-on"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pio 2 19 GPIO_ACTIVE_HIGH>; /* PC19 */ - enable-active-high; + onewire { + compatible = "w1-gpio"; + gpios = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */ + pinctrl-names = "default"; + pinctrl-0 = <&chip_w1_pin>; }; }; @@ -114,6 +128,20 @@ #include "axp209.dtsi" +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "disabled"; +}; + &i2c2 { pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins_a>; @@ -134,13 +162,14 @@ }; &mmc0_pins_a { - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + bias-pull-up; }; &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>; - vmmc-supply = <&wifi_reg_on>; + vmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&mmc0_pwrseq>; bus-width = <4>; non-removable; status = "okay"; @@ -156,24 +185,24 @@ &pio { chip_vbus_pin: chip_vbus_pin@0 { - allwinner,pins = "PB10"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PB10"; + function = "gpio_out"; }; chip_wifi_reg_on_pin: chip_wifi_reg_on_pin@0 { - allwinner,pins = "PC19"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PC19"; + function = "gpio_out"; }; chip_id_det_pin: chip_id_det_pin@0 { - allwinner,pins = "PG2"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PG2"; + function = "gpio_in"; + }; + + chip_w1_pin: chip_w1_pin@0 { + pins = "PD2"; + function = "gpio_in"; + bias-pull-up; }; }; @@ -202,17 +231,25 @@ regulator-always-on; }; +/* + * Both LDO3 and LDO4 are used in parallel to power up the WiFi/BT + * Chip. + * + * If those are not enabled, the SDIO part will not enumerate, and + * since there's no way currently to pass DT infos to an SDIO device, + * we cannot really do better than this ugly hack for now. + */ ®_ldo3 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-name = "vdd-wifi1"; + regulator-name = "vcc-wifi-1"; regulator-always-on; }; ®_ldo4 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-name = "vdd-wifi2"; + regulator-name = "vcc-wifi-2"; regulator-always-on; }; @@ -229,6 +266,12 @@ status = "okay"; }; +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "disabled"; +}; + &tcon0 { status = "okay"; }; @@ -246,7 +289,7 @@ &uart3 { pinctrl-names = "default"; pinctrl-0 = <&uart3_pins_a>, - <&uart3_pins_cts_rts_a>; + <&uart3_cts_rts_pins_a>; status = "okay"; }; diff --git a/arch/arm/dts/sun5i-r8.dtsi b/arch/arm/dts/sun5i-r8.dtsi index 8b058f53b7..de35dbcd11 100644 --- a/arch/arm/dts/sun5i-r8.dtsi +++ b/arch/arm/dts/sun5i-r8.dtsi @@ -45,43 +45,3 @@ #include "sun5i-a13.dtsi" -/ { - chosen { - framebuffer@1 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0-tve0"; - clocks = <&ahb_gates 34>, <&ahb_gates 36>, - <&ahb_gates 44>, <&de_be_clk>, - <&tcon_ch1_clk>, <&dram_gates 26>; - status = "disabled"; - }; - }; - - soc@01c00000 { - tve0: tv-encoder@01c0a000 { - compatible = "allwinner,sun4i-a10-tv-encoder"; - reg = <0x01c0a000 0x1000>; - clocks = <&ahb_gates 34>; - resets = <&tcon_ch0_clk 0>; - status = "disabled"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - tve0_in_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_out_tve0>; - }; - }; - }; - }; -}; - -&tcon0_out { - tcon0_out_tve0: endpoint@1 { - reg = <1>; - remote-endpoint = <&tve0_in_tcon0>; - }; -}; diff --git a/arch/arm/dts/sun5i-reference-design-tablet.dtsi b/arch/arm/dts/sun5i-reference-design-tablet.dtsi index 20cc940f5f..8acbaab14f 100644 --- a/arch/arm/dts/sun5i-reference-design-tablet.dtsi +++ b/arch/arm/dts/sun5i-reference-design-tablet.dtsi @@ -41,6 +41,7 @@ */ #include "sunxi-reference-design-tablet.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pwm/pwm.h> / { @@ -84,6 +85,23 @@ }; &i2c1 { + /* + * The gsl1680 is rated at 400KHz and it will not work reliable at + * 100KHz, this has been confirmed on multiple different q8 tablets. + * All other devices on this bus are also rated for 400KHz. + */ + clock-frequency = <400000>; + + touchscreen: touchscreen { + interrupt-parent = <&pio>; + interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>; /* EINT11 (PG11) */ + pinctrl-names = "default"; + pinctrl-0 = <&ts_power_pin>; + power-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ + /* Tablet dts must provide reg and compatible */ + status = "disabled"; + }; + pcf8563: rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; @@ -92,6 +110,14 @@ #include "axp209.dtsi" +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + &lradc { vref-supply = <®_ldo2>; }; @@ -101,8 +127,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; vmmc-supply = <®_vcc3v0>; bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ - cd-inverted; + cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ status = "okay"; }; @@ -112,38 +137,38 @@ &pio { codec_pa_pin: codec_pa_pin@0 { - allwinner,pins = "PG10"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PG10"; + function = "gpio_out"; }; mmc0_cd_pin: mmc0_cd_pin@0 { - allwinner,pins = "PG0"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PG0"; + function = "gpio_in"; + bias-pull-up; + }; + + ts_power_pin: ts_power_pin { + pins = "PB3"; + function = "gpio_out"; + drive-strength = <10>; + bias-disable; }; usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PG1"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; + pins = "PG1"; + function = "gpio_in"; + bias-pull-down; }; usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PG2"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PG2"; + function = "gpio_in"; + bias-pull-up; }; usb0_vbus_pin_a: usb0_vbus_pin@0 { - allwinner,pins = "PG12"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PG12"; + function = "gpio_out"; }; }; diff --git a/arch/arm/dts/sun5i.dtsi b/arch/arm/dts/sun5i.dtsi index e374f4fc80..07f2248ed5 100644 --- a/arch/arm/dts/sun5i.dtsi +++ b/arch/arm/dts/sun5i.dtsi @@ -44,9 +44,9 @@ #include "skeleton.dtsi" -#include <dt-bindings/clock/sun4i-a10-pll2.h> +#include <dt-bindings/clock/sun5i-ccu.h> #include <dt-bindings/dma/sun4i-a10.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> +#include <dt-bindings/reset/sun5i-ccu.h> / { interrupt-parent = <&intc>; @@ -59,42 +59,45 @@ device_type = "cpu"; compatible = "arm,cortex-a8"; reg = <0x0>; - clocks = <&cpu>; + clocks = <&ccu CLK_CPU>; }; }; - clocks { + chosen { #address-cells = <1>; #size-cells = <1>; ranges; - /* - * This is a dummy clock, to be used as placeholder on - * other mux clocks when a specific parent clock is not - * yet implemented. It should be dropped when the driver - * is complete. - */ - dummy: dummy { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; + framebuffer@0 { + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "de_be0-lcd0"; + clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>, + <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>; + status = "disabled"; }; - osc24M: clk@01c20050 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-osc-clk"; - reg = <0x01c20050 0x4>; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; + framebuffer@1 { + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "de_be0-lcd0-tve0"; + clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>, + <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>, + <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>; + status = "disabled"; }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; - osc3M: osc3M_clk { - compatible = "fixed-factor-clock"; + osc24M: clk@1c20050 { #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - clocks = <&osc24M>; - clock-output-names = "osc3M"; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; }; osc32k: clk@0 { @@ -103,272 +106,22 @@ clock-frequency = <32768>; clock-output-names = "osc32k"; }; - - pll1: clk@01c20000 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll1-clk"; - reg = <0x01c20000 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll1"; - }; - - pll2: clk@01c20008 { - #clock-cells = <1>; - compatible = "allwinner,sun5i-a13-pll2-clk"; - reg = <0x01c20008 0x8>; - clocks = <&osc24M>; - clock-output-names = "pll2-1x", "pll2-2x", - "pll2-4x", "pll2-8x"; - }; - - pll3: clk@01c20010 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll3-clk"; - reg = <0x01c20010 0x4>; - clocks = <&osc3M>; - clock-output-names = "pll3"; - }; - - pll3x2: pll3x2_clk { - compatible = "allwinner,sun4i-a10-pll3-2x-clk", "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <2>; - clocks = <&pll3>; - clock-output-names = "pll3-2x"; - }; - - pll4: clk@01c20018 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll1-clk"; - reg = <0x01c20018 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll4"; - }; - - pll5: clk@01c20020 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll5-clk"; - reg = <0x01c20020 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll5_ddr", "pll5_other"; - }; - - pll6: clk@01c20028 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll6-clk"; - reg = <0x01c20028 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll6_sata", "pll6_other", "pll6"; - }; - - pll7: clk@01c20030 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll3-clk"; - reg = <0x01c20030 0x4>; - clocks = <&osc3M>; - clock-output-names = "pll7"; - }; - - pll7x2: pll7x2_clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <2>; - clocks = <&pll7>; - clock-output-names = "pll7-2x"; - }; - - /* dummy is 200M */ - cpu: cpu@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-cpu-clk"; - reg = <0x01c20054 0x4>; - clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; - clock-output-names = "cpu"; - }; - - axi: axi@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-axi-clk"; - reg = <0x01c20054 0x4>; - clocks = <&cpu>; - clock-output-names = "axi"; - }; - - ahb: ahb@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun5i-a13-ahb-clk"; - reg = <0x01c20054 0x4>; - clocks = <&axi>, <&cpu>, <&pll6 1>; - clock-output-names = "ahb"; - /* - * Use PLL6 as parent, instead of CPU/AXI - * which has rate changes due to cpufreq - */ - assigned-clocks = <&ahb>; - assigned-clock-parents = <&pll6 1>; - }; - - apb0: apb0@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb0-clk"; - reg = <0x01c20054 0x4>; - clocks = <&ahb>; - clock-output-names = "apb0"; - }; - - apb1: clk@01c20058 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb1-clk"; - reg = <0x01c20058 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&osc32k>; - clock-output-names = "apb1"; - }; - - axi_gates: clk@01c2005c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-axi-gates-clk"; - reg = <0x01c2005c 0x4>; - clocks = <&axi>; - clock-indices = <0>; - clock-output-names = "axi_dram"; - }; - - nand_clk: clk@01c20080 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20080 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "nand"; - }; - - ms_clk: clk@01c20084 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20084 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ms"; - }; - - mmc0_clk: clk@01c20088 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20088 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc0", - "mmc0_output", - "mmc0_sample"; - }; - - mmc1_clk: clk@01c2008c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c2008c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc1", - "mmc1_output", - "mmc1_sample"; - }; - - mmc2_clk: clk@01c20090 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20090 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc2", - "mmc2_output", - "mmc2_sample"; - }; - - ts_clk: clk@01c20098 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20098 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ts"; - }; - - ss_clk: clk@01c2009c { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c2009c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ss"; - }; - - spi0_clk: clk@01c200a0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a0 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi0"; - }; - - spi1_clk: clk@01c200a4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a4 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi1"; - }; - - spi2_clk: clk@01c200a8 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a8 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi2"; - }; - - ir0_clk: clk@01c200b0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200b0 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ir0"; - }; - - usb_clk: clk@01c200cc { - #clock-cells = <1>; - #reset-cells = <1>; - compatible = "allwinner,sun5i-a13-usb-clk"; - reg = <0x01c200cc 0x4>; - clocks = <&pll6 1>; - clock-output-names = "usb_ohci0", "usb_phy"; - }; - - codec_clk: clk@01c20140 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-codec-clk"; - reg = <0x01c20140 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "codec"; - }; - - mbus_clk: clk@01c2015c { - #clock-cells = <0>; - compatible = "allwinner,sun5i-a13-mbus-clk"; - reg = <0x01c2015c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mbus"; - }; }; - soc@01c00000 { + soc@1c00000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; - sram-controller@01c00000 { + sram-controller@1c00000 { compatible = "allwinner,sun4i-a10-sram-controller"; reg = <0x01c00000 0x30>; #address-cells = <1>; #size-cells = <1>; ranges; - sram_a: sram@00000000 { + sram_a: sram@0 { compatible = "mmio-sram"; reg = <0x00000000 0xc000>; #address-cells = <1>; @@ -376,14 +129,20 @@ ranges = <0 0x00000000 0xc000>; }; - sram_d: sram@00010000 { + emac_sram: sram-section@8000 { + compatible = "allwinner,sun4i-a10-sram-a3-a4"; + reg = <0x8000 0x4000>; + status = "disabled"; + }; + + sram_d: sram@10000 { compatible = "mmio-sram"; reg = <0x00010000 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x00010000 0x1000>; - otg_sram: sram-section@0000 { + otg_sram: sram-section@0 { compatible = "allwinner,sun4i-a10-sram-d"; reg = <0x0000 0x1000>; status = "disabled"; @@ -391,19 +150,32 @@ }; }; - dma: dma-controller@01c02000 { + dma: dma-controller@1c02000 { compatible = "allwinner,sun4i-a10-dma"; reg = <0x01c02000 0x1000>; interrupts = <27>; - clocks = <&ahb_gates 6>; + clocks = <&ccu CLK_AHB_DMA>; #dma-cells = <2>; }; - spi0: spi@01c05000 { + nfc: nand@1c03000 { + compatible = "allwinner,sun4i-a10-nand"; + reg = <0x01c03000 0x1000>; + interrupts = <37>; + clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>; + clock-names = "ahb", "mod"; + dmas = <&dma SUN4I_DMA_DEDICATED 3>; + dma-names = "rxtx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi0: spi@1c05000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c05000 0x1000>; interrupts = <10>; - clocks = <&ahb_gates 20>, <&spi0_clk>; + clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 27>, <&dma SUN4I_DMA_DEDICATED 26>; @@ -413,11 +185,11 @@ #size-cells = <0>; }; - spi1: spi@01c06000 { + spi1: spi@1c06000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c06000 0x1000>; interrupts = <11>; - clocks = <&ahb_gates 21>, <&spi1_clk>; + clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 9>, <&dma SUN4I_DMA_DEDICATED 8>; @@ -427,61 +199,122 @@ #size-cells = <0>; }; - mmc0: mmc@01c0f000 { + tve0: tv-encoder@1c0a000 { + compatible = "allwinner,sun4i-a10-tv-encoder"; + reg = <0x01c0a000 0x1000>; + clocks = <&ccu CLK_AHB_TVE>; + resets = <&ccu RST_TVE>; + status = "disabled"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + tve0_in_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_tve0>; + }; + }; + }; + + emac: ethernet@1c0b000 { + compatible = "allwinner,sun4i-a10-emac"; + reg = <0x01c0b000 0x1000>; + interrupts = <55>; + clocks = <&ccu CLK_AHB_EMAC>; + allwinner,sram = <&emac_sram 1>; + status = "disabled"; + }; + + mdio: mdio@1c0b080 { + compatible = "allwinner,sun4i-a10-mdio"; + reg = <0x01c0b080 0x14>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + tcon0: lcd-controller@1c0c000 { + compatible = "allwinner,sun5i-a13-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = <44>; + resets = <&ccu RST_LCD>; + reset-names = "lcd"; + clocks = <&ccu CLK_AHB_LCD>, + <&ccu CLK_TCON_CH0>, + <&ccu CLK_TCON_CH1>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1"; + clock-output-names = "tcon-pixel-clock"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon0_in_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon0_out_tve0: endpoint@1 { + reg = <1>; + remote-endpoint = <&tve0_in_tcon0>; + allwinner,tcon-channel = <1>; + }; + }; + }; + }; + + mmc0: mmc@1c0f000 { compatible = "allwinner,sun5i-a13-mmc"; reg = <0x01c0f000 0x1000>; - clocks = <&ahb_gates 8>, - <&mmc0_clk 0>, - <&mmc0_clk 1>, - <&mmc0_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; + clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>; + clock-names = "ahb", "mmc"; interrupts = <32>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - mmc1: mmc@01c10000 { + mmc1: mmc@1c10000 { compatible = "allwinner,sun5i-a13-mmc"; reg = <0x01c10000 0x1000>; - clocks = <&ahb_gates 9>, - <&mmc1_clk 0>, - <&mmc1_clk 1>, - <&mmc1_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; + clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>; + clock-names = "ahb", "mmc"; interrupts = <33>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - mmc2: mmc@01c11000 { + mmc2: mmc@1c11000 { compatible = "allwinner,sun5i-a13-mmc"; reg = <0x01c11000 0x1000>; - clocks = <&ahb_gates 10>, - <&mmc2_clk 0>, - <&mmc2_clk 1>, - <&mmc2_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; + clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>; + clock-names = "ahb", "mmc"; interrupts = <34>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - usb_otg: usb@01c13000 { + usb_otg: usb@1c13000 { compatible = "allwinner,sun4i-a10-musb"; reg = <0x01c13000 0x0400>; - clocks = <&ahb_gates 0>; + clocks = <&ccu CLK_AHB_OTG>; interrupts = <38>; interrupt-names = "mc"; phys = <&usbphy 0>; @@ -491,43 +324,52 @@ status = "disabled"; }; - usbphy: phy@01c13400 { + usbphy: phy@1c13400 { #phy-cells = <1>; compatible = "allwinner,sun5i-a13-usb-phy"; reg = <0x01c13400 0x10 0x01c14800 0x4>; reg-names = "phy_ctrl", "pmu1"; - clocks = <&usb_clk 8>; + clocks = <&ccu CLK_USB_PHY0>; clock-names = "usb_phy"; - resets = <&usb_clk 0>, <&usb_clk 1>; + resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>; reset-names = "usb0_reset", "usb1_reset"; status = "disabled"; }; - ehci0: usb@01c14000 { + ehci0: usb@1c14000 { compatible = "allwinner,sun5i-a13-ehci", "generic-ehci"; reg = <0x01c14000 0x100>; interrupts = <39>; - clocks = <&ahb_gates 1>; + clocks = <&ccu CLK_AHB_EHCI>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; }; - ohci0: usb@01c14400 { + ohci0: usb@1c14400 { compatible = "allwinner,sun5i-a13-ohci", "generic-ohci"; reg = <0x01c14400 0x100>; interrupts = <40>; - clocks = <&usb_clk 6>, <&ahb_gates 2>; + clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; }; - spi2: spi@01c17000 { + crypto: crypto-engine@1c15000 { + compatible = "allwinner,sun5i-a13-crypto", + "allwinner,sun4i-a10-crypto"; + reg = <0x01c15000 0x1000>; + interrupts = <54>; + clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>; + clock-names = "ahb", "mod"; + }; + + spi2: spi@1c17000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c17000 0x1000>; interrupts = <12>; - clocks = <&ahb_gates 22>, <&spi2_clk>; + clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 29>, <&dma SUN4I_DMA_DEDICATED 28>; @@ -537,107 +379,199 @@ #size-cells = <0>; }; - intc: interrupt-controller@01c20400 { + ccu: clock@1c20000 { + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + intc: interrupt-controller@1c20400 { compatible = "allwinner,sun4i-a10-ic"; reg = <0x01c20400 0x400>; interrupt-controller; #interrupt-cells = <1>; }; - pio: pinctrl@01c20800 { + pio: pinctrl@1c20800 { reg = <0x01c20800 0x400>; interrupts = <28>; - clocks = <&apb0_gates 5>; + clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; #interrupt-cells = <3>; #gpio-cells = <3>; + emac_pins_a: emac0@0 { + pins = "PD6", "PD7", "PD10", + "PD11", "PD12", "PD13", "PD14", + "PD15", "PD18", "PD19", "PD20", + "PD21", "PD22", "PD23", "PD24", + "PD25", "PD26", "PD27"; + function = "emac"; + }; + i2c0_pins_a: i2c0@0 { - allwinner,pins = "PB0", "PB1"; - allwinner,function = "i2c0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PB0", "PB1"; + function = "i2c0"; }; i2c1_pins_a: i2c1@0 { - allwinner,pins = "PB15", "PB16"; - allwinner,function = "i2c1"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PB15", "PB16"; + function = "i2c1"; }; i2c2_pins_a: i2c2@0 { - allwinner,pins = "PB17", "PB18"; - allwinner,function = "i2c2"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PB17", "PB18"; + function = "i2c2"; + }; + + ir0_rx_pins_a: ir0@0 { + pins = "PB4"; + function = "ir0"; + }; + + lcd_rgb565_pins: lcd_rgb565@0 { + pins = "PD3", "PD4", "PD5", "PD6", "PD7", + "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", + "PD19", "PD20", "PD21", "PD22", "PD23", + "PD24", "PD25", "PD26", "PD27"; + function = "lcd0"; + }; + + lcd_rgb666_pins: lcd_rgb666@0 { + pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", + "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", + "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", + "PD24", "PD25", "PD26", "PD27"; + function = "lcd0"; }; mmc0_pins_a: mmc0@0 { - allwinner,pins = "PF0", "PF1", "PF2", "PF3", - "PF4", "PF5"; - allwinner,function = "mmc0"; - allwinner,drive = <SUN4I_PINCTRL_30_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PF0", "PF1", "PF2", "PF3", + "PF4", "PF5"; + function = "mmc0"; + drive-strength = <30>; + bias-pull-up; }; mmc2_pins_a: mmc2@0 { - allwinner,pins = "PC6", "PC7", "PC8", "PC9", - "PC10", "PC11", "PC12", "PC13", - "PC14", "PC15"; - allwinner,function = "mmc2"; - allwinner,drive = <SUN4I_PINCTRL_30_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PC6", "PC7", "PC8", "PC9", + "PC10", "PC11", "PC12", "PC13", + "PC14", "PC15"; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc2_4bit_pins_a: mmc2-4bit@0 { + pins = "PC6", "PC7", "PC8", "PC9", + "PC10", "PC11"; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; + }; + + nand_pins_a: nand-base0@0 { + pins = "PC0", "PC1", "PC2", + "PC5", "PC8", "PC9", "PC10", + "PC11", "PC12", "PC13", "PC14", + "PC15"; + function = "nand0"; + }; + + nand_cs0_pins_a: nand-cs@0 { + pins = "PC4"; + function = "nand0"; + }; + + nand_rb0_pins_a: nand-rb@0 { + pins = "PC6"; + function = "nand0"; + }; + + spi2_pins_a: spi2@0 { + pins = "PE1", "PE2", "PE3"; + function = "spi2"; + }; + + spi2_cs0_pins_a: spi2-cs0@0 { + pins = "PE0"; + function = "spi2"; + }; + + uart1_pins_a: uart1@0 { + pins = "PE10", "PE11"; + function = "uart1"; + }; + + uart1_pins_b: uart1@1 { + pins = "PG3", "PG4"; + function = "uart1"; + }; + + uart2_pins_a: uart2@0 { + pins = "PD2", "PD3"; + function = "uart2"; + }; + + uart2_cts_rts_pins_a: uart2-cts-rts@0 { + pins = "PD4", "PD5"; + function = "uart2"; }; uart3_pins_a: uart3@0 { - allwinner,pins = "PG9", "PG10"; - allwinner,function = "uart3"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PG9", "PG10"; + function = "uart3"; }; - uart3_pins_cts_rts_a: uart3-cts-rts@0 { - allwinner,pins = "PG11", "PG12"; - allwinner,function = "uart3"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + uart3_cts_rts_pins_a: uart3-cts-rts@0 { + pins = "PG11", "PG12"; + function = "uart3"; }; pwm0_pins: pwm0 { - allwinner,pins = "PB2"; - allwinner,function = "pwm"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PB2"; + function = "pwm"; }; }; - timer@01c20c00 { + timer@1c20c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0x90>; interrupts = <22>; - clocks = <&osc24M>; + clocks = <&ccu CLK_HOSC>; }; - wdt: watchdog@01c20c90 { + wdt: watchdog@1c20c90 { compatible = "allwinner,sun4i-a10-wdt"; reg = <0x01c20c90 0x10>; }; - lradc: lradc@01c22800 { + ir0: ir@1c21800 { + compatible = "allwinner,sun4i-a10-ir"; + clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>; + clock-names = "apb", "ir"; + interrupts = <5>; + reg = <0x01c21800 0x40>; + status = "disabled"; + }; + + lradc: lradc@1c22800 { compatible = "allwinner,sun4i-a10-lradc-keys"; reg = <0x01c22800 0x100>; interrupts = <31>; status = "disabled"; }; - codec: codec@01c22c00 { + codec: codec@1c22c00 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-codec"; reg = <0x01c22c00 0x40>; interrupts = <30>; - clocks = <&apb0_gates 0>, <&codec_clk>; + clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>; clock-names = "apb", "codec"; dmas = <&dma SUN4I_DMA_NORMAL 19>, <&dma SUN4I_DMA_NORMAL 19>; @@ -645,73 +579,163 @@ status = "disabled"; }; - sid: eeprom@01c23800 { + sid: eeprom@1c23800 { compatible = "allwinner,sun4i-a10-sid"; reg = <0x01c23800 0x10>; }; - rtp: rtp@01c25000 { + rtp: rtp@1c25000 { compatible = "allwinner,sun5i-a13-ts"; reg = <0x01c25000 0x100>; interrupts = <29>; #thermal-sensor-cells = <0>; }; - uart1: serial@01c28400 { + uart0: serial@1c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = <1>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_APB1_UART0>; + status = "disabled"; + }; + + uart1: serial@1c28400 { compatible = "snps,dw-apb-uart"; reg = <0x01c28400 0x400>; interrupts = <2>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 17>; + clocks = <&ccu CLK_APB1_UART1>; status = "disabled"; }; - uart3: serial@01c28c00 { + uart2: serial@1c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = <3>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_APB1_UART2>; + status = "disabled"; + }; + + uart3: serial@1c28c00 { compatible = "snps,dw-apb-uart"; reg = <0x01c28c00 0x400>; interrupts = <4>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 19>; + clocks = <&ccu CLK_APB1_UART3>; status = "disabled"; }; - i2c0: i2c@01c2ac00 { + i2c0: i2c@1c2ac00 { compatible = "allwinner,sun4i-a10-i2c"; reg = <0x01c2ac00 0x400>; interrupts = <7>; - clocks = <&apb1_gates 0>; + clocks = <&ccu CLK_APB1_I2C0>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - i2c1: i2c@01c2b000 { + i2c1: i2c@1c2b000 { compatible = "allwinner,sun4i-a10-i2c"; reg = <0x01c2b000 0x400>; interrupts = <8>; - clocks = <&apb1_gates 1>; + clocks = <&ccu CLK_APB1_I2C1>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - i2c2: i2c@01c2b400 { + i2c2: i2c@1c2b400 { compatible = "allwinner,sun4i-a10-i2c"; reg = <0x01c2b400 0x400>; interrupts = <9>; - clocks = <&apb1_gates 2>; + clocks = <&ccu CLK_APB1_I2C2>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - timer@01c60000 { + timer@1c60000 { compatible = "allwinner,sun5i-a13-hstimer"; reg = <0x01c60000 0x1000>; interrupts = <82>, <83>; - clocks = <&ahb_gates 28>; + clocks = <&ccu CLK_AHB_HSTIMER>; + }; + + fe0: display-frontend@1e00000 { + compatible = "allwinner,sun5i-a13-display-frontend"; + reg = <0x01e00000 0x20000>; + interrupts = <47>; + clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>, + <&ccu CLK_DRAM_DE_FE>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_FE>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe0_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe0>; + }; + }; + }; + }; + + be0: display-backend@1e60000 { + compatible = "allwinner,sun5i-a13-display-backend"; + reg = <0x01e60000 0x10000>; + interrupts = <47>; + clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>, + <&ccu CLK_DRAM_DE_BE>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_BE>; + status = "disabled"; + + assigned-clocks = <&ccu CLK_DE_BE>; + assigned-clock-rates = <300000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be0_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be0>; + }; + }; + + be0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_be0>; + }; + }; + }; }; }; }; diff --git a/arch/arm/dts/sun6i-a31-app4-evb1.dts b/arch/arm/dts/sun6i-a31-app4-evb1.dts index 2f8cfab771..7f34323a66 100644 --- a/arch/arm/dts/sun6i-a31-app4-evb1.dts +++ b/arch/arm/dts/sun6i-a31-app4-evb1.dts @@ -47,7 +47,6 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Allwinner A31 APP4 EVB1 Evaluation Board"; @@ -68,10 +67,8 @@ &pio { usb1_vbus_pin_a: usb1_vbus_pin@0 { - allwinner,pins = "PH27"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH27"; + function = "gpio_out"; }; }; diff --git a/arch/arm/dts/sun6i-a31-colombus.dts b/arch/arm/dts/sun6i-a31-colombus.dts index f9cf36888d..939c497a6f 100644 --- a/arch/arm/dts/sun6i-a31-colombus.dts +++ b/arch/arm/dts/sun6i-a31-colombus.dts @@ -47,7 +47,6 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "WITS A31 Colombus Evaluation Board"; @@ -118,35 +117,30 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_colombus>; vmmc-supply = <®_vcc3v0>; bus-width = <4>; - cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ - cd-inverted; + cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ status = "okay"; }; &mmc0_pins_a { - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + bias-pull-up; }; &pio { mmc0_cd_pin_colombus: mmc0_cd_pin@0 { - allwinner,pins = "PA8"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PA8"; + function = "gpio_in"; + bias-pull-up; }; usb2_vbus_pin_colombus: usb2_vbus_pin@0 { - allwinner,pins = "PH24"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH24"; + function = "gpio_out"; }; i2c_lcd_pins: i2c_lcd_pin@0 { - allwinner,pins = "PA23", "PA24"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PA23", "PA24"; + function = "gpio_out"; + bias-pull-up; }; }; diff --git a/arch/arm/dts/sun6i-a31-hummingbird.dts b/arch/arm/dts/sun6i-a31-hummingbird.dts index 9a74637f67..ce4f9e9834 100644 --- a/arch/arm/dts/sun6i-a31-hummingbird.dts +++ b/arch/arm/dts/sun6i-a31-hummingbird.dts @@ -47,7 +47,6 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Merrii A31 Hummingbird"; @@ -63,16 +62,98 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + vga-connector { + compatible = "vga-connector"; + + port { + vga_con_in: endpoint { + remote-endpoint = <&vga_dac_out>; + }; + }; + }; + + vga-dac { + compatible = "dumb-vga-dac"; + vdd-supply = <®_vga_3v3>; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + vga_dac_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_vga>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + vga_dac_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&vga_con_in>; + }; + }; + }; + }; + + reg_vga_3v3: vga_3v3_regulator { + compatible = "regulator-fixed"; + regulator-name = "vga-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpio = <&pio 7 25 GPIO_ACTIVE_HIGH>; /* PH25 */ + }; + wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 */ }; }; +&codec { + allwinner,audio-routing = + "Headphone", "HP", + "Speaker", "LINEOUT", + "LINEIN", "Line In", + "MIC1", "Mic", + "MIC2", "Headset Mic", + "Mic", "MBIAS", + "Headset Mic", "HBIAS"; + allwinner,pa-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ + status = "okay"; +}; + &cpu0 { cpu-supply = <®_dcdc3>; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -92,6 +173,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; @@ -127,14 +218,13 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_hummingbird>; vmmc-supply = <®_dcdc1>; bus-width = <4>; - cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ - cd-inverted; + cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ status = "okay"; }; &mmc0_pins_a { /* external pull-ups missing for some pins */ - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + bias-pull-up; }; &mmc1 { @@ -153,24 +243,19 @@ &pio { gmac_phy_reset_pin_hummingbird: gmac_phy_reset_pin@0 { - allwinner,pins = "PA21"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PA21"; + function = "gpio_out"; }; mmc0_cd_pin_hummingbird: mmc0_cd_pin@0 { - allwinner,pins = "PA8"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PA8"; + function = "gpio_in"; + bias-pull-up; }; wifi_reset_pin_hummingbird: wifi_reset_pin@0 { - allwinner,pins = "PG10"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PG10"; + function = "gpio_out"; }; }; @@ -182,11 +267,16 @@ reg = <0x68>; interrupt-parent = <&nmi_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + x-powers,drive-vbus-en; }; }; #include "axp22x.dtsi" +&ac_power_supply { + status = "okay"; +}; + ®_aldo1 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -240,23 +330,48 @@ regulator-name = "vcc-dram"; }; +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + ®_usb1_vbus { gpio = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */ status = "okay"; }; +&tcon0 { + pinctrl-names = "default"; + pinctrl-0 = <&lcd0_rgb888_pins>; +}; + +&tcon0_out { + tcon0_out_vga: endpoint@0 { + reg = <0>; + remote-endpoint = <&vga_dac_in>; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; status = "okay"; }; -&usb1_vbus_pin_a { - /* different pin from sunxi-common-regulators */ - allwinner,pins = "PH24"; +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; }; &usbphy { + usb0_id_det-gpio = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ + usb0_vbus_det-gpio = <&pio 0 16 GPIO_ACTIVE_HIGH>; /* PA16 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_drivevbus>; usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; }; diff --git a/arch/arm/dts/sun6i-a31-i7.dts b/arch/arm/dts/sun6i-a31-i7.dts index e9185dad67..d659be9dbc 100644 --- a/arch/arm/dts/sun6i-a31-i7.dts +++ b/arch/arm/dts/sun6i-a31-i7.dts @@ -45,7 +45,6 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Mele I7 Quad top set box"; @@ -59,6 +58,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -69,6 +79,33 @@ gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; }; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "On-board SPDIF"; + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; +}; + +&codec { + allwinner,audio-routing = + "Headphone", "HP"; + status = "okay"; +}; + +&de { + status = "okay"; }; &ehci0 { @@ -91,6 +128,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; @@ -102,31 +149,25 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_i7>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ - cd-inverted; + cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */ status = "okay"; }; &pio { led_pins_i7: led_pins@0 { - allwinner,pins = "PH13"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH13"; + function = "gpio_out"; }; mmc0_cd_pin_i7: mmc0_cd_pin@0 { - allwinner,pins = "PH22"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PH22"; + function = "gpio_in"; + bias-pull-up; }; usb1_vbus_pin_i7: usb1_vbus_pin@0 { - allwinner,pins = "PC27"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PC27"; + function = "gpio_out"; }; }; @@ -137,6 +178,17 @@ status = "okay"; }; +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&spdif_pins_a>; + spdif-out = "okay"; + status = "okay"; +}; + +&tcon0 { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; diff --git a/arch/arm/dts/sun6i-a31-m9.dts b/arch/arm/dts/sun6i-a31-m9.dts index 29016a13a2..9698f6d38d 100644 --- a/arch/arm/dts/sun6i-a31-m9.dts +++ b/arch/arm/dts/sun6i-a31-m9.dts @@ -45,7 +45,6 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Mele M9 top set box"; @@ -108,8 +107,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>; vmmc-supply = <®_dcdc1>; bus-width = <4>; - cd-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ - cd-inverted; + cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */ status = "okay"; }; @@ -128,24 +126,19 @@ &pio { led_pins_m9: led_pins@0 { - allwinner,pins = "PH13"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH13"; + function = "gpio_out"; }; mmc0_cd_pin_m9: mmc0_cd_pin@0 { - allwinner,pins = "PH22"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PH22"; + function = "gpio_in"; + bias-pull-up; }; usb1_vbus_pin_m9: usb1_vbus_pin@0 { - allwinner,pins = "PC27"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PC27"; + function = "gpio_out"; }; }; diff --git a/arch/arm/dts/sun6i-a31-mele-a1000g-quad.dts b/arch/arm/dts/sun6i-a31-mele-a1000g-quad.dts index 5faeae429e..bb14b171b1 100644 --- a/arch/arm/dts/sun6i-a31-mele-a1000g-quad.dts +++ b/arch/arm/dts/sun6i-a31-mele-a1000g-quad.dts @@ -45,7 +45,6 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Mele A1000G Quad top set box"; @@ -108,8 +107,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>; vmmc-supply = <®_dcdc1>; bus-width = <4>; - cd-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ - cd-inverted; + cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */ status = "okay"; }; @@ -128,24 +126,19 @@ &pio { led_pins_m9: led_pins@0 { - allwinner,pins = "PH13"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH13"; + function = "gpio_out"; }; mmc0_cd_pin_m9: mmc0_cd_pin@0 { - allwinner,pins = "PH22"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PH22"; + function = "gpio_in"; + bias-pull-up; }; usb1_vbus_pin_m9: usb1_vbus_pin@0 { - allwinner,pins = "PC27"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PC27"; + function = "gpio_out"; }; }; diff --git a/arch/arm/dts/sun6i-a31.dtsi b/arch/arm/dts/sun6i-a31.dtsi index b674bf79bc..c72992556a 100644 --- a/arch/arm/dts/sun6i-a31.dtsi +++ b/arch/arm/dts/sun6i-a31.dtsi @@ -47,7 +47,8 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/thermal/thermal.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> +#include <dt-bindings/clock/sun6i-a31-ccu.h> +#include <dt-bindings/reset/sun6i-a31-ccu.h> / { interrupt-parent = <&gic>; @@ -65,7 +66,10 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&pll6 0>; + clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>, + <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>, + <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>, + <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>; status = "disabled"; }; @@ -73,7 +77,9 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0"; - clocks = <&pll6 0>; + clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>, + <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>, + <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>; status = "disabled"; }; }; @@ -97,7 +103,7 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; - clocks = <&cpu>; + clocks = <&ccu CLK_CPU>; clock-latency = <244144>; /* 8 32k periods */ operating-points = < /* kHz uV */ @@ -107,8 +113,6 @@ 480000 1000000 >; #cooling-cells = <2>; - cooling-min-level = <0>; - cooling-max-level = <3>; }; cpu@1 { @@ -192,235 +196,6 @@ clock-output-names = "osc32k"; }; - pll1: clk@01c20000 { - #clock-cells = <0>; - compatible = "allwinner,sun6i-a31-pll1-clk"; - reg = <0x01c20000 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll1"; - }; - - pll6: clk@01c20028 { - #clock-cells = <1>; - compatible = "allwinner,sun6i-a31-pll6-clk"; - reg = <0x01c20028 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll6", "pll6x2"; - }; - - cpu: cpu@01c20050 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-cpu-clk"; - reg = <0x01c20050 0x4>; - - /* - * PLL1 is listed twice here. - * While it looks suspicious, it's actually documented - * that way both in the datasheet and in the code from - * Allwinner. - */ - clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; - clock-output-names = "cpu"; - }; - - axi: axi@01c20050 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-axi-clk"; - reg = <0x01c20050 0x4>; - clocks = <&cpu>; - clock-output-names = "axi"; - }; - - ahb1: ahb1@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun6i-a31-ahb1-clk"; - reg = <0x01c20054 0x4>; - clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; - clock-output-names = "ahb1"; - - /* - * Clock AHB1 from PLL6, instead of CPU/AXI which - * has rate changes due to cpufreq. Also the DMA - * controller requires AHB1 clocked from PLL6. - */ - assigned-clocks = <&ahb1>; - assigned-clock-parents = <&pll6 0>; - }; - - ahb1_gates: clk@01c20060 { - #clock-cells = <1>; - compatible = "allwinner,sun6i-a31-ahb1-gates-clk"; - reg = <0x01c20060 0x8>; - clocks = <&ahb1>; - clock-indices = <1>, <5>, - <6>, <8>, <9>, - <10>, <11>, <12>, - <13>, <14>, - <17>, <18>, <19>, - <20>, <21>, <22>, - <23>, <24>, <26>, - <27>, <29>, - <30>, <31>, <32>, - <36>, <37>, <40>, - <43>, <44>, <45>, - <46>, <47>, <50>, - <52>, <55>, <56>, - <57>, <58>; - clock-output-names = "ahb1_mipidsi", "ahb1_ss", - "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1", - "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1", - "ahb1_nand0", "ahb1_sdram", - "ahb1_gmac", "ahb1_ts", "ahb1_hstimer", - "ahb1_spi0", "ahb1_spi1", "ahb1_spi2", - "ahb1_spi3", "ahb1_otg", "ahb1_ehci0", - "ahb1_ehci1", "ahb1_ohci0", - "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve", - "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi", - "ahb1_hdmi", "ahb1_de0", "ahb1_de1", - "ahb1_fe0", "ahb1_fe1", "ahb1_mp", - "ahb1_gpu", "ahb1_deu0", "ahb1_deu1", - "ahb1_drc0", "ahb1_drc1"; - }; - - apb1: apb1@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb0-clk"; - reg = <0x01c20054 0x4>; - clocks = <&ahb1>; - clock-output-names = "apb1"; - }; - - apb1_gates: clk@01c20068 { - #clock-cells = <1>; - compatible = "allwinner,sun6i-a31-apb1-gates-clk"; - reg = <0x01c20068 0x4>; - clocks = <&apb1>; - clock-indices = <0>, <4>, - <5>, <12>, - <13>; - clock-output-names = "apb1_codec", "apb1_digital_mic", - "apb1_pio", "apb1_daudio0", - "apb1_daudio1"; - }; - - apb2: clk@01c20058 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb1-clk"; - reg = <0x01c20058 0x4>; - clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; - clock-output-names = "apb2"; - }; - - apb2_gates: clk@01c2006c { - #clock-cells = <1>; - compatible = "allwinner,sun6i-a31-apb2-gates-clk"; - reg = <0x01c2006c 0x4>; - clocks = <&apb2>; - clock-indices = <0>, <1>, - <2>, <3>, <16>, - <17>, <18>, <19>, - <20>, <21>; - clock-output-names = "apb2_i2c0", "apb2_i2c1", - "apb2_i2c2", "apb2_i2c3", - "apb2_uart0", "apb2_uart1", - "apb2_uart2", "apb2_uart3", - "apb2_uart4", "apb2_uart5"; - }; - - mmc0_clk: clk@01c20088 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20088 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "mmc0", - "mmc0_output", - "mmc0_sample"; - }; - - mmc1_clk: clk@01c2008c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c2008c 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "mmc1", - "mmc1_output", - "mmc1_sample"; - }; - - mmc2_clk: clk@01c20090 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20090 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "mmc2", - "mmc2_output", - "mmc2_sample"; - }; - - mmc3_clk: clk@01c20094 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20094 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "mmc3", - "mmc3_output", - "mmc3_sample"; - }; - - ss_clk: clk@01c2009c { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c2009c 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "ss"; - }; - - spi0_clk: clk@01c200a0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a0 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "spi0"; - }; - - spi1_clk: clk@01c200a4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a4 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "spi1"; - }; - - spi2_clk: clk@01c200a8 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a8 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "spi2"; - }; - - spi3_clk: clk@01c200ac { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200ac 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "spi3"; - }; - - usb_clk: clk@01c200cc { - #clock-cells = <1>; - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-usb-clk"; - reg = <0x01c200cc 0x4>; - clocks = <&osc24M>; - clock-indices = <8>, <9>, <10>, - <16>, <17>, - <18>; - clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2", - "usb_ohci0", "usb_ohci1", - "usb_ohci2"; - }; - /* * The following two are dummy clocks, placeholders * used in the gmac_tx clock. The gmac driver will @@ -444,7 +219,7 @@ clock-output-names = "gmac_int_tx"; }; - gmac_tx_clk: clk@01c200d0 { + gmac_tx_clk: clk@1c200d0 { #clock-cells = <0>; compatible = "allwinner,sun7i-a20-gmac-clk"; reg = <0x01c200d0 0x4>; @@ -453,34 +228,135 @@ }; }; - soc@01c00000 { + de: display-engine { + compatible = "allwinner,sun6i-a31-display-engine"; + allwinner,pipelines = <&fe0>, <&fe1>; + status = "disabled"; + }; + + soc@1c00000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; - dma: dma-controller@01c02000 { + dma: dma-controller@1c02000 { compatible = "allwinner,sun6i-a31-dma"; reg = <0x01c02000 0x1000>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 6>; - resets = <&ahb1_rst 6>; + clocks = <&ccu CLK_AHB1_DMA>; + resets = <&ccu RST_AHB1_DMA>; #dma-cells = <1>; }; - mmc0: mmc@01c0f000 { - compatible = "allwinner,sun7i-a20-mmc", - "allwinner,sun5i-a13-mmc"; + tcon0: lcd-controller@1c0c000 { + compatible = "allwinner,sun6i-a31-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + resets = <&ccu RST_AHB1_LCD0>; + reset-names = "lcd"; + clocks = <&ccu CLK_AHB1_LCD0>, + <&ccu CLK_LCD0_CH0>, + <&ccu CLK_LCD0_CH1>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1"; + clock-output-names = "tcon0-pixel-clock"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon0_in_drc0: endpoint@0 { + reg = <0>; + remote-endpoint = <&drc0_out_tcon0>; + }; + + tcon0_in_drc1: endpoint@1 { + reg = <1>; + remote-endpoint = <&drc1_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon0_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_tcon0>; + allwinner,tcon-channel = <1>; + }; + }; + }; + }; + + tcon1: lcd-controller@1c0d000 { + compatible = "allwinner,sun6i-a31-tcon"; + reg = <0x01c0d000 0x1000>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + resets = <&ccu RST_AHB1_LCD1>; + reset-names = "lcd"; + clocks = <&ccu CLK_AHB1_LCD1>, + <&ccu CLK_LCD1_CH0>, + <&ccu CLK_LCD1_CH1>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1"; + clock-output-names = "tcon1-pixel-clock"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon1_in_drc0: endpoint@0 { + reg = <0>; + remote-endpoint = <&drc0_out_tcon1>; + }; + + tcon1_in_drc1: endpoint@1 { + reg = <1>; + remote-endpoint = <&drc1_out_tcon1>; + }; + }; + + tcon1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon1_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_tcon1>; + allwinner,tcon-channel = <1>; + }; + }; + }; + }; + + mmc0: mmc@1c0f000 { + compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; - clocks = <&ahb1_gates 8>, - <&mmc0_clk 0>, - <&mmc0_clk 1>, - <&mmc0_clk 2>; + clocks = <&ccu CLK_AHB1_MMC0>, + <&ccu CLK_MMC0>, + <&ccu CLK_MMC0_OUTPUT>, + <&ccu CLK_MMC0_SAMPLE>; clock-names = "ahb", "mmc", "output", "sample"; - resets = <&ahb1_rst 8>; + resets = <&ccu RST_AHB1_MMC0>; reset-names = "ahb"; interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -488,19 +364,18 @@ #size-cells = <0>; }; - mmc1: mmc@01c10000 { - compatible = "allwinner,sun7i-a20-mmc", - "allwinner,sun5i-a13-mmc"; + mmc1: mmc@1c10000 { + compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c10000 0x1000>; - clocks = <&ahb1_gates 9>, - <&mmc1_clk 0>, - <&mmc1_clk 1>, - <&mmc1_clk 2>; + clocks = <&ccu CLK_AHB1_MMC1>, + <&ccu CLK_MMC1>, + <&ccu CLK_MMC1_OUTPUT>, + <&ccu CLK_MMC1_SAMPLE>; clock-names = "ahb", "mmc", "output", "sample"; - resets = <&ahb1_rst 9>; + resets = <&ccu RST_AHB1_MMC1>; reset-names = "ahb"; interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -508,19 +383,18 @@ #size-cells = <0>; }; - mmc2: mmc@01c11000 { - compatible = "allwinner,sun7i-a20-mmc", - "allwinner,sun5i-a13-mmc"; + mmc2: mmc@1c11000 { + compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c11000 0x1000>; - clocks = <&ahb1_gates 10>, - <&mmc2_clk 0>, - <&mmc2_clk 1>, - <&mmc2_clk 2>; + clocks = <&ccu CLK_AHB1_MMC2>, + <&ccu CLK_MMC2>, + <&ccu CLK_MMC2_OUTPUT>, + <&ccu CLK_MMC2_SAMPLE>; clock-names = "ahb", "mmc", "output", "sample"; - resets = <&ahb1_rst 10>; + resets = <&ccu RST_AHB1_MMC2>; reset-names = "ahb"; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -528,19 +402,18 @@ #size-cells = <0>; }; - mmc3: mmc@01c12000 { - compatible = "allwinner,sun7i-a20-mmc", - "allwinner,sun5i-a13-mmc"; + mmc3: mmc@1c12000 { + compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c12000 0x1000>; - clocks = <&ahb1_gates 11>, - <&mmc3_clk 0>, - <&mmc3_clk 1>, - <&mmc3_clk 2>; + clocks = <&ccu CLK_AHB1_MMC3>, + <&ccu CLK_MMC3>, + <&ccu CLK_MMC3_OUTPUT>, + <&ccu CLK_MMC3_SAMPLE>; clock-names = "ahb", "mmc", "output", "sample"; - resets = <&ahb1_rst 11>; + resets = <&ccu RST_AHB1_MMC3>; reset-names = "ahb"; interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -548,11 +421,54 @@ #size-cells = <0>; }; - usb_otg: usb@01c19000 { + hdmi: hdmi@1c16000 { + compatible = "allwinner,sun6i-a31-hdmi"; + reg = <0x01c16000 0x1000>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>, + <&ccu CLK_HDMI_DDC>, + <&ccu CLK_PLL_VIDEO0_2X>, + <&ccu CLK_PLL_VIDEO1_2X>; + clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1"; + resets = <&ccu RST_AHB1_HDMI>; + reset-names = "ahb"; + dma-names = "ddc-tx", "ddc-rx", "audio-tx"; + dmas = <&dma 13>, <&dma 13>, <&dma 14>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + hdmi_in_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_hdmi>; + }; + + hdmi_in_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + + usb_otg: usb@1c19000 { compatible = "allwinner,sun6i-a31-musb"; reg = <0x01c19000 0x0400>; - clocks = <&ahb1_gates 24>; - resets = <&ahb1_rst 24>; + clocks = <&ccu CLK_AHB1_OTG>; + resets = <&ccu RST_AHB1_OTG>; interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "mc"; phys = <&usbphy 0>; @@ -561,7 +477,7 @@ status = "disabled"; }; - usbphy: phy@01c19400 { + usbphy: phy@1c19400 { compatible = "allwinner,sun6i-a31-usb-phy"; reg = <0x01c19400 0x10>, <0x01c1a800 0x4>, @@ -569,15 +485,15 @@ reg-names = "phy_ctrl", "pmu1", "pmu2"; - clocks = <&usb_clk 8>, - <&usb_clk 9>, - <&usb_clk 10>; + clocks = <&ccu CLK_USB_PHY0>, + <&ccu CLK_USB_PHY1>, + <&ccu CLK_USB_PHY2>; clock-names = "usb0_phy", "usb1_phy", "usb2_phy"; - resets = <&usb_clk 0>, - <&usb_clk 1>, - <&usb_clk 2>; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>, + <&ccu RST_USB_PHY2>; reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; @@ -585,206 +501,202 @@ #phy-cells = <1>; }; - ehci0: usb@01c1a000 { + ehci0: usb@1c1a000 { compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; reg = <0x01c1a000 0x100>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 26>; - resets = <&ahb1_rst 26>; + clocks = <&ccu CLK_AHB1_EHCI0>; + resets = <&ccu RST_AHB1_EHCI0>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; }; - ohci0: usb@01c1a400 { + ohci0: usb@1c1a400 { compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; reg = <0x01c1a400 0x100>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 29>, <&usb_clk 16>; - resets = <&ahb1_rst 29>; + clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_AHB1_OHCI0>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; }; - ehci1: usb@01c1b000 { + ehci1: usb@1c1b000 { compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; reg = <0x01c1b000 0x100>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 27>; - resets = <&ahb1_rst 27>; + clocks = <&ccu CLK_AHB1_EHCI1>; + resets = <&ccu RST_AHB1_EHCI1>; phys = <&usbphy 2>; phy-names = "usb"; status = "disabled"; }; - ohci1: usb@01c1b400 { + ohci1: usb@1c1b400 { compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; reg = <0x01c1b400 0x100>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 30>, <&usb_clk 17>; - resets = <&ahb1_rst 30>; + clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>; + resets = <&ccu RST_AHB1_OHCI1>; phys = <&usbphy 2>; phy-names = "usb"; status = "disabled"; }; - ohci2: usb@01c1c400 { + ohci2: usb@1c1c400 { compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; reg = <0x01c1c400 0x100>; interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 31>, <&usb_clk 18>; - resets = <&ahb1_rst 31>; + clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>; + resets = <&ccu RST_AHB1_OHCI2>; status = "disabled"; }; - pio: pinctrl@01c20800 { + ccu: clock@1c20000 { + compatible = "allwinner,sun6i-a31-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pio: pinctrl@1c20800 { compatible = "allwinner,sun6i-a31-pinctrl"; reg = <0x01c20800 0x400>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb1_gates 5>; + clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; #interrupt-cells = <3>; #gpio-cells = <3>; - uart0_pins_a: uart0@0 { - allwinner,pins = "PH20", "PH21"; - allwinner,function = "uart0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + gmac_pins_gmii_a: gmac_gmii@0 { + pins = "PA0", "PA1", "PA2", "PA3", + "PA4", "PA5", "PA6", "PA7", + "PA8", "PA9", "PA10", "PA11", + "PA12", "PA13", "PA14", "PA15", + "PA16", "PA17", "PA18", "PA19", + "PA20", "PA21", "PA22", "PA23", + "PA24", "PA25", "PA26", "PA27"; + function = "gmac"; + /* + * data lines in GMII mode run at 125MHz and + * might need a higher signal drive strength + */ + drive-strength = <30>; + }; + + gmac_pins_mii_a: gmac_mii@0 { + pins = "PA0", "PA1", "PA2", "PA3", + "PA8", "PA9", "PA11", + "PA12", "PA13", "PA14", "PA19", + "PA20", "PA21", "PA22", "PA23", + "PA24", "PA26", "PA27"; + function = "gmac"; + }; + + gmac_pins_rgmii_a: gmac_rgmii@0 { + pins = "PA0", "PA1", "PA2", "PA3", + "PA9", "PA10", "PA11", + "PA12", "PA13", "PA14", "PA19", + "PA20", "PA25", "PA26", "PA27"; + function = "gmac"; + /* + * data lines in RGMII mode use DDR mode + * and need a higher signal drive strength + */ + drive-strength = <40>; }; i2c0_pins_a: i2c0@0 { - allwinner,pins = "PH14", "PH15"; - allwinner,function = "i2c0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH14", "PH15"; + function = "i2c0"; }; i2c1_pins_a: i2c1@0 { - allwinner,pins = "PH16", "PH17"; - allwinner,function = "i2c1"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH16", "PH17"; + function = "i2c1"; }; i2c2_pins_a: i2c2@0 { - allwinner,pins = "PH18", "PH19"; - allwinner,function = "i2c2"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH18", "PH19"; + function = "i2c2"; + }; + + lcd0_rgb888_pins: lcd0_rgb888 { + pins = "PD0", "PD1", "PD2", "PD3", + "PD4", "PD5", "PD6", "PD7", + "PD8", "PD9", "PD10", "PD11", + "PD12", "PD13", "PD14", "PD15", + "PD16", "PD17", "PD18", "PD19", + "PD20", "PD21", "PD22", "PD23", + "PD24", "PD25", "PD26", "PD27"; + function = "lcd0"; }; mmc0_pins_a: mmc0@0 { - allwinner,pins = "PF0", "PF1", "PF2", + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; - allwinner,function = "mmc0"; - allwinner,drive = <SUN4I_PINCTRL_30_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + function = "mmc0"; + drive-strength = <30>; + bias-pull-up; }; mmc1_pins_a: mmc1@0 { - allwinner,pins = "PG0", "PG1", "PG2", "PG3", + pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; - allwinner,function = "mmc1"; - allwinner,drive = <SUN4I_PINCTRL_30_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + function = "mmc1"; + drive-strength = <30>; + bias-pull-up; }; mmc2_pins_a: mmc2@0 { - allwinner,pins = "PC6", "PC7", "PC8", "PC9", + pins = "PC6", "PC7", "PC8", "PC9", "PC10", "PC11"; - allwinner,function = "mmc2"; - allwinner,drive = <SUN4I_PINCTRL_30_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; }; mmc2_8bit_emmc_pins: mmc2@1 { - allwinner,pins = "PC6", "PC7", "PC8", "PC9", + pins = "PC6", "PC7", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", "PC15", "PC24"; - allwinner,function = "mmc2"; - allwinner,drive = <SUN4I_PINCTRL_30_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; }; mmc3_8bit_emmc_pins: mmc3@1 { - allwinner,pins = "PC6", "PC7", "PC8", "PC9", + pins = "PC6", "PC7", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", "PC15", "PC24"; - allwinner,function = "mmc3"; - allwinner,drive = <SUN4I_PINCTRL_40_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + function = "mmc3"; + drive-strength = <40>; + bias-pull-up; }; - gmac_pins_mii_a: gmac_mii@0 { - allwinner,pins = "PA0", "PA1", "PA2", "PA3", - "PA8", "PA9", "PA11", - "PA12", "PA13", "PA14", "PA19", - "PA20", "PA21", "PA22", "PA23", - "PA24", "PA26", "PA27"; - allwinner,function = "gmac"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - gmac_pins_gmii_a: gmac_gmii@0 { - allwinner,pins = "PA0", "PA1", "PA2", "PA3", - "PA4", "PA5", "PA6", "PA7", - "PA8", "PA9", "PA10", "PA11", - "PA12", "PA13", "PA14", "PA15", - "PA16", "PA17", "PA18", "PA19", - "PA20", "PA21", "PA22", "PA23", - "PA24", "PA25", "PA26", "PA27"; - allwinner,function = "gmac"; - /* - * data lines in GMII mode run at 125MHz and - * might need a higher signal drive strength - */ - allwinner,drive = <SUN4I_PINCTRL_30_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + spdif_pins_a: spdif@0 { + pins = "PH28"; + function = "spdif"; }; - gmac_pins_rgmii_a: gmac_rgmii@0 { - allwinner,pins = "PA0", "PA1", "PA2", "PA3", - "PA9", "PA10", "PA11", - "PA12", "PA13", "PA14", "PA19", - "PA20", "PA25", "PA26", "PA27"; - allwinner,function = "gmac"; - /* - * data lines in RGMII mode use DDR mode - * and need a higher signal drive strength - */ - allwinner,drive = <SUN4I_PINCTRL_40_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + uart0_pins_a: uart0@0 { + pins = "PH20", "PH21"; + function = "uart0"; }; }; - ahb1_rst: reset@01c202c0 { - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-ahb1-reset"; - reg = <0x01c202c0 0xc>; - }; - - apb1_rst: reset@01c202d0 { - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-clock-reset"; - reg = <0x01c202d0 0x4>; - }; - - apb2_rst: reset@01c202d8 { - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-clock-reset"; - reg = <0x01c202d8 0x4>; - }; - - timer@01c20c00 { + timer@1c20c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0xa0>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, @@ -795,155 +707,194 @@ clocks = <&osc24M>; }; - wdt1: watchdog@01c20ca0 { + wdt1: watchdog@1c20ca0 { compatible = "allwinner,sun6i-a31-wdt"; reg = <0x01c20ca0 0x20>; }; - lradc: lradc@01c22800 { + spdif: spdif@1c21000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun6i-a31-spdif"; + reg = <0x01c21000 0x400>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_APB1_SPDIF>, <&ccu CLK_SPDIF>; + resets = <&ccu RST_APB1_SPDIF>; + clock-names = "apb", "spdif"; + dmas = <&dma 2>, <&dma 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2s0: i2s@1c22000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun6i-a31-i2s"; + reg = <0x01c22000 0x400>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_APB1_DAUDIO0>, <&ccu CLK_DAUDIO0>; + resets = <&ccu RST_APB1_DAUDIO0>; + clock-names = "apb", "mod"; + dmas = <&dma 3>, <&dma 3>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2s1: i2s@1c22400 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun6i-a31-i2s"; + reg = <0x01c22400 0x400>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_APB1_DAUDIO1>, <&ccu CLK_DAUDIO1>; + resets = <&ccu RST_APB1_DAUDIO1>; + clock-names = "apb", "mod"; + dmas = <&dma 4>, <&dma 4>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lradc: lradc@1c22800 { compatible = "allwinner,sun4i-a10-lradc-keys"; reg = <0x01c22800 0x100>; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; - rtp: rtp@01c25000 { + rtp: rtp@1c25000 { compatible = "allwinner,sun6i-a31-ts"; reg = <0x01c25000 0x100>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; #thermal-sensor-cells = <0>; }; - uart0: serial@01c28000 { + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb2_gates 16>; - resets = <&apb2_rst 16>; + clocks = <&ccu CLK_APB2_UART0>; + resets = <&ccu RST_APB2_UART0>; dmas = <&dma 6>, <&dma 6>; dma-names = "rx", "tx"; status = "disabled"; }; - uart1: serial@01c28400 { + uart1: serial@1c28400 { compatible = "snps,dw-apb-uart"; reg = <0x01c28400 0x400>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb2_gates 17>; - resets = <&apb2_rst 17>; + clocks = <&ccu CLK_APB2_UART1>; + resets = <&ccu RST_APB2_UART1>; dmas = <&dma 7>, <&dma 7>; dma-names = "rx", "tx"; status = "disabled"; }; - uart2: serial@01c28800 { + uart2: serial@1c28800 { compatible = "snps,dw-apb-uart"; reg = <0x01c28800 0x400>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb2_gates 18>; - resets = <&apb2_rst 18>; + clocks = <&ccu CLK_APB2_UART2>; + resets = <&ccu RST_APB2_UART2>; dmas = <&dma 8>, <&dma 8>; dma-names = "rx", "tx"; status = "disabled"; }; - uart3: serial@01c28c00 { + uart3: serial@1c28c00 { compatible = "snps,dw-apb-uart"; reg = <0x01c28c00 0x400>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb2_gates 19>; - resets = <&apb2_rst 19>; + clocks = <&ccu CLK_APB2_UART3>; + resets = <&ccu RST_APB2_UART3>; dmas = <&dma 9>, <&dma 9>; dma-names = "rx", "tx"; status = "disabled"; }; - uart4: serial@01c29000 { + uart4: serial@1c29000 { compatible = "snps,dw-apb-uart"; reg = <0x01c29000 0x400>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb2_gates 20>; - resets = <&apb2_rst 20>; + clocks = <&ccu CLK_APB2_UART4>; + resets = <&ccu RST_APB2_UART4>; dmas = <&dma 10>, <&dma 10>; dma-names = "rx", "tx"; status = "disabled"; }; - uart5: serial@01c29400 { + uart5: serial@1c29400 { compatible = "snps,dw-apb-uart"; reg = <0x01c29400 0x400>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb2_gates 21>; - resets = <&apb2_rst 21>; + clocks = <&ccu CLK_APB2_UART5>; + resets = <&ccu RST_APB2_UART5>; dmas = <&dma 22>, <&dma 22>; dma-names = "rx", "tx"; status = "disabled"; }; - i2c0: i2c@01c2ac00 { + i2c0: i2c@1c2ac00 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2ac00 0x400>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb2_gates 0>; - resets = <&apb2_rst 0>; + clocks = <&ccu CLK_APB2_I2C0>; + resets = <&ccu RST_APB2_I2C0>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - i2c1: i2c@01c2b000 { + i2c1: i2c@1c2b000 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b000 0x400>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb2_gates 1>; - resets = <&apb2_rst 1>; + clocks = <&ccu CLK_APB2_I2C1>; + resets = <&ccu RST_APB2_I2C1>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - i2c2: i2c@01c2b400 { + i2c2: i2c@1c2b400 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b400 0x400>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb2_gates 2>; - resets = <&apb2_rst 2>; + clocks = <&ccu CLK_APB2_I2C2>; + resets = <&ccu RST_APB2_I2C2>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - i2c3: i2c@01c2b800 { + i2c3: i2c@1c2b800 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b800 0x400>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb2_gates 3>; - resets = <&apb2_rst 3>; + clocks = <&ccu CLK_APB2_I2C3>; + resets = <&ccu RST_APB2_I2C3>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - gmac: ethernet@01c30000 { + gmac: ethernet@1c30000 { compatible = "allwinner,sun7i-a20-gmac"; reg = <0x01c30000 0x1054>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; - clocks = <&ahb1_gates 17>, <&gmac_tx_clk>; + clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>; clock-names = "stmmaceth", "allwinner_gmac_tx"; - resets = <&ahb1_rst 17>; + resets = <&ccu RST_AHB1_EMAC>; reset-names = "stmmaceth"; snps,pbl = <2>; snps,fixed-burst; @@ -953,17 +904,31 @@ #size-cells = <0>; }; - crypto: crypto-engine@01c15000 { - compatible = "allwinner,sun4i-a10-crypto"; + crypto: crypto-engine@1c15000 { + compatible = "allwinner,sun6i-a31-crypto", + "allwinner,sun4i-a10-crypto"; reg = <0x01c15000 0x1000>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 5>, <&ss_clk>; + clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>; clock-names = "ahb", "mod"; - resets = <&ahb1_rst 5>; + resets = <&ccu RST_AHB1_SS>; reset-names = "ahb"; }; - timer@01c60000 { + codec: codec@1c22c00 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun6i-a31-codec"; + reg = <0x01c22c00 0x400>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>; + clock-names = "apb", "codec"; + resets = <&ccu RST_APB1_CODEC>; + dmas = <&dma 15>, <&dma 15>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + timer@1c60000 { compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer"; reg = <0x01c60000 0x1000>; @@ -971,62 +936,62 @@ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 19>; - resets = <&ahb1_rst 19>; + clocks = <&ccu CLK_AHB1_HSTIMER>; + resets = <&ccu RST_AHB1_HSTIMER>; }; - spi0: spi@01c68000 { + spi0: spi@1c68000 { compatible = "allwinner,sun6i-a31-spi"; reg = <0x01c68000 0x1000>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 20>, <&spi0_clk>; + clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>; clock-names = "ahb", "mod"; dmas = <&dma 23>, <&dma 23>; dma-names = "rx", "tx"; - resets = <&ahb1_rst 20>; + resets = <&ccu RST_AHB1_SPI0>; status = "disabled"; }; - spi1: spi@01c69000 { + spi1: spi@1c69000 { compatible = "allwinner,sun6i-a31-spi"; reg = <0x01c69000 0x1000>; interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 21>, <&spi1_clk>; + clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>; clock-names = "ahb", "mod"; dmas = <&dma 24>, <&dma 24>; dma-names = "rx", "tx"; - resets = <&ahb1_rst 21>; + resets = <&ccu RST_AHB1_SPI1>; status = "disabled"; }; - spi2: spi@01c6a000 { + spi2: spi@1c6a000 { compatible = "allwinner,sun6i-a31-spi"; reg = <0x01c6a000 0x1000>; interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 22>, <&spi2_clk>; + clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>; clock-names = "ahb", "mod"; dmas = <&dma 25>, <&dma 25>; dma-names = "rx", "tx"; - resets = <&ahb1_rst 22>; + resets = <&ccu RST_AHB1_SPI2>; status = "disabled"; }; - spi3: spi@01c6b000 { + spi3: spi@1c6b000 { compatible = "allwinner,sun6i-a31-spi"; reg = <0x01c6b000 0x1000>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 23>, <&spi3_clk>; + clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>; clock-names = "ahb", "mod"; dmas = <&dma 26>, <&dma 26>; dma-names = "rx", "tx"; - resets = <&ahb1_rst 23>; + resets = <&ccu RST_AHB1_SPI3>; status = "disabled"; }; - gic: interrupt-controller@01c81000 { + gic: interrupt-controller@1c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, - <0x01c82000 0x1000>, + <0x01c82000 0x2000>, <0x01c84000 0x2000>, <0x01c86000 0x2000>; interrupt-controller; @@ -1034,30 +999,279 @@ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; - rtc: rtc@01f00000 { + fe0: display-frontend@1e00000 { + compatible = "allwinner,sun6i-a31-display-frontend"; + reg = <0x01e00000 0x20000>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>, + <&ccu CLK_DRAM_FE0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_AHB1_FE0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe0_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe0>; + }; + + fe0_out_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_in_fe0>; + }; + }; + }; + }; + + fe1: display-frontend@1e20000 { + compatible = "allwinner,sun6i-a31-display-frontend"; + reg = <0x01e20000 0x20000>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>, + <&ccu CLK_DRAM_FE1>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_AHB1_FE1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe1_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe1>; + }; + + fe1_out_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_in_fe1>; + }; + }; + }; + }; + + be1: display-backend@1e40000 { + compatible = "allwinner,sun6i-a31-display-backend"; + reg = <0x01e40000 0x10000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>, + <&ccu CLK_DRAM_BE1>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_AHB1_BE1>; + + assigned-clocks = <&ccu CLK_BE1>; + assigned-clock-rates = <300000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be1_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be1>; + }; + + be1_in_fe1: endpoint@1 { + reg = <1>; + remote-endpoint = <&fe1_out_be1>; + }; + }; + + be1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be1_out_drc1: endpoint@1 { + reg = <1>; + remote-endpoint = <&drc1_in_be1>; + }; + }; + }; + }; + + drc1: drc@1e50000 { + compatible = "allwinner,sun6i-a31-drc"; + reg = <0x01e50000 0x10000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>, + <&ccu CLK_DRAM_DRC1>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_AHB1_DRC1>; + + assigned-clocks = <&ccu CLK_IEP_DRC1>; + assigned-clock-rates = <300000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + drc1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + drc1_in_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_out_drc1>; + }; + }; + + drc1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + drc1_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_drc1>; + }; + + drc1_out_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_in_drc1>; + }; + }; + }; + }; + + be0: display-backend@1e60000 { + compatible = "allwinner,sun6i-a31-display-backend"; + reg = <0x01e60000 0x10000>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>, + <&ccu CLK_DRAM_BE0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_AHB1_BE0>; + + assigned-clocks = <&ccu CLK_BE0>; + assigned-clock-rates = <300000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be0_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be0>; + }; + + be0_in_fe1: endpoint@1 { + reg = <1>; + remote-endpoint = <&fe1_out_be0>; + }; + }; + + be0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be0_out_drc0: endpoint@0 { + reg = <0>; + remote-endpoint = <&drc0_in_be0>; + }; + }; + }; + }; + + drc0: drc@1e70000 { + compatible = "allwinner,sun6i-a31-drc"; + reg = <0x01e70000 0x10000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>, + <&ccu CLK_DRAM_DRC0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_AHB1_DRC0>; + + assigned-clocks = <&ccu CLK_IEP_DRC0>; + assigned-clock-rates = <300000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + drc0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + drc0_in_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_out_drc0>; + }; + }; + + drc0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + drc0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_drc0>; + }; + + drc0_out_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_in_drc0>; + }; + }; + }; + }; + + rtc: rtc@1f00000 { compatible = "allwinner,sun6i-a31-rtc"; reg = <0x01f00000 0x54>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; }; - nmi_intc: interrupt-controller@01f00c0c { - compatible = "allwinner,sun6i-a31-sc-nmi"; + nmi_intc: interrupt-controller@1f00c00 { + compatible = "allwinner,sun6i-a31-r-intc"; interrupt-controller; #interrupt-cells = <2>; - reg = <0x01f00c0c 0x38>; + reg = <0x01f00c00 0x400>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; }; - prcm@01f01400 { + prcm@1f01400 { compatible = "allwinner,sun6i-a31-prcm"; reg = <0x01f01400 0x200>; ar100: ar100_clk { compatible = "allwinner,sun6i-a31-ar100-clk"; #clock-cells = <0>; - clocks = <&osc32k>, <&osc24M>, <&pll6 0>, - <&pll6 0>; + clocks = <&osc32k>, <&osc24M>, + <&ccu CLK_PLL_PERIPH>, + <&ccu CLK_PLL_PERIPH>; clock-output-names = "ar100"; }; @@ -1100,12 +1314,12 @@ }; }; - cpucfg@01f01c00 { + cpucfg@1f01c00 { compatible = "allwinner,sun6i-a31-cpuconfig"; reg = <0x01f01c00 0x300>; }; - ir: ir@01f02000 { + ir: ir@1f02000 { compatible = "allwinner,sun5i-a13-ir"; clocks = <&apb0_gates 1>, <&ir_clk>; clock-names = "apb", "ir"; @@ -1115,12 +1329,13 @@ status = "disabled"; }; - r_pio: pinctrl@01f02c00 { + r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun6i-a31-r-pinctrl"; reg = <0x01f02c00 0x400>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 0>; + clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; resets = <&apb0_rst 0>; gpio-controller; interrupt-controller; @@ -1129,21 +1344,17 @@ #gpio-cells = <3>; ir_pins_a: ir@0 { - allwinner,pins = "PL4"; - allwinner,function = "s_ir"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PL4"; + function = "s_ir"; }; p2wi_pins: p2wi { - allwinner,pins = "PL0", "PL1"; - allwinner,function = "s_p2wi"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PL0", "PL1"; + function = "s_p2wi"; }; }; - p2wi: i2c@01f03400 { + p2wi: i2c@1f03400 { compatible = "allwinner,sun6i-a31-p2wi"; reg = <0x01f03400 0x400>; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/dts/sun6i-a31s-cs908.dts b/arch/arm/dts/sun6i-a31s-cs908.dts index 5e8f8c4f2b..75e578159c 100644 --- a/arch/arm/dts/sun6i-a31s-cs908.dts +++ b/arch/arm/dts/sun6i-a31s-cs908.dts @@ -43,8 +43,6 @@ /dts-v1/; #include "sun6i-a31s.dtsi" -#include <dt-bindings/pinctrl/sun4i-a10.h> - / { model = "CSQ CS908 top set box"; compatible = "csq,cs908", "allwinner,sun6i-a31s"; diff --git a/arch/arm/dts/sun6i-a31s-primo81.dts b/arch/arm/dts/sun6i-a31s-primo81.dts index 73c133f5e7..4cb9664cdb 100644 --- a/arch/arm/dts/sun6i-a31s-primo81.dts +++ b/arch/arm/dts/sun6i-a31s-primo81.dts @@ -48,22 +48,46 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "MSI Primo81 tablet"; compatible = "msi,primo81", "allwinner,sun6i-a31s"; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "c"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; }; &cpu0 { cpu-supply = <®_dcdc3>; }; +&de { + status = "okay"; +}; + &ehci0 { /* rtl8188etv wifi is connected here */ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { /* pull-ups and device VDDIO use AXP221 DLDO3 */ pinctrl-names = "default"; @@ -127,31 +151,26 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_primo81>; vmmc-supply = <®_dcdc1>; bus-width = <4>; - cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ - cd-inverted; + cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ status = "okay"; }; &pio { gt911_int_primo81: gt911_int_pin@0 { - allwinner,pins = "PA3"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PA3"; + function = "gpio_in"; }; mma8452_int_primo81: mma8452_int_pin@0 { - allwinner,pins = "PA9"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PA9"; + function = "gpio_in"; + bias-pull-up; }; mmc0_cd_pin_primo81: mmc0_cd_pin@0 { - allwinner,pins = "PA8"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PA8"; + function = "gpio_in"; + bias-pull-up; }; }; @@ -163,11 +182,16 @@ reg = <0x68>; interrupt-parent = <&nmi_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + x-powers,drive-vbus-en; }; }; #include "axp22x.dtsi" +&battery_power_supply { + status = "okay"; +}; + ®_aldo3 { regulator-always-on; regulator-min-microvolt = <2700000>; @@ -231,6 +255,11 @@ regulator-name = "vddio-csi"; }; +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + ®_eldo3 { regulator-min-microvolt = <1080000>; regulator-max-microvolt = <1320000>; @@ -243,12 +272,18 @@ }; &usb_otg { - /* otg support requires support for AXP221 usb-power-supply and GPIO */ - dr_mode = "host"; + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { status = "okay"; }; &usbphy { + usb0_id_det-gpio = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_drivevbus>; usb1_vbus-supply = <®_dldo1>; status = "okay"; }; diff --git a/arch/arm/dts/sun6i-a31s-sina31s-core.dtsi b/arch/arm/dts/sun6i-a31s-sina31s-core.dtsi index 4ec0c8679b..d7325bc4ee 100644 --- a/arch/arm/dts/sun6i-a31s-sina31s-core.dtsi +++ b/arch/arm/dts/sun6i-a31s-sina31s-core.dtsi @@ -45,7 +45,6 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Sinlinx SinA31s Core Board"; diff --git a/arch/arm/dts/sun6i-a31s-sina31s.dts b/arch/arm/dts/sun6i-a31s-sina31s.dts index 6ead2f5c84..da0ccf5a2c 100644 --- a/arch/arm/dts/sun6i-a31s-sina31s.dts +++ b/arch/arm/dts/sun6i-a31s-sina31s.dts @@ -53,6 +53,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -63,6 +74,35 @@ gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */ }; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "On-board SPDIF"; + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; +}; + +&codec { + allwinner,audio-routing = + "Line Out", "LINEOUT", + "MIC1", "Mic", + "Mic", "MBIAS"; + status = "okay"; +}; + +&de { + status = "okay"; }; &ehci0 { @@ -87,6 +127,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; @@ -117,8 +167,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_sina31s>; vmmc-supply = <®_dcdc1>; bus-width = <4>; - cd-gpios = <&pio 0 4 GPIO_ACTIVE_HIGH>; /* PA4 */ - cd-inverted; + cd-gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */ status = "okay"; }; @@ -128,17 +177,14 @@ &pio { led_pin_sina31s: led_pin@0 { - allwinner,pins = "PH13"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH13"; + function = "gpio_out"; }; mmc0_cd_pin_sina31s: mmc0_cd_pin@0 { - allwinner,pins = "PA4"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PA4"; + function = "gpio_in"; + bias-pull-up; }; }; @@ -148,6 +194,17 @@ regulator-name = "vcc-gmac-phy"; }; +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&spdif_pins_a>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + &usbphy { status = "okay"; }; diff --git a/arch/arm/dts/sun6i-a31s-sinovoip-bpi-m2.dts b/arch/arm/dts/sun6i-a31s-sinovoip-bpi-m2.dts index db7fa13f54..b8b79c0e9e 100644 --- a/arch/arm/dts/sun6i-a31s-sinovoip-bpi-m2.dts +++ b/arch/arm/dts/sun6i-a31s-sinovoip-bpi-m2.dts @@ -42,7 +42,6 @@ /dts-v1/; #include "sun6i-a31s.dtsi" -#include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> / { @@ -86,6 +85,10 @@ }; }; +&cpu0 { + cpu-supply = <®_dcdc3>; +}; + &ehci0 { status = "okay"; }; @@ -95,6 +98,7 @@ pinctrl-0 = <&gmac_pins_rgmii_a>, <&gmac_phy_reset_pin_bpi_m2>; phy = <&phy1>; phy-mode = "rgmii"; + phy-supply = <®_dldo1>; snps,reset-gpio = <&pio 0 21 GPIO_ACTIVE_HIGH>; /* PA21 */ snps,reset-active-low; snps,reset-delays-us = <0 10000 30000>; @@ -114,27 +118,26 @@ &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bpi_m2>; - vmmc-supply = <®_vcc3v0>; + vmmc-supply = <®_dcdc1>; bus-width = <4>; - cd-gpios = <&pio 0 4 GPIO_ACTIVE_HIGH>; /* PA4 */ - cd-inverted; + cd-gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */ status = "okay"; }; &mmc0_pins_a { - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + bias-pull-up; }; &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins_a>; - vmmc-supply = <®_vcc3v0>; + vmmc-supply = <®_aldo1>; mmc-pwrseq = <&mmc2_pwrseq>; bus-width = <4>; non-removable; status = "okay"; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&r_pio>; @@ -144,45 +147,148 @@ }; &mmc2_pins_a { - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + bias-pull-up; }; &ohci0 { status = "okay"; }; +&p2wi { + status = "okay"; + + axp22x: pmic@68 { + compatible = "x-powers,axp221"; + reg = <0x68>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + eldoin-supply = <®_dcdc1>; + x-powers,drive-vbus-en; + }; +}; + &pio { gmac_phy_reset_pin_bpi_m2: gmac_phy_reset_pin@0 { - allwinner,pins = "PA21"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PA21"; + function = "gpio_out"; }; led_pins_bpi_m2: led_pins@0 { - allwinner,pins = "PG5", "PG10", "PG11"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PG5", "PG10", "PG11"; + function = "gpio_out"; }; mmc0_cd_pin_bpi_m2: mmc0_cd_pin@0 { - allwinner,pins = "PA4"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PA4"; + function = "gpio_in"; + bias-pull-up; }; }; &r_pio { mmc2_pwrseq_pin_bpi_m2: mmc2_pwrseq_pin@0 { - allwinner,pins = "PL8"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PL8"; + function = "gpio_out"; }; }; +#include "axp22x.dtsi" + +®_aldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vcc-gmac"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_dc5ldo { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-cpus"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vdd-3v0"; +}; + +®_dcdc2 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-gpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc4 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-sys-dll"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dldo1 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-mac"; +}; + +®_dldo2 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "avdd-csi"; +}; + +®_dldo3 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pb"; +}; + +®_eldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vdd-csi"; + status = "okay"; +}; + +®_ldo_io1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pm-cpus"; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; diff --git a/arch/arm/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts b/arch/arm/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts index d6ad6196a7..aab6c1720e 100644 --- a/arch/arm/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts +++ b/arch/arm/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts @@ -45,7 +45,6 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Yones TopTech BS1078 v2 Tablet"; @@ -92,10 +91,9 @@ &pio { mmc0_cd_pin_bs1078v2: mmc0_cd_pin@0 { - allwinner,pins = "PA8"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PA8"; + function = "gpio_in"; + bias-pull-up; }; }; @@ -104,13 +102,12 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bs1078v2>; vmmc-supply = <®_vcc3v0>; bus-width = <4>; - cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ - cd-inverted; + cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ status = "okay"; }; &mmc0_pins_a { - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + bias-pull-up; }; &p2wi { diff --git a/arch/arm/dts/sun6i-a31s.dtsi b/arch/arm/dts/sun6i-a31s.dtsi index c17a32771b..97e2c51d0a 100644 --- a/arch/arm/dts/sun6i-a31s.dtsi +++ b/arch/arm/dts/sun6i-a31s.dtsi @@ -48,6 +48,14 @@ #include "sun6i-a31.dtsi" +&de { + compatible = "allwinner,sun6i-a31s-display-engine"; +}; + &pio { compatible = "allwinner,sun6i-a31s-pinctrl"; }; + +&tcon0 { + compatible = "allwinner,sun6i-a31s-tcon"; +}; diff --git a/arch/arm/dts/sun6i-reference-design-tablet.dtsi b/arch/arm/dts/sun6i-reference-design-tablet.dtsi index 0c434304e0..4e72e4f3ef 100644 --- a/arch/arm/dts/sun6i-reference-design-tablet.dtsi +++ b/arch/arm/dts/sun6i-reference-design-tablet.dtsi @@ -44,7 +44,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { aliases { @@ -70,24 +69,21 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_e708_q1>; vmmc-supply = <®_dcdc1>; bus-width = <4>; - cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ - cd-inverted; + cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ status = "okay"; }; &pio { mmc0_cd_pin_e708_q1: mmc0_cd_pin@0 { - allwinner,pins = "PA8"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PA8"; + function = "gpio_in"; + bias-pull-up; }; usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PA15"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PA15"; + function = "gpio_in"; + bias-pull-up; }; }; diff --git a/arch/arm/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/dts/sun7i-a20-bananapi-m1-plus.dts index 4c03cc3fd7..763cb03033 100644 --- a/arch/arm/dts/sun7i-a20-bananapi-m1-plus.dts +++ b/arch/arm/dts/sun7i-a20-bananapi-m1-plus.dts @@ -60,6 +60,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -109,6 +120,10 @@ cpu-supply = <®_dcdc2>; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -130,6 +145,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; @@ -144,6 +169,10 @@ #include "axp209.dtsi" +&ac_power_supply { + status = "okay"; +}; + &ir0 { pinctrl-names = "default"; pinctrl-0 = <&ir0_rx_pins_a>; @@ -155,8 +184,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bpi_m1p>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */ - cd-inverted; + cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ status = "okay"; }; diff --git a/arch/arm/dts/sun7i-a20-bananapi.dts b/arch/arm/dts/sun7i-a20-bananapi.dts index 67c8a7644b..70dfc4ac0b 100644 --- a/arch/arm/dts/sun7i-a20-bananapi.dts +++ b/arch/arm/dts/sun7i-a20-bananapi.dts @@ -48,7 +48,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "LeMaker Banana Pi"; @@ -64,6 +63,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -110,6 +120,10 @@ >; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -131,6 +145,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; @@ -160,8 +184,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapi>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */ - cd-inverted; + cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ status = "okay"; }; @@ -178,32 +201,77 @@ }; &pio { + gpio-line-names = + /* PA */ + "ERXD3", "ERXD2", "ERXD1", "ERXD0", "ETXD3", + "ETXD2", "ETXD1", "ETXD0", + "ERXCK", "ERXERR", "ERXDV", "EMDC", "EMDIO", + "ETXEN", "ETXCK", "ECRS", + "ECOL", "ETXERR", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* PB */ + "PMU-SCK", "PMU-SDA", "", "", "", "", "", "", + "", "USB0-DRV", "", "", "", "", "", "", + "", "", "", "", "SCL", "SDA", "", "", + "", "", "", "", "", "", "", "", + /* PC */ + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* PD */ + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* PE */ + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* PF */ + "SD0-D1", "SD0-D0", "SD0-CLK", "SD0-CMD", "SD0-D3", + "SD0-D2", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* PG */ + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* PH */ + "TXD0", "RXD0", "IO-1", "PH3", "USB0-IDDET", "PH5", "", "", + "", "", "SD0-DET", "", "", "", "", "", + "", "", "", "", "IO-4", "IO-5", "", "EMAC-PWR-EN", + "LED1", "", "", "", "", "", "", "", + /* PI */ + "", "", "", "IO-GCLK", "", "", "", "", + "", "", "SPI-CE0", "SPI-CLK", "SPI-MOSI", + "SPI-MISO", "SPI-CE1", "", + "IO-6", "IO-3", "IO-2", "IO-0", "", "", "", "", + "", "", "", "", "", "", "", ""; + usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PH4"; + function = "gpio_in"; + bias-pull-up; }; mmc0_cd_pin_bananapi: mmc0_cd_pin@0 { - allwinner,pins = "PH10"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PH10"; + function = "gpio_in"; + bias-pull-up; }; gmac_power_pin_bananapi: gmac_power_pin@0 { - allwinner,pins = "PH23"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH23"; + function = "gpio_out"; }; led_pins_bananapi: led_pins@0 { - allwinner,pins = "PH24"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH24"; + function = "gpio_out"; }; }; diff --git a/arch/arm/dts/sun7i-a20-bananapro.dts b/arch/arm/dts/sun7i-a20-bananapro.dts index 18fcc87f46..0898eb6162 100644 --- a/arch/arm/dts/sun7i-a20-bananapro.dts +++ b/arch/arm/dts/sun7i-a20-bananapro.dts @@ -76,6 +76,13 @@ }; }; + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&vmmc3_pin_bananapro>; + reset-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; + }; + reg_gmac_3v3: gmac-3v3 { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -87,23 +94,16 @@ enable-active-high; gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; }; - - reg_vmmc3: vmmc3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&vmmc3_pin_bananapro>; - regulator-name = "vmmc3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pio 7 22 GPIO_ACTIVE_HIGH>; - }; }; &ahci { status = "okay"; }; +&codec { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -158,18 +158,26 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapro>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */ - cd-inverted; + cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ status = "okay"; }; &mmc3 { pinctrl-names = "default"; pinctrl-0 = <&mmc3_pins_a>; - vmmc-supply = <®_vmmc3>; + vmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&wifi_pwrseq>; bus-width = <4>; non-removable; status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&pio>; + interrupts = <7 15 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; }; &ohci0 { @@ -182,45 +190,34 @@ &pio { gmac_power_pin_bananapro: gmac_power_pin@0 { - allwinner,pins = "PH23"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH23"; + function = "gpio_out"; }; led_pins_bananapro: led_pins@0 { - allwinner,pins = "PH24", "PG2"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH24", "PG2"; + function = "gpio_out"; }; mmc0_cd_pin_bananapro: mmc0_cd_pin@0 { - allwinner,pins = "PH10"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PH10"; + function = "gpio_in"; + bias-pull-up; }; usb1_vbus_pin_bananapro: usb1_vbus_pin@0 { - allwinner,pins = "PH0"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH0"; + function = "gpio_out"; }; usb2_vbus_pin_bananapro: usb2_vbus_pin@0 { - allwinner,pins = "PH1"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH1"; + function = "gpio_out"; }; vmmc3_pin_bananapro: vmmc3_pin@0 { - allwinner,pins = "PH22"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH22"; + function = "gpio_out"; }; }; diff --git a/arch/arm/dts/sun7i-a20-cubieboard2.dts b/arch/arm/dts/sun7i-a20-cubieboard2.dts index 1fa832d7b4..942ac9dfd4 100644 --- a/arch/arm/dts/sun7i-a20-cubieboard2.dts +++ b/arch/arm/dts/sun7i-a20-cubieboard2.dts @@ -48,7 +48,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Cubietech Cubieboard2"; @@ -62,6 +61,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -92,6 +102,10 @@ cpu-supply = <®_dcdc2>; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -112,6 +126,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; @@ -138,11 +162,10 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; @@ -160,17 +183,14 @@ &pio { led_pins_cubieboard2: led_pins@0 { - allwinner,pins = "PH20", "PH21"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH20", "PH21"; + function = "gpio_out"; }; usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PH4"; + function = "gpio_in"; + bias-pull-up; }; }; @@ -178,13 +198,12 @@ status = "okay"; }; -&usb_otg { - dr_mode = "otg"; +#include "axp209.dtsi" + +&ac_power_supply { status = "okay"; }; -#include "axp209.dtsi" - ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; @@ -224,6 +243,11 @@ status = "okay"; }; +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>; diff --git a/arch/arm/dts/sun7i-a20-cubietruck.dts b/arch/arm/dts/sun7i-a20-cubietruck.dts index 83f39b0362..5649161de1 100644 --- a/arch/arm/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/dts/sun7i-a20-cubietruck.dts @@ -48,7 +48,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Cubietech Cubietruck"; @@ -62,6 +61,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -127,6 +137,10 @@ cpu-supply = <®_dcdc2>; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -147,6 +161,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; @@ -179,11 +203,10 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; @@ -196,7 +219,7 @@ non-removable; status = "okay"; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&pio>; @@ -207,7 +230,7 @@ &mmc3_pins_a { /* AP6210 requires pull-up */ - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + bias-pull-up; }; &ohci0 { @@ -224,45 +247,33 @@ &pio { ahci_pwr_pin_cubietruck: ahci_pwr_pin@1 { - allwinner,pins = "PH12"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH12"; + function = "gpio_out"; }; led_pins_cubietruck: led_pins@0 { - allwinner,pins = "PH7", "PH11", "PH20", "PH21"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH7", "PH11", "PH20", "PH21"; + function = "gpio_out"; }; mmc3_pwrseq_pin_cubietruck: mmc3_pwrseq_pin@0 { - allwinner,pins = "PH9"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH9"; + function = "gpio_out"; }; usb0_vbus_pin_a: usb0_vbus_pin@0 { - allwinner,pins = "PH17"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH17"; + function = "gpio_out"; }; usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH19"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH19"; + function = "gpio_in"; }; usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PH22"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH22"; + function = "gpio_in"; }; }; @@ -280,6 +291,14 @@ #include "axp209.dtsi" +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; @@ -336,11 +355,16 @@ status = "okay"; }; +&usb_power_supply { + status = "okay"; +}; + &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; usb0_id_det-gpios = <&pio 7 19 GPIO_ACTIVE_HIGH>; /* PH19 */ usb0_vbus_det-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ + usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/dts/sun7i-a20-hummingbird.dts b/arch/arm/dts/sun7i-a20-hummingbird.dts index 37f4a54974..1f0e5ecbf0 100644 --- a/arch/arm/dts/sun7i-a20-hummingbird.dts +++ b/arch/arm/dts/sun7i-a20-hummingbird.dts @@ -48,7 +48,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Merrii A20 Hummingbird"; @@ -161,11 +160,10 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v0>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; @@ -188,31 +186,23 @@ &pio { ahci_pwr_pin_a20_hummingbird: ahci_pwr_pin@0 { - allwinner,pins = "PH15"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH15"; + function = "gpio_out"; }; usb1_vbus_pin_a20_hummingbird: usb1_vbus_pin@0 { - allwinner,pins = "PH2"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH2"; + function = "gpio_out"; }; mmc3_vdd_pin_a20_hummingbird: mmc3_vdd_pin@0 { - allwinner,pins = "PH9"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH9"; + function = "gpio_out"; }; gmac_vdd_pin_a20_hummingbird: gmac_vdd_pin@0 { - allwinner,pins = "PH16"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH16"; + function = "gpio_out"; }; }; diff --git a/arch/arm/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/dts/sun7i-a20-i12-tvbox.dts index 1e6bd360da..2e3f2f29d1 100644 --- a/arch/arm/dts/sun7i-a20-i12-tvbox.dts +++ b/arch/arm/dts/sun7i-a20-i12-tvbox.dts @@ -46,7 +46,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "I12 / Q5 / QT840A A20 tvbox"; @@ -158,11 +157,10 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; @@ -174,7 +172,7 @@ non-removable; status = "okay"; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&pio>; @@ -185,7 +183,7 @@ &mmc3_pins_a { /* AP6210 / AP6330 requires pull-up */ - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + bias-pull-up; }; &ohci0 { @@ -198,31 +196,23 @@ &pio { vmmc3_pin_i12_tvbox: vmmc3_pin@0 { - allwinner,pins = "PH2"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH2"; + function = "gpio_out"; }; vmmc3_io_pin_i12_tvbox: vmmc3_io_pin@0 { - allwinner,pins = "PH12"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH12"; + function = "gpio_out"; }; gmac_power_pin_i12_tvbox: gmac_power_pin@0 { - allwinner,pins = "PH21"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH21"; + function = "gpio_out"; }; led_pins_i12_tvbox: led_pins@0 { - allwinner,pins = "PH9", "PH20"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH9", "PH20"; + function = "gpio_out"; }; }; diff --git a/arch/arm/dts/sun7i-a20-icnova-swac.dts b/arch/arm/dts/sun7i-a20-icnova-swac.dts index f5b5325a70..926fa194eb 100644 --- a/arch/arm/dts/sun7i-a20-icnova-swac.dts +++ b/arch/arm/dts/sun7i-a20-icnova-swac.dts @@ -46,7 +46,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "ICnova-A20 SWAC"; @@ -105,11 +104,10 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 8 5 GPIO_ACTIVE_HIGH>; /* PI5 */ - cd-inverted; + cd-gpios = <&pio 8 5 GPIO_ACTIVE_LOW>; /* PI5 */ status = "okay"; }; diff --git a/arch/arm/dts/sun7i-a20-itead-ibox.dts b/arch/arm/dts/sun7i-a20-itead-ibox.dts index 10d48cbf81..1b05ba466e 100644 --- a/arch/arm/dts/sun7i-a20-itead-ibox.dts +++ b/arch/arm/dts/sun7i-a20-itead-ibox.dts @@ -121,20 +121,18 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; &pio { led_pins_itead_core: led_pins@0 { - allwinner,pins = "PH20","PH21"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_20_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH20","PH21"; + function = "gpio_out"; + drive-strength = <20>; }; }; diff --git a/arch/arm/dts/sun7i-a20-lamobo-r1.dts b/arch/arm/dts/sun7i-a20-lamobo-r1.dts index 73c05dab0a..b1ab7c1c33 100644 --- a/arch/arm/dts/sun7i-a20-lamobo-r1.dts +++ b/arch/arm/dts/sun7i-a20-lamobo-r1.dts @@ -46,7 +46,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Lamobo R1"; @@ -62,6 +61,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -86,10 +96,6 @@ }; }; -&ahci_pwr_pin_a { - allwinner,pins = "PB3"; -}; - &ahci { target-supply = <®_ahci_5v>; status = "okay"; @@ -103,6 +109,10 @@ cpu-supply = <®_dcdc2>; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -167,7 +177,7 @@ reg = <8>; label = "cpu"; ethernet = <&gmac>; - phy-mode = "rgmii"; + phy-mode = "rgmii-txid"; fixed-link { speed = <1000>; full-duplex; @@ -178,6 +188,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; @@ -207,8 +227,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_lamobo_r1>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */ - cd-inverted; + cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ status = "okay"; }; @@ -222,36 +241,38 @@ &pio { usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PH4"; + function = "gpio_in"; + bias-pull-up; }; mmc0_cd_pin_lamobo_r1: mmc0_cd_pin@0 { - allwinner,pins = "PH10"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PH10"; + function = "gpio_in"; + bias-pull-up; }; gmac_power_pin_lamobo_r1: gmac_power_pin@0 { - allwinner,pins = "PH23"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH23"; + function = "gpio_out"; }; led_pins_lamobo_r1: led_pins@0 { - allwinner,pins = "PH24"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH24"; + function = "gpio_out"; }; }; #include "axp209.dtsi" +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + ®_ahci_5v { gpio = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ status = "okay"; @@ -326,10 +347,6 @@ status = "okay"; }; -&usb2_vbus_pin_a { - allwinner,pins = "PH12"; -}; - &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>; diff --git a/arch/arm/dts/sun7i-a20-m3.dts b/arch/arm/dts/sun7i-a20-m3.dts index 8d9ea48dd9..e91a209850 100644 --- a/arch/arm/dts/sun7i-a20-m3.dts +++ b/arch/arm/dts/sun7i-a20-m3.dts @@ -48,7 +48,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Mele M3"; @@ -118,11 +117,10 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; @@ -145,10 +143,8 @@ &pio { led_pins_m3: led_pins@0 { - allwinner,pins = "PH20"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH20"; + function = "gpio_out"; }; }; diff --git a/arch/arm/dts/sun7i-a20-mk808c.dts b/arch/arm/dts/sun7i-a20-mk808c.dts index 90ff4a2670..6109f794a9 100644 --- a/arch/arm/dts/sun7i-a20-mk808c.dts +++ b/arch/arm/dts/sun7i-a20-mk808c.dts @@ -53,7 +53,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "mk808c"; @@ -67,12 +66,27 @@ chosen { stdout-path = "serial0:115200n8"; }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; }; &codec { status = "okay"; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -81,6 +95,16 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; @@ -110,11 +134,10 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v0>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; @@ -132,17 +155,13 @@ &pio { usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH4"; + function = "gpio_in"; }; usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PH5"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH5"; + function = "gpio_in"; }; }; diff --git a/arch/arm/dts/sun7i-a20-olimex-som-evb.dts b/arch/arm/dts/sun7i-a20-olimex-som-evb.dts index 23aacce4d6..f080f82b58 100644 --- a/arch/arm/dts/sun7i-a20-olimex-som-evb.dts +++ b/arch/arm/dts/sun7i-a20-olimex-som-evb.dts @@ -48,7 +48,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Olimex A20-Olimex-SOM-EVB"; @@ -62,6 +61,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -80,6 +90,10 @@ status = "okay"; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -88,6 +102,10 @@ status = "okay"; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + &codec { status = "okay"; }; @@ -104,6 +122,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; @@ -116,6 +144,18 @@ }; }; +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; +}; + &lradc { vref-supply = <®_vcc3v0>; status = "okay"; @@ -172,11 +212,10 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; @@ -185,8 +224,7 @@ pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_olimex_som_evb>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 0 GPIO_ACTIVE_HIGH>; /* PH0 */ - cd-inverted; + cd-gpios = <&pio 7 0 GPIO_ACTIVE_LOW>; /* PH0 */ status = "okay"; }; @@ -204,38 +242,30 @@ &pio { ahci_pwr_pin_olimex_som_evb: ahci_pwr_pin@1 { - allwinner,pins = "PC3"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PC3"; + function = "gpio_out"; }; led_pins_olimex_som_evb: led_pins@0 { - allwinner,pins = "PH2"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_20_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH2"; + function = "gpio_out"; + drive-strength = <20>; }; mmc3_cd_pin_olimex_som_evb: mmc3_cd_pin@0 { - allwinner,pins = "PH0"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PH0"; + function = "gpio_in"; + bias-pull-up; }; usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH4"; + function = "gpio_in"; }; usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PH5"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH5"; + function = "gpio_in"; }; }; @@ -284,12 +314,38 @@ status = "okay"; }; +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins_a>, + <&spi1_cs0_pins_a>; + status = "okay"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>, + <&spi2_cs0_pins_a>; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; status = "okay"; }; +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&uart6_pins_a>; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_a>; + status = "okay"; +}; + &usb_otg { dr_mode = "otg"; status = "okay"; diff --git a/arch/arm/dts/sun7i-a20-olimex-som204-evb.dts b/arch/arm/dts/sun7i-a20-olimex-som204-evb.dts index c183920cef..3d7b5c848f 100644 --- a/arch/arm/dts/sun7i-a20-olimex-som204-evb.dts +++ b/arch/arm/dts/sun7i-a20-olimex-som204-evb.dts @@ -32,6 +32,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; @@ -65,6 +76,12 @@ status = "okay"; }; +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&can0_pins_a>; + status = "okay"; +}; + &codec { status = "okay"; }; @@ -73,6 +90,10 @@ cpu-supply = <®_dcdc2>; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -98,6 +119,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; @@ -141,8 +172,7 @@ pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -181,6 +211,14 @@ #include "axp209.dtsi" +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + ®_ahci_5v { gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; status = "okay"; diff --git a/arch/arm/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/dts/sun7i-a20-olinuxino-lime.dts index 35ad7006c5..d20fd03596 100644 --- a/arch/arm/dts/sun7i-a20-olinuxino-lime.dts +++ b/arch/arm/dts/sun7i-a20-olinuxino-lime.dts @@ -49,7 +49,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Olimex A20-OLinuXino-LIME"; @@ -63,6 +62,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -81,6 +91,10 @@ status = "okay"; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -101,6 +115,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; @@ -131,11 +155,10 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; @@ -153,31 +176,26 @@ &pio { ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 { - allwinner,pins = "PC3"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PC3"; + function = "gpio_out"; }; led_pins_olinuxinolime: led_pins@0 { - allwinner,pins = "PH2"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_20_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH2"; + function = "gpio_out"; + drive-strength = <20>; }; usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PH4"; + function = "gpio_in"; + bias-pull-up; }; usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PH5"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; + pins = "PH5"; + function = "gpio_in"; + bias-pull-down; }; }; diff --git a/arch/arm/dts/sun7i-a20-olinuxino-lime2-emmc.dts b/arch/arm/dts/sun7i-a20-olinuxino-lime2-emmc.dts index 10d307408f..81f376f2a4 100644 --- a/arch/arm/dts/sun7i-a20-olinuxino-lime2-emmc.dts +++ b/arch/arm/dts/sun7i-a20-olinuxino-lime2-emmc.dts @@ -57,10 +57,8 @@ &pio { mmc2_pins_nrst: mmc2-rst-pin { - allwinner,pins = "PC16"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PC16"; + function = "gpio_out"; }; }; diff --git a/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts index d5c796c8d1..b828677f33 100644 --- a/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts +++ b/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts @@ -46,7 +46,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Olimex A20-OLinuXino-LIME2"; @@ -60,6 +59,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -86,6 +96,10 @@ status = "okay"; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -106,63 +120,25 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { - compatible = "x-powers,axp209"; reg = <0x34>; interrupt-parent = <&nmi_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - interrupt-controller; - #interrupt-cells = <1>; - - acin-supply = <®_axp_ipsout>; - vin2-supply = <®_axp_ipsout>; - vin3-supply = <®_axp_ipsout>; - ldo24in-supply = <®_axp_ipsout>; - ldo3in-supply = <®_axp_ipsout>; - - regulators { - vdd_rtc: ldo1 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - }; - - avcc: ldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcc_csi0: ldo3 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <3500000>; - regulator-always-on; - }; - - vcc_csi1: ldo4 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_cpu: dcdc2 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <2275000>; - regulator-always-on; - }; - - vdd_int: dcdc3 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <3500000>; - regulator-always-on; - }; - }; }; }; @@ -180,11 +156,10 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; @@ -202,38 +177,31 @@ &pio { ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 { - allwinner,pins = "PC3"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PC3"; + function = "gpio_out"; }; led_pins_olinuxinolime: led_pins@0 { - allwinner,pins = "PH2"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_20_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH2"; + function = "gpio_out"; + drive-strength = <20>; }; usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PH4"; + function = "gpio_in"; + bias-pull-up; }; usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PH5"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; + pins = "PH5"; + function = "gpio_in"; + bias-pull-down; }; usb0_vbus_pin_lime2: usb0_vbus_pin@0 { - allwinner,pins = "PC17"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PC17"; + function = "gpio_out"; }; }; @@ -243,6 +211,48 @@ status = "okay"; }; +#include "axp209.dtsi" + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-always-on; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_ldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vddio-csi0"; +}; + +®_ldo4 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vddio-csi1"; +}; + ®_usb0_vbus { pinctrl-0 = <&usb0_vbus_pin_lime2>; gpio = <&pio 2 17 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/dts/sun7i-a20-olinuxino-micro.dts index 7e3006f6a7..866d230593 100644 --- a/arch/arm/dts/sun7i-a20-olinuxino-micro.dts +++ b/arch/arm/dts/sun7i-a20-olinuxino-micro.dts @@ -49,7 +49,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Olimex A20-Olinuxino Micro"; @@ -67,6 +66,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -85,6 +95,18 @@ status = "okay"; }; +&codec { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -95,7 +117,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; + pinctrl-0 = <&gmac_pins_mii_a>, <&gmac_txerr>; phy = <&phy1>; phy-mode = "mii"; status = "okay"; @@ -105,19 +127,25 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; status = "okay"; axp209: pmic@34 { - compatible = "x-powers,axp209"; reg = <0x34>; interrupt-parent = <&nmi_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - interrupt-controller; - #interrupt-cells = <1>; }; }; @@ -195,11 +223,10 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; @@ -208,8 +235,7 @@ pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_olinuxinom>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ - cd-inverted; + cd-gpios = <&pio 7 11 GPIO_ACTIVE_LOW>; /* PH11 */ status = "okay"; }; @@ -226,35 +252,67 @@ }; &pio { + gmac_txerr: gmac_txerr@0 { + pins = "PA17"; + function = "gmac"; + }; + mmc3_cd_pin_olinuxinom: mmc3_cd_pin@0 { - allwinner,pins = "PH11"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PH11"; + function = "gpio_in"; + bias-pull-up; }; led_pins_olinuxino: led_pins@0 { - allwinner,pins = "PH2"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_20_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH2"; + function = "gpio_out"; + drive-strength = <20>; }; usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PH4"; + function = "gpio_in"; + bias-pull-up; }; usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PH5"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; + pins = "PH5"; + function = "gpio_in"; + bias-pull-down; }; }; +#include "axp209.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + ®_ahci_5v { status = "okay"; }; @@ -308,6 +366,10 @@ status = "okay"; }; +&usb_power_supply { + status = "okay"; +}; + &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; diff --git a/arch/arm/dts/sun7i-a20-orangepi-mini.dts b/arch/arm/dts/sun7i-a20-orangepi-mini.dts index 2be04c438b..f5c7178eb0 100644 --- a/arch/arm/dts/sun7i-a20-orangepi-mini.dts +++ b/arch/arm/dts/sun7i-a20-orangepi-mini.dts @@ -48,7 +48,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Orange Pi Mini"; @@ -62,6 +61,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -99,6 +109,10 @@ status = "okay"; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -120,6 +134,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; @@ -145,8 +169,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_orangepi>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */ - cd-inverted; + cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ status = "okay"; }; @@ -155,8 +178,7 @@ pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_orangepi>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ - cd-inverted; + cd-gpios = <&pio 7 11 GPIO_ACTIVE_LOW>; /* PH11 */ status = "okay"; }; @@ -166,52 +188,41 @@ &pio { usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PH4"; + function = "gpio_in"; + bias-pull-up; }; mmc0_cd_pin_orangepi: mmc0_cd_pin@0 { - allwinner,pins = "PH10"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PH10"; + function = "gpio_in"; + bias-pull-up; }; mmc3_cd_pin_orangepi: mmc3_cd_pin@0 { - allwinner,pins = "PH11"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PH11"; + function = "gpio_in"; + bias-pull-up; }; usb2_vbus_pin_bananapro: usb2_vbus_pin@0 { - allwinner,pins = "PH22"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH22"; + function = "gpio_out"; }; gmac_power_pin_orangepi: gmac_power_pin@0 { - allwinner,pins = "PH23"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH23"; + function = "gpio_out"; }; led_pins_orangepi: led_pins@0 { - allwinner,pins = "PH24", "PH25"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH24", "PH25"; + function = "gpio_out"; }; usb1_vbus_pin_bananapro: usb1_vbus_pin@0 { - allwinner,pins = "PH26"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH26"; + function = "gpio_out"; }; }; diff --git a/arch/arm/dts/sun7i-a20-orangepi.dts b/arch/arm/dts/sun7i-a20-orangepi.dts index 71125bf645..7a4244e575 100644 --- a/arch/arm/dts/sun7i-a20-orangepi.dts +++ b/arch/arm/dts/sun7i-a20-orangepi.dts @@ -48,7 +48,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Orange Pi"; @@ -136,8 +135,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_orangepi>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */ - cd-inverted; + cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ status = "okay"; }; @@ -147,45 +145,35 @@ &pio { usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PH4"; + function = "gpio_in"; + bias-pull-up; }; mmc0_cd_pin_orangepi: mmc0_cd_pin@0 { - allwinner,pins = "PH10"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PH10"; + function = "gpio_in"; + bias-pull-up; }; usb2_vbus_pin_bananapro: usb2_vbus_pin@0 { - allwinner,pins = "PH22"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH22"; + function = "gpio_out"; }; gmac_power_pin_orangepi: gmac_power_pin@0 { - allwinner,pins = "PH23"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH23"; + function = "gpio_out"; }; led_pins_orangepi: led_pins@0 { - allwinner,pins = "PH24"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH24"; + function = "gpio_out"; }; usb1_vbus_pin_bananapro: usb1_vbus_pin@0 { - allwinner,pins = "PH26"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH26"; + function = "gpio_out"; }; }; diff --git a/arch/arm/dts/sun7i-a20-pcduino3-nano.dts b/arch/arm/dts/sun7i-a20-pcduino3-nano.dts index ddac7328b8..bfca960b03 100644 --- a/arch/arm/dts/sun7i-a20-pcduino3-nano.dts +++ b/arch/arm/dts/sun7i-a20-pcduino3-nano.dts @@ -58,6 +58,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -90,6 +101,10 @@ cpu-supply = <®_dcdc2>; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -110,6 +125,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; @@ -130,11 +155,10 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; @@ -152,31 +176,24 @@ &pio { ahci_pwr_pin_pcduino3_nano: ahci_pwr_pin@0 { - allwinner,pins = "PH2"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH2"; + function = "gpio_out"; }; led_pins_pcduino3_nano: led_pins@0 { - allwinner,pins = "PH16", "PH15"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH16", "PH15"; + function = "gpio_out"; }; usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PH4"; + function = "gpio_in"; + bias-pull-up; }; usb1_vbus_pin_pcduino3_nano: usb1_vbus_pin@0 { - allwinner,pins = "PD2"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PD2"; + function = "gpio_out"; }; }; diff --git a/arch/arm/dts/sun7i-a20-pcduino3.dts b/arch/arm/dts/sun7i-a20-pcduino3.dts index 7f449b6a28..c576f101fb 100644 --- a/arch/arm/dts/sun7i-a20-pcduino3.dts +++ b/arch/arm/dts/sun7i-a20-pcduino3.dts @@ -48,7 +48,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "LinkSprite pcDuino3"; @@ -107,10 +106,6 @@ status = "okay"; }; -&ahci_pwr_pin_a { - allwinner,pins = "PH2"; -}; - &codec { status = "okay"; }; @@ -161,7 +156,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ @@ -182,24 +177,19 @@ &pio { led_pins_pcduino3: led_pins@0 { - allwinner,pins = "PH15", "PH16"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH15", "PH16"; + function = "gpio_out"; }; key_pins_pcduino3: key_pins@0 { - allwinner,pins = "PH17", "PH18", "PH19"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH17", "PH18", "PH19"; + function = "gpio_in"; }; usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PH4"; + function = "gpio_in"; + bias-pull-up; }; }; diff --git a/arch/arm/dts/sun7i-a20-primo73.dts b/arch/arm/dts/sun7i-a20-primo73.dts index 0658f82675..b7294e0348 100644 --- a/arch/arm/dts/sun7i-a20-primo73.dts +++ b/arch/arm/dts/sun7i-a20-primo73.dts @@ -60,43 +60,33 @@ chosen { stdout-path = "serial0:115200n8"; }; +}; - soc@01c00000 { - mmc0: mmc@01c0f000 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 0>; /* PH1 */ - cd-inverted; - status = "okay"; - }; - - usbphy: phy@01c13400 { - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; - }; +&ehci1 { + status = "okay"; +}; - ehci1: usb@01c1c000 { - /* rtl8188etv wifi is connected here */ - status = "okay"; - }; +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; - pinctrl@01c20800 { - usb2_vbus_pin_a: usb2_vbus_pin@0 { - allwinner,pins = "PH12"; - }; - }; +®_usb2_vbus { + gpio = <&pio 7 12 0>; /* PH12 */ + status = "okay"; +}; - uart0: serial@01c28000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; - }; - }; +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; - reg_usb2_vbus: usb2-vbus { - gpio = <&pio 7 12 0>; /* PH12 */ - status = "okay"; - }; +&usbphy { + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; }; diff --git a/arch/arm/dts/sun7i-a20-wexler-tab7200.dts b/arch/arm/dts/sun7i-a20-wexler-tab7200.dts index 2f6b21addd..8202c87ca6 100644 --- a/arch/arm/dts/sun7i-a20-wexler-tab7200.dts +++ b/arch/arm/dts/sun7i-a20-wexler-tab7200.dts @@ -151,11 +151,10 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; @@ -173,31 +172,24 @@ &pio { bl_enable_pin: bl_enable_pin@0 { - allwinner,pins = "PH7"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH7"; + function = "gpio_out"; }; codec_pa_pin: codec_pa_pin@0 { - allwinner,pins = "PH15"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH15"; + function = "gpio_out"; }; ts_reset_pin: ts_reset_pin@0 { - allwinner,pins = "PB13"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PB13"; + function = "gpio_out"; }; usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PH4"; + function = "gpio_in"; + bias-pull-up; }; }; diff --git a/arch/arm/dts/sun7i-a20-wits-pro-a20-dkt.dts b/arch/arm/dts/sun7i-a20-wits-pro-a20-dkt.dts index dc31d476ef..ff5c108658 100644 --- a/arch/arm/dts/sun7i-a20-wits-pro-a20-dkt.dts +++ b/arch/arm/dts/sun7i-a20-wits-pro-a20-dkt.dts @@ -120,11 +120,10 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ status = "okay"; }; @@ -137,7 +136,7 @@ non-removable; status = "okay"; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&pio>; @@ -160,17 +159,14 @@ &pio { vmmc3_pin_ap6xxx_wl_regon: vmmc3_pin@0 { - allwinner,pins = "PH9"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH9"; + function = "gpio_out"; }; usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH4"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PH4"; + function = "gpio_in"; + bias-pull-up; }; }; diff --git a/arch/arm/dts/sun7i-a20.dtsi b/arch/arm/dts/sun7i-a20.dtsi index 4394711e5a..e529e4ff21 100644 --- a/arch/arm/dts/sun7i-a20.dtsi +++ b/arch/arm/dts/sun7i-a20.dtsi @@ -46,10 +46,9 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/thermal/thermal.h> - -#include <dt-bindings/clock/sun4i-a10-pll2.h> #include <dt-bindings/dma/sun4i-a10.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> +#include <dt-bindings/clock/sun7i-a20-ccu.h> +#include <dt-bindings/reset/sun4i-a10-ccu.h> / { interrupt-parent = <&gic>; @@ -67,9 +66,10 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&ahb_gates 36>, <&ahb_gates 43>, - <&ahb_gates 44>, <&de_be0_clk>, - <&tcon0_ch1_clk>, <&dram_gates 26>; + clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, + <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, + <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>, + <&ccu CLK_HDMI>; status = "disabled"; }; @@ -77,9 +77,9 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0"; - clocks = <&ahb_gates 36>, <&ahb_gates 44>, - <&de_be0_clk>, <&tcon0_ch0_clk>, - <&dram_gates 26>; + clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>, + <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>, + <&ccu CLK_DRAM_DE_BE0>; status = "disabled"; }; @@ -87,10 +87,10 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-tve0"; - clocks = <&ahb_gates 34>, <&ahb_gates 36>, - <&ahb_gates 44>, - <&de_be0_clk>, <&tcon0_ch1_clk>, - <&dram_gates 5>, <&dram_gates 26>; + clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>, + <&ccu CLK_AHB_DE_BE0>, + <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>, + <&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>; status = "disabled"; }; }; @@ -103,7 +103,7 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; - clocks = <&cpu>; + clocks = <&ccu CLK_CPU>; clock-latency = <244144>; /* 8 32k periods */ operating-points = < /* kHz uV */ @@ -116,8 +116,6 @@ 144000 1000000 >; #cooling-cells = <2>; - cooling-min-level = <0>; - cooling-max-level = <6>; }; cpu@1 { @@ -182,23 +180,13 @@ #size-cells = <1>; ranges; - osc24M: clk@01c20050 { + osc24M: clk@1c20050 { #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-osc-clk"; - reg = <0x01c20050 0x4>; + compatible = "fixed-clock"; clock-frequency = <24000000>; clock-output-names = "osc24M"; }; - osc3M: osc3M_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <8>; - clock-mult = <1>; - clocks = <&osc24M>; - clock-output-names = "osc3M"; - }; - osc32k: clk@0 { #clock-cells = <0>; compatible = "fixed-clock"; @@ -206,528 +194,6 @@ clock-output-names = "osc32k"; }; - pll1: clk@01c20000 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll1-clk"; - reg = <0x01c20000 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll1"; - }; - - pll2: clk@01c20008 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll2-clk"; - reg = <0x01c20008 0x8>; - clocks = <&osc24M>; - clock-output-names = "pll2-1x", "pll2-2x", - "pll2-4x", "pll2-8x"; - }; - - pll3: clk@01c20010 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll3-clk"; - reg = <0x01c20010 0x4>; - clocks = <&osc3M>; - clock-output-names = "pll3"; - }; - - pll3x2: pll3x2_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&pll3>; - clock-div = <1>; - clock-mult = <2>; - clock-output-names = "pll3-2x"; - }; - - pll4: clk@01c20018 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-pll4-clk"; - reg = <0x01c20018 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll4"; - }; - - pll5: clk@01c20020 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll5-clk"; - reg = <0x01c20020 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll5_ddr", "pll5_other"; - }; - - pll6: clk@01c20028 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll6-clk"; - reg = <0x01c20028 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll6_sata", "pll6_other", "pll6", - "pll6_div_4"; - }; - - pll7: clk@01c20030 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll3-clk"; - reg = <0x01c20030 0x4>; - clocks = <&osc3M>; - clock-output-names = "pll7"; - }; - - pll7x2: pll7x2_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&pll7>; - clock-div = <1>; - clock-mult = <2>; - clock-output-names = "pll7-2x"; - }; - - pll8: clk@01c20040 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-pll4-clk"; - reg = <0x01c20040 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll8"; - }; - - cpu: cpu@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-cpu-clk"; - reg = <0x01c20054 0x4>; - clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>; - clock-output-names = "cpu"; - }; - - axi: axi@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-axi-clk"; - reg = <0x01c20054 0x4>; - clocks = <&cpu>; - clock-output-names = "axi"; - }; - - ahb: ahb@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun5i-a13-ahb-clk"; - reg = <0x01c20054 0x4>; - clocks = <&axi>, <&pll6 3>, <&pll6 1>; - clock-output-names = "ahb"; - /* - * Use PLL6 as parent, instead of CPU/AXI - * which has rate changes due to cpufreq - */ - assigned-clocks = <&ahb>; - assigned-clock-parents = <&pll6 3>; - }; - - ahb_gates: clk@01c20060 { - #clock-cells = <1>; - compatible = "allwinner,sun7i-a20-ahb-gates-clk"; - reg = <0x01c20060 0x8>; - clocks = <&ahb>; - clock-indices = <0>, <1>, - <2>, <3>, <4>, - <5>, <6>, <7>, <8>, - <9>, <10>, <11>, <12>, - <13>, <14>, <16>, - <17>, <18>, <20>, <21>, - <22>, <23>, <25>, - <28>, <32>, <33>, <34>, - <35>, <36>, <37>, <40>, - <41>, <42>, <43>, - <44>, <45>, <46>, - <47>, <49>, <50>, - <52>; - clock-output-names = "ahb_usb0", "ahb_ehci0", - "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", - "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", - "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms", - "ahb_nand", "ahb_sdram", "ahb_ace", - "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1", - "ahb_spi2", "ahb_spi3", "ahb_sata", - "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0", - "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0", - "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0", - "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", - "ahb_de_fe1", "ahb_gmac", "ahb_mp", - "ahb_mali"; - }; - - apb0: apb0@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb0-clk"; - reg = <0x01c20054 0x4>; - clocks = <&ahb>; - clock-output-names = "apb0"; - }; - - apb0_gates: clk@01c20068 { - #clock-cells = <1>; - compatible = "allwinner,sun7i-a20-apb0-gates-clk"; - reg = <0x01c20068 0x4>; - clocks = <&apb0>; - clock-indices = <0>, <1>, - <2>, <3>, <4>, - <5>, <6>, <7>, - <8>, <10>; - clock-output-names = "apb0_codec", "apb0_spdif", - "apb0_ac97", "apb0_i2s0", "apb0_i2s1", - "apb0_pio", "apb0_ir0", "apb0_ir1", - "apb0_i2s2", "apb0_keypad"; - }; - - apb1: clk@01c20058 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb1-clk"; - reg = <0x01c20058 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&osc32k>; - clock-output-names = "apb1"; - }; - - apb1_gates: clk@01c2006c { - #clock-cells = <1>; - compatible = "allwinner,sun7i-a20-apb1-gates-clk"; - reg = <0x01c2006c 0x4>; - clocks = <&apb1>; - clock-indices = <0>, <1>, - <2>, <3>, <4>, - <5>, <6>, <7>, - <15>, <16>, <17>, - <18>, <19>, <20>, - <21>, <22>, <23>; - clock-output-names = "apb1_i2c0", "apb1_i2c1", - "apb1_i2c2", "apb1_i2c3", "apb1_can", - "apb1_scr", "apb1_ps20", "apb1_ps21", - "apb1_i2c4", "apb1_uart0", "apb1_uart1", - "apb1_uart2", "apb1_uart3", "apb1_uart4", - "apb1_uart5", "apb1_uart6", "apb1_uart7"; - }; - - nand_clk: clk@01c20080 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20080 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "nand"; - }; - - ms_clk: clk@01c20084 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20084 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ms"; - }; - - mmc0_clk: clk@01c20088 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20088 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc0", - "mmc0_output", - "mmc0_sample"; - }; - - mmc1_clk: clk@01c2008c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c2008c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc1", - "mmc1_output", - "mmc1_sample"; - }; - - mmc2_clk: clk@01c20090 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20090 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc2", - "mmc2_output", - "mmc2_sample"; - }; - - mmc3_clk: clk@01c20094 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20094 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc3", - "mmc3_output", - "mmc3_sample"; - }; - - ts_clk: clk@01c20098 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20098 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ts"; - }; - - ss_clk: clk@01c2009c { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c2009c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ss"; - }; - - spi0_clk: clk@01c200a0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a0 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi0"; - }; - - spi1_clk: clk@01c200a4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a4 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi1"; - }; - - spi2_clk: clk@01c200a8 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a8 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi2"; - }; - - pata_clk: clk@01c200ac { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200ac 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "pata"; - }; - - ir0_clk: clk@01c200b0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200b0 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ir0"; - }; - - ir1_clk: clk@01c200b4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200b4 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ir1"; - }; - - i2s0_clk: clk@01c200b8 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod1-clk"; - reg = <0x01c200b8 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_8X>, - <&pll2 SUN4I_A10_PLL2_4X>, - <&pll2 SUN4I_A10_PLL2_2X>, - <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "i2s0"; - }; - - ac97_clk: clk@01c200bc { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod1-clk"; - reg = <0x01c200bc 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_8X>, - <&pll2 SUN4I_A10_PLL2_4X>, - <&pll2 SUN4I_A10_PLL2_2X>, - <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "ac97"; - }; - - spdif_clk: clk@01c200c0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod1-clk"; - reg = <0x01c200c0 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_8X>, - <&pll2 SUN4I_A10_PLL2_4X>, - <&pll2 SUN4I_A10_PLL2_2X>, - <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "spdif"; - }; - - keypad_clk: clk@01c200c4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200c4 0x4>; - clocks = <&osc24M>; - clock-output-names = "keypad"; - }; - - usb_clk: clk@01c200cc { - #clock-cells = <1>; - #reset-cells = <1>; - compatible = "allwinner,sun4i-a10-usb-clk"; - reg = <0x01c200cc 0x4>; - clocks = <&pll6 1>; - clock-output-names = "usb_ohci0", "usb_ohci1", - "usb_phy"; - }; - - spi3_clk: clk@01c200d4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200d4 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi3"; - }; - - i2s1_clk: clk@01c200d8 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod1-clk"; - reg = <0x01c200d8 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_8X>, - <&pll2 SUN4I_A10_PLL2_4X>, - <&pll2 SUN4I_A10_PLL2_2X>, - <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "i2s1"; - }; - - i2s2_clk: clk@01c200dc { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod1-clk"; - reg = <0x01c200dc 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_8X>, - <&pll2 SUN4I_A10_PLL2_4X>, - <&pll2 SUN4I_A10_PLL2_2X>, - <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "i2s2"; - }; - - dram_gates: clk@01c20100 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-dram-gates-clk"; - reg = <0x01c20100 0x4>; - clocks = <&pll5 0>; - clock-indices = <0>, - <1>, <2>, - <3>, - <4>, - <5>, <6>, - <15>, - <24>, <25>, - <26>, <27>, - <28>, <29>; - clock-output-names = "dram_ve", - "dram_csi0", "dram_csi1", - "dram_ts", - "dram_tvd", - "dram_tve0", "dram_tve1", - "dram_output", - "dram_de_fe1", "dram_de_fe0", - "dram_de_be0", "dram_de_be1", - "dram_de_mp", "dram_ace"; - }; - - de_be0_clk: clk@01c20104 { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c20104 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-be0"; - }; - - de_be1_clk: clk@01c20108 { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c20108 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-be1"; - }; - - de_fe0_clk: clk@01c2010c { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c2010c 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-fe0"; - }; - - de_fe1_clk: clk@01c20110 { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-display-clk"; - reg = <0x01c20110 0x4>; - clocks = <&pll3>, <&pll7>, <&pll5 1>; - clock-output-names = "de-fe1"; - }; - - tcon0_ch0_clk: clk@01c20118 { - #clock-cells = <0>; - #reset-cells = <1>; - compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; - reg = <0x01c20118 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon0-ch0-sclk"; - - }; - - tcon1_ch0_clk: clk@01c2011c { - #clock-cells = <0>; - #reset-cells = <1>; - compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; - reg = <0x01c2011c 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon1-ch0-sclk"; - - }; - - tcon0_ch1_clk: clk@01c2012c { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; - reg = <0x01c2012c 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon0-ch1-sclk"; - - }; - - tcon1_ch1_clk: clk@01c20130 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; - reg = <0x01c20130 0x4>; - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; - clock-output-names = "tcon1-ch1-sclk"; - - }; - - ve_clk: clk@01c2013c { - #clock-cells = <0>; - #reset-cells = <0>; - compatible = "allwinner,sun4i-a10-ve-clk"; - reg = <0x01c2013c 0x4>; - clocks = <&pll4>; - clock-output-names = "ve"; - }; - - codec_clk: clk@01c20140 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-codec-clk"; - reg = <0x01c20140 0x4>; - clocks = <&pll2 SUN4I_A10_PLL2_1X>; - clock-output-names = "codec"; - }; - - mbus_clk: clk@01c2015c { - #clock-cells = <0>; - compatible = "allwinner,sun5i-a13-mbus-clk"; - reg = <0x01c2015c 0x4>; - clocks = <&osc24M>, <&pll6 2>, <&pll5 1>; - clock-output-names = "mbus"; - }; - /* * The following two are dummy clocks, placeholders * used in the gmac_tx clock. The gmac driver will @@ -737,71 +203,50 @@ * The actual TX clock rate is not controlled by the * gmac_tx clock. */ - mii_phy_tx_clk: clk@2 { + mii_phy_tx_clk: clk@1 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <25000000>; clock-output-names = "mii_phy_tx"; }; - gmac_int_tx_clk: clk@3 { + gmac_int_tx_clk: clk@2 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <125000000>; clock-output-names = "gmac_int_tx"; }; - gmac_tx_clk: clk@01c20164 { + gmac_tx_clk: clk@1c20164 { #clock-cells = <0>; compatible = "allwinner,sun7i-a20-gmac-clk"; reg = <0x01c20164 0x4>; clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; clock-output-names = "gmac_tx"; }; + }; - /* - * Dummy clock used by output clocks - */ - osc24M_32k: clk@1 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <750>; - clock-mult = <1>; - clocks = <&osc24M>; - clock-output-names = "osc24M_32k"; - }; - - clk_out_a: clk@01c201f0 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-out-clk"; - reg = <0x01c201f0 0x4>; - clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; - clock-output-names = "clk_out_a"; - }; - clk_out_b: clk@01c201f4 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-out-clk"; - reg = <0x01c201f4 0x4>; - clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; - clock-output-names = "clk_out_b"; - }; + de: display-engine { + compatible = "allwinner,sun7i-a20-display-engine"; + allwinner,pipelines = <&fe0>, <&fe1>; + status = "disabled"; }; - soc@01c00000 { + soc@1c00000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; - sram-controller@01c00000 { + sram-controller@1c00000 { compatible = "allwinner,sun4i-a10-sram-controller"; reg = <0x01c00000 0x30>; #address-cells = <1>; #size-cells = <1>; ranges; - sram_a: sram@00000000 { + sram_a: sram@0 { compatible = "mmio-sram"; reg = <0x00000000 0xc000>; #address-cells = <1>; @@ -815,14 +260,14 @@ }; }; - sram_d: sram@00010000 { + sram_d: sram@10000 { compatible = "mmio-sram"; reg = <0x00010000 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x00010000 0x1000>; - otg_sram: sram-section@0000 { + otg_sram: sram-section@0 { compatible = "allwinner,sun4i-a10-sram-d"; reg = <0x0000 0x1000>; status = "disabled"; @@ -830,7 +275,7 @@ }; }; - nmi_intc: interrupt-controller@01c00030 { + nmi_intc: interrupt-controller@1c00030 { compatible = "allwinner,sun7i-a20-sc-nmi"; interrupt-controller; #interrupt-cells = <2>; @@ -838,19 +283,19 @@ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; }; - dma: dma-controller@01c02000 { + dma: dma-controller@1c02000 { compatible = "allwinner,sun4i-a10-dma"; reg = <0x01c02000 0x1000>; interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb_gates 6>; + clocks = <&ccu CLK_AHB_DMA>; #dma-cells = <2>; }; - nfc: nand@01c03000 { + nfc: nand@1c03000 { compatible = "allwinner,sun4i-a10-nand"; reg = <0x01c03000 0x1000>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb_gates 13>, <&nand_clk>; + clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 3>; dma-names = "rxtx"; @@ -859,11 +304,11 @@ #size-cells = <0>; }; - spi0: spi@01c05000 { + spi0: spi@1c05000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c05000 0x1000>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb_gates 20>, <&spi0_clk>; + clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 27>, <&dma SUN4I_DMA_DEDICATED 26>; @@ -871,13 +316,14 @@ status = "disabled"; #address-cells = <1>; #size-cells = <0>; + num-cs = <4>; }; - spi1: spi@01c06000 { + spi1: spi@1c06000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c06000 0x1000>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb_gates 21>, <&spi1_clk>; + clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 9>, <&dma SUN4I_DMA_DEDICATED 8>; @@ -885,18 +331,19 @@ status = "disabled"; #address-cells = <1>; #size-cells = <0>; + num-cs = <1>; }; - emac: ethernet@01c0b000 { + emac: ethernet@1c0b000 { compatible = "allwinner,sun4i-a10-emac"; reg = <0x01c0b000 0x1000>; interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb_gates 17>; + clocks = <&ccu CLK_AHB_EMAC>; allwinner,sram = <&emac_sram 1>; status = "disabled"; }; - mdio: mdio@01c0b080 { + mdio: mdio@1c0b080 { compatible = "allwinner,sun4i-a10-mdio"; reg = <0x01c0b080 0x14>; status = "disabled"; @@ -904,14 +351,111 @@ #size-cells = <0>; }; - mmc0: mmc@01c0f000 { - compatible = "allwinner,sun7i-a20-mmc", - "allwinner,sun5i-a13-mmc"; + tcon0: lcd-controller@1c0c000 { + compatible = "allwinner,sun7i-a20-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + resets = <&ccu RST_TCON0>; + reset-names = "lcd"; + clocks = <&ccu CLK_AHB_LCD0>, + <&ccu CLK_TCON0_CH0>, + <&ccu CLK_TCON0_CH1>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1"; + clock-output-names = "tcon0-pixel-clock"; + dmas = <&dma SUN4I_DMA_DEDICATED 14>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon0_in_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_out_tcon0>; + }; + + tcon0_in_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon0_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_tcon0>; + allwinner,tcon-channel = <1>; + }; + }; + }; + }; + + tcon1: lcd-controller@1c0d000 { + compatible = "allwinner,sun7i-a20-tcon"; + reg = <0x01c0d000 0x1000>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + resets = <&ccu RST_TCON1>; + reset-names = "lcd"; + clocks = <&ccu CLK_AHB_LCD1>, + <&ccu CLK_TCON1_CH0>, + <&ccu CLK_TCON1_CH1>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1"; + clock-output-names = "tcon1-pixel-clock"; + dmas = <&dma SUN4I_DMA_DEDICATED 15>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon1_in_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_out_tcon1>; + }; + + tcon1_in_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_out_tcon1>; + }; + }; + + tcon1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon1_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_tcon1>; + allwinner,tcon-channel = <1>; + }; + }; + }; + }; + + mmc0: mmc@1c0f000 { + compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; - clocks = <&ahb_gates 8>, - <&mmc0_clk 0>, - <&mmc0_clk 1>, - <&mmc0_clk 2>; + clocks = <&ccu CLK_AHB_MMC0>, + <&ccu CLK_MMC0>, + <&ccu CLK_MMC0_OUTPUT>, + <&ccu CLK_MMC0_SAMPLE>; clock-names = "ahb", "mmc", "output", @@ -922,14 +466,13 @@ #size-cells = <0>; }; - mmc1: mmc@01c10000 { - compatible = "allwinner,sun7i-a20-mmc", - "allwinner,sun5i-a13-mmc"; + mmc1: mmc@1c10000 { + compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c10000 0x1000>; - clocks = <&ahb_gates 9>, - <&mmc1_clk 0>, - <&mmc1_clk 1>, - <&mmc1_clk 2>; + clocks = <&ccu CLK_AHB_MMC1>, + <&ccu CLK_MMC1>, + <&ccu CLK_MMC1_OUTPUT>, + <&ccu CLK_MMC1_SAMPLE>; clock-names = "ahb", "mmc", "output", @@ -940,14 +483,13 @@ #size-cells = <0>; }; - mmc2: mmc@01c11000 { - compatible = "allwinner,sun7i-a20-mmc", - "allwinner,sun5i-a13-mmc"; + mmc2: mmc@1c11000 { + compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c11000 0x1000>; - clocks = <&ahb_gates 10>, - <&mmc2_clk 0>, - <&mmc2_clk 1>, - <&mmc2_clk 2>; + clocks = <&ccu CLK_AHB_MMC2>, + <&ccu CLK_MMC2>, + <&ccu CLK_MMC2_OUTPUT>, + <&ccu CLK_MMC2_SAMPLE>; clock-names = "ahb", "mmc", "output", @@ -958,14 +500,13 @@ #size-cells = <0>; }; - mmc3: mmc@01c12000 { - compatible = "allwinner,sun7i-a20-mmc", - "allwinner,sun5i-a13-mmc"; + mmc3: mmc@1c12000 { + compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c12000 0x1000>; - clocks = <&ahb_gates 11>, - <&mmc3_clk 0>, - <&mmc3_clk 1>, - <&mmc3_clk 2>; + clocks = <&ccu CLK_AHB_MMC3>, + <&ccu CLK_MMC3>, + <&ccu CLK_MMC3_OUTPUT>, + <&ccu CLK_MMC3_SAMPLE>; clock-names = "ahb", "mmc", "output", @@ -976,10 +517,10 @@ #size-cells = <0>; }; - usb_otg: usb@01c13000 { + usb_otg: usb@1c13000 { compatible = "allwinner,sun4i-a10-musb"; reg = <0x01c13000 0x0400>; - clocks = <&ahb_gates 0>; + clocks = <&ccu CLK_AHB_OTG>; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "mc"; phys = <&usbphy 0>; @@ -989,51 +530,97 @@ status = "disabled"; }; - usbphy: phy@01c13400 { + usbphy: phy@1c13400 { #phy-cells = <1>; compatible = "allwinner,sun7i-a20-usb-phy"; reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; reg-names = "phy_ctrl", "pmu1", "pmu2"; - clocks = <&usb_clk 8>; + clocks = <&ccu CLK_USB_PHY>; clock-names = "usb_phy"; - resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>, + <&ccu RST_USB_PHY2>; reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; status = "disabled"; }; - ehci0: usb@01c14000 { + ehci0: usb@1c14000 { compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; reg = <0x01c14000 0x100>; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb_gates 1>; + clocks = <&ccu CLK_AHB_EHCI0>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; }; - ohci0: usb@01c14400 { + ohci0: usb@1c14400 { compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; reg = <0x01c14400 0x100>; interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usb_clk 6>, <&ahb_gates 2>; + clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; }; - crypto: crypto-engine@01c15000 { - compatible = "allwinner,sun4i-a10-crypto"; + crypto: crypto-engine@1c15000 { + compatible = "allwinner,sun7i-a20-crypto", + "allwinner,sun4i-a10-crypto"; reg = <0x01c15000 0x1000>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb_gates 5>, <&ss_clk>; + clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>; clock-names = "ahb", "mod"; }; - spi2: spi@01c17000 { + hdmi: hdmi@1c16000 { + compatible = "allwinner,sun7i-a20-hdmi", + "allwinner,sun5i-a10s-hdmi"; + reg = <0x01c16000 0x1000>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>, + <&ccu CLK_PLL_VIDEO0_2X>, + <&ccu CLK_PLL_VIDEO1_2X>; + clock-names = "ahb", "mod", "pll-0", "pll-1"; + dmas = <&dma SUN4I_DMA_NORMAL 16>, + <&dma SUN4I_DMA_NORMAL 16>, + <&dma SUN4I_DMA_DEDICATED 24>; + dma-names = "ddc-tx", "ddc-rx", "audio-tx"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + hdmi_in_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_hdmi>; + }; + + hdmi_in_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + + spi2: spi@1c17000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c17000 0x1000>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb_gates 22>, <&spi2_clk>; + clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 29>, <&dma SUN4I_DMA_DEDICATED 28>; @@ -1041,41 +628,42 @@ status = "disabled"; #address-cells = <1>; #size-cells = <0>; + num-cs = <1>; }; - ahci: sata@01c18000 { + ahci: sata@1c18000 { compatible = "allwinner,sun4i-a10-ahci"; reg = <0x01c18000 0x1000>; interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pll6 0>, <&ahb_gates 25>; + clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>; status = "disabled"; }; - ehci1: usb@01c1c000 { + ehci1: usb@1c1c000 { compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; reg = <0x01c1c000 0x100>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb_gates 3>; + clocks = <&ccu CLK_AHB_EHCI1>; phys = <&usbphy 2>; phy-names = "usb"; status = "disabled"; }; - ohci1: usb@01c1c400 { + ohci1: usb@1c1c400 { compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; reg = <0x01c1c400 0x100>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usb_clk 7>, <&ahb_gates 4>; + clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>; phys = <&usbphy 2>; phy-names = "usb"; status = "disabled"; }; - spi3: spi@01c1f000 { + spi3: spi@1c1f000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c1f000 0x1000>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb_gates 23>, <&spi3_clk>; + clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>; clock-names = "ahb", "mod"; dmas = <&dma SUN4I_DMA_DEDICATED 31>, <&dma SUN4I_DMA_DEDICATED 30>; @@ -1083,319 +671,258 @@ status = "disabled"; #address-cells = <1>; #size-cells = <0>; + num-cs = <1>; }; - pio: pinctrl@01c20800 { + ccu: clock@1c20000 { + compatible = "allwinner,sun7i-a20-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pio: pinctrl@1c20800 { compatible = "allwinner,sun7i-a20-pinctrl"; reg = <0x01c20800 0x400>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 5>; + clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; #interrupt-cells = <3>; #gpio-cells = <3>; + can0_pins_a: can0@0 { + pins = "PH20", "PH21"; + function = "can"; + }; + clk_out_a_pins_a: clk_out_a@0 { - allwinner,pins = "PI12"; - allwinner,function = "clk_out_a"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PI12"; + function = "clk_out_a"; }; clk_out_b_pins_a: clk_out_b@0 { - allwinner,pins = "PI13"; - allwinner,function = "clk_out_b"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PI13"; + function = "clk_out_b"; }; emac_pins_a: emac0@0 { - allwinner,pins = "PA0", "PA1", "PA2", - "PA3", "PA4", "PA5", "PA6", - "PA7", "PA8", "PA9", "PA10", - "PA11", "PA12", "PA13", "PA14", - "PA15", "PA16"; - allwinner,function = "emac"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PA0", "PA1", "PA2", + "PA3", "PA4", "PA5", "PA6", + "PA7", "PA8", "PA9", "PA10", + "PA11", "PA12", "PA13", "PA14", + "PA15", "PA16"; + function = "emac"; }; gmac_pins_mii_a: gmac_mii@0 { - allwinner,pins = "PA0", "PA1", "PA2", - "PA3", "PA4", "PA5", "PA6", - "PA7", "PA8", "PA9", "PA10", - "PA11", "PA12", "PA13", "PA14", - "PA15", "PA16"; - allwinner,function = "gmac"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PA0", "PA1", "PA2", + "PA3", "PA4", "PA5", "PA6", + "PA7", "PA8", "PA9", "PA10", + "PA11", "PA12", "PA13", "PA14", + "PA15", "PA16"; + function = "gmac"; }; gmac_pins_rgmii_a: gmac_rgmii@0 { - allwinner,pins = "PA0", "PA1", "PA2", - "PA3", "PA4", "PA5", "PA6", - "PA7", "PA8", "PA10", - "PA11", "PA12", "PA13", - "PA15", "PA16"; - allwinner,function = "gmac"; + pins = "PA0", "PA1", "PA2", + "PA3", "PA4", "PA5", "PA6", + "PA7", "PA8", "PA10", + "PA11", "PA12", "PA13", + "PA15", "PA16"; + function = "gmac"; /* * data lines in RGMII mode use DDR mode * and need a higher signal drive strength */ - allwinner,drive = <SUN4I_PINCTRL_40_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + drive-strength = <40>; }; i2c0_pins_a: i2c0@0 { - allwinner,pins = "PB0", "PB1"; - allwinner,function = "i2c0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PB0", "PB1"; + function = "i2c0"; }; i2c1_pins_a: i2c1@0 { - allwinner,pins = "PB18", "PB19"; - allwinner,function = "i2c1"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PB18", "PB19"; + function = "i2c1"; }; i2c2_pins_a: i2c2@0 { - allwinner,pins = "PB20", "PB21"; - allwinner,function = "i2c2"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PB20", "PB21"; + function = "i2c2"; }; i2c3_pins_a: i2c3@0 { - allwinner,pins = "PI0", "PI1"; - allwinner,function = "i2c3"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PI0", "PI1"; + function = "i2c3"; }; ir0_rx_pins_a: ir0@0 { - allwinner,pins = "PB4"; - allwinner,function = "ir0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PB4"; + function = "ir0"; }; ir0_tx_pins_a: ir0@1 { - allwinner,pins = "PB3"; - allwinner,function = "ir0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PB3"; + function = "ir0"; }; ir1_rx_pins_a: ir1@0 { - allwinner,pins = "PB23"; - allwinner,function = "ir1"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PB23"; + function = "ir1"; }; ir1_tx_pins_a: ir1@1 { - allwinner,pins = "PB22"; - allwinner,function = "ir1"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PB22"; + function = "ir1"; }; mmc0_pins_a: mmc0@0 { - allwinner,pins = "PF0", "PF1", "PF2", - "PF3", "PF4", "PF5"; - allwinner,function = "mmc0"; - allwinner,drive = <SUN4I_PINCTRL_30_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { - allwinner,pins = "PH1"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PF0", "PF1", "PF2", + "PF3", "PF4", "PF5"; + function = "mmc0"; + drive-strength = <30>; + bias-pull-up; }; mmc2_pins_a: mmc2@0 { - allwinner,pins = "PC6", "PC7", "PC8", - "PC9", "PC10", "PC11"; - allwinner,function = "mmc2"; - allwinner,drive = <SUN4I_PINCTRL_30_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PC6", "PC7", "PC8", + "PC9", "PC10", "PC11"; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; }; mmc3_pins_a: mmc3@0 { - allwinner,pins = "PI4", "PI5", "PI6", - "PI7", "PI8", "PI9"; - allwinner,function = "mmc3"; - allwinner,drive = <SUN4I_PINCTRL_30_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PI4", "PI5", "PI6", + "PI7", "PI8", "PI9"; + function = "mmc3"; + drive-strength = <30>; + bias-pull-up; }; ps20_pins_a: ps20@0 { - allwinner,pins = "PI20", "PI21"; - allwinner,function = "ps2"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PI20", "PI21"; + function = "ps2"; }; ps21_pins_a: ps21@0 { - allwinner,pins = "PH12", "PH13"; - allwinner,function = "ps2"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH12", "PH13"; + function = "ps2"; }; pwm0_pins_a: pwm0@0 { - allwinner,pins = "PB2"; - allwinner,function = "pwm"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PB2"; + function = "pwm"; }; pwm1_pins_a: pwm1@0 { - allwinner,pins = "PI3"; - allwinner,function = "pwm"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PI3"; + function = "pwm"; }; spdif_tx_pins_a: spdif@0 { - allwinner,pins = "PB13"; - allwinner,function = "spdif"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PB13"; + function = "spdif"; + bias-pull-up; }; spi0_pins_a: spi0@0 { - allwinner,pins = "PI11", "PI12", "PI13"; - allwinner,function = "spi0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PI11", "PI12", "PI13"; + function = "spi0"; }; spi0_cs0_pins_a: spi0_cs0@0 { - allwinner,pins = "PI10"; - allwinner,function = "spi0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PI10"; + function = "spi0"; }; spi0_cs1_pins_a: spi0_cs1@0 { - allwinner,pins = "PI14"; - allwinner,function = "spi0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PI14"; + function = "spi0"; }; spi1_pins_a: spi1@0 { - allwinner,pins = "PI17", "PI18", "PI19"; - allwinner,function = "spi1"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PI17", "PI18", "PI19"; + function = "spi1"; }; spi1_cs0_pins_a: spi1_cs0@0 { - allwinner,pins = "PI16"; - allwinner,function = "spi1"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PI16"; + function = "spi1"; }; spi2_pins_a: spi2@0 { - allwinner,pins = "PC20", "PC21", "PC22"; - allwinner,function = "spi2"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PC20", "PC21", "PC22"; + function = "spi2"; }; spi2_pins_b: spi2@1 { - allwinner,pins = "PB15", "PB16", "PB17"; - allwinner,function = "spi2"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PB15", "PB16", "PB17"; + function = "spi2"; }; spi2_cs0_pins_a: spi2_cs0@0 { - allwinner,pins = "PC19"; - allwinner,function = "spi2"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PC19"; + function = "spi2"; }; spi2_cs0_pins_b: spi2_cs0@1 { - allwinner,pins = "PB14"; - allwinner,function = "spi2"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PB14"; + function = "spi2"; }; uart0_pins_a: uart0@0 { - allwinner,pins = "PB22", "PB23"; - allwinner,function = "uart0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PB22", "PB23"; + function = "uart0"; }; uart2_pins_a: uart2@0 { - allwinner,pins = "PI16", "PI17", "PI18", "PI19"; - allwinner,function = "uart2"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PI16", "PI17", "PI18", "PI19"; + function = "uart2"; }; uart3_pins_a: uart3@0 { - allwinner,pins = "PG6", "PG7", "PG8", "PG9"; - allwinner,function = "uart3"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PG6", "PG7", "PG8", "PG9"; + function = "uart3"; }; uart3_pins_b: uart3@1 { - allwinner,pins = "PH0", "PH1"; - allwinner,function = "uart3"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH0", "PH1"; + function = "uart3"; }; uart4_pins_a: uart4@0 { - allwinner,pins = "PG10", "PG11"; - allwinner,function = "uart4"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PG10", "PG11"; + function = "uart4"; }; uart4_pins_b: uart4@1 { - allwinner,pins = "PH4", "PH5"; - allwinner,function = "uart4"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH4", "PH5"; + function = "uart4"; }; uart5_pins_a: uart5@0 { - allwinner,pins = "PI10", "PI11"; - allwinner,function = "uart5"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PI10", "PI11"; + function = "uart5"; }; uart6_pins_a: uart6@0 { - allwinner,pins = "PI12", "PI13"; - allwinner,function = "uart6"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PI12", "PI13"; + function = "uart6"; }; uart7_pins_a: uart7@0 { - allwinner,pins = "PI20", "PI21"; - allwinner,function = "uart7"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PI20", "PI21"; + function = "uart7"; }; }; - timer@01c20c00 { + timer@1c20c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0x90>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, @@ -1407,18 +934,18 @@ clocks = <&osc24M>; }; - wdt: watchdog@01c20c90 { + wdt: watchdog@1c20c90 { compatible = "allwinner,sun4i-a10-wdt"; reg = <0x01c20c90 0x10>; }; - rtc: rtc@01c20d00 { + rtc: rtc@1c20d00 { compatible = "allwinner,sun7i-a20-rtc"; reg = <0x01c20d00 0x20>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; }; - pwm: pwm@01c20e00 { + pwm: pwm@1c20e00 { compatible = "allwinner,sun7i-a20-pwm"; reg = <0x01c20e00 0xc>; clocks = <&osc24M>; @@ -1426,12 +953,12 @@ status = "disabled"; }; - spdif: spdif@01c21000 { + spdif: spdif@1c21000 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-spdif"; reg = <0x01c21000 0x400>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 1>, <&spdif_clk>; + clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>; clock-names = "apb", "spdif"; dmas = <&dma SUN4I_DMA_NORMAL 2>, <&dma SUN4I_DMA_NORMAL 2>; @@ -1439,30 +966,30 @@ status = "disabled"; }; - ir0: ir@01c21800 { + ir0: ir@1c21800 { compatible = "allwinner,sun4i-a10-ir"; - clocks = <&apb0_gates 6>, <&ir0_clk>; + clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>; clock-names = "apb", "ir"; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; reg = <0x01c21800 0x40>; status = "disabled"; }; - ir1: ir@01c21c00 { + ir1: ir@1c21c00 { compatible = "allwinner,sun4i-a10-ir"; - clocks = <&apb0_gates 7>, <&ir1_clk>; + clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>; clock-names = "apb", "ir"; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; reg = <0x01c21c00 0x40>; status = "disabled"; }; - i2s1: i2s@01c22000 { + i2s1: i2s@1c22000 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-i2s"; reg = <0x01c22000 0x400>; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 4>, <&i2s1_clk>; + clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>; clock-names = "apb", "mod"; dmas = <&dma SUN4I_DMA_NORMAL 4>, <&dma SUN4I_DMA_NORMAL 4>; @@ -1470,12 +997,12 @@ status = "disabled"; }; - i2s0: i2s@01c22400 { + i2s0: i2s@1c22400 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-i2s"; reg = <0x01c22400 0x400>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 3>, <&i2s0_clk>; + clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>; clock-names = "apb", "mod"; dmas = <&dma SUN4I_DMA_NORMAL 3>, <&dma SUN4I_DMA_NORMAL 3>; @@ -1483,19 +1010,19 @@ status = "disabled"; }; - lradc: lradc@01c22800 { + lradc: lradc@1c22800 { compatible = "allwinner,sun4i-a10-lradc-keys"; reg = <0x01c22800 0x100>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; - codec: codec@01c22c00 { + codec: codec@1c22c00 { #sound-dai-cells = <0>; compatible = "allwinner,sun7i-a20-codec"; reg = <0x01c22c00 0x40>; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 0>, <&codec_clk>; + clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>; clock-names = "apb", "codec"; dmas = <&dma SUN4I_DMA_NORMAL 19>, <&dma SUN4I_DMA_NORMAL 19>; @@ -1503,17 +1030,17 @@ status = "disabled"; }; - sid: eeprom@01c23800 { + sid: eeprom@1c23800 { compatible = "allwinner,sun7i-a20-sid"; reg = <0x01c23800 0x200>; }; - i2s2: i2s@01c24400 { + i2s2: i2s@1c24400 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-i2s"; reg = <0x01c24400 0x400>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 8>, <&i2s2_clk>; + clocks = <&ccu CLK_APB0_I2S2>, <&ccu CLK_I2S2>; clock-names = "apb", "mod"; dmas = <&dma SUN4I_DMA_NORMAL 6>, <&dma SUN4I_DMA_NORMAL 6>; @@ -1521,154 +1048,204 @@ status = "disabled"; }; - rtp: rtp@01c25000 { + rtp: rtp@1c25000 { compatible = "allwinner,sun5i-a13-ts"; reg = <0x01c25000 0x100>; interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; #thermal-sensor-cells = <0>; }; - uart0: serial@01c28000 { + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 16>; + clocks = <&ccu CLK_APB1_UART0>; status = "disabled"; }; - uart1: serial@01c28400 { + uart1: serial@1c28400 { compatible = "snps,dw-apb-uart"; reg = <0x01c28400 0x400>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 17>; + clocks = <&ccu CLK_APB1_UART1>; status = "disabled"; }; - uart2: serial@01c28800 { + uart2: serial@1c28800 { compatible = "snps,dw-apb-uart"; reg = <0x01c28800 0x400>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 18>; + clocks = <&ccu CLK_APB1_UART2>; status = "disabled"; }; - uart3: serial@01c28c00 { + uart3: serial@1c28c00 { compatible = "snps,dw-apb-uart"; reg = <0x01c28c00 0x400>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 19>; + clocks = <&ccu CLK_APB1_UART3>; status = "disabled"; }; - uart4: serial@01c29000 { + uart4: serial@1c29000 { compatible = "snps,dw-apb-uart"; reg = <0x01c29000 0x400>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 20>; + clocks = <&ccu CLK_APB1_UART4>; status = "disabled"; }; - uart5: serial@01c29400 { + uart5: serial@1c29400 { compatible = "snps,dw-apb-uart"; reg = <0x01c29400 0x400>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 21>; + clocks = <&ccu CLK_APB1_UART5>; status = "disabled"; }; - uart6: serial@01c29800 { + uart6: serial@1c29800 { compatible = "snps,dw-apb-uart"; reg = <0x01c29800 0x400>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 22>; + clocks = <&ccu CLK_APB1_UART6>; status = "disabled"; }; - uart7: serial@01c29c00 { + uart7: serial@1c29c00 { compatible = "snps,dw-apb-uart"; reg = <0x01c29c00 0x400>; interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 23>; + clocks = <&ccu CLK_APB1_UART7>; status = "disabled"; }; - i2c0: i2c@01c2ac00 { + ps20: ps2@1c2a000 { + compatible = "allwinner,sun4i-a10-ps2"; + reg = <0x01c2a000 0x400>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_APB1_PS20>; + status = "disabled"; + }; + + ps21: ps2@1c2a400 { + compatible = "allwinner,sun4i-a10-ps2"; + reg = <0x01c2a400 0x400>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_APB1_PS21>; + status = "disabled"; + }; + + i2c0: i2c@1c2ac00 { compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2ac00 0x400>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb1_gates 0>; + clocks = <&ccu CLK_APB1_I2C0>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - i2c1: i2c@01c2b000 { + i2c1: i2c@1c2b000 { compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2b000 0x400>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb1_gates 1>; + clocks = <&ccu CLK_APB1_I2C1>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - i2c2: i2c@01c2b400 { + i2c2: i2c@1c2b400 { compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2b400 0x400>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb1_gates 2>; + clocks = <&ccu CLK_APB1_I2C2>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - i2c3: i2c@01c2b800 { + i2c3: i2c@1c2b800 { compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2b800 0x400>; interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb1_gates 3>; + clocks = <&ccu CLK_APB1_I2C3>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - i2c4: i2c@01c2c000 { + can0: can@1c2bc00 { + compatible = "allwinner,sun7i-a20-can", + "allwinner,sun4i-a10-can"; + reg = <0x01c2bc00 0x400>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_APB1_CAN>; + status = "disabled"; + }; + + i2c4: i2c@1c2c000 { compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2c000 0x400>; interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb1_gates 15>; + clocks = <&ccu CLK_APB1_I2C4>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - gmac: ethernet@01c50000 { + mali: gpu@1c40000 { + compatible = "allwinner,sun7i-a20-mali", "arm,mali-400"; + reg = <0x01c40000 0x10000>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pmu"; + clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>; + clock-names = "bus", "core"; + resets = <&ccu RST_GPU>; + + assigned-clocks = <&ccu CLK_GPU>; + assigned-clock-rates = <384000000>; + }; + + gmac: ethernet@1c50000 { compatible = "allwinner,sun7i-a20-gmac"; reg = <0x01c50000 0x10000>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; - clocks = <&ahb_gates 49>, <&gmac_tx_clk>; + clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>; clock-names = "stmmaceth", "allwinner_gmac_tx"; snps,pbl = <2>; snps,fixed-burst; @@ -1678,20 +1255,20 @@ #size-cells = <0>; }; - hstimer@01c60000 { + hstimer@1c60000 { compatible = "allwinner,sun7i-a20-hstimer"; reg = <0x01c60000 0x1000>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb_gates 28>; + clocks = <&ccu CLK_AHB_HSTIMER>; }; - gic: interrupt-controller@01c81000 { - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + gic: interrupt-controller@1c81000 { + compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, - <0x01c82000 0x1000>, + <0x01c82000 0x2000>, <0x01c84000 0x2000>, <0x01c86000 0x2000>; interrupt-controller; @@ -1699,20 +1276,164 @@ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; - ps20: ps2@01c2a000 { - compatible = "allwinner,sun4i-a10-ps2"; - reg = <0x01c2a000 0x400>; - interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb1_gates 6>; - status = "disabled"; + fe0: display-frontend@1e00000 { + compatible = "allwinner,sun7i-a20-display-frontend"; + reg = <0x01e00000 0x20000>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>, + <&ccu CLK_DRAM_DE_FE0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_FE0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe0_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe0>; + }; + + fe0_out_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_in_fe0>; + }; + }; + }; }; - ps21: ps2@01c2a400 { - compatible = "allwinner,sun4i-a10-ps2"; - reg = <0x01c2a400 0x400>; - interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb1_gates 7>; - status = "disabled"; + fe1: display-frontend@1e20000 { + compatible = "allwinner,sun7i-a20-display-frontend"; + reg = <0x01e20000 0x20000>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>, + <&ccu CLK_DRAM_DE_FE1>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_FE1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe1_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe1>; + }; + + fe1_out_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_in_fe1>; + }; + }; + }; + }; + + be1: display-backend@1e40000 { + compatible = "allwinner,sun7i-a20-display-backend"; + reg = <0x01e40000 0x10000>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>, + <&ccu CLK_DRAM_DE_BE1>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_BE1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be1_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be1>; + }; + + be1_in_fe1: endpoint@1 { + reg = <1>; + remote-endpoint = <&fe1_out_be1>; + }; + }; + + be1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be1_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_be1>; + }; + + be1_out_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_in_be1>; + }; + }; + }; + }; + + be0: display-backend@1e60000 { + compatible = "allwinner,sun7i-a20-display-backend"; + reg = <0x01e60000 0x10000>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, + <&ccu CLK_DRAM_DE_BE0>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_DE_BE0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be0_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be0>; + }; + + be0_in_fe1: endpoint@1 { + reg = <1>; + remote-endpoint = <&fe1_out_be0>; + }; + }; + + be0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_be0>; + }; + + be0_out_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_in_be0>; + }; + }; + }; }; }; }; diff --git a/arch/arm/dts/sun8i-a23-a33.dtsi b/arch/arm/dts/sun8i-a23-a33.dtsi index ffd21487dc..44f3cad3de 100644 --- a/arch/arm/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/dts/sun8i-a23-a33.dtsi @@ -118,13 +118,13 @@ }; }; - soc@01c00000 { + soc@1c00000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; - dma: dma-controller@01c02000 { + dma: dma-controller@1c02000 { compatible = "allwinner,sun8i-a23-dma"; reg = <0x01c02000 0x1000>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; @@ -133,7 +133,7 @@ #dma-cells = <1>; }; - mmc0: mmc@01c0f000 { + mmc0: mmc@1c0f000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; clocks = <&ccu CLK_BUS_MMC0>, @@ -152,7 +152,7 @@ #size-cells = <0>; }; - mmc1: mmc@01c10000 { + mmc1: mmc@1c10000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c10000 0x1000>; clocks = <&ccu CLK_BUS_MMC1>, @@ -171,7 +171,7 @@ #size-cells = <0>; }; - mmc2: mmc@01c11000 { + mmc2: mmc@1c11000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c11000 0x1000>; clocks = <&ccu CLK_BUS_MMC2>, @@ -190,7 +190,7 @@ #size-cells = <0>; }; - nfc: nand@01c03000 { + nfc: nand@1c03000 { compatible = "allwinner,sun4i-a10-nand"; reg = <0x01c03000 0x1000>; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; @@ -198,12 +198,14 @@ clock-names = "ahb", "mod"; resets = <&ccu RST_BUS_NAND>; reset-names = "ahb"; + pinctrl-names = "default"; + pinctrl-0 = <&nand_pins &nand_pins_cs0 &nand_pins_rb0>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - usb_otg: usb@01c19000 { + usb_otg: usb@1c19000 { /* compatible gets set in SoC specific dtsi file */ reg = <0x01c19000 0x0400>; clocks = <&ccu CLK_BUS_OTG>; @@ -216,7 +218,7 @@ status = "disabled"; }; - usbphy: phy@01c19400 { + usbphy: phy@1c19400 { /* * compatible and address regions get set in * SoC specific dtsi file @@ -233,7 +235,7 @@ #phy-cells = <1>; }; - ehci0: usb@01c1a000 { + ehci0: usb@1c1a000 { compatible = "allwinner,sun8i-a23-ehci", "generic-ehci"; reg = <0x01c1a000 0x100>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; @@ -244,7 +246,7 @@ status = "disabled"; }; - ohci0: usb@01c1a400 { + ohci0: usb@1c1a400 { compatible = "allwinner,sun8i-a23-ohci", "generic-ohci"; reg = <0x01c1a400 0x100>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; @@ -255,7 +257,7 @@ status = "disabled"; }; - ccu: clock@01c20000 { + ccu: clock@1c20000 { reg = <0x01c20000 0x400>; clocks = <&osc24M>, <&rtc 0>; clock-names = "hosc", "losc"; @@ -263,7 +265,7 @@ #reset-cells = <1>; }; - pio: pinctrl@01c20800 { + pio: pinctrl@1c20800 { /* compatible gets set in SoC specific dtsi file */ reg = <0x01c20800 0x400>; /* interrupts get set in SoC specific dtsi file */ @@ -289,23 +291,6 @@ function = "uart1"; }; - nand_pins_a: nand-base0@0 { - pins = "PC0", "PC1", "PC2", "PC5", - "PC8", "PC9", "PC10", "PC11", - "PC12", "PC13", "PC14", "PC15"; - function = "nand0"; - }; - - nand_cs0_pins_a: nand-cs@0 { - pins = "PC4"; - function = "nand0"; - }; - - nand_rb0_pins_a: nand-rb@0 { - pins = "PC6"; - function = "nand0"; - }; - mmc0_pins_a: mmc0@0 { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; @@ -332,6 +317,37 @@ bias-pull-up; }; + nand_pins: nand-pins { + pins = "PC0", "PC1", "PC2", "PC5", + "PC8", "PC9", "PC10", "PC11", + "PC12", "PC13", "PC14", "PC15"; + function = "nand0"; + }; + + nand_pins_cs0: nand-pins-cs0 { + pins = "PC4"; + function = "nand0"; + bias-pull-up; + }; + + nand_pins_cs1: nand-pins-cs1 { + pins = "PC3"; + function = "nand0"; + bias-pull-up; + }; + + nand_pins_rb0: nand-pins-rb0 { + pins = "PC6"; + function = "nand0"; + bias-pull-up; + }; + + nand_pins_rb1: nand-pins-rb1 { + pins = "PC7"; + function = "nand0"; + bias-pull-up; + }; + pwm0_pins: pwm0 { pins = "PH0"; function = "pwm0"; @@ -361,7 +377,7 @@ }; }; - timer@01c20c00 { + timer@1c20c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0xa0>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, @@ -369,13 +385,13 @@ clocks = <&osc24M>; }; - wdt0: watchdog@01c20ca0 { + wdt0: watchdog@1c20ca0 { compatible = "allwinner,sun6i-a31-wdt"; reg = <0x01c20ca0 0x20>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; }; - pwm: pwm@01c21400 { + pwm: pwm@1c21400 { compatible = "allwinner,sun7i-a20-pwm"; reg = <0x01c21400 0xc>; clocks = <&osc24M>; @@ -383,14 +399,14 @@ status = "disabled"; }; - lradc: lradc@01c22800 { + lradc: lradc@1c22800 { compatible = "allwinner,sun4i-a10-lradc-keys"; reg = <0x01c22800 0x100>; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; - uart0: serial@01c28000 { + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; @@ -403,7 +419,7 @@ status = "disabled"; }; - uart1: serial@01c28400 { + uart1: serial@1c28400 { compatible = "snps,dw-apb-uart"; reg = <0x01c28400 0x400>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; @@ -416,7 +432,7 @@ status = "disabled"; }; - uart2: serial@01c28800 { + uart2: serial@1c28800 { compatible = "snps,dw-apb-uart"; reg = <0x01c28800 0x400>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; @@ -429,7 +445,7 @@ status = "disabled"; }; - uart3: serial@01c28c00 { + uart3: serial@1c28c00 { compatible = "snps,dw-apb-uart"; reg = <0x01c28c00 0x400>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; @@ -442,7 +458,7 @@ status = "disabled"; }; - uart4: serial@01c29000 { + uart4: serial@1c29000 { compatible = "snps,dw-apb-uart"; reg = <0x01c29000 0x400>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; @@ -455,7 +471,7 @@ status = "disabled"; }; - i2c0: i2c@01c2ac00 { + i2c0: i2c@1c2ac00 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2ac00 0x400>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; @@ -466,7 +482,7 @@ #size-cells = <0>; }; - i2c1: i2c@01c2b000 { + i2c1: i2c@1c2b000 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b000 0x400>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; @@ -477,7 +493,7 @@ #size-cells = <0>; }; - i2c2: i2c@01c2b400 { + i2c2: i2c@1c2b400 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b400 0x400>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; @@ -515,7 +531,7 @@ assigned-clock-rates = <384000000>; }; - gic: interrupt-controller@01c81000 { + gic: interrupt-controller@1c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, <0x01c82000 0x2000>, @@ -526,7 +542,7 @@ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; - rtc: rtc@01f00000 { + rtc: rtc@1f00000 { compatible = "allwinner,sun6i-a31-rtc"; reg = <0x01f00000 0x54>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, @@ -544,7 +560,7 @@ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; }; - prcm@01f01400 { + prcm@1f01400 { compatible = "allwinner,sun8i-a23-prcm"; reg = <0x01f01400 0x200>; @@ -592,12 +608,12 @@ }; }; - cpucfg@01f01c00 { + cpucfg@1f01c00 { compatible = "allwinner,sun8i-a23-cpuconfig"; reg = <0x01f01c00 0x300>; }; - r_uart: serial@01f02800 { + r_uart: serial@1f02800 { compatible = "snps,dw-apb-uart"; reg = <0x01f02800 0x400>; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; @@ -608,7 +624,7 @@ status = "disabled"; }; - r_pio: pinctrl@01f02c00 { + r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun8i-a23-r-pinctrl"; reg = <0x01f02c00 0x400>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; @@ -635,7 +651,7 @@ }; }; - r_rsb: rsb@01f03400 { + r_rsb: rsb@1f03400 { compatible = "allwinner,sun8i-a23-rsb"; reg = <0x01f03400 0x400>; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/dts/sun8i-a23-evb.dts b/arch/arm/dts/sun8i-a23-evb.dts index 610786e635..8a93697df3 100644 --- a/arch/arm/dts/sun8i-a23-evb.dts +++ b/arch/arm/dts/sun8i-a23-evb.dts @@ -48,7 +48,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Allwinner A23 Evaluation Board"; @@ -108,17 +107,15 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_evb>; vmmc-supply = <®_vcc3v0>; bus-width = <4>; - cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ - cd-inverted; + cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ status = "okay"; }; &pio { mmc0_cd_pin_evb: mmc0_cd_pin@0 { - allwinner,pins = "PB4"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PB4"; + function = "gpio_in"; + bias-pull-up; }; }; diff --git a/arch/arm/dts/sun8i-a23-gt90h-v4.dts b/arch/arm/dts/sun8i-a23-gt90h-v4.dts index da55b5a6d0..e3c7a25ca3 100644 --- a/arch/arm/dts/sun8i-a23-gt90h-v4.dts +++ b/arch/arm/dts/sun8i-a23-gt90h-v4.dts @@ -53,9 +53,10 @@ status = "okay"; }; -&gsl1680 { +&touchscreen { + reg = <0x40>; compatible = "silead,gsl3675"; - touchscreen-fw-name = "silead/gsl3675-gt90h.fw"; + firmware-name = "gsl3675-gt90h.fw"; touchscreen-size-x = <1792>; touchscreen-size-y = <1024>; status = "okay"; diff --git a/arch/arm/dts/sun8i-a23-inet86dz.dts b/arch/arm/dts/sun8i-a23-inet86dz.dts index 99720218b7..d4405752a4 100644 --- a/arch/arm/dts/sun8i-a23-inet86dz.dts +++ b/arch/arm/dts/sun8i-a23-inet86dz.dts @@ -53,10 +53,12 @@ status = "okay"; }; -&gsl1680 { +&touchscreen { + reg = <0x40>; + compatible = "silead,gsl1680"; + firmware-name = "gsl1680-inet86dz.fw"; touchscreen-size-x = <960>; touchscreen-size-y = <640>; - touchscreen-fw-name = "silead/gsl1680-inet86dz.fw"; status = "okay"; }; diff --git a/arch/arm/dts/sun8i-a23-polaroid-mid2407pxe03.dts b/arch/arm/dts/sun8i-a23-polaroid-mid2407pxe03.dts index f23ca63828..649e313396 100644 --- a/arch/arm/dts/sun8i-a23-polaroid-mid2407pxe03.dts +++ b/arch/arm/dts/sun8i-a23-polaroid-mid2407pxe03.dts @@ -62,14 +62,11 @@ }; }; -&gsl1680 { - vddio-supply = <®_ldo_io1>; - touchscreen-size-x = <960>; - touchscreen-size-y = <640>; - touchscreen-inverted-x; - touchscreen-inverted-y; - touchscreen-fw-name = "silead/gsl1680-polaroid-mid2407pxe03.fw"; - status = "okay"; +&i2c1 { + mma7660: accelerometer@4c { + reg = <0x4c>; + compatible = "fsl,mma7660"; + }; }; &mmc1 { @@ -89,21 +86,24 @@ }; &mmc1_pins_a { - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + bias-pull-up; }; &r_pio { wifi_pwrseq_pin_mid2407: wifi_pwrseq_pin@0 { - allwinner,pins = "PL6"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PL6"; + function = "gpio_out"; }; }; -®_ldo_io1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-touchscreen"; +&touchscreen { + reg = <0x40>; + compatible = "silead,gsl1680"; + firmware-name = "gsl1680-polaroid-mid2407pxe03.fw"; + touchscreen-size-x = <960>; + touchscreen-size-y = <640>; + touchscreen-inverted-x; + touchscreen-inverted-y; + vddio-supply = <®_ldo_io1>; status = "okay"; }; diff --git a/arch/arm/dts/sun8i-a23-polaroid-mid2809pxe04.dts b/arch/arm/dts/sun8i-a23-polaroid-mid2809pxe04.dts index 8e8f3e0846..6b3bcae089 100644 --- a/arch/arm/dts/sun8i-a23-polaroid-mid2809pxe04.dts +++ b/arch/arm/dts/sun8i-a23-polaroid-mid2809pxe04.dts @@ -62,14 +62,6 @@ }; }; -&gsl1680 { - compatible = "silead,gsl3670"; - touchscreen-fw-name = "silead/gsl3670-polaroid-mid2809pxe04.fw"; - touchscreen-size-x = <1660>; - touchscreen-size-y = <890>; - status = "okay"; -}; - &mmc1 { pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins_a>; @@ -87,14 +79,21 @@ }; &mmc1_pins_a { - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + bias-pull-up; }; &r_pio { wifi_pwrseq_pin_mid2809: wifi_pwrseq_pin@0 { - allwinner,pins = "PL6"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PL6"; + function = "gpio_out"; }; }; + +&touchscreen { + reg = <0x40>; + compatible = "silead,gsl3670"; + firmware-name = "gsl3670-polaroid-mid2809pxe04.fw"; + touchscreen-size-x = <1660>; + touchscreen-size-y = <890>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun8i-a23-q8-tablet.dts b/arch/arm/dts/sun8i-a23-q8-tablet.dts index 956320a6cc..b6958e8f2f 100644 --- a/arch/arm/dts/sun8i-a23-q8-tablet.dts +++ b/arch/arm/dts/sun8i-a23-q8-tablet.dts @@ -48,3 +48,16 @@ model = "Q8 A23 Tablet"; compatible = "allwinner,q8-a23", "allwinner,sun8i-a23"; }; + +&codec { + allwinner,pa-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ + allwinner,audio-routing = + "Headphone", "HP", + "Headphone", "HPCOM", + "Speaker", "HP", + "MIC1", "Mic", + "MIC2", "Headset Mic", + "Mic", "MBIAS", + "Headset Mic", "HBIAS"; + status = "okay"; +}; diff --git a/arch/arm/dts/sun8i-a23.dtsi b/arch/arm/dts/sun8i-a23.dtsi index 4d1f929780..58e6585b50 100644 --- a/arch/arm/dts/sun8i-a23.dtsi +++ b/arch/arm/dts/sun8i-a23.dtsi @@ -49,8 +49,8 @@ reg = <0x40000000 0x40000000>; }; - soc@01c00000 { - codec: codec@01c22c00 { + soc@1c00000 { + codec: codec@1c22c00 { #sound-dai-cells = <0>; compatible = "allwinner,sun8i-a23-codec"; reg = <0x01c22c00 0x400>; diff --git a/arch/arm/dts/sun8i-a33-ga10h-v1.1.dts b/arch/arm/dts/sun8i-a33-ga10h-v1.1.dts index 2fea1af212..f71159987c 100644 --- a/arch/arm/dts/sun8i-a33-ga10h-v1.1.dts +++ b/arch/arm/dts/sun8i-a33-ga10h-v1.1.dts @@ -58,9 +58,10 @@ status = "okay"; }; -&gsl1680 { +&touchscreen { + reg = <0x40>; compatible = "silead,gsl3675"; - touchscreen-fw-name = "silead/gsl3675-ga10h.fw"; + firmware-name = "gsl3675-ga10h.fw"; touchscreen-size-x = <1630>; touchscreen-size-y = <990>; touchscreen-inverted-y; diff --git a/arch/arm/dts/sun8i-a33-inet-d978-rev2.dts b/arch/arm/dts/sun8i-a33-inet-d978-rev2.dts index 0f52cd9dfa..3e05959104 100644 --- a/arch/arm/dts/sun8i-a33-inet-d978-rev2.dts +++ b/arch/arm/dts/sun8i-a33-inet-d978-rev2.dts @@ -49,6 +49,15 @@ model = "INet-D978 Rev 02"; compatible = "primux,inet-d978-rev2", "allwinner,sun8i-a33"; + aliases { + serial0 = &uart1; + }; + + chosen { + /* Delete debug UART as serial0 is the UART for bluetooth */ + /delete-property/stdout-path; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -62,7 +71,7 @@ }; &mmc1_pins_a { - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + bias-pull-up; }; &mmc1 { @@ -80,9 +89,19 @@ &r_pio { led_pin_d978: led_pin_d978@0 { - allwinner,pins = "PL5"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_20_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PL5"; + function = "gpio_out"; + drive-strength = <20>; }; }; + +&r_uart { + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_a>, + <&uart1_pins_cts_rts_a>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun8i-a33-olinuxino.dts b/arch/arm/dts/sun8i-a33-olinuxino.dts index 9ea637e82b..a1a1eb64ca 100644 --- a/arch/arm/dts/sun8i-a33-olinuxino.dts +++ b/arch/arm/dts/sun8i-a33-olinuxino.dts @@ -43,7 +43,6 @@ /dts-v1/; #include "sun8i-a33.dtsi" -#include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> @@ -62,8 +61,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pin_olinuxino>; green { label = "a33-olinuxino:green:usr"; @@ -72,17 +69,24 @@ }; }; +&codec { + status = "okay"; +}; + +&dai { + status = "okay"; +}; + &ehci0 { status = "okay"; }; &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_dcdc1>; bus-width = <4>; - cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ - cd-inverted; + cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ status = "okay"; }; @@ -90,29 +94,6 @@ status = "okay"; }; -&pio { - led_pin_olinuxino: led_pins@0 { - allwinner,pins = "PB7"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 { - allwinner,pins = "PB4"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PB3"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; -}; - &r_rsb { status = "okay"; @@ -126,7 +107,15 @@ }; }; -#include "axp22x.dtsi" +#include "axp223.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; ®_aldo1 { regulator-always-on; @@ -201,6 +190,21 @@ vcc-lcd-supply = <®_dc1sw>; }; +&sound { + /* Board level jack widgets */ + simple-audio-card,widgets = "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack"; + /* Board level routing. First 2 routes copied from SoC level */ + simple-audio-card,routing = + "Left DAC", "AIF1 Slot 0 Left", + "Right DAC", "AIF1 Slot 0 Right", + "HP", "HPCOM", + "Headphone Jack", "HP", + "MIC1", "Microphone Jack", + "Microphone Jack", "MBIAS"; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_b>; @@ -217,8 +221,6 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; usb0_id_det-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_drivevbus>; diff --git a/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts index b1bc88c46c..541acb4d2b 100644 --- a/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts +++ b/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts @@ -48,7 +48,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Sinlinx SinA33"; @@ -80,7 +79,7 @@ }; }; -&de { +&codec { status = "okay"; }; @@ -88,6 +87,28 @@ cpu-supply = <®_dcdc3>; }; +&cpu0_opp_table { + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <1320000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1320000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; +}; + +&de { + status = "okay"; +}; + +&dai { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -123,8 +144,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_sina33>; vmmc-supply = <®_dcdc1>; bus-width = <4>; - cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ - cd-inverted; + cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ status = "okay"; }; @@ -140,9 +160,9 @@ &mmc2_8bit_pins { /* Increase drive strength for DDR modes */ - allwinner,drive = <SUN4I_PINCTRL_40_MA>; + drive-strength = <40>; /* eMMC is missing pull-ups */ - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + bias-pull-up; }; &ohci0 { @@ -151,10 +171,9 @@ &pio { mmc0_cd_pin_sina33: mmc0_cd_pin@0 { - allwinner,pins = "PB4"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PB4"; + function = "gpio_in"; + bias-pull-up; }; }; @@ -170,7 +189,15 @@ }; }; -#include "axp22x.dtsi" +#include "axp223.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; ®_aldo1 { regulator-always-on; @@ -232,6 +259,10 @@ regulator-name = "vcc-rtc"; }; +&sound { + status = "okay"; +}; + &tcon0 { pinctrl-names = "default"; pinctrl-0 = <&lcd_rgb666_pins>; diff --git a/arch/arm/dts/sun8i-a33.dtsi b/arch/arm/dts/sun8i-a33.dtsi index 22660919bd..8d278ee001 100644 --- a/arch/arm/dts/sun8i-a33.dtsi +++ b/arch/arm/dts/sun8i-a33.dtsi @@ -203,8 +203,8 @@ }; }; - soc@01c00000 { - tcon0: lcd-controller@01c0c000 { + soc@1c00000 { + tcon0: lcd-controller@1c0c000 { compatible = "allwinner,sun8i-a33-tcon"; reg = <0x01c0c000 0x1000>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; @@ -236,11 +236,16 @@ #address-cells = <1>; #size-cells = <0>; reg = <1>; + + tcon0_out_dsi: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi_in_tcon0>; + }; }; }; }; - crypto: crypto-engine@01c15000 { + crypto: crypto-engine@1c15000 { compatible = "allwinner,sun4i-a10-crypto"; reg = <0x01c15000 0x1000>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; @@ -250,7 +255,7 @@ reset-names = "ahb"; }; - dai: dai@01c22c00 { + dai: dai@1c22c00 { #sound-dai-cells = <0>; compatible = "allwinner,sun6i-a31-i2s"; reg = <0x01c22c00 0x200>; @@ -263,7 +268,7 @@ status = "disabled"; }; - codec: codec@01c22e00 { + codec: codec@1c22e00 { #sound-dai-cells = <0>; compatible = "allwinner,sun8i-a33-codec"; reg = <0x01c22e00 0x400>; @@ -273,14 +278,53 @@ status = "disabled"; }; - ths: ths@01c25000 { + ths: ths@1c25000 { compatible = "allwinner,sun8i-a33-ths"; reg = <0x01c25000 0x100>; #thermal-sensor-cells = <0>; #io-channel-cells = <0>; }; - fe0: display-frontend@01e00000 { + dsi: dsi@1ca0000 { + compatible = "allwinner,sun6i-a31-mipi-dsi"; + reg = <0x01ca0000 0x1000>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_MIPI_DSI>, + <&ccu CLK_DSI_SCLK>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_MIPI_DSI>; + phys = <&dphy>; + phy-names = "dphy"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + dsi_in_tcon0: endpoint { + remote-endpoint = <&tcon0_out_dsi>; + }; + }; + }; + }; + + dphy: d-phy@1ca1000 { + compatible = "allwinner,sun6i-a31-mipi-dphy"; + reg = <0x01ca1000 0x1000>; + clocks = <&ccu CLK_BUS_MIPI_DSI>, + <&ccu CLK_DSI_DPHY>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_MIPI_DSI>; + status = "disabled"; + #phy-cells = <0>; + }; + + fe0: display-frontend@1e00000 { compatible = "allwinner,sun8i-a33-display-frontend"; reg = <0x01e00000 0x20000>; interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; @@ -289,7 +333,6 @@ clock-names = "ahb", "mod", "ram"; resets = <&ccu RST_BUS_DE_FE>; - status = "disabled"; ports { #address-cells = <1>; @@ -308,7 +351,7 @@ }; }; - be0: display-backend@01e60000 { + be0: display-backend@1e60000 { compatible = "allwinner,sun8i-a33-display-backend"; reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>; reg-names = "be", "sat"; @@ -350,7 +393,7 @@ }; }; - drc0: drc@01e70000 { + drc0: drc@1e70000 { compatible = "allwinner,sun8i-a33-drc"; reg = <0x01e70000 0x10000>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/dts/sun8i-q8-common.dtsi b/arch/arm/dts/sun8i-q8-common.dtsi index 8e2cc30ec8..c676940a96 100644 --- a/arch/arm/dts/sun8i-q8-common.dtsi +++ b/arch/arm/dts/sun8i-q8-common.dtsi @@ -49,13 +49,6 @@ ethernet0 = &sdio_wifi; }; - q8_hardwaremgr { - compatible = "allwinner,sunxi-q8-hardwaremgr"; - touchscreen-i2c-bus = <&i2c0>; - touchscreen-supply = <®_ldo_io1>; - touchscreen-power-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - }; - wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; /* @@ -90,32 +83,17 @@ }; &mmc1_pins_a { - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + bias-pull-up; }; &r_pio { wifi_pwrseq_pin_q8: wifi_pwrseq_pin@0 { - allwinner,pins = "PL6", "PL7", "PL11"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PL6", "PL7", "PL11"; + function = "gpio_in"; + bias-pull-up; }; }; &usbphy { usb1_vbus-supply = <®_dldo1>; }; - -&gsl1680 { - touchscreen-size-x = <1024>; - touchscreen-size-y = <600>; - touchscreen-fw-name = "silead/gsl1680-q8-700.fw"; - status = "okay"; -}; - -®_ldo_io1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-touchscreen"; - status = "okay"; -}; diff --git a/arch/arm/dts/sun8i-r16-bananapi-m2m.dts b/arch/arm/dts/sun8i-r16-bananapi-m2m.dts index eaf0966672..0dbdb29a8f 100644 --- a/arch/arm/dts/sun8i-r16-bananapi-m2m.dts +++ b/arch/arm/dts/sun8i-r16-bananapi-m2m.dts @@ -150,8 +150,7 @@ pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_dcdc1>; bus-width = <4>; - cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ - cd-inverted; + cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ status = "okay"; }; diff --git a/arch/arm/dts/sun8i-r16-nintendo-nes-classic-edition.dts b/arch/arm/dts/sun8i-r16-nintendo-nes-classic-edition.dts index 72a8505d94..e5590208ed 100644 --- a/arch/arm/dts/sun8i-r16-nintendo-nes-classic-edition.dts +++ b/arch/arm/dts/sun8i-r16-nintendo-nes-classic-edition.dts @@ -63,8 +63,6 @@ }; &nfc { - pinctrl-names = "default"; - pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>; status = "okay"; nand@0 { diff --git a/arch/arm/dts/sun8i-r16-parrot.dts b/arch/arm/dts/sun8i-r16-parrot.dts index 47553e5229..472c03b7ae 100644 --- a/arch/arm/dts/sun8i-r16-parrot.dts +++ b/arch/arm/dts/sun8i-r16-parrot.dts @@ -84,6 +84,14 @@ }; +&codec { + status = "okay"; +}; + +&dai { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -149,8 +157,8 @@ }; &mmc2_8bit_pins { - allwinner,drive = <SUN4I_PINCTRL_40_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + drive-strength = <40>; + bias-pull-up; }; &ohci0 { @@ -159,40 +167,32 @@ &pio { mmc0_cd_pin_parrot: mmc0_cd_pin@0 { - allwinner,pins = "PD14"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PD14"; + function = "gpio_in"; + bias-pull-up; }; led_pins_parrot: led_pins@0 { - allwinner,pins = "PE16", "PE17"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PE16", "PE17"; + function = "gpio_out"; }; usb0_id_det: usb0_id_detect_pin@0 { - allwinner,pins = "PD10"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PD10"; + function = "gpio_in"; + bias-pull-up; }; usb1_vbus_pin_parrot: usb1_vbus_pin@0 { - allwinner,pins = "PD12"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PD12"; + function = "gpio_out"; }; }; &r_pio { wifi_reset_pin_parrot: wifi_reset_pin@0 { - allwinner,pins = "PL6"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PL6"; + function = "gpio_out"; }; }; @@ -209,7 +209,7 @@ }; }; -#include "axp22x.dtsi" +#include "axp223.dtsi" ®_aldo1 { regulator-always-on; @@ -325,6 +325,10 @@ status = "okay"; }; +&sound { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_b>; diff --git a/arch/arm/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/dts/sun8i-reference-design-tablet.dtsi index f29897c40a..880096c7e2 100644 --- a/arch/arm/dts/sun8i-reference-design-tablet.dtsi +++ b/arch/arm/dts/sun8i-reference-design-tablet.dtsi @@ -50,8 +50,6 @@ backlight: backlight { compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&bl_en_pin>; pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; default-brightness-level = <8>; @@ -71,15 +69,13 @@ */ clock-frequency = <400000>; - gsl1680: touchscreen@40 { - compatible = "silead,gsl1680"; - reg = <0x40>; + touchscreen: touchscreen@0 { interrupt-parent = <&pio>; interrupts = <1 5 IRQ_TYPE_EDGE_FALLING>; /* PB5 */ pinctrl-names = "default"; pinctrl-0 = <&ts_power_pin>; power-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - /* Most tablets use this touchscreen, but not all */ + /* Tablet dts must provide reg and compatible */ status = "disabled"; }; }; @@ -89,38 +85,26 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; vmmc-supply = <®_dcdc1>; bus-width = <4>; - cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ - cd-inverted; + cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ status = "okay"; }; &pio { - bl_en_pin: bl_en_pin@0 { - allwinner,pins = "PH6"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - mmc0_cd_pin: mmc0_cd_pin@0 { - allwinner,pins = "PB4"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PB4"; + function = "gpio_in"; + bias-pull-up; }; ts_power_pin: ts_power_pin@0 { - allwinner,pins = "PH1"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH1"; + function = "gpio_out"; }; usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PH8"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PH8"; + function = "gpio_in"; + bias-pull-up; }; }; @@ -138,7 +122,15 @@ }; }; -#include "axp22x.dtsi" +#include "axp223.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; ®_aldo1 { regulator-always-on; @@ -211,10 +203,21 @@ status = "okay"; }; +®_ldo_io1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-touchscreen"; + status = "okay"; +}; + ®_rtc_ldo { regulator-name = "vcc-rtc"; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + &r_uart { pinctrl-names = "default"; pinctrl-0 = <&r_uart_pins_a>; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 8a05148136..bd4ca88e16 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -195,6 +195,7 @@ /* SoC related */ #ifdef CONFIG_ARCH_LS1043A #define CONFIG_SYS_FMAN_V3 +#define CONFIG_SYS_FSL_QMAN_V3 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 7 #define CONFIG_SYS_NUM_FM1_10GEC 1 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h index a70c866651..a3f473fe28 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h @@ -68,6 +68,10 @@ void fdt_fixup_icid(void *blob); #define SET_DEBUG_ICID(streamid) \ SET_SCFG_ICID(NULL, streamid, debug_icid, 0) +#define SET_QE_ICID(streamid) \ + SET_SCFG_ICID("fsl,qe", streamid, qe_icid,\ + QE_BASE_ADDR) + #define SET_QMAN_ICID(streamid) \ SET_ICID_ENTRY("fsl,qman", streamid, streamid, \ offsetof(struct ccsr_qman, liodnr) + \ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index be0a6ae363..8c10526a6c 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -85,6 +85,8 @@ #define GPIO3_BASE_ADDR (CONFIG_SYS_IMMR + 0x1320000) #define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x1330000) +#define QE_BASE_ADDR (CONFIG_SYS_IMMR + 0x1400000) + #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) #define EDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x01c00000) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index afea9b8da8..8d002da3ed 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -35,6 +35,9 @@ * -DPAA2 * -u-boot will allocate a range of stream IDs to be used by the Management * Complex for containers and will set these values in the MC DPC image. + * -u-boot will fixup the iommu-map property in the fsl-mc node in the + * device tree (see Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt + * for more info on the msi-map definition) * -the MC is responsible for allocating and setting up 'isolation context * IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices. * diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 13a282ffe1..137cd61804 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -86,6 +86,8 @@ struct sys_info { unsigned long freq_localbus; }; +#define CCSR_DEVDISR1_QE 0x00000001 + /* Device Configuration and Pin Control */ struct ccsr_gur { u32 porsr1; /* POR status 1 */ @@ -389,33 +391,6 @@ struct ccsr_serdes { u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */ }; - - -/* AHCI (sata) register map */ -struct ccsr_ahci { - u32 res1[0xa4/4]; /* 0x0 - 0xa4 */ - u32 pcfg; /* port config */ - u32 ppcfg; /* port phy1 config */ - u32 pp2c; /* port phy2 config */ - u32 pp3c; /* port phy3 config */ - u32 pp4c; /* port phy4 config */ - u32 pp5c; /* port phy5 config */ - u32 paxic; /* port AXI config */ - u32 axicc; /* AXI cache control */ - u32 axipc; /* AXI PROT control */ - u32 ptc; /* port Trans Config */ - u32 pts; /* port Trans Status */ - u32 plc; /* port link config */ - u32 plc1; /* port link config1 */ - u32 plc2; /* port link config2 */ - u32 pls; /* port link status */ - u32 pls1; /* port link status1 */ - u32 pcmdc; /* port CMD config */ - u32 ppcs; /* port phy control status */ - u32 pberr; /* port 0/1 BIST error */ - u32 cmds; /* port 0/1 CMD status error */ -}; - #define RCPM_POWMGTCSR 0x130 #define RCPM_POWMGTCSR_SERDES_PW 0x80000000 #define RCPM_POWMGTCSR_LPM20_REQ 0x00100000 diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h deleted file mode 100644 index 3acc5af6f2..0000000000 --- a/arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ - -#ifndef __FSL_SATA_H_ -#define __FSL_SATA_H_ - -int ls1021a_sata_init(void); -#endif diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h index 42ce8dcd6d..6d31cc4422 100644 --- a/arch/arm/include/asm/omap_mmc.h +++ b/arch/arm/include/asm/omap_mmc.h @@ -68,7 +68,6 @@ struct omap_hsmmc_plat { struct mmc_config cfg; struct hsmmc *base_addr; struct mmc *mmc; - bool cd_inverted; u32 controller_flags; const char *hw_rev; }; diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 69856c8942..a6329dc022 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -151,6 +151,7 @@ config TARGET_SAMA5D2_PTC_EK bool "SAMA5D2 PTC EK board" select BOARD_EARLY_INIT_F select SAMA5D2 + select BOARD_LATE_INIT config TARGET_SAMA5D2_XPLAINED bool "SAMA5D2 Xplained board" @@ -177,6 +178,7 @@ config TARGET_SAMA5D3_XPLAINED select BOARD_EARLY_INIT_F select SAMA5D3 select SUPPORT_SPL + select BOARD_LATE_INIT config TARGET_SAMA5D3XEK bool "SAMA5D3X-EK board" diff --git a/arch/arm/mach-davinci/da850_lowlevel.c b/arch/arm/mach-davinci/da850_lowlevel.c index 95dc93a24f..822e0dc4a1 100644 --- a/arch/arm/mach-davinci/da850_lowlevel.c +++ b/arch/arm/mach-davinci/da850_lowlevel.c @@ -288,10 +288,10 @@ int arch_cpu_init(void) /* GPIO setup */ board_gpio_init(); - +#if !CONFIG_IS_ENABLED(DM_SERIAL) NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1), CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); - +#endif /* * Fix Power and Emulation Management Register * see sprufw3a.pdf page 37 Table 24 diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig index bfd99db6e2..e562d693c6 100644 --- a/arch/arm/mach-snapdragon/Kconfig +++ b/arch/arm/mach-snapdragon/Kconfig @@ -14,6 +14,7 @@ choice config TARGET_DRAGONBOARD410C bool "96Boards Dragonboard 410C" + select BOARD_LATE_INIT help Support for 96Boards Dragonboard 410C. This board complies with 96Board Open Platform Specifications. Features: diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 8faef0ba9f..c727d9162c 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -20,6 +20,7 @@ config MPC85xx select CREATE_ARCH_SYMLINK select SYS_FSL_DDR select SYS_FSL_DDR_BE + select BINMAN imply CMD_HASH imply CMD_IRQ imply USB_EHCI_HCD if USB diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 19e8d02bf4..7d139fffa2 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -1143,6 +1143,10 @@ config ARCH_T4240 imply CMD_REGINFO imply FSL_SATA +config MPC85XX_HAVE_RESET_VECTOR + bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc" + depends on MPC85xx + config BOOKE bool default y diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds index 6db6da19aa..75b0285e4e 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds @@ -74,6 +74,7 @@ SECTIONS .data.init : { *(.data.init) } . = ALIGN(256); __init_end = .; + _end = .; .bootpg ADDR(.text) - 0x1000 : { diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds index 8588d7c8ad..a2193bf768 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds @@ -42,6 +42,7 @@ SECTIONS . = ALIGN(8); __init_begin = .; __init_end = .; + _end = .; #if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */ .bootpg ADDR(.text) + 0x1000 : { diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds index 04951825d4..6dc8d9913b 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -55,6 +55,7 @@ SECTIONS . = ALIGN(8); __init_begin = .; __init_end = .; + _end = .; #ifdef CONFIG_SPL_SKIP_RELOCATE . = ALIGN(4); __bss_start = .; diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds index 14c31be5bf..22bbac51aa 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -81,6 +81,7 @@ SECTIONS .data.init : { *(.data.init) } . = ALIGN(256); __init_end = .; + _end = .; #ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC .bootpg ADDR(.text) - 0x1000 : diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile new file mode 100644 index 0000000000..a19aa56300 --- /dev/null +++ b/arch/powerpc/dts/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ + +dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb + +targets += $(dtb-y) + +# Add any required device tree compiler flags here +DTC_FLAGS += + +PHONY += dtbs +dtbs: $(addprefix $(obj)/, $(dtb-y)) + @: + +clean-files := *.dtb diff --git a/arch/powerpc/dts/e6500_power_isa.dtsi b/arch/powerpc/dts/e6500_power_isa.dtsi new file mode 100644 index 0000000000..1b06170c7a --- /dev/null +++ b/arch/powerpc/dts/e6500_power_isa.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * e6500 Power ISA Device Tree Source (include) + * + * Copyright 2013 Freescale Semiconductor Inc. + * Copyright 2018 NXP + */ + +/ { + cpus { + power-isa-version = "2.06"; + power-isa-b; // Base + power-isa-e; // Embedded + power-isa-atb; // Alternate Time Base + power-isa-cs; // Cache Specification + power-isa-ds; // Decorated Storage + power-isa-e.ed; // Embedded.Enhanced Debug + power-isa-e.pd; // Embedded.External PID + power-isa-e.hv; // Embedded.Hypervisor + power-isa-e.le; // Embedded.Little-Endian + power-isa-e.pm; // Embedded.Performance Monitor + power-isa-e.pc; // Embedded.Processor Control + power-isa-ecl; // Embedded Cache Locking + power-isa-exp; // External Proxy + power-isa-fp; // Floating Point + power-isa-fp.r; // Floating Point.Record + power-isa-mmc; // Memory Coherence + power-isa-scpm; // Store Conditional Page Mobility + power-isa-wt; // Wait + power-isa-64; // 64-bit + power-isa-e.pt; // Embedded.Page Table + power-isa-e.hv.lrat; // Embedded.Hypervisor.LRAT + power-isa-e.em; // Embedded Multi-Threading + power-isa-v; // Vector (AltiVec) + fsl,eref-er; // Enhanced Reservations + fsl,eref-deo; // Data Cache Extended Operations + mmu-type = "power-embedded"; + }; +}; diff --git a/arch/powerpc/dts/t2080.dtsi b/arch/powerpc/dts/t2080.dtsi new file mode 100644 index 0000000000..db65ea5725 --- /dev/null +++ b/arch/powerpc/dts/t2080.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * T2080/T2081 Silicon/SoC Device Tree Source (pre include) + * + * Copyright 2013 Freescale Semiconductor Inc. + * Copyright 2018 NXP + */ + +/dts-v1/; + +/include/ "e6500_power_isa.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: PowerPC,e6500@0 { + device_type = "cpu"; + reg = <0 1>; + fsl,portid-mapping = <0x80000000>; + }; + cpu1: PowerPC,e6500@2 { + device_type = "cpu"; + reg = <2 3>; + fsl,portid-mapping = <0x80000000>; + }; + cpu2: PowerPC,e6500@4 { + device_type = "cpu"; + reg = <4 5>; + fsl,portid-mapping = <0x80000000>; + }; + cpu3: PowerPC,e6500@6 { + device_type = "cpu"; + reg = <6 7>; + fsl,portid-mapping = <0x80000000>; + }; + }; + + soc: soc@ffe000000 { + ranges = <0x00000000 0xf 0xfe000000 0x1000000>; + reg = <0xf 0xfe000000 0 0x00001000>; + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <4>; + reg = <0x40000 0x40000>; + compatible = "fsl,mpic"; + device_type = "open-pic"; + clock-frequency = <0x0>; + }; + }; +}; diff --git a/arch/powerpc/dts/t2080qds.dts b/arch/powerpc/dts/t2080qds.dts new file mode 100644 index 0000000000..1819a081dd --- /dev/null +++ b/arch/powerpc/dts/t2080qds.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * T2080QDS Device Tree Source + * + * Copyright 2013 - 2015 Freescale Semiconductor Inc. + * Copyright 2018 NXP + */ + +/include/ "t2080.dtsi" + +/ { + model = "fsl,T2080QDS"; + compatible = "fsl,T2080QDS"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; +}; diff --git a/arch/powerpc/dts/u-boot.dtsi b/arch/powerpc/dts/u-boot.dtsi new file mode 100644 index 0000000000..213d543c6d --- /dev/null +++ b/arch/powerpc/dts/u-boot.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <config.h> + +/ { + binman { + filename = "u-boot-with-dtb.bin"; + skip-at-start = <CONFIG_SYS_TEXT_BASE>; + sort-by-offset; + pad-byte = <0xff>; + size = <CONFIG_SYS_MONITOR_LEN>; + + u-boot-with-ucode-ptr { + offset = <CONFIG_SYS_TEXT_BASE>; + optional-ucode; + }; + + u-boot-dtb-with-ucode { +#ifdef CONFIG_MPC85xx + align = <256>; +#endif + }; +#ifdef CONFIG_MPC85XX_HAVE_RESET_VECTOR + powerpc-mpc85xx-bootpg-resetvec { + offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>; + }; +#endif + }; +}; diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts index 6ac37f1ed7..1aa0f8eef5 100644 --- a/arch/sandbox/dts/sandbox.dts +++ b/arch/sandbox/dts/sandbox.dts @@ -153,6 +153,7 @@ pinctrl { compatible = "sandbox,pinctrl"; + status = "okay"; pinctrl_i2c0: i2c0 { groups = "i2c"; @@ -164,6 +165,12 @@ groups = "serial_a"; function = "serial"; }; + + pinctrl_onewire0: onewire0 { + groups = "w1"; + function = "w1"; + bias-pull-up; + }; }; reset@1 { @@ -322,6 +329,19 @@ reg = <0x0 0x400>; }; }; + + onewire0: onewire { + compatible = "w1-gpio"; + gpios = <&gpio_a 8>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_onewire0>; + status = "okay"; + + sandbox_eeprom0: sandbox_eeprom@0 { + compatible = "sandbox,w1-eeprom"; + status = "okay"; + }; + }; }; #include "cros-ec-keyboard.dtsi" diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 42ceeb994e..491f889f3b 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -37,6 +37,7 @@ usb1 = &usb_1; usb2 = &usb_2; axi0 = &axi; + osd0 = "/osd"; }; a-test { @@ -649,6 +650,10 @@ }; }; + osd { + compatible = "sandbox,sandbox_osd"; + }; + board { compatible = "sandbox,board_sandbox"; }; diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h index c8ae52b248..89f3d90c73 100644 --- a/arch/sandbox/include/asm/test.h +++ b/arch/sandbox/include/asm/test.h @@ -90,4 +90,12 @@ long sandbox_i2c_rtc_get_set_base_time(struct udevice *dev, long base_time); int sandbox_usb_keyb_add_string(struct udevice *dev, const char *str); +/** + * sandbox_osd_get_mem() - get the internal memory of a sandbox OSD + * + * @dev: OSD device for which to access the internal memory for + * @buf: pointer to buffer to receive the OSD memory data + * @buflen: length of buffer in bytes + */ +int sandbox_osd_get_mem(struct udevice *dev, u8 *buf, size_t buflen); #endif diff --git a/board/atmel/common/board.c b/board/atmel/common/board.c index 650eb2238c..8f9b5e137c 100644 --- a/board/atmel/common/board.c +++ b/board/atmel/common/board.c @@ -5,7 +5,64 @@ */ #include <common.h> +#include <w1.h> +#include <w1-eeprom.h> +#include <dm/device-internal.h> + +#define AT91_PDA_EEPROM_ID_OFFSET 15 +#define AT91_PDA_EEPROM_ID_LENGTH 5 +#define AT91_PDA_EEPROM_DEFAULT_BUS 0 void dummy(void) { } + +#if defined CONFIG_W1 +void at91_pda_detect(void) +{ + struct udevice *bus, *dev; + u8 buf[AT91_PDA_EEPROM_ID_LENGTH + 1] = {0}; + int ret; + int pda = 0; + + ret = w1_get_bus(AT91_PDA_EEPROM_DEFAULT_BUS, &bus); + if (ret) + return; + + for (device_find_first_child(bus, &dev); + dev; + device_find_next_child(&dev)) { + ret = device_probe(dev); + if (ret) { + continue; + } else { + ret = w1_eeprom_read_buf(dev, AT91_PDA_EEPROM_ID_OFFSET, + (u8 *)buf, AT91_PDA_EEPROM_ID_LENGTH); + if (ret) + return; + break; + } + } + pda = simple_strtoul((const char *)buf, NULL, 10); + + switch (pda) { + case 7000: + if (buf[4] == 'B') + printf("PDA TM7000B detected\n"); + else + printf("PDA TM7000 detected\n"); + break; + case 4300: + printf("PDA TM4300 detected\n"); + break; + case 5000: + printf("PDA TM5000 detected\n"); + break; + } + env_set("pda", (const char *)buf); +} +#else +void at91_pda_detect(void) +{ +} +#endif diff --git a/board/atmel/sama5d27_som1_ek/MAINTAINERS b/board/atmel/sama5d27_som1_ek/MAINTAINERS index 609583c341..295639cd3c 100644 --- a/board/atmel/sama5d27_som1_ek/MAINTAINERS +++ b/board/atmel/sama5d27_som1_ek/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/atmel/sama5d27_som1_ek/ F: include/configs/sama5d27_som1_ek.h F: configs/sama5d27_som1_ek_mmc_defconfig +F: configs/sama5d27_som1_ek_mmc1_defconfig diff --git a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c index d5ddf8d2eb..83634345f3 100644 --- a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c +++ b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c @@ -15,6 +15,8 @@ #include <asm/arch/gpio.h> #include <asm/arch/sama5d2.h> +extern void at91_pda_detect(void); + DECLARE_GLOBAL_DATA_PTR; static void board_usb_hw_init(void) @@ -28,6 +30,7 @@ int board_late_init(void) #ifdef CONFIG_DM_VIDEO at91_video_show_board_info(); #endif + at91_pda_detect(); return 0; } #endif diff --git a/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c index 789841e45a..17e08fa9b2 100644 --- a/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c +++ b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c @@ -20,6 +20,8 @@ #include <asm/arch/sama5d2.h> #include <asm/arch/sama5d2_smc.h> +extern void at91_pda_detect(void); + DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_NAND_ATMEL @@ -65,6 +67,14 @@ static void board_nand_hw_init(void) } #endif +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + at91_pda_detect(); + return 0; +} +#endif + static void board_usb_hw_init(void) { atmel_pio4_set_pio_output(AT91_PIO_PORTB, 12, ATMEL_PIO_PUEN_MASK); diff --git a/board/atmel/sama5d2_xplained/MAINTAINERS b/board/atmel/sama5d2_xplained/MAINTAINERS index ff9c86f538..5b599d8e57 100644 --- a/board/atmel/sama5d2_xplained/MAINTAINERS +++ b/board/atmel/sama5d2_xplained/MAINTAINERS @@ -5,3 +5,4 @@ F: board/atmel/sama5d2_xplained/ F: include/configs/sama5d2_xplained.h F: configs/sama5d2_xplained_mmc_defconfig F: configs/sama5d2_xplained_spiflash_defconfig +F: configs/sama5d2_xplained_emmc_defconfig diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c index 592b4d82dd..fccd80ec70 100644 --- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c +++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c @@ -15,6 +15,8 @@ #include <asm/arch/gpio.h> #include <asm/arch/sama5d2.h> +extern void at91_pda_detect(void); + DECLARE_GLOBAL_DATA_PTR; static void board_usb_hw_init(void) @@ -28,6 +30,7 @@ int board_late_init(void) #ifdef CONFIG_DM_VIDEO at91_video_show_board_info(); #endif + at91_pda_detect(); return 0; } #endif diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/board/atmel/sama5d3_xplained/sama5d3_xplained.c index c47f63864b..289f8d8499 100644 --- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c +++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c @@ -18,6 +18,8 @@ DECLARE_GLOBAL_DATA_PTR; +extern void at91_pda_detect(void); + #ifdef CONFIG_NAND_ATMEL void sama5d3_xplained_nand_hw_init(void) { @@ -72,6 +74,14 @@ void board_debug_uart_init(void) } #endif +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + at91_pda_detect(); + return 0; +} +#endif + #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c index 526c6c7f70..4da64890b3 100644 --- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c +++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c @@ -17,6 +17,8 @@ DECLARE_GLOBAL_DATA_PTR; +extern void at91_pda_detect(void); + #ifdef CONFIG_NAND_ATMEL static void sama5d4_xplained_nand_hw_init(void) { @@ -71,6 +73,7 @@ static void sama5d4_xplained_usb_hw_init(void) #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { + at91_pda_detect(); #ifdef CONFIG_DM_VIDEO at91_video_show_board_info(); #endif diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c index 315da8b866..5db1027717 100644 --- a/board/freescale/ls1012afrdm/ls1012afrdm.c +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c @@ -24,11 +24,15 @@ DECLARE_GLOBAL_DATA_PTR; static inline int get_board_version(void) { - struct ccsr_gpio *pgpio = (void *)(GPIO1_BASE_ADDR); - int val; + uint32_t val; +#ifdef CONFIG_TARGET_LS1012AFRDM + val = 0; +#else + struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR); - val = in_be32(&pgpio->gpdat); + val = in_be32(&pgpio->gpdat) & BOARD_REV_MASK;/*Get GPIO2 11,12,14*/ +#endif return val; } @@ -46,11 +50,11 @@ int checkboard(void) puts("Version"); switch (rev) { - case BOARD_REV_A: - puts(": RevA "); + case BOARD_REV_A_B: + puts(": RevA/B "); break; - case BOARD_REV_B: - puts(": RevB "); + case BOARD_REV_C: + puts(": RevC "); break; default: puts(": unknown"); @@ -100,7 +104,7 @@ int dram_init(void) #ifdef CONFIG_TARGET_LS1012AFRWY board_rev = get_board_version(); - if (board_rev & BOARD_REV_B) { + if (board_rev == BOARD_REV_C) { mparam.mdctl = 0x05180000; gd->ram_size = SYS_SDRAM_SIZE_1024; } else { diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c index a691dabc0e..fb05b55b5c 100644 --- a/board/freescale/ls1021aiot/ls1021aiot.c +++ b/board/freescale/ls1021aiot/ls1021aiot.c @@ -11,7 +11,6 @@ #include <asm/arch/ls102xa_devdis.h> #include <asm/arch/ls102xa_soc.h> -#include <asm/arch/ls102xa_sata.h> #include <fsl_csu.h> #include <fsl_esdhc.h> #include <fsl_immap.h> @@ -206,10 +205,6 @@ int board_init(void) #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { -#ifdef CONFIG_SCSI_AHCI_PLAT - ls1021a_sata_init(); -#endif - return 0; } #endif diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 6722cad27a..c828dacf9e 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -11,7 +11,6 @@ #include <asm/arch/fsl_serdes.h> #include <asm/arch/ls102xa_soc.h> #include <asm/arch/ls102xa_devdis.h> -#include <asm/arch/ls102xa_sata.h> #include <hwconfig.h> #include <mmc.h> #include <fsl_csu.h> @@ -362,9 +361,6 @@ int config_serdes_mux(void) #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { -#ifdef CONFIG_SCSI_AHCI_PLAT - ls1021a_sata_init(); -#endif #ifdef CONFIG_CHAIN_OF_TRUST fsl_setenv_chain_of_trust(); #endif diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 863bf76f73..dcd6d933ea 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -11,7 +11,6 @@ #include <asm/arch/fsl_serdes.h> #include <asm/arch/ls102xa_devdis.h> #include <asm/arch/ls102xa_soc.h> -#include <asm/arch/ls102xa_sata.h> #include <hwconfig.h> #include <mmc.h> #include <fsl_csu.h> @@ -556,9 +555,6 @@ void spl_board_init(void) #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { -#ifdef CONFIG_SCSI_AHCI_PLAT - ls1021a_sata_init(); -#endif #ifdef CONFIG_CHAIN_OF_TRUST fsl_setenv_chain_of_trust(); #endif diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index 4fba57242b..44cc509b53 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -14,6 +14,7 @@ #include <asm/arch/fdt.h> #include <asm/arch/mmu.h> #include <asm/arch/soc.h> +#include <asm/arch-fsl-layerscape/fsl_icid.h> #include <ahci.h> #include <hwconfig.h> #include <mmc.h> @@ -353,6 +354,8 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_fixup_board_enet(blob); #endif + fdt_fixup_icid(blob); + reg = QIXIS_READ(brdcfg[0]); reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index e7d8650d27..f31f0ec515 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -9,6 +9,7 @@ #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/soc.h> +#include <asm/arch-fsl-layerscape/fsl_icid.h> #include <fdt_support.h> #include <hwconfig.h> #include <ahci.h> @@ -177,6 +178,8 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_fixup_fman_ethernet(blob); #endif + fdt_fixup_icid(blob); + /* * qe-hdlc and usb multi-use the pins, * when set hwconfig to qe-hdlc, delete usb node. diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index a0dab6fc2e..517a8ceed9 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -575,6 +575,8 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS); + fdt_fsl_mc_fixup_iommu_map_entry(blob); + fsl_fdt_fixup_flash(blob); #ifdef CONFIG_FSL_MC_ENET diff --git a/board/freescale/ls2080a/ls2080a.c b/board/freescale/ls2080a/ls2080a.c index 75014fd7f9..698ae1f9a6 100644 --- a/board/freescale/ls2080a/ls2080a.c +++ b/board/freescale/ls2080a/ls2080a.c @@ -127,6 +127,8 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory_banks(blob, base, size, 2); + fdt_fsl_mc_fixup_iommu_map_entry(blob); + #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) fdt_fixup_board_enet(blob); #endif diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index c811e994d0..d336ef840c 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -332,6 +332,8 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory_banks(blob, base, size, 2); + fdt_fsl_mc_fixup_iommu_map_entry(blob); + fsl_fdt_fixup_dr_usb(blob, bd); #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 46b18cf00b..cf91bc30fb 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -394,6 +394,8 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory_banks(blob, base, size, 2); + fdt_fsl_mc_fixup_iommu_map_entry(blob); + fsl_fdt_fixup_dr_usb(blob, bd); fsl_fdt_fixup_flash(blob); diff --git a/board/freescale/t208xqds/README b/board/freescale/t208xqds/README index 2a2a0e514c..d690857f2e 100755 --- a/board/freescale/t208xqds/README +++ b/board/freescale/t208xqds/README @@ -272,3 +272,22 @@ How to update the ucode of Freescale FMAN For more details, please refer to T2080QDS User Guide and access website www.freescale.com and Freescale QorIQ SDK Infocenter document. + +Device tree support and how to enable it for different configs +-------------------------------------------------------------- +Device tree support is available for t2080qds for below mentioned boot, +1. NOR Boot +2. NAND Boot +3. SD Boot +4. SPIFLASH Boot + +To enable device tree support for other boot, below configs need to be +enabled in relative defconfig file, +1. CONFIG_DEFAULT_DEVICE_TREE="t2080qds" (Change default device tree name if required) +2. CONFIG_OF_CONTROL +3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at + CONFIG_RESET_VECTOR_ADDRESS - 0xffc + +If device tree support is enabled in defconfig, +1. use 'u-boot-with-dtb.bin' for NOR boot. +2. use 'u-boot-with-spl-pbl.bin' for other boot. diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile index 698ea3b02b..af9058a5d7 100644 --- a/board/gdsys/common/Makefile +++ b/board/gdsys/common/Makefile @@ -15,3 +15,7 @@ obj-$(CONFIG_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o obj-$(CONFIG_STRIDER) += fanctrl.o obj-$(CONFIG_STRIDER_CON) += osd.o obj-$(CONFIG_STRIDER_CON_DP) += osd.o + +ifdef CONFIG_OSD +obj-$(CONFIG_GDSYS_LEGACY_OSD_CMDS) += osd_cmd.o +endif diff --git a/board/gdsys/common/osd_cmd.c b/board/gdsys/common/osd_cmd.c new file mode 100644 index 0000000000..53179b9811 --- /dev/null +++ b/board/gdsys/common/osd_cmd.c @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2017 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + * + * based on the gdsys osd driver, which is + * + * (C) Copyright 2010 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + */ + +#include <common.h> +#include <dm.h> +#include <hexdump.h> +#include <video_osd.h> +#include <malloc.h> + +static int do_osd_write(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + struct udevice *dev; + uint x, y; + uint count; + char *hexstr; + u8 *buffer; + size_t buflen; + int res; + + if (argc < 4 || (strlen(argv[3])) % 2) + return CMD_RET_USAGE; + + x = simple_strtoul(argv[1], NULL, 16); + y = simple_strtoul(argv[2], NULL, 16); + hexstr = argv[3]; + count = (argc > 4) ? simple_strtoul(argv[4], NULL, 16) : 1; + + buflen = strlen(hexstr) / 2; + + buffer = malloc(buflen); + if (!buffer) { + puts("Memory allocation failure\n"); + return CMD_RET_FAILURE; + } + + res = hex2bin(buffer, hexstr, buflen); + if (res) { + free(buffer); + puts("Hexadecimal input contained invalid characters\n"); + return CMD_RET_FAILURE; + } + + for (uclass_first_device(UCLASS_VIDEO_OSD, &dev); + dev; + uclass_next_device(&dev)) { + int res; + + res = video_osd_set_mem(dev, x, y, buffer, buflen, count); + if (res) { + free(buffer); + printf("Could not write to video mem on osd %s\n", + dev->name); + return CMD_RET_FAILURE; + } + } + + free(buffer); + + return CMD_RET_SUCCESS; +} + +static int do_osd_print(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + struct udevice *dev; + uint x, y; + u8 color; + char *text; + + if (argc < 5) + return CMD_RET_USAGE; + + x = simple_strtoul(argv[1], NULL, 16); + y = simple_strtoul(argv[2], NULL, 16); + color = simple_strtoul(argv[3], NULL, 16); + text = argv[4]; + + for (uclass_first_device(UCLASS_VIDEO_OSD, &dev); + dev; + uclass_next_device(&dev)) { + int res; + + res = video_osd_print(dev, x, y, color, text); + if (res) { + printf("Could not print string to osd %s\n", dev->name); + return CMD_RET_FAILURE; + } + } + + return CMD_RET_SUCCESS; +} + +static int do_osd_size(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + struct udevice *dev; + uint x, y; + + if (argc < 3) + return CMD_RET_USAGE; + + x = simple_strtoul(argv[1], NULL, 16); + y = simple_strtoul(argv[2], NULL, 16); + + for (uclass_first_device(UCLASS_VIDEO_OSD, &dev); + dev; + uclass_next_device(&dev)) { + int res; + + res = video_osd_set_size(dev, x, y); + + if (res) { + printf("Could not set size on osd %s\n", dev->name); + return CMD_RET_FAILURE; + } + } + + return CMD_RET_SUCCESS; +} + +U_BOOT_CMD( + osdw, 5, 0, do_osd_write, + "write 16-bit hex encoded buffer to osd memory", + "osdw [pos_x] [pos_y] [buffer] [count] - write 8-bit hex encoded buffer to osd memory\n" +); + +U_BOOT_CMD( + osdp, 5, 0, do_osd_print, + "write ASCII buffer to osd memory", + "osdp [pos_x] [pos_y] [color] [text] - write ASCII buffer to osd memory\n" +); + +U_BOOT_CMD( + osdsize, 3, 0, do_osd_size, + "set OSD XY size in characters", + "osdsize [size_x] [size_y] - set OSD XY size in characters\n" +); diff --git a/board/gdsys/mpc8308/Kconfig b/board/gdsys/mpc8308/Kconfig index cb29c25c65..9d99f68692 100644 --- a/board/gdsys/mpc8308/Kconfig +++ b/board/gdsys/mpc8308/Kconfig @@ -1,3 +1,9 @@ +config GDSYS_LEGACY_OSD_CMDS + bool + help + Use the 'osdw', 'osdp', and 'osdsize' legacy commands required by + gdsys devices. + if TARGET_HRCON config SYS_BOARD @@ -9,6 +15,9 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "hrcon" +config GDSYS_LEGACY_OSD_CMDS + default y + endif if TARGET_STRIDER @@ -22,6 +31,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "strider" +config GDSYS_LEGACY_OSD_CMDS + default y endif config CMD_IOLOOP diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c index 620423bbc8..48d886930f 100644 --- a/board/logicpd/omap3som/omap3logic.c +++ b/board/logicpd/omap3som/omap3logic.c @@ -331,13 +331,6 @@ int board_late_init(void) #endif #if defined(CONFIG_MMC) -int board_mmc_init(bd_t *bis) -{ - return omap_mmc_init(0, 0, 0, -1, -1); -} -#endif - -#if defined(CONFIG_MMC) void board_mmc_power_init(void) { twl4030_power_mmc_init(0); diff --git a/board/logicpd/omap3som/omap3logic.h b/board/logicpd/omap3som/omap3logic.h index a5601f7a7b..aeb26b90d7 100644 --- a/board/logicpd/omap3som/omap3logic.h +++ b/board/logicpd/omap3som/omap3logic.h @@ -131,145 +131,18 @@ void set_muxconf_regs(void) MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)); /*GPIO_64*/ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)); /*GPMC_WAIT3*/ - MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)); /*CAM_HS */ - MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)); /*CAM_VS */ - MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)); /*CAM_XCLKA*/ - MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)); /*CAM_PCLK*/ - MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)); /*GPIO_98*/ - MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)); /*CAM_D0*/ - MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)); /*CAM_D1*/ - MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)); /*CAM_D2*/ - MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)); /*CAM_D3*/ - MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)); /*CAM_D4*/ - MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)); /*CAM_D5*/ - MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)); /*CAM_D6*/ - MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)); /*CAM_D7*/ - MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)); /*CAM_D8*/ - MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)); /*CAM_D9*/ - MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)); /*CAM_D10*/ - MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)); /*CAM_D11*/ - MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)); /*CAM_XCLKB*/ - MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)); /*GPIO_167*/ - MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)); /*CAM_STROBE*/ - - MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)); /*CSI2_DX0*/ - MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)); /*CSI2_DY0*/ - MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)); /*CSI2_DX1*/ - MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)); /*CSI2_DY1*/ - - MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)); /*McBSP2_FSX*/ - MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)); /*McBSP2_CLKX*/ - MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)); /*McBSP2_DR*/ - MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)); /*McBSP2_DX*/ - MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/ - MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /*MMC1_DAT4*/ - MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /*MMC1_DAT5*/ - MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /*MMC1_DAT6*/ - MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /*MMC1_DAT7*/ - - MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)); /*MMC2_CLK*/ - MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)); /*MMC2_CMD*/ - MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)); /*MMC2_DAT0*/ - MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)); /*MMC2_DAT1*/ - MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)); /*MMC2_DAT2*/ - MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)); /*MMC2_DAT3*/ - MUX_VAL(CP(MMC2_DAT4), (IDIS | PTD | DIS | M0)); /*MMC2_DAT4*/ - MUX_VAL(CP(MMC2_DAT5), (IDIS | PTD | DIS | M0)); /*MMC2_DAT5*/ - MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | DIS | M0)); /*MMC2_DAT6 */ - MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M0)); /*MMC2_DAT7*/ - - MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)); /*McBSP3_DX*/ - MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)); /*McBSP3_DR*/ - MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)); /*McBSP3_CLKX*/ - MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)); /*McBSP3_FSX*/ - - MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)); /*UART2_CTS*/ - MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)); /*UART2_RTS*/ - MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)); /*UART2_TX*/ - MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)); /*UART2_RX*/ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)); /*UART1_TX*/ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)); /*UART1_RTS*/ MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)); /*UART1_CTS*/ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)); /*UART1_RX*/ - MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)); /*GPIO_152*/ - MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)); /*GPIO_153*/ - - MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)); /*MCBSP1_CLKR*/ - MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)); /*MCBSP1_FSR*/ - MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)); /*MCBSP1_DX*/ - MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)); /*MCBSP1_DR*/ - MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)); /*MCBSP_CLKS*/ - MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)); /*MCBSP1_FSX*/ - MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)); /*MCBSP1_CLKX*/ - - MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)); /*UART3_CTS_*/ - MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)); /*UART3_RTS_SD */ - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); /*UART3_RX_IRRX*/ - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); /*UART3_TX_IRTX*/ - - MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); /*HSUSB0_CLK*/ - MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); /*HSUSB0_STP*/ - MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); /*HSUSB0_DIR*/ - MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); /*HSUSB0_NXT*/ - MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA0*/ - MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA1*/ - MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA2*/ - MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA3*/ - MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA4*/ - MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA5*/ - MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/ - MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/ - - MUX_VAL(CP(I2C1_SCL), (IEN | EN | M0)); /*I2C1_SCL*/ - MUX_VAL(CP(I2C1_SDA), (IEN | EN | M0)); /*I2C1_SDA*/ - - MUX_VAL(CP(I2C2_SCL), (IEN | EN | M0)); /*I2C2_SCL*/ - MUX_VAL(CP(I2C2_SDA), (IEN | EN | M0)); /*I2C2_SDA*/ - - MUX_VAL(CP(I2C3_SCL), (IEN | EN | M0)); /*I2C3_SCL*/ - MUX_VAL(CP(I2C3_SDA), (IEN | EN | M0)); /*I2C3_SDA*/ - - MUX_VAL(CP(I2C4_SCL), (IEN | EN | M0)); /*I2C4_SCL*/ - MUX_VAL(CP(I2C4_SDA), (IEN | EN | M0)); /*I2C4_SDA*/ - - MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)); /*HDQ_SIO*/ - - MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)); /*McSPI1_CLK*/ - MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)); /*McSPI1_SIMO */ - MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)); /*McSPI1_SOMI */ - MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)); /*McSPI1_CS0*/ - MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)); /*GPIO_175*/ - MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)); /*GPIO_176*/ - MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)); /*McSPI1_CS3*/ - - MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)); /*McSPI2_CLK*/ - MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)); /*McSPI2_SIMO*/ - MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)); /*McSPI2_SOMI*/ - MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)); /*McSPI2_CS0*/ - MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)); /*McSPI2_CS1*/ - - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /*SYS_32K*/ - MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /*SYS_CLKREQ*/ - MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /*SYS_nIRQ*/ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)); /*GPIO_2*/ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)); /*GPIO_3 */ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)); /*GPIO_4*/ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)); /*GPIO_5*/ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)); /*GPIO_6*/ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)); /*GPIO_7*/ - - MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*SYS_OFF_MODE*/ - MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*SYS_CLKOUT1*/ - MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)); /*SYS_CLKOUT2*/ - MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/ diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c b/board/qualcomm/dragonboard410c/dragonboard410c.c index 53e231e55a..9ceed3ad9b 100644 --- a/board/qualcomm/dragonboard410c/dragonboard410c.c +++ b/board/qualcomm/dragonboard410c/dragonboard410c.c @@ -44,7 +44,7 @@ int dram_init_banksize(void) return 0; } -int board_prepare_usb(enum usb_init_type type) +int board_usb_init(int index, enum usb_init_type init) { static struct udevice *pmic_gpio; static struct gpio_desc hub_reset, usb_sel; @@ -93,7 +93,7 @@ int board_prepare_usb(enum usb_init_type type) } } - if (type == USB_INIT_HOST) { + if (init == USB_INIT_HOST) { /* Start USB Hub */ dm_gpio_set_dir_flags(&hub_reset, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); @@ -140,7 +140,8 @@ int misc_init_r(void) if (dm_gpio_get_value(&resin)) { env_set("bootdelay", "-1"); - printf("Power button pressed - dropping to console.\n"); + env_set("bootcmd", "fastboot 0"); + printf("key_vol_down pressed - Starting fastboot.\n"); } return 0; @@ -151,6 +152,16 @@ int board_init(void) return 0; } +int board_late_init(void) +{ + char serial[16]; + + memset(serial, 0, 16); + snprintf(serial, 13, "%x", msm_board_serial()); + env_set("serial#", serial); + return 0; +} + /* Fixup of DTB for Linux Kernel * 1. Fixup installed DRAM. * 2. Fixup WLAN/BT Mac address: diff --git a/board/seeed/linkit-smart-7688/MAINTAINERS b/board/seeed/linkit-smart-7688/MAINTAINERS index c3bbad4231..f2186c1b9d 100644 --- a/board/seeed/linkit-smart-7688/MAINTAINERS +++ b/board/seeed/linkit-smart-7688/MAINTAINERS @@ -4,5 +4,5 @@ S: Maintained F: board/seeed/linkit-smart-7688 F: include/configs/linkit-smart-7688.h F: configs/linkit-smart-7688_defconfig -F: configs/linkit-smart-7688_ram_defconfig +F: configs/linkit-smart-7688-ram_defconfig F: arch/mips/dts/linkit-smart-7688.dts diff --git a/cmd/Kconfig b/cmd/Kconfig index cf97a0f2be..d1f1dc04b4 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -304,11 +304,6 @@ config CMD_XIMG help Extract a part of a multi-image. -config CMD_POWEROFF - bool "poweroff" - help - Poweroff/Shutdown the system - config CMD_SPL bool "spl export - Export boot information for Falcon boot" depends on SPL @@ -832,6 +827,13 @@ config CMD_I2C help I2C support. +config CMD_W1 + depends on W1 + default y if W1 + bool "w1 - Support for Dallas 1-Wire protocol" + help + Dallas 1-wire protocol support + config CMD_LOADB bool "loadb" default y @@ -913,6 +915,14 @@ config CMD_ONENAND and erasing blocks. It allso provides a way to show and change bad blocks, and test the device. +config CMD_OSD + bool "osd" + help + Enable the 'osd' command which allows to query information from and + write text data to a on-screen display (OSD) device; a virtual device + associated with a display capable of displaying a text overlay on the + display it's associated with.. + config CMD_PART bool "part" select HAVE_BLOCK_DEVICE @@ -937,6 +947,11 @@ config CMD_PCMCIA about 1990. These devices are typically removable memory or network cards using a standard 68-pin connector. +config CMD_POWEROFF + bool "poweroff" + help + Poweroff/Shutdown the system + config CMD_READ bool "read - Read binary data from a partition" help diff --git a/cmd/Makefile b/cmd/Makefile index d3815abf26..2c858f9500 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -97,6 +97,7 @@ obj-$(CONFIG_CMD_MTDPARTS) += mtdparts.o obj-$(CONFIG_CMD_NAND) += nand.o obj-$(CONFIG_CMD_NET) += net.o obj-$(CONFIG_CMD_ONENAND) += onenand.o +obj-$(CONFIG_CMD_OSD) += osd.o obj-$(CONFIG_CMD_PART) += part.o ifdef CONFIG_PCI obj-$(CONFIG_CMD_PCI) += pci.o @@ -146,6 +147,7 @@ obj-$(CONFIG_CMD_THOR_DOWNLOAD) += thordown.o obj-$(CONFIG_CMD_XIMG) += ximg.o obj-$(CONFIG_CMD_YAFFS2) += yaffs2.o obj-$(CONFIG_CMD_SPL) += spl.o +obj-$(CONFIG_CMD_W1) += w1.o obj-$(CONFIG_CMD_ZIP) += zip.o obj-$(CONFIG_CMD_ZFS) += zfs.o @@ -219,7 +219,10 @@ static unsigned long load_elf_image_shdr(unsigned long addr) memcpy((void *)(uintptr_t)shdr->sh_addr, (const void *)image, shdr->sh_size); } - flush_cache(shdr->sh_addr, shdr->sh_size); + flush_cache(rounddown(shdr->sh_addr, ARCH_DMA_MINALIGN), + roundup((shdr->sh_addr + shdr->sh_size), + ARCH_DMA_MINALIGN) - + rounddown(shdr->sh_addr, ARCH_DMA_MINALIGN)); } return ehdr->e_entry; diff --git a/cmd/nvedit.c b/cmd/nvedit.c index 793b68b887..de16c72c23 100644 --- a/cmd/nvedit.c +++ b/cmd/nvedit.c @@ -987,7 +987,8 @@ NXTARG: ; } if (chk) { - envp->crc = crc32(0, envp->data, ENV_SIZE); + envp->crc = crc32(0, envp->data, + size ? size - offsetof(env_t, data) : ENV_SIZE); #ifdef CONFIG_ENV_ADDR_REDUND envp->flags = ACTIVE_FLAG; #endif diff --git a/cmd/osd.c b/cmd/osd.c new file mode 100644 index 0000000000..0b1fa49936 --- /dev/null +++ b/cmd/osd.c @@ -0,0 +1,291 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2017 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + * + * based on the gdsys osd driver, which is + * + * (C) Copyright 2010 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + */ + +#include <common.h> +#include <dm.h> +#include <hexdump.h> +#include <video_osd.h> +#include <malloc.h> + +/* Container for selected OSD device */ +static struct udevice *osd_cur; + +/** + * cmd_osd_set_osd_num() - Set the OSD selected for operation + * + * Set the OSD device, which will be used by all subsequent OSD commands. + * + * Devices are identified by their uclass sequence number (as listed by 'osd + * show'). + * + * @osdnum: The OSD device to be selected, identified by its sequence number. + * Return: 0 if OK, -ve on error + */ +static int cmd_osd_set_osd_num(unsigned int osdnum) +{ + struct udevice *osd; + int res; + + res = uclass_get_device_by_seq(UCLASS_VIDEO_OSD, osdnum, &osd); + if (res) { + printf("%s: No OSD %u (err = %d)\n", __func__, osdnum, res); + return res; + } + osd_cur = osd; + + return 0; +} + +/** + * osd_get_osd_cur() - Get the selected OSD device + * + * Get the OSD device that is used by all OSD commands. + * + * @osdp: Pointer to structure that will receive the currently selected OSD + * device. + * Return: 0 if OK, -ve on error + */ +static int osd_get_osd_cur(struct udevice **osdp) +{ + if (!osd_cur) { + puts("No osd selected\n"); + return -ENODEV; + } + *osdp = osd_cur; + + return 0; +} + +/** + * show_osd() - Display information about a OSD device + * + * Display a device's ID (sequence number), and whether it is active (i.e. + * probed) or not. + * + * @osd: OSD device to print information for + */ +static void show_osd(struct udevice *osd) +{ + printf("OSD %d:\t%s", osd->req_seq, osd->name); + if (device_active(osd)) + printf(" (active %d)", osd->seq); + printf("\n"); +} + +static int do_osd_write(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + uint x, y; + uint count; + char *hexstr; + u8 *buffer; + size_t buflen; + int res; + + if (argc < 4 || (strlen(argv[3]) % 2)) + return CMD_RET_USAGE; + + if (!osd_cur) { + puts("No osd selected\n"); + return CMD_RET_FAILURE; + } + + x = simple_strtoul(argv[1], NULL, 16); + y = simple_strtoul(argv[2], NULL, 16); + hexstr = argv[3]; + count = (argc > 4) ? simple_strtoul(argv[4], NULL, 16) : 1; + + buflen = strlen(hexstr) / 2; + + buffer = malloc(buflen); + if (!buffer) { + puts("Memory allocation failure\n"); + return CMD_RET_FAILURE; + } + + res = hex2bin(buffer, hexstr, buflen); + if (res) { + free(buffer); + puts("Hexadecimal input contained invalid characters\n"); + return CMD_RET_FAILURE; + } + + res = video_osd_set_mem(osd_cur, x, y, buffer, buflen, count); + if (res) { + free(buffer); + printf("%s: Could not write to video mem\n", + osd_cur->name); + return CMD_RET_FAILURE; + } + + free(buffer); + + return CMD_RET_SUCCESS; +} + +static int do_osd_print(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + uint x, y; + u8 color; + char *text; + int res; + + if (argc < 5) + return CMD_RET_USAGE; + + if (!osd_cur) { + puts("No osd selected\n"); + return CMD_RET_FAILURE; + } + + x = simple_strtoul(argv[1], NULL, 16); + y = simple_strtoul(argv[2], NULL, 16); + color = simple_strtoul(argv[3], NULL, 16); + text = argv[4]; + + res = video_osd_print(osd_cur, x, y, color, text); + if (res) { + printf("Could not print string to osd %s\n", osd_cur->name); + return CMD_RET_FAILURE; + } + + return CMD_RET_SUCCESS; +} + +static int do_osd_size(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + uint x, y; + int res; + + if (argc < 3) + return CMD_RET_USAGE; + + if (!osd_cur) { + puts("No osd selected\n"); + return CMD_RET_FAILURE; + } + + x = simple_strtoul(argv[1], NULL, 16); + y = simple_strtoul(argv[2], NULL, 16); + + res = video_osd_set_size(osd_cur, x, y); + if (res) { + printf("Could not set size on osd %s\n", osd_cur->name); + return CMD_RET_FAILURE; + } + + return CMD_RET_SUCCESS; +} + +static int do_show_osd(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + struct udevice *osd; + + if (argc == 1) { + /* show all OSDs */ + struct uclass *uc; + int res; + + res = uclass_get(UCLASS_VIDEO_OSD, &uc); + if (res) { + printf("Error while getting OSD uclass (err=%d)\n", + res); + return CMD_RET_FAILURE; + } + + uclass_foreach_dev(osd, uc) + show_osd(osd); + } else { + int i, res; + + /* show specific OSD */ + i = simple_strtoul(argv[1], NULL, 10); + + res = uclass_get_device_by_seq(UCLASS_VIDEO_OSD, i, &osd); + if (res) { + printf("Invalid osd %d: err=%d\n", i, res); + return CMD_RET_FAILURE; + } + show_osd(osd); + } + + return CMD_RET_SUCCESS; +} + +static int do_osd_num(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + int osd_no; + int res = 0; + + if (argc == 1) { + /* querying current setting */ + struct udevice *osd; + + if (!osd_get_osd_cur(&osd)) + osd_no = osd->seq; + else + osd_no = -1; + printf("Current osd is %d\n", osd_no); + } else { + osd_no = simple_strtoul(argv[1], NULL, 10); + printf("Setting osd to %d\n", osd_no); + + res = cmd_osd_set_osd_num(osd_no); + if (res) + printf("Failure changing osd number (err = %d)\n", res); + } + + return res ? CMD_RET_FAILURE : CMD_RET_SUCCESS; +} + +static cmd_tbl_t cmd_osd_sub[] = { + U_BOOT_CMD_MKENT(show, 1, 1, do_show_osd, "", ""), + U_BOOT_CMD_MKENT(dev, 1, 1, do_osd_num, "", ""), + U_BOOT_CMD_MKENT(write, 4, 1, do_osd_write, "", ""), + U_BOOT_CMD_MKENT(print, 4, 1, do_osd_print, "", ""), + U_BOOT_CMD_MKENT(size, 2, 1, do_osd_size, "", ""), +}; + +static int do_osd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + cmd_tbl_t *c; + + if (argc < 2) + return CMD_RET_USAGE; + + /* Strip off leading 'osd' command argument */ + argc--; + argv++; + + c = find_cmd_tbl(argv[0], &cmd_osd_sub[0], ARRAY_SIZE(cmd_osd_sub)); + + if (c) + return c->cmd(cmdtp, flag, argc, argv); + else + return CMD_RET_USAGE; +} + +static char osd_help_text[] = + "show - show OSD info\n" + "osd dev [dev] - show or set current OSD\n" + "write [pos_x] [pos_y] [buffer] [count] - write 8-bit hex encoded buffer to osd memory at a given position\n" + "print [pos_x] [pos_y] [color] [text] - write ASCII buffer (given by text data and driver-specific color information) to osd memory\n" + "size [size_x] [size_y] - set OSD XY size in characters\n"; + +U_BOOT_CMD( + osd, 6, 1, do_osd, + "OSD sub-system", + osd_help_text +); @@ -47,8 +47,7 @@ struct selected_dev { static struct selected_dev ubi_dev; #ifdef CONFIG_CMD_UBIFS -int ubifs_is_mounted(void); -void cmd_ubifs_umount(void); +#include <ubifs_uboot.h> #endif static void display_volume_info(struct ubi_device *ubi) diff --git a/cmd/ubifs.c b/cmd/ubifs.c index 11bab7a1a1..e4000b7ad1 100644 --- a/cmd/ubifs.c +++ b/cmd/ubifs.c @@ -19,16 +19,10 @@ static int ubifs_initialized; static int ubifs_mounted; -static int do_ubifs_mount(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) +int cmd_ubifs_mount(char *vol_name) { - char *vol_name; int ret; - if (argc != 2) - return CMD_RET_USAGE; - - vol_name = argv[1]; debug("Using volume %s\n", vol_name); if (ubifs_initialized == 0) { @@ -42,7 +36,19 @@ static int do_ubifs_mount(cmd_tbl_t *cmdtp, int flag, int argc, ubifs_mounted = 1; - return 0; + return ret; +} +static int do_ubifs_mount(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + char *vol_name; + + if (argc != 2) + return CMD_RET_USAGE; + + vol_name = argv[1]; + + return cmd_ubifs_mount(vol_name); } int ubifs_is_mounted(void) @@ -50,11 +56,18 @@ int ubifs_is_mounted(void) return ubifs_mounted; } -void cmd_ubifs_umount(void) +int cmd_ubifs_umount(void) { + if (ubifs_initialized == 0) { + printf("No UBIFS volume mounted!\n"); + return -1; + } + uboot_ubifs_umount(); ubifs_mounted = 0; ubifs_initialized = 0; + + return 0; } static int do_ubifs_umount(cmd_tbl_t *cmdtp, int flag, int argc, @@ -63,14 +76,7 @@ static int do_ubifs_umount(cmd_tbl_t *cmdtp, int flag, int argc, if (argc != 1) return CMD_RET_USAGE; - if (ubifs_initialized == 0) { - printf("No UBIFS volume mounted!\n"); - return -1; - } - - cmd_ubifs_umount(); - - return 0; + return cmd_ubifs_umount(); } static int do_ubifs_ls(cmd_tbl_t *cmdtp, int flag, int argc, diff --git a/cmd/w1.c b/cmd/w1.c new file mode 100644 index 0000000000..9c95fcf9cd --- /dev/null +++ b/cmd/w1.c @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * (C) Copyright 2018 + * Microchip Technology, Inc. + * Eugen Hristev <eugen.hristev@microchip.com> + */ +#include <common.h> +#include <command.h> +#include <w1.h> +#include <w1-eeprom.h> +#include <dm/device-internal.h> + +static int w1_bus(void) +{ + struct udevice *bus, *dev; + int ret; + + ret = w1_get_bus(0, &bus); + if (ret) { + printf("one wire interface not found\n"); + return CMD_RET_FAILURE; + } + printf("Bus %d:\t%s", bus->seq, bus->name); + if (device_active(bus)) + printf(" (active)"); + printf("\n"); + + for (device_find_first_child(bus, &dev); + dev; + device_find_next_child(&dev)) { + ret = device_probe(dev); + + printf("\t%s (%d) uclass %s : ", dev->name, dev->seq, + dev->uclass->uc_drv->name); + + if (ret) + printf("device error\n"); + else + printf("family 0x%x\n", w1_get_device_family(dev)); + } + return CMD_RET_SUCCESS; +} + +static int w1_read(int argc, char *const argv[]) +{ + int bus_n = 0, dev_n = 0, offset = 0, len = 512; + int i; + struct udevice *bus, *dev; + int ret; + u8 buf[512]; + + if (argc > 2) + bus_n = simple_strtoul(argv[2], NULL, 10); + + if (argc > 3) + dev_n = simple_strtoul(argv[3], NULL, 10); + + if (argc > 4) + offset = simple_strtoul(argv[4], NULL, 10); + + if (argc > 5) + len = simple_strtoul(argv[5], NULL, 10); + + if (len > 512) { + printf("len needs to be <= 512\n"); + return CMD_RET_FAILURE; + } + + ret = w1_get_bus(bus_n, &bus); + if (ret) { + printf("one wire interface not found\n"); + return CMD_RET_FAILURE; + } + + for (device_find_first_child(bus, &dev), i = 0; + dev && i <= dev_n; + device_find_next_child(&dev), i++) { + ret = device_probe(dev); + if (!ret && i == dev_n) + break; + } + + if (i != dev_n || ret || !dev) { + printf("invalid dev\n"); + return CMD_RET_FAILURE; + } + + if (strcmp(dev->uclass->uc_drv->name, "w1_eeprom")) { + printf("the device present on the interface is of unknown device class\n"); + return CMD_RET_FAILURE; + } + + ret = w1_eeprom_read_buf(dev, offset, (u8 *)buf, len); + if (ret) { + printf("error reading device %s\n", dev->name); + return CMD_RET_FAILURE; + } + + for (i = 0; i < len; i++) + printf("%x", buf[i]); + printf("\n"); + + return CMD_RET_SUCCESS; +} + +int do_w1(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + if (argc < 2) + return CMD_RET_USAGE; + + if (!strcmp(argv[1], "bus")) + return w1_bus(); + + if (!strcmp(argv[1], "read")) + return w1_read(argc, argv); + + return CMD_RET_SUCCESS; +} + +U_BOOT_CMD(w1, 6, 0, do_w1, + "onewire interface utility commands", + "bus - show onewire bus info (all)\n" + "w1 read [<bus> [<dev> [offset [length]]]]" + " - read from onewire device 'dev' on onewire bus 'bus'" + " starting from offset 'offset' and length 'length'\n" + " defaults: bus 0, dev 0, offset 0, length 512 bytes."); diff --git a/common/Kconfig b/common/Kconfig index be2e1b80f7..41f27a1338 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -259,6 +259,11 @@ config CONSOLE_RECORD_IN_SIZE The buffer is allocated immediately after the malloc() region is ready. +config DISABLE_CONSOLE + bool "Add functionality to disable console completely" + help + Disable console (in & out). + config IDENT_STRING string "Board specific string to be added to uboot version string" help diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index 75c41598e6..4d55dccc92 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -140,7 +140,8 @@ static int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device) #endif if (err) { #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT - printf("spl: could not find mmc device. error: %d\n", err); + printf("spl: could not find mmc device %d. error: %d\n", + mmc_dev, err); #endif return err; } diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index 6b5de4d009..4a39cd2d1d 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -7,6 +7,7 @@ CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_T2080QDS=y +CONFIG_DEFAULT_DEVICE_TREE="t2080qds" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -35,6 +36,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)" +CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y CONFIG_FSL_CAAM=y CONFIG_FSL_ESDHC=y @@ -54,4 +56,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index a203582cb5..c89c63d92d 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -8,6 +8,7 @@ CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_T2080QDS=y +CONFIG_DEFAULT_DEVICE_TREE="t2080qds" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -35,6 +36,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)" +CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_FSL_CAAM=y CONFIG_FSL_ESDHC=y @@ -53,4 +55,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index 6528eea389..b5f960fa1f 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_MPC85xx=y CONFIG_TARGET_T2080QDS=y +CONFIG_DEFAULT_DEVICE_TREE="t2080qds" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -36,6 +37,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)" +CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_FSL_CAAM=y CONFIG_FSL_ESDHC=y @@ -54,4 +56,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index 4a5cbb26ad..b34a0f5c99 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_MPC85xx=y CONFIG_TARGET_T2080QDS=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -24,6 +25,8 @@ CONFIG_CMD_FAT=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="t2080qds" CONFIG_ENV_IS_IN_FLASH=y CONFIG_FSL_CAAM=y CONFIG_FSL_ESDHC=y @@ -42,4 +45,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig index 96491f37b2..e334030e51 100644 --- a/configs/am3517_evm_defconfig +++ b/configs/am3517_evm_defconfig @@ -38,6 +38,7 @@ CONFIG_DEFAULT_DEVICE_TREE="am3517-evm" CONFIG_SPL_OF_PLATDATA=y # CONFIG_ENV_IS_IN_FAT is not set CONFIG_ENV_IS_IN_NAND=y +CONFIG_DM_PCA953X=y CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y CONFIG_SYS_NAND_BUSWIDTH_16BIT=y @@ -47,6 +48,8 @@ CONFIG_SPL_NAND_SIMPLE=y CONFIG_MII=y CONFIG_DRIVER_TI_EMAC=y # CONFIG_TWL4030_POWER is not set +CONFIG_PINCTRL=y +CONFIG_PINCTRL_SINGLE=y CONFIG_CONS_INDEX=3 CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig index c30f396e65..6dc70dd387 100644 --- a/configs/da850evm_defconfig +++ b/configs/da850evm_defconfig @@ -24,6 +24,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CRC32_VERIFY=y # CONFIG_CMD_EEPROM is not set +CONFIG_CMD_DM=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_GPT is not set # CONFIG_CMD_PART is not set @@ -50,6 +51,8 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_SINGLE=y CONFIG_SPI_FLASH_MTD=y CONFIG_MII=y CONFIG_DRIVER_TI_EMAC=y diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig index 4039d0ee59..8ea522af93 100644 --- a/configs/da850evm_direct_nor_defconfig +++ b/configs/da850evm_direct_nor_defconfig @@ -5,7 +5,6 @@ CONFIG_TARGET_DA850EVM=y CONFIG_DA850_LOWLEVEL=y CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_NR_DRAM_BANKS=1 -# CONFIG_SYS_MALLOC_F is not set CONFIG_SYS_EXTRA_OPTIONS="USE_NOR,DIRECT_NOR_BOOT" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -21,6 +20,7 @@ CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CMD_IMLS=y CONFIG_CRC32_VERIFY=y # CONFIG_CMD_EEPROM is not set +CONFIG_CMD_DM=y # CONFIG_CMD_GPIO is not set # CONFIG_CMD_GPT is not set # CONFIG_CMD_MMC is not set @@ -48,8 +48,12 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_SINGLE=y CONFIG_MII=y CONFIG_DRIVER_TI_EMAC=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig index 11d6a2b4c5..d13d832e81 100644 --- a/configs/da850evm_nand_defconfig +++ b/configs/da850evm_nand_defconfig @@ -24,6 +24,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CRC32_VERIFY=y # CONFIG_CMD_EEPROM is not set +CONFIG_CMD_DM=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_GPT is not set CONFIG_CMD_NAND=y @@ -51,6 +52,8 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_SINGLE=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig index 96a831443a..a55abaf8df 100644 --- a/configs/dragonboard410c_defconfig +++ b/configs/dragonboard410c_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x80080000 CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 410C" CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=1 +# CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_MISC_INIT_R=y @@ -22,6 +23,10 @@ CONFIG_CMD_TIMER=y CONFIG_DEFAULT_DEVICE_TREE="dragonboard410c" CONFIG_ENV_IS_IN_MMC=y CONFIG_CLK=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x91000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_MSM_GPIO=y CONFIG_PM8916_GPIO=y CONFIG_LED=y @@ -29,6 +34,7 @@ CONFIG_LED_GPIO=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_MSM=y +CONFIG_PHY=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_DM_PMIC=y @@ -42,6 +48,11 @@ CONFIG_USB_EHCI_MSM=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 +CONFIG_USB_GADGET_PRODUCT_NUM=0xd00d +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DUALSPEED=n CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index a7742b45dc..1d1586d7e4 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -50,3 +50,5 @@ CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_RSA=y CONFIG_SPL_RSA=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index e9224b0298..c22686398e 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -50,3 +50,10 @@ CONFIG_USB_STORAGE=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_BLK=y +CONFIG_DM_MMC=y +CONFIG_DM_SCSI=y +CONFIG_SATA_CEVA=y +CONFIG_SCSI_AHCI=y +CONFIG_SCSI=y +CONFIG_AHCI=y diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index 5619d23b6e..221755ca3e 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -51,3 +51,5 @@ CONFIG_USB_STORAGE=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index af7939de9c..b59fdf3153 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -57,3 +57,5 @@ CONFIG_USB_STORAGE=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index e5d2b28aa6..2dfe44dcd1 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -61,3 +61,5 @@ CONFIG_USB_STORAGE=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index 54813b4d21..94c16dacb1 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -67,3 +67,5 @@ CONFIG_USB_STORAGE=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig index 493b58286e..fe0aeafbea 100644 --- a/configs/ls1043aqds_defconfig +++ b/configs/ls1043aqds_defconfig @@ -47,3 +47,10 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_BLK=y +CONFIG_DM_MMC=y +CONFIG_DM_SCSI=y +CONFIG_SATA_CEVA=y +CONFIG_SCSI_AHCI=y +CONFIG_SCSI=y +CONFIG_AHCI=y diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig index b91542cddf..2e06f6d8df 100644 --- a/configs/ls1043aqds_lpuart_defconfig +++ b/configs/ls1043aqds_lpuart_defconfig @@ -49,3 +49,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig index 779a8bf86b..aed30c1e7f 100644 --- a/configs/ls1043aqds_nand_defconfig +++ b/configs/ls1043aqds_nand_defconfig @@ -62,3 +62,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig index 2d098d3f34..c1e86d1e3b 100644 --- a/configs/ls1043aqds_nor_ddr3_defconfig +++ b/configs/ls1043aqds_nor_ddr3_defconfig @@ -48,3 +48,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig index 55935f22cf..b0a562e726 100644 --- a/configs/ls1043aqds_qspi_defconfig +++ b/configs/ls1043aqds_qspi_defconfig @@ -46,3 +46,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig index ad18b46c5b..b37d52dbcc 100644 --- a/configs/ls1043aqds_sdcard_ifc_defconfig +++ b/configs/ls1043aqds_sdcard_ifc_defconfig @@ -62,3 +62,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig index 7aa271f674..2ef5b01382 100644 --- a/configs/ls1043aqds_sdcard_qspi_defconfig +++ b/configs/ls1043aqds_sdcard_qspi_defconfig @@ -59,3 +59,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig index 83a7afbf6a..28027ff24e 100644 --- a/configs/ls1043ardb_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_SECURE_BOOT_defconfig @@ -45,3 +45,5 @@ CONFIG_USB_STORAGE=y CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig index c72231b307..df68b94f0f 100644 --- a/configs/ls1043ardb_defconfig +++ b/configs/ls1043ardb_defconfig @@ -43,3 +43,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig index 64e41ecfd2..97364b0218 100644 --- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig @@ -62,3 +62,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y CONFIG_RSA=y CONFIG_SPL_RSA=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig index a3d1ee84b4..476bb90cba 100644 --- a/configs/ls1043ardb_nand_defconfig +++ b/configs/ls1043ardb_nand_defconfig @@ -60,3 +60,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index b44c35d1ec..95438004e5 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -58,3 +58,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig index 01effd9fb1..bab8009128 100644 --- a/configs/ls1046aqds_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_SECURE_BOOT_defconfig @@ -49,3 +49,5 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y CONFIG_RSA=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig index ca1703ba8c..fad2eed085 100644 --- a/configs/ls1046aqds_defconfig +++ b/configs/ls1046aqds_defconfig @@ -49,3 +49,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig index 9b0200d802..08f2f14475 100644 --- a/configs/ls1046aqds_lpuart_defconfig +++ b/configs/ls1046aqds_lpuart_defconfig @@ -51,3 +51,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig index b1ecedff1b..3d302057d6 100644 --- a/configs/ls1046aqds_nand_defconfig +++ b/configs/ls1046aqds_nand_defconfig @@ -56,3 +56,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig index e5495ad26a..56443adeba 100644 --- a/configs/ls1046aqds_qspi_defconfig +++ b/configs/ls1046aqds_qspi_defconfig @@ -49,3 +49,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig index 7fd3e77755..e9c101fabe 100644 --- a/configs/ls1046aqds_sdcard_ifc_defconfig +++ b/configs/ls1046aqds_sdcard_ifc_defconfig @@ -65,3 +65,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig index a3eea7a777..021d4f9300 100644 --- a/configs/ls1046aqds_sdcard_qspi_defconfig +++ b/configs/ls1046aqds_sdcard_qspi_defconfig @@ -64,3 +64,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig index e0f07b702d..3968136ec0 100644 --- a/configs/ls1046ardb_emmc_defconfig +++ b/configs/ls1046ardb_emmc_defconfig @@ -60,3 +60,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig index 6495447b83..c142df3832 100644 --- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig @@ -46,3 +46,5 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y CONFIG_RSA=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig index 5204bb51a1..f9660c03cf 100644 --- a/configs/ls1046ardb_qspi_defconfig +++ b/configs/ls1046ardb_qspi_defconfig @@ -46,3 +46,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig index 07eebbf50f..9486e90edb 100644 --- a/configs/ls1046ardb_sdcard_defconfig +++ b/configs/ls1046ardb_sdcard_defconfig @@ -59,3 +59,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfig index 1d288ab698..64677f0f9d 100644 --- a/configs/ls1088aqds_defconfig +++ b/configs/ls1088aqds_defconfig @@ -47,3 +47,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig index 606c52d91a..7c5f696ed1 100644 --- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig @@ -54,3 +54,5 @@ CONFIG_USB_GADGET=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig index 21f64abef8..9bda1b38cd 100644 --- a/configs/ls1088aqds_qspi_defconfig +++ b/configs/ls1088aqds_qspi_defconfig @@ -52,3 +52,5 @@ CONFIG_USB_DWC3=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig b/configs/ls1088aqds_sdcard_ifc_defconfig index 09ead404f6..b1dc2ef306 100644 --- a/configs/ls1088aqds_sdcard_ifc_defconfig +++ b/configs/ls1088aqds_sdcard_ifc_defconfig @@ -55,3 +55,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig index fad7c7f48a..615fb5fa61 100644 --- a/configs/ls1088aqds_sdcard_qspi_defconfig +++ b/configs/ls1088aqds_sdcard_qspi_defconfig @@ -61,3 +61,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig index 859ff11a1d..f54b4a9f5a 100644 --- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig @@ -55,3 +55,5 @@ CONFIG_USB_GADGET=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig index a42158c862..1feadedf70 100644 --- a/configs/ls1088ardb_qspi_defconfig +++ b/configs/ls1088ardb_qspi_defconfig @@ -53,3 +53,5 @@ CONFIG_USB_DWC3=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig index bc53bba1e6..4b6695d1b3 100644 --- a/configs/ls1088ardb_sdcard_qspi_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_defconfig @@ -62,3 +62,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls2080a_emu_defconfig b/configs/ls2080a_emu_defconfig index 1f2c052427..ccccc28dd5 100644 --- a/configs/ls2080a_emu_defconfig +++ b/configs/ls2080a_emu_defconfig @@ -33,3 +33,5 @@ CONFIG_FSL_CAAM=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls2080a_simu_defconfig b/configs/ls2080a_simu_defconfig index a4263b7f38..57a568d9bb 100644 --- a/configs/ls2080a_simu_defconfig +++ b/configs/ls2080a_simu_defconfig @@ -36,3 +36,5 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig index a6d6daeb57..b8b043172f 100644 --- a/configs/ls2080aqds_SECURE_BOOT_defconfig +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -54,3 +54,5 @@ CONFIG_USB_STORAGE=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig index 6ada3487dd..30263513de 100644 --- a/configs/ls2080aqds_defconfig +++ b/configs/ls2080aqds_defconfig @@ -53,3 +53,5 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index ee986d56c2..86696513de 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -62,3 +62,5 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig index 4dbb6dd4ac..9980caacec 100644 --- a/configs/ls2080aqds_qspi_defconfig +++ b/configs/ls2080aqds_qspi_defconfig @@ -53,3 +53,5 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig index 2259178529..8bcab1e28b 100644 --- a/configs/ls2080aqds_sdcard_defconfig +++ b/configs/ls2080aqds_sdcard_defconfig @@ -60,3 +60,5 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig index 3c015e3173..9d79a22c0e 100644 --- a/configs/ls2080ardb_SECURE_BOOT_defconfig +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -55,3 +55,5 @@ CONFIG_USB_STORAGE=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig index a62e09bdf7..f3ff02c087 100644 --- a/configs/ls2080ardb_defconfig +++ b/configs/ls2080ardb_defconfig @@ -54,3 +54,5 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index 4801f51bcc..8af5cba98b 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -58,3 +58,5 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig index 5813d2999d..6ae87248f5 100644 --- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig @@ -53,3 +53,5 @@ CONFIG_USB_STORAGE=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig index 944384b590..ba1f1687b0 100644 --- a/configs/ls2088ardb_qspi_defconfig +++ b/configs/ls2088ardb_qspi_defconfig @@ -55,3 +55,5 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_BLK=y +CONFIG_DM_MMC=y diff --git a/configs/sama5d27_som1_ek_mmc_defconfig b/configs/sama5d27_som1_ek_mmc_defconfig index 3607470de5..fbde79c4ef 100644 --- a/configs/sama5d27_som1_ek_mmc_defconfig +++ b/configs/sama5d27_som1_ek_mmc_defconfig @@ -90,3 +90,8 @@ CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_DM_VIDEO=y CONFIG_ATMEL_HLCD=y +CONFIG_W1=y +CONFIG_W1_GPIO=y +CONFIG_W1_EEPROM=y +CONFIG_W1_EEPROM_DS24XXX=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/sama5d2_ptc_ek_mmc_defconfig b/configs/sama5d2_ptc_ek_mmc_defconfig index 42f0c95b79..60df0f0062 100644 --- a/configs/sama5d2_ptc_ek_mmc_defconfig +++ b/configs/sama5d2_ptc_ek_mmc_defconfig @@ -63,3 +63,8 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y +CONFIG_W1=y +CONFIG_W1_GPIO=y +CONFIG_W1_EEPROM=y +CONFIG_W1_EEPROM_DS24XXX=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/sama5d2_ptc_ek_nandflash_defconfig b/configs/sama5d2_ptc_ek_nandflash_defconfig index c4b308596e..4e39406a24 100644 --- a/configs/sama5d2_ptc_ek_nandflash_defconfig +++ b/configs/sama5d2_ptc_ek_nandflash_defconfig @@ -62,3 +62,8 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y +CONFIG_W1=y +CONFIG_W1_GPIO=y +CONFIG_W1_EEPROM=y +CONFIG_W1_EEPROM_DS24XXX=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig index 77dc82ce0c..f8748f8c84 100644 --- a/configs/sama5d2_xplained_mmc_defconfig +++ b/configs/sama5d2_xplained_mmc_defconfig @@ -88,3 +88,8 @@ CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_DM_VIDEO=y CONFIG_ATMEL_HLCD=y +CONFIG_W1=y +CONFIG_W1_GPIO=y +CONFIG_W1_EEPROM=y +CONFIG_W1_EEPROM_DS24XXX=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig index fc9ec9c80a..efe71769a4 100644 --- a/configs/sama5d2_xplained_spiflash_defconfig +++ b/configs/sama5d2_xplained_spiflash_defconfig @@ -85,3 +85,8 @@ CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_DM_VIDEO=y CONFIG_ATMEL_HLCD=y +CONFIG_W1=y +CONFIG_W1_GPIO=y +CONFIG_W1_EEPROM=y +CONFIG_W1_EEPROM_DS24XXX=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig index 7f2d276b29..154cdc2189 100644 --- a/configs/sama5d3_xplained_mmc_defconfig +++ b/configs/sama5d3_xplained_mmc_defconfig @@ -76,3 +76,8 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y +CONFIG_W1=y +CONFIG_W1_GPIO=y +CONFIG_W1_EEPROM=y +CONFIG_W1_EEPROM_DS24XXX=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig index ac8435e4dd..3bf93de9c0 100644 --- a/configs/sama5d3_xplained_nandflash_defconfig +++ b/configs/sama5d3_xplained_nandflash_defconfig @@ -72,4 +72,9 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y +CONFIG_W1=y +CONFIG_W1_GPIO=y +CONFIG_W1_EEPROM=y +CONFIG_W1_EEPROM_DS24XXX=y CONFIG_FAT_WRITE=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig index 89393a979e..f60b6b5bc9 100644 --- a/configs/sama5d4_xplained_mmc_defconfig +++ b/configs/sama5d4_xplained_mmc_defconfig @@ -84,3 +84,8 @@ CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_DM_VIDEO=y CONFIG_ATMEL_HLCD=y +CONFIG_W1=y +CONFIG_W1_GPIO=y +CONFIG_W1_EEPROM=y +CONFIG_W1_EEPROM_DS24XXX=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig index 5387966316..3524dbffcf 100644 --- a/configs/sama5d4_xplained_nandflash_defconfig +++ b/configs/sama5d4_xplained_nandflash_defconfig @@ -80,3 +80,8 @@ CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_DM_VIDEO=y CONFIG_ATMEL_HLCD=y +CONFIG_W1=y +CONFIG_W1_GPIO=y +CONFIG_W1_EEPROM=y +CONFIG_W1_EEPROM_DS24XXX=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig index 39c86ecd9b..3f519cd503 100644 --- a/configs/sama5d4_xplained_spiflash_defconfig +++ b/configs/sama5d4_xplained_spiflash_defconfig @@ -84,3 +84,8 @@ CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_DM_VIDEO=y CONFIG_ATMEL_HLCD=y +CONFIG_W1=y +CONFIG_W1_GPIO=y +CONFIG_W1_EEPROM=y +CONFIG_W1_EEPROM_DS24XXX=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index b80e2eba9c..623eb267a2 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -39,6 +39,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_GPT_RENAME=y CONFIG_CMD_IDE=y CONFIG_CMD_I2C=y +CONFIG_CMD_OSD=y CONFIG_CMD_PCI=y CONFIG_CMD_READ=y CONFIG_CMD_REMOTEPROC=y @@ -188,6 +189,8 @@ CONFIG_CONSOLE_ROTATION=y CONFIG_CONSOLE_TRUETYPE=y CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y CONFIG_VIDEO_SANDBOX_SDL=y +CONFIG_OSD=y +CONFIG_SANDBOX_OSD=y CONFIG_WDT=y CONFIG_WDT_SANDBOX=y CONFIG_FS_CBFS=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 356c48b220..1c4a3330b4 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -41,6 +41,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_GPT_RENAME=y CONFIG_CMD_IDE=y CONFIG_CMD_I2C=y +CONFIG_CMD_OSD=y CONFIG_CMD_PCI=y CONFIG_CMD_READ=y CONFIG_CMD_REMOTEPROC=y @@ -194,6 +195,12 @@ CONFIG_CONSOLE_ROTATION=y CONFIG_CONSOLE_TRUETYPE=y CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y CONFIG_VIDEO_SANDBOX_SDL=y +CONFIG_W1=y +CONFIG_W1_GPIO=y +CONFIG_W1_EEPROM=y +CONFIG_W1_EEPROM_SANDBOX=y +CONFIG_OSD=y +CONFIG_SANDBOX_OSD=y CONFIG_WDT=y CONFIG_WDT_SANDBOX=y CONFIG_FS_CBFS=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index 1d3dd9f451..9f672e5063 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -31,6 +31,7 @@ CONFIG_CMD_DEMO=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y +CONFIG_CMD_OSD=y CONFIG_CMD_PCI=y CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_SF=y @@ -169,6 +170,8 @@ CONFIG_CONSOLE_ROTATION=y CONFIG_CONSOLE_TRUETYPE=y CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y CONFIG_VIDEO_SANDBOX_SDL=y +CONFIG_OSD=y +CONFIG_SANDBOX_OSD=y CONFIG_CMD_DHRYSTONE=y CONFIG_TPM=y CONFIG_LZ4=y diff --git a/configs/sandbox_noblk_defconfig b/configs/sandbox_noblk_defconfig index 5789cf3c8a..c8d33c7a1d 100644 --- a/configs/sandbox_noblk_defconfig +++ b/configs/sandbox_noblk_defconfig @@ -35,6 +35,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_IDE=y CONFIG_CMD_I2C=y +CONFIG_CMD_OSD=y CONFIG_CMD_PCI=y CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_SF=y @@ -168,6 +169,8 @@ CONFIG_CONSOLE_ROTATION=y CONFIG_CONSOLE_TRUETYPE=y CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y CONFIG_VIDEO_SANDBOX_SDL=y +CONFIG_OSD=y +CONFIG_SANDBOX_OSD=y CONFIG_FS_CBFS=y CONFIG_FS_CRAMFS=y CONFIG_CMD_DHRYSTONE=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index 3ee276f085..c019eeb65b 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -43,6 +43,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_IDE=y CONFIG_CMD_I2C=y +CONFIG_CMD_OSD=y CONFIG_CMD_PCI=y CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_SF=y @@ -187,6 +188,8 @@ CONFIG_CONSOLE_ROTATION=y CONFIG_CONSOLE_TRUETYPE=y CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y CONFIG_VIDEO_SANDBOX_SDL=y +CONFIG_OSD=y +CONFIG_SANDBOX_OSD=y CONFIG_FS_CBFS=y CONFIG_FS_CRAMFS=y CONFIG_CMD_DHRYSTONE=y diff --git a/doc/device-tree-bindings/chosen.txt b/doc/device-tree-bindings/chosen.txt index da7b4e6c45..86c533ad6d 100644 --- a/doc/device-tree-bindings/chosen.txt +++ b/doc/device-tree-bindings/chosen.txt @@ -83,3 +83,24 @@ of where said later stage was booted from. You should not define this property yourself in the device-tree, as it may be overwritten without warning. + +firmware-loader property +------------------------ +Multiple file system firmware loader nodes could be defined in device trees for +multiple storage type and their default partition, then a property +"firmware-loader" can be used to pass default firmware loader +node(default storage type) to the firmware loader driver. + +Example +------- +/ { + chosen { + firmware-loader = &fs_loader0; + }; + + fs_loader0: fs-loader@0 { + u-boot,dm-pre-reloc; + compatible = "u-boot,fs-loader"; + phandlepart = <&mmc 1>; + }; +}; diff --git a/doc/device-tree-bindings/misc/fs_loader.txt b/doc/device-tree-bindings/misc/fs_loader.txt new file mode 100644 index 0000000000..884fbf47c0 --- /dev/null +++ b/doc/device-tree-bindings/misc/fs_loader.txt @@ -0,0 +1,48 @@ +* File system firmware loader + +Required properties: +-------------------- + +- compatible: should contain "u-boot,fs-loader" +- phandlepart: which block storage device and partition the image loading from, + this property is required for mmc, usb and sata. This is unsigned + 32-bit array. For example phandlepart=<&mmc_0 1>, meaning use + that MMC0 node pointer, partition 1. +- mdtpart: which partition of ubi the image loading from, this property is + required for ubi and mounting. +- ubivol: which volume of ubi the image loading from, this property is required + for ubi and mounting. + +Example of storage device and partition search set for mmc, usb, sata and +ubi in device tree source as shown in below: + + Example of storage type and device partition search set for mmc, usb, + sata and ubi as shown in below: + Example for mmc: + fs_loader0: fs-loader@0 { + u-boot,dm-pre-reloc; + compatible = "u-boot,fs-loader"; + phandlepart = <&mmc_0 1>; + }; + + Example for usb: + fs_loader1: fs-loader@1 { + u-boot,dm-pre-reloc; + compatible = "u-boot,fs-loader"; + phandlepart = <&usb0 1>; + }; + + Example for sata: + fs_loader2: fs-loader@2 { + u-boot,dm-pre-reloc; + compatible = "u-boot,fs-loader"; + phandlepart = <&sata0 1>; + }; + + Example for ubi: + fs_loader3: fs-loader@3 { + u-boot,dm-pre-reloc; + compatible = "u-boot,fs-loader"; + mtdpart = "UBI", + ubivol = "ubi0"; + }; diff --git a/doc/device-tree-bindings/video/osd/gdsys,ihs_video_out.txt b/doc/device-tree-bindings/video/osd/gdsys,ihs_video_out.txt new file mode 100644 index 0000000000..d7aacc827e --- /dev/null +++ b/doc/device-tree-bindings/video/osd/gdsys,ihs_video_out.txt @@ -0,0 +1,23 @@ +* Guntermann & Drunck Integrated Hardware Systems OSD + +Required properties: +- compatible: "gdsys,ihs_video_out" +- reg: A combination of three register spaces: + - Register base for the video registers + - Register base for the OSD registers + - Address of the OSD video memory +- mode: The initial resolution and frequency: "1024_768_60", "720_400_70", or + "640_480_70" +- clk_gen: phandle to the pixel clock generator +- dp_tx: phandle to the display associated with the OSD + +Example: + +fpga0_video0 { + compatible = "gdsys,ihs_video_out"; + reg = <0x100 0x40 + 0x180 0x20 + 0x1000 0x1000>; + dp_tx = <&fpga0_dp_video0>; + clk_gen = <&fpga0_video0_clkgen>; +}; diff --git a/doc/device-tree-bindings/w1-eeprom/ds24xxx.txt b/doc/device-tree-bindings/w1-eeprom/ds24xxx.txt new file mode 100644 index 0000000000..2e91be93b7 --- /dev/null +++ b/doc/device-tree-bindings/w1-eeprom/ds24xxx.txt @@ -0,0 +1,37 @@ +Maxim DS24 families driver device binding - one wire protocol EEPROMS from Maxim +======================= + +This memory needs to be connected to a onewire bus, as a child node. +The bus will read the device serial number and match this node with a found +device on the bus +Also check doc/device-tree-bindings/w1 for onewire bus drivers + +Driver: +- drivers/w1-eeprom/ds24xxx.c + +Software ds24xxx device-tree node properties: +Required: +* compatible = "maxim,ds24b33" +or +* compatible = "maxim,ds2431" +Further memories can be added. + +Optional: +* none + +Example: + eeprom1: eeprom@0 { + compatible = "maxim,ds24xxx"; + } + +Example with parent bus: + +onewire_tm: onewire { + compatible = "w1-gpio"; + gpios = <&pioA 32 0>; + + eeprom1: eeprom@0 { + compatible = "maxim,ds24xxx"; + } +}; + diff --git a/doc/device-tree-bindings/w1-eeprom/eep_sandbox.txt b/doc/device-tree-bindings/w1-eeprom/eep_sandbox.txt new file mode 100644 index 0000000000..82bb5899af --- /dev/null +++ b/doc/device-tree-bindings/w1-eeprom/eep_sandbox.txt @@ -0,0 +1,34 @@ +Onewire EEPROM sandbox driver device binding - one wire protocol sandbox EEPROM +======================= + +This memory needs to be connected to a onewire bus, as a child node. +The bus will read the device serial number and match this node with a found +device on the bus +Also check doc/device-tree-bindings/w1 for onewire bus drivers + +Driver: +- drivers/w1-eeprom/eep_sandbox.c + +Software ds24xxx device-tree node properties: +Required: +* compatible = "sandbox,w1-eeprom" + +Optional: +* none + +Example: + eeprom1: eeprom@0 { + compatible = "sandbox,w1-eeprom"; + } + +Example with parent bus: + +onewire_tm: onewire { + compatible = "w1-gpio"; + gpios = <&gpio_a 8>; + + eeprom1: eeprom@0 { + compatible = "sandbox,w1-eeprom"; + } +}; + diff --git a/doc/device-tree-bindings/w1/w1-gpio.txt b/doc/device-tree-bindings/w1/w1-gpio.txt new file mode 100644 index 0000000000..5a582448e4 --- /dev/null +++ b/doc/device-tree-bindings/w1/w1-gpio.txt @@ -0,0 +1,40 @@ +W1 gpio device binding - one wire protocol over bitbanged gpio +======================= + + +Child nodes are required in device tree. The driver will detect +the devices serial number and then search in the child nodes in the device tree +for the proper node and try to match it with the device. + +Also check doc/device-tree-bindings/w1-eeprom for possible child nodes drivers + +Driver: +- drivers/w1/w1-gpio.c + +Software w1 device-tree node properties: +Required: +* compatible = "w1-gpio"; +* gpios = <...>; + This is the gpio used for one wire protocol, using bitbanging + +Optional: +* none + +Example: + +onewire_tm: onewire { + compatible = "w1-gpio"; + gpios = <&pioA 32 0>; +}; + +Example with child: + +onewire_tm: onewire { + compatible = "w1-gpio"; + gpios = <&pioA 32 0>; + + eeprom1: eeprom@0 { + compatible = "maxim,ds24xxx"; + } +}; + diff --git a/doc/driver-model/fs_firmware_loader.txt b/doc/driver-model/fs_firmware_loader.txt new file mode 100644 index 0000000000..290915a959 --- /dev/null +++ b/doc/driver-model/fs_firmware_loader.txt @@ -0,0 +1,133 @@ +# Copyright (C) 2018 Intel Corporation <www.intel.com> +# +# SPDX-License-Identifier: GPL-2.0 + +Introduction +============ + +This is file system firmware loader for U-Boot framework, which has very close +to some Linux Firmware API. For the details of Linux Firmware API, you can refer +to https://01.org/linuxgraphics/gfx-docs/drm/driver-api/firmware/index.html. + +File system firmware loader can be used to load whatever(firmware, image, +and binary) from the storage device in file system format into target location +such as memory, then consumer driver such as FPGA driver can program FPGA image +from the target location into FPGA. + +To enable firmware loader, CONFIG_FS_LOADER need to be set at +<board_name>_defconfig such as "CONFIG_FS_LOADER=y". + +Firmware Loader API core features +--------------------------------- + +Firmware storage device described in device tree source +------------------------------------------------------- + For passing data like storage device phandle and partition where the + firmware loading from to the firmware loader driver, those data could be + defined in fs-loader node as shown in below: + + Example for block device: + fs_loader0: fs-loader@0 { + u-boot,dm-pre-reloc; + compatible = "u-boot,fs-loader"; + phandlepart = <&mmc 1>; + }; + + <&mmc 1> means block storage device pointer and its partition. + + Above example is a description for block storage, but for UBI storage + device, it can be described in FDT as shown in below: + + Example for ubi: + fs_loader1: fs-loader@1 { + u-boot,dm-pre-reloc; + compatible = "u-boot,fs-loader"; + mtdpart = "UBI", + ubivol = "ubi0"; + }; + + Then, firmware_loader property would be set with the path of fs_loader + node under /chosen node such as: + /{ + chosen { + firmware_loader = &fs_loader0; + }; + }; + + However, this driver is also designed to support U-boot environment + variables, so all these data from FDT can be overwritten + through the U-boot environment variable during run time. + For examples: + "storage_interface" - Storage interface, it can be "mmc", "usb", "sata" + or "ubi". + "fw_dev_part" - Block device number and its partition, it can be "0:1". + "fw_ubi_mtdpart" - UBI device mtd partition, it can be "UBI". + "fw_ubi_volume" - UBI volume, it can be "ubi0". + + When above environment variables are set, environment values would be + used instead of data from FDT. + The benefit of this design allows user to change storage attribute data + at run time through U-boot console and saving the setting as default + environment values in the storage for the next power cycle, so no + compilation is required for both driver and FDT. + +File system firmware Loader API +------------------------------- + +int request_firmware_into_buf(struct device_platdata *plat, + const char *name, + void *buf, size_t size, u32 offset, + struct firmware **firmwarep) +-------------------------------------------------------------------- +Load firmware into a previously allocated buffer + +Parameters: + +1. struct device_platdata *plat + Platform data such as storage and partition firmware loading from + +2. const char *name + name of firmware file + +3. void *buf + address of buffer to load firmware into + +4. size_t size + size of buffer + +5. u32 offset + offset of a file for start reading into buffer + +6. struct firmware **firmwarep + pointer to firmware image + +return: + size of total read + -ve when error + +Description: + The firmware is loaded directly into the buffer pointed to by buf and + the @firmwarep data member is pointed at buf + +Note: Memory would be allocated for firmware image, hence user should + free() *firmwarep and *firmwarep->priv structs after usage of + request_firmware_into_buf(), otherwise it will always leak memory + while subsequent calls of request_firmware_into_buf() with the same + *firmwarep argument. Those arguments can be free through calling API + below release_firmware(); + +Example of creating firmware loader instance and calling +request_firmware_into_buf API: + if (uclass_get_device(UCLASS_FS_FIRMWARE_LOADER, 0, &dev)) { + request_firmware_into_buf(dev->plat, filename, buffer_location, + buffer_size, offset_ofreading, &fw); + } + +void release_firmware(struct firmware *firmware) +------------------------------------------------ +Release the resource associated with a firmware image + +Parameters: + +1. struct firmware *firmware + Firmware resource to release diff --git a/drivers/Kconfig b/drivers/Kconfig index 64ba5bf25f..11b88a1e1a 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -76,6 +76,8 @@ source "drivers/power/Kconfig" source "drivers/pwm/Kconfig" +source "drivers/qe/Kconfig" + source "drivers/ram/Kconfig" source "drivers/remoteproc/Kconfig" @@ -108,6 +110,10 @@ source "drivers/usb/Kconfig" source "drivers/video/Kconfig" +source "drivers/w1/Kconfig" + +source "drivers/w1-eeprom/Kconfig" + source "drivers/watchdog/Kconfig" config PHYS_TO_BUS diff --git a/drivers/Makefile b/drivers/Makefile index 764f51d746..091b5e8119 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -106,6 +106,8 @@ obj-y += smem/ obj-y += soc/ obj-y += thermal/ obj-y += axi/ +obj-$(CONFIG_W1) += w1/ +obj-$(CONFIG_W1_EEPROM) += w1-eeprom/ obj-$(CONFIG_MACH_PIC32) += ddr/microchip/ endif diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sata_ceva.c index 047cff7f83..65896d1705 100644 --- a/drivers/ata/sata_ceva.c +++ b/drivers/ata/sata_ceva.c @@ -81,13 +81,24 @@ #define CEVA_TRANS_CFG 0x08000029 #define CEVA_AXICC_CFG 0x3fffffff +/* for ls1021a */ +#define LS1021_AHCI_VEND_AXICC 0xC0 +#define LS1021_CEVA_PHY2_CFG 0x28183414 +#define LS1021_CEVA_PHY3_CFG 0x0e080e06 +#define LS1021_CEVA_PHY4_CFG 0x064a080b +#define LS1021_CEVA_PHY5_CFG 0x2aa86470 + /* ecc addr-val pair */ #define ECC_DIS_ADDR_CH2 0x80000000 -#define ECC_DIS_VAL_CH2 0x20140520 +#define ECC_DIS_VAL_CH2 0x20140520 +#define SATA_ECC_REG_ADDR 0x20220520 +#define SATA_ECC_DISABLE 0x00020000 enum ceva_soc { CEVA_1V84, CEVA_LS1012A, + CEVA_LS1021A, + CEVA_LS1043A, }; struct ceva_sata_priv { @@ -113,7 +124,20 @@ static int ceva_init_sata(struct ceva_sata_priv *priv) writel(tmp, base + AHCI_VEND_PTC); break; + case CEVA_LS1021A: + writel(SATA_ECC_DISABLE, SATA_ECC_REG_ADDR); + writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG); + writel(LS1021_CEVA_PHY2_CFG, base + AHCI_VEND_PP2C); + writel(LS1021_CEVA_PHY3_CFG, base + AHCI_VEND_PP3C); + writel(LS1021_CEVA_PHY4_CFG, base + AHCI_VEND_PP4C); + writel(LS1021_CEVA_PHY5_CFG, base + AHCI_VEND_PP5C); + writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC); + if (priv->flag & FLAG_COHERENT) + writel(CEVA_AXICC_CFG, base + LS1021_AHCI_VEND_AXICC); + break; + case CEVA_LS1012A: + case CEVA_LS1043A: writel(ECC_DIS_ADDR_CH2, ECC_DIS_VAL_CH2); writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG); writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC); @@ -144,6 +168,8 @@ static int sata_ceva_probe(struct udevice *dev) static const struct udevice_id sata_ceva_ids[] = { { .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 }, { .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A }, + { .compatible = "fsl,ls1021a-ahci", .data = CEVA_LS1021A }, + { .compatible = "fsl,ls1043a-ahci", .data = CEVA_LS1043A }, { } }; diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c index 9e0c823969..facf52711c 100644 --- a/drivers/block/blk-uclass.c +++ b/drivers/block/blk-uclass.c @@ -132,6 +132,29 @@ struct blk_desc *blk_get_devnum_by_typename(const char *if_typename, int devnum) } /** + * blk_get_by_device() - Get the block device descriptor for the given device + * @dev: Instance of a storage device + * + * Return: With block device descriptor on success , NULL if there is no such + * block device. + */ +struct blk_desc *blk_get_by_device(struct udevice *dev) +{ + struct udevice *child_dev, *next; + + device_foreach_child_safe(child_dev, next, dev) { + if (device_get_uclass_id(child_dev) != UCLASS_BLK) + continue; + + return dev_get_uclass_platdata(child_dev); + } + + debug("%s: No block device found\n", __func__); + + return NULL; +} + +/** * get_desc() - Get the block device descriptor for the given device number * * @if_type: Interface type diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index c996d6574b..7853a7a9d3 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -68,6 +68,13 @@ config CLK_HSDK help Enable this to support the cgu clocks on Synopsys ARC HSDK +config CLK_VEXPRESS_OSC + bool "Enable driver for Arm Versatile Express OSC clock generators" + depends on CLK && VEXPRESS_CONFIG + help + This clock driver adds support for clock generators present on + Arm Versatile Express platforms. + config CLK_ZYNQ bool "Enable clock driver support for Zynq" depends on CLK && ARCH_ZYNQ diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 11468f2ee6..8bc9f520c1 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_CLK_RENESAS) += renesas/ obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o obj-$(CONFIG_CLK_UNIPHIER) += uniphier/ +obj-$(CONFIG_CLK_VEXPRESS_OSC) += clk_vexpress_osc.o obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o obj-$(CONFIG_ICS8N3QV01) += ics8n3qv01.o diff --git a/drivers/clk/clk_vexpress_osc.c b/drivers/clk/clk_vexpress_osc.c new file mode 100644 index 0000000000..7fef4b2e31 --- /dev/null +++ b/drivers/clk/clk_vexpress_osc.c @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Arm Ltd + * Author: Liviu Dudau <liviu.dudau@foss.arm.com> + * + */ +#define DEBUG +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <dm/lists.h> +#include <errno.h> +#include <misc.h> + +#define CLK_FUNCTION BIT(20) + +struct vexpress_osc_clk_priv { + u8 osc; + ulong rate_min; + ulong rate_max; +}; + +static ulong vexpress_osc_clk_get_rate(struct clk *clk) +{ + int err; + u32 data; + struct udevice *vexpress_cfg = dev_get_parent(clk->dev); + struct vexpress_osc_clk_priv *priv = dev_get_priv(clk->dev); + + data = CLK_FUNCTION | priv->osc; + err = misc_read(vexpress_cfg, 0, &data, sizeof(data)); + if (err) + return err; + + return data; +} + +#ifndef CONFIG_SPL_BUILD +static ulong vexpress_osc_clk_set_rate(struct clk *clk, ulong rate) +{ + int err; + u32 buffer[2]; + struct udevice *vexpress_cfg = dev_get_parent(clk->dev); + struct vexpress_osc_clk_priv *priv = dev_get_priv(clk->dev); + + if (rate < priv->rate_min || rate > priv->rate_max) + return -EINVAL; + + /* + * we are sending the parent the info about the oscillator + * and the value we want to set + */ + buffer[0] = CLK_FUNCTION | priv->osc; + buffer[1] = rate; + err = misc_write(vexpress_cfg, 0, buffer, 2 * sizeof(u32)); + if (err) + return err; + + return rate; +} +#endif + +static struct clk_ops vexpress_osc_clk_ops = { + .get_rate = vexpress_osc_clk_get_rate, +#ifndef CONFIG_SPL_BUILD + .set_rate = vexpress_osc_clk_set_rate, +#endif +}; + +static int vexpress_osc_clk_probe(struct udevice *dev) +{ + struct vexpress_osc_clk_priv *priv = dev_get_priv(dev); + u32 values[2]; + int err; + + err = dev_read_u32_array(dev, "freq-range", values, 2); + if (err) + return err; + priv->rate_min = values[0]; + priv->rate_max = values[1]; + + err = dev_read_u32_array(dev, "arm,vexpress-sysreg,func", values, 2); + if (err) + return err; + + if (values[0] != 1) { + dev_err(dev, "Invalid VExpress function for clock, must be '1'"); + return -EINVAL; + } + priv->osc = values[1]; + debug("clk \"%s%d\", min freq %luHz, max freq %luHz\n", dev->name, + priv->osc, priv->rate_min, priv->rate_max); + + return 0; +} + +static const struct udevice_id vexpress_osc_clk_ids[] = { + { .compatible = "arm,vexpress-osc", }, + {} +}; + +U_BOOT_DRIVER(vexpress_osc_clk) = { + .name = "vexpress_osc_clk", + .id = UCLASS_CLK, + .of_match = vexpress_osc_clk_ids, + .ops = &vexpress_osc_clk_ops, + .priv_auto_alloc_size = sizeof(struct vexpress_osc_clk_priv), + .probe = vexpress_osc_clk_probe, +}; diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index bfa5c91687..b0fb73f692 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -295,4 +295,13 @@ config MPC83XX_SERDES help Support for serdes found on MPC83xx SoCs. +config FS_LOADER + bool "Enable loader driver for file system" + help + This is file system generic loader which can be used to load + the file image from the storage into target such as memory. + + The consumer driver would then use this loader to program whatever, + ie. the FPGA device. + endmenu diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index da4666fdfc..acf24c44fa 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -56,3 +56,4 @@ obj-$(CONFIG_SYS_DPAA_QBMAN) += fsl_portals.o obj-$(CONFIG_GDSYS_IOEP) += gdsys_ioep.o obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o +obj-$(CONFIG_FS_LOADER) += fs_loader.o diff --git a/drivers/misc/fs_loader.c b/drivers/misc/fs_loader.c new file mode 100644 index 0000000000..5fe642b4be --- /dev/null +++ b/drivers/misc/fs_loader.c @@ -0,0 +1,295 @@ +/* + * Copyright (C) 2018 Intel Corporation <www.intel.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <blk.h> +#include <fs.h> +#include <fs_loader.h> +#include <linux/string.h> +#include <mapmem.h> +#include <malloc.h> +#include <spl.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct firmware_priv { + const char *name; /* Filename */ + u32 offset; /* Offset of reading a file */ +}; + +#ifdef CONFIG_CMD_UBIFS +static int mount_ubifs(char *mtdpart, char *ubivol) +{ + int ret = ubi_part(mtdpart, NULL); + + if (ret) { + debug("Cannot find mtd partition %s\n", mtdpart); + return ret; + } + + return cmd_ubifs_mount(ubivol); +} + +static int umount_ubifs(void) +{ + return cmd_ubifs_umount(); +} +#else +static int mount_ubifs(char *mtdpart, char *ubivol) +{ + debug("Error: Cannot load image: no UBIFS support\n"); + return -ENOSYS; +} +#endif + +static int select_fs_dev(struct device_platdata *plat) +{ + int ret; + + if (plat->phandlepart.phandle) { + ofnode node; + + node = ofnode_get_by_phandle(plat->phandlepart.phandle); + + int of_offset = ofnode_to_offset(node); + + struct udevice *dev; + + ret = device_get_global_by_of_offset(of_offset, &dev); + if (!ret) { + struct blk_desc *desc = blk_get_by_device(dev); + if (desc) { + ret = fs_set_blk_dev_with_part(desc, + plat->phandlepart.partition); + } else { + debug("%s: No device found\n", __func__); + return -ENODEV; + } + } + } else if (plat->mtdpart && plat->ubivol) { + ret = mount_ubifs(plat->mtdpart, plat->ubivol); + if (ret) + return ret; + + ret = fs_set_blk_dev("ubi", NULL, FS_TYPE_UBIFS); + } else { + debug("Error: unsupported storage device.\n"); + return -ENODEV; + } + + if (ret) + debug("Error: could not access storage.\n"); + + return ret; +} + +/** + * _request_firmware_prepare - Prepare firmware struct. + * + * @name: Name of firmware file. + * @dbuf: Address of buffer to load firmware into. + * @size: Size of buffer. + * @offset: Offset of a file for start reading into buffer. + * @firmwarep: Pointer to pointer to firmware image. + * + * Return: Negative value if fail, 0 for successful. + */ +static int _request_firmware_prepare(const char *name, void *dbuf, + size_t size, u32 offset, + struct firmware **firmwarep) +{ + if (!name || name[0] == '\0') + return -EINVAL; + + /* No memory allocation is required if *firmwarep is allocated */ + if (!(*firmwarep)) { + (*firmwarep) = calloc(1, sizeof(struct firmware)); + if (!(*firmwarep)) + return -ENOMEM; + + (*firmwarep)->priv = calloc(1, sizeof(struct firmware_priv)); + if (!(*firmwarep)->priv) { + free(*firmwarep); + return -ENOMEM; + } + } else if (!(*firmwarep)->priv) { + (*firmwarep)->priv = calloc(1, sizeof(struct firmware_priv)); + if (!(*firmwarep)->priv) { + free(*firmwarep); + return -ENOMEM; + } + } + + ((struct firmware_priv *)((*firmwarep)->priv))->name = name; + ((struct firmware_priv *)((*firmwarep)->priv))->offset = offset; + (*firmwarep)->data = dbuf; + (*firmwarep)->size = size; + + return 0; +} + +/** + * release_firmware - Release the resource associated with a firmware image + * @firmware: Firmware resource to release + */ +void release_firmware(struct firmware *firmware) +{ + if (firmware) { + if (firmware->priv) { + free(firmware->priv); + firmware->priv = NULL; + } + free(firmware); + } +} + +/** + * fw_get_filesystem_firmware - load firmware into an allocated buffer. + * @plat: Platform data such as storage and partition firmware loading from. + * @firmware: pointer to firmware image. + * + * Return: Size of total read, negative value when error. + */ +static int fw_get_filesystem_firmware(struct device_platdata *plat, + struct firmware *firmware) +{ + struct firmware_priv *fw_priv = NULL; + loff_t actread; + char *storage_interface, *dev_part, *ubi_mtdpart, *ubi_volume; + int ret; + + storage_interface = env_get("storage_interface"); + dev_part = env_get("fw_dev_part"); + ubi_mtdpart = env_get("fw_ubi_mtdpart"); + ubi_volume = env_get("fw_ubi_volume"); + + if (storage_interface && dev_part) { + ret = fs_set_blk_dev(storage_interface, dev_part, FS_TYPE_ANY); + } else if (storage_interface && ubi_mtdpart && ubi_volume) { + ret = mount_ubifs(ubi_mtdpart, ubi_volume); + if (ret) + return ret; + + if (!strcmp("ubi", storage_interface)) + ret = fs_set_blk_dev(storage_interface, NULL, + FS_TYPE_UBIFS); + else + ret = -ENODEV; + } else { + ret = select_fs_dev(plat); + } + + if (ret) + goto out; + + fw_priv = firmware->priv; + + ret = fs_read(fw_priv->name, (ulong)map_to_sysmem(firmware->data), + fw_priv->offset, firmware->size, &actread); + if (ret) { + debug("Error: %d Failed to read %s from flash %lld != %d.\n", + ret, fw_priv->name, actread, firmware->size); + } else { + ret = actread; + } + +out: +#ifdef CONFIG_CMD_UBIFS + umount_ubifs(); +#endif + return ret; +} + +/** + * request_firmware_into_buf - Load firmware into a previously allocated buffer. + * @plat: Platform data such as storage and partition firmware loading from. + * @name: Name of firmware file. + * @buf: Address of buffer to load firmware into. + * @size: Size of buffer. + * @offset: Offset of a file for start reading into buffer. + * @firmwarep: Pointer to firmware image. + * + * The firmware is loaded directly into the buffer pointed to by @buf and + * the @firmwarep data member is pointed at @buf. + * + * Return: Size of total read, negative value when error. + */ +int request_firmware_into_buf(struct device_platdata *plat, + const char *name, + void *buf, size_t size, u32 offset, + struct firmware **firmwarep) +{ + int ret; + + if (!plat) + return -EINVAL; + + ret = _request_firmware_prepare(name, buf, size, offset, firmwarep); + if (ret < 0) /* error */ + return ret; + + ret = fw_get_filesystem_firmware(plat, *firmwarep); + + return ret; +} + +static int fs_loader_ofdata_to_platdata(struct udevice *dev) +{ + const char *fs_loader_path; + u32 phandlepart[2]; + + fs_loader_path = ofnode_get_chosen_prop("firmware-loader"); + + if (fs_loader_path) { + ofnode fs_loader_node; + + fs_loader_node = ofnode_path(fs_loader_path); + if (ofnode_valid(fs_loader_node)) { + struct device_platdata *plat; + plat = dev->platdata; + + if (!ofnode_read_u32_array(fs_loader_node, + "phandlepart", + phandlepart, 2)) { + plat->phandlepart.phandle = phandlepart[0]; + plat->phandlepart.partition = phandlepart[1]; + } + + plat->mtdpart = (char *)ofnode_read_string( + fs_loader_node, "mtdpart"); + + plat->ubivol = (char *)ofnode_read_string( + fs_loader_node, "ubivol"); + } + } + + return 0; +} + +static int fs_loader_probe(struct udevice *dev) +{ + return 0; +}; + +static const struct udevice_id fs_loader_ids[] = { + { .compatible = "u-boot,fs-loader"}, + { } +}; + +U_BOOT_DRIVER(fs_loader) = { + .name = "fs-loader", + .id = UCLASS_FS_FIRMWARE_LOADER, + .of_match = fs_loader_ids, + .probe = fs_loader_probe, + .ofdata_to_platdata = fs_loader_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct device_platdata), +}; + +UCLASS_DRIVER(fs_loader) = { + .id = UCLASS_FS_FIRMWARE_LOADER, + .name = "fs-loader", +}; diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c index d3137680ad..45eed22f6e 100644 --- a/drivers/misc/fsl_portals.c +++ b/drivers/misc/fsl_portals.c @@ -49,7 +49,7 @@ void setup_qbman_portals(void) out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn); } #else -#ifdef CONFIG_ARCH_LS1046A +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) int i; for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) { @@ -197,7 +197,7 @@ void fdt_fixup_qportals(void *blob) char compat[64]; int compat_len; -#ifdef CONFIG_ARCH_LS1046A +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) int smmu_ph = fdt_get_smmu_phandle(blob); #endif @@ -211,7 +211,8 @@ void fdt_fixup_qportals(void *blob) off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal"); while (off != -FDT_ERR_NOTFOUND) { -#if defined(CONFIG_PPC) || defined(CONFIG_ARCH_LS1046A) +#if defined(CONFIG_PPC) || defined(CONFIG_ARCH_LS1043A) || \ +defined(CONFIG_ARCH_LS1046A) #ifdef CONFIG_FSL_CORENET u32 liodns[2]; #endif @@ -226,7 +227,7 @@ void fdt_fixup_qportals(void *blob) int j; #endif -#endif /* CONFIG_PPC || CONFIG_ARCH_LS1046A */ +#endif /* CONFIG_PPC || CONFIG_ARCH_LS1043A || CONFIG_ARCH_LS1046A */ err = fdt_setprop(blob, off, "compatible", compat, compat_len); if (err < 0) goto err; @@ -275,7 +276,7 @@ void fdt_fixup_qportals(void *blob) goto err; #endif #else -#ifdef CONFIG_ARCH_LS1046A +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) if (smmu_ph >= 0) { u32 icids[3]; diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 8ab56d247d..ec853d063f 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -83,7 +83,6 @@ struct omap_hsmmc_data { #if CONFIG_IS_ENABLED(DM_MMC) struct gpio_desc cd_gpio; /* Change Detect GPIO */ struct gpio_desc wp_gpio; /* Write Protect GPIO */ - bool cd_inverted; #else int cd_gpio; int wp_gpio; @@ -1368,17 +1367,15 @@ static int omap_hsmmc_set_ios(struct udevice *dev) #if CONFIG_IS_ENABLED(DM_MMC) static int omap_hsmmc_getcd(struct udevice *dev) { - struct omap_hsmmc_data *priv = dev_get_priv(dev); int value = -1; #if CONFIG_IS_ENABLED(DM_GPIO) + struct omap_hsmmc_data *priv = dev_get_priv(dev); value = dm_gpio_get_value(&priv->cd_gpio); #endif /* if no CD return as 1 */ if (value < 0) return 1; - if (priv->cd_inverted) - return !value; return value; } @@ -1860,10 +1857,6 @@ static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev) } #endif -#ifdef OMAP_HSMMC_USE_GPIO - plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted"); -#endif - return 0; } #endif @@ -1892,9 +1885,6 @@ static int omap_hsmmc_probe(struct udevice *dev) priv->base_addr = plat->base_addr; priv->controller_flags = plat->controller_flags; priv->hw_rev = plat->hw_rev; -#ifdef OMAP_HSMMC_USE_GPIO - priv->cd_inverted = plat->cd_inverted; -#endif #ifdef CONFIG_BLK mmc = plat->mmc; diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index 3327073bf1..c5cf188f05 100644 --- a/drivers/net/fm/fm.c +++ b/drivers/net/fm/fm.c @@ -402,7 +402,7 @@ int fm_init_common(int index, struct ccsr_fman *reg) printf("\nMMC read: dev # %u, block # %u, count %u ...\n", dev, blk, cnt); mmc_init(mmc); - (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, + (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr); } #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE) diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c index 147d0437c5..f896e80b6d 100644 --- a/drivers/net/fm/init.c +++ b/drivers/net/fm/init.c @@ -328,7 +328,8 @@ void fdt_fixup_fman_ethernet(void *blob) ft_fixup_port(blob, &fm_info[i], "fsl,fman-1g-mac"); } else { - if (ft_fixup_port(blob, &fm_info[i], "fsl,fman-tgec")) + if (ft_fixup_port(blob, &fm_info[i], "fsl,fman-xgec") && + ft_fixup_port(blob, &fm_info[i], "fsl,fman-tgec")) ft_fixup_port(blob, &fm_info[i], "fsl,fman-10g-mac"); } diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index 940025a467..d9a897dc86 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -2,6 +2,7 @@ /* * Copyright 2014 Freescale Semiconductor, Inc. * Copyright 2017 NXP + * Copyright 2017-2018 NXP */ #include <common.h> #include <errno.h> @@ -29,6 +30,7 @@ #define MC_BOOT_ENV_VAR "mcinitcmd" DECLARE_GLOBAL_DATA_PTR; +static int mc_memset_resv_ram; static int mc_boot_status = -1; static int mc_dpl_applied = -1; #ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET @@ -278,6 +280,40 @@ static int mc_fixup_dpl_mac_addr(void *blob, int dpmac_id, MC_FIXUP_DPL); } +void fdt_fsl_mc_fixup_iommu_map_entry(void *blob) +{ + u32 *prop; + u32 iommu_map[4]; + int offset; + int lenp; + + /* find fsl-mc node */ + offset = fdt_path_offset(blob, "/soc/fsl-mc"); + if (offset < 0) + offset = fdt_path_offset(blob, "/fsl-mc"); + if (offset < 0) { + printf("%s: fsl-mc: ERR: fsl-mc node not found in DT, err %d\n", + __func__, offset); + return; + } + + prop = fdt_getprop_w(blob, offset, "iommu-map", &lenp); + if (!prop) { + debug("%s: fsl-mc: ERR: missing iommu-map in fsl-mc bus node\n", + __func__); + return; + } + + iommu_map[0] = cpu_to_fdt32(FSL_DPAA2_STREAM_ID_START); + iommu_map[1] = *++prop; + iommu_map[2] = cpu_to_fdt32(FSL_DPAA2_STREAM_ID_START); + iommu_map[3] = cpu_to_fdt32(FSL_DPAA2_STREAM_ID_END - + FSL_DPAA2_STREAM_ID_START + 1); + + fdt_setprop_inplace(blob, offset, "iommu-map", + iommu_map, sizeof(iommu_map)); +} + static int mc_fixup_dpc_mac_addr(void *blob, int dpmac_id, struct eth_device *eth_dev) { @@ -810,6 +846,11 @@ u64 mc_get_dram_addr(void) { size_t mc_ram_size = mc_get_dram_block_size(); + if (!mc_memset_resv_ram || (get_mc_boot_status() < 0)) { + mc_memset_resv_ram = 1; + memset((void *)gd->arch.resv_ram, 0, mc_ram_size); + } + return (gd->arch.resv_ram + mc_ram_size - 1) & MC_RAM_BASE_ADDR_ALIGNMENT_MASK; } diff --git a/drivers/net/pfe_eth/pfe_mdio.c b/drivers/net/pfe_eth/pfe_mdio.c index b53edb741f..2dde9e7ac8 100644 --- a/drivers/net/pfe_eth/pfe_mdio.c +++ b/drivers/net/pfe_eth/pfe_mdio.c @@ -162,7 +162,6 @@ static void pfe_configure_serdes(struct pfe_eth_dev *priv) if (gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500) sgmii_2500 = 1; - printf("%s %d\n", __func__, priv->gemac_port); /* PCS configuration done with corresponding GEMAC */ bus.priv = gem_info[priv->gemac_port].gemac_base; diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index e0822bb775..bcc8e22795 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -139,4 +139,12 @@ config MESON_GXL_USB_PHY This is the generic phy driver for the Amlogic Meson GXL USB2 and USB3 PHYS. +config MSM8916_USB_PHY + bool "Qualcomm MSM8916 USB PHY support" + depends on PHY + help + Support the USB PHY in msm8916 + + This PHY is found on qualcomm dragonboard410c development board. + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 178fb4530e..1e1e4ca11e 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -15,3 +15,4 @@ obj-$(CONFIG_STI_USB_PHY) += sti_usb_phy.o obj-$(CONFIG_PHY_RCAR_GEN2) += phy-rcar-gen2.o obj-$(CONFIG_PHY_STM32_USBPHYC) += phy-stm32-usbphyc.o obj-$(CONFIG_MESON_GXL_USB_PHY) += meson-gxl-usb2.o meson-gxl-usb3.o +obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o diff --git a/drivers/phy/msm8916-usbh-phy.c b/drivers/phy/msm8916-usbh-phy.c new file mode 100644 index 0000000000..2c90738fca --- /dev/null +++ b/drivers/phy/msm8916-usbh-phy.c @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Ramon Fried <ramon.fried@gmail.com> + */ + +#include <common.h> +#include <dm.h> +#include <generic-phy.h> +#include <usb/ehci-ci.h> +#include <usb/ulpi.h> +#include <asm/io.h> + +/* PHY viewport regs */ +#define ULPI_MISC_A_READ 0x96 +#define ULPI_MISC_A_SET 0x97 +#define ULPI_MISC_A_CLEAR 0x98 +#define ULPI_MISC_A_VBUSVLDEXT BIT(0) +#define ULPI_MISC_A_VBUSVLDEXTSEL BIT(1) +#define GEN2_SESS_VLD_CTRL_EN BIT(7) +#define SESS_VLD_CTRL BIT(25) + +struct msm_phy_priv { + void __iomem *regs; + struct usb_ehci *ehci; /* Start of IP core*/ + struct ulpi_viewport ulpi_vp; /* ULPI Viewport */ +}; + +static int msm_phy_power_on(struct phy *phy) +{ + struct msm_phy_priv *priv = dev_get_priv(phy->dev); + + /* Select and enable external configuration with USB PHY */ + ulpi_write(&priv->ulpi_vp, (u8 *)ULPI_MISC_A_SET, + ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT); + + return 0; +} + +static int msm_phy_power_off(struct phy *phy) +{ + struct msm_phy_priv *priv = dev_get_priv(phy->dev); + + /* Disable VBUS mimicing in the controller. */ + ulpi_write(&priv->ulpi_vp, (u8 *)ULPI_MISC_A_CLEAR, + ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT); + return 0; +} + +static int msm_phy_reset(struct phy *phy) +{ + struct msm_phy_priv *p = dev_get_priv(phy->dev); + + /* select ULPI phy */ + writel(PORT_PTS_ULPI, &p->ehci->portsc); + + /* Enable sess_vld */ + setbits_le32(&p->ehci->genconfig2, GEN2_SESS_VLD_CTRL_EN); + + /* Enable external vbus configuration in the LINK */ + setbits_le32(&p->ehci->usbcmd, SESS_VLD_CTRL); + + /* USB_OTG_HS_AHB_BURST */ + writel(0x0, &p->ehci->sbuscfg); + + /* USB_OTG_HS_AHB_MODE: HPROT_MODE */ + /* Bus access related config. */ + writel(0x08, &p->ehci->sbusmode); + + return 0; +} + +static int msm_phy_probe(struct udevice *dev) +{ + struct msm_phy_priv *priv = dev_get_priv(dev); + + priv->regs = dev_remap_addr(dev); + if (!priv->regs) + return -EINVAL; + + priv->ehci = (struct usb_ehci *)priv->regs; + priv->ulpi_vp.port_num = 0; + + /* Warning: this will not work if viewport address is > 64 bit due to + * ULPI design. + */ + priv->ulpi_vp.viewport_addr = (phys_addr_t)&priv->ehci->ulpi_viewpoint; + + return 0; +} + +static struct phy_ops msm_phy_ops = { + .power_on = msm_phy_power_on, + .power_off = msm_phy_power_off, + .reset = msm_phy_reset, +}; + +static const struct udevice_id msm_phy_ids[] = { + { .compatible = "qcom,apq8016-usbphy" }, + { } +}; + +U_BOOT_DRIVER(msm8916_usbphy) = { + .name = "msm8916_usbphy", + .id = UCLASS_PHY, + .of_match = msm_phy_ids, + .ops = &msm_phy_ops, + .probe = msm_phy_probe, + .priv_auto_alloc_size = sizeof(struct msm_phy_priv), +}; diff --git a/drivers/pinctrl/pinctrl-sandbox.c b/drivers/pinctrl/pinctrl-sandbox.c index 468fa2a7d0..755ac08bdf 100644 --- a/drivers/pinctrl/pinctrl-sandbox.c +++ b/drivers/pinctrl/pinctrl-sandbox.c @@ -14,6 +14,7 @@ static const char * const sandbox_pins[] = { "SDA", "TX", "RX", + "W1" }; static const char * const sandbox_groups[] = { @@ -21,12 +22,14 @@ static const char * const sandbox_groups[] = { "serial_a", "serial_b", "spi", + "w1", }; static const char * const sandbox_functions[] = { "i2c", "serial", "spi", + "w1", }; static const struct pinconf_param sandbox_conf_params[] = { diff --git a/drivers/qe/Kconfig b/drivers/qe/Kconfig new file mode 100644 index 0000000000..49a6e32b16 --- /dev/null +++ b/drivers/qe/Kconfig @@ -0,0 +1,12 @@ +# +# QUICC Engine Drivers +# +config U_QE + bool "Enable support for U QUICC Engine" + default y if (ARCH_LS1021A && !SD_BOOT && !NAND_BOOT && !QSPI_BOOT) \ + || (TARGET_T1024QDS) \ + || (TARGET_T1024RDB) \ + || (TARGET_T1040QDS && !NOBQFMAN) \ + || (TARGET_LS1043ARDB && !SPL_NO_QE && !NAND_BOOT && !QSPI_BOOT) + help + Choose this option to add support for U QUICC Engine. diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 7654df8008..7010bbc230 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -218,7 +218,7 @@ void u_qe_init(void) printf("\nMMC read: dev # %u, block # %u, count %u ...\n", dev, blk, cnt); mmc_init(mmc); - (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, + (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr); } #endif diff --git a/drivers/serial/serial_stm32.h b/drivers/serial/serial_stm32.h index ccafa31219..5549f8c536 100644 --- a/drivers/serial/serial_stm32.h +++ b/drivers/serial/serial_stm32.h @@ -37,7 +37,7 @@ struct stm32_uart_info stm32f4_info = { struct stm32_uart_info stm32f7_info = { .uart_enable_bit = 0, .stm32f4 = false, - .has_fifo = false, + .has_fifo = true, }; struct stm32_uart_info stm32h7_info = { diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 2b9dbf06b9..0a84f6850d 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -104,6 +104,10 @@ static struct usb_ep_ops ci_ep_ops = { .free_request = ci_ep_free_request, }; +__weak void ci_init_after_reset(struct ehci_ctrl *ctrl) +{ +} + /* Init values for USB endpoints. */ static const struct usb_ep ci_ep_init[5] = { [0] = { /* EP 0 */ @@ -887,6 +891,8 @@ static int ci_pullup(struct usb_gadget *gadget, int is_on) writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RST, &udc->usbcmd); udelay(200); + ci_init_after_reset(controller.ctrl); + writel((unsigned long)controller.epts, &udc->epinitaddr); /* select DEVICE mode */ @@ -900,7 +906,8 @@ static int ci_pullup(struct usb_gadget *gadget, int is_on) writel(0xffffffff, &udc->epflush); /* Turn on the USB connection by enabling the pullup resistor */ - writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RUN, &udc->usbcmd); + setbits_le32(&udc->usbcmd, USBCMD_ITC(MICRO_8FRAME) | + USBCMD_RUN); } else { udc_disconnect(); } diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index b4dd005651..a213c918bc 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -167,12 +167,11 @@ config USB_EHCI_MSM bool "Support for Qualcomm on-chip EHCI USB controller" depends on DM_USB select USB_ULPI_VIEWPORT + select MSM8916_USB_PHY default n ---help--- Enables support for the on-chip EHCI controller on Qualcomm Snapdragon SoCs. - This driver supports combination of Chipidea USB controller - and Synapsys USB PHY in host mode only. config USB_EHCI_PCI bool "Support for PCI-based EHCI USB controller" diff --git a/drivers/usb/host/ehci-msm.c b/drivers/usb/host/ehci-msm.c index 17bfa7c02f..5c257ccf4d 100644 --- a/drivers/usb/host/ehci-msm.c +++ b/drivers/usb/host/ehci-msm.c @@ -21,64 +21,19 @@ #include <linux/compat.h> #include "ehci.h" -/* PHY viewport regs */ -#define ULPI_MISC_A_READ 0x96 -#define ULPI_MISC_A_SET 0x97 -#define ULPI_MISC_A_CLEAR 0x98 -#define ULPI_MISC_A_VBUSVLDEXTSEL (1 << 1) -#define ULPI_MISC_A_VBUSVLDEXT (1 << 0) - -#define GEN2_SESS_VLD_CTRL_EN (1 << 7) - -#define SESS_VLD_CTRL (1 << 25) - struct msm_ehci_priv { struct ehci_ctrl ctrl; /* Needed by EHCI */ struct usb_ehci *ehci; /* Start of IP core*/ struct ulpi_viewport ulpi_vp; /* ULPI Viewport */ + struct phy phy; }; -int __weak board_prepare_usb(enum usb_init_type type) -{ - return 0; -} - -static void setup_usb_phy(struct msm_ehci_priv *priv) -{ - /* Select and enable external configuration with USB PHY */ - ulpi_write(&priv->ulpi_vp, (u8 *)ULPI_MISC_A_SET, - ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT); -} - -static void reset_usb_phy(struct msm_ehci_priv *priv) -{ - /* Disable VBUS mimicing in the controller. */ - ulpi_write(&priv->ulpi_vp, (u8 *)ULPI_MISC_A_CLEAR, - ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT); -} - - static int msm_init_after_reset(struct ehci_ctrl *dev) { struct msm_ehci_priv *p = container_of(dev, struct msm_ehci_priv, ctrl); struct usb_ehci *ehci = p->ehci; - /* select ULPI phy */ - writel(PORT_PTS_ULPI, &ehci->portsc); - setup_usb_phy(p); - - /* Enable sess_vld */ - setbits_le32(&ehci->genconfig2, GEN2_SESS_VLD_CTRL_EN); - - /* Enable external vbus configuration in the LINK */ - setbits_le32(&ehci->usbcmd, SESS_VLD_CTRL); - - /* USB_OTG_HS_AHB_BURST */ - writel(0x0, &ehci->sbuscfg); - - /* USB_OTG_HS_AHB_MODE: HPROT_MODE */ - /* Bus access related config. */ - writel(0x08, &ehci->sbusmode); + generic_phy_reset(&p->phy); /* set mode to host controller */ writel(CM_HOST, &ehci->usbmode); @@ -94,6 +49,7 @@ static int ehci_usb_probe(struct udevice *dev) { struct msm_ehci_priv *p = dev_get_priv(dev); struct usb_ehci *ehci = p->ehci; + struct usb_platdata *plat = dev_get_platdata(dev); struct ehci_hccr *hccr; struct ehci_hcor *hcor; int ret; @@ -102,11 +58,16 @@ static int ehci_usb_probe(struct udevice *dev) hcor = (struct ehci_hcor *)((phys_addr_t)hccr + HC_LENGTH(ehci_readl(&(hccr)->cr_capbase))); - ret = board_prepare_usb(USB_INIT_HOST); + ret = ehci_setup_phy(dev, &p->phy, 0); + if (ret) + return ret; + + ret = board_usb_init(0, plat->init_type); if (ret < 0) return ret; - return ehci_register(dev, hccr, hcor, &msm_ehci_ops, 0, USB_INIT_HOST); + return ehci_register(dev, hccr, hcor, &msm_ehci_ops, 0, + plat->init_type); } static int ehci_usb_remove(struct udevice *dev) @@ -122,9 +83,11 @@ static int ehci_usb_remove(struct udevice *dev) /* Stop controller. */ clrbits_le32(&ehci->usbcmd, CMD_RUN); - reset_usb_phy(p); + ret = ehci_shutdown_phy(dev, &p->phy); + if (ret) + return ret; - ret = board_prepare_usb(USB_INIT_DEVICE); /* Board specific hook */ + ret = board_usb_init(0, USB_INIT_DEVICE); /* Board specific hook */ if (ret < 0) return ret; @@ -158,6 +121,18 @@ static int ehci_usb_ofdata_to_platdata(struct udevice *dev) return 0; } +#if defined(CONFIG_CI_UDC) +/* Little quirk that MSM needs with Chipidea controller + * Must reinit phy after reset + */ +void ci_init_after_reset(struct ehci_ctrl *ctrl) +{ + struct msm_ehci_priv *p = ctrl->priv; + + generic_phy_reset(&p->phy); +} +#endif + static const struct udevice_id ehci_usb_ids[] = { { .compatible = "qcom,ehci-host", }, { } @@ -172,5 +147,6 @@ U_BOOT_DRIVER(usb_ehci) = { .remove = ehci_usb_remove, .ops = &ehci_usb_ops, .priv_auto_alloc_size = sizeof(struct msm_ehci_priv), + .platdata_auto_alloc_size = sizeof(struct usb_platdata), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index ed0b21f2a7..25c94f4a9e 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -431,6 +431,14 @@ config DISPLAY The devices provide a simple interface to start up the display, read display information and enable it. +config NXP_TDA19988 + bool "Enable NXP TDA19988 support" + depends on DISPLAY + default n + help + This enables support for the NXP TDA19988 HDMI encoder. This encoder + will convert RGB data streams into HDMI-encoded signals. + config ATMEL_HLCD bool "Enable ATMEL video support using HLCDC" depends on DM_VIDEO @@ -489,6 +497,14 @@ config VIDEO_FSL_DCU_MAX_FB_SIZE_MB source "drivers/video/rockchip/Kconfig" +config VIDEO_ARM_MALIDP + bool "Enable Arm Mali Display Processor support" + depends on DM_VIDEO && OF_CONTROL + select VEXPRESS_CLK + help + This enables support for Arm Ltd Mali Display Processors from + the DP500, DP550 and DP650 family. + config VIDEO_SANDBOX_SDL bool "Enable sandbox video console using SDL" depends on SANDBOX @@ -683,4 +699,27 @@ config VIDEO_DT_SIMPLEFB The video output is initialized by U-Boot, and kept by the kernel. +config OSD + bool "Enable OSD support" + depends on DM + default n + help + This supports drivers that provide a OSD (on-screen display), which + is a (usually text-oriented) graphics buffer to show information on + a display. + +config SANDBOX_OSD + bool "Enable sandbox OSD" + depends on OSD + help + Enable support for sandbox OSD device used for testing purposes. + +config IHS_VIDEO_OUT + bool "Enable IHS video out driver" + depends on OSD + help + Enable support for the gdsys Integrated Hardware Systems (IHS) video + out On-screen Display (OSD) used on gdsys FPGAs to control dynamic + textual overlays of the display outputs. + endmenu diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 0f41a23193..80e1e82903 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -28,12 +28,17 @@ obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o obj-$(CONFIG_CFB_CONSOLE) += cfb_console.o obj-$(CONFIG_FORMIKE) += formike.o obj-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o +obj-$(CONFIG_IHS_VIDEO_OUT) += ihs_video_out.o obj-$(CONFIG_LD9040) += ld9040.o obj-$(CONFIG_LG4573) += lg4573.o obj-$(CONFIG_LOGICORE_DP_TX) += logicore_dp_tx.o +obj-$(CONFIG_NXP_TDA19988) += tda19988.o +obj-$(CONFIG_OSD) += video_osd-uclass.o obj-$(CONFIG_PXA_LCD) += pxa_lcd.o +obj-$(CONFIG_SANDBOX_OSD) += sandbox_osd.o obj-$(CONFIG_S6E8AX0) += s6e8ax0.o obj-$(CONFIG_SCF0403_LCD) += scf0403_lcd.o +obj-$(CONFIG_VIDEO_ARM_MALIDP) += mali_dp.o obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o obj-$(CONFIG_VIDEO_BROADWELL_IGD) += broadwell_igd.o obj-$(CONFIG_VIDEO_COREBOOT) += coreboot.o diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index 40110668a6..636c3e8c18 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -1297,6 +1297,10 @@ next_run: break; } } + + if (cfb_do_flush_cache) + flush_cache(VIDEO_FB_ADRS, VIDEO_SIZE); + return 0; error: printf("Error: Too much encoded pixel data, validate your bitmap\n"); diff --git a/drivers/video/ihs_video_out.c b/drivers/video/ihs_video_out.c new file mode 100644 index 0000000000..5cdf17aec1 --- /dev/null +++ b/drivers/video/ihs_video_out.c @@ -0,0 +1,341 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2017 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + * + * based on the gdsys osd driver, which is + * + * (C) Copyright 2010 + * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.de + */ + +#include <common.h> +#include <display.h> +#include <dm.h> +#include <regmap.h> +#include <video_osd.h> +#include <asm/gpio.h> + +static const uint MAX_X_CHARS = 53; +static const uint MAX_Y_CHARS = 26; +static const uint MAX_VIDEOMEM_WIDTH = 64; +static const uint MAX_VIDEOMEM_HEIGHT = 32; +static const uint CHAR_WIDTH = 12; +static const uint CHAR_HEIGHT = 18; + +static const u16 BASE_WIDTH_MASK = 0x3f00; +static const uint BASE_WIDTH_SHIFT = 8; +static const u16 BASE_HEIGTH_MASK = 0x001f; +static const uint BASE_HEIGTH_SHIFT; + +struct ihs_video_out_regs { + /* Device version register */ + u16 versions; + /* Device feature register */ + u16 features; + /* Device control register */ + u16 control; + /* Register controlling screen size */ + u16 xy_size; + /* Register controlling screen scaling */ + u16 xy_scale; + /* Register controlling screen x position */ + u16 x_pos; + /* Register controlling screen y position */ + u16 y_pos; +}; + +#define ihs_video_out_set(map, member, val) \ + regmap_range_set(map, 1, struct ihs_video_out_regs, member, val) + +#define ihs_video_out_get(map, member, valp) \ + regmap_range_get(map, 1, struct ihs_video_out_regs, member, valp) + +enum { + CONTROL_FILTER_BLACK = (0 << 0), + CONTROL_FILTER_ORIGINAL = (1 << 0), + CONTROL_FILTER_DARKER = (2 << 0), + CONTROL_FILTER_GRAY = (3 << 0), + + CONTROL_MODE_PASSTHROUGH = (0 << 3), + CONTROL_MODE_OSD = (1 << 3), + CONTROL_MODE_AUTO = (2 << 3), + CONTROL_MODE_OFF = (3 << 3), + + CONTROL_ENABLE_OFF = (0 << 6), + CONTROL_ENABLE_ON = (1 << 6), +}; + +struct ihs_video_out_priv { + /* Register map for OSD device */ + struct regmap *map; + /* Pointer to video memory */ + u16 *vidmem; + /* Display width in text columns */ + uint base_width; + /* Display height in text rows */ + uint base_height; + /* x-resolution of the display in pixels */ + uint res_x; + /* y-resolution of the display in pixels */ + uint res_y; + /* OSD's sync mode (resolution + frequency) */ + int sync_src; + /* The display port output for this OSD */ + struct udevice *video_tx; + /* The pixel clock generator for the display */ + struct udevice *clk_gen; +}; + +static const struct udevice_id ihs_video_out_ids[] = { + { .compatible = "gdsys,ihs_video_out" }, + { } +}; + +/** + * set_control() - Set the control register to a given value + * + * The current value of sync_src is preserved by the function automatically. + * + * @dev: the OSD device whose control register to set + * @value: the 16-bit value to write to the control register + * Return: 0 + */ +static int set_control(struct udevice *dev, u16 value) +{ + struct ihs_video_out_priv *priv = dev_get_priv(dev); + + if (priv->sync_src) + value |= ((priv->sync_src & 0x7) << 8); + + ihs_video_out_set(priv->map, control, value); + + return 0; +} + +int ihs_video_out_get_info(struct udevice *dev, struct video_osd_info *info) +{ + struct ihs_video_out_priv *priv = dev_get_priv(dev); + u16 versions; + + ihs_video_out_get(priv->map, versions, &versions); + + info->width = priv->base_width; + info->height = priv->base_height; + info->major_version = versions / 100; + info->minor_version = versions % 100; + + return 0; +} + +int ihs_video_out_set_mem(struct udevice *dev, uint col, uint row, u8 *buf, + size_t buflen, uint count) +{ + struct ihs_video_out_priv *priv = dev_get_priv(dev); + int res; + uint offset; + uint k, rep; + u16 data; + + /* Repetitions (controlled via count parmeter) */ + for (rep = 0; rep < count; ++rep) { + offset = row * priv->base_width + col + rep * (buflen / 2); + + /* Write a single buffer copy */ + for (k = 0; k < buflen / 2; ++k) { + uint max_size = priv->base_width * priv->base_height; + + if (offset + k >= max_size) { + debug("%s: Write would be out of OSD bounds\n", + dev->name); + return -E2BIG; + } + + data = buf[2 * k + 1] + 256 * buf[2 * k]; + out_le16(priv->vidmem + offset + k, data); + } + } + + res = set_control(dev, CONTROL_FILTER_ORIGINAL | + CONTROL_MODE_OSD | + CONTROL_ENABLE_ON); + if (res) { + debug("%s: Could not set control register\n", dev->name); + return res; + } + + return 0; +} + +/** + * div2_u16() - Approximately divide a 16-bit number by 2 + * + * @val: The 16-bit value to divide by two + * Return: The approximate division of val by two + */ +static inline u16 div2_u16(u16 val) +{ + return (32767 * val) / 65535; +} + +int ihs_video_out_set_size(struct udevice *dev, uint col, uint row) +{ + struct ihs_video_out_priv *priv = dev_get_priv(dev); + + if (!col || col > MAX_VIDEOMEM_WIDTH || col > MAX_X_CHARS || + !row || row > MAX_VIDEOMEM_HEIGHT || row > MAX_Y_CHARS) { + debug("%s: Desired OSD size invalid\n", dev->name); + return -EINVAL; + } + + ihs_video_out_set(priv->map, xy_size, ((col - 1) << 8) | (row - 1)); + /* Center OSD on screen */ + ihs_video_out_set(priv->map, x_pos, + div2_u16(priv->res_x - CHAR_WIDTH * col)); + ihs_video_out_set(priv->map, y_pos, + div2_u16(priv->res_y - CHAR_HEIGHT * row)); + + return 0; +} + +int ihs_video_out_print(struct udevice *dev, uint col, uint row, ulong color, + char *text) +{ + int res; + u8 buffer[2 * MAX_VIDEOMEM_WIDTH]; + uint k; + uint charcount = strlen(text); + uint len = min(charcount, 2 * MAX_VIDEOMEM_WIDTH); + + for (k = 0; k < len; ++k) { + buffer[2 * k] = text[k]; + buffer[2 * k + 1] = color; + } + + res = ihs_video_out_set_mem(dev, col, row, buffer, 2 * len, 1); + if (res < 0) { + debug("%s: Could not write to video memory\n", dev->name); + return res; + } + + return 0; +} + +static const struct video_osd_ops ihs_video_out_ops = { + .get_info = ihs_video_out_get_info, + .set_mem = ihs_video_out_set_mem, + .set_size = ihs_video_out_set_size, + .print = ihs_video_out_print, +}; + +int ihs_video_out_probe(struct udevice *dev) +{ + struct ihs_video_out_priv *priv = dev_get_priv(dev); + struct ofnode_phandle_args phandle_args; + const char *mode; + u16 features; + struct display_timing timing; + int res; + + res = regmap_init_mem(dev_ofnode(dev), &priv->map); + if (!res) { + debug("%s: Could initialize regmap (err = %d)\n", dev->name, + res); + return res; + } + + /* Range with index 2 is video memory */ + priv->vidmem = regmap_get_range(priv->map, 2); + + mode = dev_read_string(dev, "mode"); + if (!mode) { + debug("%s: Could not read mode property\n", dev->name); + return -EINVAL; + } + + if (!strcmp(mode, "1024_768_60")) { + priv->sync_src = 2; + priv->res_x = 1024; + priv->res_y = 768; + timing.hactive.typ = 1024; + timing.vactive.typ = 768; + } else if (!strcmp(mode, "720_400_70")) { + priv->sync_src = 1; + priv->res_x = 720; + priv->res_y = 400; + timing.hactive.typ = 720; + timing.vactive.typ = 400; + } else { + priv->sync_src = 0; + priv->res_x = 640; + priv->res_y = 480; + timing.hactive.typ = 640; + timing.vactive.typ = 480; + } + + ihs_video_out_get(priv->map, features, &features); + + res = set_control(dev, CONTROL_FILTER_ORIGINAL | + CONTROL_MODE_OSD | + CONTROL_ENABLE_OFF); + if (res) { + debug("%s: Could not set control register (err = %d)\n", + dev->name, res); + return res; + } + + priv->base_width = ((features & BASE_WIDTH_MASK) + >> BASE_WIDTH_SHIFT) + 1; + priv->base_height = ((features & BASE_HEIGTH_MASK) + >> BASE_HEIGTH_SHIFT) + 1; + + res = dev_read_phandle_with_args(dev, "clk_gen", NULL, 0, 0, + &phandle_args); + if (res) { + debug("%s: Could not get clk_gen node (err = %d)\n", + dev->name, res); + return -EINVAL; + } + + res = uclass_get_device_by_ofnode(UCLASS_CLK, phandle_args.node, + &priv->clk_gen); + if (res) { + debug("%s: Could not get clk_gen dev (err = %d)\n", + dev->name, res); + return -EINVAL; + } + + res = dev_read_phandle_with_args(dev, "video_tx", NULL, 0, 0, + &phandle_args); + if (res) { + debug("%s: Could not get video_tx (err = %d)\n", + dev->name, res); + return -EINVAL; + } + + res = uclass_get_device_by_ofnode(UCLASS_DISPLAY, phandle_args.node, + &priv->video_tx); + if (res) { + debug("%s: Could not get video_tx dev (err = %d)\n", + dev->name, res); + return -EINVAL; + } + + res = display_enable(priv->video_tx, 8, &timing); + if (res) { + debug("%s: Could not enable the display (err = %d)\n", + dev->name, res); + return res; + } + + return 0; +} + +U_BOOT_DRIVER(ihs_video_out_drv) = { + .name = "ihs_video_out_drv", + .id = UCLASS_VIDEO_OSD, + .ops = &ihs_video_out_ops, + .of_match = ihs_video_out_ids, + .probe = ihs_video_out_probe, + .priv_auto_alloc_size = sizeof(struct ihs_video_out_priv), +}; diff --git a/drivers/video/mali_dp.c b/drivers/video/mali_dp.c new file mode 100644 index 0000000000..71151a87aa --- /dev/null +++ b/drivers/video/mali_dp.c @@ -0,0 +1,405 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016-2018 ARM Ltd. + * Author: Liviu Dudau <liviu.dudau@foss.arm.com> + * + */ +#define DEBUG +#include <common.h> +#include <video.h> +#include <dm.h> +#ifdef CONFIG_DISPLAY +#include <display.h> +#endif +#include <fdtdec.h> +#include <asm/io.h> +#include <os.h> +#include <fdt_support.h> +#include <clk.h> +#include <linux/sizes.h> + +#define MALIDP_CORE_ID 0x0018 +#define MALIDP_REG_BG_COLOR 0x0044 +#define MALIDP_LAYER_LV1 0x0100 +#define MALIDP_DC_STATUS 0xc000 +#define MALIDP_DC_CONTROL 0xc010 +#define MALIDP_DC_CFG_VALID 0xc014 + +/* offsets inside the modesetting register block */ +#define MALIDP_H_INTERVALS 0x0000 +#define MALIDP_V_INTERVALS 0x0004 +#define MALIDP_SYNC_CONTROL 0x0008 +#define MALIDP_HV_ACTIVESIZE 0x000c +#define MALIDP_OUTPUT_DEPTH 0x001c + +/* offsets inside the layer register block */ +#define MALIDP_LAYER_FORMAT 0x0000 +#define MALIDP_LAYER_CONTROL 0x0004 +#define MALIDP_LAYER_IN_SIZE 0x000c +#define MALIDP_LAYER_CMP_SIZE 0x0010 +#define MALIDP_LAYER_STRIDE 0x0018 +#define MALIDP_LAYER_PTR_LOW 0x0024 +#define MALIDP_LAYER_PTR_HIGH 0x0028 + +/* offsets inside the IRQ control blocks */ +#define MALIDP_REG_MASKIRQ 0x0008 +#define MALIDP_REG_CLEARIRQ 0x000c + +#define M1BITS 0x0001 +#define M2BITS 0x0003 +#define M4BITS 0x000f +#define M8BITS 0x00ff +#define M10BITS 0x03ff +#define M12BITS 0x0fff +#define M13BITS 0x1fff +#define M16BITS 0xffff +#define M17BITS 0x1ffff + +#define MALIDP_H_FRONTPORCH(x) (((x) & M12BITS) << 0) +#define MALIDP_H_BACKPORCH(x) (((x) & M10BITS) << 16) +#define MALIDP_V_FRONTPORCH(x) (((x) & M12BITS) << 0) +#define MALIDP_V_BACKPORCH(x) (((x) & M8BITS) << 16) +#define MALIDP_H_SYNCWIDTH(x) (((x) & M10BITS) << 0) +#define MALIDP_V_SYNCWIDTH(x) (((x) & M8BITS) << 16) +#define MALIDP_H_ACTIVE(x) (((x) & M13BITS) << 0) +#define MALIDP_V_ACTIVE(x) (((x) & M13BITS) << 16) + +#define MALIDP_CMP_V_SIZE(x) (((x) & M13BITS) << 16) +#define MALIDP_CMP_H_SIZE(x) (((x) & M13BITS) << 0) + +#define MALIDP_IN_V_SIZE(x) (((x) & M13BITS) << 16) +#define MALIDP_IN_H_SIZE(x) (((x) & M13BITS) << 0) + +#define MALIDP_DC_CM_CONTROL(x) ((x) & M1BITS) << 16, 1 << 16 +#define MALIDP_DC_STATUS_GET_CM(reg) (((reg) >> 16) & M1BITS) + +#define MALIDP_FORMAT_ARGB8888 0x08 +#define MALIDP_DEFAULT_BG_R 0x0 +#define MALIDP_DEFAULT_BG_G 0x0 +#define MALIDP_DEFAULT_BG_B 0x0 + +#define MALIDP_PRODUCT_ID(core_id) ((u32)(core_id) >> 16) + +#define MALIDP500 0x500 + +DECLARE_GLOBAL_DATA_PTR; + +struct malidp_priv { + phys_addr_t base_addr; + phys_addr_t dc_status_addr; + phys_addr_t dc_control_addr; + phys_addr_t cval_addr; + struct udevice *display; /* display device attached */ + struct clk aclk; + struct clk pxlclk; + u16 modeset_regs_offset; + u8 config_bit_shift; + u8 clear_irq; /* offset for IRQ clear register */ +}; + +static const struct video_ops malidp_ops = { +}; + +static int malidp_get_hwid(phys_addr_t base_addr) +{ + int hwid; + + /* + * reading from the old CORE_ID offset will always + * return 0x5000000 on DP500 + */ + hwid = readl(base_addr + MALIDP_CORE_ID); + if (MALIDP_PRODUCT_ID(hwid) == MALIDP500) + return hwid; + /* otherwise try the other gen CORE_ID offset */ + hwid = readl(base_addr + MALIDP_DC_STATUS + MALIDP_CORE_ID); + + return hwid; +} + +/* + * wait for config mode bit setup to be acted upon by the hardware + */ +static int malidp_wait_configdone(struct malidp_priv *malidp) +{ + u32 status, tries = 300; + + while (tries--) { + status = readl(malidp->dc_status_addr); + if ((status >> malidp->config_bit_shift) & 1) + break; + udelay(500); + } + + if (!tries) + return -ETIMEDOUT; + + return 0; +} + +/* + * signal the hardware to enter configuration mode + */ +static int malidp_enter_config(struct malidp_priv *malidp) +{ + setbits_le32(malidp->dc_control_addr, 1 << malidp->config_bit_shift); + return malidp_wait_configdone(malidp); +} + +/* + * signal the hardware to exit configuration mode + */ +static int malidp_leave_config(struct malidp_priv *malidp) +{ + clrbits_le32(malidp->dc_control_addr, 1 << malidp->config_bit_shift); + return malidp_wait_configdone(malidp); +} + +static void malidp_setup_timings(struct malidp_priv *malidp, + struct display_timing *timings) +{ + u32 val = MALIDP_H_SYNCWIDTH(timings->hsync_len.typ) | + MALIDP_V_SYNCWIDTH(timings->vsync_len.typ); + writel(val, malidp->base_addr + malidp->modeset_regs_offset + + MALIDP_SYNC_CONTROL); + val = MALIDP_H_BACKPORCH(timings->hback_porch.typ) | + MALIDP_H_FRONTPORCH(timings->hfront_porch.typ); + writel(val, malidp->base_addr + malidp->modeset_regs_offset + + MALIDP_H_INTERVALS); + val = MALIDP_V_BACKPORCH(timings->vback_porch.typ) | + MALIDP_V_FRONTPORCH(timings->vfront_porch.typ); + writel(val, malidp->base_addr + malidp->modeset_regs_offset + + MALIDP_V_INTERVALS); + val = MALIDP_H_ACTIVE(timings->hactive.typ) | + MALIDP_V_ACTIVE(timings->vactive.typ); + writel(val, malidp->base_addr + malidp->modeset_regs_offset + + MALIDP_HV_ACTIVESIZE); + /* default output bit-depth per colour is 8 bits */ + writel(0x080808, malidp->base_addr + malidp->modeset_regs_offset + + MALIDP_OUTPUT_DEPTH); +} + +static int malidp_setup_mode(struct malidp_priv *malidp, + struct display_timing *timings) +{ + int err; + + if (clk_set_rate(&malidp->pxlclk, timings->pixelclock.typ) == 0) + return -EIO; + + malidp_setup_timings(malidp, timings); + + err = display_enable(malidp->display, 8, timings); + if (err) + printf("display_enable failed with %d\n", err); + + return err; +} + +static void malidp_setup_layer(struct malidp_priv *malidp, + struct display_timing *timings, + u32 layer_offset, phys_addr_t fb_addr) +{ + u32 val; + + /* setup the base layer's pixel format to A8R8G8B8 */ + writel(MALIDP_FORMAT_ARGB8888, malidp->base_addr + layer_offset + + MALIDP_LAYER_FORMAT); + /* setup layer composition size */ + val = MALIDP_CMP_V_SIZE(timings->vactive.typ) | + MALIDP_CMP_H_SIZE(timings->hactive.typ); + writel(val, malidp->base_addr + layer_offset + + MALIDP_LAYER_CMP_SIZE); + /* setup layer input size */ + val = MALIDP_IN_V_SIZE(timings->vactive.typ) | + MALIDP_IN_H_SIZE(timings->hactive.typ); + writel(val, malidp->base_addr + layer_offset + MALIDP_LAYER_IN_SIZE); + /* setup layer stride in bytes */ + writel(timings->hactive.typ << 2, malidp->base_addr + layer_offset + + MALIDP_LAYER_STRIDE); + /* set framebuffer address */ + writel(lower_32_bits(fb_addr), malidp->base_addr + layer_offset + + MALIDP_LAYER_PTR_LOW); + writel(upper_32_bits(fb_addr), malidp->base_addr + layer_offset + + MALIDP_LAYER_PTR_HIGH); + /* enable layer */ + setbits_le32(malidp->base_addr + layer_offset + + MALIDP_LAYER_CONTROL, 1); +} + +static void malidp_set_configvalid(struct malidp_priv *malidp) +{ + setbits_le32(malidp->cval_addr, 1); +} + +static int malidp_update_timings_from_edid(struct udevice *dev, + struct display_timing *timings) +{ +#ifdef CONFIG_DISPLAY + struct malidp_priv *priv = dev_get_priv(dev); + struct udevice *disp_dev; + int err; + + err = uclass_first_device(UCLASS_DISPLAY, &disp_dev); + if (err) + return err; + + priv->display = disp_dev; + + err = display_read_timing(disp_dev, timings); + if (err) + return err; + +#endif + return 0; +} + +static int malidp_probe(struct udevice *dev) +{ + struct video_priv *uc_priv = dev_get_uclass_priv(dev); + struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev); + ofnode framebuffer = ofnode_find_subnode(dev_ofnode(dev), "framebuffer"); + struct malidp_priv *priv = dev_get_priv(dev); + struct display_timing timings; + phys_addr_t fb_base, fb_size; + const char *format; + u32 value; + int err; + + if (!ofnode_valid(framebuffer)) + return -EINVAL; + + err = clk_get_by_name(dev, "pxlclk", &priv->pxlclk); + if (err) { + dev_err(dev, "failed to get pixel clock\n"); + return err; + } + err = clk_get_by_name(dev, "aclk", &priv->aclk); + if (err) { + dev_err(dev, "failed to get AXI clock\n"); + goto fail_aclk; + } + + err = ofnode_decode_display_timing(dev_ofnode(dev), 1, &timings); + if (err) { + dev_err(dev, "failed to get any display timings\n"); + goto fail_timings; + } + + err = malidp_update_timings_from_edid(dev, &timings); + if (err) { + printf("malidp_update_timings_from_edid failed: %d\n", err); + goto fail_timings; + } + + fb_base = ofnode_get_addr_size(framebuffer, "reg", &fb_size); + if (fb_base != FDT_ADDR_T_NONE) { + uc_plat->base = fb_base; + uc_plat->size = fb_size; + } else { + printf("cannot get address size for framebuffer\n"); + } + + err = ofnode_read_u32(framebuffer, "width", &value); + if (err) + goto fail_timings; + uc_priv->xsize = (ushort)value; + + err = ofnode_read_u32(framebuffer, "height", &value); + if (err) + goto fail_timings; + uc_priv->ysize = (ushort)value; + + format = ofnode_read_string(framebuffer, "format"); + if (!format) { + err = -EINVAL; + goto fail_timings; + } else if (!strncmp(format, "a8r8g8b8", 8)) { + uc_priv->bpix = VIDEO_BPP32; + } + + uc_priv->rot = 0; + priv->base_addr = (phys_addr_t)dev_read_addr(dev); + + clk_enable(&priv->pxlclk); + clk_enable(&priv->aclk); + + value = malidp_get_hwid(priv->base_addr); + printf("Display: Arm Mali DP%3x r%dp%d\n", MALIDP_PRODUCT_ID(value), + (value >> 12) & 0xf, (value >> 8) & 0xf); + + if (MALIDP_PRODUCT_ID(value) == MALIDP500) { + /* DP500 is special */ + priv->modeset_regs_offset = 0x28; + priv->dc_status_addr = priv->base_addr; + priv->dc_control_addr = priv->base_addr + 0xc; + priv->cval_addr = priv->base_addr + 0xf00; + priv->config_bit_shift = 17; + priv->clear_irq = 0; + } else { + priv->modeset_regs_offset = 0x30; + priv->dc_status_addr = priv->base_addr + MALIDP_DC_STATUS; + priv->dc_control_addr = priv->base_addr + MALIDP_DC_CONTROL; + priv->cval_addr = priv->base_addr + MALIDP_DC_CFG_VALID; + priv->config_bit_shift = 16; + priv->clear_irq = MALIDP_REG_CLEARIRQ; + } + + /* enter config mode */ + err = malidp_enter_config(priv); + if (err) + return err; + + /* disable interrupts */ + writel(0, priv->dc_status_addr + MALIDP_REG_MASKIRQ); + writel(0xffffffff, priv->dc_status_addr + priv->clear_irq); + + err = malidp_setup_mode(priv, &timings); + if (err) + goto fail_timings; + + malidp_setup_layer(priv, &timings, MALIDP_LAYER_LV1, + (phys_addr_t)uc_plat->base); + + err = malidp_leave_config(priv); + if (err) + goto fail_timings; + + malidp_set_configvalid(priv); + + return 0; + +fail_timings: + clk_free(&priv->aclk); +fail_aclk: + clk_free(&priv->pxlclk); + + return err; +} + +static int malidp_bind(struct udevice *dev) +{ + struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev); + + /* choose max possible size: 2K x 2K, XRGB888 framebuffer */ + uc_plat->size = 4 * 2048 * 2048; + + return 0; +} + +static const struct udevice_id malidp_ids[] = { + { .compatible = "arm,mali-dp500" }, + { .compatible = "arm,mali-dp550" }, + { .compatible = "arm,mali-dp650" }, + { } +}; + +U_BOOT_DRIVER(mali_dp) = { + .name = "mali_dp", + .id = UCLASS_VIDEO, + .of_match = malidp_ids, + .bind = malidp_bind, + .probe = malidp_probe, + .priv_auto_alloc_size = sizeof(struct malidp_priv), + .ops = &malidp_ops, +}; diff --git a/drivers/video/sandbox_osd.c b/drivers/video/sandbox_osd.c new file mode 100644 index 0000000000..dd84489add --- /dev/null +++ b/drivers/video/sandbox_osd.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2018 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + */ +#include <common.h> +#include <display.h> +#include <dm.h> +#include <video_osd.h> + +#include "sandbox_osd.h" + +struct sandbox_osd_priv { + uint width; + uint height; + u16 *buf; +}; + +static const struct udevice_id sandbox_osd_ids[] = { + { .compatible = "sandbox,sandbox_osd" }, + { } +}; + +inline u16 make_memval(u8 chr, u8 color) +{ + return chr * 0x100 + color; +} + +int sandbox_osd_get_info(struct udevice *dev, struct video_osd_info *info) +{ + struct sandbox_osd_priv *priv = dev_get_priv(dev); + + info->width = priv->width; + info->height = priv->height; + info->major_version = 1; + info->minor_version = 0; + + return 0; +} + +int sandbox_osd_set_mem(struct udevice *dev, uint col, uint row, u8 *buf, + size_t buflen, uint count) +{ + struct sandbox_osd_priv *priv = dev_get_priv(dev); + int pos; + u8 *mem = (u8 *)priv->buf; + int i; + + pos = 2 * (row * priv->width + col); + + if (pos >= 2 * (priv->width * priv->height)) + return -EINVAL; + + for (i = 0; i < count; i++) + memcpy(mem + pos + (i * buflen), buf, buflen); + + return 0; +} + +int _sandbox_osd_set_size(struct udevice *dev, uint col, uint row) +{ + struct sandbox_osd_priv *priv = dev_get_priv(dev); + int i; + uint size; + + priv->width = col; + priv->height = row; + size = priv->width * priv->height; + if (!priv->buf) + priv->buf = calloc(size, sizeof(u16)); + else + priv->buf = realloc(priv->buf, size * sizeof(u16)); + + if (!priv->buf) + return -ENOMEM; + + /* Fill OSD with black spaces */ + for (i = 0; i < size; i++) + priv->buf[i] = make_memval(' ', 'k'); + + return 0; +} + +int sandbox_osd_set_size(struct udevice *dev, uint col, uint row) +{ + return _sandbox_osd_set_size(dev, col, row); +} + +int sandbox_osd_print(struct udevice *dev, uint col, uint row, ulong color, + char *text) +{ + struct sandbox_osd_priv *priv = dev_get_priv(dev); + char cval; + char *p; + int pos; + + if (col >= priv->width || row >= priv->height) + return -EINVAL; + + switch (color) { + case COLOR_BLACK: + cval = 'k'; + break; + case COLOR_WHITE: + cval = 'w'; + break; + case COLOR_RED: + cval = 'r'; + break; + case COLOR_GREEN: + cval = 'g'; + break; + case COLOR_BLUE: + cval = 'b'; + break; + default: + return -EINVAL; + } + + p = text; + pos = row * priv->width + col; + + while (*p) + priv->buf[pos++] = make_memval(*(p++), cval); + + return 0; +} + +int sandbox_osd_get_mem(struct udevice *dev, u8 *buf, size_t buflen) +{ + struct sandbox_osd_priv *priv = dev_get_priv(dev); + uint memsize = 2 * (priv->width * priv->height); + + if (buflen < memsize) + return -EINVAL; + + memcpy(buf, priv->buf, memsize); + + return 0; +} + +static const struct video_osd_ops sandbox_osd_ops = { + .get_info = sandbox_osd_get_info, + .set_mem = sandbox_osd_set_mem, + .set_size = sandbox_osd_set_size, + .print = sandbox_osd_print, +}; + +int sandbox_osd_probe(struct udevice *dev) +{ + return _sandbox_osd_set_size(dev, 10, 10); +} + +U_BOOT_DRIVER(sandbox_osd_drv) = { + .name = "sandbox_osd_drv", + .id = UCLASS_VIDEO_OSD, + .ops = &sandbox_osd_ops, + .of_match = sandbox_osd_ids, + .probe = sandbox_osd_probe, + .priv_auto_alloc_size = sizeof(struct sandbox_osd_priv), +}; diff --git a/drivers/video/sandbox_osd.h b/drivers/video/sandbox_osd.h new file mode 100644 index 0000000000..15a2c91c52 --- /dev/null +++ b/drivers/video/sandbox_osd.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2018 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + */ + +enum { + COLOR_BLACK, + COLOR_WHITE, + COLOR_RED, + COLOR_GREEN, + COLOR_BLUE, +}; diff --git a/drivers/video/tda19988.c b/drivers/video/tda19988.c new file mode 100644 index 0000000000..01ed6193ea --- /dev/null +++ b/drivers/video/tda19988.c @@ -0,0 +1,653 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2018 Liviu Dudau <liviu@dudau.co.uk> + * + * Based on the Linux driver, (C) 2012 Texas Instruments + */ + +#include <common.h> +#include <dm.h> +#include <display.h> +#include <i2c.h> + +/* + * TDA19988 uses paged registers. We encode the page# in the upper + * bits of the register#. It also means that reads/writes to a register + * have to ensure that the register's page is selected as the current + * page. + */ +#define REG(page, addr) (((page) << 8) | (addr)) +#define REG2ADDR(reg) ((reg) & 0xff) +#define REG2PAGE(reg) (((reg) >> 8) & 0xff) + +/* register for setting current page */ +#define REG_CURRENT_PAGE 0xff + +/* Page 00h: General Control */ +#define REG_VERSION_LSB REG(0x00, 0x00) /* read */ +#define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */ +#define MAIN_CNTRL0_SR BIT(0) +#define MAIN_CNTRL0_DECS BIT(1) +#define MAIN_CNTRL0_DEHS BIT(2) +#define MAIN_CNTRL0_CECS BIT(3) +#define MAIN_CNTRL0_CEHS BIT(4) +#define MAIN_CNTRL0_SCALER BIT(7) +#define REG_VERSION_MSB REG(0x00, 0x02) /* read */ +#define REG_SOFTRESET REG(0x00, 0x0a) /* write */ +#define SOFTRESET_AUDIO BIT(0) +#define SOFTRESET_I2C_MASTER BIT(1) +#define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */ +#define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */ +#define I2C_MASTER_DIS_MM BIT(0) +#define I2C_MASTER_DIS_FILT BIT(1) +#define I2C_MASTER_APP_STRT_LAT BIT(2) +#define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */ +#define FEAT_POWERDOWN_PREFILT BIT(0) +#define FEAT_POWERDOWN_CSC BIT(1) +#define FEAT_POWERDOWN_SPDIF BIT(3) +#define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */ +#define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */ +#define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */ +#define INT_FLAGS_2_EDID_BLK_RD BIT(1) +#define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */ +#define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */ +#define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */ +#define REG_ENA_AP REG(0x00, 0x1e) /* read/write */ +#define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */ +#define VIP_CNTRL_0_MIRR_A BIT(7) +#define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4) +#define VIP_CNTRL_0_MIRR_B BIT(3) +#define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0) +#define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */ +#define VIP_CNTRL_1_MIRR_C BIT(7) +#define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4) +#define VIP_CNTRL_1_MIRR_D BIT(3) +#define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0) +#define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */ +#define VIP_CNTRL_2_MIRR_E BIT(7) +#define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4) +#define VIP_CNTRL_2_MIRR_F BIT(3) +#define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0) +#define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */ +#define VIP_CNTRL_3_X_TGL BIT(0) +#define VIP_CNTRL_3_H_TGL BIT(1) +#define VIP_CNTRL_3_V_TGL BIT(2) +#define VIP_CNTRL_3_EMB BIT(3) +#define VIP_CNTRL_3_SYNC_DE BIT(4) +#define VIP_CNTRL_3_SYNC_HS BIT(5) +#define VIP_CNTRL_3_DE_INT BIT(6) +#define VIP_CNTRL_3_EDGE BIT(7) +#define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */ +#define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0) +#define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2) +#define VIP_CNTRL_4_CCIR656 BIT(4) +#define VIP_CNTRL_4_656_ALT BIT(5) +#define VIP_CNTRL_4_TST_656 BIT(6) +#define VIP_CNTRL_4_TST_PAT BIT(7) +#define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */ +#define VIP_CNTRL_5_CKCASE BIT(0) +#define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1) +#define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */ +#define REG_MAT_CONTRL REG(0x00, 0x80) /* write */ +#define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0) +#define MAT_CONTRL_MAT_BP BIT(2) +#define REG_VIDFORMAT REG(0x00, 0xa0) /* write */ +#define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */ +#define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */ +#define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */ +#define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */ +#define REG_NPIX_MSB REG(0x00, 0xa5) /* write */ +#define REG_NPIX_LSB REG(0x00, 0xa6) /* write */ +#define REG_NLINE_MSB REG(0x00, 0xa7) /* write */ +#define REG_NLINE_LSB REG(0x00, 0xa8) /* write */ +#define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */ +#define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */ +#define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */ +#define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */ +#define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */ +#define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */ +#define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */ +#define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */ +#define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */ +#define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */ +#define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */ +#define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */ +#define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */ +#define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */ +#define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */ +#define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */ +#define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */ +#define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */ +#define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */ +#define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */ +#define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */ +#define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */ +#define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */ +#define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */ +#define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */ +#define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */ +#define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */ +#define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */ +#define REG_DE_START_MSB REG(0x00, 0xc5) /* write */ +#define REG_DE_START_LSB REG(0x00, 0xc6) /* write */ +#define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */ +#define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */ +#define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */ +#define TBG_CNTRL_0_TOP_TGL BIT(0) +#define TBG_CNTRL_0_TOP_SEL BIT(1) +#define TBG_CNTRL_0_DE_EXT BIT(2) +#define TBG_CNTRL_0_TOP_EXT BIT(3) +#define TBG_CNTRL_0_FRAME_DIS BIT(5) +#define TBG_CNTRL_0_SYNC_MTHD BIT(6) +#define TBG_CNTRL_0_SYNC_ONCE BIT(7) +#define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */ +#define TBG_CNTRL_1_H_TGL BIT(0) +#define TBG_CNTRL_1_V_TGL BIT(1) +#define TBG_CNTRL_1_TGL_EN BIT(2) +#define TBG_CNTRL_1_X_EXT BIT(3) +#define TBG_CNTRL_1_H_EXT BIT(4) +#define TBG_CNTRL_1_V_EXT BIT(5) +#define TBG_CNTRL_1_DWIN_DIS BIT(6) +#define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */ +#define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */ +#define HVF_CNTRL_0_SM BIT(7) +#define HVF_CNTRL_0_RWB BIT(6) +#define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2) +#define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0) +#define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */ +#define HVF_CNTRL_1_FOR BIT(0) +#define HVF_CNTRL_1_YUVBLK BIT(1) +#define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2) +#define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4) +#define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */ +#define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */ +#define AIP_CLKSEL_AIP_SPDIF (0 << 3) +#define AIP_CLKSEL_AIP_I2S BIT(3) +#define AIP_CLKSEL_FS_ACLK (0 << 0) +#define AIP_CLKSEL_FS_MCLK BIT(0) + +/* Page 02h: PLL settings */ +#define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */ +#define PLL_SERIAL_1_SRL_FDN BIT(0) +#define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1) +#define PLL_SERIAL_1_SRL_MAN_IZ BIT(6) +#define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */ +#define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0) +#define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4) +#define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */ +#define PLL_SERIAL_3_SRL_CCIR BIT(0) +#define PLL_SERIAL_3_SRL_DE BIT(2) +#define PLL_SERIAL_3_SRL_PXIN_SEL BIT(4) +#define REG_SERIALIZER REG(0x02, 0x03) /* read/write */ +#define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */ +#define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */ +#define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */ +#define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */ +#define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */ +#define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */ +#define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */ +#define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */ +#define AUDIO_DIV_SERCLK_1 0 +#define AUDIO_DIV_SERCLK_2 1 +#define AUDIO_DIV_SERCLK_4 2 +#define AUDIO_DIV_SERCLK_8 3 +#define AUDIO_DIV_SERCLK_16 4 +#define AUDIO_DIV_SERCLK_32 5 +#define REG_SEL_CLK REG(0x02, 0x11) /* read/write */ +#define SEL_CLK_SEL_CLK1 BIT(0) +#define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1) +#define SEL_CLK_ENA_SC_CLK BIT(3) +#define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */ + +/* Page 09h: EDID Control */ +#define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */ +/* next 127 successive registers are the EDID block */ +#define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */ +#define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */ +#define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */ +#define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */ +#define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */ + +/* Page 11h: audio settings and content info packets */ +#define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */ +#define AIP_CNTRL_0_RST_FIFO BIT(0) +#define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */ +#define ENC_CNTRL_RST_ENC BIT(0) +#define ENC_CNTRL_RST_SEL BIT(1) +#define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2) + +/* Page 12h: HDCP and OTP */ +#define REG_TX3 REG(0x12, 0x9a) /* read/write */ +#define REG_TX4 REG(0x12, 0x9b) /* read/write */ +#define TX4_PD_RAM BIT(1) +#define REG_TX33 REG(0x12, 0xb8) /* read/write */ +#define TX33_HDMI BIT(1) + +/* CEC registers, not paged */ +#define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */ +#define CEC_FRO_IM_CLK_CTRL_GHOST_DIS BIT(7) +#define CEC_FRO_IM_CLK_CTRL_ENA_OTP BIT(6) +#define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL BIT(1) +#define CEC_FRO_IM_CLK_CTRL_FRO_DIV BIT(0) +#define REG_CEC_RXSHPDINTENA 0xfc /* read/write */ +#define REG_CEC_RXSHPDINT 0xfd /* read */ +#define CEC_RXSHPDINT_RXSENS BIT(0) +#define CEC_RXSHPDINT_HPD BIT(1) +#define TDA19988_CEC_ENAMODS 0xff /* read/write */ +#define CEC_ENAMODS_EN_RXSENS BIT(2) +#define CEC_ENAMODS_EN_HDMI BIT(1) +#define CEC_ENAMODS_EN_CEC BIT(0) + +/* Device versions */ +#define TDA9989N2 0x0101 +#define TDA19989 0x0201 +#define TDA19989N2 0x0202 +#define TDA19988 0x0301 + +struct tda19988_priv { + struct udevice *chip; + struct udevice *cec_chip; + u16 revision; + u8 current_page; +}; + +static void tda19988_register_set(struct tda19988_priv *priv, u16 reg, u8 val) +{ + u8 old_val, page = REG2PAGE(reg); + + if (priv->current_page != page) { + dm_i2c_reg_write(priv->chip, REG_CURRENT_PAGE, page); + priv->current_page = page; + } + old_val = dm_i2c_reg_read(priv->chip, REG2ADDR(reg)); + old_val |= val; + dm_i2c_reg_write(priv->chip, REG2ADDR(reg), old_val); +} + +static void tda19988_register_clear(struct tda19988_priv *priv, u16 reg, u8 val) +{ + u8 old_val, page = REG2PAGE(reg); + + if (priv->current_page != page) { + dm_i2c_reg_write(priv->chip, REG_CURRENT_PAGE, page); + priv->current_page = page; + } + old_val = dm_i2c_reg_read(priv->chip, REG2ADDR(reg)); + old_val &= ~val; + dm_i2c_reg_write(priv->chip, REG2ADDR(reg), old_val); +} + +static void tda19988_register_write(struct tda19988_priv *priv, u16 reg, u8 val) +{ + u8 page = REG2PAGE(reg); + + if (priv->current_page != page) { + dm_i2c_reg_write(priv->chip, REG_CURRENT_PAGE, page); + priv->current_page = page; + } + dm_i2c_reg_write(priv->chip, REG2ADDR(reg), val); +} + +static int tda19988_register_read(struct tda19988_priv *priv, u16 reg) +{ + u8 page = REG2PAGE(reg); + + if (priv->current_page != page) { + dm_i2c_reg_write(priv->chip, REG_CURRENT_PAGE, page); + priv->current_page = page; + } + return dm_i2c_reg_read(priv->chip, REG2ADDR(reg)); +} + +static void tda19988_register_write16(struct tda19988_priv *priv, + u16 reg, u16 val) +{ + u8 buf[] = { val >> 8, val }, page = REG2PAGE(reg); + + if (priv->current_page != page) { + dm_i2c_reg_write(priv->chip, REG_CURRENT_PAGE, page); + priv->current_page = page; + } + dm_i2c_write(priv->chip, REG2ADDR(reg), buf, 2); +} + +static int tda19988_read_edid(struct udevice *dev, u8 *buf, int buf_size) +{ + struct tda19988_priv *priv = dev_get_priv(dev); + int i, val = 0, offset = 0; + + /* + * The TDA998x has a problem when trying to read the EDID close to a + * HPD assertion: it needs a delay of 100ms to avoid timing out while + * trying to read EDID data. + */ + mdelay(120); + + if (priv->revision == TDA19988) + tda19988_register_clear(priv, REG_TX4, TX4_PD_RAM); + + while (offset < buf_size) { + tda19988_register_write(priv, REG_DDC_ADDR, 0xa0); + tda19988_register_write(priv, REG_DDC_OFFS, offset); + tda19988_register_write(priv, REG_DDC_SEGM_ADDR, 0x60); + tda19988_register_write(priv, REG_DDC_SEGM, 0); + + /* enable reading EDID */ + tda19988_register_write(priv, REG_EDID_CTRL, 1); + + /* flags must be cleared by software */ + tda19988_register_write(priv, REG_EDID_CTRL, 0); + + /* wait for block read to complete */ + for (i = 300; i > 0; i--) { + mdelay(1); + val = tda19988_register_read(priv, REG_INT_FLAGS_2); + if (val < 0) + return val; + if (val & INT_FLAGS_2_EDID_BLK_RD) + break; + } + + if (i == 0) + return -ETIMEDOUT; + + priv->current_page = REG2PAGE(REG_EDID_DATA_0); + dm_i2c_reg_write(priv->chip, + REG_CURRENT_PAGE, REG2PAGE(REG_EDID_DATA_0)); + val = dm_i2c_read(priv->chip, + REG2ADDR(REG_EDID_DATA_0), buf + offset, 128); + offset += 128; + } + + if (priv->revision == TDA19988) + tda19988_register_set(priv, REG_TX4, TX4_PD_RAM); + + return offset; +} + +static int tda19988_enable(struct udevice *dev, int panel_bpp, + const struct display_timing *timing) +{ + struct tda19988_priv *priv = dev_get_priv(dev); + u8 div = 148500000 / timing->pixelclock.typ, reg; + u16 line_clocks, lines; + + if (dev != 0) { + div--; + if (div > 3) + div = 3; + } + /* first disable the video ports */ + tda19988_register_write(priv, REG_ENA_VP_0, 0); + tda19988_register_write(priv, REG_ENA_VP_1, 0); + tda19988_register_write(priv, REG_ENA_VP_2, 0); + + /* shutdown audio */ + tda19988_register_write(priv, REG_ENA_AP, 0); + + line_clocks = timing->hsync_len.typ + timing->hback_porch.typ + + timing->hactive.typ + timing->hfront_porch.typ; + lines = timing->vsync_len.typ + timing->vback_porch.typ + + timing->vactive.typ + timing->vfront_porch.typ; + + /* mute the audio FIFO */ + tda19988_register_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); + /* HDMI HDCP: off */ + tda19988_register_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); + tda19988_register_clear(priv, REG_TX33, TX33_HDMI); + tda19988_register_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0)); + + /* no pre-filter or interpolator */ + tda19988_register_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) | + HVF_CNTRL_0_INTPOL(0)); + tda19988_register_set(priv, REG_FEAT_POWERDOWN, + FEAT_POWERDOWN_PREFILT); + tda19988_register_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0)); + tda19988_register_write(priv, REG_VIP_CNTRL_4, + VIP_CNTRL_4_BLANKIT(0) | VIP_CNTRL_4_BLC(0) | + VIP_CNTRL_4_TST_PAT); + + tda19988_register_clear(priv, REG_PLL_SERIAL_1, + PLL_SERIAL_1_SRL_MAN_IZ); + tda19988_register_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR | + PLL_SERIAL_3_SRL_DE); + + tda19988_register_write(priv, REG_SERIALIZER, 0); + tda19988_register_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0)); + + tda19988_register_write(priv, REG_RPT_CNTRL, 0); + tda19988_register_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) | + SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); + tda19988_register_write(priv, REG_PLL_SERIAL_2, + PLL_SERIAL_2_SRL_NOSC(div) | + PLL_SERIAL_2_SRL_PR(0)); + + /* set color matrix bypass flag: */ + tda19988_register_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP | + MAT_CONTRL_MAT_SC(1)); + tda19988_register_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC); + + /* set BIAS tmds value: */ + tda19988_register_write(priv, REG_ANA_GENERAL, 0x09); + + /* + * Sync on rising HSYNC/VSYNC + */ + reg = VIP_CNTRL_3_SYNC_HS; + + /* + * TDA19988 requires high-active sync at input stage, + * so invert low-active sync provided by master encoder here + */ + if (timing->flags & DISPLAY_FLAGS_HSYNC_LOW) + reg |= VIP_CNTRL_3_H_TGL; + if (timing->flags & DISPLAY_FLAGS_VSYNC_LOW) + reg |= VIP_CNTRL_3_V_TGL; + tda19988_register_write(priv, REG_VIP_CNTRL_3, reg); + + tda19988_register_write(priv, REG_VIDFORMAT, 0x00); + tda19988_register_write16(priv, REG_REFPIX_MSB, + timing->hfront_porch.typ + 3); + tda19988_register_write16(priv, REG_REFLINE_MSB, + timing->vfront_porch.typ + 1); + tda19988_register_write16(priv, REG_NPIX_MSB, line_clocks); + tda19988_register_write16(priv, REG_NLINE_MSB, lines); + tda19988_register_write16(priv, REG_VS_LINE_STRT_1_MSB, + timing->vfront_porch.typ); + tda19988_register_write16(priv, REG_VS_PIX_STRT_1_MSB, + timing->hfront_porch.typ); + tda19988_register_write16(priv, REG_VS_LINE_END_1_MSB, + timing->vfront_porch.typ + + timing->vsync_len.typ); + tda19988_register_write16(priv, REG_VS_PIX_END_1_MSB, + timing->hfront_porch.typ); + tda19988_register_write16(priv, REG_VS_LINE_STRT_2_MSB, 0); + tda19988_register_write16(priv, REG_VS_PIX_STRT_2_MSB, 0); + tda19988_register_write16(priv, REG_VS_LINE_END_2_MSB, 0); + tda19988_register_write16(priv, REG_VS_PIX_END_2_MSB, 0); + tda19988_register_write16(priv, REG_HS_PIX_START_MSB, + timing->hfront_porch.typ); + tda19988_register_write16(priv, REG_HS_PIX_STOP_MSB, + timing->hfront_porch.typ + + timing->hsync_len.typ); + tda19988_register_write16(priv, REG_VWIN_START_1_MSB, + lines - timing->vactive.typ - 1); + tda19988_register_write16(priv, REG_VWIN_END_1_MSB, lines - 1); + tda19988_register_write16(priv, REG_VWIN_START_2_MSB, 0); + tda19988_register_write16(priv, REG_VWIN_END_2_MSB, 0); + tda19988_register_write16(priv, REG_DE_START_MSB, + line_clocks - timing->hactive.typ); + tda19988_register_write16(priv, REG_DE_STOP_MSB, line_clocks); + + if (priv->revision == TDA19988) { + /* let incoming pixels fill the active space (if any) */ + tda19988_register_write(priv, REG_ENABLE_SPACE, 0x00); + } + + /* + * Always generate sync polarity relative to input sync and + * revert input stage toggled sync at output stage + */ + reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN; + if (timing->flags & DISPLAY_FLAGS_HSYNC_LOW) + reg |= TBG_CNTRL_1_H_TGL; + if (timing->flags & DISPLAY_FLAGS_VSYNC_LOW) + reg |= TBG_CNTRL_1_V_TGL; + tda19988_register_write(priv, REG_TBG_CNTRL_1, reg); + + /* must be last register set: */ + tda19988_register_write(priv, REG_TBG_CNTRL_0, 0); + + /* turn on HDMI HDCP */ + reg &= ~TBG_CNTRL_1_DWIN_DIS; + tda19988_register_write(priv, REG_TBG_CNTRL_1, reg); + tda19988_register_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1)); + tda19988_register_set(priv, REG_TX33, TX33_HDMI); + + mdelay(400); + + /* enable video ports */ + tda19988_register_write(priv, REG_ENA_VP_0, 0xff); + tda19988_register_write(priv, REG_ENA_VP_1, 0xff); + tda19988_register_write(priv, REG_ENA_VP_2, 0xff); + /* set muxing after enabling ports: */ + tda19988_register_write(priv, REG_VIP_CNTRL_0, + VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3)); + tda19988_register_write(priv, REG_VIP_CNTRL_1, + VIP_CNTRL_1_SWAP_C(4) | VIP_CNTRL_1_SWAP_D(5)); + tda19988_register_write(priv, REG_VIP_CNTRL_2, + VIP_CNTRL_2_SWAP_E(0) | VIP_CNTRL_2_SWAP_F(1)); + + return 0; +} + +struct dm_display_ops tda19988_ops = { + .read_edid = tda19988_read_edid, + .enable = tda19988_enable, +}; + +static const struct udevice_id tda19988_ids[] = { + { .compatible = "nxp,tda998x" }, + { } +}; + +static int tda19988_probe(struct udevice *dev) +{ + u8 cec_addr, chip_addr, rev_lo, rev_hi; + int err; + struct tda19988_priv *priv = dev_get_priv(dev); + + chip_addr = dev_read_addr(dev); + /* CEC I2C address is using TDA19988 I2C address configuration pins */ + cec_addr = 0x34 + (chip_addr & 0x03); + + err = i2c_get_chip_for_busnum(0, cec_addr, 1, &priv->cec_chip); + if (err) { + printf("cec i2c_get_chip_for_busnum returned %d\n", err); + return err; + } + + err = i2c_get_chip_for_busnum(0, chip_addr, 1, &priv->chip); + if (err) { + printf("i2c_get_chip_for_busnum returned %d\n", err); + return err; + } + + priv->current_page = 0xff; + + /* wake up device */ + dm_i2c_reg_write(priv->cec_chip, TDA19988_CEC_ENAMODS, + CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI); + + /* reset audio and I2C master */ + tda19988_register_write(priv, REG_SOFTRESET, + SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); + mdelay(50); + tda19988_register_write(priv, REG_SOFTRESET, 0); + mdelay(50); + + /* reset transmitter */ + tda19988_register_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); + tda19988_register_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); + + /* PLL registers common configuration */ + tda19988_register_write(priv, REG_PLL_SERIAL_1, 0x00); + tda19988_register_write(priv, REG_PLL_SERIAL_2, + PLL_SERIAL_2_SRL_NOSC(1)); + tda19988_register_write(priv, REG_PLL_SERIAL_3, 0x00); + tda19988_register_write(priv, REG_SERIALIZER, 0x00); + tda19988_register_write(priv, REG_BUFFER_OUT, 0x00); + tda19988_register_write(priv, REG_PLL_SCG1, 0x00); + tda19988_register_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8); + tda19988_register_write(priv, REG_SEL_CLK, + SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); + tda19988_register_write(priv, REG_PLL_SCGN1, 0xfa); + tda19988_register_write(priv, REG_PLL_SCGN2, 0x00); + tda19988_register_write(priv, REG_PLL_SCGR1, 0x5b); + tda19988_register_write(priv, REG_PLL_SCGR2, 0x00); + tda19988_register_write(priv, REG_PLL_SCG2, 0x10); + + /* Write the default value MUX register */ + tda19988_register_write(priv, REG_MUX_VP_VIP_OUT, 0x24); + + /* read version */ + rev_lo = dm_i2c_reg_read(priv->chip, REG_VERSION_LSB); + rev_hi = dm_i2c_reg_read(priv->chip, REG_VERSION_MSB); + + /* mask off feature bits */ + priv->revision = ((rev_hi << 8) | rev_lo) & ~0x30; + + printf("HDMI: "); + switch (priv->revision) { + case TDA9989N2: + printf("TDA9989 n2\n"); + break; + case TDA19989: + printf("TDA19989\n"); + break; + case TDA19989N2: + printf("TDA19989 n2\n"); + break; + case TDA19988: + printf("TDA19988\n"); + break; + default: + printf("unknown TDA device: 0x%04x\n", priv->revision); + return -ENXIO; + } + + /* after reset, enable DDC */ + tda19988_register_write(priv, REG_DDC_DISABLE, 0x00); + + /* set clock on DDC channel */ + tda19988_register_write(priv, REG_TX3, 39); + + /* if necessary, disable multi-master */ + if (priv->revision == TDA19989) + tda19988_register_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM); + + dm_i2c_reg_write(priv->cec_chip, REG_CEC_FRO_IM_CLK_CTRL, + CEC_FRO_IM_CLK_CTRL_GHOST_DIS | + CEC_FRO_IM_CLK_CTRL_IMCLK_SEL); + /* ensure interrupts are disabled */ + dm_i2c_reg_write(priv->cec_chip, REG_CEC_RXSHPDINTENA, 0); + /* clear pending interrupts */ + dm_i2c_reg_read(priv->cec_chip, REG_CEC_RXSHPDINT); + tda19988_register_read(priv, REG_INT_FLAGS_0); + tda19988_register_read(priv, REG_INT_FLAGS_1); + tda19988_register_read(priv, REG_INT_FLAGS_2); + + /* enable EDID read irq */ + tda19988_register_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); + + return 0; +} + +U_BOOT_DRIVER(tda19988) = { + .name = "tda19988", + .id = UCLASS_DISPLAY, + .of_match = tda19988_ids, + .ops = &tda19988_ops, + .probe = tda19988_probe, + .priv_auto_alloc_size = sizeof(struct tda19988_priv), +}; diff --git a/drivers/video/vidconsole-uclass.c b/drivers/video/vidconsole-uclass.c index 0c36a5de0a..7f95e9c6e5 100644 --- a/drivers/video/vidconsole-uclass.c +++ b/drivers/video/vidconsole-uclass.c @@ -165,6 +165,43 @@ static char *parsenum(char *s, int *num) return end; } +/** + * set_cursor_position() - set cursor position + * + * @priv: private data of the video console + * @row: new row + * @col: new column + */ +static void set_cursor_position(struct vidconsole_priv *priv, int row, int col) +{ + /* + * Ensure we stay in the bounds of the screen. + */ + if (row >= priv->rows) + row = priv->rows - 1; + if (col >= priv->cols) + col = priv->cols - 1; + + priv->ycur = row * priv->y_charsize; + priv->xcur_frac = priv->xstart_frac + + VID_TO_POS(col * priv->x_charsize); +} + +/** + * get_cursor_position() - get cursor position + * + * @priv: private data of the video console + * @row: row + * @col: column + */ +static void get_cursor_position(struct vidconsole_priv *priv, + int *row, int *col) +{ + *row = priv->ycur / priv->y_charsize; + *col = VID_TO_PIXEL(priv->xcur_frac - priv->xstart_frac) / + priv->x_charsize; +} + /* * Process a character while accumulating an escape string. Chars are * accumulated into escape_buf until the end of escape sequence is @@ -180,8 +217,30 @@ static void vidconsole_escape_char(struct udevice *dev, char ch) /* Sanity checking for bogus ESC sequences: */ if (priv->escape_len >= sizeof(priv->escape_buf)) goto error; - if (priv->escape_len == 0 && ch != '[') - goto error; + if (priv->escape_len == 0) { + switch (ch) { + case '7': + /* Save cursor position */ + get_cursor_position(priv, &priv->row_saved, + &priv->col_saved); + priv->escape = 0; + + return; + case '8': { + /* Restore cursor position */ + int row = priv->row_saved; + int col = priv->col_saved; + + set_cursor_position(priv, row, col); + priv->escape = 0; + return; + } + case '[': + break; + default: + goto error; + } + } priv->escape_buf[priv->escape_len++] = ch; @@ -213,17 +272,7 @@ static void vidconsole_escape_char(struct udevice *dev, char ch) s++; /* ; */ s = parsenum(s, &col); - /* - * Ensure we stay in the bounds of the screen. - */ - if (row >= priv->rows) - row = priv->rows - 1; - if (col >= priv->cols) - col = priv->cols - 1; - - priv->ycur = row * priv->y_charsize; - priv->xcur_frac = priv->xstart_frac + - VID_TO_POS(col * priv->x_charsize); + set_cursor_position(priv, row, col); break; } diff --git a/drivers/video/video_osd-uclass.c b/drivers/video/video_osd-uclass.c new file mode 100644 index 0000000000..82136a292b --- /dev/null +++ b/drivers/video/video_osd-uclass.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2017 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + */ + +#include <common.h> +#include <dm.h> +#include <video_osd.h> + +int video_osd_get_info(struct udevice *dev, struct video_osd_info *info) +{ + struct video_osd_ops *ops = video_osd_get_ops(dev); + + return ops->get_info(dev, info); +} + +int video_osd_set_mem(struct udevice *dev, uint col, uint row, u8 *buf, + size_t buflen, uint count) +{ + struct video_osd_ops *ops = video_osd_get_ops(dev); + + return ops->set_mem(dev, col, row, buf, buflen, count); +} + +int video_osd_set_size(struct udevice *dev, uint col, uint row) +{ + struct video_osd_ops *ops = video_osd_get_ops(dev); + + return ops->set_size(dev, col, row); +} + +int video_osd_print(struct udevice *dev, uint col, uint row, ulong color, + char *text) +{ + struct video_osd_ops *ops = video_osd_get_ops(dev); + + return ops->print(dev, col, row, color, text); +} + +UCLASS_DRIVER(video_osd) = { + .id = UCLASS_VIDEO_OSD, + .name = "video_osd", + .flags = DM_UC_FLAG_SEQ_ALIAS, +}; diff --git a/drivers/w1-eeprom/Kconfig b/drivers/w1-eeprom/Kconfig new file mode 100644 index 0000000000..4b7f3c4e0b --- /dev/null +++ b/drivers/w1-eeprom/Kconfig @@ -0,0 +1,29 @@ +# +# EEPROM subsystem configuration +# + +menu "1-wire EEPROM support" + +config W1_EEPROM + bool "Enable support for EEPROMs on 1wire interface" + depends on DM + help + Support for the EEPROMs connected on 1-wire Dallas protocol interface + +if W1_EEPROM + +config W1_EEPROM_DS24XXX + bool "Enable Maxim DS24 families EEPROM support" + depends on W1 + help + Maxim DS24 EEPROMs 1-Wire EEPROM support + +config W1_EEPROM_SANDBOX + bool "Enable sandbox onewire EEPROM driver" + depends on W1 + help + Sandbox driver for a onewire EEPROM memory + +endif + +endmenu diff --git a/drivers/w1-eeprom/Makefile b/drivers/w1-eeprom/Makefile new file mode 100644 index 0000000000..03cc4c8ac8 --- /dev/null +++ b/drivers/w1-eeprom/Makefile @@ -0,0 +1,5 @@ +obj-$(CONFIG_W1_EEPROM) += w1-eeprom-uclass.o + +obj-$(CONFIG_W1_EEPROM_DS24XXX) += ds24xxx.o + +obj-$(CONFIG_W1_EEPROM_SANDBOX) += eep_sandbox.o diff --git a/drivers/w1-eeprom/ds24xxx.c b/drivers/w1-eeprom/ds24xxx.c new file mode 100644 index 0000000000..56186e587c --- /dev/null +++ b/drivers/w1-eeprom/ds24xxx.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * + * Copyright (c) 2015 Free Electrons + * Copyright (c) 2015 NextThing Co + * Copyright (c) 2018 Microchip Technology, Inc. + * + */ + +#include <common.h> +#include <linux/err.h> +#include <dm.h> +#include <w1-eeprom.h> +#include <w1.h> + +#define W1_F2D_READ_EEPROM 0xf0 + +static int ds24xxx_read_buf(struct udevice *dev, unsigned int offset, + u8 *buf, unsigned int count) +{ + w1_reset_select(dev); + + w1_write_byte(dev, W1_F2D_READ_EEPROM); + w1_write_byte(dev, offset & 0xff); + w1_write_byte(dev, offset >> 8); + + return w1_read_buf(dev, buf, count); +} + +static int ds24xxx_probe(struct udevice *dev) +{ + struct w1_device *w1; + + w1 = dev_get_platdata(dev); + w1->id = 0; + return 0; +} + +static const struct w1_eeprom_ops ds24xxx_ops = { + .read_buf = ds24xxx_read_buf, +}; + +static const struct udevice_id ds24xxx_id[] = { + { .compatible = "maxim,ds24b33", .data = W1_FAMILY_DS24B33 }, + { .compatible = "maxim,ds2431", .data = W1_FAMILY_DS2431 }, + { }, +}; + +U_BOOT_DRIVER(ds24xxx) = { + .name = "ds24xxx", + .id = UCLASS_W1_EEPROM, + .of_match = ds24xxx_id, + .ops = &ds24xxx_ops, + .probe = ds24xxx_probe, +}; diff --git a/drivers/w1-eeprom/eep_sandbox.c b/drivers/w1-eeprom/eep_sandbox.c new file mode 100644 index 0000000000..27c7f9f1b6 --- /dev/null +++ b/drivers/w1-eeprom/eep_sandbox.c @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (c) 2018 Microchip Technology, Inc. + * + */ + +#include <common.h> +#include <linux/err.h> +#include <dm.h> +#include <w1-eeprom.h> +#include <w1.h> + +#define W1_F2D_READ_EEPROM 0xf0 + +#define EEP_SANDBOX_SAMPLE_MEM "this is a sample EEPROM memory string." + +static int eep_sandbox_read_buf(struct udevice *dev, unsigned int offset, + u8 *buf, unsigned int count) +{ + /* do not allow to copy more than our maximum sample string */ + if (offset + count < strlen(EEP_SANDBOX_SAMPLE_MEM)) { + offset = 0; + count = strlen(EEP_SANDBOX_SAMPLE_MEM); + } + strncpy((char *)buf, EEP_SANDBOX_SAMPLE_MEM, count); + + /* + * in case the w1 subsystem uses some different kind of sandbox testing, + * like randomized gpio values , we take the buffer from there + */ + + w1_reset_select(dev); + + w1_write_byte(dev, W1_F2D_READ_EEPROM); + w1_write_byte(dev, offset & 0xff); + w1_write_byte(dev, offset >> 8); + + w1_read_buf(dev, buf, count); + + /* + * even if read buf from w1 fails, return success as we hardcoded + * the buffer. + */ + return 0; +} + +static const struct w1_eeprom_ops eep_sandbox_ops = { + .read_buf = eep_sandbox_read_buf, +}; + +static const struct udevice_id eep_sandbox_id[] = { + { .compatible = "sandbox,w1-eeprom", .data = W1_FAMILY_EEP_SANDBOX }, + { }, +}; + +U_BOOT_DRIVER(eep_sandbox) = { + .name = "eep_sandbox", + .id = UCLASS_W1_EEPROM, + .of_match = eep_sandbox_id, + .ops = &eep_sandbox_ops, +}; diff --git a/drivers/w1-eeprom/w1-eeprom-uclass.c b/drivers/w1-eeprom/w1-eeprom-uclass.c new file mode 100644 index 0000000000..7b0579344c --- /dev/null +++ b/drivers/w1-eeprom/w1-eeprom-uclass.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * + * Copyright (c) 2015 Free Electrons + * Copyright (c) 2015 NextThing Co. + * Copyright (c) 2018 Microchip Technology, Inc. + * + * Maxime Ripard <maxime.ripard@free-electrons.com> + * Eugen Hristev <eugen.hristev@microchip.com> + * + */ + +#include <common.h> +#include <dm.h> +#include <w1.h> +#include <w1-eeprom.h> + +#include <dm/device-internal.h> + +int w1_eeprom_read_buf(struct udevice *dev, unsigned int offset, + u8 *buf, unsigned int count) +{ + const struct w1_eeprom_ops *ops = device_get_ops(dev); + u64 id = 0; + int ret; + + if (!ops->read_buf) + return -ENOSYS; + + ret = w1_eeprom_get_id(dev, &id); + if (ret) + return ret; + if (!id) + return -ENODEV; + + return ops->read_buf(dev, offset, buf, count); +} + +int w1_eeprom_register_new_device(u64 id) +{ + u8 family = id & 0xff; + int ret; + struct udevice *dev; + + for (ret = uclass_first_device(UCLASS_W1_EEPROM, &dev); + !ret && dev; + uclass_next_device(&dev)) { + if (ret || !dev) { + debug("cannot find w1 eeprom dev\n"); + return ret; + } + if (dev_get_driver_data(dev) == family) { + struct w1_device *w1; + + w1 = dev_get_parent_platdata(dev); + if (w1->id) /* device already in use */ + continue; + w1->id = id; + debug("%s: Match found: %s:%s %llx\n", __func__, + dev->name, dev->driver->name, id); + return 0; + } + } + + debug("%s: No matches found: error %d\n", __func__, ret); + + return ret; +} + +int w1_eeprom_get_id(struct udevice *dev, u64 *id) +{ + struct w1_device *w1 = dev_get_parent_platdata(dev); + + if (!w1) + return -ENODEV; + *id = w1->id; + + return 0; +} + +UCLASS_DRIVER(w1_eeprom) = { + .name = "w1_eeprom", + .id = UCLASS_W1_EEPROM, + .flags = DM_UC_FLAG_SEQ_ALIAS, +#if CONFIG_IS_ENABLED(OF_CONTROL) + .post_bind = dm_scan_fdt_dev, +#endif +}; + +int w1_eeprom_dm_init(void) +{ + struct udevice *dev; + struct uclass *uc; + int ret; + + ret = uclass_get(UCLASS_W1_EEPROM, &uc); + if (ret) { + debug("W1_EEPROM uclass not available\n"); + return ret; + } + + uclass_foreach_dev(dev, uc) { + ret = device_probe(dev); + if (ret == -ENODEV) { /* No such device. */ + debug("W1_EEPROM not available.\n"); + continue; + } + + if (ret) { /* Other error. */ + printf("W1_EEPROM probe failed, error %d\n", ret); + continue; + } + } + + return 0; +} diff --git a/drivers/w1/Kconfig b/drivers/w1/Kconfig new file mode 100644 index 0000000000..d6e045739d --- /dev/null +++ b/drivers/w1/Kconfig @@ -0,0 +1,25 @@ +# +# W1 subsystem configuration +# + +menu "1-Wire support" + +config W1 + bool "Enable 1-wire controllers support" + default no + depends on DM + help + Support for the Dallas 1-Wire bus. + +if W1 + +config W1_GPIO + bool "Enable 1-wire GPIO bitbanging" + default no + depends on DM_GPIO + help + Emulate a 1-wire bus using a GPIO. + +endif + +endmenu diff --git a/drivers/w1/Makefile b/drivers/w1/Makefile new file mode 100644 index 0000000000..7fd8697f84 --- /dev/null +++ b/drivers/w1/Makefile @@ -0,0 +1,3 @@ +obj-$(CONFIG_W1) += w1-uclass.o + +obj-$(CONFIG_W1_GPIO) += w1-gpio.o diff --git a/drivers/w1/w1-gpio.c b/drivers/w1/w1-gpio.c new file mode 100644 index 0000000000..5e5d6b3f6c --- /dev/null +++ b/drivers/w1/w1-gpio.c @@ -0,0 +1,176 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (c) 2015 Free Electrons + * Copyright (c) 2015 NextThing Co + * + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + */ + +#include <common.h> +#include <dm.h> +#include <w1.h> + +#include <asm/gpio.h> + +#define W1_TIMING_A 6 +#define W1_TIMING_B 64 +#define W1_TIMING_C 60 +#define W1_TIMING_D 10 +#define W1_TIMING_E 9 +#define W1_TIMING_F 55 +#define W1_TIMING_G 0 +#define W1_TIMING_H 480 +#define W1_TIMING_I 70 +#define W1_TIMING_J 410 + +struct w1_gpio_pdata { + struct gpio_desc gpio; + u64 search_id; +}; + +static bool w1_gpio_read_bit(struct udevice *dev) +{ + struct w1_gpio_pdata *pdata = dev_get_platdata(dev); + int val; + + dm_gpio_set_dir_flags(&pdata->gpio, GPIOD_IS_OUT); + udelay(W1_TIMING_A); + + dm_gpio_set_dir_flags(&pdata->gpio, GPIOD_IS_IN); + udelay(W1_TIMING_E); + + val = dm_gpio_get_value(&pdata->gpio); + if (val < 0) + debug("error in retrieving GPIO value"); + udelay(W1_TIMING_F); + + return val; +} + +static u8 w1_gpio_read_byte(struct udevice *dev) +{ + int i; + u8 ret = 0; + + for (i = 0; i < 8; ++i) + ret |= (w1_gpio_read_bit(dev) ? 1 : 0) << i; + + return ret; +} + +static void w1_gpio_write_bit(struct udevice *dev, bool bit) +{ + struct w1_gpio_pdata *pdata = dev_get_platdata(dev); + + dm_gpio_set_dir_flags(&pdata->gpio, GPIOD_IS_OUT); + + bit ? udelay(W1_TIMING_A) : udelay(W1_TIMING_C); + + dm_gpio_set_value(&pdata->gpio, 1); + + bit ? udelay(W1_TIMING_B) : udelay(W1_TIMING_D); +} + +static void w1_gpio_write_byte(struct udevice *dev, u8 byte) +{ + int i; + + for (i = 0; i < 8; ++i) + w1_gpio_write_bit(dev, (byte >> i) & 0x1); +} + +static bool w1_gpio_reset(struct udevice *dev) +{ + struct w1_gpio_pdata *pdata = dev_get_platdata(dev); + int val; + + /* initiate the reset pulse. first we must pull the bus to low */ + dm_gpio_set_dir_flags(&pdata->gpio, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + udelay(W1_TIMING_G); + + dm_gpio_set_value(&pdata->gpio, 0); + /* wait for the specified time with the bus kept low */ + udelay(W1_TIMING_H); + + /* now we must read the presence pulse */ + dm_gpio_set_dir_flags(&pdata->gpio, GPIOD_IS_IN); + udelay(W1_TIMING_I); + + val = dm_gpio_get_value(&pdata->gpio); + if (val < 0) + debug("error in retrieving GPIO value"); + + /* if nobody pulled the bus down , it means nobody is on the bus */ + if (val != 0) + return 1; + /* we have the bus pulled down, let's wait for the specified presence time */ + udelay(W1_TIMING_J); + + /* read again, the other end should leave the bus free */ + val = dm_gpio_get_value(&pdata->gpio); + if (val < 0) + debug("error in retrieving GPIO value"); + + /* bus is not going up again, so we have an error */ + if (val != 1) + return 1; + + /* all good, presence detected */ + return 0; +} + +static u8 w1_gpio_triplet(struct udevice *dev, bool bdir) +{ + u8 id_bit = w1_gpio_read_bit(dev); + u8 comp_bit = w1_gpio_read_bit(dev); + u8 retval; + + if (id_bit && comp_bit) + return 0x03; /* error */ + + if (!id_bit && !comp_bit) { + /* Both bits are valid, take the direction given */ + retval = bdir ? 0x04 : 0; + } else { + /* Only one bit is valid, take that direction */ + bdir = id_bit; + retval = id_bit ? 0x05 : 0x02; + } + + w1_gpio_write_bit(dev, bdir); + return retval; +} + +static const struct w1_ops w1_gpio_ops = { + .read_byte = w1_gpio_read_byte, + .reset = w1_gpio_reset, + .triplet = w1_gpio_triplet, + .write_byte = w1_gpio_write_byte, +}; + +static int w1_gpio_ofdata_to_platdata(struct udevice *dev) +{ + struct w1_gpio_pdata *pdata = dev_get_platdata(dev); + int ret; + + ret = gpio_request_by_name(dev, "gpios", 0, &pdata->gpio, 0); + if (ret < 0) + printf("Error claiming GPIO %d\n", ret); + + return ret; +}; + +static const struct udevice_id w1_gpio_id[] = { + { "w1-gpio", 0 }, + { }, +}; + +U_BOOT_DRIVER(w1_gpio_drv) = { + .id = UCLASS_W1, + .name = "w1_gpio_drv", + .of_match = w1_gpio_id, + .ofdata_to_platdata = w1_gpio_ofdata_to_platdata, + .ops = &w1_gpio_ops, + .platdata_auto_alloc_size = sizeof(struct w1_gpio_pdata), +}; diff --git a/drivers/w1/w1-uclass.c b/drivers/w1/w1-uclass.c new file mode 100644 index 0000000000..aecf7fec77 --- /dev/null +++ b/drivers/w1/w1-uclass.c @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * + * Copyright (c) 2015 Free Electrons + * Copyright (c) 2015 NextThing Co. + * Copyright (c) 2018 Microchip Technology, Inc. + * + * Maxime Ripard <maxime.ripard@free-electrons.com> + * Eugen Hristev <eugen.hristev@microchip.com> + * + */ + +#include <common.h> +#include <dm.h> +#include <w1.h> +#include <w1-eeprom.h> + +#include <dm/device-internal.h> + +#define W1_MATCH_ROM 0x55 +#define W1_SKIP_ROM 0xcc +#define W1_SEARCH 0xf0 + +struct w1_bus { + u64 search_id; +}; + +static int w1_enumerate(struct udevice *bus) +{ + const struct w1_ops *ops = device_get_ops(bus); + struct w1_bus *w1 = dev_get_uclass_priv(bus); + u64 last_rn, rn = w1->search_id, tmp64; + bool last_device = false; + int search_bit, desc_bit = 64; + int last_zero = -1; + u8 triplet_ret = 0; + int i; + + if (!ops->reset || !ops->write_byte || !ops->triplet) + return -ENOSYS; + + while (!last_device) { + last_rn = rn; + rn = 0; + + /* + * Reset bus and all 1-wire device state machines + * so they can respond to our requests. + * + * Return 0 - device(s) present, 1 - no devices present. + */ + if (ops->reset(bus)) { + debug("%s: No devices present on the wire.\n", + __func__); + break; + } + + /* Start the search */ + ops->write_byte(bus, W1_SEARCH); + for (i = 0; i < 64; ++i) { + /* Determine the direction/search bit */ + if (i == desc_bit) + /* took the 0 path last time, so take the 1 path */ + search_bit = 1; + else if (i > desc_bit) + /* take the 0 path on the next branch */ + search_bit = 0; + else + search_bit = ((last_rn >> i) & 0x1); + + /* Read two bits and write one bit */ + triplet_ret = ops->triplet(bus, search_bit); + + /* quit if no device responded */ + if ((triplet_ret & 0x03) == 0x03) + break; + + /* If both directions were valid, and we took the 0 path... */ + if (triplet_ret == 0) + last_zero = i; + + /* extract the direction taken & update the device number */ + tmp64 = (triplet_ret >> 2); + rn |= (tmp64 << i); + } + + /* last device or error, aborting here */ + if ((triplet_ret & 0x03) == 0x03) + last_device = true; + + if ((triplet_ret & 0x03) != 0x03) { + if (desc_bit == last_zero || last_zero < 0) { + last_device = 1; + w1->search_id = 0; + } else { + w1->search_id = rn; + } + desc_bit = last_zero; + + debug("%s: Detected new device 0x%llx (family 0x%x)\n", + bus->name, rn, (u8)(rn & 0xff)); + + /* attempt to register as w1-eeprom device */ + w1_eeprom_register_new_device(rn); + } + } + + return 0; +} + +int w1_get_bus(int busnum, struct udevice **busp) +{ + int ret, i = 0; + + struct udevice *dev; + + for (ret = uclass_first_device(UCLASS_W1, &dev); + !ret; + uclass_next_device(&dev), i++) { + if (ret) { + debug("Cannot find w1 bus %d\n", busnum); + return ret; + } + if (i == busnum) { + *busp = dev; + return 0; + } + } + return ret; +} + +u8 w1_get_device_family(struct udevice *dev) +{ + struct w1_device *w1 = dev_get_parent_platdata(dev); + + return w1->id & 0xff; +} + +int w1_reset_select(struct udevice *dev) +{ + struct w1_device *w1 = dev_get_parent_platdata(dev); + struct udevice *bus = dev_get_parent(dev); + const struct w1_ops *ops = device_get_ops(bus); + int i; + + if (!ops->reset || !ops->write_byte) + return -ENOSYS; + + ops->reset(bus); + + ops->write_byte(bus, W1_MATCH_ROM); + + for (i = 0; i < sizeof(w1->id); i++) + ops->write_byte(bus, (w1->id >> (i * 8)) & 0xff); + + return 0; +} + +int w1_read_byte(struct udevice *dev) +{ + struct udevice *bus = dev_get_parent(dev); + const struct w1_ops *ops = device_get_ops(bus); + + if (!ops->read_byte) + return -ENOSYS; + + return ops->read_byte(bus); +} + +int w1_read_buf(struct udevice *dev, u8 *buf, unsigned int count) +{ + int i, ret; + + for (i = 0; i < count; i++) { + ret = w1_read_byte(dev); + if (ret < 0) + return ret; + + buf[i] = ret & 0xff; + } + + return 0; +} + +int w1_write_byte(struct udevice *dev, u8 byte) +{ + struct udevice *bus = dev_get_parent(dev); + const struct w1_ops *ops = device_get_ops(bus); + + if (!ops->write_byte) + return -ENOSYS; + + ops->write_byte(bus, byte); + + return 0; +} + +static int w1_post_probe(struct udevice *bus) +{ + w1_enumerate(bus); + + return 0; +} + +int w1_init(void) +{ + struct udevice *bus; + struct uclass *uc; + int ret; + + ret = uclass_get(UCLASS_W1, &uc); + if (ret) + return ret; + + uclass_foreach_dev(bus, uc) { + ret = device_probe(bus); + if (ret == -ENODEV) { /* No such device. */ + printf("W1 controller not available.\n"); + continue; + } + + if (ret) { /* Other error. */ + printf("W1 controller probe failed.\n"); + continue; + } + } + return 0; +} + +UCLASS_DRIVER(w1) = { + .name = "w1", + .id = UCLASS_W1, + .flags = DM_UC_FLAG_SEQ_ALIAS, + .per_device_auto_alloc_size = sizeof(struct w1_bus), + .post_probe = w1_post_probe, +#if CONFIG_IS_ENABLED(OF_CONTROL) + .post_bind = dm_scan_fdt_dev, +#endif + .per_child_platdata_auto_alloc_size = sizeof(struct w1_device), +}; diff --git a/dts/Makefile b/dts/Makefile index 36dfbe76d1..9a9a3d5c98 100644 --- a/dts/Makefile +++ b/dts/Makefile @@ -61,4 +61,4 @@ dtbs: $(obj)/dt.dtb $(obj)/dt-spl.dtb clean-files := dt.dtb.S dt-spl.dtb.S # Let clean descend into dts directories -subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/mips/dts ../arch/sandbox/dts ../arch/x86/dts +subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/mips/dts ../arch/sandbox/dts ../arch/x86/dts ../arch/powerpc/dts diff --git a/fs/btrfs/ctree.c b/fs/btrfs/ctree.c index 4da36a9bc7..18b47d92fe 100644 --- a/fs/btrfs/ctree.c +++ b/fs/btrfs/ctree.c @@ -7,6 +7,7 @@ #include "btrfs.h" #include <malloc.h> +#include <memalign.h> int btrfs_comp_keys(struct btrfs_key *a, struct btrfs_key *b) { @@ -105,23 +106,24 @@ void btrfs_free_path(struct btrfs_path *p) static int read_tree_node(u64 physical, union btrfs_tree_node **buf) { - struct btrfs_header hdr; - unsigned long size, offset = sizeof(hdr); + ALLOC_CACHE_ALIGN_BUFFER(struct btrfs_header, hdr, + sizeof(struct btrfs_header)); + unsigned long size, offset = sizeof(*hdr); union btrfs_tree_node *res; u32 i; - if (!btrfs_devread(physical, sizeof(hdr), &hdr)) + if (!btrfs_devread(physical, sizeof(*hdr), hdr)) return -1; - btrfs_header_to_cpu(&hdr); + btrfs_header_to_cpu(hdr); - if (hdr.level) + if (hdr->level) size = sizeof(struct btrfs_node) - + hdr.nritems * sizeof(struct btrfs_key_ptr); + + hdr->nritems * sizeof(struct btrfs_key_ptr); else size = btrfs_info.sb.nodesize; - res = malloc(size); + res = malloc_cache_aligned(size); if (!res) { debug("%s: malloc failed\n", __func__); return -1; @@ -133,12 +135,12 @@ static int read_tree_node(u64 physical, union btrfs_tree_node **buf) return -1; } - res->header = hdr; - if (hdr.level) - for (i = 0; i < hdr.nritems; ++i) + memcpy(&res->header, hdr, sizeof(*hdr)); + if (hdr->level) + for (i = 0; i < hdr->nritems; ++i) btrfs_key_ptr_to_cpu(&res->node.ptrs[i]); else - for (i = 0; i < hdr.nritems; ++i) + for (i = 0; i < hdr->nritems; ++i) btrfs_item_to_cpu(&res->leaf.items[i]); *buf = res; diff --git a/fs/btrfs/extent-io.c b/fs/btrfs/extent-io.c index 7263f41644..66d0e1c7d6 100644 --- a/fs/btrfs/extent-io.c +++ b/fs/btrfs/extent-io.c @@ -7,6 +7,7 @@ #include "btrfs.h" #include <malloc.h> +#include <memalign.h> u64 btrfs_read_extent_inline(struct btrfs_path *path, struct btrfs_file_extent_item *extent, u64 offset, @@ -89,7 +90,7 @@ u64 btrfs_read_extent_reg(struct btrfs_path *path, return size; } - cbuf = malloc(dlen > size ? clen + dlen : clen); + cbuf = malloc_cache_aligned(dlen > size ? clen + dlen : clen); if (!cbuf) return -1ULL; diff --git a/fs/btrfs/super.c b/fs/btrfs/super.c index e680caa56a..7aaf8f9b0d 100644 --- a/fs/btrfs/super.c +++ b/fs/btrfs/super.c @@ -6,6 +6,7 @@ */ #include "btrfs.h" +#include <memalign.h> #define BTRFS_SUPER_FLAG_SUPP (BTRFS_HEADER_FLAG_WRITTEN \ | BTRFS_HEADER_FLAG_RELOC \ @@ -179,7 +180,7 @@ int btrfs_read_superblock(void) 0x4000000000ull, 0x4000000000000ull }; - char raw_sb[BTRFS_SUPER_INFO_SIZE]; + ALLOC_CACHE_ALIGN_BUFFER(char, raw_sb, BTRFS_SUPER_INFO_SIZE); struct btrfs_super_block *sb = (struct btrfs_super_block *) raw_sb; u64 dev_total_bytes; int i; diff --git a/include/blk.h b/include/blk.h index 86f6d5057f..6af219681c 100644 --- a/include/blk.h +++ b/include/blk.h @@ -406,6 +406,15 @@ int blk_select_hwpart(struct udevice *dev, int hwpart); */ int blk_get_from_parent(struct udevice *parent, struct udevice **devp); +/** + * blk_get_by_device() - Get the block device descriptor for the given device + * @dev: Instance of a storage device + * + * Return: With block device descriptor on success , NULL if there is no such + * block device. + */ +struct blk_desc *blk_get_by_device(struct udevice *dev); + #else #include <errno.h> /* diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 8a38c5e19c..191616b8b0 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -659,7 +659,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_DPAA_FMAN #define CONFIG_QE -#define CONFIG_U_QE /* Default address of microcode for the Linux FMan driver */ #if defined(CONFIG_SPIFLASH) /* diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index f7a54f7a97..ac5de8d164 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -669,7 +669,6 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_TARGET_T1024RDB #define CONFIG_QE -#define CONFIG_U_QE #endif /* Default address of microcode for the Linux FMan driver */ #if defined(CONFIG_SPIFLASH) diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index e890860b7e..25615be40e 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -549,7 +549,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_DPAA_PME #define CONFIG_QE -#define CONFIG_U_QE /* Default address of microcode for the Linux Fman driver */ #if defined(CONFIG_SPIFLASH) /* diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 14a6b9e591..319f6aadf5 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -116,7 +116,7 @@ * Serial Driver info */ -#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_DIRECT_NOR_BOOT) +#if !CONFIG_IS_ENABLED(DM_SERIAL) #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h index 8129595d51..e450002e83 100644 --- a/include/configs/ls1012afrwy.h +++ b/include/configs/ls1012afrwy.h @@ -9,9 +9,9 @@ #include "ls1012a_common.h" /* Board Rev*/ -#define BOARD_REV_A 0x0 -#define BOARD_REV_B 0x200 - +#define BOARD_REV_A_B 0x0 +#define BOARD_REV_C 0x00080000 +#define BOARD_REV_MASK 0x001A0000 /* DDR */ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 994e6ca362..7f7ffdede1 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -107,7 +107,6 @@ unsigned long get_board_ddr_clk(void); #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ !defined(CONFIG_QSPI_BOOT) -#define CONFIG_U_QE #define CONFIG_SYS_QE_FMAN_FW_IN_NOR #endif diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 75b2e2fbbd..ddd024e8c0 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -106,7 +106,6 @@ #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ !defined(CONFIG_QSPI_BOOT) -#define CONFIG_U_QE #define CONFIG_SYS_QE_FMAN_FW_IN_NOR #endif diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index bc639e586f..ffd92dbb43 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -268,13 +268,6 @@ #endif #endif -/* QE */ -#ifndef SPL_NO_QE -#if !defined(CONFIG_NAND_BOOT) && !defined(CONFIG_QSPI_BOOT) -#define CONFIG_U_QE -#endif -#endif - /* SATA */ #ifndef SPL_NO_SATA #ifndef CONFIG_CMD_EXT2 diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index eb220bf6e9..363154a40b 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -455,8 +455,7 @@ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ - func(SCSI, scsi, 0) \ - func(DHCP, dhcp, na) + func(SCSI, scsi, 0) #include <config_distro_bootcmd.h> #endif diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 3d53a69e8a..05c02df52e 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -323,8 +323,7 @@ unsigned long get_board_sys_clk(void); #define BOOT_TARGET_DEVICES(func) \ func(USB, usb, 0) \ func(MMC, mmc, 0) \ - func(SCSI, scsi, 0) \ - func(DHCP, dhcp, na) + func(SCSI, scsi, 0) #include <config_distro_bootcmd.h> #ifdef CONFIG_QSPI_BOOT diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 5e19465894..79fd3008d5 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -38,6 +38,7 @@ enum uclass_id { UCLASS_DMA, /* Direct Memory Access */ UCLASS_EFI, /* EFI managed devices */ UCLASS_ETH, /* Ethernet device */ + UCLASS_FS_FIRMWARE_LOADER, /* Generic loader */ UCLASS_GPIO, /* Bank of general-purpose I/O pins */ UCLASS_FIRMWARE, /* Firmware */ UCLASS_I2C, /* I2C bus */ @@ -93,6 +94,9 @@ enum uclass_id { UCLASS_VIDEO, /* Video or LCD device */ UCLASS_VIDEO_BRIDGE, /* Video bridge, e.g. DisplayPort to LVDS */ UCLASS_VIDEO_CONSOLE, /* Text console driver for video device */ + UCLASS_VIDEO_OSD, /* On-screen display */ + UCLASS_W1, /* Dallas 1-Wire bus */ + UCLASS_W1_EEPROM, /* one-wire EEPROMs */ UCLASS_WDT, /* Watchdot Timer driver */ UCLASS_COUNT, diff --git a/include/dt-bindings/clock/sun4i-a10-ccu.h b/include/dt-bindings/clock/sun4i-a10-ccu.h new file mode 100644 index 0000000000..e4fa61be5c --- /dev/null +++ b/include/dt-bindings/clock/sun4i-a10-ccu.h @@ -0,0 +1,202 @@ +/* + * Copyright (C) 2017 Priit Laes <plaes@plaes.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_CLK_SUN4I_A10_H_ +#define _DT_BINDINGS_CLK_SUN4I_A10_H_ + +#define CLK_HOSC 1 +#define CLK_PLL_VIDEO0_2X 9 +#define CLK_PLL_VIDEO1_2X 18 +#define CLK_CPU 20 + +/* AHB Gates */ +#define CLK_AHB_OTG 26 +#define CLK_AHB_EHCI0 27 +#define CLK_AHB_OHCI0 28 +#define CLK_AHB_EHCI1 29 +#define CLK_AHB_OHCI1 30 +#define CLK_AHB_SS 31 +#define CLK_AHB_DMA 32 +#define CLK_AHB_BIST 33 +#define CLK_AHB_MMC0 34 +#define CLK_AHB_MMC1 35 +#define CLK_AHB_MMC2 36 +#define CLK_AHB_MMC3 37 +#define CLK_AHB_MS 38 +#define CLK_AHB_NAND 39 +#define CLK_AHB_SDRAM 40 +#define CLK_AHB_ACE 41 +#define CLK_AHB_EMAC 42 +#define CLK_AHB_TS 43 +#define CLK_AHB_SPI0 44 +#define CLK_AHB_SPI1 45 +#define CLK_AHB_SPI2 46 +#define CLK_AHB_SPI3 47 +#define CLK_AHB_PATA 48 +#define CLK_AHB_SATA 49 +#define CLK_AHB_GPS 50 +#define CLK_AHB_HSTIMER 51 +#define CLK_AHB_VE 52 +#define CLK_AHB_TVD 53 +#define CLK_AHB_TVE0 54 +#define CLK_AHB_TVE1 55 +#define CLK_AHB_LCD0 56 +#define CLK_AHB_LCD1 57 +#define CLK_AHB_CSI0 58 +#define CLK_AHB_CSI1 59 +#define CLK_AHB_HDMI0 60 +#define CLK_AHB_HDMI1 61 +#define CLK_AHB_DE_BE0 62 +#define CLK_AHB_DE_BE1 63 +#define CLK_AHB_DE_FE0 64 +#define CLK_AHB_DE_FE1 65 +#define CLK_AHB_GMAC 66 +#define CLK_AHB_MP 67 +#define CLK_AHB_GPU 68 + +/* APB0 Gates */ +#define CLK_APB0_CODEC 69 +#define CLK_APB0_SPDIF 70 +#define CLK_APB0_I2S0 71 +#define CLK_APB0_AC97 72 +#define CLK_APB0_I2S1 73 +#define CLK_APB0_PIO 74 +#define CLK_APB0_IR0 75 +#define CLK_APB0_IR1 76 +#define CLK_APB0_I2S2 77 +#define CLK_APB0_KEYPAD 78 + +/* APB1 Gates */ +#define CLK_APB1_I2C0 79 +#define CLK_APB1_I2C1 80 +#define CLK_APB1_I2C2 81 +#define CLK_APB1_I2C3 82 +#define CLK_APB1_CAN 83 +#define CLK_APB1_SCR 84 +#define CLK_APB1_PS20 85 +#define CLK_APB1_PS21 86 +#define CLK_APB1_I2C4 87 +#define CLK_APB1_UART0 88 +#define CLK_APB1_UART1 89 +#define CLK_APB1_UART2 90 +#define CLK_APB1_UART3 91 +#define CLK_APB1_UART4 92 +#define CLK_APB1_UART5 93 +#define CLK_APB1_UART6 94 +#define CLK_APB1_UART7 95 + +/* IP clocks */ +#define CLK_NAND 96 +#define CLK_MS 97 +#define CLK_MMC0 98 +#define CLK_MMC0_OUTPUT 99 +#define CLK_MMC0_SAMPLE 100 +#define CLK_MMC1 101 +#define CLK_MMC1_OUTPUT 102 +#define CLK_MMC1_SAMPLE 103 +#define CLK_MMC2 104 +#define CLK_MMC2_OUTPUT 105 +#define CLK_MMC2_SAMPLE 106 +#define CLK_MMC3 107 +#define CLK_MMC3_OUTPUT 108 +#define CLK_MMC3_SAMPLE 109 +#define CLK_TS 110 +#define CLK_SS 111 +#define CLK_SPI0 112 +#define CLK_SPI1 113 +#define CLK_SPI2 114 +#define CLK_PATA 115 +#define CLK_IR0 116 +#define CLK_IR1 117 +#define CLK_I2S0 118 +#define CLK_AC97 119 +#define CLK_SPDIF 120 +#define CLK_KEYPAD 121 +#define CLK_SATA 122 +#define CLK_USB_OHCI0 123 +#define CLK_USB_OHCI1 124 +#define CLK_USB_PHY 125 +#define CLK_GPS 126 +#define CLK_SPI3 127 +#define CLK_I2S1 128 +#define CLK_I2S2 129 + +/* DRAM Gates */ +#define CLK_DRAM_VE 130 +#define CLK_DRAM_CSI0 131 +#define CLK_DRAM_CSI1 132 +#define CLK_DRAM_TS 133 +#define CLK_DRAM_TVD 134 +#define CLK_DRAM_TVE0 135 +#define CLK_DRAM_TVE1 136 +#define CLK_DRAM_OUT 137 +#define CLK_DRAM_DE_FE1 138 +#define CLK_DRAM_DE_FE0 139 +#define CLK_DRAM_DE_BE0 140 +#define CLK_DRAM_DE_BE1 141 +#define CLK_DRAM_MP 142 +#define CLK_DRAM_ACE 143 + +/* Display Engine Clocks */ +#define CLK_DE_BE0 144 +#define CLK_DE_BE1 145 +#define CLK_DE_FE0 146 +#define CLK_DE_FE1 147 +#define CLK_DE_MP 148 +#define CLK_TCON0_CH0 149 +#define CLK_TCON1_CH0 150 +#define CLK_CSI_SCLK 151 +#define CLK_TVD_SCLK2 152 +#define CLK_TVD 153 +#define CLK_TCON0_CH1_SCLK2 154 +#define CLK_TCON0_CH1 155 +#define CLK_TCON1_CH1_SCLK2 156 +#define CLK_TCON1_CH1 157 +#define CLK_CSI0 158 +#define CLK_CSI1 159 +#define CLK_CODEC 160 +#define CLK_VE 161 +#define CLK_AVS 162 +#define CLK_ACE 163 +#define CLK_HDMI 164 +#define CLK_GPU 165 + +#endif /* _DT_BINDINGS_CLK_SUN4I_A10_H_ */ diff --git a/include/dt-bindings/clock/sun5i-ccu.h b/include/dt-bindings/clock/sun5i-ccu.h new file mode 100644 index 0000000000..81f34d477a --- /dev/null +++ b/include/dt-bindings/clock/sun5i-ccu.h @@ -0,0 +1,106 @@ +/* + * Copyright 2016 Maxime Ripard + * + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_SUN5I_H_ +#define _DT_BINDINGS_CLK_SUN5I_H_ + +#define CLK_HOSC 1 + +#define CLK_PLL_VIDEO0_2X 9 + +#define CLK_PLL_VIDEO1_2X 16 +#define CLK_CPU 17 + +#define CLK_AHB_OTG 23 +#define CLK_AHB_EHCI 24 +#define CLK_AHB_OHCI 25 +#define CLK_AHB_SS 26 +#define CLK_AHB_DMA 27 +#define CLK_AHB_BIST 28 +#define CLK_AHB_MMC0 29 +#define CLK_AHB_MMC1 30 +#define CLK_AHB_MMC2 31 +#define CLK_AHB_NAND 32 +#define CLK_AHB_SDRAM 33 +#define CLK_AHB_EMAC 34 +#define CLK_AHB_TS 35 +#define CLK_AHB_SPI0 36 +#define CLK_AHB_SPI1 37 +#define CLK_AHB_SPI2 38 +#define CLK_AHB_GPS 39 +#define CLK_AHB_HSTIMER 40 +#define CLK_AHB_VE 41 +#define CLK_AHB_TVE 42 +#define CLK_AHB_LCD 43 +#define CLK_AHB_CSI 44 +#define CLK_AHB_HDMI 45 +#define CLK_AHB_DE_BE 46 +#define CLK_AHB_DE_FE 47 +#define CLK_AHB_IEP 48 +#define CLK_AHB_GPU 49 +#define CLK_APB0_CODEC 50 +#define CLK_APB0_SPDIF 51 +#define CLK_APB0_I2S 52 +#define CLK_APB0_PIO 53 +#define CLK_APB0_IR 54 +#define CLK_APB0_KEYPAD 55 +#define CLK_APB1_I2C0 56 +#define CLK_APB1_I2C1 57 +#define CLK_APB1_I2C2 58 +#define CLK_APB1_UART0 59 +#define CLK_APB1_UART1 60 +#define CLK_APB1_UART2 61 +#define CLK_APB1_UART3 62 +#define CLK_NAND 63 +#define CLK_MMC0 64 +#define CLK_MMC1 65 +#define CLK_MMC2 66 +#define CLK_TS 67 +#define CLK_SS 68 +#define CLK_SPI0 69 +#define CLK_SPI1 70 +#define CLK_SPI2 71 +#define CLK_IR 72 +#define CLK_I2S 73 +#define CLK_SPDIF 74 +#define CLK_KEYPAD 75 +#define CLK_USB_OHCI 76 +#define CLK_USB_PHY0 77 +#define CLK_USB_PHY1 78 +#define CLK_GPS 79 +#define CLK_DRAM_VE 80 +#define CLK_DRAM_CSI 81 +#define CLK_DRAM_TS 82 +#define CLK_DRAM_TVE 83 +#define CLK_DRAM_DE_FE 84 +#define CLK_DRAM_DE_BE 85 +#define CLK_DRAM_ACE 86 +#define CLK_DRAM_IEP 87 +#define CLK_DE_BE 88 +#define CLK_DE_FE 89 +#define CLK_TCON_CH0 90 + +#define CLK_TCON_CH1 92 +#define CLK_CSI 93 +#define CLK_VE 94 +#define CLK_CODEC 95 +#define CLK_AVS 96 +#define CLK_HDMI 97 +#define CLK_GPU 98 + +#define CLK_IEP 100 + +#endif /* _DT_BINDINGS_CLK_SUN5I_H_ */ diff --git a/include/dt-bindings/clock/sun6i-a31-ccu.h b/include/dt-bindings/clock/sun6i-a31-ccu.h new file mode 100644 index 0000000000..c5d1334018 --- /dev/null +++ b/include/dt-bindings/clock/sun6i-a31-ccu.h @@ -0,0 +1,191 @@ +/* + * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_CLK_SUN6I_A31_H_ +#define _DT_BINDINGS_CLK_SUN6I_A31_H_ + +#define CLK_PLL_VIDEO0_2X 7 + +#define CLK_PLL_PERIPH 10 + +#define CLK_PLL_VIDEO1_2X 13 + +#define CLK_CPU 18 + +#define CLK_AHB1_MIPIDSI 23 +#define CLK_AHB1_SS 24 +#define CLK_AHB1_DMA 25 +#define CLK_AHB1_MMC0 26 +#define CLK_AHB1_MMC1 27 +#define CLK_AHB1_MMC2 28 +#define CLK_AHB1_MMC3 29 +#define CLK_AHB1_NAND1 30 +#define CLK_AHB1_NAND0 31 +#define CLK_AHB1_SDRAM 32 +#define CLK_AHB1_EMAC 33 +#define CLK_AHB1_TS 34 +#define CLK_AHB1_HSTIMER 35 +#define CLK_AHB1_SPI0 36 +#define CLK_AHB1_SPI1 37 +#define CLK_AHB1_SPI2 38 +#define CLK_AHB1_SPI3 39 +#define CLK_AHB1_OTG 40 +#define CLK_AHB1_EHCI0 41 +#define CLK_AHB1_EHCI1 42 +#define CLK_AHB1_OHCI0 43 +#define CLK_AHB1_OHCI1 44 +#define CLK_AHB1_OHCI2 45 +#define CLK_AHB1_VE 46 +#define CLK_AHB1_LCD0 47 +#define CLK_AHB1_LCD1 48 +#define CLK_AHB1_CSI 49 +#define CLK_AHB1_HDMI 50 +#define CLK_AHB1_BE0 51 +#define CLK_AHB1_BE1 52 +#define CLK_AHB1_FE0 53 +#define CLK_AHB1_FE1 54 +#define CLK_AHB1_MP 55 +#define CLK_AHB1_GPU 56 +#define CLK_AHB1_DEU0 57 +#define CLK_AHB1_DEU1 58 +#define CLK_AHB1_DRC0 59 +#define CLK_AHB1_DRC1 60 + +#define CLK_APB1_CODEC 61 +#define CLK_APB1_SPDIF 62 +#define CLK_APB1_DIGITAL_MIC 63 +#define CLK_APB1_PIO 64 +#define CLK_APB1_DAUDIO0 65 +#define CLK_APB1_DAUDIO1 66 + +#define CLK_APB2_I2C0 67 +#define CLK_APB2_I2C1 68 +#define CLK_APB2_I2C2 69 +#define CLK_APB2_I2C3 70 +#define CLK_APB2_UART0 71 +#define CLK_APB2_UART1 72 +#define CLK_APB2_UART2 73 +#define CLK_APB2_UART3 74 +#define CLK_APB2_UART4 75 +#define CLK_APB2_UART5 76 + +#define CLK_NAND0 77 +#define CLK_NAND1 78 +#define CLK_MMC0 79 +#define CLK_MMC0_SAMPLE 80 +#define CLK_MMC0_OUTPUT 81 +#define CLK_MMC1 82 +#define CLK_MMC1_SAMPLE 83 +#define CLK_MMC1_OUTPUT 84 +#define CLK_MMC2 85 +#define CLK_MMC2_SAMPLE 86 +#define CLK_MMC2_OUTPUT 87 +#define CLK_MMC3 88 +#define CLK_MMC3_SAMPLE 89 +#define CLK_MMC3_OUTPUT 90 +#define CLK_TS 91 +#define CLK_SS 92 +#define CLK_SPI0 93 +#define CLK_SPI1 94 +#define CLK_SPI2 95 +#define CLK_SPI3 96 +#define CLK_DAUDIO0 97 +#define CLK_DAUDIO1 98 +#define CLK_SPDIF 99 +#define CLK_USB_PHY0 100 +#define CLK_USB_PHY1 101 +#define CLK_USB_PHY2 102 +#define CLK_USB_OHCI0 103 +#define CLK_USB_OHCI1 104 +#define CLK_USB_OHCI2 105 + +#define CLK_DRAM_VE 110 +#define CLK_DRAM_CSI_ISP 111 +#define CLK_DRAM_TS 112 +#define CLK_DRAM_DRC0 113 +#define CLK_DRAM_DRC1 114 +#define CLK_DRAM_DEU0 115 +#define CLK_DRAM_DEU1 116 +#define CLK_DRAM_FE0 117 +#define CLK_DRAM_FE1 118 +#define CLK_DRAM_BE0 119 +#define CLK_DRAM_BE1 120 +#define CLK_DRAM_MP 121 + +#define CLK_BE0 122 +#define CLK_BE1 123 +#define CLK_FE0 124 +#define CLK_FE1 125 +#define CLK_MP 126 +#define CLK_LCD0_CH0 127 +#define CLK_LCD1_CH0 128 +#define CLK_LCD0_CH1 129 +#define CLK_LCD1_CH1 130 +#define CLK_CSI0_SCLK 131 +#define CLK_CSI0_MCLK 132 +#define CLK_CSI1_MCLK 133 +#define CLK_VE 134 +#define CLK_CODEC 135 +#define CLK_AVS 136 +#define CLK_DIGITAL_MIC 137 +#define CLK_HDMI 138 +#define CLK_HDMI_DDC 139 +#define CLK_PS 140 + +#define CLK_MIPI_DSI 143 +#define CLK_MIPI_DSI_DPHY 144 +#define CLK_MIPI_CSI_DPHY 145 +#define CLK_IEP_DRC0 146 +#define CLK_IEP_DRC1 147 +#define CLK_IEP_DEU0 148 +#define CLK_IEP_DEU1 149 +#define CLK_GPU_CORE 150 +#define CLK_GPU_MEMORY 151 +#define CLK_GPU_HYD 152 +#define CLK_ATS 153 +#define CLK_TRACE 154 + +#define CLK_OUT_A 155 +#define CLK_OUT_B 156 +#define CLK_OUT_C 157 + +#endif /* _DT_BINDINGS_CLK_SUN6I_A31_H_ */ diff --git a/include/dt-bindings/clock/sun7i-a20-ccu.h b/include/dt-bindings/clock/sun7i-a20-ccu.h new file mode 100644 index 0000000000..045a5178da --- /dev/null +++ b/include/dt-bindings/clock/sun7i-a20-ccu.h @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2017 Priit Laes <plaes@plaes.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_CLK_SUN7I_A20_H_ +#define _DT_BINDINGS_CLK_SUN7I_A20_H_ + +#include <dt-bindings/clock/sun4i-a10-ccu.h> + +#define CLK_MBUS 166 +#define CLK_HDMI1_SLOW 167 +#define CLK_HDMI1 168 +#define CLK_OUT_A 169 +#define CLK_OUT_B 170 + +#endif /* _DT_BINDINGS_CLK_SUN7I_A20_H_ */ diff --git a/include/dt-bindings/reset/sun4i-a10-ccu.h b/include/dt-bindings/reset/sun4i-a10-ccu.h new file mode 100644 index 0000000000..5f4480bedc --- /dev/null +++ b/include/dt-bindings/reset/sun4i-a10-ccu.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2017 Priit Laes <plaes@plaes.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_RST_SUN4I_A10_H +#define _DT_BINDINGS_RST_SUN4I_A10_H + +#define RST_USB_PHY0 1 +#define RST_USB_PHY1 2 +#define RST_USB_PHY2 3 +#define RST_GPS 4 +#define RST_DE_BE0 5 +#define RST_DE_BE1 6 +#define RST_DE_FE0 7 +#define RST_DE_FE1 8 +#define RST_DE_MP 9 +#define RST_TVE0 10 +#define RST_TCON0 11 +#define RST_TVE1 12 +#define RST_TCON1 13 +#define RST_CSI0 14 +#define RST_CSI1 15 +#define RST_VE 16 +#define RST_ACE 17 +#define RST_LVDS 18 +#define RST_GPU 19 +#define RST_HDMI_H 20 +#define RST_HDMI_SYS 21 +#define RST_HDMI_AUDIO_DMA 22 + +#endif /* DT_BINDINGS_RST_SUN4I_A10_H */ diff --git a/include/dt-bindings/reset/sun5i-ccu.h b/include/dt-bindings/reset/sun5i-ccu.h new file mode 100644 index 0000000000..c2b9726b50 --- /dev/null +++ b/include/dt-bindings/reset/sun5i-ccu.h @@ -0,0 +1,32 @@ +/* + * Copyright 2016 Maxime Ripard + * + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _RST_SUN5I_H_ +#define _RST_SUN5I_H_ + +#define RST_USB_PHY0 0 +#define RST_USB_PHY1 1 +#define RST_GPS 2 +#define RST_DE_BE 3 +#define RST_DE_FE 4 +#define RST_TVE 5 +#define RST_LCD 6 +#define RST_CSI 7 +#define RST_VE 8 +#define RST_GPU 9 +#define RST_IEP 10 + +#endif /* _RST_SUN5I_H_ */ diff --git a/include/dt-bindings/reset/sun6i-a31-ccu.h b/include/dt-bindings/reset/sun6i-a31-ccu.h new file mode 100644 index 0000000000..fbff365ed6 --- /dev/null +++ b/include/dt-bindings/reset/sun6i-a31-ccu.h @@ -0,0 +1,106 @@ +/* + * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_RST_SUN6I_A31_H_ +#define _DT_BINDINGS_RST_SUN6I_A31_H_ + +#define RST_USB_PHY0 0 +#define RST_USB_PHY1 1 +#define RST_USB_PHY2 2 + +#define RST_AHB1_MIPI_DSI 3 +#define RST_AHB1_SS 4 +#define RST_AHB1_DMA 5 +#define RST_AHB1_MMC0 6 +#define RST_AHB1_MMC1 7 +#define RST_AHB1_MMC2 8 +#define RST_AHB1_MMC3 9 +#define RST_AHB1_NAND1 10 +#define RST_AHB1_NAND0 11 +#define RST_AHB1_SDRAM 12 +#define RST_AHB1_EMAC 13 +#define RST_AHB1_TS 14 +#define RST_AHB1_HSTIMER 15 +#define RST_AHB1_SPI0 16 +#define RST_AHB1_SPI1 17 +#define RST_AHB1_SPI2 18 +#define RST_AHB1_SPI3 19 +#define RST_AHB1_OTG 20 +#define RST_AHB1_EHCI0 21 +#define RST_AHB1_EHCI1 22 +#define RST_AHB1_OHCI0 23 +#define RST_AHB1_OHCI1 24 +#define RST_AHB1_OHCI2 25 +#define RST_AHB1_VE 26 +#define RST_AHB1_LCD0 27 +#define RST_AHB1_LCD1 28 +#define RST_AHB1_CSI 29 +#define RST_AHB1_HDMI 30 +#define RST_AHB1_BE0 31 +#define RST_AHB1_BE1 32 +#define RST_AHB1_FE0 33 +#define RST_AHB1_FE1 34 +#define RST_AHB1_MP 35 +#define RST_AHB1_GPU 36 +#define RST_AHB1_DEU0 37 +#define RST_AHB1_DEU1 38 +#define RST_AHB1_DRC0 39 +#define RST_AHB1_DRC1 40 +#define RST_AHB1_LVDS 41 + +#define RST_APB1_CODEC 42 +#define RST_APB1_SPDIF 43 +#define RST_APB1_DIGITAL_MIC 44 +#define RST_APB1_DAUDIO0 45 +#define RST_APB1_DAUDIO1 46 +#define RST_APB2_I2C0 47 +#define RST_APB2_I2C1 48 +#define RST_APB2_I2C2 49 +#define RST_APB2_I2C3 50 +#define RST_APB2_UART0 51 +#define RST_APB2_UART1 52 +#define RST_APB2_UART2 53 +#define RST_APB2_UART3 54 +#define RST_APB2_UART4 55 +#define RST_APB2_UART5 56 + +#endif /* _DT_BINDINGS_RST_SUN6I_A31_H_ */ diff --git a/include/fs_loader.h b/include/fs_loader.h new file mode 100644 index 0000000000..0be4f17e63 --- /dev/null +++ b/include/fs_loader.h @@ -0,0 +1,79 @@ +/* + * Copyright (C) 2018 Intel Corporation <www.intel.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ +#ifndef _FS_LOADER_H_ +#define _FS_LOADER_H_ + +#include <dm.h> + +/** + * struct firmware - A place for storing firmware and its attribute data. + * + * This holds information about a firmware and its content. + * + * @size: Size of a file + * @data: Buffer for file + * @priv: Firmware loader private fields + */ +struct firmware { + size_t size; + const u8 *data; + void *priv; +}; + +/** + * struct phandle_part - A place for storing phandle of node and its partition + * + * This holds information about a phandle of the block device, and its + * partition where the firmware would be loaded from. + * + * @phandle: Phandle of storage device node + * @partition: Partition of block device + */ +struct phandle_part { + u32 phandle; + u32 partition; +}; + +/** + * struct phandle_part - A place for storing all supported storage devices + * + * This holds information about all supported storage devices for driver use. + * + * @phandlepart: Attribute data for block device. + * @mtdpart: MTD partition for ubi partition. + * @ubivol: UBI volume-name for ubifsmount. + */ +struct device_platdata { + struct phandle_part phandlepart; + char *mtdpart; + char *ubivol; +}; + +/** + * release_firmware - Release the resource associated with a firmware image + * @firmware: Firmware resource to release + */ +void release_firmware(struct firmware *firmware); + +/** + * request_firmware_into_buf - Load firmware into a previously allocated buffer. + * @plat: Platform data such as storage and partition firmware loading from. + * @name: Name of firmware file. + * @buf: Address of buffer to load firmware into. + * @size: Size of buffer. + * @offset: Offset of a file for start reading into buffer. + * @firmwarep: Pointer to firmware image. + * + * The firmware is loaded directly into the buffer pointed to by @buf and + * the @firmwarep data member is pointed at @buf. + * + * Return: Size of total read, negative value when error. + */ +int request_firmware_into_buf(struct device_platdata *plat, + const char *name, + void *buf, size_t size, u32 offset, + struct firmware **firmwarep); +#endif diff --git a/include/fsl-mc/fsl_mc.h b/include/fsl-mc/fsl_mc.h index 7f4859b004..aef40d3911 100644 --- a/include/fsl-mc/fsl_mc.h +++ b/include/fsl-mc/fsl_mc.h @@ -51,6 +51,7 @@ struct mc_ccsr_registers { u32 reg_error[]; }; +void fdt_fsl_mc_fixup_iommu_map_entry(void *blob); int get_mc_boot_status(void); int get_dpl_apply_status(void); #ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET diff --git a/include/test/ut.h b/include/test/ut.h index fce75fd12a..19bcb8c374 100644 --- a/include/test/ut.h +++ b/include/test/ut.h @@ -78,6 +78,24 @@ void ut_failf(struct unit_test_state *uts, const char *fname, int line, } \ } +/* Assert that two memory areas are equal */ +#define ut_asserteq_mem(expr1, expr2, len) { \ + const u8 *val1 = (u8 *)(expr1), *val2 = (u8 *)(expr2); \ + const uint __len = len; \ + \ + if (memcmp(val1, val2, __len)) { \ + char __buf1[64 + 1] = "\0"; \ + char __buf2[64 + 1] = "\0"; \ + bin2hex(__buf1, val1, min(__len, (uint)32)); \ + bin2hex(__buf2, val2, min(__len, (uint)32)); \ + ut_failf(uts, __FILE__, __LINE__, __func__, \ + #expr1 " = " #expr2, \ + "Expected \"%s\", got \"%s\"", \ + __buf1, __buf2); \ + return CMD_RET_FAILURE; \ + } \ +} + /* Assert that two pointers are equal */ #define ut_asserteq_ptr(expr1, expr2) { \ const void *val1 = (expr1), *val2 = (expr2); \ diff --git a/include/ubi_uboot.h b/include/ubi_uboot.h index 80acbcb148..0770228cd8 100644 --- a/include/ubi_uboot.h +++ b/include/ubi_uboot.h @@ -75,5 +75,7 @@ extern int ubi_volume_write(char *volume, void *buf, size_t size); extern int ubi_volume_read(char *volume, char *buf, size_t size); extern struct ubi_device *ubi_devices[]; +int cmd_ubifs_mount(char *vol_name); +int cmd_ubifs_umount(void); #endif diff --git a/include/video.h b/include/video.h index ddc2eeb5a9..e7fc5c94e2 100644 --- a/include/video.h +++ b/include/video.h @@ -198,12 +198,6 @@ void video_set_default_colors(struct video_priv *priv); /* Video functions */ -struct stdio_dev; - -int video_init(void *videobase); -void video_putc(struct stdio_dev *dev, const char c); -void video_puts(struct stdio_dev *dev, const char *s); - /** * Display a BMP format bitmap on the screen * diff --git a/include/video_console.h b/include/video_console.h index 63af741778..52a41ac200 100644 --- a/include/video_console.h +++ b/include/video_console.h @@ -43,20 +43,22 @@ enum color_idx { * Drivers must set up @rows, @cols, @x_charsize, @y_charsize in their probe() * method. Drivers may set up @xstart_frac if desired. * - * @sdev: stdio device, acting as an output sink - * @xcur_frac: Current X position, in fractional units (VID_TO_POS(x)) - * @curr_row: Current Y position in pixels (0=top) - * @rows: Number of text rows - * @cols: Number of text columns - * @x_charsize: Character width in pixels - * @y_charsize: Character height in pixels + * @sdev: stdio device, acting as an output sink + * @xcur_frac: Current X position, in fractional units (VID_TO_POS(x)) + * @ycur: Current Y position in pixels (0=top) + * @rows: Number of text rows + * @cols: Number of text columns + * @x_charsize: Character width in pixels + * @y_charsize: Character height in pixels * @tab_width_frac: Tab width in fractional units - * @xsize_frac: Width of the display in fractional units + * @xsize_frac: Width of the display in fractional units * @xstart_frac: Left margin for the text console in fractional units - * @last_ch: Last character written to the text console on this line - * @escape: TRUE if currently accumulating an ANSI escape sequence - * @escape_len: Length of accumulated escape sequence so far - * @escape_buf: Buffer to accumulate escape sequence + * @last_ch: Last character written to the text console on this line + * @escape: TRUE if currently accumulating an ANSI escape sequence + * @escape_len: Length of accumulated escape sequence so far + * @col_saved: Saved X position, in fractional units (VID_TO_POS(x)) + * @row_saved: Saved Y position in pixels (0=top) + * @escape_buf: Buffer to accumulate escape sequence */ struct vidconsole_priv { struct stdio_dev sdev; @@ -77,6 +79,8 @@ struct vidconsole_priv { */ int escape; int escape_len; + int row_saved; + int col_saved; char escape_buf[32]; }; diff --git a/include/video_osd.h b/include/video_osd.h new file mode 100644 index 0000000000..01ac94b425 --- /dev/null +++ b/include/video_osd.h @@ -0,0 +1,192 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2017 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + */ + +#ifndef _VIDEO_OSD_H_ +#define _VIDEO_OSD_H_ + +struct video_osd_info { + /* The width of the OSD display in columns */ + uint width; + /* The height of the OSD display in rows */ + uint height; + /* The major version of the OSD device */ + uint major_version; + /* The minor version of the OSD device */ + uint minor_version; +}; + +/** + * struct video_osd_ops - driver operations for OSD uclass + * + * The OSD uclass implements support for text-oriented on-screen displays, + * which are taken to be devices that independently display a graphical + * text-based overlay over the video output of an associated display. + * + * The functions defined by the uclass support writing text to the display in + * either a generic form (by specifying a string, a driver-specific color value + * for the text, and screen coordinates in rows and columns) or a + * driver-specific form (by specifying "raw" driver-specific data to display at + * a given coordinate). + * + * Functions to read device information and set the size of the virtual OSD + * screen (in rows and columns) are also supported. + * + * Drivers should support these operations unless otherwise noted. These + * operations are intended to be used by uclass code, not directly from + * other code. + */ +struct video_osd_ops { + /** + * get_info() - Get information about a OSD instance + * + * A OSD instance may keep some internal data about itself. This + * function can be used to access this data. + * + * @dev: OSD instance to query. + * @info: Pointer to a structure that takes the information read + * from the OSD instance. + * @return 0 if OK, -ve on error. + */ + int (*get_info)(struct udevice *dev, struct video_osd_info *info); + + /** + * set_mem() - Write driver-specific text data to OSD screen + * + * The passed data are device-specific, and it's up to the driver how + * to interpret them. How the count parameter is interpreted is also + * driver-specific; most likely the given data will be written to the + * OSD count times back-to-back, which is e.g. convenient for filling + * areas of the OSD with a single character. + * + * For example a invocation of + * + * video_osd_set_mem(dev, 0, 0, "A", 1, 10); + * + * will write the device-specific text data "A" to the positions (0, 0) + * to (9, 0) on the OSD. + * + * Device-specific text data may, e.g. be a special encoding of glyphs + * to display and color values in binary format. + * + * @dev: OSD instance to write to. + * @col: Horizontal character coordinate to write to. + * @row Vertical character coordinate to write to. + * @buf: Array containing device-specific data to write to the + * specified coordinate on the OSD screen. + * @buflen: Length of the data in the passed buffer (in byte). + * @count: Write count many repetitions of the given text data + * @return 0 if OK, -ve on error. + */ + int (*set_mem)(struct udevice *dev, uint col, uint row, u8 *buf, + size_t buflen, uint count); + + /** + * set_size() - Set the position and dimension of the OSD's + * writeable window + * + * @dev: OSD instance to write to. + * @col The number of characters in the window's columns + * @row The number of characters in the window's rows + * @return 0 if OK, -ve on error. + */ + int (*set_size)(struct udevice *dev, uint col, uint row); + + /** + * print() - Print a string in a given color to specified coordinates + * on the OSD + * + * @dev: OSD instance to write to. + * @col The x-coordinate of the position the string should be + * written to + * @row The y-coordinate of the position the string should be + * written to + * @color: The color in which the specified string should be + * printed; the interpretation of the value is + * driver-specific, and possible values should be defined + * e.g. in a driver include file. + * @text: The string data that should be printed on the OSD + * @return 0 if OK, -ve on error. + */ + int (*print)(struct udevice *dev, uint col, uint row, ulong color, + char *text); +}; + +#define video_osd_get_ops(dev) ((struct video_osd_ops *)(dev)->driver->ops) + +/** + * video_osd_get_info() - Get information about a OSD instance + * + * A OSD instance may keep some internal data about itself. This function can + * be used to access this data. + * + * @dev: OSD instance to query. + * @info: Pointer to a structure that takes the information read from the + * OSD instance. + * @return 0 if OK, -ve on error. + */ +int video_osd_get_info(struct udevice *dev, struct video_osd_info *info); + +/** + * video_osd_set_mem() - Write text data to OSD memory + * + * The passed data are device-specific, and it's up to the driver how to + * interpret them. How the count parameter is interpreted is also + * driver-specific; most likely the given data will be written to the OSD count + * times back-to-back, which is e.g. convenient for filling areas of the OSD + * with a single character. + * + * For example a invocation of + * + * video_osd_set_mem(dev, 0, 0, "A", 1, 10); + * + * will write the device-specific text data "A" to the positions (0, 0) to (9, + * 0) on the OSD. + * + * Device-specific text data may, e.g. be a special encoding of glyphs to + * display and color values in binary format. + * + * @dev: OSD instance to write to. + * @col: Horizontal character coordinate to write to. + * @row Vertical character coordinate to write to. + * @buf: Array containing device-specific data to write to the specified + * coordinate on the OSD screen. + * @buflen: Length of the data in the passed buffer (in byte). + * @count: Write count many repetitions of the given text data + * @return 0 if OK, -ve on error. + */ +int video_osd_set_mem(struct udevice *dev, uint col, uint row, u8 *buf, + size_t buflen, uint count); + +/** + * video_osd_set_size() - Set the position and dimension of the OSD's + * writeable window + * + * @dev: OSD instance to write to. + * @col The number of characters in the window's columns + * @row The number of characters in the window's rows + * @return 0 if OK, -ve on error. + */ +int video_osd_set_size(struct udevice *dev, uint col, uint row); + +/** + * video_osd_print() - Print a string in a given color to specified coordinates + * on the OSD + * + * @dev: OSD instance to write to. + * @col The x-coordinate of the position the string should be written + * to + * @row The y-coordinate of the position the string should be written + * to + * @color: The color in which the specified string should be printed; the + * interpretation of the value is driver-specific, and possible + * values should be defined e.g. in a driver include file. + * @text: The string data that should be printed on the OSD + * @return 0 if OK, -ve on error. + */ +int video_osd_print(struct udevice *dev, uint col, uint row, ulong color, + char *text); + +#endif /* !_VIDEO_OSD_H_ */ diff --git a/include/w1-eeprom.h b/include/w1-eeprom.h new file mode 100644 index 0000000000..22337368b4 --- /dev/null +++ b/include/w1-eeprom.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (c) 2015 Free Electrons + * Copyright (c) 2015 NextThing Co + * Copyright (c) 2018 Microchip Technology, Inc. + * + */ + +#ifndef __W1_EEPROM_H +#define __W1_EEPROM_H + +struct udevice; + +struct w1_eeprom_ops { + /* + * Reads a buff from the given EEPROM memory, starting at + * given offset and place the results into the given buffer. + * Should read given count of bytes. + * Should return 0 on success, and normal error.h on error + */ + int (*read_buf)(struct udevice *dev, unsigned int offset, + u8 *buf, unsigned int count); +}; + +int w1_eeprom_read_buf(struct udevice *dev, unsigned int offset, + u8 *buf, unsigned int count); + +int w1_eeprom_dm_init(void); + +int w1_eeprom_register_new_device(u64 id); + +int w1_eeprom_get_id(struct udevice *dev, u64 *id); +#endif diff --git a/include/w1.h b/include/w1.h new file mode 100644 index 0000000000..399177a12e --- /dev/null +++ b/include/w1.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (c) 2015 Free Electrons + * Copyright (c) 2015 NextThing Co + * + */ + +#ifndef __W1_H +#define __W1_H + +#include <dm.h> + +#define W1_FAMILY_DS24B33 0x23 +#define W1_FAMILY_DS2431 0x2d +#define W1_FAMILY_EEP_SANDBOX 0xfe + +struct w1_device { + u64 id; +}; + +struct w1_ops { + u8 (*read_byte)(struct udevice *dev); + bool (*reset)(struct udevice *dev); + u8 (*triplet)(struct udevice *dev, bool bdir); + void (*write_byte)(struct udevice *dev, u8 byte); +}; + +int w1_get_bus(int busnum, struct udevice **busp); +u8 w1_get_device_family(struct udevice *dev); + +int w1_read_buf(struct udevice *dev, u8 *buf, unsigned int count); +int w1_read_byte(struct udevice *dev); +int w1_reset_select(struct udevice *dev); +int w1_write_buf(struct udevice *dev, u8 *buf, unsigned int count); +int w1_write_byte(struct udevice *dev, u8 byte); + +#endif diff --git a/scripts/Kbuild.include b/scripts/Kbuild.include index 2c7918ad37..13ebddda65 100644 --- a/scripts/Kbuild.include +++ b/scripts/Kbuild.include @@ -7,6 +7,7 @@ quote := " squote := ' empty := space := $(empty) $(empty) +pound := \# ### # Name of target with a '.' as filename prefix. foo/bar.o => foo/.bar.o @@ -242,11 +243,11 @@ endif # Replace >$< with >$$< to preserve $ when reloading the .cmd file # (needed for make) -# Replace >#< with >\#< to avoid starting a comment in the .cmd file +# Replace >#< with >$(pound)< to avoid starting a comment in the .cmd file # (needed for make) # Replace >'< with >'\''< to be able to enclose the whole string in '...' # (needed for the shell) -make-cmd = $(call escsq,$(subst \#,\\\#,$(subst $$,$$$$,$(cmd_$(1))))) +make-cmd = $(call escsq,$(subst $(pound),$$(pound),$(subst $$,$$$$,$(cmd_$(1))))) # Find any prerequisites that is newer than target or that does not exist. # PHONY targets skipped in both cases. diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index f8c3fff1d1..4dceb6d1b3 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -299,7 +299,7 @@ quiet_cmd_dtc = DTC $@ # Modified for U-Boot # Bring in any U-Boot-specific include at the end of the file cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \ - (cat $<; $(if $(u_boot_dtsi),echo '\#include "$(u_boot_dtsi)"')) > $(pre-tmp); \ + (cat $<; $(if $(u_boot_dtsi),echo '$(pound)include "$(u_boot_dtsi)"')) > $(pre-tmp); \ $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $(pre-tmp) ; \ $(DTC) -O dtb -o $@ -b 0 \ -i $(dir $<) $(DTC_FLAGS) \ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 03e4d28b76..96d3f75750 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -366,7 +366,6 @@ CONFIG_DHCP_MIN_EXT_LEN CONFIG_DIALOG_POWER CONFIG_DIMM_SLOTS_PER_CTLR CONFIG_DIRECT_NOR_BOOT -CONFIG_DISABLE_CONSOLE CONFIG_DISCONTIGMEM CONFIG_DISCOVER_PHY CONFIG_DISPLAY_AER_xxxx @@ -4631,7 +4630,6 @@ CONFIG_USE_SPIFLASH CONFIG_UTBIPAR_INIT_TBIPA CONFIG_U_BOOT_HDR_ADDR CONFIG_U_BOOT_HDR_SIZE -CONFIG_U_QE CONFIG_VAL CONFIG_VAR_SIZE_SPL CONFIG_VCT_NOR diff --git a/test/Makefile b/test/Makefile index a5f52fd5ad..1e434730b6 100644 --- a/test/Makefile +++ b/test/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_SANDBOX) += print_ut.o obj-$(CONFIG_UT_TIME) += time_ut.o obj-$(CONFIG_UT_UNICODE) += unicode_ut.o obj-$(CONFIG_$(SPL_)LOG) += log/ +obj-$(CONFIG_UNIT_TEST) += lib/ diff --git a/test/dm/Makefile b/test/dm/Makefile index 00acc7f242..264f12633f 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_LED) += led.o obj-$(CONFIG_DM_MAILBOX) += mailbox.o obj-$(CONFIG_DM_MMC) += mmc.o obj-y += ofnode.o +obj-$(CONFIG_OSD) += osd.o obj-$(CONFIG_DM_PCI) += pci.o obj-$(CONFIG_PHY) += phy.o obj-$(CONFIG_POWER_DOMAIN) += power-domain.o diff --git a/test/dm/osd.c b/test/dm/osd.c new file mode 100644 index 0000000000..6910690b3a --- /dev/null +++ b/test/dm/osd.c @@ -0,0 +1,210 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2018 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + */ + +#include <common.h> +#include <display_options.h> +#include <dm.h> +#include <dm/test.h> +#include <test/ut.h> +#include <video_osd.h> +#include <asm/test.h> + +#include "../../drivers/video/sandbox_osd.h" + +const uint memsize = 2 * 10 * 10; + +static void split(u8 *mem, uint size, u8 *text, u8 *colors) +{ + int i; + u16 *p = (u16 *)mem; + + for (i = 0; i < size; i++) { + colors[i] = p[i] % 0x100; + text[i] = p[i] / 0x100; + } +} + +static void print_mem(u8 *mem, uint width, uint height) +{ + const uint memsize = 2 * 10 * 10; + u8 colors[memsize / 2]; + u8 text[memsize / 2]; + int i; + + split(mem, memsize / 2, text, colors); + + for (i = 0; i < width * height; i++) { + printf("%c", text[i]); + if (i > 0 && ((i + 1) % width) == 0) + printf("\n"); + } + + printf("\n"); + + for (i = 0; i < width * height; i++) { + printf("%c", colors[i]); + if (i > 0 && ((i + 1) % width) == 0) + printf("\n"); + } +} + +static int dm_test_osd_basics(struct unit_test_state *uts) +{ + struct udevice *dev; + u8 mem[memsize + 1]; + u8 colors[memsize / 2]; + u8 text[memsize / 2]; + struct video_osd_info info; + + ut_assertok(uclass_first_device_err(UCLASS_VIDEO_OSD, &dev)); + + video_osd_get_info(dev, &info); + + ut_asserteq(10, info.width); + ut_asserteq(10, info.height); + ut_asserteq(1, info.major_version); + ut_asserteq(0, info.minor_version); + + ut_assertok(sandbox_osd_get_mem(dev, mem, memsize)); + split(mem, memsize / 2, text, colors); + + ut_assertok(memcmp(text, " " + " " + " " + " " + " " + " " + " " + " " + " " + " ", memsize / 2)); + + ut_assertok(memcmp(colors, "kkkkkkkkkk" + "kkkkkkkkkk" + "kkkkkkkkkk" + "kkkkkkkkkk" + "kkkkkkkkkk" + "kkkkkkkkkk" + "kkkkkkkkkk" + "kkkkkkkkkk" + "kkkkkkkkkk" + "kkkkkkkkkk", memsize / 2)); + + print_mem(mem, 10, 10); + + ut_assertok(video_osd_print(dev, 1, 1, COLOR_RED, "Blah")); + + ut_assertok(sandbox_osd_get_mem(dev, mem, memsize)); + split(mem, memsize / 2, text, colors); + + ut_assertok(memcmp(text, " " + " Blah " + " " + " " + " " + " " + " " + " " + " " + " ", memsize / 2)); + + ut_assertok(memcmp(colors, "kkkkkkkkkk" + "krrrrkkkkk" + "kkkkkkkkkk" + "kkkkkkkkkk" + "kkkkkkkkkk" + "kkkkkkkkkk" + "kkkkkkkkkk" + "kkkkkkkkkk" + "kkkkkkkkkk" + "kkkkkkkkkk", memsize / 2)); + + print_mem(mem, 10, 10); + + return 0; +} + +DM_TEST(dm_test_osd_basics, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +static int dm_test_osd_extended(struct unit_test_state *uts) +{ + struct udevice *dev; + u8 mem[memsize + 1]; + u8 colors[memsize / 2]; + u8 text[memsize / 2]; + struct video_osd_info info; + u16 val; + + ut_assertok(uclass_first_device_err(UCLASS_VIDEO_OSD, &dev)); + + ut_assertok(video_osd_set_size(dev, 20, 5)); + + video_osd_get_info(dev, &info); + + ut_asserteq(20, info.width); + ut_asserteq(5, info.height); + ut_asserteq(1, info.major_version); + ut_asserteq(0, info.minor_version); + + ut_assertok(sandbox_osd_get_mem(dev, mem, memsize)); + split(mem, memsize / 2, text, colors); + + ut_assertok(memcmp(text, " " + " " + " " + " " + " ", memsize / 2)); + + ut_assertok(memcmp(colors, "kkkkkkkkkkkkkkkkkkkk" + "kkkkkkkkkkkkkkkkkkkk" + "kkkkkkkkkkkkkkkkkkkk" + "kkkkkkkkkkkkkkkkkkkk" + "kkkkkkkkkkkkkkkkkkkk", memsize / 2)); + + print_mem(mem, 20, 5); + + /* Draw green border */ + val = '-' * 0x100 + 'g'; + ut_assertok(video_osd_set_mem(dev, 1, 0, (u8 *)&val, 2, 18)); + ut_assertok(video_osd_set_mem(dev, 1, 4, (u8 *)&val, 2, 18)); + ut_assertok(video_osd_print(dev, 0, 1, COLOR_GREEN, "|")); + ut_assertok(video_osd_print(dev, 0, 2, COLOR_GREEN, "|")); + ut_assertok(video_osd_print(dev, 0, 3, COLOR_GREEN, "|")); + ut_assertok(video_osd_print(dev, 19, 1, COLOR_GREEN, "|")); + ut_assertok(video_osd_print(dev, 19, 2, COLOR_GREEN, "|")); + ut_assertok(video_osd_print(dev, 19, 3, COLOR_GREEN, "|")); + ut_assertok(video_osd_print(dev, 0, 0, COLOR_GREEN, "+")); + ut_assertok(video_osd_print(dev, 19, 0, COLOR_GREEN, "+")); + ut_assertok(video_osd_print(dev, 19, 4, COLOR_GREEN, "+")); + ut_assertok(video_osd_print(dev, 0, 4, COLOR_GREEN, "+")); + + /* Add menu caption and entries */ + ut_assertok(video_osd_print(dev, 5, 0, COLOR_GREEN, " OSD menu ")); + ut_assertok(video_osd_print(dev, 2, 1, COLOR_BLUE, " * Entry 1")); + ut_assertok(video_osd_print(dev, 2, 2, COLOR_BLUE, "(*) Entry 2")); + ut_assertok(video_osd_print(dev, 2, 3, COLOR_BLUE, " * Entry 3")); + + ut_assertok(sandbox_osd_get_mem(dev, mem, memsize)); + split(mem, memsize / 2, text, colors); + + print_mem(mem, 20, 5); + + ut_assertok(memcmp(text, "+---- OSD menu ----+" + "| * Entry 1 |" + "| (*) Entry 2 |" + "| * Entry 3 |" + "+------------------+", memsize / 2)); + + ut_assertok(memcmp(colors, "gggggggggggggggggggg" + "gkbbbbbbbbbbbkkkkkkg" + "gkbbbbbbbbbbbkkkkkkg" + "gkbbbbbbbbbbbkkkkkkg" + "gggggggggggggggggggg", memsize / 2)); + + return 0; +} + +DM_TEST(dm_test_osd_extended, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); diff --git a/test/lib/Makefile b/test/lib/Makefile new file mode 100644 index 0000000000..ea68fae566 --- /dev/null +++ b/test/lib/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2018 +# Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc +obj-y += hexdump.o diff --git a/test/lib/hexdump.c b/test/lib/hexdump.c new file mode 100644 index 0000000000..e8b3e566e0 --- /dev/null +++ b/test/lib/hexdump.c @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2018 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + */ + +#include <common.h> +#include <hexdump.h> +#include <dm/test.h> +#include <test/ut.h> + +static int lib_test_hex_to_bin(struct unit_test_state *uts) +{ + return 0; + + ut_asserteq(0x0, hex_to_bin('0')); + ut_asserteq(0x1, hex_to_bin('1')); + ut_asserteq(0x2, hex_to_bin('2')); + ut_asserteq(0x3, hex_to_bin('3')); + ut_asserteq(0x4, hex_to_bin('4')); + ut_asserteq(0x5, hex_to_bin('5')); + ut_asserteq(0x6, hex_to_bin('6')); + ut_asserteq(0x7, hex_to_bin('7')); + ut_asserteq(0x8, hex_to_bin('8')); + ut_asserteq(0x9, hex_to_bin('9')); + ut_asserteq(0xa, hex_to_bin('a')); + ut_asserteq(0xb, hex_to_bin('b')); + ut_asserteq(0xc, hex_to_bin('c')); + ut_asserteq(0xd, hex_to_bin('d')); + ut_asserteq(0xe, hex_to_bin('e')); + ut_asserteq(0xf, hex_to_bin('f')); + ut_asserteq(-1, hex_to_bin('g')); +} + +DM_TEST(lib_test_hex_to_bin, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +static int lib_test_hex2bin(struct unit_test_state *uts) +{ + u8 dst[4]; + + hex2bin(dst, "649421de", 4); + ut_asserteq_mem("\x64\x94\x21\xde", dst, 4); + hex2bin(dst, "aa2e7545", 4); + ut_asserteq_mem("\xaa\x2e\x75\x45", dst, 4); + hex2bin(dst, "75453bc5", 4); + ut_asserteq_mem("\x75\x45\x3b\xc5", dst, 4); + hex2bin(dst, "a16884c3", 4); + ut_asserteq_mem("\xa1\x68\x84\xc3", dst, 4); + hex2bin(dst, "156b2e5e", 4); + ut_asserteq_mem("\x15\x6b\x2e\x5e", dst, 4); + hex2bin(dst, "2e035fff", 4); + ut_asserteq_mem("\x2e\x03\x5f\xff", dst, 4); + hex2bin(dst, "0ffce99f", 4); + ut_asserteq_mem("\x0f\xfc\xe9\x9f", dst, 4); + hex2bin(dst, "d3999443", 4); + ut_asserteq_mem("\xd3\x99\x94\x43", dst, 4); + hex2bin(dst, "91dd87bc", 4); + ut_asserteq_mem("\x91\xdd\x87\xbc", dst, 4); + hex2bin(dst, "7fec8963", 4); + ut_asserteq_mem("\x7f\xec\x89\x63", dst, 4); + + return 0; +} + +DM_TEST(lib_test_hex2bin, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +static int lib_test_bin2hex(struct unit_test_state *uts) +{ + char dst[8 + 1] = "\0"; + + bin2hex(dst, "\x64\x94\x21\xde", 4); + ut_asserteq_str("649421de", dst); + bin2hex(dst, "\xaa\x2e\x75\x45", 4); + ut_asserteq_str("aa2e7545", dst); + bin2hex(dst, "\x75\x45\x3b\xc5", 4); + ut_asserteq_str("75453bc5", dst); + bin2hex(dst, "\xa1\x68\x84\xc3", 4); + ut_asserteq_str("a16884c3", dst); + bin2hex(dst, "\x15\x6b\x2e\x5e", 4); + ut_asserteq_str("156b2e5e", dst); + bin2hex(dst, "\x2e\x03\x5f\xff", 4); + ut_asserteq_str("2e035fff", dst); + bin2hex(dst, "\x0f\xfc\xe9\x9f", 4); + ut_asserteq_str("0ffce99f", dst); + bin2hex(dst, "\xd3\x99\x94\x43", 4); + ut_asserteq_str("d3999443", dst); + bin2hex(dst, "\x91\xdd\x87\xbc", 4); + ut_asserteq_str("91dd87bc", dst); + bin2hex(dst, "\x7f\xec\x89\x63", 4); + ut_asserteq_str("7fec8963", dst); + + return 0; +} + +DM_TEST(lib_test_bin2hex, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); diff --git a/tools/binman/README b/tools/binman/README index 088f3a63d9..b64dedf2eb 100644 --- a/tools/binman/README +++ b/tools/binman/README @@ -401,6 +401,15 @@ end-at-4gb: 8MB ROM, the offset of the first entry would be 0xfff80000 with this option, instead of 0 without this option. +skip-at-start: + This property specifies the entry offset of the first entry. + + For PowerPC mpc85xx based CPU, CONFIG_SYS_TEXT_BASE is the entry + offset of the first entry. It can be 0xeff40000 or 0xfff40000 for + nor flash boot, 0x201000 for sd boot etc. + + 'end-at-4gb' property is not applicable where CONFIG_SYS_TEXT_BASE + + Image size != 4gb. Examples of the above options can be found in the tests. See the tools/binman/test directory. diff --git a/tools/binman/README.entries b/tools/binman/README.entries index 69b435f96e..9fc2f83280 100644 --- a/tools/binman/README.entries +++ b/tools/binman/README.entries @@ -252,6 +252,18 @@ See README.x86 for information about Intel binary blobs. +Entry: powerpc-mpc85xx-bootpg-resetvec: PowerPC mpc85xx bootpg + resetvec code for U-Boot +----------------------------------------------------------------------------------------- + +Properties / Entry arguments: + - filename: Filename of u-boot-br.bin (default 'u-boot-br.bin') + +This enrty is valid for PowerPC mpc85xx cpus. This entry holds +'bootpg + resetvec' code for PowerPC mpc85xx CPUs which needs to be +placed at offset 'RESET_VECTOR_ADDRESS - 0xffc'. + + + Entry: section: Entry that contains other entries ------------------------------------------------- diff --git a/tools/binman/bsection.py b/tools/binman/bsection.py index c208029c25..ccf2920c5b 100644 --- a/tools/binman/bsection.py +++ b/tools/binman/bsection.py @@ -64,7 +64,7 @@ class Section(object): self._pad_after = 0 self._pad_byte = 0 self._sort = False - self._skip_at_start = 0 + self._skip_at_start = None self._end_4gb = False self._name_prefix = '' self._entries = OrderedDict() @@ -85,10 +85,17 @@ class Section(object): self._pad_byte = fdt_util.GetInt(self._node, 'pad-byte', 0) self._sort = fdt_util.GetBool(self._node, 'sort-by-offset') self._end_4gb = fdt_util.GetBool(self._node, 'end-at-4gb') - if self._end_4gb and not self._size: - self._Raise("Section size must be provided when using end-at-4gb") + self._skip_at_start = fdt_util.GetInt(self._node, 'skip-at-start') if self._end_4gb: - self._skip_at_start = 0x100000000 - self._size + if not self._size: + self._Raise("Section size must be provided when using end-at-4gb") + if self._skip_at_start is not None: + self._Raise("Provide either 'end-at-4gb' or 'skip-at-start'") + else: + self._skip_at_start = 0x100000000 - self._size + else: + if self._skip_at_start is None: + self._skip_at_start = 0 self._name_prefix = fdt_util.GetString(self._node, 'name-prefix') def _ReadEntries(self): diff --git a/tools/binman/etype/powerpc_mpc85xx_bootpg_resetvec.py b/tools/binman/etype/powerpc_mpc85xx_bootpg_resetvec.py new file mode 100644 index 0000000000..59fedd2b54 --- /dev/null +++ b/tools/binman/etype/powerpc_mpc85xx_bootpg_resetvec.py @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright 2018 NXP +# +# Entry-type module for the PowerPC mpc85xx bootpg and resetvec code for U-Boot +# + +from entry import Entry +from blob import Entry_blob + +class Entry_powerpc_mpc85xx_bootpg_resetvec(Entry_blob): + """PowerPC mpc85xx bootpg + resetvec code for U-Boot + + Properties / Entry arguments: + - filename: Filename of u-boot-br.bin (default 'u-boot-br.bin') + + This enrty is valid for PowerPC mpc85xx cpus. This entry holds + 'bootpg + resetvec' code for PowerPC mpc85xx CPUs which needs to be + placed at offset 'RESET_VECTOR_ADDRESS - 0xffc'. + """ + + def __init__(self, section, etype, node): + Entry_blob.__init__(self, section, etype, node) + + def GetDefaultFilename(self): + return 'u-boot-br.bin' diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py index abf02b62e8..57725c928e 100644 --- a/tools/binman/ftest.py +++ b/tools/binman/ftest.py @@ -42,6 +42,7 @@ U_BOOT_TPL_DTB_DATA = 'tpldtb' X86_START16_DATA = 'start16' X86_START16_SPL_DATA = 'start16spl' X86_START16_TPL_DATA = 'start16tpl' +PPC_MPC85XX_BR_DATA = 'ppcmpc85xxbr' U_BOOT_NODTB_DATA = 'nodtb with microcode pointer somewhere in here' U_BOOT_SPL_NODTB_DATA = 'splnodtb with microcode pointer somewhere in here' U_BOOT_TPL_NODTB_DATA = 'tplnodtb with microcode pointer somewhere in here' @@ -97,6 +98,7 @@ class TestFunctional(unittest.TestCase): TestFunctional._MakeInputFile('vga.bin', VGA_DATA) self._ResetDtbs() TestFunctional._MakeInputFile('u-boot-x86-16bit.bin', X86_START16_DATA) + TestFunctional._MakeInputFile('u-boot-br.bin', PPC_MPC85XX_BR_DATA) TestFunctional._MakeInputFile('spl/u-boot-x86-16bit-spl.bin', X86_START16_SPL_DATA) TestFunctional._MakeInputFile('tpl/u-boot-x86-16bit-tpl.bin', @@ -763,6 +765,14 @@ class TestFunctional(unittest.TestCase): self.assertIn("Section '/binman': Section size must be provided when " "using end-at-4gb", str(e.exception)) + def test4gbAndSkipAtStartTogether(self): + """Test that the end-at-4gb and skip-at-size property can't be used + together""" + with self.assertRaises(ValueError) as e: + self._DoTestFile('80_4gb_and_skip_at_start_together.dts') + self.assertIn("Section '/binman': Provide either 'end-at-4gb' or " + "'skip-at-start'", str(e.exception)) + def testPackX86RomOutside(self): """Test that the end-at-4gb property checks for offset boundaries""" with self.assertRaises(ValueError) as e: @@ -808,6 +818,12 @@ class TestFunctional(unittest.TestCase): data = self._DoReadFile('33_x86-start16.dts') self.assertEqual(X86_START16_DATA, data[:len(X86_START16_DATA)]) + def testPackPowerpcMpc85xxBootpgResetvec(self): + """Test that an image with powerpc-mpc85xx-bootpg-resetvec can be + created""" + data = self._DoReadFile('81_powerpc_mpc85xx_bootpg_resetvec.dts') + self.assertEqual(PPC_MPC85XX_BR_DATA, data[:len(PPC_MPC85XX_BR_DATA)]) + def _RunMicrocodeTest(self, dts_fname, nodtb_data, ucode_second=False): """Handle running a test for insertion of microcode diff --git a/tools/binman/test/80_4gb_and_skip_at_start_together.dts b/tools/binman/test/80_4gb_and_skip_at_start_together.dts new file mode 100644 index 0000000000..90c467d910 --- /dev/null +++ b/tools/binman/test/80_4gb_and_skip_at_start_together.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + size = <32>; + sort-by-offset; + end-at-4gb; + skip-at-start = <0xffffffe0>; + u-boot { + offset = <0xffffffe0>; + }; + }; +}; diff --git a/tools/binman/test/81_powerpc_mpc85xx_bootpg_resetvec.dts b/tools/binman/test/81_powerpc_mpc85xx_bootpg_resetvec.dts new file mode 100644 index 0000000000..8f4b16c399 --- /dev/null +++ b/tools/binman/test/81_powerpc_mpc85xx_bootpg_resetvec.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + powerpc-mpc85xx-bootpg-resetvec { + }; + }; +}; |