diff options
974 files changed, 9033 insertions, 5576 deletions
@@ -31,8 +31,8 @@ Markus Klotzbuecher <mk@denx.de> Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com> Prabhakar Kushwaha <prabhakar@freescale.com> Rajeshwari Shinde <rajeshwari.s@samsung.com> -Ricardo Ribalda <ricardo.ribalda@uam.es> -Ricardo Ribalda <ricardo.ribalda@gmail.com> +Ricardo Ribalda <ricardo@ribalda.com> <ricardo.ribalda@uam.es> +Ricardo Ribalda <ricardo@ribalda.com> <ricardo.ribalda@gmail.com> Sandeep Paulraj <s-paulraj@ti.com> Shaohui Xie <Shaohui.Xie@freescale.com> Stefan Roese <stroese> @@ -156,14 +156,15 @@ config SYS_MALLOC_F_LEN config SYS_MALLOC_LEN hex "Define memory for Dynamic allocation" - depends on ARCH_ZYNQ || ARCH_VERSAL || ARCH_STM32MP + depends on ARCH_ZYNQ || ARCH_VERSAL || ARCH_STM32MP || ARCH_ROCKCHIP + default 0x2000000 if ARCH_ROCKCHIP help This defines memory to be allocated for Dynamic allocation TODO: Use for other architectures config SPL_SYS_MALLOC_F_LEN hex "Size of malloc() pool in SPL before relocation" - depends on SYS_MALLOC_F + depends on SYS_MALLOC_F && SPL default 0x2800 if RCAR_GEN3 default SYS_MALLOC_F_LEN help @@ -174,7 +175,7 @@ config SPL_SYS_MALLOC_F_LEN config TPL_SYS_MALLOC_F_LEN hex "Size of malloc() pool in TPL before relocation" - depends on SYS_MALLOC_F + depends on SYS_MALLOC_F && TPL default SYS_MALLOC_F_LEN help Before relocation, memory is very limited on many platforms. Still, @@ -238,6 +239,7 @@ config SPL_IMAGE string "SPL image used in the combined SPL+U-Boot image" default "spl/boot.bin" if ARCH_AT91 && SPL_NAND_SUPPORT default "spl/u-boot-spl.bin" + depends on SPL help Select the SPL build target that shall be generated by the SPL build process (default spl/u-boot-spl.bin). This image will be @@ -250,7 +252,8 @@ config BUILD_TARGET default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_GEN5 default "u-boot-spl.kwb" if ARCH_MVEBU && SPL default "u-boot-elf.srec" if RCAR_GEN3 - default "u-boot.itb" if SPL_LOAD_FIT && (ROCKCHIP_RK3399 || ARCH_SUNXI) + default "u-boot.itb" if SPL_LOAD_FIT && (ROCKCHIP_RK3399 || \ + ARCH_SUNXI || RISCV) default "u-boot.kwb" if KIRKWOOD default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT help @@ -463,6 +466,7 @@ config SPL_FIT_GENERATOR depends on SPL_FIT default "board/sunxi/mksunxi_fit_atf.sh" if SPL_LOAD_FIT && ARCH_SUNXI default "arch/arm/mach-rockchip/make_fit_atf.py" if SPL_LOAD_FIT && ARCH_ROCKCHIP + default "arch/riscv/lib/mkimage_fit_opensbi.sh" if SPL_LOAD_FIT && RISCV help Specifies a (platform specific) script file to generate the FIT source file used to build the U-Boot FIT image file. This gets diff --git a/MAINTAINERS b/MAINTAINERS index 74a1423f50..08222fd569 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -321,14 +321,19 @@ ARM STM STM32MP M: Patrick Delaunay <patrick.delaunay@st.com> M: Patrice Chotard <patrice.chotard@st.com> L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers) -T: git https://gitlab.denx.de/u-boot/custodians/u-boot-stm +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git S: Maintained F: arch/arm/mach-stm32mp/ +F: drivers/adc/stm32-adc* F: drivers/clk/clk_stm32mp1.c +F: drivers/gpio/stm32_gpio.c +F: drivers/hwspinlock/stm32_hwspinlock.c F: drivers/i2c/stm32f7_i2c.c F: drivers/mailbox/stm32-ipcc.c F: drivers/misc/stm32mp_fuse.c +F: drivers/misc/stm32_rcc.c F: drivers/mmc/stm32_sdmmc2.c +F: drivers/mtd/nand/raw/stm32_fmc2_nand.c F: drivers/phy/phy-stm32-usbphyc.c F: drivers/pinctrl/pinctrl_stm32.c F: drivers/power/pmic/stpmic1.c @@ -336,11 +341,21 @@ F: drivers/power/regulator/stm32-vrefbuf.c F: drivers/power/regulator/stpmic1.c F: drivers/ram/stm32mp1/ F: drivers/remoteproc/stm32_copro.c -F: drivers/misc/stm32_rcc.c F: drivers/reset/stm32-reset.c +F: drivers/rtc/stm32_rtc.c +F: drivers/serial/serial_stm32.* F: drivers/spi/stm32_qspi.c F: drivers/spi/stm32_spi.c +F: drivers/video/stm32/stm32_ltdc.c F: drivers/watchdog/stm32mp_wdt.c +F: include/dt-bindings/clock/stm32fx-clock.h +F: include/dt-bindings/clock/stm32mp1-clks.h +F: include/dt-bindings/clock/stm32mp1-clksrc.h +F: include/dt-bindings/pinctrl/stm32-pinfunc.h +F: include/dt-bindings/reset/stm32mp1-resets.h +F: include/stm32_rcc.h +F: tools/stm32image.c + ARM STM STV0991 M: Vikas Manocha <vikas.manocha@st.com> @@ -3,7 +3,7 @@ VERSION = 2019 PATCHLEVEL = 10 SUBLEVEL = -EXTRAVERSION = -rc2 +EXTRAVERSION = -rc3 NAME = # *DOCUMENTATION* @@ -1256,8 +1256,16 @@ MKIMAGEFLAGS_u-boot-spl.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \ MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \ -R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage +ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy) +UBOOT_BIN := u-boot-with-dtb.bin +else +UBOOT_BIN := u-boot.bin +endif + u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \ - $(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin dts/dt.dtb,u-boot.bin) FORCE + $(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin \ + $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_OF_HOSTFILE),dts/dt.dtb) \ + ,$(UBOOT_BIN)) FORCE $(call if_changed,mkimage) $(BOARD_SIZE_CHECK) @@ -1267,7 +1275,9 @@ else MKIMAGEFLAGS_u-boot.itb = -E endif -u-boot.itb: u-boot-nodtb.bin dts/dt.dtb $(U_BOOT_ITS) FORCE +u-boot.itb: u-boot-nodtb.bin \ + $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_OF_HOSTFILE),dts/dt.dtb) \ + $(U_BOOT_ITS) FORCE $(call if_changed,mkfitimage) $(BOARD_SIZE_CHECK) @@ -1690,7 +1700,7 @@ define filechk_defaultenv.h (grep -v '^#' | \ grep -v '^$$' | \ tr '\n' '\0' | \ - sed -e 's/\\\x0/\n/' | \ + sed -e 's/\\\x0/\n/g' | \ xxd -i ; echo ", 0x00" ; ) endef @@ -1842,7 +1852,7 @@ clean: $(clean-dirs) -o -name 'dsdt.aml' -o -name 'dsdt.asl.tmp' -o -name 'dsdt.c' \ -o -name '*.efi' -o -name '*.gcno' -o -name '*.so' \) \ -type f -print | xargs rm -f \ - bl31.c bl31.elf bl31_*.bin image.map + bl31.c bl31.elf bl31_*.bin image.map tispl.bin* # mrproper - Delete all generated files, including .config # diff --git a/arch/Kconfig b/arch/Kconfig index e510e971b4..f4ada57909 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -76,6 +76,12 @@ config RISCV imply MTD imply TIMER imply CMD_DM + imply SPL_DM + imply SPL_OF_CONTROL + imply SPL_LIBCOMMON_SUPPORT + imply SPL_LIBGENERIC_SUPPORT + imply SPL_SERIAL_SUPPORT + imply SPL_TIMER config SANDBOX bool "Sandbox" diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 1cb89c6f15..3b0e315061 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -329,6 +329,12 @@ config SYS_CACHELINE_SIZE default 64 if SYS_CACHE_SHIFT_6 default 32 if SYS_CACHE_SHIFT_5 +config ARCH_CPU_INIT + bool "Enable ARCH_CPU_INIT" + help + Some architectures require a call to arch_cpu_init() + Say Y here to enable it + config SYS_ARCH_TIMER bool "ARM Generic Timer support" depends on CPU_V7A || ARM64 @@ -367,7 +373,7 @@ config SYS_THUMB_BUILD config SPL_SYS_THUMB_BUILD bool "Build SPL using the Thumb instruction set" default y if SYS_THUMB_BUILD - depends on !ARM64 + depends on !ARM64 && SPL help Use this flag to build SPL using the Thumb instruction set for ARM architectures. Thumb instruction set provides better code @@ -414,7 +420,7 @@ config USE_ARCH_MEMCPY config SPL_USE_ARCH_MEMCPY bool "Use an assembly optimized implementation of memcpy for SPL" default y if USE_ARCH_MEMCPY - depends on !ARM64 + depends on !ARM64 && SPL help Enable the generation of an optimized version of memcpy. Such implementation may be faster under some conditions @@ -423,7 +429,7 @@ config SPL_USE_ARCH_MEMCPY config TPL_USE_ARCH_MEMCPY bool "Use an assembly optimized implementation of memcpy for TPL" default y if USE_ARCH_MEMCPY - depends on !ARM64 + depends on !ARM64 && TPL help Enable the generation of an optimized version of memcpy. Such implementation may be faster under some conditions @@ -441,7 +447,7 @@ config USE_ARCH_MEMSET config SPL_USE_ARCH_MEMSET bool "Use an assembly optimized implementation of memset for SPL" default y if USE_ARCH_MEMSET - depends on !ARM64 + depends on !ARM64 && SPL help Enable the generation of an optimized version of memset. Such implementation may be faster under some conditions @@ -450,7 +456,7 @@ config SPL_USE_ARCH_MEMSET config TPL_USE_ARCH_MEMSET bool "Use an assembly optimized implementation of memset for TPL" default y if USE_ARCH_MEMSET - depends on !ARM64 + depends on !ARM64 && TPL help Enable the generation of an optimized version of memset. Such implementation may be faster under some conditions @@ -458,7 +464,8 @@ config TPL_USE_ARCH_MEMSET config ARM64_SUPPORT_AARCH32 bool "ARM64 system support AArch32 execution state" - default y if ARM64 && !TARGET_THUNDERX_88XX + depends on ARM64 + default y if !TARGET_THUNDERX_88XX help This ARM64 system supports AArch32 execution state. @@ -1059,16 +1066,6 @@ config TARGET_VEXPRESS64_BASE_FVP select PL01X_SERIAL select SEMIHOSTING -config TARGET_VEXPRESS64_BASE_FVP_DRAM - bool "Support Versatile Express ARMv8a FVP BASE model booting from DRAM" - select ARM64 - select PL01X_SERIAL - help - This target is derived from TARGET_VEXPRESS64_BASE_FVP and over-rides - the default config to allow the user to load the images directly into - DRAM using model parameters rather than by using semi-hosting to load - the files from the host filesystem. - config TARGET_VEXPRESS64_JUNO bool "Support Versatile Express Juno Development Platform" select ARM64 @@ -1093,6 +1090,7 @@ config TARGET_LS2080A_SIMU select ARCH_MISC_INIT select ARM64 select ARMV8_MULTIENTRY + select BOARD_LATE_INIT help Support for Freescale LS2080A_SIMU platform The LS2080A Development System (QDS) is a pre silicon @@ -1306,6 +1304,8 @@ config TARGET_LS1028AQDS select ARM64 select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT + select BOARD_LATE_INIT + select ARCH_MISC_INIT help Support for Freescale LS1028AQDS platform The LS1028A Development System (QDS) is a high-performance @@ -1557,6 +1557,7 @@ config ARCH_STM32MP imply SPL_SYSRESET imply CMD_DM imply CMD_POWEROFF + imply OF_LIBFDT_OVERLAY imply ENV_VARS_UBOOT_RUNTIME_CONFIG imply USE_PREBOOT help diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 5c32738fbf..42d31fdab0 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -40,14 +40,6 @@ config ARCH_LS1028A select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F select SYS_I2C_MXC - select SYS_I2C_MXC_I2C1 - select SYS_I2C_MXC_I2C2 - select SYS_I2C_MXC_I2C3 - select SYS_I2C_MXC_I2C4 - select SYS_I2C_MXC_I2C5 - select SYS_I2C_MXC_I2C6 - select SYS_I2C_MXC_I2C7 - select SYS_I2C_MXC_I2C8 select SYS_FSL_ERRATUM_A008997 select SYS_FSL_ERRATUM_A009007 select SYS_FSL_ERRATUM_A008514 if !TFABOOT @@ -155,10 +147,10 @@ config ARCH_LS1088A select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F select SYS_I2C_MXC - select SYS_I2C_MXC_I2C1 - select SYS_I2C_MXC_I2C2 - select SYS_I2C_MXC_I2C3 - select SYS_I2C_MXC_I2C4 + select SYS_I2C_MXC_I2C1 if !TFABOOT + select SYS_I2C_MXC_I2C2 if !TFABOOT + select SYS_I2C_MXC_I2C3 if !TFABOOT + select SYS_I2C_MXC_I2C4 if !TFABOOT imply SCSI imply PANIC_HANG @@ -205,10 +197,10 @@ config ARCH_LS2080A select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F select SYS_I2C_MXC - select SYS_I2C_MXC_I2C1 - select SYS_I2C_MXC_I2C2 - select SYS_I2C_MXC_I2C3 - select SYS_I2C_MXC_I2C4 + select SYS_I2C_MXC_I2C1 if !TFABOOT + select SYS_I2C_MXC_I2C2 if !TFABOOT + select SYS_I2C_MXC_I2C3 if !TFABOOT + select SYS_I2C_MXC_I2C4 if !TFABOOT imply DISTRO_DEFAULTS imply PANIC_HANG @@ -235,14 +227,6 @@ config ARCH_LX2160A select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F select SYS_I2C_MXC - select SYS_I2C_MXC_I2C1 - select SYS_I2C_MXC_I2C2 - select SYS_I2C_MXC_I2C3 - select SYS_I2C_MXC_I2C4 - select SYS_I2C_MXC_I2C5 - select SYS_I2C_MXC_I2C6 - select SYS_I2C_MXC_I2C7 - select SYS_I2C_MXC_I2C8 imply DISTRO_DEFAULTS imply PANIC_HANG imply SCSI @@ -513,6 +497,10 @@ config SYS_FSL_DUART_CLK_DIV config SYS_FSL_I2C_CLK_DIV int "I2C clock divider" default 1 if ARCH_LS1043A + default 4 if ARCH_LS1012A + default 4 if ARCH_LS1028A + default 8 if ARCH_LX2160A + default 8 if ARCH_LS1088A default 2 help This is the divider that is used to derive I2C clock from Platform diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index a8d3cf91fc..efecbc07e7 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -47,8 +47,10 @@ endif ifneq ($(CONFIG_ARCH_LS1088A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o +obj-y += icid.o ls1088_ids.o endif ifneq ($(CONFIG_ARCH_LS1028A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls1028a_serdes.o +obj-y += icid.o ls1028_ids.o endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c b/arch/arm/cpu/armv8/fsl-layerscape/icid.c index b1a950e7f9..82c5a8b123 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c @@ -17,7 +17,10 @@ static void set_icid(struct icid_id_table *tbl, int size) int i; for (i = 0; i < size; i++) - out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg); + if (tbl[i].le) + out_le32((u32 *)(tbl[i].reg_addr), tbl[i].reg); + else + out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg); } #ifdef CONFIG_SYS_DPAA_FMAN diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c new file mode 100644 index 0000000000..d9d125e8ba --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <asm/arch-fsl-layerscape/immap_lsch3.h> +#include <asm/arch-fsl-layerscape/fsl_icid.h> +#include <asm/arch-fsl-layerscape/fsl_portals.h> + +struct icid_id_table icid_tbl[] = { + SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID), + SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID), + SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID), + SET_SDHC_ICID(2, FSL_SDMMC2_STREAM_ID), + SET_SATA_ICID(1, "fsl,ls1028a-ahci", FSL_SATA1_STREAM_ID), + SET_EDMA_ICID(FSL_EDMA_STREAM_ID), + SET_QDMA_ICID("fsl,ls1028a-qdma", FSL_DMA_STREAM_ID), + SET_GPU_ICID("fsl,ls1028a-gpu", FSL_GPU_STREAM_ID), + SET_DISPLAY_ICID(FSL_DISPLAY_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID), +}; + +int icid_tbl_sz = ARRAY_SIZE(icid_tbl); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c new file mode 100644 index 0000000000..49e27553b1 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <asm/arch-fsl-layerscape/immap_lsch3.h> +#include <asm/arch-fsl-layerscape/fsl_icid.h> +#include <asm/arch-fsl-layerscape/fsl_portals.h> + +struct icid_id_table icid_tbl[] = { + SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID), + SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID), + SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID), + SET_SATA_ICID(1, "fsl,ls1088a-ahci", FSL_SATA1_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID), +}; + +int icid_tbl_sz = ARRAY_SIZE(icid_tbl); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index ca8005992a..3fd34e3a43 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -340,6 +340,10 @@ void fsl_lsch3_early_init_f(void) if (fsl_check_boot_mode_secure() == 1) bypass_smmu(); #endif + +#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) + set_icids(); +#endif } /* Get VDD in the unit mV from voltage ID */ diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 05ff624c07..aac1b83d49 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -81,7 +81,6 @@ dtb-$(CONFIG_ROCKCHIP_RK322X) += \ dtb-$(CONFIG_ROCKCHIP_RK3288) += \ rk3288-evb.dtb \ - rk3288-fennec.dtb \ rk3288-firefly.dtb \ rk3288-miqi.dtb \ rk3288-phycore-rdk.dtb \ diff --git a/arch/arm/dts/fsl-ls1028a-qds.dts b/arch/arm/dts/fsl-ls1028a-qds.dts index 94d0aa0f95..3fb35f186d 100644 --- a/arch/arm/dts/fsl-ls1028a-qds.dts +++ b/arch/arm/dts/fsl-ls1028a-qds.dts @@ -37,10 +37,23 @@ &i2c0 { status = "okay"; + u-boot,dm-pre-reloc; + + i2c-mux@77 { + compatible = "nxp,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + }; }; &i2c1 { status = "okay"; + + rtc@51 { + compatible = "pcf2127-rtc"; + reg = <0x51>; + }; }; &i2c2 { diff --git a/arch/arm/dts/fsl-ls1028a-rdb.dts b/arch/arm/dts/fsl-ls1028a-rdb.dts index 052538937b..d18cf6d5ae 100644 --- a/arch/arm/dts/fsl-ls1028a-rdb.dts +++ b/arch/arm/dts/fsl-ls1028a-rdb.dts @@ -37,6 +37,26 @@ &i2c0 { status = "okay"; + u-boot,dm-pre-reloc; + + i2c-mux@77 { + + compatible = "nxp,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + rtc@51 { + compatible = "pcf2127-rtc"; + reg = <0x51>; + }; + }; + }; }; &i2c1 { diff --git a/arch/arm/dts/fsl-ls1088a-qds.dts b/arch/arm/dts/fsl-ls1088a-qds.dts index 8fbb52f0e0..f07d0c6f27 100644 --- a/arch/arm/dts/fsl-ls1088a-qds.dts +++ b/arch/arm/dts/fsl-ls1088a-qds.dts @@ -18,6 +18,29 @@ }; }; +&i2c0 { + status = "okay"; + u-boot,dm-pre-reloc; + + i2c-mux@77 { + compatible = "nxp,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + rtc@51 { + compatible = "pcf2127-rtc"; + reg = <0x51>; + }; + }; + }; +}; + &ifc { #address-cells = <2>; #size-cells = <1>; diff --git a/arch/arm/dts/fsl-ls1088a-rdb.dts b/arch/arm/dts/fsl-ls1088a-rdb.dts index 765d1e3d74..0fe351973d 100644 --- a/arch/arm/dts/fsl-ls1088a-rdb.dts +++ b/arch/arm/dts/fsl-ls1088a-rdb.dts @@ -17,6 +17,29 @@ }; }; +&i2c0 { + status = "okay"; + u-boot,dm-pre-reloc; + + i2c-mux@77 { + compatible = "nxp,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + rtc@51 { + compatible = "pcf2127-rtc"; + reg = <0x51>; + }; + }; + }; +}; + &qspi { bus-num = <0>; status = "okay"; diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 7c705858fd..4be1ab87d2 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -34,6 +34,38 @@ <1 10 0x8>; /* Hypervisor PPI, active-low */ }; + i2c0: i2c@2000000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts = <0 34 4>; + }; + + i2c1: i2c@2010000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2010000 0x0 0x10000>; + interrupts = <0 34 4>; + }; + + i2c2: i2c@2020000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2020000 0x0 0x10000>; + interrupts = <0 35 4>; + }; + + i2c3: i2c@2030000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2030000 0x0 0x10000>; + interrupts = <0 35 4>; + }; + serial0: serial@21c0500 { device_type = "serial"; compatible = "fsl,ns16550", "ns16550a"; diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b/arch/arm/dts/fsl-ls2080a-qds.dts index 2a0a5280d0..13461b5c45 100644 --- a/arch/arm/dts/fsl-ls2080a-qds.dts +++ b/arch/arm/dts/fsl-ls2080a-qds.dts @@ -19,6 +19,25 @@ }; }; +&i2c0 { + status = "okay"; + pca9547@77 { + compatible = "nxp,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x00>; + rtc@68 { + compatible = "dallas,ds3232"; + reg = <0x68>; + }; + }; + }; +}; + &dspi { bus-num = <0>; status = "okay"; diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi index 5c0769bc99..99ed33af95 100644 --- a/arch/arm/dts/fsl-ls2080a.dtsi +++ b/arch/arm/dts/fsl-ls2080a.dtsi @@ -56,6 +56,42 @@ <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ }; + i2c0: i2c@2000000 { + status = "disabled"; + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts = <0 34 0x4>; /* Level high type */ + }; + + i2c1: i2c@2010000 { + status = "disabled"; + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2010000 0x0 0x10000>; + interrupts = <0 34 0x4>; /* Level high type */ + }; + + i2c2: i2c@2020000 { + status = "disabled"; + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2020000 0x0 0x10000>; + interrupts = <0 35 0x4>; /* Level high type */ + }; + + i2c3: i2c@2030000 { + status = "disabled"; + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2030000 0x0 0x10000>; + interrupts = <0 35 0x4>; /* Level high type */ + }; + dspi: dspi@2100000 { compatible = "fsl,vf610-dspi"; #address-cells = <1>; diff --git a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts index bf97d138fc..72b2177b70 100644 --- a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts +++ b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts @@ -57,6 +57,28 @@ }; }; +&i2c0 { + status = "okay"; + u-boot,dm-pre-reloc; + + pca9547@75 { + compatible = "nxp,pca9547"; + reg = <0x75>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x01>; + rtc@68 { + compatible = "dallas,ds3232"; + reg = <0x68>; + }; + }; + }; +}; + &sata { status = "okay"; }; diff --git a/arch/arm/dts/fsl-lx2160a-qds.dts b/arch/arm/dts/fsl-lx2160a-qds.dts index 99836c4ccb..34df0f5106 100644 --- a/arch/arm/dts/fsl-lx2160a-qds.dts +++ b/arch/arm/dts/fsl-lx2160a-qds.dts @@ -23,6 +23,29 @@ status = "okay"; }; +&i2c0 { + status = "okay"; + u-boot,dm-pre-reloc; + + i2c-mux@77 { + compatible = "nxp,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + rtc@51 { + compatible = "pcf2127-rtc"; + reg = <0x51>; + }; + }; + }; +}; + &sata0 { status = "okay"; }; diff --git a/arch/arm/dts/fsl-lx2160a-rdb.dts b/arch/arm/dts/fsl-lx2160a-rdb.dts index 4b526449a1..7b6608b1d6 100644 --- a/arch/arm/dts/fsl-lx2160a-rdb.dts +++ b/arch/arm/dts/fsl-lx2160a-rdb.dts @@ -27,6 +27,20 @@ status = "okay"; }; +&i2c0 { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&i2c4 { + status = "okay"; + + rtc@51 { + compatible = "pcf2127-rtc"; + reg = <0x51>; + }; +}; + &sata0 { status = "okay"; }; diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi index 28220781d3..a189333e40 100644 --- a/arch/arm/dts/fsl-lx2160a.dtsi +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -49,6 +49,80 @@ <1 10 0x8>; /* Hypervisor PPI, active-low */ }; + i2c0: i2c@2000000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts = <0 34 4>; + scl-gpio = <&gpio2 15 0>; + status = "disabled"; + }; + + i2c1: i2c@2010000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2010000 0x0 0x10000>; + interrupts = <0 34 4>; + status = "disabled"; + }; + + i2c2: i2c@2020000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2020000 0x0 0x10000>; + interrupts = <0 35 4>; + status = "disabled"; + }; + + i2c3: i2c@2030000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2030000 0x0 0x10000>; + interrupts = <0 35 4>; + status = "disabled"; + }; + + i2c4: i2c@2040000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2040000 0x0 0x10000>; + interrupts = <0 74 4>; + scl-gpio = <&gpio2 16 0>; + status = "disabled"; + }; + + i2c5: i2c@2050000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2050000 0x0 0x10000>; + interrupts = <0 74 4>; + status = "disabled"; + }; + + i2c6: i2c@2060000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2060000 0x0 0x10000>; + interrupts = <0 75 4>; + status = "disabled"; + }; + + i2c7: i2c@2070000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2070000 0x0 0x10000>; + interrupts = <0 75 4>; + status = "disabled"; + }; + uart0: serial@21c0000 { compatible = "arm,pl011"; reg = <0x0 0x21c0000 0x0 0x1000>; @@ -102,6 +176,17 @@ num-cs = <6>; }; + gpio2: gpio@2320000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x0 0x2320000 0x0 0x10000>; + interrupts = <0 37 4>; + gpio-controller; + little-endian; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + usb0: usb3@3100000 { compatible = "fsl,layerscape-dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; diff --git a/arch/arm/dts/logicpd-som-lv.dtsi b/arch/arm/dts/logicpd-som-lv.dtsi index 5563ee54c9..b56524cc7f 100644 --- a/arch/arm/dts/logicpd-som-lv.dtsi +++ b/arch/arm/dts/logicpd-som-lv.dtsi @@ -228,6 +228,20 @@ >; }; + i2c2_pins: pinmux_i2c2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ + OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ + >; + }; + + i2c3_pins: pinmux_i2c3_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ + OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ + >; + }; + tsc2004_pins: pinmux_tsc2004_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE4) /* mcbsp4_dr.gpio_153 */ @@ -249,18 +263,6 @@ OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */ >; }; - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ - OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ - >; - }; - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ - OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ - >; - }; }; &omap3_pmx_core2 { diff --git a/arch/arm/dts/rk3288-fennec-u-boot.dtsi b/arch/arm/dts/rk3288-fennec-u-boot.dtsi deleted file mode 100644 index 2efb309d6b..0000000000 --- a/arch/arm/dts/rk3288-fennec-u-boot.dtsi +++ /dev/null @@ -1,54 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2019 Rockchip Electronics Co., Ltd - */ - -#include "rk3288-u-boot.dtsi" - -&pinctrl { - u-boot,dm-pre-reloc; -}; - -&uart2 { - u-boot,dm-pre-reloc; -}; - -&sdmmc { - u-boot,dm-pre-reloc; -}; - -&emmc { - u-boot,dm-pre-reloc; -}; - -&gpio3 { - u-boot,dm-pre-reloc; -}; - -&gpio8 { - u-boot,dm-pre-reloc; -}; - -&pcfg_pull_none_drv_8ma { - u-boot,dm-spl; -}; - -&pcfg_pull_up_drv_8ma { - u-boot,dm-spl; -}; - -&sdmmc_bus4 { - u-boot,dm-spl; -}; - -&sdmmc_clk { - u-boot,dm-spl; -}; - -&sdmmc_cmd { - u-boot,dm-spl; -}; - -&sdmmc_pwr { - u-boot,dm-spl; -}; diff --git a/arch/arm/dts/rk3288-fennec.dts b/arch/arm/dts/rk3288-fennec.dts deleted file mode 100644 index e1d55e3104..0000000000 --- a/arch/arm/dts/rk3288-fennec.dts +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -/dts-v1/; -#include "rk3288-fennec.dtsi" - -/ { - model = "Rockchip RK3288 Fennec Board"; - compatible = "rockchip,rk3288-fennec", "rockchip,rk3288"; - - chosen { - stdout-path = &uart2; - }; -}; - -&dmc { - rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d - 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 - 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0 - 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4 - 0x8 0x1f4>; - rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076 - 0x0 0xc3 0x6 0x2>; - rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>; -}; - -&pwm1 { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3288-fennec.dtsi b/arch/arm/dts/rk3288-fennec.dtsi deleted file mode 100644 index f61252ce9d..0000000000 --- a/arch/arm/dts/rk3288-fennec.dtsi +++ /dev/null @@ -1,421 +0,0 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "rk3288.dtsi" - -/ { - memory { - reg = <0x0 0x80000000>; - device_type = "memory"; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - status = "okay"; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - clock_in_out = "input"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio0>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int &global_pwroff>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc_io>; - vcc9-supply = <&vcc_io>; - vcc10-supply = <&vcc_io>; - vcc11-supply = <&vcc_io>; - vcc12-supply = <&vcc_io>; - vddio-supply = <&vcc_io>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-name = "vdd_arm"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd_gpu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_ddr"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_io"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vccio_pmu: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_pmu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca_33: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcca_33"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_10: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd_10"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_wl: LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_wl"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vdd10_lcd: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd10_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_18: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_18"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc18_lcd: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sd: SWITCH_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_sd"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_lan: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_lan"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - }; - }; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { - drive-strength = <8>; - }; - - pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - gmac { - phy_int: phy-int { - rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_pmeb: phy-pmeb { - rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_rst: phy-rst { - rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdmmc { - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, - <6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, - <6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, - <6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; - }; - - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usbphy { - host_drv: host-drv { - rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&uart2 { - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&host_drv>; - vbus_drv-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host1 { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&usb_hsic { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&vpu { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3328-evb-u-boot.dtsi b/arch/arm/dts/rk3328-evb-u-boot.dtsi index 58ebf52b4b..4a827063c5 100644 --- a/arch/arm/dts/rk3328-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3328-evb-u-boot.dtsi @@ -1,33 +1,12 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * (C) Copyright 2016-2019 Rockchip Electronics Co., Ltd */ +#include "rk3328-u-boot.dtsi" #include "rk3328-sdram-ddr3-666.dtsi" -/ { - aliases { - mmc0 = &emmc; - mmc1 = &sdmmc; - }; - - chosen { - u-boot,spl-boot-order = &emmc, &sdmmc; - }; -}; - -&cru { - u-boot,dm-pre-reloc; -}; - -&uart2 { - u-boot,dm-pre-reloc; -}; - -&emmc { - u-boot,dm-pre-reloc; -}; - -&sdmmc { - u-boot,dm-pre-reloc; +&usb_host0_xhci { + vbus-supply = <&vcc5v0_host_xhci>; + status = "okay"; }; diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts index ec594a8452..a2ee838fcd 100644 --- a/arch/arm/dts/rk3328-evb.dts +++ b/arch/arm/dts/rk3328-evb.dts @@ -116,11 +116,6 @@ status = "okay"; }; -&usb_host0_xhci { - vbus-supply = <&vcc5v0_host_xhci>; - status = "okay"; -}; - &i2c1 { clock-frequency = <400000>; i2c-scl-rising-time-ns = <168>; diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index dbcce6ac64..1d441f7124 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -1,34 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * (C) Copyright 2018 Rockchip Electronics Co., Ltd - * - * SPDX-License-Identifier: GPL-2.0+ + * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd */ +#include "rk3328-u-boot.dtsi" #include "rk3328-sdram-lpddr3-1600.dtsi" -/ { - aliases { - mmc0 = &emmc; - mmc1 = &sdmmc; - }; - - chosen { - u-boot,spl-boot-order = &emmc, &sdmmc; - }; -}; - -&cru { - u-boot,dm-pre-reloc; -}; - -&uart2 { - u-boot,dm-pre-reloc; -}; - -&emmc { - u-boot,dm-pre-reloc; -}; - -&sdmmc { - u-boot,dm-pre-reloc; +&usb_host0_xhci { + status = "okay"; }; diff --git a/arch/arm/dts/rk3328-rock64.dts b/arch/arm/dts/rk3328-rock64.dts index 7bcc53fcce..a78eb4ac6f 100644 --- a/arch/arm/dts/rk3328-rock64.dts +++ b/arch/arm/dts/rk3328-rock64.dts @@ -34,23 +34,10 @@ vcc_host_5v: vcc-host-5v-regulator { compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb30_host_drv>; - regulator-name = "vcc_host_5v"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&usb20_host_drv>; - regulator-name = "vcc_host1_5v"; + regulator-name = "vcc_host_5v"; regulator-always-on; regulator-boot-on; vin-supply = <&vcc_sys>; @@ -244,12 +231,6 @@ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; - - usb3 { - usb30_host_drv: usb30-host-drv { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; }; &sdmmc { diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi new file mode 100644 index 0000000000..ffbd657e31 --- /dev/null +++ b/arch/arm/dts/rk3328-u-boot.dtsi @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +/ { + aliases { + mmc0 = &emmc; + mmc1 = &sdmmc; + }; + + chosen { + u-boot,spl-boot-order = &emmc, &sdmmc; + }; + + dmc: dmc { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3328-dmc"; + reg = <0x0 0xff400000 0x0 0x1000 + 0x0 0xff780000 0x0 0x3000 + 0x0 0xff100000 0x0 0x1000 + 0x0 0xff440000 0x0 0x1000 + 0x0 0xff720000 0x0 0x1000 + 0x0 0xff798000 0x0 0x1000>; + }; + + usb_host0_xhci: usb@ff600000 { + compatible = "rockchip,rk3328-xhci"; + reg = <0x0 0xff600000 0x0 0x100000>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + snps,dis-enblslpm-quirk; + snps,phyif-utmi-bits = <16>; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-u2-susphy-quirk; + status = "disabled"; + }; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&grf { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; + clock-frequency = <24000000>; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; + +&sdmmc { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi index a080ae8d69..060c84e6c0 100644 --- a/arch/arm/dts/rk3328.dtsi +++ b/arch/arm/dts/rk3328.dtsi @@ -186,7 +186,6 @@ }; grf: syscon@ff100000 { - u-boot,dm-pre-reloc; compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; reg = <0x0 0xff100000 0x0 0x1000>; @@ -232,7 +231,6 @@ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; - clock-frequency = <24000000>; reg-shift = <2>; reg-io-width = <4>; dmas = <&dmac 6>, <&dmac 7>; @@ -351,17 +349,6 @@ status = "disabled"; }; - dmc: dmc { - u-boot,dm-pre-reloc; - compatible = "rockchip,rk3328-dmc"; - reg = <0x0 0xff400000 0x0 0x1000 - 0x0 0xff780000 0x0 0x3000 - 0x0 0xff100000 0x0 0x1000 - 0x0 0xff440000 0x0 0x1000 - 0x0 0xff720000 0x0 0x1000 - 0x0 0xff798000 0x0 0x1000>; - }; - cru: clock-controller@ff440000 { compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; reg = <0x0 0xff440000 0x0 0x1000>; @@ -512,17 +499,6 @@ status = "disabled"; }; - usb_host0_xhci: usb@ff600000 { - compatible = "rockchip,rk3328-xhci"; - reg = <0x0 0xff600000 0x0 0x100000>; - interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; - snps,dis-enblslpm-quirk; - snps,phyif-utmi-bits = <16>; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-u2-susphy-quirk; - status = "disabled"; - }; - gic: interrupt-controller@ffb70000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; diff --git a/arch/arm/dts/stih407-clock.dtsi b/arch/arm/dts/stih407-clock.dtsi index 13029c03d7..1ab40db7c9 100644 --- a/arch/arm/dts/stih407-clock.dtsi +++ b/arch/arm/dts/stih407-clock.dtsi @@ -1,39 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 STMicroelectronics R&D Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include <dt-bindings/clock/stih407-clks.h> / { + /* + * Fixed 30MHz oscillator inputs to SoC + */ + clk_sysin: clk-sysin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <30000000>; + }; + + clk_tmdsout_hdmi: clk-tmdsout-hdmi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + clocks { #address-cells = <1>; #size-cells = <1>; ranges; /* - * Fixed 30MHz oscillator inputs to SoC - */ - clk_sysin: clk-sysin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <30000000>; - }; - - /* - * ARM Peripheral clock for timers - */ - arm_periph_clk: clk-m-a9-periphs { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - - clocks = <&clk_m_a9>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* * A9 PLL. */ clockgen-a9@92b0000 { @@ -62,35 +53,22 @@ <&clockgen_a9_pll 0>, <&clk_s_c0_flexgen 13>, <&clk_m_a9_ext2f_div2>; - }; - /* - * ARM Peripheral clock for timers - */ - clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_s_c0_flexgen 13>; - - clock-output-names = "clk-m-a9-ext2f-div2"; - - clock-div = <2>; - clock-mult = <1>; - }; + /* + * ARM Peripheral clock for timers + */ + arm_periph_clk: clk-m-a9-periphs { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; - /* - * Bootloader initialized system infrastructure clock for - * serial devices. - */ - clk_ext2f_a9: clockgen-c0@13 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <200000000>; - clock-output-names = "clk-s-icn-reg-0"; + clocks = <&clk_m_a9>; + clock-div = <2>; + clock-mult = <1>; + }; }; - clockgen-a@090ff000 { + clockgen-a@90ff000 { compatible = "st,clkgen-c32"; reg = <0x90ff000 0x1000>; @@ -101,6 +79,7 @@ clocks = <&clk_sysin>; clock-output-names = "clk-s-a0-pll-ofd-0"; + clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */ }; clk_s_a0_flexgen: clk-s-a0-flexgen { @@ -112,6 +91,7 @@ <&clk_sysin>; clock-output-names = "clk-ic-lmi0"; + clock-critical = <CLK_IC_LMI0>; }; }; @@ -126,9 +106,10 @@ "clk-s-c0-fs0-ch1", "clk-s-c0-fs0-ch2", "clk-s-c0-fs0-ch3"; + clock-critical = <0>; /* clk-s-c0-fs0-ch0 */ }; - clk_s_c0: clockgen-c@09103000 { + clk_s_c0: clockgen-c@9103000 { compatible = "st,clkgen-c32"; reg = <0x9103000 0x1000>; @@ -139,6 +120,7 @@ clocks = <&clk_sysin>; clock-output-names = "clk-s-c0-pll0-odf-0"; + clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */ }; clk_s_c0_pll1: clk-s-c0-pll1 { @@ -194,6 +176,27 @@ "clk-main-disp", "clk-aux-disp", "clk-compo-dvp"; + clock-critical = <CLK_PROC_STFE>, + <CLK_ICN_CPU>, + <CLK_TX_ICN_DMU>, + <CLK_EXT2F_A9>, + <CLK_ICN_LMI>, + <CLK_ICN_SBC>; + + /* + * ARM Peripheral clock for timers + */ + clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + + clocks = <&clk_s_c0_flexgen 13>; + + clock-output-names = "clk-m-a9-ext2f-div2"; + + clock-div = <2>; + clock-mult = <1>; + }; }; }; @@ -210,7 +213,7 @@ "clk-s-d0-fs0-ch3"; }; - clockgen-d0@09104000 { + clockgen-d0@9104000 { compatible = "st,clkgen-c32"; reg = <0x9104000 0x1000>; @@ -244,13 +247,7 @@ "clk-s-d2-fs0-ch3"; }; - clk_tmdsout_hdmi: clk-tmdsout-hdmi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clockgen-d2@x9106000 { + clockgen-d2@9106000 { compatible = "st,clkgen-c32"; reg = <0x9106000 0x1000>; diff --git a/arch/arm/dts/stih407-family.dtsi b/arch/arm/dts/stih407-family.dtsi index 6c6de58029..7c36c37260 100644 --- a/arch/arm/dts/stih407-family.dtsi +++ b/arch/arm/dts/stih407-family.dtsi @@ -1,10 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 STMicroelectronics Limited. * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. */ #include "stih407-pinctrl.dtsi" #include <dt-bindings/mfd/st-lpc.h> @@ -20,7 +17,13 @@ #size-cells = <1>; ranges; - dmu_reserved: rproc@44000000 { + gp0_reserved: rproc@45000000 { + compatible = "shared-dma-pool"; + reg = <0x45000000 0x00400000>; + no-map; + }; + + delta_reserved: rproc@44000000 { compatible = "shared-dma-pool"; reg = <0x44000000 0x01000000>; no-map; @@ -47,6 +50,7 @@ clocks = <&clk_m_a9>; clock-names = "cpu"; clock-latency = <100000>; + cpu0-supply = <&pwm_regulator>; st,syscfg = <&syscfg_core 0x8e0>; }; cpu@1 { @@ -65,19 +69,19 @@ }; }; - intc: interrupt-controller@08761000 { + intc: interrupt-controller@8761000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0x08761000 0x1000>, <0x08760100 0x100>; }; - scu@08760000 { + scu@8760000 { compatible = "arm,cortex-a9-scu"; reg = <0x08760000 0x1000>; }; - timer@08760200 { + timer@8760200 { interrupt-parent = <&intc>; compatible = "arm,cortex-a9-global-timer"; reg = <0x08760200 0x100>; @@ -85,7 +89,7 @@ clocks = <&arm_periph_clk>; }; - l2: cache-controller { + l2: cache-controller@8762000 { compatible = "arm,pl310-cache"; reg = <0x08762000 0x1000>; arm,data-latency = <3 3 3>; @@ -118,24 +122,28 @@ ranges; compatible = "simple-bus"; - restart { + restart: restart-controller@0 { compatible = "st,stih407-restart"; + reg = <0 0>; st,syscfg = <&syscfg_sbc_reg>; status = "okay"; }; - powerdown: powerdown-controller { + powerdown: powerdown-controller@0 { compatible = "st,stih407-powerdown"; + reg = <0 0>; #reset-cells = <1>; }; - softreset: softreset-controller { + softreset: softreset-controller@0 { compatible = "st,stih407-softreset"; + reg = <0 0>; #reset-cells = <1>; }; - picophyreset: picophyreset-controller { + picophyreset: picophyreset-controller@0 { compatible = "st,stih407-picophyreset"; + reg = <0 0>; #reset-cells = <1>; }; @@ -167,6 +175,13 @@ syscfg_core: core-syscfg@92b0000 { compatible = "st,stih407-core-syscfg", "syscon"; reg = <0x92b0000 0x1000>; + + sti_sasg_codec: sti-sasg-codec { + compatible = "st,stih407-sas-codec"; + #sound-dai-cells = <1>; + status = "disabled"; + st,syscfg = <&syscfg_core>; + }; }; syscfg_lpm: lpm-syscfg@94b5100 { @@ -174,8 +189,9 @@ reg = <0x94b5100 0x1000>; }; - irq-syscfg { + irq-syscfg@0 { compatible = "st,stih407-irq-syscfg"; + reg = <0 0>; st,syscfg = <&syscfg_core>; st,irq-device = <ST_IRQ_SYSCFG_PMU_0>, <ST_IRQ_SYSCFG_PMU_1>; @@ -187,22 +203,21 @@ vtg_main: sti-vtg-main@8d02800 { compatible = "st,vtg"; reg = <0x8d02800 0x200>; - interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; }; vtg_aux: sti-vtg-aux@8d00200 { compatible = "st,vtg"; reg = <0x8d00200 0x100>; - interrupts = <GIC_SPI 109 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; }; serial@9830000 { compatible = "st,asc"; reg = <0x9830000 0x2c>; - interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_serial0>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; + /* Pinctrl moved out to a per-board configuration */ status = "disabled"; }; @@ -210,7 +225,7 @@ serial@9831000 { compatible = "st,asc"; reg = <0x9831000 0x2c>; - interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_serial1>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; @@ -221,7 +236,7 @@ serial@9832000 { compatible = "st,asc"; reg = <0x9832000 0x2c>; - interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_serial2>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; @@ -233,7 +248,7 @@ sbc_serial0: serial@9530000 { compatible = "st,asc"; reg = <0x9530000 0x2c>; - interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sbc_serial0>; clocks = <&clk_sysin>; @@ -244,7 +259,7 @@ serial@9531000 { compatible = "st,asc"; reg = <0x9531000 0x2c>; - interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sbc_serial1>; clocks = <&clk_sysin>; @@ -374,8 +389,9 @@ status = "disabled"; }; - usb2_picophy0: phy1 { + usb2_picophy0: phy1@0 { compatible = "st,stih407-usb2-phy"; + reg = <0 0>; #phy-cells = <0>; st,syscfg = <&syscfg_core 0x100 0xf4>; resets = <&softreset STIH407_PICOPHY_SOFTRESET>, @@ -383,12 +399,13 @@ reset-names = "global", "port"; }; - miphy28lp_phy: miphy28lp@9b22000 { + miphy28lp_phy: miphy28lp@0 { compatible = "st,miphy28lp-phy"; st,syscfg = <&syscfg_core>; #address-cells = <1>; #size-cells = <1>; ranges; + reg = <0 0>; phy_port0: port@9b22000 { reg = <0x9b22000 0xff>, @@ -458,6 +475,8 @@ clock-names = "ssc"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1_default>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -470,6 +489,8 @@ clock-names = "ssc"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi2_default>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -482,6 +503,8 @@ clock-names = "ssc"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi3_default>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -494,6 +517,8 @@ clock-names = "ssc"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi4_default>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -507,6 +532,8 @@ clock-names = "ssc"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi10_default>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -519,6 +546,8 @@ clock-names = "ssc"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi11_default>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -531,16 +560,18 @@ clock-names = "ssc"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi12_default>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; - mmc0: sdhci@09060000 { + mmc0: sdhci@9060000 { compatible = "st,sdhci-stih407", "st,sdhci"; status = "disabled"; reg = <0x09060000 0x7ff>, <0x9061008 0x20>; reg-names = "mmc", "top-mmc-delay"; - interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "mmcirq"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mmc0>; @@ -550,12 +581,12 @@ bus-width = <8>; }; - mmc1: sdhci@09080000 { + mmc1: sdhci@9080000 { compatible = "st,sdhci-stih407", "st,sdhci"; status = "disabled"; reg = <0x09080000 0x7ff>; reg-names = "mmc"; - interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "mmcirq"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sd1>; @@ -563,7 +594,6 @@ clocks = <&clk_s_c0_flexgen CLK_MMC_1>, <&clk_s_c0_flexgen CLK_RX_ICN_HVA>; resets = <&softreset STIH407_MMC1_SOFTRESET>; - reset-names = "softreset"; bus-width = <4>; }; @@ -590,7 +620,7 @@ compatible = "st,ahci"; reg = <0x9b20000 0x1000>; - interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hostc"; phys = <&phy_port0 PHY_TYPE_SATA>; @@ -613,7 +643,7 @@ compatible = "st,ahci"; reg = <0x9b28000 0x1000>; - interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hostc"; phys = <&phy_port1 PHY_TYPE_SATA>; @@ -654,11 +684,12 @@ dwc3: dwc3@9900000 { compatible = "snps,dwc3"; reg = <0x09900000 0x100000>; - interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>; - dr_mode = "peripheral"; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; phy-names = "usb2-phy", "usb3-phy"; phys = <&usb2_picophy0>, <&phy_port2 PHY_TYPE_USB3>; + snps,dis_u3_susphy_quirk; }; }; @@ -667,7 +698,7 @@ compatible = "st,sti-pwm"; #pwm-cells = <2>; reg = <0x9810000 0x68>; - interrupts = <GIC_SPI 128 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm0_chan0_default>; clock-names = "pwm"; @@ -682,6 +713,7 @@ compatible = "st,sti-pwm"; #pwm-cells = <2>; reg = <0x9510000 0x68>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1_chan0_default &pinctrl_pwm1_chan1_default @@ -694,14 +726,14 @@ status = "disabled"; }; - rng10: rng@08a89000 { + rng10: rng@8a89000 { compatible = "st,rng"; reg = <0x08a89000 0x1000>; clocks = <&clk_sysin>; status = "okay"; }; - rng11: rng@08a8a000 { + rng11: rng@8a8a000 { compatible = "st,rng"; reg = <0x08a8a000 0x1000>; clocks = <&clk_sysin>; @@ -720,8 +752,8 @@ resets = <&softreset STIH407_ETH1_SOFTRESET>; reset-names = "stmmaceth"; - interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>, - <GIC_SPI 99 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq", "eth_wake_irq"; /* DMA Bus Mode */ @@ -735,26 +767,14 @@ <&clk_s_c0_flexgen CLK_ETH_PHY>; }; - cec: sti-cec@094a087c { - compatible = "st,stih-cec"; - reg = <0x94a087c 0x64>; - clocks = <&clk_sysin>; - clock-names = "cec-clk"; - interrupts = <GIC_SPI 140 IRQ_TYPE_NONE>; - interrupt-names = "cec-irq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cec0_default>; - resets = <&softreset STIH407_LPM_SOFTRESET>; - }; - - rng10: rng@08a89000 { + rng10: rng@8a89000 { compatible = "st,rng"; reg = <0x08a89000 0x1000>; clocks = <&clk_sysin>; status = "okay"; }; - rng11: rng@08a8a000 { + rng11: rng@8a8a000 { compatible = "st,rng"; reg = <0x08a8a000 0x1000>; clocks = <&clk_sysin>; @@ -764,7 +784,7 @@ mailbox0: mailbox@8f00000 { compatible = "st,stih407-mailbox"; reg = <0x8f00000 0x1000>; - interrupts = <GIC_SPI 1 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; #mbox-cells = <2>; mbox-name = "a9"; status = "okay"; @@ -794,9 +814,24 @@ status = "okay"; }; - st231_delta: st231-delta@44000000 { + st231_gp0: st231-gp0@0 { compatible = "st,st231-rproc"; - memory-region = <&dmu_reserved>; + reg = <0 0>; + memory-region = <&gp0_reserved>; + resets = <&softreset STIH407_ST231_GP0_SOFTRESET>; + reset-names = "sw_reset"; + clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>; + clock-frequency = <600000000>; + st,syscfg = <&syscfg_core 0x22c>; + #mbox-cells = <1>; + mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; + mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>; + }; + + st231_delta: st231-delta@0 { + compatible = "st,st231-rproc"; + reg = <0 0>; + memory-region = <&delta_reserved>; resets = <&softreset STIH407_ST231_DMU_SOFTRESET>; reset-names = "sw_reset"; clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>; @@ -819,7 +854,7 @@ <&clk_s_c0_flexgen CLK_EXT2F_A9>, <&clk_s_c0_flexgen CLK_EXT2F_A9>, <&clk_s_c0_flexgen CLK_EXT2F_A9>; - interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; dma-channels = <16>; #dma-cells = <3>; }; @@ -837,9 +872,11 @@ <&clk_s_c0_flexgen CLK_TX_ICN_DMU>, <&clk_s_c0_flexgen CLK_EXT2F_A9>; - interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; dma-channels = <16>; #dma-cells = <3>; + + status = "disabled"; }; /* fdma free running */ @@ -850,20 +887,15 @@ <0x8e77000 0x1000>, <0x8e78000 0x8000>; reg-names = "slimcore", "dmem", "peripherals", "imem"; - interrupts = <GIC_SPI 9 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; dma-channels = <16>; #dma-cells = <3>; clocks = <&clk_s_c0_flexgen CLK_FDMA>, <&clk_s_c0_flexgen CLK_EXT2F_A9>, <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, <&clk_s_c0_flexgen CLK_EXT2F_A9>; - }; - sti_sasg_codec: sti-sasg-codec { - compatible = "st,stih407-sas-codec"; - #sound-dai-cells = <1>; status = "disabled"; - st,syscfg = <&syscfg_core>; }; sti_uni_player0: sti-uni-player@8d80000 { @@ -875,7 +907,7 @@ assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>; assigned-clock-rates = <50000000>; reg = <0x8d80000 0x158>; - interrupts = <GIC_SPI 84 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; dmas = <&fdma0 2 0 1>; dma-names = "tx"; @@ -891,7 +923,7 @@ assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>; assigned-clock-rates = <50000000>; reg = <0x8d81000 0x158>; - interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; dmas = <&fdma0 3 0 1>; dma-names = "tx"; @@ -907,7 +939,7 @@ assigned-clock-parents = <0>, <&clk_s_d0_quadfs 2>; assigned-clock-rates = <50000000>; reg = <0x8d82000 0x158>; - interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; dmas = <&fdma0 4 0 1>; dma-names = "tx"; @@ -923,7 +955,7 @@ assigned-clock-parents = <0>, <&clk_s_d0_quadfs 3>; assigned-clock-rates = <50000000>; reg = <0x8d85000 0x158>; - interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; dmas = <&fdma0 7 0 1>; dma-names = "tx"; @@ -935,7 +967,7 @@ #sound-dai-cells = <0>; st,syscfg = <&syscfg_core>; reg = <0x8d83000 0x158>; - interrupts = <GIC_SPI 87 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; dmas = <&fdma0 5 0 1>; dma-names = "rx"; @@ -947,32 +979,22 @@ #sound-dai-cells = <0>; st,syscfg = <&syscfg_core>; reg = <0x8d84000 0x158>; - interrupts = <GIC_SPI 88 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; dmas = <&fdma0 6 0 1>; dma-names = "rx"; status = "disabled"; }; - rc: rc@09518000 { - compatible = "st,comms-irb"; - reg = <0x09518000 0x234>; - interrupts = <GIC_SPI 132 IRQ_TYPE_NONE>; - rx-mode = "infrared"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ir - &pinctrl_uhf - &pinctrl_tx - &pinctrl_tx_od>; - clocks = <&clk_sysin>; - resets = <&softreset STIH407_IRB_SOFTRESET>; - - status = "disabled"; - }; - - socinfo { - compatible = "st,stih407-socinfo"; - st,syscfg = <&syscfg_core>; + delta0@0 { + compatible = "st,st-delta"; + reg = <0 0>; + clock-names = "delta", + "delta-st231", + "delta-flash-promip"; + clocks = <&clk_s_c0_flexgen CLK_VID_DMU>, + <&clk_s_c0_flexgen CLK_ST231_DMU>, + <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; }; }; }; diff --git a/arch/arm/dts/stih407-pinctrl.dtsi b/arch/arm/dts/stih407-pinctrl.dtsi index f27ae21f67..2cf335714c 100644 --- a/arch/arm/dts/stih407-pinctrl.dtsi +++ b/arch/arm/dts/stih407-pinctrl.dtsi @@ -1,10 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 STMicroelectronics Limited. * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. */ #include "st-pincfg.h" #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -45,18 +42,18 @@ }; soc { - pin-controller-sbc { + pin-controller-sbc@961f080 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stih407-sbc-pinctrl"; st,syscfg = <&syscfg_sbc>; reg = <0x0961f080 0x4>; reg-names = "irqmux"; - interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "irqmux"; ranges = <0 0x09610000 0x6000>; - pio0: gpio@09610000 { + pio0: gpio@9610000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -64,7 +61,7 @@ reg = <0x0 0x100>; st,bank-name = "PIO0"; }; - pio1: gpio@09611000 { + pio1: gpio@9611000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -72,7 +69,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO1"; }; - pio2: gpio@09612000 { + pio2: gpio@9612000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -80,7 +77,7 @@ reg = <0x2000 0x100>; st,bank-name = "PIO2"; }; - pio3: gpio@09613000 { + pio3: gpio@9613000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -88,7 +85,7 @@ reg = <0x3000 0x100>; st,bank-name = "PIO3"; }; - pio4: gpio@09614000 { + pio4: gpio@9614000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -97,7 +94,7 @@ st,bank-name = "PIO4"; }; - pio5: gpio@09615000 { + pio5: gpio@9615000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -369,18 +366,18 @@ }; }; - pin-controller-front0 { + pin-controller-front0@920f080 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stih407-front-pinctrl"; st,syscfg = <&syscfg_front>; reg = <0x0920f080 0x4>; reg-names = "irqmux"; - interrupts = <GIC_SPI 189 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "irqmux"; ranges = <0 0x09200000 0x10000>; - pio10: pio@09200000 { + pio10: pio@9200000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -388,7 +385,7 @@ reg = <0x0 0x100>; st,bank-name = "PIO10"; }; - pio11: pio@09201000 { + pio11: pio@9201000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -396,7 +393,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO11"; }; - pio12: pio@09202000 { + pio12: pio@9202000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -404,7 +401,7 @@ reg = <0x2000 0x100>; st,bank-name = "PIO12"; }; - pio13: pio@09203000 { + pio13: pio@9203000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -412,7 +409,7 @@ reg = <0x3000 0x100>; st,bank-name = "PIO13"; }; - pio14: pio@09204000 { + pio14: pio@9204000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -420,7 +417,7 @@ reg = <0x4000 0x100>; st,bank-name = "PIO14"; }; - pio15: pio@09205000 { + pio15: pio@9205000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -428,7 +425,7 @@ reg = <0x5000 0x100>; st,bank-name = "PIO15"; }; - pio16: pio@09206000 { + pio16: pio@9206000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -436,7 +433,7 @@ reg = <0x6000 0x100>; st,bank-name = "PIO16"; }; - pio17: pio@09207000 { + pio17: pio@9207000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -444,7 +441,7 @@ reg = <0x7000 0x100>; st,bank-name = "PIO17"; }; - pio18: pio@09208000 { + pio18: pio@9208000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -452,7 +449,7 @@ reg = <0x8000 0x100>; st,bank-name = "PIO18"; }; - pio19: pio@09209000 { + pio19: pio@9209000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -465,19 +462,16 @@ serial0 { pinctrl_serial0: serial0-0 { st,pins { - tx = <&pio17 0 ALT1 OUT>; - rx = <&pio17 1 ALT1 IN>; + tx = <&pio17 0 ALT1 OUT>; + rx = <&pio17 1 ALT1 IN>; }; }; - pinctrl_serial0_rts: serial0_rts { - st,pins { - rts = <&pio17 3 ALT1 OUT>; - }; - }; - - pinctrl_serial0_cts: serial0_cts { + pinctrl_serial0_hw_flowctrl: serial0-0_hw_flowctrl { st,pins { + tx = <&pio17 0 ALT1 OUT>; + rx = <&pio17 1 ALT1 IN>; cts = <&pio17 2 ALT1 IN>; + rts = <&pio17 3 ALT1 OUT>; }; }; }; @@ -932,18 +926,18 @@ }; }; - pin-controller-front1 { + pin-controller-front1@921f080 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stih407-front-pinctrl"; st,syscfg = <&syscfg_front>; reg = <0x0921f080 0x4>; reg-names = "irqmux"; - interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "irqmux"; ranges = <0 0x09210000 0x10000>; - pio20: pio@09210000 { + pio20: pio@9210000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -965,18 +959,18 @@ }; }; - pin-controller-rear { + pin-controller-rear@922f080 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stih407-rear-pinctrl"; st,syscfg = <&syscfg_rear>; reg = <0x0922f080 0x4>; reg-names = "irqmux"; - interrupts = <GIC_SPI 191 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "irqmux"; ranges = <0 0x09220000 0x6000>; - pio30: gpio@09220000 { + pio30: gpio@9220000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -984,7 +978,7 @@ reg = <0x0 0x100>; st,bank-name = "PIO30"; }; - pio31: gpio@09221000 { + pio31: gpio@9221000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -992,7 +986,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO31"; }; - pio32: gpio@09222000 { + pio32: gpio@9222000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -1000,7 +994,7 @@ reg = <0x2000 0x100>; st,bank-name = "PIO32"; }; - pio33: gpio@09223000 { + pio33: gpio@9223000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -1008,7 +1002,7 @@ reg = <0x3000 0x100>; st,bank-name = "PIO33"; }; - pio34: gpio@09224000 { + pio34: gpio@9224000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -1016,7 +1010,7 @@ reg = <0x4000 0x100>; st,bank-name = "PIO34"; }; - pio35: gpio@09225000 { + pio35: gpio@9225000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -1026,41 +1020,6 @@ st,retime-pin-mask = <0x7f>; }; - dvo { - pinctrl_dvo: dvo { - st,pins { - hs = <&pio30 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - vs = <&pio30 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - de = <&pio30 2 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - ck = <&pio30 3 ALT2 (OE | CLKNOTDATA) 0>; - d0 = <&pio30 4 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d1 = <&pio30 5 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d2 = <&pio30 6 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d3 = <&pio30 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d4 = <&pio31 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d5 = <&pio31 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d6 = <&pio31 2 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d7 = <&pio31 3 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d8 = <&pio31 4 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d9 = <&pio31 5 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d10 = <&pio31 6 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d11 = <&pio31 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d12 = <&pio32 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d13 = <&pio32 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d14 = <&pio32 2 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d15 = <&pio32 3 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d16 = <&pio32 4 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d17 = <&pio32 5 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d18 = <&pio32 6 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d19 = <&pio32 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d20 = <&pio33 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d21 = <&pio33 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d22 = <&pio33 2 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d23 = <&pio33 3 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - i2c4 { pinctrl_i2c4_default: i2c4-default { st,pins { @@ -1195,18 +1154,18 @@ }; }; - pin-controller-flash { + pin-controller-flash@923f080 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stih407-flash-pinctrl"; st,syscfg = <&syscfg_flash>; reg = <0x0923f080 0x4>; reg-names = "irqmux"; - interrupts = <GIC_SPI 192 IRQ_TYPE_NONE>; - interrupts-names = "irqmux"; + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irqmux"; ranges = <0 0x09230000 0x3000>; - pio40: gpio@09230000 { + pio40: gpio@9230000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -1214,7 +1173,7 @@ reg = <0 0x100>; st,bank-name = "PIO40"; }; - pio41: gpio@09231000 { + pio41: gpio@9231000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -1222,7 +1181,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO41"; }; - pio42: gpio@09232000 { + pio42: gpio@9232000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; diff --git a/arch/arm/dts/stih410-b2260-u-boot.dtsi b/arch/arm/dts/stih410-b2260-u-boot.dtsi index 83916319fc..897c42146a 100644 --- a/arch/arm/dts/stih410-b2260-u-boot.dtsi +++ b/arch/arm/dts/stih410-b2260-u-boot.dtsi @@ -9,8 +9,25 @@ soc { st_dwc3: dwc3@8f94000 { dwc3: dwc3@9900000 { + dr_mode = "peripheral"; phys = <&usb2_picophy0>; }; }; + + ohci0: usb@9a03c00 { + compatible = "generic-ohci"; + }; + + ehci0: usb@9a03e00 { + compatible = "generic-ehci"; + }; + + ohci1: usb@9a83c00 { + compatible = "generic-ohci"; + }; + + ehci1: usb@9a83e00 { + compatible = "generic-ehci"; + }; }; }; diff --git a/arch/arm/dts/stih410-b2260.dts b/arch/arm/dts/stih410-b2260.dts index 54250e2518..4fbd8e9eb5 100644 --- a/arch/arm/dts/stih410-b2260.dts +++ b/arch/arm/dts/stih410-b2260.dts @@ -1,10 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2016 STMicroelectronics (R&D) Limited. * Author: Patrice Chotard <patrice.chotard@st.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ /dts-v1/; #include "stih410.dtsi" @@ -15,68 +12,79 @@ compatible = "st,stih410-b2260", "st,stih410"; chosen { - bootargs = "console=ttyAS1,115200"; - linux,stdout-path = &uart1; + bootargs = "clk_ignore_unused"; stdout-path = &uart1; }; - memory { + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x40000000>; }; aliases { - ttyAS1 = &uart1; + serial1 = &uart1; ethernet0 = ðernet0; }; - soc { - - leds { - compatible = "gpio-leds"; - user_green_1 { - label = "User_green_1"; - gpios = <&pio1 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; + leds { + compatible = "gpio-leds"; + user_green_1 { + label = "User_green_1"; + gpios = <&pio1 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; - user_green_2 { - label = "User_green_2"; - gpios = <&pio4 1 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; + user_green_2 { + label = "User_green_2"; + gpios = <&pio4 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; - user_green_3 { - label = "User_green_3"; - gpios = <&pio2 1 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; + user_green_3 { + label = "User_green_3"; + gpios = <&pio2 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; - user_green_4 { - label = "User_green_4"; - gpios = <&pio2 5 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; + user_green_4 { + label = "User_green_4"; + gpios = <&pio2 5 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; - wifi_yellow { - label = "Wifi_yellow"; - gpios = <&pio4 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "wifi-activity"; - default-state = "off"; + sound: sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "STI-B2260"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + simple-audio-card,dai-link@0 { + reg = <0>; + /* DAC */ + format = "i2s"; + mclk-fs = <128>; + cpu { + sound-dai = <&sti_uni_player0>; }; - bt_blue { - label = "Bluetooth_blue"; - gpios = <&pio3 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "hci0-power"; - default-state = "off"; + codec { + sound-dai = <&sti_hdmi>; }; }; + }; + soc { /* Low speed expansion connector */ uart0: serial@9830000 { label = "LS-UART0"; + pinctrl-names = "default", "no-hw-flowctrl"; + pinctrl-0 = <&pinctrl_serial0_hw_flowctrl>; + pinctrl-1 = <&pinctrl_serial0>; + rts-gpios = <&pio17 3 GPIO_ACTIVE_LOW>; + uart-has-rtscts; status = "okay"; }; @@ -119,14 +127,14 @@ status = "okay"; }; - mmc0: sdhci@09060000 { + mmc0: sdhci@9060000 { pinctrl-0 = <&pinctrl_sd0>; bus-width = <4>; status = "okay"; }; /* high speed expansion connector */ - mmc1: sdhci@09080000 { + mmc1: sdhci@9080000 { status = "okay"; }; @@ -138,11 +146,11 @@ status = "okay"; }; - usb2_picophy1: phy2 { + usb2_picophy1: phy2@0 { status = "okay"; }; - usb2_picophy2: phy3 { + usb2_picophy2: phy3@0 { status = "okay"; }; @@ -183,17 +191,17 @@ sti_uni_player0: sti-uni-player@8d80000 { status = "okay"; }; - /* SSC11 to HDMI */ hdmiddc: i2c@9541000 { /* HDMI V1.3a supports Standard mode only */ clock-frequency = <100000>; st,i2c-min-scl-pulse-width-us = <0>; - st,i2c-min-sda-pulse-width-us = <1>; + st,i2c-min-sda-pulse-width-us = <5>; status = "okay"; }; - miphy28lp_phy: miphy28lp@9b22000 { + miphy28lp_phy: miphy28lp@0 { + phy_port1: port@9b2a000 { st,osc-force-ext; }; @@ -202,25 +210,5 @@ sata1: sata@9b28000 { status = "okay"; }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "STI-B2260"; - status = "okay"; - - simple-audio-card,dai-link@0 { - /* DAC */ - format = "i2s"; - mclk-fs = <128>; - cpu { - sound-dai = <&sti_uni_player0>; - }; - - codec { - sound-dai = <&sti_hdmi>; - }; - }; - }; - }; }; diff --git a/arch/arm/dts/stih410-clock.dtsi b/arch/arm/dts/stih410-clock.dtsi index 8598effd6c..81a8c25d7b 100644 --- a/arch/arm/dts/stih410-clock.dtsi +++ b/arch/arm/dts/stih410-clock.dtsi @@ -1,12 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 STMicroelectronics R&D Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include <dt-bindings/clock/stih410-clks.h> / { + /* + * Fixed 30MHz oscillator inputs to SoC + */ + clk_sysin: clk-sysin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <30000000>; + clock-output-names = "CLK_SYSIN"; + }; + + clk_tmdsout_hdmi: clk-tmdsout-hdmi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + clocks { #address-cells = <1>; #size-cells = <1>; @@ -15,27 +28,6 @@ compatible = "st,stih410-clk", "simple-bus"; /* - * Fixed 30MHz oscillator inputs to SoC - */ - clk_sysin: clk-sysin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <30000000>; - clock-output-names = "CLK_SYSIN"; - }; - - /* - * ARM Peripheral clock for timers - */ - arm_periph_clk: clk-m-a9-periphs { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_m_a9>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* * A9 PLL. */ clockgen-a9@92b0000 { @@ -64,35 +56,19 @@ <&clockgen_a9_pll 0>, <&clk_s_c0_flexgen 13>, <&clk_m_a9_ext2f_div2>; + /* + * ARM Peripheral clock for timers + */ + arm_periph_clk: clk-m-a9-periphs { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&clk_m_a9>; + clock-div = <2>; + clock-mult = <1>; + }; }; - /* - * ARM Peripheral clock for timers - */ - clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - - clocks = <&clk_s_c0_flexgen 13>; - - clock-output-names = "clk-m-a9-ext2f-div2"; - - clock-div = <2>; - clock-mult = <1>; - }; - - /* - * Bootloader initialized system infrastructure clock for - * serial devices. - */ - clk_ext2f_a9: clockgen-c0@13 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <200000000>; - clock-output-names = "clk-s-icn-reg-0"; - }; - - clockgen-a@090ff000 { + clockgen-a@90ff000 { compatible = "st,clkgen-c32"; reg = <0x90ff000 0x1000>; @@ -134,7 +110,7 @@ clock-critical = <0>; /* clk-s-c0-fs0-ch0 */ }; - clk_s_c0: clockgen-c@09103000 { + clk_s_c0: clockgen-c@9103000 { compatible = "st,clkgen-c32"; reg = <0x9103000 0x1000>; @@ -208,11 +184,27 @@ "clk-clust-hades", "clk-hwpe-hades", "clk-fc-hades"; - clock-critical = <CLK_ICN_CPU>, + clock-critical = <CLK_PROC_STFE>, + <CLK_ICN_CPU>, <CLK_TX_ICN_DMU>, <CLK_EXT2F_A9>, <CLK_ICN_LMI>, <CLK_ICN_SBC>; + + /* + * ARM Peripheral clock for timers + */ + clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + + clocks = <&clk_s_c0_flexgen 13>; + + clock-output-names = "clk-m-a9-ext2f-div2"; + + clock-div = <2>; + clock-mult = <1>; + }; }; }; @@ -229,7 +221,7 @@ "clk-s-d0-fs0-ch3"; }; - clockgen-d0@09104000 { + clockgen-d0@9104000 { compatible = "st,clkgen-c32"; reg = <0x9104000 0x1000>; @@ -265,13 +257,7 @@ "clk-s-d2-fs0-ch3"; }; - clk_tmdsout_hdmi: clk-tmdsout-hdmi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clockgen-d2@x9106000 { + clockgen-d2@9106000 { compatible = "st,clkgen-c32"; reg = <0x9106000 0x1000>; diff --git a/arch/arm/dts/stih410-pinctrl.dtsi b/arch/arm/dts/stih410-pinctrl.dtsi index b3e9dfc81c..e6eadd1244 100644 --- a/arch/arm/dts/stih410-pinctrl.dtsi +++ b/arch/arm/dts/stih410-pinctrl.dtsi @@ -1,16 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 STMicroelectronics Limited. * Author: Peter Griffin <peter.griffin@linaro.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. */ #include "st-pincfg.h" / { soc { - pin-controller-rear { + pin-controller-rear@922f080 { usb0 { pinctrl_usb0: usb2-0 { diff --git a/arch/arm/dts/stih410.dtsi b/arch/arm/dts/stih410.dtsi index b59b110989..6d847019c5 100644 --- a/arch/arm/dts/stih410.dtsi +++ b/arch/arm/dts/stih410.dtsi @@ -1,67 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 STMicroelectronics Limited. * Author: Peter Griffin <peter.griffin@linaro.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. */ #include "stih410-clock.dtsi" #include "stih407-family.dtsi" #include "stih410-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> / { aliases { bdisp0 = &bdisp0; }; - cpus { - cpu@0 { - st,syscfg = <&syscfg_core 0x8e0>; - st,syscfg-eng = <&syscfg_opp 0x4 0x0>; - clocks = <&clk_m_a9>; - operating-points-v2 = <&cpu0_opp_table>; - }; - cpu@1 { - clocks = <&clk_m_a9>; - operating-points-v2 = <&cpu0_opp_table>; - }; - }; - - cpu0_opp_table: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp@1500000000 { - opp-supported-hw = <0xffffffff 0xffffffff 0xffffffff>; - opp-hz = /bits/ 64 <1500000000>; - clock-latency-ns = <10000000>; - opp-suspend; - }; - opp@1200000000 { - opp-supported-hw = <0xffffffff 0xffffffff 0xffffffff>; - opp-hz = /bits/ 64 <1200000000>; - clock-latency-ns = <10000000>; - }; - opp@800000000 { - opp-supported-hw = <0xffffffff 0xffffffff 0xffffffff>; - opp-hz = /bits/ 64 <800000000>; - clock-latency-ns = <10000000>; - }; - opp@400000000 { - opp-supported-hw = <0xffffffff 0xffffffff 0xffffffff>; - opp-hz = /bits/ 64 <400000000>; - clock-latency-ns = <10000000>; - }; - }; - soc { - syscfg_opp: @08a6583c { - compatible = "syscon"; - reg = <0x08a6583c 0x8>; - }; - - usb2_picophy1: phy2 { + usb2_picophy1: phy2@0 { compatible = "st,stih407-usb2-phy"; + reg = <0 0>; #phy-cells = <0>; st,syscfg = <&syscfg_core 0xf8 0xf4>; resets = <&softreset STIH407_PICOPHY_SOFTRESET>, @@ -71,8 +25,9 @@ status = "disabled"; }; - usb2_picophy2: phy3 { + usb2_picophy2: phy3@0 { compatible = "st,stih407-usb2-phy"; + reg = <0 0>; #phy-cells = <0>; st,syscfg = <&syscfg_core 0xfc 0xf4>; resets = <&softreset STIH407_PICOPHY_SOFTRESET>, @@ -83,15 +38,14 @@ }; ohci0: usb@9a03c00 { - compatible = "generic-ohci"; + compatible = "st,st-ohci-300x"; reg = <0x9a03c00 0x100>; - interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, <&softreset STIH407_USB2_PORT0_SOFTRESET>; reset-names = "power", "softreset"; - phys = <&usb2_picophy1>; phy-names = "usb"; @@ -99,9 +53,9 @@ }; ehci0: usb@9a03e00 { - compatible = "generic-ehci"; + compatible = "st,st-ehci-300x"; reg = <0x9a03e00 0x100>; - interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>; clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, @@ -116,15 +70,14 @@ }; ohci1: usb@9a83c00 { - compatible = "generic-ohci"; + compatible = "st,st-ohci-300x"; reg = <0x9a83c00 0x100>; - interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, <&softreset STIH407_USB2_PORT1_SOFTRESET>; reset-names = "power", "softreset"; - phys = <&usb2_picophy2>; phy-names = "usb"; @@ -132,9 +85,9 @@ }; ehci1: usb@9a83e00 { - compatible = "generic-ehci"; + compatible = "st,st-ehci-300x"; reg = <0x9a83e00 0x100>; - interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, @@ -142,18 +95,18 @@ resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, <&softreset STIH407_USB2_PORT1_SOFTRESET>; reset-names = "power", "softreset"; - phys = <&usb2_picophy2>; phy-names = "usb"; status = "disabled"; }; - sti-display-subsystem { + sti-display-subsystem@0 { compatible = "st,sti-display-subsystem"; #address-cells = <1>; #size-cells = <1>; + reg = <0 0>; assigned-clocks = <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>, <&clk_s_c0_pll1 0>, @@ -243,10 +196,10 @@ sti_hdmi: sti-hdmi@8d04000 { compatible = "st,stih407-hdmi"; - #sound-dai-cells = <0>; reg = <0x8d04000 0x1000>; reg-names = "hdmi-reg"; - interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>; + #sound-dai-cells = <0>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "irq"; clock-names = "pix", "tmds", @@ -262,7 +215,7 @@ <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>; - hdmi,hpd-gpio = <&pio5 3>; + hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>; reset-names = "hdmi"; resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>; ddc = <&hdmiddc>; @@ -283,24 +236,7 @@ <&clk_s_d2_quadfs 1>; }; - sti-dvo@8d00400 { - compatible = "st,stih407-dvo"; - status = "disabled"; - reg = <0x8d00400 0x200>; - reg-names = "dvo-reg"; - clock-names = "dvo_pix", - "dvo", - "main_parent", - "aux_parent"; - clocks = <&clk_s_d2_flexgen CLK_PIX_DVO>, - <&clk_s_d2_flexgen CLK_DVO>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dvo>; - }; - - sti-hqvdp@9c000000 { + sti-hqvdp@9c00000 { compatible = "st,stih407-hqvdp"; reg = <0x9C00000 0x100000>; clock-names = "hqvdp", "pix_main"; @@ -315,7 +251,7 @@ bdisp0:bdisp@9f10000 { compatible = "st,stih407-bdisp"; reg = <0x9f10000 0x1000>; - interrupts = <GIC_SPI 38 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; clock-names = "bdisp"; clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>; }; @@ -324,8 +260,8 @@ compatible = "st,st-hva"; reg = <0x8c85000 0x400>, <0x6000000 0x40000>; reg-names = "hva_registers", "hva_esram"; - interrupts = <GIC_SPI 58 IRQ_TYPE_NONE>, - <GIC_SPI 59 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_hva"; clocks = <&clk_s_c0_flexgen CLK_HVA>; }; @@ -338,66 +274,7 @@ interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>; }; - g1@8c80000 { - compatible = "st,g1"; - reg = <0x8c80000 0x194>; - interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>; - }; - - temp0{ - compatible = "st,stih407-thermal"; - reg = <0x91a0000 0x28>; - clock-names = "thermal"; - clocks = <&clk_sysin>; - interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>; - }; - - delta0 { - compatible = "st,delta"; - clock-names = "delta", "delta-st231", "delta-flash-promip"; - clocks = <&clk_s_c0_flexgen CLK_VID_DMU>, - <&clk_s_c0_flexgen CLK_ST231_DMU>, - <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; - }; - - h264pp0: h264pp@8c00000 { - compatible = "st,h264pp"; - reg = <0x8c00000 0x20000>; - interrupts = <GIC_SPI 53 IRQ_TYPE_NONE>; - clock-names = "clk_h264pp_0"; - clocks = <&clk_s_c0_flexgen CLK_PP_DMU>; - }; - - mali: mali@09f00000 { - compatible = "arm,mali-400"; - reg = <0x09f00000 0x10000>; - interrupts = <GIC_SPI 49 IRQ_TYPE_NONE>, - <GIC_SPI 50 IRQ_TYPE_NONE>, - <GIC_SPI 41 IRQ_TYPE_NONE>, - <GIC_SPI 45 IRQ_TYPE_NONE>, - <GIC_SPI 42 IRQ_TYPE_NONE>, - <GIC_SPI 46 IRQ_TYPE_NONE>, - <GIC_SPI 43 IRQ_TYPE_NONE>, - <GIC_SPI 47 IRQ_TYPE_NONE>, - <GIC_SPI 44 IRQ_TYPE_NONE>, - <GIC_SPI 48 IRQ_TYPE_NONE>; - interrupt-names = "IRQGP", - "IRQGPMMU", - "IRQPP0", - "IRQPPMMU0", - "IRQPP1", - "IRQPPMMU1", - "IRQPP2", - "IRQPPMMU2", - "IRQPP3", - "IRQPPMMU3"; - clock-names = "gpu-clk"; - clocks = <&clk_s_c0_flexgen CLK_ICN_GPU>; - reset-names = "gpu"; - resets = <&softreset STIH407_GPU_SOFTRESET>; - }; - - delta0 { + delta0@0 { compatible = "st,st-delta"; clock-names = "delta", "delta-st231", @@ -407,51 +284,17 @@ <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; }; - h264pp0: h264pp@8c00000 { - compatible = "st,h264pp"; - reg = <0x8c00000 0x20000>; - interrupts = <GIC_SPI 53 IRQ_TYPE_NONE>; - clock-names = "clk_h264pp_0"; - clocks = <&clk_s_c0_flexgen CLK_PP_DMU>; - }; - - mali: mali@09f00000 { - compatible = "arm,mali-400"; - reg = <0x09f00000 0x10000>; - interrupts = <GIC_SPI 49 IRQ_TYPE_NONE>, - <GIC_SPI 50 IRQ_TYPE_NONE>, - <GIC_SPI 41 IRQ_TYPE_NONE>, - <GIC_SPI 45 IRQ_TYPE_NONE>, - <GIC_SPI 42 IRQ_TYPE_NONE>, - <GIC_SPI 46 IRQ_TYPE_NONE>, - <GIC_SPI 43 IRQ_TYPE_NONE>, - <GIC_SPI 47 IRQ_TYPE_NONE>, - <GIC_SPI 44 IRQ_TYPE_NONE>, - <GIC_SPI 48 IRQ_TYPE_NONE>; - interrupt-names = "IRQGP", - "IRQGPMMU", - "IRQPP0", - "IRQPPMMU0", - "IRQPP1", - "IRQPPMMU1", - "IRQPP2", - "IRQPPMMU2", - "IRQPP3", - "IRQPPMMU3"; - clock-names = "gpu-clk"; - clocks = <&clk_s_c0_flexgen CLK_ICN_GPU>; - reset-names = "gpu"; - resets = <&softreset STIH407_GPU_SOFTRESET>; - }; - - hva@8c85000{ - compatible = "st,st-hva"; - reg = <0x8c85000 0x400>, <0x6000000 0x40000>; - reg-names = "hva_registers", "hva_esram"; - interrupts = <GIC_SPI 58 IRQ_TYPE_NONE>, - <GIC_SPI 59 IRQ_TYPE_NONE>; - clock-names = "clk_hva"; - clocks = <&clk_s_c0_flexgen CLK_HVA>; + sti-cec@94a087c { + compatible = "st,stih-cec"; + reg = <0x94a087c 0x64>; + clocks = <&clk_sysin>; + clock-names = "cec-clk"; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cec-irq"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cec0_default>; + resets = <&softreset STIH407_LPM_SOFTRESET>; + hdmi-phandle = <&sti_hdmi>; }; }; }; diff --git a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi index dc30360b0a..11e8f2bef6 100644 --- a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi +++ b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi @@ -16,7 +16,7 @@ * address mapping : RBC * Tc > + 85C : N */ -#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.44" +#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.45" #define DDR_MEM_SPEED 533000 #define DDR_MEM_SIZE 0x20000000 @@ -89,7 +89,7 @@ #define DDR_PTR2 0x042DA068 #define DDR_ACIOCR 0x10400812 #define DDR_DXCCR 0x00000C40 -#define DDR_DSGCR 0xF200001F +#define DDR_DSGCR 0xF200011F #define DDR_DCR 0x0000000B #define DDR_DTPR0 0x38D488D0 #define DDR_DTPR1 0x098B00D8 diff --git a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi index 8158a56f13..4b70b60554 100644 --- a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi +++ b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi @@ -16,8 +16,7 @@ * address mapping : RBC * Tc > + 85C : N */ - -#define DDR_MEM_NAME "DDR3-1066/888 bin G 2x4Gb 533MHz v1.44" +#define DDR_MEM_NAME "DDR3-1066/888 bin G 2x4Gb 533MHz v1.45" #define DDR_MEM_SPEED 533000 #define DDR_MEM_SIZE 0x40000000 @@ -90,7 +89,7 @@ #define DDR_PTR2 0x042DA068 #define DDR_ACIOCR 0x10400812 #define DDR_DXCCR 0x00000C40 -#define DDR_DSGCR 0xF200001F +#define DDR_DSGCR 0xF200011F #define DDR_DCR 0x0000000B #define DDR_DTPR0 0x38D488D0 #define DDR_DTPR1 0x098B00D8 diff --git a/arch/arm/dts/stm32mp157-pinctrl.dtsi b/arch/arm/dts/stm32mp157-pinctrl.dtsi index 9bae85045a..4367e8dcf7 100644 --- a/arch/arm/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp157-pinctrl.dtsi @@ -25,8 +25,7 @@ reg = <0x0 0x400>; clocks = <&rcc GPIOA>; st,bank-name = "GPIOA"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 0 16>; + status = "disabled"; }; gpiob: gpio@50003000 { @@ -37,8 +36,7 @@ reg = <0x1000 0x400>; clocks = <&rcc GPIOB>; st,bank-name = "GPIOB"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 16 16>; + status = "disabled"; }; gpioc: gpio@50004000 { @@ -49,8 +47,7 @@ reg = <0x2000 0x400>; clocks = <&rcc GPIOC>; st,bank-name = "GPIOC"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 32 16>; + status = "disabled"; }; gpiod: gpio@50005000 { @@ -61,8 +58,7 @@ reg = <0x3000 0x400>; clocks = <&rcc GPIOD>; st,bank-name = "GPIOD"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 48 16>; + status = "disabled"; }; gpioe: gpio@50006000 { @@ -73,8 +69,7 @@ reg = <0x4000 0x400>; clocks = <&rcc GPIOE>; st,bank-name = "GPIOE"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 64 16>; + status = "disabled"; }; gpiof: gpio@50007000 { @@ -85,8 +80,7 @@ reg = <0x5000 0x400>; clocks = <&rcc GPIOF>; st,bank-name = "GPIOF"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 80 16>; + status = "disabled"; }; gpiog: gpio@50008000 { @@ -97,8 +91,7 @@ reg = <0x6000 0x400>; clocks = <&rcc GPIOG>; st,bank-name = "GPIOG"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 96 16>; + status = "disabled"; }; gpioh: gpio@50009000 { @@ -109,8 +102,7 @@ reg = <0x7000 0x400>; clocks = <&rcc GPIOH>; st,bank-name = "GPIOH"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 112 16>; + status = "disabled"; }; gpioi: gpio@5000a000 { @@ -121,8 +113,7 @@ reg = <0x8000 0x400>; clocks = <&rcc GPIOI>; st,bank-name = "GPIOI"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 128 16>; + status = "disabled"; }; gpioj: gpio@5000b000 { @@ -133,8 +124,7 @@ reg = <0x9000 0x400>; clocks = <&rcc GPIOJ>; st,bank-name = "GPIOJ"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 144 16>; + status = "disabled"; }; gpiok: gpio@5000c000 { @@ -145,8 +135,7 @@ reg = <0xa000 0x400>; clocks = <&rcc GPIOK>; st,bank-name = "GPIOK"; - ngpios = <8>; - gpio-ranges = <&pinctrl 0 160 8>; + status = "disabled"; }; adc12_usb_pwr_pins_a: adc12-usb-pwr-pins-0 { @@ -186,6 +175,47 @@ }; }; + dcmi_pins_a: dcmi-0 { + pins { + pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */ + <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */ + <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */ + <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */ + <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */ + <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */ + <STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */ + <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */ + <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */ + <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */ + <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */ + <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */ + <STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */ + <STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */ + <STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */ + bias-disable; + }; + }; + + dcmi_sleep_pins_a: dcmi-sleep-0 { + pins { + pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */ + <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */ + <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */ + <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */ + <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */ + <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */ + <STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */ + <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */ + <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */ + <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */ + <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */ + <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */ + <STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */ + <STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */ + <STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */ + }; + }; + ethernet0_rgmii_pins_a: rgmii-0 { pins1 { pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ @@ -308,6 +338,13 @@ }; }; + i2c1_pins_sleep_b: i2c1-3 { + pins { + pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */ + <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */ + }; + }; + i2c2_pins_a: i2c2-0 { pins { pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */ @@ -325,16 +362,21 @@ }; }; - i2c2_pins_b: i2c2-2 { + i2c2_pins_b1: i2c2-2 { pins { - pinmux = <STM32_PINMUX('Z', 0, AF3)>, /* I2C2_SCL */ - <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ + pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ bias-disable; drive-open-drain; slew-rate = <0>; }; }; + i2c2_pins_sleep_b1: i2c2-3 { + pins { + pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ + }; + }; + i2c5_pins_a: i2c5-0 { pins { pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */ @@ -353,6 +395,25 @@ }; }; + i2s2_pins_a: i2s2-0 { + pins { + pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */ + <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */ + <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + }; + + i2s2_pins_sleep_a: i2s2-1 { + pins { + pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */ + <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */ + <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */ + }; + }; + ltdc_pins_a: ltdc-a-0 { pins { pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */ @@ -547,6 +608,12 @@ }; }; + qspi_clk_sleep_pins_a: qspi-clk-sleep-0 { + pins { + pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */ + }; + }; + qspi_bk1_pins_a: qspi-bk1-0 { pins1 { pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */ @@ -565,6 +632,16 @@ }; }; + qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { + pins { + pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */ + <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */ + <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */ + <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */ + <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */ + }; + }; + qspi_bk2_pins_a: qspi-bk2-0 { pins1 { pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */ @@ -583,6 +660,89 @@ }; }; + qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 { + pins { + pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */ + <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */ + <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */ + <STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */ + <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */ + }; + }; + + sai2a_pins_a: sai2a-0 { + pins { + pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */ + <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */ + <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */ + <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */ + slew-rate = <0>; + drive-push-pull; + bias-disable; + }; + }; + + sai2a_sleep_pins_a: sai2a-1 { + pins { + pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */ + <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */ + <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */ + <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */ + }; + }; + + sai2b_pins_a: sai2b-0 { + pins1 { + pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */ + <STM32_PINMUX('E', 13, AF10)>, /* SAI2_FS_B */ + <STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */ + slew-rate = <0>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ + bias-disable; + }; + }; + + sai2b_sleep_pins_a: sai2b-1 { + pins { + pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */ + <STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */ + <STM32_PINMUX('E', 13, ANALOG)>, /* SAI2_FS_B */ + <STM32_PINMUX('E', 14, ANALOG)>; /* SAI2_MCLK_B */ + }; + }; + + sai2b_pins_b: sai2b-2 { + pins { + pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ + bias-disable; + }; + }; + + sai2b_sleep_pins_b: sai2b-3 { + pins { + pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */ + }; + }; + + sai4a_pins_a: sai4a-0 { + pins { + pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */ + slew-rate = <0>; + drive-push-pull; + bias-disable; + }; + }; + + sai4a_sleep_pins_a: sai4a-1 { + pins { + pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */ + }; + }; + sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins { pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ @@ -752,12 +912,6 @@ bias-disable; }; }; - - usbotg_hs_pins_a: usbotg_hs-0 { - pins { - pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */ - }; - }; }; pinctrl_z: pin-controller-z@54004000 { @@ -779,8 +933,22 @@ clocks = <&rcc GPIOZ>; st,bank-name = "GPIOZ"; st,bank-ioport = <11>; - ngpios = <8>; - gpio-ranges = <&pinctrl_z 0 400 8>; + status = "disabled"; + }; + + i2c2_pins_b2: i2c2-0 { + pins { + pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c2_pins_sleep_b2: i2c2-1 { + pins { + pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */ + }; }; i2c4_pins_a: i2c4-0 { diff --git a/arch/arm/dts/stm32mp157-u-boot.dtsi b/arch/arm/dts/stm32mp157-u-boot.dtsi index 8102ce20d0..0d1d387e54 100644 --- a/arch/arm/dts/stm32mp157-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157-u-boot.dtsi @@ -25,6 +25,11 @@ u-boot,dm-pre-reloc; }; + /* need PSCI for sysreset during board_f */ + psci { + u-boot,dm-pre-proper; + }; + reboot { u-boot,dm-pre-reloc; }; @@ -106,6 +111,15 @@ u-boot,dm-pre-reloc; }; +&iwdg2 { + u-boot,dm-pre-reloc; +}; + +/* pre-reloc probe = reserve video frame buffer in video_reserve() */ +<dc { + u-boot,dm-pre-proper; +}; + &pinctrl { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index dd0859769b..5b15a4a915 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -1,8 +1,5 @@ // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) /* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics. - * * Copyright (C) Linaro Ltd 2019 - All Rights Reserved * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> */ @@ -10,17 +7,19 @@ /dts-v1/; #include "stm32mp157c.dtsi" -#include "stm32mp157-pinctrl.dtsi" +#include "stm32mp157xac-pinctrl.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/mfd/st,stpmic1.h> / { model = "Arrow Electronics STM32MP157A Avenger96 board"; - compatible = "st,stm32mp157a-avenger96", "st,stm32mp157"; + compatible = "arrow,stm32mp157a-avenger96", "st,stm32mp157"; aliases { ethernet0 = ðernet0; + mmc0 = &sdmmc1; serial0 = &uart4; + serial1 = &uart7; }; chosen { @@ -28,6 +27,7 @@ }; memory@c0000000 { + device_type = "memory"; reg = <0xc0000000 0x40000000>; }; @@ -109,7 +109,7 @@ &i2c2 { pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_b>; + pinctrl-0 = <&i2c2_pins_b1 &i2c2_pins_b2>; i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; status = "okay"; @@ -151,10 +151,10 @@ vddcore: buck1 { regulator-name = "vddcore"; - regulator-min-microvolt = <800000>; + regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1350000>; regulator-always-on; - regulator-initial-mode = <2>; + regulator-initial-mode = <0>; regulator-over-current-protection; }; @@ -163,17 +163,17 @@ regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; regulator-always-on; - regulator-initial-mode = <2>; + regulator-initial-mode = <0>; regulator-over-current-protection; }; vdd: buck3 { regulator-name = "vdd"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-always-on; st,mask_reset; - regulator-initial-mode = <8>; + regulator-initial-mode = <0>; regulator-over-current-protection; }; @@ -183,7 +183,7 @@ regulator-max-microvolt = <3300000>; regulator-always-on; regulator-over-current-protection; - regulator-initial-mode = <8>; + regulator-initial-mode = <0>; }; vdda: ldo1 { @@ -204,8 +204,8 @@ vtt_ddr: ldo3 { regulator-name = "vtt_ddr"; - regulator-min-microvolt = <0000000>; - regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; regulator-always-on; regulator-over-current-protection; }; @@ -233,6 +233,7 @@ regulator-max-microvolt = <1800000>; interrupts = <IT_CURLIM_LDO6 0>; interrupt-parent = <&pmic>; + regulator-enable-ramp-delay = <300000>; }; vref_ddr: vref_ddr { @@ -282,7 +283,10 @@ }; &pwr { - pwr-supply = <&vdd>; + pwr-regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; + }; }; &rng1 { @@ -294,8 +298,10 @@ }; &sdmmc1 { - pinctrl-names = "default"; + pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; broken-cd; st,sig-dir; st,neg-edge; @@ -325,12 +331,16 @@ }; &uart4 { + /* On Low speed expansion header */ + label = "LS-UART1"; pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_b>; status = "okay"; }; &uart7 { + /* On Low speed expansion header */ + label = "LS-UART0"; pinctrl-names = "default"; pinctrl-0 = <&uart7_pins_a>; status = "okay"; diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi index 36c852d28b..dcaab3eef2 100644 --- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi @@ -17,6 +17,8 @@ u-boot,boot-led = "heartbeat"; u-boot,error-led = "error"; st,adc_usb_pd = <&adc1 18>, <&adc1 19>; + st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; }; led { red { @@ -187,6 +189,8 @@ }; pins2 { u-boot,dm-pre-reloc; + /* pull-up on rx to avoid floating level */ + bias-pull-up; }; }; diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts index adb2464920..c210acc0aa 100644 --- a/arch/arm/dts/stm32mp157a-dk1.dts +++ b/arch/arm/dts/stm32mp157a-dk1.dts @@ -7,7 +7,7 @@ /dts-v1/; #include "stm32mp157c.dtsi" -#include "stm32mp157-pinctrl.dtsi" +#include "stm32mp157xac-pinctrl.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/mfd/st,stpmic1.h> @@ -28,6 +28,17 @@ reg = <0xc0000000 0x20000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpu_reserved: gpu@d4000000 { + reg = <0xd4000000 0x4000000>; + no-map; + }; + }; + led { compatible = "gpio-leds"; blue { @@ -65,6 +76,47 @@ }; }; +&gpu { + contiguous-area = <&gpu_reserved>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_a>; + pinctrl-1 = <&i2c1_pins_sleep_a>; + i2c-scl-rising-time-ns = <100>; + i2c-scl-falling-time-ns = <7>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + hdmi-transmitter@39 { + compatible = "sil,sii9022"; + reg = <0x39>; + iovcc-supply = <&v3v3_hdmi>; + cvcc12-supply = <&v1v2_hdmi>; + reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpiog>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <<dc_pins_a>; + pinctrl-1 = <<dc_pins_sleep_a>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + sii9022_in: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + }; + }; +}; &i2c4 { pinctrl-names = "default"; @@ -241,8 +293,31 @@ status = "okay"; }; +<dc { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + ltdc_ep0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&sii9022_in>; + }; + }; +}; + +&m4_rproc { + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; + mbox-names = "vq0", "vq1", "shutdown"; + status = "okay"; +}; + &pwr { - pwr-supply = <&vdd>; + pwr-regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; + }; }; &rng1 { diff --git a/arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi b/arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi index 06ef3a4095..18ac1e3cb2 100644 --- a/arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi @@ -4,3 +4,9 @@ */ #include "stm32mp157a-dk1-u-boot.dtsi" + +&i2c1 { + hdmi-transmitter@39 { + reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>; + }; +}; diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi index 200601edff..4953a0db55 100644 --- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi @@ -15,31 +15,22 @@ }; config { + u-boot,boot-led = "heartbeat"; + u-boot,error-led = "error"; st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; }; led { - compatible = "gpio-leds"; - red { - label = "stm32mp:red:status"; + label = "error"; gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; default-state = "off"; + status = "okay"; }; - green { - label = "stm32mp:green:user"; - gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - orange { - label = "stm32mp:orange:status"; - gpios = <&gpioh 7 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; + blue { - label = "stm32mp:blue:user"; - gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>; + default-state = "on"; }; }; }; @@ -206,5 +197,7 @@ }; pins2 { u-boot,dm-pre-reloc; + /* pull-up on rx to avoid floating level */ + bias-pull-up; }; }; diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index 11981d6dd4..1d9cc734f1 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -6,7 +6,7 @@ /dts-v1/; #include "stm32mp157c.dtsi" -#include "stm32mp157-pinctrl.dtsi" +#include "stm32mp157xaa-pinctrl.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/mfd/st,stpmic1.h> @@ -23,6 +23,17 @@ reg = <0xC0000000 0x40000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpu_reserved: gpu@e8000000 { + reg = <0xe8000000 0x8000000>; + no-map; + }; + }; + aliases { serial0 = &uart4; }; @@ -45,6 +56,11 @@ status = "okay"; }; +&gpu { + contiguous-area = <&gpu_reserved>; + status = "okay"; +}; + &i2c4 { pinctrl-names = "default"; pinctrl-0 = <&i2c4_pins_a>; @@ -201,8 +217,17 @@ status = "okay"; }; +&m4_rproc { + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; + mbox-names = "vq0", "vq1", "shutdown"; + status = "okay"; +}; + &pwr { - pwr-supply = <&vdd>; + pwr-regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; + }; }; &rng1 { diff --git a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi index b656eb120d..ec60486f41 100644 --- a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi @@ -17,14 +17,9 @@ }; &flash0 { - compatible = "jedec,spi-nor"; u-boot,dm-spl; }; -&flash1 { - compatible = "jedec,spi-nor"; -}; - &qspi { u-boot,dm-spl; }; diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts index ca2a333d43..23de232831 100644 --- a/arch/arm/dts/stm32mp157c-ev1.dts +++ b/arch/arm/dts/stm32mp157c-ev1.dts @@ -7,6 +7,7 @@ #include "stm32mp157c-ed1.dts" #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> / { model = "STMicroelectronics STM32MP157C eval daughter on eval mother"; @@ -21,6 +22,51 @@ ethernet0 = ðernet0; }; + clocks { + clk_ext_camera: clk-ext-camera { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + }; + + joystick { + compatible = "gpio-keys"; + #size-cells = <0>; + pinctrl-0 = <&joystick_pins>; + pinctrl-names = "default"; + button-0 { + label = "JoySel"; + linux,code = <KEY_ENTER>; + interrupt-parent = <&stmfx_pinctrl>; + interrupts = <0 IRQ_TYPE_EDGE_RISING>; + }; + button-1 { + label = "JoyDown"; + linux,code = <KEY_DOWN>; + interrupt-parent = <&stmfx_pinctrl>; + interrupts = <1 IRQ_TYPE_EDGE_RISING>; + }; + button-2 { + label = "JoyLeft"; + linux,code = <KEY_LEFT>; + interrupt-parent = <&stmfx_pinctrl>; + interrupts = <2 IRQ_TYPE_EDGE_RISING>; + }; + button-3 { + label = "JoyRight"; + linux,code = <KEY_RIGHT>; + interrupt-parent = <&stmfx_pinctrl>; + interrupts = <3 IRQ_TYPE_EDGE_RISING>; + }; + button-4 { + label = "JoyUp"; + linux,code = <KEY_UP>; + interrupt-parent = <&stmfx_pinctrl>; + interrupts = <4 IRQ_TYPE_EDGE_RISING>; + }; + }; + panel_backlight: panel-backlight { compatible = "gpio-backlight"; gpios = <&gpiod 13 GPIO_ACTIVE_LOW>; @@ -35,6 +81,23 @@ status = "okay"; }; +&dcmi { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&dcmi_pins_a>; + pinctrl-1 = <&dcmi_sleep_pins_a>; + + port { + dcmi_0: endpoint { + remote-endpoint = <&ov5640_0>; + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <1>; + }; + }; +}; + &dsi { #address-cells = <1>; #size-cells = <0>; @@ -64,6 +127,7 @@ reg = <0>; reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>; backlight = <&panel_backlight>; + power-supply = <&v3v3>; status = "okay"; port { @@ -116,6 +180,31 @@ i2c-scl-falling-time-ns = <20>; status = "okay"; + ov5640: camera@3c { + compatible = "ovti,ov5640"; + pinctrl-names = "default"; + pinctrl-0 = <&ov5640_pins>; + reg = <0x3c>; + clocks = <&clk_ext_camera>; + clock-names = "xclk"; + DOVDD-supply = <&v2v8>; + powerdown-gpios = <&stmfx_pinctrl 18 GPIO_ACTIVE_HIGH>; + reset-gpios = <&stmfx_pinctrl 19 GPIO_ACTIVE_LOW>; + rotation = <180>; + status = "okay"; + + port { + ov5640_0: endpoint { + remote-endpoint = <&dcmi_0>; + bus-width = <8>; + data-shift = <2>; /* lines 9:2 are used */ + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <1>; + }; + }; + }; + stmfx: stmfx@42 { compatible = "st,stmfx-0300"; reg = <0x42>; @@ -130,7 +219,18 @@ interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&stmfx_pinctrl 0 0 24>; - status = "disabled"; + + joystick_pins: joystick { + pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4"; + drive-push-pull; + bias-pull-down; + }; + + ov5640_pins: camera { + pins = "agpio2", "agpio3"; /* stmfx pins 18 & 19 */ + drive-push-pull; + output-low; + }; }; }; }; @@ -165,14 +265,16 @@ }; &qspi { - pinctrl-names = "default"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>; reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; #address-cells = <1>; #size-cells = <0>; status = "okay"; flash0: mx66l51235l@0 { + compatible = "jedec,spi-nor"; reg = <0>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; @@ -181,6 +283,7 @@ }; flash1: mx66l51235l@1 { + compatible = "jedec,spi-nor"; reg = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; @@ -245,8 +348,6 @@ }; &usbotg_hs { - pinctrl-names = "default"; - pinctrl-0 = <&usbotg_hs_pins_a>; dr_mode = "peripheral"; phys = <&usbphyc_port1 0>; phy-names = "usb2-phy"; diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi index d15fba0c80..a6045dd682 100644 --- a/arch/arm/dts/stm32mp157c.dtsi +++ b/arch/arm/dts/stm32mp157c.dtsi @@ -372,6 +372,17 @@ status = "disabled"; }; + i2s2: audio-controller@4000b000 { + compatible = "st,stm32h7-i2s"; + #sound-dai-cells = <0>; + reg = <0x4000b000 0x400>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 39 0x400 0x01>, + <&dmamux1 40 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + spi3: spi@4000c000 { #address-cells = <1>; #size-cells = <0>; @@ -386,6 +397,17 @@ status = "disabled"; }; + i2s3: audio-controller@4000c000 { + compatible = "st,stm32h7-i2s"; + #sound-dai-cells = <0>; + reg = <0x4000c000 0x400>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 61 0x400 0x01>, + <&dmamux1 62 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + spdifrx: audio-controller@4000d000 { compatible = "st,stm32h7-spdifrx"; #sound-dai-cells = <0>; @@ -614,6 +636,17 @@ status = "disabled"; }; + i2s1: audio-controller@44004000 { + compatible = "st,stm32h7-i2s"; + #sound-dai-cells = <0>; + reg = <0x44004000 0x400>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 37 0x400 0x01>, + <&dmamux1 38 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + spi4: spi@44005000 { #address-cells = <1>; #size-cells = <0>; @@ -715,6 +748,100 @@ status = "disabled"; }; + sai1: sai@4400a000 { + compatible = "st,stm32h7-sai"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4400a000 0x400>; + reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rcc SAI1_R>; + status = "disabled"; + + sai1a: audio-controller@4400a004 { + #sound-dai-cells = <0>; + + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x1c>; + clocks = <&rcc SAI1_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 87 0x400 0x01>; + status = "disabled"; + }; + + sai1b: audio-controller@4400a024 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x1c>; + clocks = <&rcc SAI1_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 88 0x400 0x01>; + status = "disabled"; + }; + }; + + sai2: sai@4400b000 { + compatible = "st,stm32h7-sai"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4400b000 0x400>; + reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rcc SAI2_R>; + status = "disabled"; + + sai2a: audio-controller@4400b004 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x1c>; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 89 0x400 0x01>; + status = "disabled"; + }; + + sai2b: audio-controller@4400b024 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x1c>; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 90 0x400 0x01>; + status = "disabled"; + }; + }; + + sai3: sai@4400c000 { + compatible = "st,stm32h7-sai"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4400c000 0x400>; + reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rcc SAI3_R>; + status = "disabled"; + + sai3a: audio-controller@4400c004 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-a"; + reg = <0x04 0x1c>; + clocks = <&rcc SAI3_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 113 0x400 0x01>; + status = "disabled"; + }; + + sai3b: audio-controller@4400c024 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x1c>; + clocks = <&rcc SAI3_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 114 0x400 0x01>; + status = "disabled"; + }; + }; + dfsdm: dfsdm@4400d000 { compatible = "st,stm32mp1-dfsdm"; reg = <0x4400d000 0x800>; @@ -945,6 +1072,18 @@ status = "disabled"; }; + dcmi: dcmi@4c006000 { + compatible = "st,stm32-dcmi"; + reg = <0x4c006000 0x400>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rcc CAMITF_R>; + clocks = <&rcc DCMI>; + clock-names = "mclk"; + dmas = <&dmamux1 75 0x400 0x0d>; + dma-names = "tx"; + status = "disabled"; + }; + rcc: rcc@50000000 { compatible = "st,stm32mp1-rcc", "syscon"; reg = <0x50000000 0x1000>; @@ -1084,6 +1223,37 @@ status = "disabled"; }; + sai4: sai@50027000 { + compatible = "st,stm32h7-sai"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x50027000 0x400>; + reg = <0x50027000 0x4>, <0x500273f0 0x10>; + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rcc SAI4_R>; + status = "disabled"; + + sai4a: audio-controller@50027004 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-a"; + reg = <0x04 0x1c>; + clocks = <&rcc SAI4_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 99 0x400 0x01>; + status = "disabled"; + }; + + sai4b: audio-controller@50027024 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x1c>; + clocks = <&rcc SAI4_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 100 0x400 0x01>; + status = "disabled"; + }; + }; + dts: thermal@50028000 { compatible = "st,stm32-thermal"; reg = <0x50028000 0x100>; @@ -1242,6 +1412,16 @@ status = "disabled"; }; + gpu: gpu@59000000 { + compatible = "vivante,gc"; + reg = <0x59000000 0x800>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc GPU>, <&rcc GPU_K>; + clock-names = "bus" ,"core"; + resets = <&rcc GPU_R>; + status = "disabled"; + }; + dsi: dsi@5a000000 { compatible = "st,stm32-dsi"; reg = <0x5a000000 0x800>; @@ -1363,4 +1543,24 @@ status = "disabled"; }; }; + + mlahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + dma-ranges = <0x00000000 0x38000000 0x10000>, + <0x10000000 0x10000000 0x60000>, + <0x30000000 0x30000000 0x60000>; + + m4_rproc: m4@10000000 { + compatible = "st,stm32mp1-m4"; + reg = <0x10000000 0x40000>, + <0x30000000 0x40000>, + <0x38000000 0x10000>; + resets = <&rcc MCU_R>; + st,syscfg-holdboot = <&rcc 0x10C 0x1>; + st,syscfg-tz = <&rcc 0x000 0x1>; + status = "disabled"; + }; + }; }; diff --git a/arch/arm/dts/stm32mp157xaa-pinctrl.dtsi b/arch/arm/dts/stm32mp157xaa-pinctrl.dtsi new file mode 100644 index 0000000000..875adf5e1e --- /dev/null +++ b/arch/arm/dts/stm32mp157xaa-pinctrl.dtsi @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@st.com> + */ + +#include "stm32mp157-pinctrl.dtsi" +/ { + soc { + pinctrl: pin-controller@50002000 { + st,package = <STM32MP_PKG_AA>; + + gpioa: gpio@50002000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@50003000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@50004000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 32 16>; + }; + + gpiod: gpio@50005000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@50006000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@50007000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@50008000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@50009000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 112 16>; + }; + + gpioi: gpio@5000a000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 128 16>; + }; + + gpioj: gpio@5000b000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 144 16>; + }; + + gpiok: gpio@5000c000 { + status = "okay"; + ngpios = <8>; + gpio-ranges = <&pinctrl 0 160 8>; + }; + }; + + pinctrl_z: pin-controller-z@54004000 { + st,package = <STM32MP_PKG_AA>; + + gpioz: gpio@54004000 { + status = "okay"; + ngpios = <8>; + gpio-ranges = <&pinctrl_z 0 400 8>; + }; + }; + }; +}; diff --git a/arch/arm/dts/stm32mp157xab-pinctrl.dtsi b/arch/arm/dts/stm32mp157xab-pinctrl.dtsi new file mode 100644 index 0000000000..961fa12a59 --- /dev/null +++ b/arch/arm/dts/stm32mp157xab-pinctrl.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@st.com> + */ + +#include "stm32mp157-pinctrl.dtsi" +/ { + soc { + pinctrl: pin-controller@50002000 { + st,package = <STM32MP_PKG_AB>; + + gpioa: gpio@50002000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@50003000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@50004000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 32 16>; + }; + + gpiod: gpio@50005000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@50006000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@50007000 { + status = "okay"; + ngpios = <6>; + gpio-ranges = <&pinctrl 6 86 6>; + }; + + gpiog: gpio@50008000 { + status = "okay"; + ngpios = <10>; + gpio-ranges = <&pinctrl 6 102 10>; + }; + + gpioh: gpio@50009000 { + status = "okay"; + ngpios = <2>; + gpio-ranges = <&pinctrl 0 112 2>; + }; + }; + }; +}; diff --git a/arch/arm/dts/stm32mp157xac-pinctrl.dtsi b/arch/arm/dts/stm32mp157xac-pinctrl.dtsi new file mode 100644 index 0000000000..26600f188d --- /dev/null +++ b/arch/arm/dts/stm32mp157xac-pinctrl.dtsi @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@st.com> + */ + +#include "stm32mp157-pinctrl.dtsi" +/ { + soc { + pinctrl: pin-controller@50002000 { + st,package = <STM32MP_PKG_AC>; + + gpioa: gpio@50002000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@50003000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@50004000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 32 16>; + }; + + gpiod: gpio@50005000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@50006000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@50007000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@50008000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@50009000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 112 16>; + }; + + gpioi: gpio@5000a000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 0 128 12>; + }; + }; + + pinctrl_z: pin-controller-z@54004000 { + st,package = <STM32MP_PKG_AC>; + + gpioz: gpio@54004000 { + status = "okay"; + ngpios = <8>; + gpio-ranges = <&pinctrl_z 0 400 8>; + }; + }; + }; +}; diff --git a/arch/arm/dts/stm32mp157xad-pinctrl.dtsi b/arch/arm/dts/stm32mp157xad-pinctrl.dtsi new file mode 100644 index 0000000000..910113f3e6 --- /dev/null +++ b/arch/arm/dts/stm32mp157xad-pinctrl.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@st.com> + */ + +#include "stm32mp157-pinctrl.dtsi" +/ { + soc { + pinctrl: pin-controller@50002000 { + st,package = <STM32MP_PKG_AD>; + + gpioa: gpio@50002000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@50003000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@50004000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 32 16>; + }; + + gpiod: gpio@50005000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@50006000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@50007000 { + status = "okay"; + ngpios = <6>; + gpio-ranges = <&pinctrl 6 86 6>; + }; + + gpiog: gpio@50008000 { + status = "okay"; + ngpios = <10>; + gpio-ranges = <&pinctrl 6 102 10>; + }; + + gpioh: gpio@50009000 { + status = "okay"; + ngpios = <2>; + gpio-ranges = <&pinctrl 0 112 2>; + }; + }; + }; +}; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index eb21c09e01..a83c70ece2 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -178,8 +178,10 @@ #elif defined(CONFIG_ARCH_LX2160A) #define TZPC_BASE 0x02200000 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) +#if !defined(CONFIG_DM_I2C) #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_EARLY_INIT +#endif #define SRDS_MAX_LANES 8 #ifndef L1_CACHE_BYTES #define L1_CACHE_SHIFT 6 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h index f971af8d26..37e2fe4e66 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h @@ -17,6 +17,7 @@ struct icid_id_table { u32 reg; phys_addr_t compat_addr; phys_addr_t reg_addr; + bool le; }; struct fman_icid_id_table { @@ -30,18 +31,35 @@ int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids); void set_icids(void); void fdt_fixup_icid(void *blob); -#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr) \ +#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr, _le) \ { .compat = name, \ .id = idA, \ .reg = regA, \ .compat_addr = compataddr, \ .reg_addr = addr, \ + .le = _le \ } +#ifdef CONFIG_SYS_FSL_SEC_LE +#define SEC_IS_LE true +#elif defined(CONFIG_SYS_FSL_SEC_BE) +#define SEC_IS_LE false +#endif + +#ifdef CONFIG_FSL_LSCH2 + +#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE +#define SCFG_IS_LE true +#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE) +#define SCFG_IS_LE false +#endif + +#define QDMA_IS_LE false + #define SET_SCFG_ICID(compat, streamid, name, compataddr) \ SET_ICID_ENTRY(compat, streamid, (((streamid) << 24) | (1 << 23)), \ offsetof(struct ccsr_scfg, name) + CONFIG_SYS_FSL_SCFG_ADDR, \ - compataddr) + compataddr, SCFG_IS_LE) #define SET_USB_ICID(usb_num, compat, streamid) \ SET_SCFG_ICID(compat, streamid, usb##usb_num##_icid,\ @@ -55,14 +73,6 @@ void fdt_fixup_icid(void *blob); SET_SCFG_ICID("fsl,esdhc", streamid, sdhc_icid,\ CONFIG_SYS_FSL_ESDHC_ADDR) -#define SET_QDMA_ICID(compat, streamid) \ - SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \ - QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \ - QDMA_BASE_ADDR), \ - SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \ - QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \ - QDMA_BASE_ADDR) - #define SET_EDMA_ICID(streamid) \ SET_SCFG_ICID("fsl,vf610-edma", streamid, edma_icid,\ EDMA_BASE_ADDR) @@ -81,22 +91,78 @@ void fdt_fixup_icid(void *blob); SET_ICID_ENTRY("fsl,qman", streamid, streamid, \ offsetof(struct ccsr_qman, liodnr) + \ CONFIG_SYS_FSL_QMAN_ADDR, \ - CONFIG_SYS_FSL_QMAN_ADDR) + CONFIG_SYS_FSL_QMAN_ADDR, false) #define SET_BMAN_ICID(streamid) \ SET_ICID_ENTRY("fsl,bman", streamid, streamid, \ offsetof(struct ccsr_bman, liodnr) + \ CONFIG_SYS_FSL_BMAN_ADDR, \ - CONFIG_SYS_FSL_BMAN_ADDR) + CONFIG_SYS_FSL_BMAN_ADDR, false) #define SET_FMAN_ICID_ENTRY(_port_id, streamid) \ { .port_id = (_port_id), .icid = (streamid) } +#define SEC_ICID_REG_VAL(streamid) (((streamid) << 16) | (streamid)) + #define SET_SEC_QI_ICID(streamid) \ SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \ 0, offsetof(ccsr_sec_t, qilcr_ls) + \ CONFIG_SYS_FSL_SEC_ADDR, \ - CONFIG_SYS_FSL_SEC_ADDR) + CONFIG_SYS_FSL_SEC_ADDR, SEC_IS_LE) + +extern struct fman_icid_id_table fman_icid_tbl[]; +extern int fman_icid_tbl_sz; + +#else /* CONFIG_FSL_LSCH2 */ + +#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE +#define GUR_IS_LE true +#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE) +#define GUR_IS_LE false +#endif + +#define QDMA_IS_LE true + +#define SET_GUR_ICID(compat, streamid, name, compataddr) \ + SET_ICID_ENTRY(compat, streamid, streamid, \ + offsetof(struct ccsr_gur, name) + CONFIG_SYS_FSL_GUTS_ADDR, \ + compataddr, GUR_IS_LE) + +#define SET_USB_ICID(usb_num, compat, streamid) \ + SET_GUR_ICID(compat, streamid, usb##usb_num##_amqr,\ + CONFIG_SYS_XHCI_USB##usb_num##_ADDR) + +#define SET_SATA_ICID(sata_num, compat, streamid) \ + SET_GUR_ICID(compat, streamid, sata##sata_num##_amqr, \ + AHCI_BASE_ADDR##sata_num) + +#define SET_SDHC_ICID(sdhc_num, streamid) \ + SET_GUR_ICID("fsl,esdhc", streamid, sdmm##sdhc_num##_amqr,\ + FSL_ESDHC##sdhc_num##_BASE_ADDR) + +#define SET_EDMA_ICID(streamid) \ + SET_GUR_ICID("fsl,vf610-edma", streamid, spare3_amqr,\ + EDMA_BASE_ADDR) + +#define SET_GPU_ICID(compat, streamid) \ + SET_GUR_ICID(compat, streamid, misc1_amqr,\ + GPU_BASE_ADDR) + +#define SET_DISPLAY_ICID(streamid) \ + SET_GUR_ICID("arm,mali-dp500", streamid, spare2_amqr,\ + DISPLAY_BASE_ADDR) + +#define SEC_ICID_REG_VAL(streamid) (streamid) + +#endif /* CONFIG_FSL_LSCH2 */ + +#define SET_QDMA_ICID(compat, streamid) \ + SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \ + QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \ + QDMA_BASE_ADDR, QDMA_IS_LE), \ + SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \ + QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \ + QDMA_BASE_ADDR, QDMA_IS_LE) #define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \ SET_ICID_ENTRY( \ @@ -106,24 +172,22 @@ void fdt_fixup_icid(void *blob); ? NULL \ : "fsl,sec-v4.0-job-ring"), \ streamid, \ - (((streamid) << 16) | (streamid)), \ + SEC_ICID_REG_VAL(streamid), \ offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \ CONFIG_SYS_FSL_SEC_ADDR, \ - FSL_SEC_JR##jr_num##_BASE_ADDR) + FSL_SEC_JR##jr_num##_BASE_ADDR, SEC_IS_LE) #define SET_SEC_DECO_ICID_ENTRY(deco_num, streamid) \ - SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \ + SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \ offsetof(ccsr_sec_t, decoliodnr[deco_num].ls) + \ - CONFIG_SYS_FSL_SEC_ADDR, 0) + CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE) #define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \ - SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \ + SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \ offsetof(ccsr_sec_t, rticliodnr[rtic_num].ls) + \ - CONFIG_SYS_FSL_SEC_ADDR, 0) + CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE) extern struct icid_id_table icid_tbl[]; -extern struct fman_icid_id_table fman_icid_tbl[]; extern int icid_tbl_sz; -extern int fman_icid_tbl_sz; #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index ee9b33becf..8a5446df1a 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -25,6 +25,8 @@ #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000) #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000) +#define FSL_ESDHC1_BASE_ADDR CONFIG_SYS_FSL_ESDHC_ADDR +#define FSL_ESDHC2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01150000) #ifndef CONFIG_NXP_LSCH3_2 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) #endif @@ -79,20 +81,41 @@ #define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) #define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) +/* EDMA */ +#define EDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x012c0000) + /* SATA */ #define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000) #define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000) +/* QDMA */ +#define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000) +#define QMAN_CQSIDR_REG 0x20a80 + +/* DISPLAY */ +#define DISPLAY_BASE_ADDR (CONFIG_SYS_IMMR + 0x0e080000) + +/* GPU */ +#define GPU_BASE_ADDR (CONFIG_SYS_IMMR + 0x0e0c0000) + /* SFP */ #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) /* SEC */ #define CONFIG_SYS_FSL_SEC_OFFSET 0x07000000ull #define CONFIG_SYS_FSL_JR0_OFFSET 0x07010000ull +#define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET +#define FSL_SEC_JR1_OFFSET 0x07020000ull +#define FSL_SEC_JR2_OFFSET 0x07030000ull +#define FSL_SEC_JR3_OFFSET 0x07040000ull #define CONFIG_SYS_FSL_SEC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) #define CONFIG_SYS_FSL_JR0_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) +#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET) +#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET) +#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET) +#define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR3_OFFSET) #ifdef CONFIG_TFABOOT #ifdef CONFIG_NXP_LSCH3_2 @@ -417,7 +440,8 @@ struct ccsr_gur { u32 usb2_amqr; u8 res_528[0x530-0x528]; /* add more registers when needed */ u32 sdmm1_amqr; - u8 res_534[0x550-0x534]; /* add more registers when needed */ + u32 sdmm2_amqr; + u8 res_538[0x550 - 0x538]; /* add more registers when needed */ u32 sata1_amqr; u32 sata2_amqr; u8 res_558[0x570-0x558]; /* add more registers when needed */ @@ -425,7 +449,8 @@ struct ccsr_gur { u8 res_574[0x590-0x574]; /* add more registers when needed */ u32 spare1_amqr; u32 spare2_amqr; - u8 res_598[0x620-0x598]; /* add more registers when needed */ + u32 spare3_amqr; + u8 res_59c[0x620 - 0x59c]; /* add more registers when needed */ u32 gencr[7]; /* General Control Registers */ u8 res_63c[0x640-0x63c]; /* add more registers when needed */ u32 cgensr1; /* Core General Status Register */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index c53cc57e56..93bdcc4caa 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -76,7 +76,7 @@ #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) #define FSL_DMA_STREAM_ID 6 -#elif defined(CONFIG_ARCH_LS1088A) +#elif defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) #define FSL_DMA_STREAM_ID 5 #endif @@ -98,4 +98,15 @@ #define FSL_DPAA2_STREAM_ID_START 23 #define FSL_DPAA2_STREAM_ID_END 63 +#define FSL_SEC_STREAM_ID 64 +#define FSL_SEC_JR1_STREAM_ID 65 +#define FSL_SEC_JR2_STREAM_ID 66 +#define FSL_SEC_JR3_STREAM_ID 67 +#define FSL_SEC_JR4_STREAM_ID 68 + +#define FSL_SDMMC2_STREAM_ID 69 +#define FSL_EDMA_STREAM_ID 70 +#define FSL_GPU_STREAM_ID 71 +#define FSL_DISPLAY_STREAM_ID 72 + #endif diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index 471a336f13..0836091af2 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -10,7 +10,6 @@ /* Basic CPU architecture */ -#define CONFIG_ARCH_CPU_INIT /* UART configuration */ #if (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \ diff --git a/arch/arm/include/asm/arch-rockchip/misc.h b/arch/arm/include/asm/arch-rockchip/misc.h new file mode 100644 index 0000000000..b6b03c934e --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/misc.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * RK3399: Architecture common definitions + * + * Copyright (C) 2019 Collabora Inc - https://www.collabora.com/ + * Rohan Garg <rohan.garg@collabora.com> + */ + +int rockchip_cpuid_from_efuse(const u32 cpuid_offset, + const u32 cpuid_length, + u8 *cpuid); +int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length); +int rockchip_setup_macaddr(void); diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index 370031f2ac..b9461058ae 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h @@ -1,6 +1,8 @@ #if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) && \ !defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM6858) && \ - !defined(CONFIG_ARCH_BCM63158) && !defined(CONFIG_ARCH_ROCKCHIP) + !defined(CONFIG_ARCH_BCM63158) && !defined(CONFIG_ARCH_ROCKCHIP) && \ + !defined(CONFIG_ARCH_LX2160A) && !defined(CONFIG_ARCH_LS1028A) && \ + !defined(CONFIG_ARCH_LS2080A) && !defined(CONFIG_ARCH_LS1088A) #include <asm/arch/gpio.h> #endif #include <asm-generic/gpio.h> diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 449544d11c..463d283cb7 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -77,6 +77,7 @@ void noncached_init(void) phys_addr_t start, end; size_t size; + /* If this calculation changes, update board_f.c:reserve_noncached() */ end = ALIGN(mem_malloc_start, MMU_SECTION_SIZE) - MMU_SECTION_SIZE; size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE); start = end - size; diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h index d45343b4d3..3412df0f06 100644 --- a/arch/arm/mach-at91/include/mach/at91rm9200.h +++ b/arch/arm/mach-at91/include/mach/at91rm9200.h @@ -5,7 +5,6 @@ #ifndef __AT91RM9200_H__ #define __AT91RM9200_H__ -#define CONFIG_ARCH_CPU_INIT /* we need arch_cpu_init() for hw timers */ #define CONFIG_AT91_GPIO /* and require always gpio features */ /* Periperial Identifiers */ diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index aed379a0dc..207f900011 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -25,6 +25,10 @@ endif obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o +ifdef CONFIG_MISC_INIT_R +obj-y += misc.o +endif + obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/ ifndef CONFIG_TPL_BUILD diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index b2a88e789d..8ca3463731 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -11,6 +11,7 @@ #include <asm/arch-rockchip/boot_mode.h> #include <asm/arch-rockchip/clock.h> #include <asm/arch-rockchip/periph.h> +#include <asm/arch-rockchip/misc.h> #include <power/regulator.h> DECLARE_GLOBAL_DATA_PTR; @@ -102,3 +103,25 @@ int fastboot_set_reboot_flag(void) return 0; } #endif + +#ifdef CONFIG_MISC_INIT_R +__weak int misc_init_r(void) +{ + const u32 cpuid_offset = 0x7; + const u32 cpuid_length = 0x10; + u8 cpuid[cpuid_length]; + int ret; + + ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); + if (ret) + return ret; + + ret = rockchip_cpuid_set(cpuid, cpuid_length); + if (ret) + return ret; + + ret = rockchip_setup_macaddr(); + + return ret; +} +#endif diff --git a/arch/arm/mach-rockchip/misc.c b/arch/arm/mach-rockchip/misc.c new file mode 100644 index 0000000000..fdb763cc53 --- /dev/null +++ b/arch/arm/mach-rockchip/misc.c @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * RK3399: Architecture common definitions + * + * Copyright (C) 2019 Collabora Inc - https://www.collabora.com/ + * Rohan Garg <rohan.garg@collabora.com> + * + * Based on puma-rk3399.c: + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + */ + +#include <common.h> +#include <env.h> +#include <dm.h> +#include <dm/uclass-internal.h> +#include <misc.h> +#include <u-boot/sha256.h> + +#include <asm/arch-rockchip/misc.h> + +int rockchip_setup_macaddr(void) +{ +#if CONFIG_IS_ENABLED(CMD_NET) + int ret; + const char *cpuid = env_get("cpuid#"); + u8 hash[SHA256_SUM_LEN]; + int size = sizeof(hash); + u8 mac_addr[6]; + + /* Only generate a MAC address, if none is set in the environment */ + if (env_get("ethaddr")) + return -1; + + if (!cpuid) { + debug("%s: could not retrieve 'cpuid#'\n", __func__); + return -1; + } + + ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, &size); + if (ret) { + debug("%s: failed to calculate SHA256\n", __func__); + return -1; + } + + /* Copy 6 bytes of the hash to base the MAC address on */ + memcpy(mac_addr, hash, 6); + + /* Make this a valid MAC address and set it */ + mac_addr[0] &= 0xfe; /* clear multicast bit */ + mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */ + eth_env_set_enetaddr("ethaddr", mac_addr); +#endif + return 0; +} + +int rockchip_cpuid_from_efuse(const u32 cpuid_offset, + const u32 cpuid_length, + u8 *cpuid) +{ +#if CONFIG_IS_ENABLED(ROCKCHIP_EFUSE) + struct udevice *dev; + int ret; + + /* retrieve the device */ + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(rockchip_efuse), &dev); + if (ret) { + debug("%s: could not find efuse device\n", __func__); + return -1; + } + + /* read the cpu_id range from the efuses */ + ret = misc_read(dev, cpuid_offset, cpuid, sizeof(cpuid)); + if (ret) { + debug("%s: reading cpuid from the efuses failed\n", + __func__); + return -1; + } +#endif + return 0; +} + +int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length) +{ + u8 low[cpuid_length / 2], high[cpuid_length / 2]; + char cpuid_str[cpuid_length * 2 + 1]; + u64 serialno; + char serialno_str[17]; + int i; + + memset(cpuid_str, 0, sizeof(cpuid_str)); + for (i = 0; i < 16; i++) + sprintf(&cpuid_str[i * 2], "%02x", cpuid[i]); + + debug("cpuid: %s\n", cpuid_str); + + /* + * Mix the cpuid bytes using the same rules as in + * ${linux}/drivers/soc/rockchip/rockchip-cpuinfo.c + */ + for (i = 0; i < 8; i++) { + low[i] = cpuid[1 + (i << 1)]; + high[i] = cpuid[i << 1]; + } + + serialno = crc32_no_comp(0, low, 8); + serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32; + snprintf(serialno_str, sizeof(serialno_str), "%016llx", serialno); + + env_set("cpuid#", cpuid_str); + env_set("serial#", serialno_str); + + return 0; +} diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 87d0786ba8..87e3d342f6 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -191,8 +191,6 @@ source "board/radxa/rock2/Kconfig" source "board/rockchip/evb_rk3288/Kconfig" -source "board/rockchip/fennec_rk3288/Kconfig" - source "board/rockchip/tinker_rk3288/Kconfig" endif diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index 9dc3c4d1c5..c9bc084194 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -16,8 +16,9 @@ config SPL select SPL_REGMAP select SPL_DM_RESET select SPL_SERIAL_SUPPORT + select SPL_SPI_LOAD select SPL_SYSCON - select SPL_WATCHDOG_SUPPORT + select SPL_WATCHDOG_SUPPORT if WATCHDOG imply BOOTSTAGE_STASH if SPL_BOOTSTAGE imply SPL_BOOTSTAGE if BOOTSTAGE imply SPL_DISPLAY_PRINT @@ -42,11 +43,15 @@ config TARGET_STM32MP1 select PINCTRL_STM32 select STM32_RCC select STM32_RESET + select STM32_SERIAL select SYS_ARCH_TIMER imply BOOTCOUNT_LIMIT imply BOOTSTAGE imply CMD_BOOTCOUNT imply CMD_BOOTSTAGE + imply DISABLE_CONSOLE + imply PRE_CONSOLE_BUFFER + imply SILENT_CONSOLE imply SYSRESET_PSCI if STM32MP1_TRUSTED imply SYSRESET_SYSCON if !STM32MP1_TRUSTED help @@ -109,6 +114,13 @@ config CMD_STM32KEY fuse public key hash in corresponding fuse used to authenticate binary. + +config PRE_CON_BUF_ADDR + default 0xC02FF000 + +config PRE_CON_BUF_SZ + default 4096 + config BOOTSTAGE_STASH_ADDR default 0xC3000000 diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile index ad5fd46ccd..eee39c27c3 100644 --- a/arch/arm/mach-stm32mp/Makefile +++ b/arch/arm/mach-stm32mp/Makefile @@ -12,7 +12,8 @@ obj-y += spl.o else obj-y += bsec.o obj-$(CONFIG_CMD_STM32KEY) += cmd_stm32key.o -endif obj-$(CONFIG_ARMV7_PSCI) += psci.o +endif + obj-$(CONFIG_$(SPL_)DM_REGULATOR) += pwr_regulator.o obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c index 8018366885..a77c706a1a 100644 --- a/arch/arm/mach-stm32mp/bsec.c +++ b/arch/arm/mach-stm32mp/bsec.c @@ -364,15 +364,13 @@ static int stm32mp_bsec_read(struct udevice *dev, int offset, offs -= STM32_BSEC_OTP_OFFSET; shadow = false; } - otp = offs / sizeof(u32); - if (otp < 0 || (otp + nb_otp - 1) > BSEC_OTP_MAX_VALUE) { - dev_err(dev, "wrong value for otp, max value : %i\n", - BSEC_OTP_MAX_VALUE); + if (offs < 0 || (offs % 4) || (size % 4)) return -EINVAL; - } - for (i = otp; i < (otp + nb_otp); i++) { + otp = offs / sizeof(u32); + + for (i = otp; i < (otp + nb_otp) && i <= BSEC_OTP_MAX_VALUE; i++) { u32 *addr = &((u32 *)buf)[i - otp]; if (shadow) @@ -383,7 +381,10 @@ static int stm32mp_bsec_read(struct udevice *dev, int offset, if (ret) break; } - return ret; + if (ret) + return ret; + else + return (i - otp) * 4; } static int stm32mp_bsec_write(struct udevice *dev, int offset, @@ -400,15 +401,13 @@ static int stm32mp_bsec_write(struct udevice *dev, int offset, offs -= STM32_BSEC_OTP_OFFSET; shadow = false; } - otp = offs / sizeof(u32); - if (otp < 0 || (otp + nb_otp - 1) > BSEC_OTP_MAX_VALUE) { - dev_err(dev, "wrong value for otp, max value : %d\n", - BSEC_OTP_MAX_VALUE); + if (offs < 0 || (offs % 4) || (size % 4)) return -EINVAL; - } - for (i = otp; i < otp + nb_otp; i++) { + otp = offs / sizeof(u32); + + for (i = otp; i < otp + nb_otp && i <= BSEC_OTP_MAX_VALUE; i++) { u32 *val = &((u32 *)buf)[i - otp]; if (shadow) @@ -418,7 +417,10 @@ static int stm32mp_bsec_write(struct udevice *dev, int offset, if (ret) break; } - return ret; + if (ret) + return ret; + else + return (i - otp) * 4; } static const struct misc_ops stm32mp_bsec_ops = { diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h index 1d4b5482ac..b3e9ccc5d3 100644 --- a/arch/arm/mach-stm32mp/include/mach/stm32.h +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@ -94,6 +94,7 @@ enum boot_device { #define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4) #define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0) #define TAMP_BOOT_FORCED_MASK GENMASK(7, 0) +#define TAMP_BOOT_DEBUG_ON BIT(16) enum forced_boot_mode { BOOT_NORMAL = 0x00, diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index 6a28f802c2..021c85f00f 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -1,6 +1,18 @@ # SPDX-License-Identifier: GPL-2.0+ +dtb-$(CONFIG_TARGET_MPC8548CDS) += mpc8548cds.dtb mpc8548cds_36b.dtb +dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb +dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb +dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb +dtb-$(CONFIG_TARGET_P2041RDB) += p2041rdb.dtb +dtb-$(CONFIG_TARGET_P3041DS) += p3041ds.dtb +dtb-$(CONFIG_TARGET_P4080DS) += p4080ds.dtb +dtb-$(CONFIG_TARGET_P5040DS) += p5040ds.dtb +dtb-$(CONFIG_TARGET_T1024RDB) += t1024rdb.dtb +dtb-$(CONFIG_TARGET_T1042D4RDB) += t1042d4rdb.dtb dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb +dtb-$(CONFIG_TARGET_T2080RDB) += t2080rdb.dtb +dtb-$(CONFIG_TARGET_T4240RDB) += t4240rdb.dtb dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb diff --git a/arch/powerpc/dts/e500mc_power_isa.dtsi b/arch/powerpc/dts/e500mc_power_isa.dtsi new file mode 100644 index 0000000000..e486ae501a --- /dev/null +++ b/arch/powerpc/dts/e500mc_power_isa.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * e500mc Power ISA Device Tree Source (include) + * + * Copyright 2012 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/ { + cpus { + power-isa-version = "2.06"; + power-isa-b; // Base + power-isa-e; // Embedded + power-isa-atb; // Alternate Time Base + power-isa-cs; // Cache Specification + power-isa-ds; // Decorated Storage + power-isa-e.ed; // Embedded.Enhanced Debug + power-isa-e.pd; // Embedded.External PID + power-isa-e.hv; // Embedded.Hypervisor + power-isa-e.le; // Embedded.Little-Endian + power-isa-e.pm; // Embedded.Performance Monitor + power-isa-e.pc; // Embedded.Processor Control + power-isa-ecl; // Embedded Cache Locking + power-isa-exp; // External Proxy + power-isa-fp; // Floating Point + power-isa-fp.r; // Floating Point.Record + power-isa-mmc; // Memory Coherence + power-isa-scpm; // Store Conditional Page Mobility + power-isa-wt; // Wait + fsl,eref-deo; // Data Cache Extended Operations + mmu-type = "power-embedded"; + }; +}; diff --git a/arch/powerpc/dts/e500v2_power_isa.dtsi b/arch/powerpc/dts/e500v2_power_isa.dtsi new file mode 100644 index 0000000000..010e8e5f3f --- /dev/null +++ b/arch/powerpc/dts/e500v2_power_isa.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * e500v2 Power ISA Device Tree Source (include) + * + * Copyright 2012 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/ { + cpus { + power-isa-version = "2.03"; + power-isa-b; // Base + power-isa-e; // Embedded + power-isa-atb; // Alternate Time Base + power-isa-cs; // Cache Specification + power-isa-e.le; // Embedded.Little-Endian + power-isa-e.pm; // Embedded.Performance Monitor + power-isa-ecl; // Embedded Cache Locking + power-isa-mmc; // Memory Coherence + power-isa-sp; // Signal Processing Engine + power-isa-sp.fd; // SPE.Embedded Float Scalar Double + power-isa-sp.fs; // SPE.Embedded Float Scalar Single + power-isa-sp.fv; // SPE.Embedded Float Vector + mmu-type = "power-embedded"; + }; +}; diff --git a/arch/powerpc/dts/e5500_power_isa.dtsi b/arch/powerpc/dts/e5500_power_isa.dtsi new file mode 100644 index 0000000000..0a0943b0bb --- /dev/null +++ b/arch/powerpc/dts/e5500_power_isa.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * e5500 Power ISA Device Tree Source (include) + * + * Copyright 2012 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/ { + cpus { + power-isa-version = "2.06"; + power-isa-b; // Base + power-isa-e; // Embedded + power-isa-atb; // Alternate Time Base + power-isa-cs; // Cache Specification + power-isa-ds; // Decorated Storage + power-isa-e.ed; // Embedded.Enhanced Debug + power-isa-e.pd; // Embedded.External PID + power-isa-e.hv; // Embedded.Hypervisor + power-isa-e.le; // Embedded.Little-Endian + power-isa-e.pm; // Embedded.Performance Monitor + power-isa-e.pc; // Embedded.Processor Control + power-isa-ecl; // Embedded Cache Locking + power-isa-exp; // External Proxy + power-isa-fp; // Floating Point + power-isa-fp.r; // Floating Point.Record + power-isa-mmc; // Memory Coherence + power-isa-scpm; // Store Conditional Page Mobility + power-isa-wt; // Wait + power-isa-64; // 64-bit + fsl,eref-deo; // Data Cache Extended Operations + mmu-type = "power-embedded"; + }; +}; diff --git a/arch/powerpc/dts/mpc8548-post.dtsi b/arch/powerpc/dts/mpc8548-post.dtsi new file mode 100644 index 0000000000..2206f2da9f --- /dev/null +++ b/arch/powerpc/dts/mpc8548-post.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * MPC8548 Silicon/SoC Device Tree Source (post include) + * + * Copyright 2012 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +&soc { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "fsl,mpc8548-immr", "simple-bus"; + bus-frequency = <0x0>; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <4>; + reg = <0x40000 0x40000>; + compatible = "fsl,mpic"; + device_type = "open-pic"; + big-endian; + single-cpu-affinity; + last-interrupt-source = <255>; + }; +}; + +&pcie { + compatible = "fsl,pcie-mpc8548", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; +}; diff --git a/arch/powerpc/dts/mpc8548.dtsi b/arch/powerpc/dts/mpc8548.dtsi new file mode 100644 index 0000000000..b24567dc65 --- /dev/null +++ b/arch/powerpc/dts/mpc8548.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * MPC8548CDS Silicon/SoC Device Tree Source (pre include) + * + * Copyright 2011 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/dts-v1/; + +/include/ "e500v2_power_isa.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8548@0 { + device_type = "cpu"; + reg = <0>; + }; + }; +}; diff --git a/arch/powerpc/dts/mpc8548cds.dts b/arch/powerpc/dts/mpc8548cds.dts new file mode 100644 index 0000000000..3b927bd265 --- /dev/null +++ b/arch/powerpc/dts/mpc8548cds.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * MPC8548CDS Device Tree Source + * + * Copyright 2006 - 2012 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/include/ "mpc8548.dtsi" + +/ { + model = "fsl,MPC8548CDS"; + compatible = "fsl,MPC8548CDS"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + soc: soc8548@e0000000 { + ranges = <0x0 0x0 0xe0000000 0x100000>; + }; + + pcie: pcie@e000a000 { + reg = <0x0 0xe000a000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0x0 0xe3000000 0x0 0x00100000 /* downstream I/O */ + 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; +}; + +/include/ "mpc8548-post.dtsi" diff --git a/arch/powerpc/dts/mpc8548cds_36b.dts b/arch/powerpc/dts/mpc8548cds_36b.dts new file mode 100644 index 0000000000..98d7c2410b --- /dev/null +++ b/arch/powerpc/dts/mpc8548cds_36b.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * MPC8548CDS (36-bit address map) Device Tree Source + * + * Copyright 2012 - 2015 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/include/ "mpc8548.dtsi" + +/ { + model = "fsl,MPC8548CDS"; + compatible = "fsl,MPC8548CDS"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + soc: soc8548@fe0000000 { + ranges = <0x0 0xf 0xe0000000 0x100000>; + }; + + pcie: pcie@fe000a000 { + reg = <0xf 0xe000a000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0xf 0xe3000000 0x0 0x00100000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; +}; + +/include/ "mpc8548-post.dtsi" diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi new file mode 100644 index 0000000000..1e5e67804b --- /dev/null +++ b/arch/powerpc/dts/p1020-post.dtsi @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1020 Silicon/SoC Device Tree Source (post include) + * + * Copyright 2013 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +&soc { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "fsl,p1020-immr", "simple-bus"; + bus-frequency = <0x0>; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <4>; + reg = <0x40000 0x40000>; + compatible = "fsl,mpic"; + device_type = "open-pic"; + big-endian; + single-cpu-affinity; + last-interrupt-source = <255>; + }; +}; + +/* PCIe controller base address 0x9000 */ +&pci1 { + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; +}; + +/* PCIe controller base address 0xa000 */ +&pci0 { + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; +}; diff --git a/arch/powerpc/dts/p1020.dtsi b/arch/powerpc/dts/p1020.dtsi new file mode 100644 index 0000000000..ee2b6f4945 --- /dev/null +++ b/arch/powerpc/dts/p1020.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1020 Silicon/SoC Device Tree Source (pre include) + * + * Copyright 2013 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/dts-v1/; + +/include/ "e500v2_power_isa.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: PowerPC,P1020@0 { + device_type = "cpu"; + reg = <0>; + }; + cpu1: PowerPC,P1020@1 { + device_type = "cpu"; + reg = <1>; + }; + }; +}; diff --git a/arch/powerpc/dts/p1020rdb-pc.dts b/arch/powerpc/dts/p1020rdb-pc.dts new file mode 100644 index 0000000000..7ebaa619df --- /dev/null +++ b/arch/powerpc/dts/p1020rdb-pc.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1020RDB-PC Device Tree Source + * + * Copyright 2013 - 2015 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/include/ "p1020.dtsi" + +/ { + model = "fsl,P1020RDB-PC"; + compatible = "fsl,P1020RDB-PC"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + soc: soc@ffe00000 { + ranges = <0x0 0x0 0xffe00000 0x100000>; + }; + + pci1: pcie@ffe09000 { + reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pci0: pcie@ffe0a000 { + reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; +}; + +/include/ "p1020-post.dtsi" diff --git a/arch/powerpc/dts/p1020rdb-pc_36b.dts b/arch/powerpc/dts/p1020rdb-pc_36b.dts new file mode 100644 index 0000000000..c0e5ef4cf4 --- /dev/null +++ b/arch/powerpc/dts/p1020rdb-pc_36b.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1020RDB-PC (36-bit address map) Device Tree Source + * + * Copyright 2013 - 2015 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/include/ "p1020.dtsi" + +/ { + model = "fsl,P1020RDB-PC"; + compatible = "fsl,P1020RDB-PC"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + soc: soc@fffe00000 { + ranges = <0x0 0xf 0xffe00000 0x100000>; + }; + + pci1: pcie@fffe09000 { + reg = <0xf 0xffe09000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pci0: pcie@fffe0a000 { + reg = <0xf 0xffe0a000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; +}; + +/include/ "p1020-post.dtsi" diff --git a/arch/powerpc/dts/p1020rdb-pd.dts b/arch/powerpc/dts/p1020rdb-pd.dts new file mode 100644 index 0000000000..21174a09be --- /dev/null +++ b/arch/powerpc/dts/p1020rdb-pd.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1020RDB-PD Device Tree Source + * + * Copyright 2013 - 2015 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/include/ "p1020.dtsi" + +/ { + model = "fsl,P1020RDB-PD"; + compatible = "fsl,P1020RDB-PD"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + soc: soc@ffe00000 { + ranges = <0x0 0x0 0xffe00000 0x100000>; + }; + + pci1: pcie@ffe09000 { + reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pci0: pcie@ffe0a000 { + reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; +}; + +/include/ "p1020-post.dtsi" diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi new file mode 100644 index 0000000000..f696f35960 --- /dev/null +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P2020 Silicon/SoC Device Tree Source (post include) + * + * Copyright 2013 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +&soc { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "fsl,p2020-immr", "simple-bus"; + bus-frequency = <0x0>; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <4>; + reg = <0x40000 0x40000>; + compatible = "fsl,mpic"; + device_type = "open-pic"; + big-endian; + single-cpu-affinity; + last-interrupt-source = <255>; + }; +}; + +/* PCIe controller base address 0x8000 */ +&pci2 { + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; +}; + +/* PCIe controller base address 0x9000 */ +&pci1 { + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; +}; + +/* PCIe controller base address 0xa000 */ +&pci0 { + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; +}; diff --git a/arch/powerpc/dts/p2020.dtsi b/arch/powerpc/dts/p2020.dtsi new file mode 100644 index 0000000000..7c4c2061d4 --- /dev/null +++ b/arch/powerpc/dts/p2020.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P2020 Silicon/SoC Device Tree Source (pre include) + * + * Copyright 2013 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/dts-v1/; + +/include/ "e500v2_power_isa.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: PowerPC,P2020@0 { + device_type = "cpu"; + reg = <0>; + }; + cpu1: PowerPC,P2020@1 { + device_type = "cpu"; + reg = <1>; + }; + }; +}; diff --git a/arch/powerpc/dts/p2020rdb-pc.dts b/arch/powerpc/dts/p2020rdb-pc.dts new file mode 100644 index 0000000000..08befd4c59 --- /dev/null +++ b/arch/powerpc/dts/p2020rdb-pc.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P2020RDB-PC Device Tree Source + * + * Copyright 2013 - 2015 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/include/ "p2020.dtsi" + +/ { + model = "fsl,P2020RDB-PC"; + compatible = "fsl,P2020RDB-PC"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + soc: soc@ffe00000 { + ranges = <0x0 0x0 0xffe00000 0x100000>; + }; + + pci2: pcie@ffe08000 { + reg = <0x0 0xffe08000 0x0 0x1000>; /* registers */ + status = "disabled"; + }; + + pci1: pcie@ffe09000 { + reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pci0: pcie@ffe0a000 { + reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; +}; + +/include/ "p2020-post.dtsi" diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts b/arch/powerpc/dts/p2020rdb-pc_36b.dts new file mode 100644 index 0000000000..04b2519e1a --- /dev/null +++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P2020RDB-PC (36-bit address map) Device Tree Source + * + * Copyright 2013 - 2015 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/include/ "p2020.dtsi" + +/ { + model = "fsl,P2020RDB-PC"; + compatible = "fsl,P2020RDB-PC"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + soc: soc@fffe00000 { + ranges = <0x0 0xf 0xffe00000 0x100000>; + }; + + pci2: pcie@fffe08000 { + reg = <0xf 0xffe08000 0x0 0x1000>; /* registers */ + status = "disabled"; + }; + + pci1: pcie@fffe09000 { + reg = <0xf 0xffe09000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pci0: pcie@fffe0a000 { + reg = <0xf 0xffe0a000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; +}; + +/include/ "p2020-post.dtsi" diff --git a/arch/powerpc/dts/p2041.dtsi b/arch/powerpc/dts/p2041.dtsi new file mode 100644 index 0000000000..55f7adc50e --- /dev/null +++ b/arch/powerpc/dts/p2041.dtsi @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P2041 Silicon/SoC Device Tree Source (pre include) + * + * Copyright 2011 - 2015 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/dts-v1/; + +/include/ "e500mc_power_isa.dtsi" + +/ { + compatible = "fsl,P2041"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: PowerPC,e500mc@0 { + device_type = "cpu"; + reg = <0>; + fsl,portid-mapping = <0x80000000>; + }; + cpu1: PowerPC,e500mc@1 { + device_type = "cpu"; + reg = <1>; + fsl,portid-mapping = <0x40000000>; + }; + cpu2: PowerPC,e500mc@2 { + device_type = "cpu"; + reg = <2>; + fsl,portid-mapping = <0x20000000>; + }; + cpu3: PowerPC,e500mc@3 { + device_type = "cpu"; + reg = <3>; + fsl,portid-mapping = <0x10000000>; + }; + }; + + soc: soc@ffe000000 { + ranges = <0x00000000 0xf 0xfe000000 0x1000000>; + reg = <0xf 0xfe000000 0 0x00001000>; + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <4>; + reg = <0x40000 0x40000>; + compatible = "fsl,mpic", "chrp,open-pic"; + device_type = "open-pic"; + clock-frequency = <0x0>; + }; + }; + + pcie@ffe200000 { + compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */ + law_trgt_if = <0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe201000 { + compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */ + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe202000 { + compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */ + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; +}; diff --git a/arch/powerpc/dts/p2041rdb.dts b/arch/powerpc/dts/p2041rdb.dts new file mode 100644 index 0000000000..6e9d9c058a --- /dev/null +++ b/arch/powerpc/dts/p2041rdb.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P2041RDB Device Tree Source + * + * Copyright 2011 - 2015 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/include/ "p2041.dtsi" + +/ { + model = "fsl,P2041RDB"; + compatible = "fsl,P2041RDB"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + +}; diff --git a/arch/powerpc/dts/p3041.dtsi b/arch/powerpc/dts/p3041.dtsi new file mode 100644 index 0000000000..197896d35a --- /dev/null +++ b/arch/powerpc/dts/p3041.dtsi @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P3041 Silicon/SoC Device Tree Source (pre include) + * + * Copyright 2010 - 2015 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/dts-v1/; + +/include/ "e500mc_power_isa.dtsi" + +/ { + compatible = "fsl,P3041"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: PowerPC,e500mc@0 { + device_type = "cpu"; + reg = <0>; + fsl,portid-mapping = <0x80000000>; + }; + cpu1: PowerPC,e500mc@1 { + device_type = "cpu"; + reg = <1>; + fsl,portid-mapping = <0x40000000>; + }; + cpu2: PowerPC,e500mc@2 { + device_type = "cpu"; + reg = <2>; + fsl,portid-mapping = <0x20000000>; + }; + cpu3: PowerPC,e500mc@3 { + device_type = "cpu"; + reg = <3>; + fsl,portid-mapping = <0x10000000>; + }; + }; + + soc: soc@ffe000000 { + ranges = <0x00000000 0xf 0xfe000000 0x1000000>; + reg = <0xf 0xfe000000 0 0x00001000>; + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <4>; + reg = <0x40000 0x40000>; + compatible = "fsl,mpic", "chrp,open-pic"; + device_type = "open-pic"; + clock-frequency = <0x0>; + }; + }; + + pcie@ffe200000 { + compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */ + law_trgt_if = <0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe201000 { + compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */ + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe202000 { + compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */ + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe203000 { + compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe203000 0x0 0x1000>; /* registers */ + law_trgt_if = <3>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x60000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; +}; diff --git a/arch/powerpc/dts/p3041ds.dts b/arch/powerpc/dts/p3041ds.dts new file mode 100644 index 0000000000..c30bf7ac77 --- /dev/null +++ b/arch/powerpc/dts/p3041ds.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P3041DS Device Tree Source + * + * Copyright 2010 - 2015 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/include/ "p3041.dtsi" + +/ { + model = "fsl,P3041DS"; + compatible = "fsl,P3041DS"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + +}; diff --git a/arch/powerpc/dts/p4080.dtsi b/arch/powerpc/dts/p4080.dtsi new file mode 100644 index 0000000000..ab766803a3 --- /dev/null +++ b/arch/powerpc/dts/p4080.dtsi @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P4080/P4040 Silicon/SoC Device Tree Source (pre include) + * + * Copyright 2011 - 2015 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/dts-v1/; + +/include/ "e500mc_power_isa.dtsi" + +/ { + compatible = "fsl,P4080"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: PowerPC,e500mc@0 { + device_type = "cpu"; + reg = <0>; + fsl,portid-mapping = <0x80000000>; + }; + cpu1: PowerPC,e500mc@1 { + device_type = "cpu"; + reg = <1>; + fsl,portid-mapping = <0x40000000>; + }; + cpu2: PowerPC,e500mc@2 { + device_type = "cpu"; + reg = <2>; + fsl,portid-mapping = <0x20000000>; + }; + cpu3: PowerPC,e500mc@3 { + device_type = "cpu"; + reg = <3>; + fsl,portid-mapping = <0x10000000>; + }; + cpu4: PowerPC,e500mc@4 { + device_type = "cpu"; + reg = <4>; + fsl,portid-mapping = <0x08000000>; + }; + cpu5: PowerPC,e500mc@5 { + device_type = "cpu"; + reg = <5>; + fsl,portid-mapping = <0x04000000>; + }; + cpu6: PowerPC,e500mc@6 { + device_type = "cpu"; + reg = <6>; + fsl,portid-mapping = <0x02000000>; + }; + cpu7: PowerPC,e500mc@7 { + device_type = "cpu"; + reg = <7>; + fsl,portid-mapping = <0x01000000>; + }; + }; + + soc: soc@ffe000000 { + ranges = <0x00000000 0xf 0xfe000000 0x1000000>; + reg = <0xf 0xfe000000 0 0x00001000>; + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <4>; + reg = <0x40000 0x40000>; + compatible = "fsl,mpic", "chrp,open-pic"; + device_type = "open-pic"; + clock-frequency = <0x0>; + }; + }; + + pcie@ffe200000 { + compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */ + law_trgt_if = <0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe201000 { + compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */ + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe202000 { + compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */ + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; +}; diff --git a/arch/powerpc/dts/p4080ds.dts b/arch/powerpc/dts/p4080ds.dts new file mode 100644 index 0000000000..15a0f66fb6 --- /dev/null +++ b/arch/powerpc/dts/p4080ds.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P4080DS Device Tree Source + * + * Copyright 2011 - 2015 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/include/ "p4080.dtsi" + +/ { + model = "fsl,P4080DS"; + compatible = "fsl,P4080DS"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + +}; diff --git a/arch/powerpc/dts/p5040.dtsi b/arch/powerpc/dts/p5040.dtsi new file mode 100644 index 0000000000..8ab123dca4 --- /dev/null +++ b/arch/powerpc/dts/p5040.dtsi @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P5040 Silicon/SoC Device Tree Source (pre include) + * + * Copyright 2012 - 2015 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/dts-v1/; + +/include/ "e5500_power_isa.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: PowerPC,e5500@0 { + device_type = "cpu"; + reg = <0>; + fsl,portid-mapping = <0x80000000>; + }; + cpu1: PowerPC,e5500@1 { + device_type = "cpu"; + reg = <1>; + fsl,portid-mapping = <0x40000000>; + }; + cpu2: PowerPC,e5500@2 { + device_type = "cpu"; + reg = <2>; + fsl,portid-mapping = <0x20000000>; + }; + cpu3: PowerPC,e5500@3 { + device_type = "cpu"; + reg = <3>; + fsl,portid-mapping = <0x10000000>; + }; + }; + + soc: soc@ffe000000 { + ranges = <0x00000000 0xf 0xfe000000 0x1000000>; + reg = <0xf 0xfe000000 0 0x00001000>; + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <4>; + reg = <0x40000 0x40000>; + compatible = "fsl,mpic", "chrp,open-pic"; + device_type = "open-pic"; + clock-frequency = <0x0>; + }; + }; + + pcie@ffe200000 { + compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */ + law_trgt_if = <0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe201000 { + compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */ + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe202000 { + compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */ + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; +}; diff --git a/arch/powerpc/dts/p5040ds.dts b/arch/powerpc/dts/p5040ds.dts new file mode 100644 index 0000000000..723d31d5fb --- /dev/null +++ b/arch/powerpc/dts/p5040ds.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P5040DS Device Tree Source + * + * Copyright 2012 - 2015 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/include/ "p5040.dtsi" + +/ { + model = "fsl,P5040DS"; + compatible = "fsl,P5040DS"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + +}; diff --git a/arch/powerpc/dts/t1024rdb.dts b/arch/powerpc/dts/t1024rdb.dts new file mode 100644 index 0000000000..19a6652a23 --- /dev/null +++ b/arch/powerpc/dts/t1024rdb.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * T1024RDB Device Tree Source + * + * Copyright 2013 - 2015 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/include/ "t102x.dtsi" + +/ { + model = "fsl,T1024RDB"; + compatible = "fsl,T1024RDB"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; +}; diff --git a/arch/powerpc/dts/t102x.dtsi b/arch/powerpc/dts/t102x.dtsi new file mode 100644 index 0000000000..c49fd21088 --- /dev/null +++ b/arch/powerpc/dts/t102x.dtsi @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * T102X Silicon/SoC Device Tree Source (pre include) + * + * Copyright 2013 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/dts-v1/; + +/include/ "e5500_power_isa.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: PowerPC,e5500@0 { + device_type = "cpu"; + reg = <0>; + #cooling-cells = <2>; + }; + cpu1: PowerPC,e5500@1 { + device_type = "cpu"; + reg = <1>; + #cooling-cells = <2>; + }; + }; + + soc: soc@ffe000000 { + ranges = <0x00000000 0xf 0xfe000000 0x1000000>; + reg = <0xf 0xfe000000 0 0x00001000>; + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <4>; + reg = <0x40000 0x40000>; + compatible = "fsl,mpic", "chrp,open-pic"; + device_type = "open-pic"; + clock-frequency = <0x0>; + }; + }; + + pcie@ffe240000 { + compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe240000 0x0 0x1000>; /* registers */ + law_trgt_if = <0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; + + pcie@ffe250000 { + compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe250000 0x0 0x1000>; /* registers */ + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; + + pcie@ffe260000 { + compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe260000 0x0 0x1000>; /* registers */ + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; +}; diff --git a/arch/powerpc/dts/t1042d4rdb.dts b/arch/powerpc/dts/t1042d4rdb.dts new file mode 100644 index 0000000000..16a8ed4c79 --- /dev/null +++ b/arch/powerpc/dts/t1042d4rdb.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * T1042D4RDB Device Tree Source + * + * Copyright 2013 - 2015 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/include/ "t104x.dtsi" + +/ { + model = "fsl,T1042D4RDB"; + compatible = "fsl,T1042D4RDB"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; +}; diff --git a/arch/powerpc/dts/t104x.dtsi b/arch/powerpc/dts/t104x.dtsi new file mode 100644 index 0000000000..59989677a2 --- /dev/null +++ b/arch/powerpc/dts/t104x.dtsi @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * T104X Silicon/SoC Device Tree Source (pre include) + * + * Copyright 2013 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/dts-v1/; + +/include/ "e5500_power_isa.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: PowerPC,e5500@0 { + device_type = "cpu"; + reg = <0>; + #cooling-cells = <2>; + }; + cpu1: PowerPC,e5500@1 { + device_type = "cpu"; + reg = <1>; + #cooling-cells = <2>; + }; + cpu2: PowerPC,e5500@2 { + device_type = "cpu"; + reg = <2>; + #cooling-cells = <2>; + }; + cpu3: PowerPC,e5500@3 { + device_type = "cpu"; + reg = <3>; + #cooling-cells = <2>; + }; + }; + + soc: soc@ffe000000 { + ranges = <0x00000000 0xf 0xfe000000 0x1000000>; + reg = <0xf 0xfe000000 0 0x00001000>; + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <4>; + reg = <0x40000 0x40000>; + compatible = "fsl,mpic", "chrp,open-pic"; + device_type = "open-pic"; + clock-frequency = <0x0>; + }; + }; + + pcie@ffe240000 { + compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe240000 0x0 0x1000>; /* registers */ + law_trgt_if = <0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; + + pcie@ffe250000 { + compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe250000 0x0 0x1000>; /* registers */ + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; + + pcie@ffe260000 { + compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe260000 0x0 0x1000>; /* registers */ + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; + + pcie@ffe270000 { + compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe270000 0x0 0x1000>; /* registers */ + law_trgt_if = <3>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x30000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; +}; diff --git a/arch/powerpc/dts/t2080rdb.dts b/arch/powerpc/dts/t2080rdb.dts new file mode 100644 index 0000000000..49c1765b29 --- /dev/null +++ b/arch/powerpc/dts/t2080rdb.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * T2080RDB Device Tree Source + * + * Copyright 2013 - 2015 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/include/ "t2080.dtsi" + +/ { + model = "fsl,T2080RDB"; + compatible = "fsl,T2080RDB"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; +}; diff --git a/arch/powerpc/dts/t4240.dtsi b/arch/powerpc/dts/t4240.dtsi new file mode 100644 index 0000000000..fc34974c7f --- /dev/null +++ b/arch/powerpc/dts/t4240.dtsi @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * T4240 Silicon/SoC Device Tree Source (pre include) + * + * Copyright 2013 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/dts-v1/; + +/include/ "e6500_power_isa.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: PowerPC,e6500@0 { + device_type = "cpu"; + reg = <0 1>; + fsl,portid-mapping = <0x80000000>; + }; + cpu1: PowerPC,e6500@2 { + device_type = "cpu"; + reg = <2 3>; + fsl,portid-mapping = <0x80000000>; + }; + cpu2: PowerPC,e6500@4 { + device_type = "cpu"; + reg = <4 5>; + fsl,portid-mapping = <0x80000000>; + }; + cpu3: PowerPC,e6500@6 { + device_type = "cpu"; + reg = <6 7>; + fsl,portid-mapping = <0x80000000>; + }; + cpu4: PowerPC,e6500@8 { + device_type = "cpu"; + reg = <8 9>; + fsl,portid-mapping = <0x80000000>; + }; + cpu5: PowerPC,e6500@10 { + device_type = "cpu"; + reg = <10 11>; + fsl,portid-mapping = <0x80000000>; + }; + cpu6: PowerPC,e6500@12 { + device_type = "cpu"; + reg = <12 13>; + fsl,portid-mapping = <0x80000000>; + }; + cpu7: PowerPC,e6500@14 { + device_type = "cpu"; + reg = <14 15>; + fsl,portid-mapping = <0x80000000>; + }; + cpu8: PowerPC,e6500@16 { + device_type = "cpu"; + reg = <16 17>; + fsl,portid-mapping = <0x80000000>; + }; + cpu9: PowerPC,e6500@18 { + device_type = "cpu"; + reg = <18 19>; + fsl,portid-mapping = <0x80000000>; + }; + cpu10: PowerPC,e6500@20 { + device_type = "cpu"; + reg = <20 21>; + fsl,portid-mapping = <0x80000000>; + }; + cpu11: PowerPC,e6500@22 { + device_type = "cpu"; + reg = <22 23>; + fsl,portid-mapping = <0x80000000>; + }; + }; + + soc: soc@ffe000000 { + ranges = <0x00000000 0xf 0xfe000000 0x1000000>; + reg = <0xf 0xfe000000 0 0x00001000>; + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <4>; + reg = <0x40000 0x40000>; + compatible = "fsl,mpic"; + device_type = "open-pic"; + clock-frequency = <0x0>; + }; + }; + + pcie@ffe240000 { + compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe240000 0x0 0x4000>; /* registers */ + law_trgt_if = <0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe250000 { + compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe250000 0x0 0x4000>; /* registers */ + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe260000 { + compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe260000 0x0 0x4000>; /* registers */ + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe270000 { + compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe270000 0x0 0x4000>; /* registers */ + law_trgt_if = <3>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x60000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; +}; diff --git a/arch/powerpc/dts/t4240rdb.dts b/arch/powerpc/dts/t4240rdb.dts new file mode 100644 index 0000000000..f67d7ce2ae --- /dev/null +++ b/arch/powerpc/dts/t4240rdb.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * T4240RDB Device Tree Source + * + * Copyright 2013 - 2015 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/include/ "t4240.dtsi" + +/ { + model = "fsl,T4240RDB"; + compatible = "fsl,T4240RDB"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; +}; diff --git a/arch/powerpc/dts/u-boot.dtsi b/arch/powerpc/dts/u-boot.dtsi index 213d543c6d..9661f4dc88 100644 --- a/arch/powerpc/dts/u-boot.dtsi +++ b/arch/powerpc/dts/u-boot.dtsi @@ -24,6 +24,9 @@ #endif }; #ifdef CONFIG_MPC85XX_HAVE_RESET_VECTOR +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#endif powerpc-mpc85xx-bootpg-resetvec { offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>; }; diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 8cfc7d0faa..01975d7c60 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -113,6 +113,23 @@ config RISCV_SMODE endchoice +choice + prompt "SPL Run Mode" + default SPL_RISCV_MMODE + depends on SPL + +config SPL_RISCV_MMODE + bool "Machine" + help + Choose this option to build U-Boot SPL for RISC-V M-Mode. + +config SPL_RISCV_SMODE + bool "Supervisor" + help + Choose this option to build U-Boot SPL for RISC-V S-Mode. + +endchoice + config RISCV_ISA_C bool "Emit compressed instructions" default y @@ -132,34 +149,40 @@ config 64BIT config SIFIVE_CLINT bool - depends on RISCV_MMODE + depends on RISCV_MMODE || SPL_RISCV_MMODE select REGMAP select SYSCON + select SPL_REGMAP if SPL + select SPL_SYSCON if SPL help The SiFive CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. config ANDES_PLIC bool - depends on RISCV_MMODE + depends on RISCV_MMODE || SPL_RISCV_MMODE select REGMAP select SYSCON + select SPL_REGMAP if SPL + select SPL_SYSCON if SPL help The Andes PLIC block holds memory-mapped claim and pending registers associated with software interrupt. config ANDES_PLMT bool - depends on RISCV_MMODE + depends on RISCV_MMODE || SPL_RISCV_MMODE select REGMAP select SYSCON + select SPL_REGMAP if SPL + select SPL_SYSCON if SPL help The Andes PLMT block holds memory-mapped mtime register associated with timer tick. config RISCV_RDTIME bool - default y if RISCV_SMODE + default y if RISCV_SMODE || SPL_RISCV_SMODE help The provides the riscv_get_time() API that is implemented using the standard rdtime instruction. This is the case for S-mode U-Boot, and @@ -189,7 +212,7 @@ config NR_CPUS config SBI_IPI bool - default y if RISCV_SMODE + default y if RISCV_SMODE || SPL_RISCV_SMODE depends on SMP config XIP @@ -203,4 +226,7 @@ config STACK_SIZE_SHIFT int default 13 +config SPL_LDSCRIPT + default "arch/riscv/cpu/u-boot-spl.lds" + endmenu diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig index 6b4b92e692..f4b59cb71d 100644 --- a/arch/riscv/cpu/ax25/Kconfig +++ b/arch/riscv/cpu/ax25/Kconfig @@ -4,8 +4,8 @@ config RISCV_NDS imply CPU imply CPU_RISCV imply RISCV_TIMER - imply ANDES_PLIC if RISCV_MMODE - imply ANDES_PLMT if RISCV_MMODE + imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE) + imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE) help Run U-Boot on AndeStar V5 platforms and use some specific features which are provided by Andes Technology AndeStar V5 families. @@ -14,7 +14,7 @@ if RISCV_NDS config RISCV_NDS_CACHE bool "AndeStar V5 families specific cache support" - depends on RISCV_MMODE + depends on RISCV_MMODE || SPL_RISCV_MMODE help Provide Andes Technology AndeStar V5 families specific cache support. diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 5ca185745e..e457f6acbf 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -46,13 +46,13 @@ static inline bool supports_extension(char ext) return false; #else /* !CONFIG_CPU */ -#ifdef CONFIG_RISCV_MMODE +#if CONFIG_IS_ENABLED(RISCV_MMODE) return csr_read(CSR_MISA) & (1 << (ext - 'a')); -#else /* !CONFIG_RISCV_MMODE */ +#else /* !CONFIG_IS_ENABLED(RISCV_MMODE) */ #warning "There is no way to determine the available extensions in S-mode." #warning "Please convert your board to use the RISC-V CPU driver." return false; -#endif /* CONFIG_RISCV_MMODE */ +#endif /* CONFIG_IS_ENABLED(RISCV_MMODE) */ #endif /* CONFIG_CPU */ } diff --git a/arch/riscv/cpu/generic/Kconfig b/arch/riscv/cpu/generic/Kconfig index 1d6ab5032d..b2cb155d6d 100644 --- a/arch/riscv/cpu/generic/Kconfig +++ b/arch/riscv/cpu/generic/Kconfig @@ -8,5 +8,8 @@ config GENERIC_RISCV imply CPU imply CPU_RISCV imply RISCV_TIMER - imply SIFIVE_CLINT if RISCV_MMODE + imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE) imply CMD_CPU + imply SPL_CPU_SUPPORT + imply SPL_OPENSBI + imply SPL_LOAD_FIT diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index e06db404f5..b15209d623 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -39,7 +39,7 @@ secondary_harts_relocation_error: .section .text .globl _start _start: -#ifdef CONFIG_RISCV_MMODE +#if CONFIG_IS_ENABLED(RISCV_MMODE) csrr a0, CSR_MHARTID #endif @@ -62,7 +62,7 @@ _start: #ifdef CONFIG_SMP /* set xSIE bit to receive IPIs */ -#ifdef CONFIG_RISCV_MMODE +#if CONFIG_IS_ENABLED(RISCV_MMODE) li t0, MIE_MSIE #else li t0, SIE_SSIE @@ -75,7 +75,11 @@ _start: */ call_board_init_f: li t0, -16 +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) + li t1, CONFIG_SPL_STACK +#else li t1, CONFIG_SYS_INIT_SP_ADDR +#endif and sp, t1, t0 /* force 16 byte alignment */ call_board_init_f_0: @@ -159,7 +163,57 @@ wait_for_gd_init: mv a0, zero /* a0 <-- boot_flags = 0 */ la t5, board_init_f - jr t5 /* jump to board_init_f() */ + jalr t5 /* jump to board_init_f() */ + +#ifdef CONFIG_SPL_BUILD +spl_clear_bss: + la t0, __bss_start + la t1, __bss_end + beq t0, t1, spl_stack_gd_setup + +spl_clear_bss_loop: + SREG zero, 0(t0) + addi t0, t0, REGBYTES + bne t0, t1, spl_clear_bss_loop + +spl_stack_gd_setup: + jal spl_relocate_stack_gd + + /* skip setup if we did not relocate */ + beqz a0, spl_call_board_init_r + mv s0, a0 + + /* setup stack on main hart */ +#ifdef CONFIG_SMP + /* tp: hart id */ + slli t0, tp, CONFIG_STACK_SIZE_SHIFT + sub sp, s0, t0 +#else + mv sp, s0 +#endif + + /* set new stack and global data pointer on secondary harts */ +spl_secondary_hart_stack_gd_setup: + la a0, secondary_hart_relocate + mv a1, s0 + mv a2, s0 + jal smp_call_function + + /* hang if relocation of secondary harts has failed */ + beqz a0, 1f + mv a1, a0 + la a0, secondary_harts_relocation_error + jal printf + jal hang + + /* set new global data pointer on main hart */ +1: mv gp, s0 + +spl_call_board_init_r: + mv a0, zero + mv a1, zero + jal board_init_r +#endif /* * void relocate_code (addr_sp, gd, addr_moni) @@ -344,7 +398,7 @@ secondary_hart_loop: #ifdef CONFIG_SMP csrr t0, MODE_PREFIX(ip) -#ifdef CONFIG_RISCV_MMODE +#if CONFIG_IS_ENABLED(RISCV_MMODE) andi t0, t0, MIE_MSIE #else andi t0, t0, SIE_SSIE diff --git a/arch/riscv/cpu/u-boot-spl.lds b/arch/riscv/cpu/u-boot-spl.lds new file mode 100644 index 0000000000..32255d58de --- /dev/null +++ b/arch/riscv/cpu/u-boot-spl.lds @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Based on arch/riscv/cpu/u-boot.lds, which is + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation <rick@andestech.com> + * + * and arch/mips/cpu/u-boot-spl.lds. + */ +MEMORY { .spl_mem : ORIGIN = IMAGE_TEXT_BASE, LENGTH = IMAGE_MAX_SIZE } +MEMORY { .bss_mem : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + +OUTPUT_ARCH("riscv") +ENTRY(_start) + +SECTIONS +{ + . = ALIGN(4); + .text : { + arch/riscv/cpu/start.o (.text) + *(.text*) + } > .spl_mem + + . = ALIGN(4); + .rodata : { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } > .spl_mem + + . = ALIGN(4); + .data : { + *(.data*) + } > .spl_mem + . = ALIGN(4); + + .got : { + __got_start = .; + *(.got.plt) *(.got) + __got_end = .; + } > .spl_mem + + . = ALIGN(4); + + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } > .spl_mem + + . = ALIGN(4); + + .binman_sym_table : { + __binman_sym_start = .; + KEEP(*(SORT(.binman_sym*))); + __binman_sym_end = .; + } > .spl_mem + + . = ALIGN(4); + + /DISCARD/ : { *(.rela.plt*) } + .rela.dyn : { + __rel_dyn_start = .; + *(.rela*) + __rel_dyn_end = .; + } > .spl_mem + + . = ALIGN(4); + + .dynsym : { + __dyn_sym_start = .; + *(.dynsym) + __dyn_sym_end = .; + } > .spl_mem + + . = ALIGN(4); + + _end = .; + + .bss : { + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end = .; + } > .bss_mem +} diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h index c450eb9103..a0695da936 100644 --- a/arch/riscv/include/asm/encoding.h +++ b/arch/riscv/include/asm/encoding.h @@ -9,7 +9,7 @@ #include <asm/csr.h> -#ifdef CONFIG_RISCV_SMODE +#if CONFIG_IS_ENABLED(RISCV_SMODE) #define MODE_PREFIX(__suffix) s##__suffix #else #define MODE_PREFIX(__suffix) m##__suffix diff --git a/arch/riscv/include/asm/spl.h b/arch/riscv/include/asm/spl.h new file mode 100644 index 0000000000..45c03fb9b6 --- /dev/null +++ b/arch/riscv/include/asm/spl.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Based on arch/mips/include/asm/spl.h. + * + * (C) Copyright 2012 + * Texas Instruments, <www.ti.com> + */ +#ifndef _ASM_RISCV_SPL_H_ +#define _ASM_RISCV_SPL_H_ + +enum { + BOOT_DEVICE_RAM, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_MMC2_2, + BOOT_DEVICE_NAND, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_NOR, + BOOT_DEVICE_UART, + BOOT_DEVICE_SPI, + BOOT_DEVICE_USB, + BOOT_DEVICE_SATA, + BOOT_DEVICE_I2C, + BOOT_DEVICE_BOARD, + BOOT_DEVICE_DFU, + BOOT_DEVICE_XIP, + BOOT_DEVICE_BOOTROM, + BOOT_DEVICE_NONE +}; + +#endif diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 6ae6ebbeaf..c9179a5ff8 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -10,15 +10,19 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o obj-$(CONFIG_CMD_GO) += boot.o obj-y += cache.o -obj-$(CONFIG_RISCV_RDTIME) += rdtime.o +ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y) obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o obj-$(CONFIG_ANDES_PLIC) += andes_plic.o obj-$(CONFIG_ANDES_PLMT) += andes_plmt.o +else +obj-$(CONFIG_RISCV_RDTIME) += rdtime.o +obj-$(CONFIG_SBI_IPI) += sbi_ipi.o +endif obj-y += interrupts.o obj-y += reset.o -obj-$(CONFIG_SBI_IPI) += sbi_ipi.o obj-y += setjmp.o obj-$(CONFIG_SMP) += smp.o +obj-$(CONFIG_SPL_BUILD) += spl.o # For building EFI apps CFLAGS_$(EFI_CRT0) := $(CFLAGS_EFI) diff --git a/arch/riscv/lib/mkimage_fit_opensbi.sh b/arch/riscv/lib/mkimage_fit_opensbi.sh new file mode 100755 index 0000000000..d6f95e5bfd --- /dev/null +++ b/arch/riscv/lib/mkimage_fit_opensbi.sh @@ -0,0 +1,100 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0+ +# +# script to generate FIT image source for RISC-V boards with OpenSBI +# and, optionally, multiple device trees (given on the command line). +# +# usage: $0 [<dt_name> [<dt_name] ...] + +[ -z "$OPENSBI" ] && OPENSBI="fw_dynamic.bin" + +if [ -z "$UBOOT_LOAD_ADDR" ]; then + UBOOT_LOAD_ADDR="$(grep "^CONFIG_SYS_TEXT_BASE=" .config | awk 'BEGIN{FS="="} {print $2}')" +fi + +if [ -z "$OPENSBI_LOAD_ADDR" ]; then + OPENSBI_LOAD_ADDR="$(grep "^CONFIG_SPL_OPENSBI_LOAD_ADDR=" .config | awk 'BEGIN{FS="="} {print $2}')" +fi + +if [ ! -f $OPENSBI ]; then + echo "WARNING: OpenSBI binary \"$OPENSBI\" not found, resulting binary is not functional." >&2 + OPENSBI=/dev/null +fi + +cat << __HEADER_EOF +/dts-v1/; + +/ { + description = "Configuration to load OpenSBI before U-Boot"; + + images { + uboot { + description = "U-Boot"; + data = /incbin/("u-boot-nodtb.bin"); + type = "standalone"; + os = "U-Boot"; + arch = "riscv"; + compression = "none"; + load = <$UBOOT_LOAD_ADDR>; + }; + opensbi { + description = "RISC-V OpenSBI"; + data = /incbin/("$OPENSBI"); + type = "firmware"; + os = "opensbi"; + arch = "riscv"; + compression = "none"; + load = <$OPENSBI_LOAD_ADDR>; + entry = <$OPENSBI_LOAD_ADDR>; + }; +__HEADER_EOF + +cnt=1 +for dtname in $* +do + cat << __FDT_IMAGE_EOF + fdt_$cnt { + description = "$(basename $dtname .dtb)"; + data = /incbin/("$dtname"); + type = "flat_dt"; + compression = "none"; + }; +__FDT_IMAGE_EOF +cnt=$((cnt+1)) +done + +cat << __CONF_HEADER_EOF + }; + configurations { + default = "config_1"; + +__CONF_HEADER_EOF + +if [ $# -eq 0 ]; then +cat << __CONF_SECTION_EOF + config_1 { + description = "U-Boot FIT"; + firmware = "opensbi"; + loadables = "uboot"; + }; +__CONF_SECTION_EOF +else +cnt=1 +for dtname in $* +do +cat << __CONF_SECTION_EOF + config_$cnt { + description = "$(basename $dtname .dtb)"; + firmware = "opensbi"; + loadables = "uboot"; + fdt = "fdt_$cnt"; + }; +__CONF_SECTION_EOF +cnt=$((cnt+1)) +done +fi + +cat << __ITS_EOF + }; +}; +__ITS_EOF diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c new file mode 100644 index 0000000000..bea8695987 --- /dev/null +++ b/arch/riscv/lib/spl.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Fraunhofer AISEC, + * Lukas Auer <lukas.auer@aisec.fraunhofer.de> + */ +#include <common.h> +#include <spl.h> +#include <asm/smp.h> + +DECLARE_GLOBAL_DATA_PTR; + +__weak void board_init_f(ulong dummy) +{ + int ret; + + ret = spl_early_init(); + if (ret) + panic("spl_early_init() failed: %d\n", ret); + + arch_cpu_init_dm(); + + preloader_console_init(); +} + +void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +{ + typedef void __noreturn (*image_entry_riscv_t)(ulong hart, void *dtb); + void *fdt_blob; + int ret; + +#if CONFIG_IS_ENABLED(LOAD_FIT) || CONFIG_IS_ENABLED(LOAD_FIT_FULL) + fdt_blob = spl_image->fdt_addr; +#else + fdt_blob = (void *)gd->fdt_blob; +#endif + + image_entry_riscv_t image_entry = + (image_entry_riscv_t)spl_image->entry_point; + invalidate_icache_all(); + + debug("image entry point: 0x%lX\n", spl_image->entry_point); +#ifdef CONFIG_SMP + ret = smp_call_function(spl_image->entry_point, (ulong)fdt_blob, 0); + if (ret) + hang(); +#endif + image_entry(gd->arch.boot_hart, fdt_blob); +} diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig index e05f353b80..9014418433 100644 --- a/board/armltd/vexpress64/Kconfig +++ b/board/armltd/vexpress64/Kconfig @@ -1,4 +1,4 @@ -if TARGET_VEXPRESS64_BASE_FVP || TARGET_VEXPRESS64_JUNO || TARGET_VEXPRESS64_BASE_FVP_DRAM +if TARGET_VEXPRESS64_BASE_FVP || TARGET_VEXPRESS64_JUNO config SYS_BOARD default "vexpress64" diff --git a/board/armltd/vexpress64/MAINTAINERS b/board/armltd/vexpress64/MAINTAINERS index 15b0a08646..0ba044d7ff 100644 --- a/board/armltd/vexpress64/MAINTAINERS +++ b/board/armltd/vexpress64/MAINTAINERS @@ -10,11 +10,6 @@ M: Linus Walleij <linus.walleij@linaro.org> S: Maintained F: configs/vexpress_aemv8a_semi_defconfig -VEXPRESS_AEMV8A_DRAM BOARD -M: Ryan Harkin <ryan.harkin@linaro.org> -S: Maintained -F: configs/vexpress_aemv8a_dram_defconfig - JUNO DEVELOPMENT PLATFORM BOARD M: Linus Walleij <linus.walleij@linaro.org> S: Maintained diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index 6cc7c31dc6..7ce12018e7 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -13,13 +13,22 @@ config SYS_CONFIG_NAME default "qemu-riscv" config SYS_TEXT_BASE + default 0x81200000 if SPL default 0x80000000 if !RISCV_SMODE default 0x80200000 if RISCV_SMODE && ARCH_RV64I default 0x80400000 if RISCV_SMODE && ARCH_RV32I +config SPL_TEXT_BASE + default 0x80000000 + +config SPL_OPENSBI_LOAD_ADDR + hex + default 0x81000000 + config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select GENERIC_RISCV + select SUPPORT_SPL imply SYS_NS16550 imply VIRTIO_MMIO imply VIRTIO_NET @@ -43,5 +52,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply CMD_PCI imply E1000 imply NVME + imply SPL_RAM_SUPPORT + imply SPL_RAM_DEVICE endif diff --git a/board/emulation/qemu-riscv/MAINTAINERS b/board/emulation/qemu-riscv/MAINTAINERS index c701c83d77..78969ed6bd 100644 --- a/board/emulation/qemu-riscv/MAINTAINERS +++ b/board/emulation/qemu-riscv/MAINTAINERS @@ -5,5 +5,7 @@ F: board/emulation/qemu-riscv/ F: include/configs/qemu-riscv.h F: configs/qemu-riscv32_defconfig F: configs/qemu-riscv32_smode_defconfig +F: configs/qemu-riscv32_spl_defconfig F: configs/qemu-riscv64_defconfig F: configs/qemu-riscv64_smode_defconfig +F: configs/qemu-riscv64_spl_defconfig diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c index 49e304f7eb..37d48d04f2 100644 --- a/board/emulation/qemu-riscv/qemu-riscv.c +++ b/board/emulation/qemu-riscv/qemu-riscv.c @@ -7,6 +7,7 @@ #include <dm.h> #include <env.h> #include <fdtdec.h> +#include <spl.h> #include <virtio_types.h> #include <virtio.h> @@ -88,3 +89,19 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } + +#ifdef CONFIG_SPL +u32 spl_boot_device(void) +{ + /* RISC-V QEMU only supports RAM as SPL boot device */ + return BOOT_DEVICE_RAM; +} +#endif + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* boot using first FIT config */ + return 0; +} +#endif diff --git a/board/freescale/common/cds_pci_ft.c b/board/freescale/common/cds_pci_ft.c index 3ff2fa416b..fb2e5c7bf3 100644 --- a/board/freescale/common/cds_pci_ft.c +++ b/board/freescale/common/cds_pci_ft.c @@ -9,6 +9,7 @@ #include "cadmus.h" #if defined(CONFIG_OF_BOARD_SETUP) +#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI) static void cds_pci_fixup(void *blob) { int node; @@ -61,11 +62,12 @@ static void cds_pci_fixup(void *blob) } } } +#endif int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI +#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI) ft_pci_setup(blob, bd); cds_pci_fixup(blob); #endif diff --git a/board/freescale/common/emc2305.c b/board/freescale/common/emc2305.c index 8523084da9..b1ca051db2 100644 --- a/board/freescale/common/emc2305.c +++ b/board/freescale/common/emc2305.c @@ -24,10 +24,22 @@ void set_fan_speed(u8 data) I2C_EMC2305_FAN5}; for (index = 0; index < NUM_OF_FANS; index++) { +#ifndef CONFIG_DM_I2C if (i2c_write(I2C_EMC2305_ADDR, Fan[index], 1, &data, 1) != 0) { printf("Error: failed to change fan speed @%x\n", Fan[index]); } +#else + struct udevice *dev; + + if (i2c_get_chip_for_busnum(0, I2C_EMC2305_ADDR, 1, &dev)) + continue; + + if (dm_i2c_write(dev, Fan[index], &data, 1) != 0) { + printf("Error: failed to change fan speed @%x\n", + Fan[index]); + } +#endif } } @@ -36,6 +48,15 @@ void emc2305_init(void) u8 data; data = I2C_EMC2305_CMD; +#ifndef CONFIG_DM_I2C if (i2c_write(I2C_EMC2305_ADDR, I2C_EMC2305_CONF, 1, &data, 1) != 0) printf("Error: failed to configure EMC2305\n"); +#else + struct udevice *dev; + + if (!i2c_get_chip_for_busnum(0, I2C_EMC2305_ADDR, 1, &dev)) + if (dm_i2c_write(dev, I2C_EMC2305_CONF, &data, 1)) + printf("Error: failed to configure EMC2305\n"); +#endif + } diff --git a/board/freescale/common/p_corenet/pci.c b/board/freescale/common/p_corenet/pci.c index a2df928fc5..a6abe66dc0 100644 --- a/board/freescale/common/p_corenet/pci.c +++ b/board/freescale/common/p_corenet/pci.c @@ -11,6 +11,7 @@ #include <fdt_support.h> #include <asm/fsl_serdes.h> +#if !defined(CONFIG_DM_PCI) void pci_init_board(void) { fsl_pcie_init_board(0); @@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd) { FT_FSL_PCI_SETUP; } +#endif diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index f1b98bcd2a..716c93b2c2 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -21,16 +21,40 @@ #define QIXIS_LBMAP_BRDCFG_REG 0x00 #endif +#ifndef QIXIS_RCFG_CTL_RECONFIG_IDLE +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#endif +#ifndef QIXIS_RCFG_CTL_RECONFIG_START +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#endif + #ifdef CONFIG_SYS_I2C_FPGA_ADDR u8 qixis_read_i2c(unsigned int reg) { +#ifndef CONFIG_DM_I2C return i2c_reg_read(CONFIG_SYS_I2C_FPGA_ADDR, reg); +#else + struct udevice *dev; + + if (i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev)) + return 0xff; + + return dm_i2c_reg_read(dev, reg); +#endif } void qixis_write_i2c(unsigned int reg, u8 value) { u8 val = value; +#ifndef CONFIG_DM_I2C i2c_reg_write(CONFIG_SYS_I2C_FPGA_ADDR, reg, val); +#else + struct udevice *dev; + + if (!i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev)) + dm_i2c_reg_write(dev, reg, val); +#endif + } #endif @@ -142,11 +166,13 @@ static void qixis_reset(void) QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET); } +#ifdef QIXIS_LBMAP_ALTBANK static void qixis_bank_reset(void) { QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); } +#endif static void __maybe_unused set_lbmap(int lbmap) { @@ -159,12 +185,16 @@ static void __maybe_unused set_lbmap(int lbmap) static void __maybe_unused set_rcw_src(int rcw_src) { +#ifdef CONFIG_NXP_LSCH3_2 + QIXIS_WRITE(dutcfg[0], (rcw_src & 0xff)); +#else u8 reg; reg = QIXIS_READ(dutcfg[1]); reg = (reg & ~1) | (rcw_src & 1); QIXIS_WRITE(dutcfg[1], reg); QIXIS_WRITE(dutcfg[0], (rcw_src >> 1) & 0xff); +#endif } static void qixis_dump_regs(void) @@ -210,16 +240,20 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar set_lbmap(QIXIS_LBMAP_DFLTBANK); qixis_reset(); } else if (strcmp(argv[1], "altbank") == 0) { +#ifdef QIXIS_LBMAP_ALTBANK set_lbmap(QIXIS_LBMAP_ALTBANK); qixis_bank_reset(); +#else + printf("No Altbank!\n"); +#endif } else if (strcmp(argv[1], "nand") == 0) { #ifdef QIXIS_LBMAP_NAND QIXIS_WRITE(rst_ctl, 0x30); QIXIS_WRITE(rcfg_ctl, 0); set_lbmap(QIXIS_LBMAP_NAND); set_rcw_src(QIXIS_RCW_SRC_NAND); - QIXIS_WRITE(rcfg_ctl, 0x20); - QIXIS_WRITE(rcfg_ctl, 0x21); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); #else printf("Not implemented\n"); #endif @@ -233,8 +267,8 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar set_lbmap(QIXIS_LBMAP_SD); set_rcw_src(QIXIS_RCW_SRC_SD); #endif - QIXIS_WRITE(rcfg_ctl, 0x20); - QIXIS_WRITE(rcfg_ctl, 0x21); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); #else printf("Not implemented\n"); #endif @@ -244,8 +278,8 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar QIXIS_WRITE(rcfg_ctl, 0); set_lbmap(QIXIS_LBMAP_IFC); set_rcw_src(QIXIS_RCW_SRC_IFC); - QIXIS_WRITE(rcfg_ctl, 0x20); - QIXIS_WRITE(rcfg_ctl, 0x21); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); #else printf("Not implemented\n"); #endif @@ -255,8 +289,8 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar QIXIS_WRITE(rcfg_ctl, 0); set_lbmap(QIXIS_LBMAP_EMMC); set_rcw_src(QIXIS_RCW_SRC_EMMC); - QIXIS_WRITE(rcfg_ctl, 0x20); - QIXIS_WRITE(rcfg_ctl, 0x21); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); #else printf("Not implemented\n"); #endif @@ -266,8 +300,10 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar QIXIS_WRITE(rcfg_ctl, 0); set_lbmap(QIXIS_LBMAP_SD_QSPI); set_rcw_src(QIXIS_RCW_SRC_SD); - qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20); - qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), + QIXIS_RCFG_CTL_RECONFIG_IDLE); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), + QIXIS_RCFG_CTL_RECONFIG_START); #else printf("Not implemented\n"); #endif @@ -277,8 +313,10 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar QIXIS_WRITE(rcfg_ctl, 0); set_lbmap(QIXIS_LBMAP_QSPI); set_rcw_src(QIXIS_RCW_SRC_QSPI); - qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20); - qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), + QIXIS_RCFG_CTL_RECONFIG_IDLE); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), + QIXIS_RCFG_CTL_RECONFIG_START); #else printf("Not implemented\n"); #endif diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index 510d7c266b..bb655ca744 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -149,23 +149,42 @@ static int read_eeprom(void) { int ret; #ifdef CONFIG_SYS_EEPROM_BUS_NUM +#ifndef CONFIG_DM_I2C unsigned int bus; #endif +#endif if (has_been_read) return 0; #ifdef CONFIG_SYS_EEPROM_BUS_NUM +#ifndef CONFIG_DM_I2C bus = i2c_get_bus_num(); i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); #endif +#endif - ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, - (void *)&e, sizeof(e)); +#ifndef CONFIG_DM_I2C + ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + (void *)&e, sizeof(e)); +#else + struct udevice *dev; +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, + CONFIG_SYS_I2C_EEPROM_ADDR, 1, &dev); +#else + ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, 1, &dev); +#endif + if (!ret) + ret = dm_i2c_read(dev, 0, (void *)&e, sizeof(e)); +#endif #ifdef CONFIG_SYS_EEPROM_BUS_NUM +#ifndef CONFIG_DM_I2C i2c_set_bus_num(bus); #endif +#endif #ifdef DEBUG show_eeprom(); @@ -199,8 +218,10 @@ static int prog_eeprom(void) int i; void *p; #ifdef CONFIG_SYS_EEPROM_BUS_NUM +#ifndef CONFIG_DM_I2C unsigned int bus; #endif +#endif /* Set the reserved values to 0xFF */ #ifdef CONFIG_SYS_I2C_EEPROM_NXID @@ -211,10 +232,12 @@ static int prog_eeprom(void) #endif update_crc(); +#ifndef CONFIG_DM_I2C #ifdef CONFIG_SYS_EEPROM_BUS_NUM bus = i2c_get_bus_num(); i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); #endif +#endif /* * The AT24C02 datasheet says that data can only be written in page @@ -222,8 +245,26 @@ static int prog_eeprom(void) * complete a given write. */ for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) { - ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, +#ifndef CONFIG_DM_I2C + ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, p, min((int)(sizeof(e) - i), 8)); +#else + struct udevice *dev; +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, + CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + &dev); +#else + ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + &dev); +#endif + if (!ret) + ret = dm_i2c_write(dev, i, p, min((int)(sizeof(e) - i), + 8)); +#endif if (ret) break; udelay(5000); /* 5ms write cycle timing */ @@ -233,15 +274,34 @@ static int prog_eeprom(void) /* Verify the write by reading back the EEPROM and comparing */ struct eeprom e2; +#ifndef CONFIG_DM_I2C ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (void *)&e2, sizeof(e2)); + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + (void *)&e2, sizeof(e2)); +#else + struct udevice *dev; +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, + CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + &dev); +#else + ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + &dev); +#endif + if (!ret) + ret = dm_i2c_read(dev, 0, (void *)&e2, sizeof(e2)); +#endif if (!ret && memcmp(&e, &e2, sizeof(e))) ret = -1; } +#ifndef CONFIG_DM_I2C #ifdef CONFIG_SYS_EEPROM_BUS_NUM i2c_set_bus_num(bus); #endif +#endif if (ret) { printf("Programming failed.\n"); @@ -529,8 +589,24 @@ unsigned int get_cpu_board_revision(void) u8 minor; /* 0x05 Board revision, minor */ } be; +#ifndef CONFIG_DM_I2C i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (void *)&be, sizeof(be)); +#else + struct udevice *dev; +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, + CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + &dev); +#else + ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + &dev) +#endif + if (!ret) + dm_i2c_read(dev, 0, (void *)&be, sizeof(be)); +#endif if (be.id != (('C' << 24) | ('C' << 16) | ('I' << 8) | 'D')) return MPC85XX_CPU_BOARD_REV(0, 0); diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index b804971981..b37f3bf4f8 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -61,13 +61,23 @@ static int find_ir_chip_on_i2c(void) u8 byte; int i; const int ir_i2c_addr[] = {0x38, 0x08, 0x09}; +#ifdef CONFIG_DM_I2C + struct udevice *dev; +#endif /* Check all the address */ for (i = 0; i < (sizeof(ir_i2c_addr)/sizeof(ir_i2c_addr[0])); i++) { i2caddress = ir_i2c_addr[i]; +#ifndef CONFIG_DM_I2C ret = i2c_read(i2caddress, IR36021_MFR_ID_OFFSET, 1, (void *)&byte, sizeof(byte)); +#else + ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev); + if (!ret) + ret = dm_i2c_read(dev, IR36021_MFR_ID_OFFSET, + (void *)&byte, sizeof(byte)); +#endif if ((ret >= 0) && (byte == IR36021_MFR_ID)) return i2caddress; } @@ -103,11 +113,21 @@ static int read_voltage_from_INA220(int i2caddress) int i, ret, voltage_read = 0; u16 vol_mon; u8 buf[2]; +#ifdef CONFIG_DM_I2C + struct udevice *dev; +#endif for (i = 0; i < NUM_READINGS; i++) { +#ifndef CONFIG_DM_I2C ret = i2c_read(I2C_VOL_MONITOR_ADDR, I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&buf, 2); +#else + ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev); + if (!ret) + ret = dm_i2c_read(dev, I2C_VOL_MONITOR_BUS_V_OFFSET, + (void *)&buf, 2); +#endif if (ret) { printf("VID: failed to read core voltage\n"); return ret; @@ -136,11 +156,21 @@ static int read_voltage_from_IR(int i2caddress) int i, ret, voltage_read = 0; u16 vol_mon; u8 buf; +#ifdef CONFIG_DM_I2C + struct udevice *dev; +#endif for (i = 0; i < NUM_READINGS; i++) { +#ifndef CONFIG_DM_I2C ret = i2c_read(i2caddress, IR36021_LOOP1_VOUT_OFFSET, 1, (void *)&buf, 1); +#else + ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev); + if (!ret) + ret = dm_i2c_read(dev, IR36021_LOOP1_VOUT_OFFSET, + (void *)&buf, 1); +#endif if (ret) { printf("VID: failed to read vcpu\n"); return ret; @@ -179,17 +209,33 @@ static int read_voltage_from_LTC(int i2caddress) int ret, vcode = 0; u8 chan = PWM_CHANNEL0; +#ifndef CONFIG_DM_I2C /* select the PAGE 0 using PMBus commands PAGE for VDD*/ ret = i2c_write(I2C_VOL_MONITOR_ADDR, PMBUS_CMD_PAGE, 1, &chan, 1); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev); + if (!ret) + ret = dm_i2c_write(dev, PMBUS_CMD_PAGE, &chan, 1); +#endif if (ret) { printf("VID: failed to select VDD Page 0\n"); return ret; } +#ifndef CONFIG_DM_I2C /*read the output voltage using PMBus command READ_VOUT*/ ret = i2c_read(I2C_VOL_MONITOR_ADDR, PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2); +#else + ret = dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2); + if (ret) { + printf("VID: failed to read the volatge\n"); + return ret; + } +#endif if (ret) { printf("VID: failed to read the volatge\n"); return ret; @@ -294,8 +340,18 @@ static int set_voltage_to_IR(int i2caddress, int vdd) vid = DIV_ROUND_UP(vdd - 245, 5); #endif +#ifndef CONFIG_DM_I2C ret = i2c_write(i2caddress, IR36021_LOOP1_MANUAL_ID_OFFSET, 1, (void *)&vid, sizeof(vid)); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev); + if (!ret) + ret = dm_i2c_write(dev, IR36021_LOOP1_MANUAL_ID_OFFSET, + (void *)&vid, sizeof(vid)); + +#endif if (ret) { printf("VID: failed to write VID\n"); return -1; @@ -331,8 +387,17 @@ static int set_voltage_to_LTC(int i2caddress, int vdd) vdd & 0xFF, (vdd & 0xFF00) >> 8}; /* Write the desired voltage code to the regulator */ +#ifndef CONFIG_DM_I2C ret = i2c_write(I2C_VOL_MONITOR_ADDR, PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev); + if (!ret) + ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE, + (void *)&buff, 5); +#endif if (ret) { printf("VID: I2C failed to write to the volatge regulator\n"); return -1; @@ -516,14 +581,24 @@ int adjust_vdd(ulong vdd_override) } /* check IR chip work on Intel mode*/ +#ifndef CONFIG_DM_I2C ret = i2c_read(i2caddress, IR36021_INTEL_MODE_OOFSET, 1, (void *)&buf, 1); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev); + if (!ret) + ret = dm_i2c_read(dev, IR36021_INTEL_MODE_OOFSET, + (void *)&buf, 1); +#endif if (ret) { printf("VID: failed to read IR chip mode.\n"); ret = -1; goto exit; } + if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) { printf("VID: IR Chip is not used in Intel mode.\n"); ret = -1; @@ -688,9 +763,18 @@ int adjust_vdd(ulong vdd_override) } /* check IR chip work on Intel mode*/ +#ifndef CONFIG_DM_I2C ret = i2c_read(i2caddress, IR36021_INTEL_MODE_OOFSET, 1, (void *)&buf, 1); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev); + if (!ret) + ret = dm_i2c_read(dev, IR36021_INTEL_MODE_OOFSET, + (void *)&buf, 1); +#endif if (ret) { printf("VID: failed to read IR chip mode.\n"); ret = -1; diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c index 4aa7cec9ce..095971448f 100644 --- a/board/freescale/ls1028a/ls1028a.c +++ b/board/freescale/ls1028a/ls1028a.c @@ -13,6 +13,7 @@ #include <linux/libfdt.h> #include <env_internal.h> #include <asm/arch-fsl-layerscape/soc.h> +#include <asm/arch-fsl-layerscape/fsl_icid.h> #include <i2c.h> #include <asm/arch/soc.h> #ifdef CONFIG_FSL_LS_PPA @@ -73,7 +74,15 @@ int board_init(void) #if defined(CONFIG_TARGET_LS1028ARDB) u8 val = I2C_MUX_CH_DEFAULT; +#ifndef CONFIG_DM_I2C i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1); +#else + struct udevice *dev; + + if (!i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev)) + dm_i2c_write(dev, 0x0b, &val, 1); +#endif + #endif return 0; } @@ -135,6 +144,8 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory_banks(blob, base, size, 2); + fdt_fixup_icid(blob); + return 0; } #endif diff --git a/board/freescale/ls1088a/eth_ls1088aqds.c b/board/freescale/ls1088a/eth_ls1088aqds.c index d4ab9791e9..237088a537 100644 --- a/board/freescale/ls1088a/eth_ls1088aqds.c +++ b/board/freescale/ls1088a/eth_ls1088aqds.c @@ -81,11 +81,16 @@ struct ls1088a_qds_mdio { struct mii_dev *realbus; }; +struct reg_pair { + uint addr; + u8 *val; +}; + static void sgmii_configure_repeater(int dpmac) { struct mii_dev *bus; uint8_t a = 0xf; - int i, j, ret; + int i, j, k, ret; unsigned short value; const char *dev = "LS1088A_QDS_MDIO2"; int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b}; @@ -97,8 +102,28 @@ static void sgmii_configure_repeater(int dpmac) uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7}; uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84}; + u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20}; + struct reg_pair reg_pair[10] = { + {6, ®_val[0]}, {4, ®_val[1]}, + {8, ®_val[2]}, {0xf, NULL}, + {0x11, NULL}, {0x16, NULL}, + {0x18, NULL}, {0x23, ®_val[3]}, + {0x2d, ®_val[4]}, {4, ®_val[5]}, + }; +#ifdef CONFIG_DM_I2C + struct udevice *udev; +#endif + /* Set I2c to Slot 1 */ - i2c_write(0x77, 0, 0, &a, 1); +#ifndef CONFIG_DM_I2C + ret = i2c_write(0x77, 0, 0, &a, 1); +#else + ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, 0, &a, 1); +#endif + if (ret) + goto error; switch (dpmac) { case 1: @@ -144,31 +169,34 @@ static void sgmii_configure_repeater(int dpmac) return; } +#ifdef CONFIG_DM_I2C + i2c_get_chip_for_busnum(0, i2c_phy_addr, 1, &udev); +#endif + for (i = 0; i < 4; i++) { for (j = 0; j < 4; j++) { - a = 0x18; - i2c_write(i2c_phy_addr, 6, 1, &a, 1); - a = 0x38; - i2c_write(i2c_phy_addr, 4, 1, &a, 1); - a = 0x4; - i2c_write(i2c_phy_addr, 8, 1, &a, 1); - - i2c_write(i2c_phy_addr, 0xf, 1, - &ch_a_eq[i], 1); - i2c_write(i2c_phy_addr, 0x11, 1, - &ch_a_ctl2[j], 1); - - i2c_write(i2c_phy_addr, 0x16, 1, - &ch_b_eq[i], 1); - i2c_write(i2c_phy_addr, 0x18, 1, - &ch_b_ctl2[j], 1); - - a = 0x14; - i2c_write(i2c_phy_addr, 0x23, 1, &a, 1); - a = 0xb5; - i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1); - a = 0x20; - i2c_write(i2c_phy_addr, 4, 1, &a, 1); + reg_pair[3].val = &ch_a_eq[i]; + reg_pair[4].val = &ch_a_ctl2[j]; + reg_pair[5].val = &ch_b_eq[i]; + reg_pair[6].val = &ch_b_ctl2[j]; + for (k = 0; k < 10; k++) { +#ifndef CONFIG_DM_I2C + ret = i2c_write(i2c_phy_addr, + reg_pair[k].addr, + 1, reg_pair[k].val, 1); +#else + ret = i2c_get_chip_for_busnum(0, + i2c_phy_addr, + 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, + reg_pair[k].addr, + reg_pair[k].val, 1); +#endif + if (ret) + goto error; + } + mdelay(100); ret = miiphy_read(dev, phy_addr, 0x11, &value); if (ret > 0) @@ -203,7 +231,7 @@ error: static void qsgmii_configure_repeater(int dpmac) { uint8_t a = 0xf; - int i, j; + int i, j, k; int i2c_phy_addr = 0; int phy_addr = 0; int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b}; @@ -213,12 +241,32 @@ static void qsgmii_configure_repeater(int dpmac) uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7}; uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84}; + u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20}; + struct reg_pair reg_pair[10] = { + {6, ®_val[0]}, {4, ®_val[1]}, + {8, ®_val[2]}, {0xf, NULL}, + {0x11, NULL}, {0x16, NULL}, + {0x18, NULL}, {0x23, ®_val[3]}, + {0x2d, ®_val[4]}, {4, ®_val[5]}, + }; + const char *dev = mdio_names[EMI1_SLOT1]; int ret = 0; unsigned short value; +#ifdef CONFIG_DM_I2C + struct udevice *udev; +#endif /* Set I2c to Slot 1 */ - i2c_write(0x77, 0, 0, &a, 1); +#ifndef CONFIG_DM_I2C + ret = i2c_write(0x77, 0, 0, &a, 1); +#else + ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, 0, &a, 1); +#endif + if (ret) + goto error; switch (dpmac) { case 7: @@ -252,28 +300,35 @@ static void qsgmii_configure_repeater(int dpmac) return; } +#ifdef CONFIG_DM_I2C + i2c_get_chip_for_busnum(0, i2c_phy_addr, 1, &udev); +#endif + for (i = 0; i < 4; i++) { for (j = 0; j < 4; j++) { - a = 0x18; - i2c_write(i2c_phy_addr, 6, 1, &a, 1); - a = 0x38; - i2c_write(i2c_phy_addr, 4, 1, &a, 1); - a = 0x4; - i2c_write(i2c_phy_addr, 8, 1, &a, 1); - - i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1); - i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1); - - i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1); - i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1); - - a = 0x14; - i2c_write(i2c_phy_addr, 0x23, 1, &a, 1); - a = 0xb5; - i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1); - a = 0x20; - i2c_write(i2c_phy_addr, 4, 1, &a, 1); - mdelay(100); + reg_pair[3].val = &ch_a_eq[i]; + reg_pair[4].val = &ch_a_ctl2[j]; + reg_pair[5].val = &ch_b_eq[i]; + reg_pair[6].val = &ch_b_ctl2[j]; + + for (k = 0; k < 10; k++) { +#ifndef CONFIG_DM_I2C + ret = i2c_write(i2c_phy_addr, + reg_pair[k].addr, + 1, reg_pair[k].val, 1); +#else + ret = i2c_get_chip_for_busnum(0, + i2c_addr[dpmac], + 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, + reg_pair[k].addr, + reg_pair[k].val, 1); +#endif + if (ret) + goto error; + } + ret = miiphy_read(dev, phy_addr, 0x11, &value); if (ret > 0) goto error; diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index f0bea7327d..f1592982a3 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -21,6 +21,7 @@ #include <hwconfig.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/soc.h> +#include <asm/arch-fsl-layerscape/fsl_icid.h> #include "../common/qixis.h" #include "ls1088a_qixis.h" @@ -374,7 +375,15 @@ int select_i2c_ch_pca9547(u8 ch) { int ret; +#ifndef CONFIG_DM_I2C ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev); + if (!ret) + ret = dm_i2c_write(dev, 0, &ch, 1); +#endif if (ret) { puts("PCA: failed to select proper channel\n"); return ret; @@ -393,38 +402,89 @@ void board_retimer_init(void) /* Access to Control/Shared register */ reg = 0x0; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); +#else + struct udevice *dev; + + i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR, 1, &dev); + dm_i2c_write(dev, 0xff, ®, 1); +#endif /* Read device revision and ID */ +#ifndef CONFIG_DM_I2C i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1); +#else + dm_i2c_read(dev, 1, ®, 1); +#endif debug("Retimer version id = 0x%x\n", reg); /* Enable Broadcast. All writes target all channel register sets */ reg = 0x0c; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); +#else + dm_i2c_write(dev, 0xff, ®, 1); +#endif /* Reset Channel Registers */ +#ifndef CONFIG_DM_I2C i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1); +#else + dm_i2c_read(dev, 0, ®, 1); +#endif reg |= 0x4; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1); +#else + dm_i2c_write(dev, 0, ®, 1); +#endif /* Set data rate as 10.3125 Gbps */ reg = 0x90; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1); +#else + dm_i2c_write(dev, 0x60, ®, 1); +#endif reg = 0xb3; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1); +#else + dm_i2c_write(dev, 0x61, ®, 1); +#endif reg = 0x90; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1); +#else + dm_i2c_write(dev, 0x62, ®, 1); +#endif reg = 0xb3; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1); +#else + dm_i2c_write(dev, 0x63, ®, 1); +#endif reg = 0xcd; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); +#else + dm_i2c_write(dev, 0x64, ®, 1); +#endif /* Select VCO Divider to full rate (000) */ +#ifndef CONFIG_DM_I2C i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1); +#else + dm_i2c_read(dev, 0x2F, ®, 1); +#endif reg &= 0x0f; reg |= 0x70; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1); +#else + dm_i2c_write(dev, 0x2F, ®, 1); +#endif #ifdef CONFIG_TARGET_LS1088AQDS /* Retimer is connected to I2C1_CH5 */ @@ -432,38 +492,88 @@ void board_retimer_init(void) /* Access to Control/Shared register */ reg = 0x0; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1); +#else + i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2, 1, &dev); + dm_i2c_write(dev, 0xff, ®, 1); +#endif /* Read device revision and ID */ +#ifndef CONFIG_DM_I2C i2c_read(I2C_RETIMER_ADDR2, 1, 1, ®, 1); +#else + dm_i2c_read(dev, 1, ®, 1); +#endif debug("Retimer version id = 0x%x\n", reg); /* Enable Broadcast. All writes target all channel register sets */ reg = 0x0c; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1); +#else + dm_i2c_write(dev, 0xff, ®, 1); +#endif /* Reset Channel Registers */ +#ifndef CONFIG_DM_I2C i2c_read(I2C_RETIMER_ADDR2, 0, 1, ®, 1); +#else + dm_i2c_read(dev, 0, ®, 1); +#endif reg |= 0x4; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR2, 0, 1, ®, 1); +#else + dm_i2c_write(dev, 0, ®, 1); +#endif /* Set data rate as 10.3125 Gbps */ reg = 0x90; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, ®, 1); +#else + dm_i2c_write(dev, 0x60, ®, 1); +#endif reg = 0xb3; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, ®, 1); +#else + dm_i2c_write(dev, 0x61, ®, 1); +#endif reg = 0x90; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, ®, 1); +#else + dm_i2c_write(dev, 0x62, ®, 1); +#endif reg = 0xb3; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, ®, 1); +#else + dm_i2c_write(dev, 0x63, ®, 1); +#endif reg = 0xcd; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, ®, 1); +#else + dm_i2c_write(dev, 0x64, ®, 1); +#endif /* Select VCO Divider to full rate (000) */ +#ifndef CONFIG_DM_I2C i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1); +#else + dm_i2c_read(dev, 0x2F, ®, 1); +#endif reg &= 0x0f; reg |= 0x70; +#ifndef CONFIG_DM_I2C i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1); +#else + dm_i2c_write(dev, 0x2F, ®, 1); +#endif + #endif /*return the default channel*/ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); @@ -482,6 +592,32 @@ int misc_init_r(void) QIXIS_WRITE(brdcfg[5], brdcfg5); } #endif + +#ifdef CONFIG_TARGET_LS1088AQDS + u8 brdcfg4, brdcfg5; + + if (hwconfig("dspi-on-board")) { + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= ~BRDCFG4_USBOSC_MASK; + brdcfg4 |= BRDCFG4_SPI; + QIXIS_WRITE(brdcfg[4], brdcfg4); + + brdcfg5 = QIXIS_READ(brdcfg[5]); + brdcfg5 &= ~BRDCFG5_SPR_MASK; + brdcfg5 |= BRDCFG5_SPI_ON_BOARD; + QIXIS_WRITE(brdcfg[5], brdcfg5); + } else if (hwconfig("dspi-off-board")) { + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= ~BRDCFG4_USBOSC_MASK; + brdcfg4 |= BRDCFG4_SPI; + QIXIS_WRITE(brdcfg[4], brdcfg4); + + brdcfg5 = QIXIS_READ(brdcfg[5]); + brdcfg5 &= ~BRDCFG5_SPR_MASK; + brdcfg5 |= BRDCFG5_SPI_OFF_BOARD; + QIXIS_WRITE(brdcfg[5], brdcfg5); + } +#endif return 0; } #endif @@ -500,16 +636,30 @@ int get_serdes_volt(void) u8 chan = PWM_CHANNEL0; /* Select the PAGE 0 using PMBus commands PAGE for VDD */ +#ifndef CONFIG_DM_I2C ret = i2c_write(I2C_SVDD_MONITOR_ADDR, PMBUS_CMD_PAGE, 1, &chan, 1); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev); + if (!ret) + ret = dm_i2c_write(dev, PMBUS_CMD_PAGE, + &chan, 1); +#endif + if (ret) { printf("VID: failed to select VDD Page 0\n"); return ret; } /* Read the output voltage using PMBus command READ_VOUT */ +#ifndef CONFIG_DM_I2C ret = i2c_read(I2C_SVDD_MONITOR_ADDR, PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2); +#else + dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2); +#endif if (ret) { printf("VID: failed to read the volatge\n"); return ret; @@ -525,8 +675,17 @@ int set_serdes_volt(int svdd) svdd & 0xFF, (svdd & 0xFF00) >> 8}; /* Write the desired voltage code to the SVDD regulator */ +#ifndef CONFIG_DM_I2C ret = i2c_write(I2C_SVDD_MONITOR_ADDR, PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev); + if (!ret) + ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE, + (void *)&buff, 5); +#endif if (ret) { printf("VID: I2C failed to write to the volatge regulator\n"); return -1; @@ -557,8 +716,18 @@ int set_serdes_volt(int svdd) printf("SVDD changing of RDB\n"); /* Read the BRDCFG54 via CLPD */ +#ifndef CONFIG_DM_I2C ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR, QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev); + if (!ret) + ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET, + (void *)&brdcfg4, 1); +#endif + if (ret) { printf("VID: I2C failed to read the CPLD BRDCFG4\n"); return -1; @@ -567,8 +736,14 @@ int set_serdes_volt(int svdd) brdcfg4 = brdcfg4 | 0x08; /* Write to the BRDCFG4 */ +#ifndef CONFIG_DM_I2C ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1); +#else + ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET, + (void *)&brdcfg4, 1); +#endif + if (ret) { debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n"); return -1; @@ -739,11 +914,26 @@ void fsl_fdt_fixup_flash(void *fdt) int ft_board_setup(void *blob, bd_t *bd) { int i; - u64 base[CONFIG_NR_DRAM_BANKS]; - u64 size[CONFIG_NR_DRAM_BANKS]; + u16 mc_memory_bank = 0; + + u64 *base; + u64 *size; + u64 mc_memory_base = 0; + u64 mc_memory_size = 0; + u16 total_memory_banks; ft_cpu_setup(blob, bd); + fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size); + + if (mc_memory_base != 0) + mc_memory_bank++; + + total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank; + + base = calloc(total_memory_banks, sizeof(u64)); + size = calloc(total_memory_banks, sizeof(u64)); + /* fixup DT for the two GPP DDR banks */ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { base[i] = gd->bd->bi_dram[i].start; @@ -760,7 +950,17 @@ int ft_board_setup(void *blob, bd_t *bd) size[1] = gd->arch.resv_ram - base[1]; #endif - fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS); + if (mc_memory_base != 0) { + for (i = 0; i <= total_memory_banks; i++) { + if (base[i] == 0 && size[i] == 0) { + base[i] = mc_memory_base; + size[i] = mc_memory_size; + break; + } + } + } + + fdt_fixup_memory_banks(blob, base, size, total_memory_banks); fdt_fsl_mc_fixup_iommu_map_entry(blob); @@ -769,6 +969,9 @@ int ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_FSL_MC_ENET fdt_fixup_board_enet(blob); #endif + + fdt_fixup_icid(blob); + if (is_pb_board()) fixup_ls1088ardb_pb_banner(blob); diff --git a/board/freescale/ls1088a/ls1088a_qixis.h b/board/freescale/ls1088a/ls1088a_qixis.h index c58852617f..e3502eb1d1 100644 --- a/board/freescale/ls1088a/ls1088a_qixis.h +++ b/board/freescale/ls1088a/ls1088a_qixis.h @@ -41,4 +41,15 @@ #define BRDCFG5_SPISDHC_MASK 0x0C #define BRDCFG5_FORCE_SD 0x08 +/* Definitions of QIXIS Registers for LS1088AQDS */ + +/* BRDCFG4 */ +#define BRDCFG4_USBOSC_MASK 0x01 +#define BRDCFG4_SPI 0x01 + +/* BRDCFG5 */ +#define BRDCFG5_SPR_MASK 0x0f +#define BRDCFG5_SPI_ON_BOARD 0x0a +#define BRDCFG5_SPI_OFF_BOARD 0x0f + #endif diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c index 1b4e6c65fb..6a8788c312 100644 --- a/board/freescale/ls2080aqds/eth.c +++ b/board/freescale/ls2080aqds/eth.c @@ -90,11 +90,16 @@ struct ls2080a_qds_mdio { struct mii_dev *realbus; }; +struct reg_pair { + uint addr; + u8 *val; +}; + static void sgmii_configure_repeater(int serdes_port) { struct mii_dev *bus; uint8_t a = 0xf; - int i, j, ret; + int i, j, k, ret; int dpmac_id = 0, dpmac, mii_bus = 0; unsigned short value; char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"}; @@ -105,10 +110,30 @@ static void sgmii_configure_repeater(int serdes_port) uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7}; uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84}; + u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20}; + struct reg_pair reg_pair[10] = { + {6, ®_val[0]}, {4, ®_val[1]}, + {8, ®_val[2]}, {0xf, NULL}, + {0x11, NULL}, {0x16, NULL}, + {0x18, NULL}, {0x23, ®_val[3]}, + {0x2d, ®_val[4]}, {4, ®_val[5]}, + }; + int *riser_phy_addr = &xqsgii_riser_phy_addr[0]; +#ifdef CONFIG_DM_I2C + struct udevice *udev; +#endif /* Set I2c to Slot 1 */ - i2c_write(0x77, 0, 0, &a, 1); +#ifndef CONFIG_DM_I2C + ret = i2c_write(0x77, 0, 0, &a, 1); +#else + ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, 0, &a, 1); +#endif + if (ret) + goto error; for (dpmac = 0; dpmac < 8; dpmac++) { /* Check the PHY status */ @@ -121,7 +146,15 @@ static void sgmii_configure_repeater(int serdes_port) mii_bus = 1; dpmac_id = dpmac + 9; a = 0xb; - i2c_write(0x76, 0, 0, &a, 1); +#ifndef CONFIG_DM_I2C + ret = i2c_write(0x76, 0, 0, &a, 1); +#else + ret = i2c_get_chip_for_busnum(0, 0x76, 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, 0, &a, 1); +#endif + if (ret) + goto error; break; } @@ -154,29 +187,29 @@ static void sgmii_configure_repeater(int serdes_port) for (i = 0; i < 4; i++) { for (j = 0; j < 4; j++) { - a = 0x18; - i2c_write(i2c_addr[dpmac], 6, 1, &a, 1); - a = 0x38; - i2c_write(i2c_addr[dpmac], 4, 1, &a, 1); - a = 0x4; - i2c_write(i2c_addr[dpmac], 8, 1, &a, 1); - - i2c_write(i2c_addr[dpmac], 0xf, 1, - &ch_a_eq[i], 1); - i2c_write(i2c_addr[dpmac], 0x11, 1, - &ch_a_ctl2[j], 1); - - i2c_write(i2c_addr[dpmac], 0x16, 1, - &ch_b_eq[i], 1); - i2c_write(i2c_addr[dpmac], 0x18, 1, - &ch_b_ctl2[j], 1); - - a = 0x14; - i2c_write(i2c_addr[dpmac], 0x23, 1, &a, 1); - a = 0xb5; - i2c_write(i2c_addr[dpmac], 0x2d, 1, &a, 1); - a = 0x20; - i2c_write(i2c_addr[dpmac], 4, 1, &a, 1); + reg_pair[3].val = &ch_a_eq[i]; + reg_pair[4].val = &ch_a_ctl2[j]; + reg_pair[5].val = &ch_b_eq[i]; + reg_pair[6].val = &ch_b_ctl2[j]; + + for (k = 0; k < 10; k++) { +#ifndef CONFIG_DM_I2C + ret = i2c_write(i2c_addr[dpmac], + reg_pair[k].addr, + 1, reg_pair[k].val, 1); +#else + ret = i2c_get_chip_for_busnum(0, + i2c_addr[dpmac], + 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, + reg_pair[k].addr, + reg_pair[k].val, 1); +#endif + if (ret) + goto error; + } + mdelay(100); ret = miiphy_read(dev[mii_bus], riser_phy_addr[dpmac], @@ -217,7 +250,7 @@ error: static void qsgmii_configure_repeater(int dpmac) { uint8_t a = 0xf; - int i, j; + int i, j, k; int i2c_phy_addr = 0; int phy_addr = 0; int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b}; @@ -227,12 +260,32 @@ static void qsgmii_configure_repeater(int dpmac) uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7}; uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84}; + u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20}; + struct reg_pair reg_pair[10] = { + {6, ®_val[0]}, {4, ®_val[1]}, + {8, ®_val[2]}, {0xf, NULL}, + {0x11, NULL}, {0x16, NULL}, + {0x18, NULL}, {0x23, ®_val[3]}, + {0x2d, ®_val[4]}, {4, ®_val[5]}, + }; + const char *dev = "LS2080A_QDS_MDIO0"; int ret = 0; unsigned short value; +#ifdef CONFIG_DM_I2C + struct udevice *udev; +#endif /* Set I2c to Slot 1 */ - i2c_write(0x77, 0, 0, &a, 1); +#ifndef CONFIG_DM_I2C + ret = i2c_write(0x77, 0, 0, &a, 1); +#else + ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, 0, &a, 1); +#endif + if (ret) + goto error; switch (dpmac) { case 1: @@ -283,25 +336,29 @@ static void qsgmii_configure_repeater(int dpmac) for (i = 0; i < 4; i++) { for (j = 0; j < 4; j++) { - a = 0x18; - i2c_write(i2c_phy_addr, 6, 1, &a, 1); - a = 0x38; - i2c_write(i2c_phy_addr, 4, 1, &a, 1); - a = 0x4; - i2c_write(i2c_phy_addr, 8, 1, &a, 1); - - i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1); - i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1); - - i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1); - i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1); - - a = 0x14; - i2c_write(i2c_phy_addr, 0x23, 1, &a, 1); - a = 0xb5; - i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1); - a = 0x20; - i2c_write(i2c_phy_addr, 4, 1, &a, 1); + reg_pair[3].val = &ch_a_eq[i]; + reg_pair[4].val = &ch_a_ctl2[j]; + reg_pair[5].val = &ch_b_eq[i]; + reg_pair[6].val = &ch_b_ctl2[j]; + + for (k = 0; k < 10; k++) { +#ifndef CONFIG_DM_I2C + ret = i2c_write(i2c_phy_addr, + reg_pair[k].addr, + 1, reg_pair[k].val, 1); +#else + ret = i2c_get_chip_for_busnum(0, + i2c_phy_addr, + 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, + reg_pair[k].addr, + reg_pair[k].val, 1); +#endif + if (ret) + goto error; + } + mdelay(100); ret = miiphy_read(dev, phy_addr, 0x11, &value); if (ret > 0) diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index e9c055745f..91c80353ed 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -161,8 +161,16 @@ unsigned long get_board_ddr_clk(void) int select_i2c_ch_pca9547(u8 ch) { int ret; +#ifdef CONFIG_DM_I2C + struct udevice *dev; + ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev); + if (!ret) + ret = dm_i2c_write(dev, 0, &ch, 1); + +#else ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); +#endif if (ret) { puts("PCA: failed to select proper channel\n"); return ret; @@ -225,7 +233,15 @@ int board_init(void) gd->env_addr = (ulong)&default_environment[0]; #endif select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + +#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT +#ifdef CONFIG_DM_I2C + rtc_enable_32khz_output(0, CONFIG_SYS_I2C_RTC_ADDR); +#else rtc_enable_32khz_output(); +#endif +#endif + #ifdef CONFIG_FSL_CAAM sec_init(); #endif diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 2b2dbbb0ce..e20267f27c 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -164,7 +164,16 @@ int select_i2c_ch_pca9547(u8 ch) { int ret; +#ifndef CONFIG_DM_I2C ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev); + if (!ret) + ret = dm_i2c_write(dev, 0, &ch, 1); +#endif + if (ret) { puts("PCA: failed to select proper channel\n"); return ret; @@ -410,11 +419,27 @@ void fsl_fdt_fixup_flash(void *fdt) int ft_board_setup(void *blob, bd_t *bd) { - u64 base[CONFIG_NR_DRAM_BANKS]; - u64 size[CONFIG_NR_DRAM_BANKS]; + int i; + u16 mc_memory_bank = 0; + + u64 *base; + u64 *size; + u64 mc_memory_base = 0; + u64 mc_memory_size = 0; + u16 total_memory_banks; ft_cpu_setup(blob, bd); + fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size); + + if (mc_memory_base != 0) + mc_memory_bank++; + + total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank; + + base = calloc(total_memory_banks, sizeof(u64)); + size = calloc(total_memory_banks, sizeof(u64)); + /* fixup DT for the two GPP DDR banks */ base[0] = gd->bd->bi_dram[0].start; size[0] = gd->bd->bi_dram[0].size; @@ -431,7 +456,17 @@ int ft_board_setup(void *blob, bd_t *bd) size[1] = gd->arch.resv_ram - base[1]; #endif - fdt_fixup_memory_banks(blob, base, size, 2); + if (mc_memory_base != 0) { + for (i = 0; i <= total_memory_banks; i++) { + if (base[i] == 0 && size[i] == 0) { + base[i] = mc_memory_base; + size[i] = mc_memory_size; + break; + } + } + } + + fdt_fixup_memory_banks(blob, base, size, total_memory_banks); fdt_fsl_mc_fixup_iommu_map_entry(blob); diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index f3885fa8b7..7f19a1a145 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -74,7 +74,15 @@ int select_i2c_ch_pca9547(u8 ch) { int ret; +#ifndef CONFIG_DM_I2C ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev); + if (!ret) + ret = dm_i2c_write(dev, 0, &ch, 1); +#endif if (ret) { puts("PCA: failed to select proper channel\n"); return ret; @@ -402,6 +410,26 @@ int config_board_mux(void) return 0; } +#elif defined(CONFIG_TARGET_LX2160ARDB) +int config_board_mux(void) +{ + u8 brdcfg; + + brdcfg = QIXIS_READ(brdcfg[4]); + /* The BRDCFG4 register controls general board configuration. + *|-------------------------------------------| + *|Field | Function | + *|-------------------------------------------| + *|5 | CAN I/O Enable (net CFG_CAN_EN_B):| + *|CAN_EN | 0= CAN transceivers are disabled. | + *| | 1= CAN transceivers are enabled. | + *|-------------------------------------------| + */ + brdcfg |= BIT_MASK(5); + QIXIS_WRITE(brdcfg[4], brdcfg); + + return 0; +} #else int config_board_mux(void) { @@ -529,11 +557,26 @@ void board_quiesce_devices(void) int ft_board_setup(void *blob, bd_t *bd) { int i; - u64 base[CONFIG_NR_DRAM_BANKS]; - u64 size[CONFIG_NR_DRAM_BANKS]; + u16 mc_memory_bank = 0; + + u64 *base; + u64 *size; + u64 mc_memory_base = 0; + u64 mc_memory_size = 0; + u16 total_memory_banks; ft_cpu_setup(blob, bd); + fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size); + + if (mc_memory_base != 0) + mc_memory_bank++; + + total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank; + + base = calloc(total_memory_banks, sizeof(u64)); + size = calloc(total_memory_banks, sizeof(u64)); + /* fixup DT for the three GPP DDR banks */ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { base[i] = gd->bd->bi_dram[i].start; @@ -553,7 +596,17 @@ int ft_board_setup(void *blob, bd_t *bd) size[2] = gd->arch.resv_ram - base[2]; #endif - fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS); + if (mc_memory_base != 0) { + for (i = 0; i <= total_memory_banks; i++) { + if (base[i] == 0 && size[i] == 0) { + base[i] = mc_memory_base; + size[i] = mc_memory_size; + break; + } + } + } + + fdt_fixup_memory_banks(blob, base, size, total_memory_banks); #ifdef CONFIG_USB fsl_fdt_fixup_dr_usb(blob, bd); diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 7d819d8df5..2799b5b5a4 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -164,7 +164,7 @@ void lbc_sdram_init(void) #endif /* enable SDRAM init */ } -#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) +#if (defined(CONFIG_PCI) || defined(CONFIG_PCI1)) && !defined(CONFIG_DM_PCI) /* For some reason the Tundra PCI bridge shows up on itself as a * different device. Work around that by refusing to configure it. */ @@ -189,6 +189,7 @@ static struct pci_config_table pci_mpc85xxcds_config_table[] = { static struct pci_controller pci1_hose; #endif /* CONFIG_PCI */ +#if !defined(CONFIG_DM_PCI) void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); @@ -268,6 +269,7 @@ void pci_init_board(void) fsl_pcie_init_board(first_free_busno); } +#endif void configure_rgmii(void) { @@ -349,7 +351,7 @@ int board_eth_init(bd_t *bis) return pci_eth_init(bis); } -#if defined(CONFIG_OF_BOARD_SETUP) +#if defined(CONFIG_OF_BOARD_SETUP) && !defined(CONFIG_DM_PCI) void ft_pci_setup(void *blob, bd_t *bd) { FT_FSL_PCI_SETUP; diff --git a/board/freescale/p1_p2_rdb_pc/README b/board/freescale/p1_p2_rdb_pc/README index f4cc43fbfa..b85cf0209e 100644 --- a/board/freescale/p1_p2_rdb_pc/README +++ b/board/freescale/p1_p2_rdb_pc/README @@ -45,3 +45,22 @@ enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below 'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD. 'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD. + +Device tree support and how to enable it for different configs +-------------------------------------------------------------- +Device tree support is available for p1020rdb and p2020rdb for below mentioned boot, +1. NOR Boot +2. NAND Boot +3. SD Boot +4. SPIFLASH Boot + +To enable device tree support for other boot, below configs need to be +enabled in relative defconfig file, +1. CONFIG_DEFAULT_DEVICE_TREE="p1020rdb" (Change default device tree name if required) +2. CONFIG_OF_CONTROL +3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at + CONFIG_RESET_VECTOR_ADDRESS - 0xffc + +If device tree support is enabled in defconfig, +1. use 'u-boot-with-dtb.bin' for NOR boot. +2. use 'u-boot-with-spl.bin' for other boot. diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index a04a73528f..3649f16598 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -278,7 +278,7 @@ int checkboard(void) return 0; } -#ifdef CONFIG_PCI +#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI) void pci_init_board(void) { fsl_pcie_init_board(0); @@ -444,7 +444,9 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#if !defined(CONFIG_DM_PCI) FT_FSL_PCI_SETUP; +#endif #ifdef CONFIG_QE do_fixup_by_compat(blob, "fsl,qe", "status", "okay", diff --git a/board/freescale/p2041rdb/README b/board/freescale/p2041rdb/README index 9b5539fff3..79f77e4961 100644 --- a/board/freescale/p2041rdb/README +++ b/board/freescale/p2041rdb/README @@ -85,6 +85,24 @@ Boot from SPI flash SW1[1-5] = 10100 Note: 1 stands for 'on', 0 stands for 'off' +Device tree support and how to enable it for different configs +-------------------------------------------------------------- +Device tree support is available for p2041rdb for below mentioned boot, +1. NOR Boot +2. NAND Boot +3. SD Boot +4. SPIFLASH Boot + +To enable device tree support for other boot, below configs need to be +enabled in relative defconfig file, +1. CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" (Change default device tree name if required) +2. CONFIG_OF_CONTROL +3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at + CONFIG_RESET_VECTOR_ADDRESS - 0xffc + +If device tree support is enabled in defconfig, use 'u-boot-with-dtb.bin' +instead of u-boot.bin for all boot. + CPLD command ============ The CPLD is used to control the power sequence and some serdes lane diff --git a/board/freescale/t102xrdb/README b/board/freescale/t102xrdb/README index a0af25a432..dde3f8ca37 100644 --- a/board/freescale/t102xrdb/README +++ b/board/freescale/t102xrdb/README @@ -251,6 +251,25 @@ Software configurations and board settings SW3[3] = '0' for eMMC (or 'switch emmc' by software) +device tree support and how to enable it for different configs +-------------------------------------------------------------- +device tree support is available for t1024rdb for below mentioned boot, +1. nor boot +2. nand boot +3. sd boot +4. spiflash boot + +to enable device tree support for other boot, below configs need to be +enabled in relative defconfig file, +1. config_default_device_tree="t1024rdb" (change default device tree name if required) +2. config_of_control +3. config_mpc85xx_have_reset_vector if reset vector is located at + config_reset_vector_address - 0xffc + +if device tree support is enabled in defconfig, +1. use 'u-boot-with-dtb.bin' for nor boot. +2. use 'u-boot-with-spl-pbl.bin' for other boot. + 2-stage NAND/SPI/SD boot loader ------------------------------- PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM. diff --git a/board/freescale/t102xrdb/pci.c b/board/freescale/t102xrdb/pci.c index 161b8cb403..adc128d924 100644 --- a/board/freescale/t102xrdb/pci.c +++ b/board/freescale/t102xrdb/pci.c @@ -11,6 +11,7 @@ #include <fdt_support.h> #include <asm/fsl_serdes.h> +#if !defined(CONFIG_DM_PCI) void pci_init_board(void) { fsl_pcie_init_board(0); @@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd) { FT_FSL_PCI_SETUP; } +#endif diff --git a/board/freescale/t104xrdb/README b/board/freescale/t104xrdb/README index 98b3f63db2..09cb98e33d 100644 --- a/board/freescale/t104xrdb/README +++ b/board/freescale/t104xrdb/README @@ -365,3 +365,22 @@ to 2. SPI does not support flush so remove flush from pbl, make changes in tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000 with 0x091380c0 + +Device tree support and how to enable it for different configs +-------------------------------------------------------------- +Device tree support is available for t1042d4rdb for below mentioned boot, +1. NOR Boot +2. NAND Boot +3. SD Boot +4. SPIFLASH Boot + +To enable device tree support for other boot, below configs need to be +enabled in relative defconfig file, +1. CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb" (Change default device tree name if required) +2. CONFIG_OF_CONTROL +3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at + CONFIG_RESET_VECTOR_ADDRESS - 0xffc + +If device tree support is enabled in defconfig, +1. use 'u-boot-with-dtb.bin' for NOR boot. +2. use 'u-boot-with-spl-pbl.bin' for other boot. diff --git a/board/freescale/t104xrdb/pci.c b/board/freescale/t104xrdb/pci.c index 9fd66594f4..6b666ba2d2 100644 --- a/board/freescale/t104xrdb/pci.c +++ b/board/freescale/t104xrdb/pci.c @@ -11,6 +11,7 @@ #include <fdt_support.h> #include <asm/fsl_serdes.h> +#if !defined(CONFIG_DM_PCI) void pci_init_board(void) { fsl_pcie_init_board(0); @@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd) { FT_FSL_PCI_SETUP; } +#endif diff --git a/board/freescale/t208xrdb/README b/board/freescale/t208xrdb/README index 42b2b92396..9e4b28faf4 100644 --- a/board/freescale/t208xrdb/README +++ b/board/freescale/t208xrdb/README @@ -262,3 +262,22 @@ How to update the ucode of Freescale FMAN For more details, please refer to T2080PCIe-RDB User Guide and access website www.freescale.com and Freescale QorIQ SDK Infocenter document. + +Device tree support and how to enable it for different configs +-------------------------------------------------------------- +Device tree support is available for t2080rdb for below mentioned boot, +1. NOR Boot +2. NAND Boot +3. SD Boot +4. SPIFLASH Boot + +To enable device tree support for other boot, below configs need to be +enabled in relative defconfig file, +1. CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" (Change default device tree name if required) +2. CONFIG_OF_CONTROL +3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at + CONFIG_RESET_VECTOR_ADDRESS - 0xffc + +If device tree support is enabled in defconfig, +1. use 'u-boot-with-dtb.bin' for NOR boot. +2. use 'u-boot-with-spl-pbl.bin' for other boot. diff --git a/board/freescale/t208xrdb/pci.c b/board/freescale/t208xrdb/pci.c index 161b8cb403..adc128d924 100644 --- a/board/freescale/t208xrdb/pci.c +++ b/board/freescale/t208xrdb/pci.c @@ -11,6 +11,7 @@ #include <fdt_support.h> #include <asm/fsl_serdes.h> +#if !defined(CONFIG_DM_PCI) void pci_init_board(void) { fsl_pcie_init_board(0); @@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd) { FT_FSL_PCI_SETUP; } +#endif diff --git a/board/freescale/t4rdb/pci.c b/board/freescale/t4rdb/pci.c index 4100370e20..7d670e1a2f 100644 --- a/board/freescale/t4rdb/pci.c +++ b/board/freescale/t4rdb/pci.c @@ -11,6 +11,7 @@ #include <fdt_support.h> #include <asm/fsl_serdes.h> +#if !defined(CONFIG_DM_PCI) void pci_init_board(void) { fsl_pcie_init_board(0); @@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd) { FT_FSL_PCI_SETUP; } +#endif diff --git a/board/rockchip/fennec_rk3288/Kconfig b/board/rockchip/fennec_rk3288/Kconfig deleted file mode 100644 index 1dcfcf0317..0000000000 --- a/board/rockchip/fennec_rk3288/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_FENNEC_RK3288 - -config SYS_BOARD - default "fennec_rk3288" - -config SYS_VENDOR - default "rockchip" - -config SYS_CONFIG_NAME - default "fennec_rk3288" - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - -endif diff --git a/board/rockchip/fennec_rk3288/MAINTAINERS b/board/rockchip/fennec_rk3288/MAINTAINERS deleted file mode 100644 index 78a389b060..0000000000 --- a/board/rockchip/fennec_rk3288/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -FENNEC-RK3288 -M: Lin Huang <hl@rock-chips.com> -S: Maintained -F: board/rockchip/fennec_rk3288 -F: include/configs/fennec_rk3288.h -F: configs/fennec-rk3288_defconfig diff --git a/board/rockchip/fennec_rk3288/Makefile b/board/rockchip/fennec_rk3288/Makefile deleted file mode 100644 index b287db699e..0000000000 --- a/board/rockchip/fennec_rk3288/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# (C) Copyright 2016 Rockchip Electronics Co., Ltd -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += fennec-rk3288.o diff --git a/board/rockchip/fennec_rk3288/fennec-rk3288.c b/board/rockchip/fennec_rk3288/fennec-rk3288.c deleted file mode 100644 index 779bc646b2..0000000000 --- a/board/rockchip/fennec_rk3288/fennec-rk3288.c +++ /dev/null @@ -1,5 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c index 676935a843..75462d1c34 100644 --- a/board/siemens/common/board.c +++ b/board/siemens/common/board.c @@ -189,14 +189,11 @@ void set_env_gpios(unsigned char state) { char *ptr_env; char str_tmp[5]; /* must contain "ledX"*/ - char num[1]; unsigned char i, idx, pos1, pos2, ccount; unsigned char gpio_n, gpio_s0, gpio_s1; for (i = 0; i < MAX_NR_LEDS; i++) { - strcpy(str_tmp, "led"); - sprintf(num, "%d", i); - strcat(str_tmp, num); + sprintf(str_tmp, "led%d", i); /* If env var is not found we stop */ ptr_env = env_get(str_tmp); diff --git a/board/siemens/draco/MAINTAINERS b/board/siemens/draco/MAINTAINERS index e9107f08bf..c73f18c002 100644 --- a/board/siemens/draco/MAINTAINERS +++ b/board/siemens/draco/MAINTAINERS @@ -1,5 +1,5 @@ DRACO BOARD -M: Roger Meier <r.meier@siemens.com> +M: Samuel Egli <samuel.egli@siemens.com> S: Maintained F: board/siemens/draco/ F: include/configs/draco.h diff --git a/board/siemens/pxm2/MAINTAINERS b/board/siemens/pxm2/MAINTAINERS index fa734c9c11..dc02fe87c9 100644 --- a/board/siemens/pxm2/MAINTAINERS +++ b/board/siemens/pxm2/MAINTAINERS @@ -1,5 +1,5 @@ PXM2 BOARD -M: Roger Meier <r.meier@siemens.com> +M: Samuel Egli <samuel.egli@siemens.com> S: Maintained F: board/siemens/pxm2/ F: include/configs/pxm2.h diff --git a/board/siemens/rut/MAINTAINERS b/board/siemens/rut/MAINTAINERS index 8c1b77059b..1e92710904 100644 --- a/board/siemens/rut/MAINTAINERS +++ b/board/siemens/rut/MAINTAINERS @@ -1,5 +1,5 @@ RUT BOARD -M: Roger Meier <r.meier@siemens.com> +M: Samuel Egli <samuel.egli@siemens.com> S: Maintained F: board/siemens/rut/ F: include/configs/rut.h diff --git a/board/st/stm32mp1/Kconfig b/board/st/stm32mp1/Kconfig index 87216c0963..4fa2360b4f 100644 --- a/board/st/stm32mp1/Kconfig +++ b/board/st/stm32mp1/Kconfig @@ -22,4 +22,8 @@ config CMD_STBOARD This compile the stboard command to read and write the board in the OTP. +config TARGET_STM32MP157C_DK2 + bool "support of STMicroelectronics STM32MP157C-DK2 Discovery Board" + default y + endif diff --git a/board/st/stm32mp1/MAINTAINERS b/board/st/stm32mp1/MAINTAINERS index 3bf4c21b60..2930947716 100644 --- a/board/st/stm32mp1/MAINTAINERS +++ b/board/st/stm32mp1/MAINTAINERS @@ -1,9 +1,10 @@ STM32MP1 BOARD M: Patrick Delaunay <patrick.delaunay@st.com> L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers) +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git S: Maintained -F: arch/arm/dts/stm32mp157* -F: board/st/stm32mp1 +F: arch/arm/dts/stm32mp15* +F: board/st/stm32mp1/ F: configs/stm32mp15_basic_defconfig F: configs/stm32mp15_optee_defconfig F: configs/stm32mp15_trusted_defconfig diff --git a/board/st/stm32mp1/README b/board/st/stm32mp1/README index 428357cfa0..c807e0842e 100644 --- a/board/st/stm32mp1/README +++ b/board/st/stm32mp1/README @@ -139,7 +139,6 @@ the supported device trees for stm32mp157 are: # make DEVICE_TREE=<name> all - example: a) trusted boot on ev1 # export KBUILD_OUTPUT=stm32mp15_trusted @@ -190,7 +189,7 @@ the supported device trees for stm32mp157 are: 6. Switch Setting for Boot Mode =============================== -You can select the boot mode, on the board ed1 with the switch SW1 +You can select the boot mode, on the board with one switch : - on the daugther board ed1 with the switch SW1 : BOOT0, BOOT1, BOOT2 @@ -358,3 +357,36 @@ on bank 0 to access to internal OTP: 4 check env update STM32MP> print ethaddr ethaddr=12:34:56:78:9a:bc + +10. Coprocessor firmware +======================== + +U-Boot can boot the coprocessor before the kernel (coprocessor early boot). + +A/ Manuallly by using rproc commands (update the bootcmd) + Configurations + # env set name_copro "rproc-m4-fw.elf" + # env set dev_copro 0 + # env set loadaddr_copro 0xC1000000 + + Load binary from bootfs partition (number 4) on SDCard (mmc 0) + # ext4load mmc 0:4 ${loadaddr_copro} ${name_copro} + => ${filesize} updated with the size of the loaded file + + Start M4 firmware with remote proc command + # rproc init + # rproc load ${dev_copro} ${loadaddr_copro} ${filesize} + # rproc start ${dev_copro} + +B/ Automatically by using FIT feature and generic DISTRO bootcmd + + see examples in this directory : + + Generate FIT including kernel + device tree + M4 firmware + with cfg with M4 boot + $> mkimage -f fit_copro_kernel_dtb.its fit_copro_kernel_dtb.itb + + Then using DISTRO configuration file: see extlinux.conf to select + the correct configuration + => stm32mp157c-ev1-m4 + => stm32mp157c-dk2-m4 diff --git a/board/st/stm32mp1/cmd_stboard.c b/board/st/stm32mp1/cmd_stboard.c index f781c364cf..04352ae8ed 100644 --- a/board/st/stm32mp1/cmd_stboard.c +++ b/board/st/stm32mp1/cmd_stboard.c @@ -60,7 +60,7 @@ static int do_stboard(cmd_tbl_t *cmdtp, int flag, int argc, ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD), &otp, sizeof(otp)); - if (ret) { + if (ret < 0) { puts("OTP read error"); return CMD_RET_FAILURE; } diff --git a/board/st/stm32mp1/extlinux.conf b/board/st/stm32mp1/extlinux.conf new file mode 100644 index 0000000000..2b4632804d --- /dev/null +++ b/board/st/stm32mp1/extlinux.conf @@ -0,0 +1,20 @@ +# Generic Distro Configuration for STM32MP157 +menu title Select the boot mode +TIMEOUT 20 +DEFAULT stm32mp157c-ev1 + +LABEL stm32mp157c-ev1 + KERNEL /fit_kernel_dtb.itb#ev1 + APPEND root=/dev/mmcblk0p6 rootwait rw earlyprintk console=ttyS3,115200 + +LABEL stm32mp157c-ev1-m4 + KERNEL /fit_copro_kernel_dtb.itb#ev1-m4 + APPEND root=/dev/mmcblk0p6 rootwait rw earlyprintk console=ttyS3,115200 + +LABEL stm32mp157c-dk2 + KERNEL /fit_kernel_dtb.itb#dk2 + APPEND root=/dev/mmcblk0p6 rootwait rw earlyprintk console=ttyS3,115200 + +LABEL stm32mp157c-dk2-m4 + KERNEL /fit_copro_kernel_dtb.itb#dk2-m4 + APPEND root=/dev/mmcblk0p6 rootwait rw earlyprintk console=ttyS3,115200 diff --git a/board/st/stm32mp1/fit_copro_kernel_dtb.its b/board/st/stm32mp1/fit_copro_kernel_dtb.its new file mode 100644 index 0000000000..3e08fd943e --- /dev/null +++ b/board/st/stm32mp1/fit_copro_kernel_dtb.its @@ -0,0 +1,103 @@ +/* + * Compilation: + * mkimage -f fit_copro_kernel_dtb.its fit_copro_kernel_dtb.itb + */ + +/dts-v1/; +/ { + description = "U-Boot fitImage for stm32mp157"; + #address-cells = <1>; + + images { + + copro { + description = "M4 copro"; + data = /incbin/("rproc-m4-fw.elf"); + type = "copro"; + arch = "arm"; + compression = "none"; + load = <0xC0800000>; + hash-1 { + algo = "sha1"; + }; + }; + + kernel { + description = "Linux kernel"; + data = /incbin/("zImage"); + type = "kernel"; + arch = "arm"; + os = "linux"; + compression = "none"; + load = <0xC0008000>; + entry = <0xC0008000>; + hash-1 { + algo = "sha1"; + }; + }; + + fdt-dk2 { + description = "FDT dk2"; + data = /incbin/("stm32mp157c-dk2.dtb"); + type = "flat_dt"; + arch = "arm"; + compression = "none"; + hash-1 { + algo = "sha1"; + }; + }; + + fdt-ev1 { + description = "FDT ev1"; + data = /incbin/("stm32mp157c-ev1.dtb"); + type = "flat_dt"; + arch = "arm"; + compression = "none"; + hash-1 { + algo = "sha1"; + }; + }; + }; + + configurations { + default = "dk2-m4"; + + dk2-m4 { + description = "dk2-m4"; + loadables = "copro"; + kernel = "kernel"; + fdt = "fdt-dk2"; + hash-1 { + algo = "sha1"; + }; + }; + + dk2 { + description = "dk2"; + kernel = "kernel"; + fdt = "fdt-dk2"; + hash-1 { + algo = "sha1"; + }; + }; + + ev1-m4 { + description = "ev1-m4"; + loadables = "copro"; + kernel = "kernel"; + fdt = "fdt-ev1"; + hash-1 { + algo = "sha1"; + }; + }; + + ev1 { + description = "ev1"; + kernel = "kernel"; + fdt = "fdt-ev1"; + hash-1 { + algo = "sha1"; + }; + }; + }; +}; diff --git a/board/st/stm32mp1/fit_kernel_dtb.its b/board/st/stm32mp1/fit_kernel_dtb.its new file mode 100644 index 0000000000..18d03ebf3c --- /dev/null +++ b/board/st/stm32mp1/fit_kernel_dtb.its @@ -0,0 +1,82 @@ +/* + * Compilation: + * mkimage -f fit_kernel_dtb.its fit_kernel_dtb.itb + * + * Files in linux build dir: + * - arch/arm/boot/zImage + * - arch/arm/boot/dts/stm32mp157c-dk2.dtb + * - arch/arm/boot/dts/stm32mp157c-ev1.dtb + * + * load mmc 0:4 $kernel_addr_r fit_kernel_dtb.itb + * bootm $kernel_addr_r + * bootm $kernel_addr_r#dk2 + * bootm $kernel_addr_r#ev1 + * + * or use extlinux.conf in this directory + */ + +/dts-v1/; +/ { + description = "U-Boot fitImage for stm32mp157"; + #address-cells = <1>; + + images { + kernel { + description = "Linux kernel"; + data = /incbin/("zImage"); + type = "kernel"; + arch = "arm"; + os = "linux"; + compression = "none"; + load = <0xC0008000>; + entry = <0xC0008000>; + hash-1 { + algo = "sha1"; + }; + }; + + fdt-dk2 { + description = "FDT dk2"; + data = /incbin/("stm32mp157c-dk2.dtb"); + type = "flat_dt"; + arch = "arm"; + compression = "none"; + hash-1 { + algo = "sha1"; + }; + }; + + fdt-ev1 { + description = "FDT ev1"; + data = /incbin/("stm32mp157c-ev1.dtb"); + type = "flat_dt"; + arch = "arm"; + compression = "none"; + hash-1 { + algo = "sha1"; + }; + }; + }; + + configurations { + default = "dk2"; + + dk2 { + description = "dk2"; + kernel = "kernel"; + fdt = "fdt-dk2"; + hash-1 { + algo = "sha1"; + }; + }; + + ev1 { + description = "ev1"; + kernel = "kernel"; + fdt = "fdt-ev1"; + hash-1 { + algo = "sha1"; + }; + }; + }; +}; diff --git a/board/st/stm32mp1/spl.c b/board/st/stm32mp1/spl.c index e19be0f770..e65ff288ea 100644 --- a/board/st/stm32mp1/spl.c +++ b/board/st/stm32mp1/spl.c @@ -27,5 +27,19 @@ void spl_board_init(void) STPMIC1_BUCKS_MRST_CR, STPMIC1_MRST_BUCK(STPMIC1_BUCK3), STPMIC1_MRST_BUCK(STPMIC1_BUCK3)); + + /* Check if debug is enabled to program PMIC according to the bit */ + if ((readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_DEBUG_ON) && !ret) { + printf("Keep debug unit ON\n"); + + pmic_clrsetbits(dev, STPMIC1_BUCKS_MRST_CR, + STPMIC1_MRST_BUCK_DEBUG, + STPMIC1_MRST_BUCK_DEBUG); + + if (STPMIC1_MRST_LDO_DEBUG) + pmic_clrsetbits(dev, STPMIC1_LDOS_MRST_CR, + STPMIC1_MRST_LDO_DEBUG, + STPMIC1_MRST_LDO_DEBUG); + } #endif } diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 279c7b7797..fc14ad375c 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -5,8 +5,8 @@ #include <common.h> #include <adc.h> #include <bootm.h> -#include <config.h> #include <clk.h> +#include <config.h> #include <dm.h> #include <env.h> #include <env_internal.h> @@ -18,9 +18,11 @@ #include <mtd.h> #include <mtd_node.h> #include <phy.h> +#include <remoteproc.h> #include <reset.h> #include <syscon.h> #include <usb.h> +#include <watchdog.h> #include <asm/io.h> #include <asm/gpio.h> #include <asm/arch/stm32.h> @@ -102,7 +104,7 @@ int checkboard(void) if (!ret) ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD), &otp, sizeof(otp)); - if (!ret && otp) { + if (ret > 0 && otp) { printf("Board: MB%04x Var%d Rev.%c-%02d\n", otp >> 16, (otp >> 12) & 0xF, @@ -232,6 +234,7 @@ int g_dnl_board_usb_cable_connected(void) } #endif /* CONFIG_USB_GADGET */ +#ifdef CONFIG_LED static int get_led(struct udevice **dev, char *led_string) { char *led_name; @@ -264,12 +267,42 @@ static int setup_led(enum led_state_t cmd) ret = led_set_state(dev, cmd); return ret; } +#endif + +static void __maybe_unused led_error_blink(u32 nb_blink) +{ +#ifdef CONFIG_LED + int ret; + struct udevice *led; + u32 i; +#endif + + if (!nb_blink) + return; + +#ifdef CONFIG_LED + ret = get_led(&led, "u-boot,error-led"); + if (!ret) { + /* make u-boot,error-led blinking */ + /* if U32_MAX and 125ms interval, for 17.02 years */ + for (i = 0; i < 2 * nb_blink; i++) { + led_set_state(led, LEDST_TOGGLE); + mdelay(125); + WATCHDOG_RESET(); + } + } +#endif + + /* infinite: the boot process must be stopped */ + if (nb_blink == U32_MAX) + hang(); +} +#ifdef CONFIG_ADC static int board_check_usb_power(void) { struct ofnode_phandle_args adc_args; struct udevice *adc; - struct udevice *led; ofnode node; unsigned int raw; int max_uV = 0; @@ -395,23 +428,11 @@ static int board_check_usb_power(void) pr_err("****************************************************\n\n"); } - ret = get_led(&led, "u-boot,error-led"); - if (ret) { - /* in unattached case, the boot process must be stopped */ - if (nb_blink == U32_MAX) - hang(); - return ret; - } - - /* make u-boot,error-led blinking */ - for (i = 0; i < nb_blink * 2; i++) { - led_set_state(led, LEDST_TOGGLE); - mdelay(125); - } - led_set_state(led, LEDST_ON); + led_error_blink(nb_blink); return 0; } +#endif /* CONFIG_ADC */ static void sysconf_init(void) { @@ -454,7 +475,9 @@ static void sysconf_init(void) * => U-Boot set the register only if VDD < 2.7V (in DT) * but this value need to be consistent with board design */ - ret = syscon_get_by_driver_data(STM32MP_SYSCON_PWR, &pwr_dev); + ret = uclass_get_device_by_driver(UCLASS_PMIC, + DM_GET_DRIVER(stm32mp_pwr_pmic), + &pwr_dev); if (!ret) { ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(stm32mp_bsec), @@ -465,11 +488,11 @@ static void sysconf_init(void) } ret = misc_read(dev, STM32_BSEC_SHADOW(18), &otp, 4); - if (!ret) + if (ret > 0) otp = otp & BIT(13); - /* get VDD = pwr-supply */ - ret = device_get_supply_regulator(pwr_dev, "pwr-supply", + /* get VDD = vdd-supply */ + ret = device_get_supply_regulator(pwr_dev, "vdd-supply", &pwr_reg); /* check if VDD is Low Voltage */ @@ -505,6 +528,73 @@ static void sysconf_init(void) #endif } +#ifdef CONFIG_DM_REGULATOR +/* Fix to make I2C1 usable on DK2 for touchscreen usage in kernel */ +static int dk2_i2c1_fix(void) +{ + ofnode node; + struct gpio_desc hdmi, audio; + int ret = 0; + + node = ofnode_path("/soc/i2c@40012000/hdmi-transmitter@39"); + if (!ofnode_valid(node)) { + pr_debug("%s: no hdmi-transmitter@39 ?\n", __func__); + return -ENOENT; + } + + if (gpio_request_by_name_nodev(node, "reset-gpios", 0, + &hdmi, GPIOD_IS_OUT)) { + pr_debug("%s: could not find reset-gpios\n", + __func__); + return -ENOENT; + } + + node = ofnode_path("/soc/i2c@40012000/cs42l51@4a"); + if (!ofnode_valid(node)) { + pr_debug("%s: no cs42l51@4a ?\n", __func__); + return -ENOENT; + } + + if (gpio_request_by_name_nodev(node, "reset-gpios", 0, + &audio, GPIOD_IS_OUT)) { + pr_debug("%s: could not find reset-gpios\n", + __func__); + return -ENOENT; + } + + /* before power up, insure that HDMI and AUDIO IC is under reset */ + ret = dm_gpio_set_value(&hdmi, 1); + if (ret) { + pr_err("%s: can't set_value for hdmi_nrst gpio", __func__); + goto error; + } + ret = dm_gpio_set_value(&audio, 1); + if (ret) { + pr_err("%s: can't set_value for audio_nrst gpio", __func__); + goto error; + } + + /* power-up audio IC */ + regulator_autoset_by_name("v1v8_audio", NULL); + + /* power-up HDMI IC */ + regulator_autoset_by_name("v1v2_hdmi", NULL); + regulator_autoset_by_name("v3v3_hdmi", NULL); + +error: + return ret; +} + +static bool board_is_dk2(void) +{ + if (CONFIG_IS_ENABLED(TARGET_STM32MP157C_DK2) && + of_machine_is_compatible("st,stm32mp157c-dk2")) + return true; + + return false; +} +#endif + /* board dependent setup after realloc */ int board_init(void) { @@ -523,12 +613,15 @@ int board_init(void) board_key_check(); #ifdef CONFIG_DM_REGULATOR + if (board_is_dk2()) + dk2_i2c1_fix(); + regulators_enable_boot_on(_DEBUG); #endif sysconf_init(); - if (IS_ENABLED(CONFIG_LED)) + if (CONFIG_IS_ENABLED(CONFIG_LED)) led_default_state(); return 0; @@ -536,9 +629,14 @@ int board_init(void) int board_late_init(void) { + char *boot_device; #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG const void *fdt_compat; int fdt_compat_len; + int ret; + u32 otp; + struct udevice *dev; + char buf[10]; fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible", &fdt_compat_len); @@ -548,21 +646,44 @@ int board_late_init(void) else env_set("board_name", fdt_compat + 3); } + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(stm32mp_bsec), + &dev); + + if (!ret) + ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD), + &otp, sizeof(otp)); + if (!ret && otp) { + snprintf(buf, sizeof(buf), "0x%04x", otp >> 16); + env_set("board_id", buf); + + snprintf(buf, sizeof(buf), "0x%04x", + ((otp >> 8) & 0xF) - 1 + 0xA); + env_set("board_rev", buf); + } #endif +#ifdef CONFIG_ADC /* for DK1/DK2 boards */ board_check_usb_power(); +#endif /* CONFIG_ADC */ + + /* Check the boot-source to disable bootdelay */ + boot_device = env_get("boot_device"); + if (!strcmp(boot_device, "serial") || !strcmp(boot_device, "usb")) + env_set("bootdelay", "0"); return 0; } void board_quiesce_devices(void) { +#ifdef CONFIG_LED setup_led(LEDST_OFF); +#endif } /* board interface eth init */ -/* this is a weak define that we are overriding */ int board_interface_eth_init(phy_interface_t interface_type, bool eth_clk_sel_reg, bool eth_ref_clk_sel_reg) { @@ -771,3 +892,26 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } #endif + +static void board_copro_image_process(ulong fw_image, size_t fw_size) +{ + int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */ + + if (!rproc_is_initialized()) + if (rproc_init()) { + printf("Remote Processor %d initialization failed\n", + id); + return; + } + + ret = rproc_load(id, fw_image, fw_size); + printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n", + id, fw_image, fw_size, ret ? " Failed!" : " Success!"); + + if (!ret) { + rproc_start(id); + env_set("copro_state", "booted"); + } +} + +U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_COPRO, board_copro_image_process); diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c index 4113a1c6ee..47259b7149 100644 --- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c +++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c @@ -18,97 +18,10 @@ #include <asm/arch-rockchip/hardware.h> #include <asm/arch-rockchip/grf_rk3399.h> #include <asm/arch-rockchip/periph.h> +#include <asm/arch-rockchip/misc.h> #include <power/regulator.h> #include <u-boot/sha256.h> -static void setup_macaddr(void) -{ -#if CONFIG_IS_ENABLED(CMD_NET) - int ret; - const char *cpuid = env_get("cpuid#"); - u8 hash[SHA256_SUM_LEN]; - int size = sizeof(hash); - u8 mac_addr[6]; - - /* Only generate a MAC address, if none is set in the environment */ - if (env_get("ethaddr")) - return; - - if (!cpuid) { - debug("%s: could not retrieve 'cpuid#'\n", __func__); - return; - } - - ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, &size); - if (ret) { - debug("%s: failed to calculate SHA256\n", __func__); - return; - } - - /* Copy 6 bytes of the hash to base the MAC address on */ - memcpy(mac_addr, hash, 6); - - /* Make this a valid MAC address and set it */ - mac_addr[0] &= 0xfe; /* clear multicast bit */ - mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */ - eth_env_set_enetaddr("ethaddr", mac_addr); -#endif -} - -static void setup_serial(void) -{ -#if CONFIG_IS_ENABLED(ROCKCHIP_EFUSE) - const u32 cpuid_offset = 0x7; - const u32 cpuid_length = 0x10; - - struct udevice *dev; - int ret, i; - u8 cpuid[cpuid_length]; - u8 low[cpuid_length/2], high[cpuid_length/2]; - char cpuid_str[cpuid_length * 2 + 1]; - u64 serialno; - char serialno_str[17]; - - /* retrieve the device */ - ret = uclass_get_device_by_driver(UCLASS_MISC, - DM_GET_DRIVER(rockchip_efuse), &dev); - if (ret) { - debug("%s: could not find efuse device\n", __func__); - return; - } - - /* read the cpu_id range from the efuses */ - ret = misc_read(dev, cpuid_offset, &cpuid, sizeof(cpuid)); - if (ret) { - debug("%s: reading cpuid from the efuses failed\n", - __func__); - return; - } - - memset(cpuid_str, 0, sizeof(cpuid_str)); - for (i = 0; i < 16; i++) - sprintf(&cpuid_str[i * 2], "%02x", cpuid[i]); - - debug("cpuid: %s\n", cpuid_str); - - /* - * Mix the cpuid bytes using the same rules as in - * ${linux}/drivers/soc/rockchip/rockchip-cpuinfo.c - */ - for (i = 0; i < 8; i++) { - low[i] = cpuid[1 + (i << 1)]; - high[i] = cpuid[i << 1]; - } - - serialno = crc32_no_comp(0, low, 8); - serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32; - snprintf(serialno_str, sizeof(serialno_str), "%016llx", serialno); - - env_set("cpuid#", cpuid_str); - env_set("serial#", serialno_str); -#endif -} - static void setup_iodomain(void) { const u32 GRF_IO_VSEL_GPIO4CD_SHIFT = 3; @@ -198,8 +111,23 @@ static int setup_boottargets(void) int misc_init_r(void) { - setup_serial(); - setup_macaddr(); + const u32 cpuid_offset = 0x7; + const u32 cpuid_length = 0x10; + u8 cpuid[cpuid_length]; + int ret; + + ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); + if (ret) + return ret; + + ret = rockchip_cpuid_set(cpuid, cpuid_length); + if (ret) + return ret; + + ret = rockchip_setup_macaddr(); + if (ret) + return ret; + setup_iodomain(); setup_boottargets(); diff --git a/cmd/Kconfig b/cmd/Kconfig index 041de1d831..05872fa0d7 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -611,6 +611,20 @@ config CMD_MEMORY base - print or set address offset loop - initialize loop on address range +config MX_CYCLIC + bool "Enable cyclic md/mw commands" + depends on CMD_MEMORY + help + Add the "mdc" and "mwc" memory commands. These are cyclic + "md/mw" commands. + Examples: + + => mdc.b 10 4 500 + This command will print 4 bytes (10,11,12,13) each 500 ms. + + => mwc.l 100 12345678 10 + This command will write 12345678 to address 100 all 10 ms. + config CMD_RANDOM bool "random" default y @@ -7,51 +7,70 @@ #include <clk.h> #if defined(CONFIG_DM) && defined(CONFIG_CLK) #include <dm.h> +#include <dm/device.h> +#include <dm/root.h> #include <dm/device-internal.h> +#include <linux/clk-provider.h> #endif -int __weak soc_clk_dump(void) -{ #if defined(CONFIG_DM) && defined(CONFIG_CLK) - struct udevice *dev; - struct uclass *uc; - struct clk clk; - int ret; - ulong rate; - - /* Device addresses start at 1 */ - ret = uclass_get(UCLASS_CLK, &uc); - if (ret) - return ret; - - uclass_foreach_dev(dev, uc) { - memset(&clk, 0, sizeof(clk)); - ret = device_probe(dev); - if (ret) - goto noclk; +static void show_clks(struct udevice *dev, int depth, int last_flag) +{ + int i, is_last; + struct udevice *child; + struct clk *clkp; + u32 rate; + + clkp = dev_get_clk_ptr(dev); + if (device_get_uclass_id(dev) == UCLASS_CLK && clkp) { + rate = clk_get_rate(clkp); + + printf(" %-12u %8d ", rate, clkp->enable_count); + + for (i = depth; i >= 0; i--) { + is_last = (last_flag >> i) & 1; + if (i) { + if (is_last) + printf(" "); + else + printf("| "); + } else { + if (is_last) + printf("`-- "); + else + printf("|-- "); + } + } - ret = clk_request(dev, &clk); - if (ret) - goto noclk; + printf("%s\n", dev->name); + } - rate = clk_get_rate(&clk); - clk_free(&clk); + list_for_each_entry(child, &dev->child_head, sibling_node) { + is_last = list_is_last(&child->sibling_node, &dev->child_head); + show_clks(child, depth + 1, (last_flag << 1) | is_last); + } +} - if (rate == -ENODEV) - goto noclk; +int __weak soc_clk_dump(void) +{ + struct udevice *root; - printf("%-30.30s : %lu Hz\n", dev->name, rate); - continue; - noclk: - printf("%-30.30s : ? Hz\n", dev->name); + root = dm_root(); + if (root) { + printf(" Rate Usecnt Name\n"); + printf("------------------------------------------\n"); + show_clks(root, -1, 0); } return 0; +} #else +int __weak soc_clk_dump(void) +{ puts("Not implemented\n"); return 1; -#endif } +#endif static int do_clk_dump(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) diff --git a/cmd/gpio.c b/cmd/gpio.c index 53366f36e7..eff36ab2af 100644 --- a/cmd/gpio.c +++ b/cmd/gpio.c @@ -91,7 +91,7 @@ static int do_gpio_status(bool all, const char *gpio_name) if (!gpio_name || !bank_name || !strncasecmp(gpio_name, bank_name, banklen)) { - const char *p = NULL; + const char *p; int offset; p = gpio_name + banklen; @@ -148,7 +148,7 @@ int pci_bar_show(struct udevice *dev) if ((!is_64 && size_low) || (is_64 && size)) { size = ~size + 1; - printf(" %d %#016llx %#016llx %d %s %s\n", + printf(" %d %#018llx %#018llx %d %s %s\n", bar_id, (unsigned long long)base, (unsigned long long)size, is_64 ? 64 : 32, is_io ? "I/O" : "MEM", @@ -629,10 +629,10 @@ static void pci_show_regions(struct udevice *bus) return; } - printf("# %-16s %-16s %-16s %s\n", "Bus start", "Phys start", "Size", + printf("# %-18s %-18s %-18s %s\n", "Bus start", "Phys start", "Size", "Flags"); for (i = 0, reg = hose->regions; i < hose->region_count; i++, reg++) { - printf("%d %#016llx %#016llx %#016llx ", i, + printf("%d %#018llx %#018llx %#018llx ", i, (unsigned long long)reg->bus_start, (unsigned long long)reg->phys_start, (unsigned long long)reg->size); diff --git a/common/board_f.c b/common/board_f.c index 31181a9dc4..591f18f391 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -467,12 +467,38 @@ static int reserve_uboot(void) return 0; } +#ifdef CONFIG_SYS_NONCACHED_MEMORY +static int reserve_noncached(void) +{ + /* + * The value of gd->start_addr_sp must match the value of malloc_start + * calculated in boatrd_f.c:initr_malloc(), which is passed to + * board_r.c:mem_malloc_init() and then used by + * cache.c:noncached_init() + * + * These calculations must match the code in cache.c:noncached_init() + */ + gd->start_addr_sp = ALIGN(gd->start_addr_sp, MMU_SECTION_SIZE) - + MMU_SECTION_SIZE; + gd->start_addr_sp -= ALIGN(CONFIG_SYS_NONCACHED_MEMORY, + MMU_SECTION_SIZE); + debug("Reserving %dM for noncached_alloc() at: %08lx\n", + CONFIG_SYS_NONCACHED_MEMORY >> 20, gd->start_addr_sp); + + return 0; +} +#endif + /* reserve memory for malloc() area */ static int reserve_malloc(void) { gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN; debug("Reserving %dk for malloc() at: %08lx\n", TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp); +#ifdef CONFIG_SYS_NONCACHED_MEMORY + reserve_noncached(); +#endif + return 0; } diff --git a/common/board_r.c b/common/board_r.c index b7f68bba4a..d6fb5047a2 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -247,6 +247,10 @@ static int initr_malloc(void) gd->malloc_ptr / 1024); #endif /* The malloc area is immediately below the monitor copy in DRAM */ + /* + * This value MUST match the value of gd->start_addr_sp in board_f.c: + * reserve_noncached(). + */ malloc_start = gd->relocaddr - TOTAL_MALLOC_LEN; mem_malloc_init((ulong)map_sysmem(malloc_start, TOTAL_MALLOC_LEN), TOTAL_MALLOC_LEN); diff --git a/common/image.c b/common/image.c index 84e859a30f..179eef0bd2 100644 --- a/common/image.c +++ b/common/image.c @@ -132,6 +132,7 @@ static const table_entry_t uimage_os[] = { #if defined(CONFIG_BOOTM_OPENRTOS) || defined(USE_HOSTCC) { IH_OS_OPENRTOS, "openrtos", "OpenRTOS", }, #endif + { IH_OS_OPENSBI, "opensbi", "RISC-V OpenSBI", }, { -1, "", "", }, }; @@ -175,6 +176,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_PMMC, "pmmc", "TI Power Management Micro-Controller Firmware",}, { IH_TYPE_STM32IMAGE, "stm32image", "STMicroelectronics STM32 Image" }, { IH_TYPE_MTKIMAGE, "mtk_image", "MediaTek BootROM loadable Image" }, + { IH_TYPE_COPRO, "copro", "Coprocessor Image"}, { -1, "", "", }, }; diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 630491699c..f467eca2be 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -208,6 +208,7 @@ config SPL_SYS_MALLOC_SIMPLE config TPL_SYS_MALLOC_SIMPLE bool prompt "Only use malloc_simple functions in the TPL" + depends on TPL help Say Y here to only use the *_simple malloc functions from malloc_simple.c, rather then using the versions from dlmalloc.c; @@ -261,6 +262,7 @@ config SPL_BANNER_PRINT config TPL_BANNER_PRINT bool "Enable output of the TPL banner 'U-Boot TPL ...'" + depends on TPL default y help If this option is enabled, SPL will not print the banner with version @@ -433,6 +435,7 @@ config SPL_HASH_SUPPORT config TPL_HASH_SUPPORT bool "Support hashing drivers in TPL" + depends on TPL select SHA1 select SHA256 help @@ -1000,6 +1003,14 @@ config SPL_SPI_LOAD endif # SPL_SPI_FLASH_SUPPORT +config SYS_SPI_U_BOOT_OFFS + hex "address of u-boot payload in SPI flash" + default 0x0 + depends on SPL_SPI_LOAD || SPL_SPI_SUNXI + help + Address within SPI-Flash from where the u-boot payload is fetched + from. + config SPL_SPI_SUPPORT bool "Support SPI drivers" help @@ -1146,6 +1157,23 @@ config SPL_OPTEE OP-TEE is an open source Trusted OS which is loaded by SPL. More detail at: https://github.com/OP-TEE/optee_os +config SPL_OPENSBI + bool "Support RISC-V OpenSBI" + depends on RISCV && SPL_RISCV_MMODE && RISCV_SMODE + help + OpenSBI is an open-source implementation of the RISC-V Supervisor Binary + Interface (SBI) specification. U-Boot supports the OpenSBI FW_DYNAMIC + firmware. It is loaded and started by U-Boot SPL. + + More details are available at https://github.com/riscv/opensbi and + https://github.com/riscv/riscv-sbi-doc + +config SPL_OPENSBI_LOAD_ADDR + hex "OpenSBI load address" + depends on SPL_OPENSBI + help + Load address of the OpenSBI binary. + config TPL bool depends on SUPPORT_TPL diff --git a/common/spl/Makefile b/common/spl/Makefile index d28de692dd..5ce6f4ae48 100644 --- a/common/spl/Makefile +++ b/common/spl/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_$(SPL_TPL_)NET_SUPPORT) += spl_net.o obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += spl_mmc.o obj-$(CONFIG_$(SPL_TPL_)ATF) += spl_atf.o obj-$(CONFIG_$(SPL_TPL_)OPTEE) += spl_optee.o +obj-$(CONFIG_$(SPL_TPL_)OPENSBI) += spl_opensbi.o obj-$(CONFIG_$(SPL_TPL_)USB_STORAGE) += spl_usb.o obj-$(CONFIG_$(SPL_TPL_)FS_FAT) += spl_fat.o obj-$(CONFIG_$(SPL_TPL_)FS_EXT4) += spl_ext.o diff --git a/common/spl/spl.c b/common/spl/spl.c index 2c696f2a79..082fa2bd94 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -659,6 +659,12 @@ void board_init_r(gd_t *dummy1, ulong dummy2) (void *)spl_image.entry_point); break; #endif +#if CONFIG_IS_ENABLED(OPENSBI) + case IH_OS_OPENSBI: + debug("Jumping to U-Boot via RISC-V OpenSBI\n"); + spl_invoke_opensbi(&spl_image); + break; +#endif #ifdef CONFIG_SPL_OS_BOOT case IH_OS_LINUX: debug("Jumping to Linux\n"); @@ -775,7 +781,7 @@ ulong spl_relocate_stack_gd(void) #if CONFIG_IS_ENABLED(DM) dm_fixup_for_gd_move(new_gd); #endif -#if !defined(CONFIG_ARM) +#if !defined(CONFIG_ARM) && !defined(CONFIG_RISCV) gd = new_gd; #endif return ptr; diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index 2e2e09eafb..b3e3ccd5a2 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -12,6 +12,8 @@ #include <linux/libfdt.h> #include <spl.h> +DECLARE_GLOBAL_DATA_PTR; + #ifndef CONFIG_SYS_BOOTM_LEN #define CONFIG_SYS_BOOTM_LEN (64 << 20) #endif @@ -279,25 +281,34 @@ static int spl_fit_append_fdt(struct spl_image_info *spl_image, void *fit, int images, ulong base_offset) { struct spl_image_info image_info; - int node, ret; + int node, ret = 0; + + /* + * Use the address following the image as target address for the + * device tree. + */ + image_info.load_addr = spl_image->load_addr + spl_image->size; /* Figure out which device tree the board wants to use */ node = spl_fit_get_image_node(fit, images, FIT_FDT_PROP, 0); if (node < 0) { debug("%s: cannot find FDT node\n", __func__); - return node; - } - - /* - * Read the device tree and place it after the image. - * Align the destination address to ARCH_DMA_MINALIGN. - */ - image_info.load_addr = spl_image->load_addr + spl_image->size; - ret = spl_load_fit_image(info, sector, fit, base_offset, node, - &image_info); - if (ret < 0) - return ret; + /* + * U-Boot did not find a device tree inside the FIT image. Use + * the U-Boot device tree instead. + */ + if (gd->fdt_blob) + memcpy((void *)image_info.load_addr, gd->fdt_blob, + fdt_totalsize(gd->fdt_blob)); + else + return node; + } else { + ret = spl_load_fit_image(info, sector, fit, base_offset, node, + &image_info); + if (ret < 0) + return ret; + } /* Make the load-address of the FDT available for the SPL framework */ spl_image->fdt_addr = (void *)image_info.load_addr; diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c new file mode 100644 index 0000000000..a6b4480ed2 --- /dev/null +++ b/common/spl/spl_opensbi.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Fraunhofer AISEC, + * Lukas Auer <lukas.auer@aisec.fraunhofer.de> + * + * Based on common/spl/spl_atf.c + */ +#include <common.h> +#include <errno.h> +#include <spl.h> +#include <asm/smp.h> +#include <opensbi.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct fw_dynamic_info opensbi_info; + +static int spl_opensbi_find_uboot_node(void *blob, int *uboot_node) +{ + int fit_images_node, node; + const char *fit_os; + + fit_images_node = fdt_path_offset(blob, "/fit-images"); + if (fit_images_node < 0) + return -ENODEV; + + fdt_for_each_subnode(node, blob, fit_images_node) { + fit_os = fdt_getprop(blob, node, FIT_OS_PROP, NULL); + if (!fit_os) + continue; + + if (genimg_get_os_id(fit_os) == IH_OS_U_BOOT) { + *uboot_node = node; + return 0; + } + } + + return -ENODEV; +} + +void spl_invoke_opensbi(struct spl_image_info *spl_image) +{ + int ret, uboot_node; + ulong uboot_entry; + void (*opensbi_entry)(ulong hartid, ulong dtb, ulong info); + + if (!spl_image->fdt_addr) { + pr_err("No device tree specified in SPL image\n"); + hang(); + } + + /* Find U-Boot image in /fit-images */ + ret = spl_opensbi_find_uboot_node(spl_image->fdt_addr, &uboot_node); + if (ret) { + pr_err("Can't find U-Boot node, %d", ret); + hang(); + } + + /* Get U-Boot entry point */ + uboot_entry = fdt_getprop_u32(spl_image->fdt_addr, uboot_node, + "entry-point"); + if (uboot_entry == FDT_ERROR) + uboot_entry = fdt_getprop_u32(spl_image->fdt_addr, uboot_node, + "load-addr"); + + /* Prepare obensbi_info object */ + opensbi_info.magic = FW_DYNAMIC_INFO_MAGIC_VALUE; + opensbi_info.version = FW_DYNAMIC_INFO_VERSION; + opensbi_info.next_addr = uboot_entry; + opensbi_info.next_mode = FW_DYNAMIC_INFO_NEXT_MODE_S; + opensbi_info.options = SBI_SCRATCH_NO_BOOT_PRINTS; + + opensbi_entry = (void (*)(ulong, ulong, ulong))spl_image->entry_point; + invalidate_icache_all(); + +#ifdef CONFIG_SMP + ret = smp_call_function((ulong)spl_image->entry_point, + (ulong)spl_image->fdt_addr, + (ulong)&opensbi_info); + if (ret) + hang(); +#endif + opensbi_entry(gd->arch.boot_hart, (ulong)spl_image->fdt_addr, + (ulong)&opensbi_info); +} diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig index 298c9f2072..7e48328290 100644 --- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig +++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig @@ -15,6 +15,7 @@ CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000 CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_USB_MASS_STORAGE=y diff --git a/configs/M5249EVB_defconfig b/configs/M5249EVB_defconfig index c39818b4a6..b93f1271d4 100644 --- a/configs/M5249EVB_defconfig +++ b/configs/M5249EVB_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_AUTOBOOT is not set CONFIG_CMD_IMLS=y CONFIG_LOOPW=y +CONFIG_MX_CYCLIC=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y CONFIG_DEFAULT_DEVICE_TREE="M5249EVB" diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index 672dc78211..102716bc07 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -1,8 +1,11 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF80000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8548CDS=y +CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds_36b" +CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -23,6 +26,10 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2 diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index 09726d2830..9cccb609e5 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -1,8 +1,11 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF80000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8548CDS=y +CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds" +CONFIG_OF_CONTROL=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=10 @@ -22,6 +25,10 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2 diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index 4a2d11f1b6..782f8270c8 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -1,8 +1,11 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF80000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8548CDS=y +CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds" +CONFIG_OF_CONTROL=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="LEGACY" @@ -22,6 +25,10 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2 diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index e4c565e244..c4e41f2010 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -42,6 +42,8 @@ CONFIG_MP=y # CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b" CONFIG_ENV_IS_IN_NAND=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y @@ -56,6 +58,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y @@ -63,4 +69,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index 0d92bb2af2..b21fc2159b 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -38,6 +38,8 @@ CONFIG_MP=y # CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b" CONFIG_ENV_IS_IN_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y @@ -51,6 +53,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y @@ -58,4 +64,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index 95000db775..2f69683379 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -39,6 +39,8 @@ CONFIG_MP=y # CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y @@ -52,6 +54,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y @@ -59,4 +65,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index 8ada9bbf38..6145bf2cc6 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -26,6 +27,8 @@ CONFIG_MP=y # CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b" CONFIG_ENV_IS_IN_FLASH=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y @@ -39,6 +42,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y @@ -46,4 +53,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index 2ea2f00e93..832c96967e 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -41,6 +41,8 @@ CONFIG_MP=y # CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc" CONFIG_ENV_IS_IN_NAND=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y @@ -55,6 +57,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y @@ -62,4 +68,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index a139fe8769..2b5537bc32 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -37,6 +37,8 @@ CONFIG_MP=y # CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc" CONFIG_ENV_IS_IN_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y @@ -50,6 +52,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y @@ -57,4 +63,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index 8b46b088d6..dc4f7d6a70 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -38,6 +38,8 @@ CONFIG_MP=y # CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y @@ -51,6 +53,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y @@ -58,4 +64,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index dec97c4d81..bd0bb1796c 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -25,6 +26,8 @@ CONFIG_MP=y # CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc" CONFIG_ENV_IS_IN_FLASH=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y @@ -38,6 +41,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y @@ -45,4 +52,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index 0327e5adc8..acbb9e0159 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -44,6 +44,8 @@ CONFIG_CMD_FAT=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=ec000000.nor" CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:128k(dtb),6016k(kernel),57088k(fs),1m(vsc7385-firmware),1280k(u-boot)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd" CONFIG_ENV_IS_IN_NAND=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y @@ -59,6 +61,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y @@ -66,4 +72,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index 49d8fc70e1..208138f594 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -40,6 +40,8 @@ CONFIG_CMD_FAT=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=ec000000.nor" CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:128k(dtb),6016k(kernel),57088k(fs),1m(vsc7385-firmware),1280k(u-boot)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd" CONFIG_ENV_IS_IN_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y @@ -54,6 +56,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y @@ -61,4 +67,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index 28a2c40444..960f2718a9 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -41,6 +41,8 @@ CONFIG_CMD_FAT=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=ec000000.nor" CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:128k(dtb),6016k(kernel),57088k(fs),1m(vsc7385-firmware),1280k(u-boot)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y @@ -55,6 +57,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y @@ -62,4 +68,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index 0f25faf207..217ae7b1e6 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -28,6 +29,8 @@ CONFIG_CMD_FAT=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=ec000000.nor" CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:128k(dtb),6016k(kernel),57088k(fs),1m(vsc7385-firmware),1280k(u-boot)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd" CONFIG_ENV_IS_IN_FLASH=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y @@ -42,6 +45,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y @@ -49,4 +56,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 10c27e95ea..5e279814a1 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -46,6 +46,8 @@ CONFIG_CMD_FAT=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor" CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b" CONFIG_ENV_IS_IN_NAND=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y @@ -61,6 +63,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y @@ -68,4 +74,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index c0f37740c9..49a7c8052d 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -42,6 +42,8 @@ CONFIG_CMD_FAT=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor" CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b" CONFIG_ENV_IS_IN_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y @@ -56,6 +58,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y @@ -63,4 +69,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index 160878f143..59fce53690 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -43,6 +43,8 @@ CONFIG_CMD_FAT=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor" CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y @@ -57,6 +59,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y @@ -64,4 +70,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index a9c21fbadb..401742463d 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -30,6 +31,8 @@ CONFIG_CMD_FAT=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor" CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b" CONFIG_ENV_IS_IN_FLASH=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y @@ -44,6 +47,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y @@ -51,4 +58,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index 8938503646..3c65108d7d 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -45,6 +45,8 @@ CONFIG_CMD_FAT=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor" CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc" CONFIG_ENV_IS_IN_NAND=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y @@ -60,6 +62,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y @@ -67,4 +73,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index b2b78412fd..05f42aef8a 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -41,6 +41,8 @@ CONFIG_CMD_FAT=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor" CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc" CONFIG_ENV_IS_IN_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y @@ -55,6 +57,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y @@ -62,4 +68,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index aeff863393..bfb7026f2d 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -42,6 +42,8 @@ CONFIG_CMD_FAT=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor" CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y @@ -56,6 +58,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y @@ -63,4 +69,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index 706a27dd1b..6c7ac9d759 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -29,6 +30,8 @@ CONFIG_CMD_FAT=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor" CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc" CONFIG_ENV_IS_IN_FLASH=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y @@ -43,6 +46,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y @@ -50,4 +57,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index e42fac34d4..70b9190b53 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF40000 CONFIG_MPC85xx=y CONFIG_TARGET_P2041RDB=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -23,6 +24,8 @@ CONFIG_CMD_PING=y CONFIG_MP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" CONFIG_ENV_IS_IN_NAND=y CONFIG_FSL_CAAM=y CONFIG_FSL_ESDHC=y @@ -38,6 +41,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y @@ -46,4 +53,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index c339f1bba3..2542526aee 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF40000 CONFIG_MPC85xx=y CONFIG_TARGET_P2041RDB=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -23,6 +24,8 @@ CONFIG_CMD_PING=y CONFIG_MP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" CONFIG_ENV_IS_IN_MMC=y CONFIG_FSL_CAAM=y CONFIG_FSL_ESDHC=y @@ -37,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y @@ -45,4 +52,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index f164b1f34d..4edb581f7c 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF40000 CONFIG_MPC85xx=y CONFIG_TARGET_P2041RDB=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -23,6 +24,8 @@ CONFIG_CMD_PING=y CONFIG_MP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_FSL_CAAM=y CONFIG_FSL_ESDHC=y @@ -37,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y @@ -45,4 +52,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index f322c93763..8a158f52b7 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_MPC85xx=y CONFIG_TARGET_P2041RDB=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -22,6 +23,8 @@ CONFIG_CMD_PING=y CONFIG_MP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" CONFIG_ENV_IS_IN_FLASH=y CONFIG_FSL_CAAM=y CONFIG_FSL_ESDHC=y @@ -36,6 +39,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y @@ -44,4 +51,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig index 6a31ce956e..7f8145fe4c 100644 --- a/configs/P3041DS_NAND_defconfig +++ b/configs/P3041DS_NAND_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF40000 CONFIG_MPC85xx=y CONFIG_TARGET_P3041DS=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -23,6 +24,8 @@ CONFIG_CMD_PING=y CONFIG_MP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p3041ds" CONFIG_ENV_IS_IN_NAND=y CONFIG_FSL_CAAM=y CONFIG_FSL_ESDHC=y @@ -38,6 +41,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y @@ -46,4 +53,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig index c6b22919bb..c6b2750cc2 100644 --- a/configs/P3041DS_SDCARD_defconfig +++ b/configs/P3041DS_SDCARD_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF40000 CONFIG_MPC85xx=y CONFIG_TARGET_P3041DS=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -23,6 +24,8 @@ CONFIG_CMD_PING=y CONFIG_MP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p3041ds" CONFIG_ENV_IS_IN_MMC=y CONFIG_FSL_CAAM=y CONFIG_FSL_ESDHC=y @@ -37,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y @@ -45,4 +52,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig index 0aebf869e9..1b247cc931 100644 --- a/configs/P3041DS_SPIFLASH_defconfig +++ b/configs/P3041DS_SPIFLASH_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF40000 CONFIG_MPC85xx=y CONFIG_TARGET_P3041DS=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -23,6 +24,8 @@ CONFIG_CMD_PING=y CONFIG_MP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p3041ds" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_FSL_CAAM=y CONFIG_FSL_ESDHC=y @@ -37,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y @@ -45,4 +52,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig index a44c1b4446..f8e30efbd4 100644 --- a/configs/P3041DS_defconfig +++ b/configs/P3041DS_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_MPC85xx=y CONFIG_TARGET_P3041DS=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -22,6 +23,8 @@ CONFIG_CMD_PING=y CONFIG_MP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p3041ds" CONFIG_ENV_IS_IN_FLASH=y CONFIG_FSL_CAAM=y CONFIG_FSL_ESDHC=y @@ -36,6 +39,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y @@ -44,4 +51,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig index 36884a88f6..0c309f92ca 100644 --- a/configs/P4080DS_SDCARD_defconfig +++ b/configs/P4080DS_SDCARD_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF40000 CONFIG_MPC85xx=y CONFIG_TARGET_P4080DS=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -23,6 +24,8 @@ CONFIG_CMD_PING=y CONFIG_MP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p4080ds" CONFIG_ENV_IS_IN_MMC=y CONFIG_FSL_CAAM=y CONFIG_FSL_ESDHC=y @@ -37,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y @@ -45,4 +52,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig index 5155657b9e..070ade5cfa 100644 --- a/configs/P4080DS_SPIFLASH_defconfig +++ b/configs/P4080DS_SPIFLASH_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF40000 CONFIG_MPC85xx=y CONFIG_TARGET_P4080DS=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -23,6 +24,8 @@ CONFIG_CMD_PING=y CONFIG_MP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p4080ds" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_FSL_CAAM=y CONFIG_FSL_ESDHC=y @@ -37,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y @@ -45,4 +52,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig index 995248d095..0a35266cd5 100644 --- a/configs/P4080DS_defconfig +++ b/configs/P4080DS_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_MPC85xx=y CONFIG_TARGET_P4080DS=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -22,6 +23,8 @@ CONFIG_CMD_PING=y CONFIG_MP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p4080ds" CONFIG_ENV_IS_IN_FLASH=y CONFIG_FSL_CAAM=y CONFIG_FSL_ESDHC=y @@ -36,6 +39,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y @@ -44,4 +51,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig index 5368f40ad2..847250e0d9 100644 --- a/configs/P5040DS_NAND_defconfig +++ b/configs/P5040DS_NAND_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF40000 CONFIG_MPC85xx=y CONFIG_TARGET_P5040DS=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -24,6 +25,8 @@ CONFIG_CMD_PING=y CONFIG_MP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p5040ds" CONFIG_ENV_IS_IN_NAND=y CONFIG_FSL_CAAM=y CONFIG_FSL_ESDHC=y @@ -39,6 +42,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y @@ -47,4 +54,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig index f1aa187332..a61d36d1ff 100644 --- a/configs/P5040DS_SDCARD_defconfig +++ b/configs/P5040DS_SDCARD_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF40000 CONFIG_MPC85xx=y CONFIG_TARGET_P5040DS=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -24,6 +25,8 @@ CONFIG_CMD_PING=y CONFIG_MP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p5040ds" CONFIG_ENV_IS_IN_MMC=y CONFIG_FSL_CAAM=y CONFIG_FSL_ESDHC=y @@ -38,6 +41,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y @@ -46,4 +53,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig index 7f3181368a..4eaa35448b 100644 --- a/configs/P5040DS_SPIFLASH_defconfig +++ b/configs/P5040DS_SPIFLASH_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF40000 CONFIG_MPC85xx=y CONFIG_TARGET_P5040DS=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -24,6 +25,8 @@ CONFIG_CMD_PING=y CONFIG_MP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p5040ds" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_FSL_CAAM=y CONFIG_FSL_ESDHC=y @@ -38,6 +41,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y @@ -46,4 +53,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig index 40d04e9694..2e67dce267 100644 --- a/configs/P5040DS_defconfig +++ b/configs/P5040DS_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_MPC85xx=y CONFIG_TARGET_P5040DS=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -23,6 +24,8 @@ CONFIG_CMD_PING=y CONFIG_MP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="p5040ds" CONFIG_ENV_IS_IN_FLASH=y CONFIG_FSL_CAAM=y CONFIG_FSL_ESDHC=y @@ -37,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y @@ -45,4 +52,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/SBx81LIFKW_defconfig b/configs/SBx81LIFKW_defconfig index f9ca3428a2..db843db9c2 100644 --- a/configs/SBx81LIFKW_defconfig +++ b/configs/SBx81LIFKW_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x00600000 CONFIG_TARGET_SBx81LIFKW=y diff --git a/configs/SBx81LIFXCAT_defconfig b/configs/SBx81LIFXCAT_defconfig index a8dc9f1749..c06ad6e32f 100644 --- a/configs/SBx81LIFXCAT_defconfig +++ b/configs/SBx81LIFXCAT_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x00600000 CONFIG_TARGET_SBx81LIFXCAT=y diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index dec004462b..c38912dc38 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -45,6 +45,8 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1" CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="t1024rdb" CONFIG_ENV_IS_IN_NAND=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y @@ -62,6 +64,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y @@ -70,4 +76,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index 5143046862..5215953caf 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -43,6 +43,8 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1" CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="t1024rdb" CONFIG_ENV_IS_IN_MMC=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y @@ -59,6 +61,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y @@ -67,4 +73,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index ff45291668..2e6b81b0c2 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -44,6 +44,8 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1" CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="t1024rdb" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y @@ -60,6 +62,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y @@ -68,4 +74,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index 9059329450..ccd9112832 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_MPC85xx=y CONFIG_TARGET_T1024RDB=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -29,6 +30,8 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1" CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="t1024rdb" CONFIG_ENV_IS_IN_FLASH=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y @@ -45,6 +48,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y @@ -53,4 +60,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index fefa5ca1d0..920af5b4c4 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -44,6 +44,8 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb" CONFIG_ENV_IS_IN_NAND=y CONFIG_FSL_CAAM=y CONFIG_FSL_ESDHC=y @@ -60,6 +62,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y @@ -70,4 +76,3 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index 9fdfb4e043..e532366218 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -42,6 +42,8 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb" CONFIG_ENV_IS_IN_MMC=y CONFIG_FSL_CAAM=y CONFIG_FSL_ESDHC=y @@ -57,6 +59,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y @@ -67,4 +73,3 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index 84e0b50f5b..78e4582113 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -43,6 +43,8 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_FSL_CAAM=y CONFIG_FSL_ESDHC=y @@ -58,6 +60,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y @@ -68,4 +74,3 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index 749baf622e..3a4699b3ef 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_MPC85xx=y CONFIG_TARGET_T1042D4RDB=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -28,6 +29,8 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb" CONFIG_ENV_IS_IN_FLASH=y CONFIG_FSL_CAAM=y CONFIG_FSL_ESDHC=y @@ -43,6 +46,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y @@ -53,4 +60,3 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index 3a34df3588..dcd57f7b3a 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -42,6 +42,8 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1" CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:1m(uboot),5m(kernel),128k(dtb),-(user)" # CONFIG_CMD_IRQ is not set +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" CONFIG_ENV_IS_IN_NAND=y CONFIG_FSL_CAAM=y CONFIG_FSL_ESDHC=y @@ -58,6 +60,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y @@ -66,4 +72,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index d40ae389ba..235e8ee514 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -40,6 +40,8 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1" CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:1m(uboot),5m(kernel),128k(dtb),-(user)" # CONFIG_CMD_IRQ is not set +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" CONFIG_ENV_IS_IN_MMC=y CONFIG_FSL_CAAM=y CONFIG_FSL_ESDHC=y @@ -55,6 +57,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y @@ -63,4 +69,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index 3cbf4a03c8..7b64b7d490 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -41,6 +41,8 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1" CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:1m(uboot),5m(kernel),128k(dtb),-(user)" # CONFIG_CMD_IRQ is not set +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_FSL_CAAM=y CONFIG_FSL_ESDHC=y @@ -56,6 +58,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y @@ -64,4 +70,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig index f1f0f139f4..69ee626ee0 100644 --- a/configs/T2080RDB_defconfig +++ b/configs/T2080RDB_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_MPC85xx=y CONFIG_TARGET_T2080RDB=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -26,6 +27,8 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1" CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:1m(uboot),5m(kernel),128k(dtb),-(user)" # CONFIG_CMD_IRQ is not set +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" CONFIG_ENV_IS_IN_FLASH=y CONFIG_FSL_CAAM=y CONFIG_FSL_ESDHC=y @@ -41,6 +44,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y @@ -49,4 +56,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig index 9405755f9e..7f97166860 100644 --- a/configs/T4240RDB_SDCARD_defconfig +++ b/configs/T4240RDB_SDCARD_defconfig @@ -35,6 +35,8 @@ CONFIG_CMD_PING=y CONFIG_MP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="t4240rdb" CONFIG_ENV_IS_IN_MMC=y CONFIG_FSL_CAAM=y CONFIG_FSL_ESDHC=y @@ -49,6 +51,10 @@ CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y @@ -57,4 +63,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig index 446c141c8e..81bd59566d 100644 --- a/configs/T4240RDB_defconfig +++ b/configs/T4240RDB_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_MPC85xx=y CONFIG_TARGET_T4240RDB=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -21,6 +22,8 @@ CONFIG_CMD_PING=y CONFIG_MP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="t4240rdb" CONFIG_ENV_IS_IN_FLASH=y CONFIG_FSL_CAAM=y CONFIG_FSL_ESDHC=y @@ -35,6 +38,10 @@ CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y @@ -43,4 +50,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/alt_defconfig b/configs/alt_defconfig index a86ff906c8..49254e149d 100644 --- a/configs/alt_defconfig +++ b/configs/alt_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set @@ -25,6 +26,7 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig index af027a3c5d..d6db96c379 100644 --- a/configs/am335x_baltos_defconfig +++ b/configs/am335x_baltos_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig index e53b8ff115..47c4e99233 100644 --- a/configs/am335x_boneblack_vboot_defconfig +++ b/configs/am335x_boneblack_vboot_defconfig @@ -1,8 +1,7 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set -# CONFIG_TPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set -# CONFIG_TPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_AM33XX=y diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig index 649e8b49a2..2aa9b65caf 100644 --- a/configs/am335x_evm_defconfig +++ b/configs/am335x_evm_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_AM33XX=y diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig index df91615b5c..3cada51d35 100644 --- a/configs/am335x_guardian_defconfig +++ b/configs/am335x_guardian_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig index 42e7fc97ba..f5da7f674f 100644 --- a/configs/am335x_hs_evm_defconfig +++ b/configs/am335x_hs_evm_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_SECURE_DEVICE=y CONFIG_ISW_ENTRY_ADDR=0x40300350 diff --git a/configs/am335x_hs_evm_uart_defconfig b/configs/am335x_hs_evm_uart_defconfig index ba1b8a15ba..3708a6f623 100644 --- a/configs/am335x_hs_evm_uart_defconfig +++ b/configs/am335x_hs_evm_uart_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_SECURE_DEVICE=y CONFIG_ISW_ENTRY_ADDR=0x40301950 diff --git a/configs/am335x_igep003x_defconfig b/configs/am335x_igep003x_defconfig index 5874831ba1..8ed52a5ffb 100644 --- a/configs/am335x_igep003x_defconfig +++ b/configs/am335x_igep003x_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y diff --git a/configs/am335x_pdu001_defconfig b/configs/am335x_pdu001_defconfig index d6d9c69b9b..e69f81b6e5 100644 --- a/configs/am335x_pdu001_defconfig +++ b/configs/am335x_pdu001_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y diff --git a/configs/am335x_shc_defconfig b/configs/am335x_shc_defconfig index 972fc0ad22..5698208f84 100644 --- a/configs/am335x_shc_defconfig +++ b/configs/am335x_shc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y diff --git a/configs/am335x_shc_ict_defconfig b/configs/am335x_shc_ict_defconfig index 9a68ae47b0..3f8a6bad03 100644 --- a/configs/am335x_shc_ict_defconfig +++ b/configs/am335x_shc_ict_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y diff --git a/configs/am335x_shc_netboot_defconfig b/configs/am335x_shc_netboot_defconfig index c526cd568c..d0a7d62a24 100644 --- a/configs/am335x_shc_netboot_defconfig +++ b/configs/am335x_shc_netboot_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y diff --git a/configs/am335x_shc_sdboot_defconfig b/configs/am335x_shc_sdboot_defconfig index b412ecaf46..30fa40abda 100644 --- a/configs/am335x_shc_sdboot_defconfig +++ b/configs/am335x_shc_sdboot_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig index b10d045ab0..01fc52b4ed 100644 --- a/configs/am335x_sl50_defconfig +++ b/configs/am335x_sl50_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig index 932f9de3b2..ade4fd7c14 100644 --- a/configs/am3517_evm_defconfig +++ b/configs/am3517_evm_defconfig @@ -1,8 +1,6 @@ CONFIG_ARM=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set -# CONFIG_TPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set -# CONFIG_TPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_OMAP2PLUS=y CONFIG_SYS_TEXT_BASE=0x80100000 CONFIG_TI_COMMON_CMD_OPTIONS=y diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig index 152f489e1f..7c74047f3a 100644 --- a/configs/am43xx_evm_defconfig +++ b/configs/am43xx_evm_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SYS_MALLOC_F_LEN=0x2000 @@ -37,7 +38,6 @@ CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y -CONFIG_BLK=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig index 09f73d8c8f..b1bf67002b 100644 --- a/configs/am43xx_evm_qspiboot_defconfig +++ b/configs/am43xx_evm_qspiboot_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y # CONFIG_SYS_THUMB_BUILD is not set CONFIG_ARCH_OMAP2PLUS=y CONFIG_SYS_TEXT_BASE=0x30000000 @@ -34,7 +35,6 @@ CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y -CONFIG_BLK=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y @@ -50,6 +50,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_TI_QSPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y diff --git a/configs/am43xx_evm_rtconly_defconfig b/configs/am43xx_evm_rtconly_defconfig index 37a1f2b827..3064f3198d 100644 --- a/configs/am43xx_evm_rtconly_defconfig +++ b/configs/am43xx_evm_rtconly_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SYS_MALLOC_F_LEN=0x2000 @@ -29,7 +30,6 @@ CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm" CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm" CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y -CONFIG_BLK=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y @@ -49,6 +49,7 @@ CONFIG_TI_QSPI=y CONFIG_TIMER=y CONFIG_OMAP_TIMER=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig index dbc2fe11ea..9a2f31fef0 100644 --- a/configs/am43xx_evm_usbhost_boot_defconfig +++ b/configs/am43xx_evm_usbhost_boot_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_ISW_ENTRY_ADDR=0x40300350 CONFIG_SYS_MALLOC_F_LEN=0x2000 @@ -14,8 +15,9 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_ETHER=y CONFIG_SPL_USB_HOST_SUPPORT=y -CONFIG_SPL_USB_STORAGE=y CONFIG_CMD_SPL=y CONFIG_CMD_SPL_NAND_OFS=0x00100000 CONFIG_CMD_SPL_WRITE_SIZE=0x40000 @@ -41,7 +43,6 @@ CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm" CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y -CONFIG_BLK=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y @@ -61,6 +62,7 @@ CONFIG_TI_QSPI=y CONFIG_TIMER=y CONFIG_OMAP_TIMER=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig index 0a993b0ef0..8be210293c 100644 --- a/configs/am43xx_hs_evm_defconfig +++ b/configs/am43xx_hs_evm_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_SECURE_DEVICE=y CONFIG_ISW_ENTRY_ADDR=0x403018e0 @@ -26,7 +27,6 @@ CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_NET_SUPPORT=y CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL" CONFIG_SPL_USB_HOST_SUPPORT=y -CONFIG_SPL_USB_STORAGE=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_ETHER=y # CONFIG_CMD_FLASH is not set @@ -40,7 +40,6 @@ CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm" CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm" CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y -CONFIG_BLK=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y @@ -60,6 +59,7 @@ CONFIG_TI_QSPI=y CONFIG_TIMER=y CONFIG_OMAP_TIMER=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig index 96de6f48c9..248c302057 100644 --- a/configs/am57xx_evm_defconfig +++ b/configs/am57xx_evm_defconfig @@ -27,6 +27,7 @@ CONFIG_SPL_DMA_SUPPORT=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_DTIMG=y CONFIG_CMD_SPL=y diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig index d776a0b244..7b56df8db7 100644 --- a/configs/am57xx_hs_evm_defconfig +++ b/configs/am57xx_hs_evm_defconfig @@ -31,6 +31,7 @@ CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DMA_SUPPORT=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_CMD_DTIMG=y CONFIG_CMD_BCB=y # CONFIG_CMD_FLASH is not set diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig index 6419c53296..c8078e9f4e 100644 --- a/configs/am57xx_hs_evm_usb_defconfig +++ b/configs/am57xx_hs_evm_usb_defconfig @@ -33,6 +33,7 @@ CONFIG_SPL_DMA_SUPPORT=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_SPL_USB_GADGET=y CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y diff --git a/configs/amcore_defconfig b/configs/amcore_defconfig index 6a00ea29e4..d68d5223c1 100644 --- a/configs/amcore_defconfig +++ b/configs/amcore_defconfig @@ -12,6 +12,7 @@ CONFIG_SYS_PROMPT="amcore $ " CONFIG_CMD_IMLS=y # CONFIG_CMD_XIMG is not set CONFIG_LOOPW=y +CONFIG_MX_CYCLIC=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y CONFIG_CMD_TIMER=y diff --git a/configs/apalis-imx8qm_defconfig b/configs/apalis-imx8qm_defconfig index 46a0a2a975..6a259381c2 100644 --- a/configs/apalis-imx8qm_defconfig +++ b/configs/apalis-imx8qm_defconfig @@ -35,7 +35,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_IMX_LPI2C=y CONFIG_MISC=y CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_MICREL=y diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig index b76c4c1b85..7b73265abd 100644 --- a/configs/apalis_imx6_defconfig +++ b/configs/apalis_imx6_defconfig @@ -59,7 +59,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/configs/apx4devkit_defconfig b/configs/apx4devkit_defconfig index c5eb53ebef..138cfa648c 100644 --- a/configs/apx4devkit_defconfig +++ b/configs/apx4devkit_defconfig @@ -31,6 +31,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:128k(bootstrap),1024k(boot),768k(env),-(root)" CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_MXS_GPIO=y CONFIG_MMC_MXS=y CONFIG_NAND=y CONFIG_NAND_MXS=y diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index 33e40cd7d3..18ef5d2dce 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -35,7 +35,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_NAND=y CONFIG_NAND_MXS=y CONFIG_SPI_FLASH=y diff --git a/configs/aristainetos2b_defconfig b/configs/aristainetos2b_defconfig index 34a6cde1ee..1054c05d8c 100644 --- a/configs/aristainetos2b_defconfig +++ b/configs/aristainetos2b_defconfig @@ -35,7 +35,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_NAND=y CONFIG_NAND_MXS=y CONFIG_SPI_FLASH=y diff --git a/configs/aristainetos_defconfig b/configs/aristainetos_defconfig index cb361daafb..4080a7b310 100644 --- a/configs/aristainetos_defconfig +++ b/configs/aristainetos_defconfig @@ -35,7 +35,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_NAND=y CONFIG_NAND_MXS=y CONFIG_SPI_FLASH=y diff --git a/configs/armadillo-800eva_defconfig b/configs/armadillo-800eva_defconfig index 8168c3a7f7..6eefabd8b6 100644 --- a/configs/armadillo-800eva_defconfig +++ b/configs/armadillo-800eva_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y # CONFIG_SYS_THUMB_BUILD is not set CONFIG_ARCH_RMOBILE=y CONFIG_SYS_TEXT_BASE=0xE80C0000 diff --git a/configs/arndale_defconfig b/configs/arndale_defconfig index 6f586bae68..012d6f571d 100644 --- a/configs/arndale_defconfig +++ b/configs/arndale_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_EXYNOS=y CONFIG_SYS_TEXT_BASE=0x43E00000 CONFIG_ARCH_EXYNOS5=y diff --git a/configs/aspenite_defconfig b/configs/aspenite_defconfig index fed2de5c37..8e677172cf 100644 --- a/configs/aspenite_defconfig +++ b/configs/aspenite_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_TARGET_ASPENITE=y CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_NR_DRAM_BANKS=2 diff --git a/configs/at91rm9200ek_defconfig b/configs/at91rm9200ek_defconfig index 6b1ed50a1e..834457cb99 100644 --- a/configs/at91rm9200ek_defconfig +++ b/configs/at91rm9200ek_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x10000000 CONFIG_TARGET_AT91RM9200EK=y diff --git a/configs/at91rm9200ek_ram_defconfig b/configs/at91rm9200ek_ram_defconfig index 88a0bcfaa2..93171912bc 100644 --- a/configs/at91rm9200ek_ram_defconfig +++ b/configs/at91rm9200ek_ram_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x20100000 CONFIG_TARGET_AT91RM9200EK=y diff --git a/configs/at91sam9260ek_dataflash_cs0_defconfig b/configs/at91sam9260ek_dataflash_cs0_defconfig index 46e43c9df7..ef1b3b46be 100644 --- a/configs/at91sam9260ek_dataflash_cs0_defconfig +++ b/configs/at91sam9260ek_dataflash_cs0_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21f00000 CONFIG_TARGET_AT91SAM9260EK=y @@ -41,6 +42,7 @@ CONFIG_DM_GPIO=y CONFIG_AT91_GPIO=y # CONFIG_MMC is not set CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/at91sam9260ek_dataflash_cs1_defconfig b/configs/at91sam9260ek_dataflash_cs1_defconfig index 1274435e70..89129ce2f9 100644 --- a/configs/at91sam9260ek_dataflash_cs1_defconfig +++ b/configs/at91sam9260ek_dataflash_cs1_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21f00000 CONFIG_TARGET_AT91SAM9260EK=y @@ -41,6 +42,7 @@ CONFIG_DM_GPIO=y CONFIG_AT91_GPIO=y # CONFIG_MMC is not set CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/at91sam9260ek_nandflash_defconfig b/configs/at91sam9260ek_nandflash_defconfig index b9bad09002..79ef08c8ce 100644 --- a/configs/at91sam9260ek_nandflash_defconfig +++ b/configs/at91sam9260ek_nandflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21f00000 CONFIG_TARGET_AT91SAM9260EK=y @@ -36,6 +37,7 @@ CONFIG_DM_GPIO=y CONFIG_AT91_GPIO=y # CONFIG_MMC is not set CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/at91sam9261ek_dataflash_cs0_defconfig b/configs/at91sam9261ek_dataflash_cs0_defconfig index d061fbc1e6..410f71142d 100644 --- a/configs/at91sam9261ek_dataflash_cs0_defconfig +++ b/configs/at91sam9261ek_dataflash_cs0_defconfig @@ -42,6 +42,7 @@ CONFIG_DM_GPIO=y CONFIG_AT91_GPIO=y # CONFIG_MMC is not set CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/at91sam9261ek_dataflash_cs3_defconfig b/configs/at91sam9261ek_dataflash_cs3_defconfig index 95bfe7cecd..83437583b6 100644 --- a/configs/at91sam9261ek_dataflash_cs3_defconfig +++ b/configs/at91sam9261ek_dataflash_cs3_defconfig @@ -42,6 +42,7 @@ CONFIG_DM_GPIO=y CONFIG_AT91_GPIO=y # CONFIG_MMC is not set CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/at91sam9261ek_nandflash_defconfig b/configs/at91sam9261ek_nandflash_defconfig index d94f93003a..471715ab86 100644 --- a/configs/at91sam9261ek_nandflash_defconfig +++ b/configs/at91sam9261ek_nandflash_defconfig @@ -37,6 +37,7 @@ CONFIG_DM_GPIO=y CONFIG_AT91_GPIO=y # CONFIG_MMC is not set CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/at91sam9263ek_dataflash_cs0_defconfig b/configs/at91sam9263ek_dataflash_cs0_defconfig index b0d91e2019..ce30dbb370 100644 --- a/configs/at91sam9263ek_dataflash_cs0_defconfig +++ b/configs/at91sam9263ek_dataflash_cs0_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21F00000 CONFIG_TARGET_AT91SAM9263EK=y @@ -46,6 +47,7 @@ CONFIG_AT91_GPIO=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/at91sam9263ek_dataflash_defconfig b/configs/at91sam9263ek_dataflash_defconfig index b0d91e2019..ce30dbb370 100644 --- a/configs/at91sam9263ek_dataflash_defconfig +++ b/configs/at91sam9263ek_dataflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21F00000 CONFIG_TARGET_AT91SAM9263EK=y @@ -46,6 +47,7 @@ CONFIG_AT91_GPIO=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/at91sam9263ek_nandflash_defconfig b/configs/at91sam9263ek_nandflash_defconfig index b1cf7497ee..5149b34760 100644 --- a/configs/at91sam9263ek_nandflash_defconfig +++ b/configs/at91sam9263ek_nandflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21F00000 CONFIG_TARGET_AT91SAM9263EK=y @@ -41,6 +42,7 @@ CONFIG_AT91_GPIO=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/at91sam9263ek_norflash_boot_defconfig b/configs/at91sam9263ek_norflash_boot_defconfig index 51eb48eb1c..6e7ab93062 100644 --- a/configs/at91sam9263ek_norflash_boot_defconfig +++ b/configs/at91sam9263ek_norflash_boot_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x0000000 CONFIG_TARGET_AT91SAM9263EK=y @@ -45,6 +46,7 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI=y CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/at91sam9263ek_norflash_defconfig b/configs/at91sam9263ek_norflash_defconfig index 50f5e48d9f..03c55622e0 100644 --- a/configs/at91sam9263ek_norflash_defconfig +++ b/configs/at91sam9263ek_norflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21F00000 CONFIG_TARGET_AT91SAM9263EK=y @@ -45,6 +46,7 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI=y CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/at91sam9g10ek_dataflash_cs0_defconfig b/configs/at91sam9g10ek_dataflash_cs0_defconfig index 764612ae7e..8a3cf115dc 100644 --- a/configs/at91sam9g10ek_dataflash_cs0_defconfig +++ b/configs/at91sam9g10ek_dataflash_cs0_defconfig @@ -42,6 +42,7 @@ CONFIG_DM_GPIO=y CONFIG_AT91_GPIO=y # CONFIG_MMC is not set CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/at91sam9g10ek_dataflash_cs3_defconfig b/configs/at91sam9g10ek_dataflash_cs3_defconfig index 1527a5024f..89466b0014 100644 --- a/configs/at91sam9g10ek_dataflash_cs3_defconfig +++ b/configs/at91sam9g10ek_dataflash_cs3_defconfig @@ -42,6 +42,7 @@ CONFIG_DM_GPIO=y CONFIG_AT91_GPIO=y # CONFIG_MMC is not set CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/at91sam9g10ek_nandflash_defconfig b/configs/at91sam9g10ek_nandflash_defconfig index f498def21a..029cc9bbcf 100644 --- a/configs/at91sam9g10ek_nandflash_defconfig +++ b/configs/at91sam9g10ek_nandflash_defconfig @@ -37,6 +37,7 @@ CONFIG_DM_GPIO=y CONFIG_AT91_GPIO=y # CONFIG_MMC is not set CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/at91sam9g20ek_2mmc_defconfig b/configs/at91sam9g20ek_2mmc_defconfig index dde834356c..1c9cc0cdc9 100644 --- a/configs/at91sam9g20ek_2mmc_defconfig +++ b/configs/at91sam9g20ek_2mmc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21f00000 CONFIG_TARGET_AT91SAM9260EK=y @@ -40,6 +41,7 @@ CONFIG_AT91_GPIO=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/at91sam9g20ek_2mmc_nandflash_defconfig b/configs/at91sam9g20ek_2mmc_nandflash_defconfig index cf44706744..a0a149904d 100644 --- a/configs/at91sam9g20ek_2mmc_nandflash_defconfig +++ b/configs/at91sam9g20ek_2mmc_nandflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21f00000 CONFIG_TARGET_AT91SAM9260EK=y @@ -38,6 +39,7 @@ CONFIG_AT91_GPIO=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/at91sam9g20ek_dataflash_cs0_defconfig b/configs/at91sam9g20ek_dataflash_cs0_defconfig index d5bc5e3090..86c7116b83 100644 --- a/configs/at91sam9g20ek_dataflash_cs0_defconfig +++ b/configs/at91sam9g20ek_dataflash_cs0_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21f00000 CONFIG_TARGET_AT91SAM9260EK=y @@ -41,6 +42,7 @@ CONFIG_DM_GPIO=y CONFIG_AT91_GPIO=y # CONFIG_MMC is not set CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/at91sam9g20ek_dataflash_cs1_defconfig b/configs/at91sam9g20ek_dataflash_cs1_defconfig index 7abcdbe937..c1c7b21cd8 100644 --- a/configs/at91sam9g20ek_dataflash_cs1_defconfig +++ b/configs/at91sam9g20ek_dataflash_cs1_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21f00000 CONFIG_TARGET_AT91SAM9260EK=y @@ -41,6 +42,7 @@ CONFIG_DM_GPIO=y CONFIG_AT91_GPIO=y # CONFIG_MMC is not set CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/at91sam9g20ek_nandflash_defconfig b/configs/at91sam9g20ek_nandflash_defconfig index 73a967da4c..d8535b60d9 100644 --- a/configs/at91sam9g20ek_nandflash_defconfig +++ b/configs/at91sam9g20ek_nandflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21f00000 CONFIG_TARGET_AT91SAM9260EK=y @@ -36,6 +37,7 @@ CONFIG_DM_GPIO=y CONFIG_AT91_GPIO=y # CONFIG_MMC is not set CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/at91sam9m10g45ek_mmc_defconfig b/configs/at91sam9m10g45ek_mmc_defconfig index dc1dedd280..a5b6f45a8e 100644 --- a/configs/at91sam9m10g45ek_mmc_defconfig +++ b/configs/at91sam9m10g45ek_mmc_defconfig @@ -41,6 +41,7 @@ CONFIG_AT91_GPIO=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_ETH=y CONFIG_MACB=y diff --git a/configs/at91sam9m10g45ek_nandflash_defconfig b/configs/at91sam9m10g45ek_nandflash_defconfig index 21fb3f0c1a..44c50739a0 100644 --- a/configs/at91sam9m10g45ek_nandflash_defconfig +++ b/configs/at91sam9m10g45ek_nandflash_defconfig @@ -39,6 +39,7 @@ CONFIG_DM_GPIO=y CONFIG_AT91_GPIO=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_ETH=y CONFIG_MACB=y diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig index ce3603b6bb..aad6ee43f3 100644 --- a/configs/at91sam9n12ek_mmc_defconfig +++ b/configs/at91sam9n12ek_mmc_defconfig @@ -41,6 +41,7 @@ CONFIG_AT91_GPIO=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig index a54e8f02ff..a2cb37e1ae 100644 --- a/configs/at91sam9n12ek_nandflash_defconfig +++ b/configs/at91sam9n12ek_nandflash_defconfig @@ -39,6 +39,7 @@ CONFIG_DM_GPIO=y CONFIG_AT91_GPIO=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig index d8621462fd..e49a90d21f 100644 --- a/configs/at91sam9n12ek_spiflash_defconfig +++ b/configs/at91sam9n12ek_spiflash_defconfig @@ -43,6 +43,7 @@ CONFIG_AT91_GPIO=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/at91sam9rlek_dataflash_defconfig b/configs/at91sam9rlek_dataflash_defconfig index 463917c47d..85130d7a49 100644 --- a/configs/at91sam9rlek_dataflash_defconfig +++ b/configs/at91sam9rlek_dataflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21F00000 CONFIG_TARGET_AT91SAM9RLEK=y @@ -44,6 +45,7 @@ CONFIG_AT91_GPIO=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/at91sam9rlek_mmc_defconfig b/configs/at91sam9rlek_mmc_defconfig index 80a5b8deaf..38357632e7 100644 --- a/configs/at91sam9rlek_mmc_defconfig +++ b/configs/at91sam9rlek_mmc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21F00000 CONFIG_TARGET_AT91SAM9RLEK=y @@ -40,6 +41,7 @@ CONFIG_AT91_GPIO=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/at91sam9rlek_nandflash_defconfig b/configs/at91sam9rlek_nandflash_defconfig index 166659242b..41a59891af 100644 --- a/configs/at91sam9rlek_nandflash_defconfig +++ b/configs/at91sam9rlek_nandflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21F00000 CONFIG_TARGET_AT91SAM9RLEK=y @@ -39,6 +40,7 @@ CONFIG_AT91_GPIO=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/at91sam9x5ek_dataflash_defconfig b/configs/at91sam9x5ek_dataflash_defconfig index 1850231d25..10df6441a4 100644 --- a/configs/at91sam9x5ek_dataflash_defconfig +++ b/configs/at91sam9x5ek_dataflash_defconfig @@ -45,6 +45,7 @@ CONFIG_AT91_GPIO=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig index 3fd4a8132a..158c1ec3cb 100644 --- a/configs/at91sam9x5ek_mmc_defconfig +++ b/configs/at91sam9x5ek_mmc_defconfig @@ -43,6 +43,7 @@ CONFIG_AT91_GPIO=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig index 7d517257a2..b5c282dc25 100644 --- a/configs/at91sam9x5ek_nandflash_defconfig +++ b/configs/at91sam9x5ek_nandflash_defconfig @@ -41,6 +41,7 @@ CONFIG_DM_GPIO=y CONFIG_AT91_GPIO=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig index f73580e440..1fe37f96d1 100644 --- a/configs/at91sam9x5ek_spiflash_defconfig +++ b/configs/at91sam9x5ek_spiflash_defconfig @@ -45,6 +45,7 @@ CONFIG_AT91_GPIO=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/at91sam9xeek_dataflash_cs0_defconfig b/configs/at91sam9xeek_dataflash_cs0_defconfig index 00a0e5b2cc..c713735306 100644 --- a/configs/at91sam9xeek_dataflash_cs0_defconfig +++ b/configs/at91sam9xeek_dataflash_cs0_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21f00000 CONFIG_TARGET_AT91SAM9260EK=y @@ -41,6 +42,7 @@ CONFIG_DM_GPIO=y CONFIG_AT91_GPIO=y # CONFIG_MMC is not set CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/at91sam9xeek_dataflash_cs1_defconfig b/configs/at91sam9xeek_dataflash_cs1_defconfig index e42a6abcaf..1862fc4b5a 100644 --- a/configs/at91sam9xeek_dataflash_cs1_defconfig +++ b/configs/at91sam9xeek_dataflash_cs1_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21f00000 CONFIG_TARGET_AT91SAM9260EK=y @@ -41,6 +42,7 @@ CONFIG_DM_GPIO=y CONFIG_AT91_GPIO=y # CONFIG_MMC is not set CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/at91sam9xeek_nandflash_defconfig b/configs/at91sam9xeek_nandflash_defconfig index c566904e6b..110b1799f2 100644 --- a/configs/at91sam9xeek_nandflash_defconfig +++ b/configs/at91sam9xeek_nandflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21f00000 CONFIG_TARGET_AT91SAM9260EK=y @@ -36,6 +37,7 @@ CONFIG_DM_GPIO=y CONFIG_AT91_GPIO=y # CONFIG_MMC is not set CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/axm_defconfig b/configs/axm_defconfig index f1aba32552..a1d374aeb5 100644 --- a/configs/axm_defconfig +++ b/configs/axm_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SPL_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_SYS_THUMB_BUILD=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set @@ -20,7 +21,6 @@ CONFIG_DEBUG_UART_CLOCK=18432000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y -CONFIG_TPL_SYS_MALLOC_F_LEN=0x1000 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2068" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y @@ -29,7 +29,6 @@ CONFIG_BOOTCOMMAND="run flash_self" CONFIG_BOARD_EARLY_INIT_F=y # CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y -# CONFIG_TPL_BANNER_PRINT is not set CONFIG_SPL_CRC32_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_HUSH_PARSER=y @@ -59,6 +58,7 @@ CONFIG_CLK=y CONFIG_CLK_AT91=y # CONFIG_MMC is not set CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/bcm11130_defconfig b/configs/bcm11130_defconfig index f13c27777e..dc7d723fe3 100644 --- a/configs/bcm11130_defconfig +++ b/configs/bcm11130_defconfig @@ -11,6 +11,7 @@ CONFIG_HUSH_PARSER=y # CONFIG_AUTOBOOT is not set CONFIG_CMD_BOOTZ=y CONFIG_CMD_ASKENV=y +CONFIG_MX_CYCLIC=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/bcm11130_nand_defconfig b/configs/bcm11130_nand_defconfig index 2d941f339e..aa4105db39 100644 --- a/configs/bcm11130_nand_defconfig +++ b/configs/bcm11130_nand_defconfig @@ -10,6 +10,7 @@ CONFIG_HUSH_PARSER=y # CONFIG_AUTOBOOT is not set CONFIG_CMD_BOOTZ=y CONFIG_CMD_ASKENV=y +CONFIG_MX_CYCLIC=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/bcm23550_w1d_defconfig b/configs/bcm23550_w1d_defconfig index baffb2d117..b94b2db0a0 100644 --- a/configs/bcm23550_w1d_defconfig +++ b/configs/bcm23550_w1d_defconfig @@ -13,6 +13,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_ASKENV=y +CONFIG_MX_CYCLIC=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/bcm28155_ap_defconfig b/configs/bcm28155_ap_defconfig index d64c7b07d5..f04e3644c8 100644 --- a/configs/bcm28155_ap_defconfig +++ b/configs/bcm28155_ap_defconfig @@ -12,6 +12,7 @@ CONFIG_HUSH_PARSER=y # CONFIG_AUTOBOOT is not set CONFIG_CMD_BOOTZ=y CONFIG_CMD_ASKENV=y +CONFIG_MX_CYCLIC=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/bcm28155_w1d_defconfig b/configs/bcm28155_w1d_defconfig index 7972e273fd..9f3020c16e 100644 --- a/configs/bcm28155_w1d_defconfig +++ b/configs/bcm28155_w1d_defconfig @@ -11,6 +11,7 @@ CONFIG_HUSH_PARSER=y # CONFIG_AUTOBOOT is not set CONFIG_CMD_BOOTZ=y CONFIG_CMD_ASKENV=y +CONFIG_MX_CYCLIC=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y diff --git a/configs/bcm911360_entphn-ns_defconfig b/configs/bcm911360_entphn-ns_defconfig index be8a90e1f3..673c0f2182 100644 --- a/configs/bcm911360_entphn-ns_defconfig +++ b/configs/bcm911360_entphn-ns_defconfig @@ -11,6 +11,7 @@ CONFIG_HUSH_PARSER=y # CONFIG_AUTOBOOT is not set CONFIG_CMD_BOOTZ=y CONFIG_CMD_ASKENV=y +CONFIG_MX_CYCLIC=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_MII=y diff --git a/configs/bcm911360_entphn_defconfig b/configs/bcm911360_entphn_defconfig index ba81847a16..723482eb2d 100644 --- a/configs/bcm911360_entphn_defconfig +++ b/configs/bcm911360_entphn_defconfig @@ -11,6 +11,7 @@ CONFIG_HUSH_PARSER=y # CONFIG_AUTOBOOT is not set CONFIG_CMD_BOOTZ=y CONFIG_CMD_ASKENV=y +CONFIG_MX_CYCLIC=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_MII=y diff --git a/configs/bcm911360k_defconfig b/configs/bcm911360k_defconfig index 132234cf55..dfb9f8461f 100644 --- a/configs/bcm911360k_defconfig +++ b/configs/bcm911360k_defconfig @@ -11,6 +11,7 @@ CONFIG_HUSH_PARSER=y # CONFIG_AUTOBOOT is not set CONFIG_CMD_BOOTZ=y CONFIG_CMD_ASKENV=y +CONFIG_MX_CYCLIC=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_MII=y diff --git a/configs/bcm958300k-ns_defconfig b/configs/bcm958300k-ns_defconfig index d95ef15156..cc510530f6 100644 --- a/configs/bcm958300k-ns_defconfig +++ b/configs/bcm958300k-ns_defconfig @@ -11,6 +11,7 @@ CONFIG_HUSH_PARSER=y # CONFIG_AUTOBOOT is not set CONFIG_CMD_BOOTZ=y CONFIG_CMD_ASKENV=y +CONFIG_MX_CYCLIC=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_MII=y diff --git a/configs/bcm958300k_defconfig b/configs/bcm958300k_defconfig index 132234cf55..dfb9f8461f 100644 --- a/configs/bcm958300k_defconfig +++ b/configs/bcm958300k_defconfig @@ -11,6 +11,7 @@ CONFIG_HUSH_PARSER=y # CONFIG_AUTOBOOT is not set CONFIG_CMD_BOOTZ=y CONFIG_CMD_ASKENV=y +CONFIG_MX_CYCLIC=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_MII=y diff --git a/configs/bcm958305k_defconfig b/configs/bcm958305k_defconfig index 132234cf55..dfb9f8461f 100644 --- a/configs/bcm958305k_defconfig +++ b/configs/bcm958305k_defconfig @@ -11,6 +11,7 @@ CONFIG_HUSH_PARSER=y # CONFIG_AUTOBOOT is not set CONFIG_CMD_BOOTZ=y CONFIG_CMD_ASKENV=y +CONFIG_MX_CYCLIC=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_MII=y diff --git a/configs/bcm958622hr_defconfig b/configs/bcm958622hr_defconfig index d5cb7f680d..5ee8c6912b 100644 --- a/configs/bcm958622hr_defconfig +++ b/configs/bcm958622hr_defconfig @@ -12,6 +12,7 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_ASKENV=y CONFIG_CRC32_VERIFY=y +CONFIG_MX_CYCLIC=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y diff --git a/configs/bcm963158_ram_defconfig b/configs/bcm963158_ram_defconfig index 5eafbaaa5a..8863131ed0 100644 --- a/configs/bcm963158_ram_defconfig +++ b/configs/bcm963158_ram_defconfig @@ -3,11 +3,9 @@ CONFIG_ARM=y CONFIG_ARCH_BCM63158=y CONFIG_SYS_TEXT_BASE=0x10000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 CONFIG_NR_DRAM_BANKS=1 CONFIG_TARGET_BCM963158=y CONFIG_ENV_VARS_UBOOT_CONFIG=y -CONFIG_TPL_SYS_MALLOC_F_LEN=0x400 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT=y diff --git a/configs/bcm968580xref_ram_defconfig b/configs/bcm968580xref_ram_defconfig index 49731ee230..7e63dd145b 100644 --- a/configs/bcm968580xref_ram_defconfig +++ b/configs/bcm968580xref_ram_defconfig @@ -2,11 +2,9 @@ CONFIG_ARM=y CONFIG_ARCH_BCM6858=y CONFIG_SYS_TEXT_BASE=0x10000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 CONFIG_NR_DRAM_BANKS=1 CONFIG_TARGET_BCM968580XREF=y CONFIG_ENV_VARS_UBOOT_CONFIG=y -CONFIG_TPL_SYS_MALLOC_F_LEN=0x400 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y diff --git a/configs/bg0900_defconfig b/configs/bg0900_defconfig index 353790f446..d0d527c8f0 100644 --- a/configs/bg0900_defconfig +++ b/configs/bg0900_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_DOS_PARTITION=y +CONFIG_MXS_GPIO=y # CONFIG_MMC is not set CONFIG_NAND=y CONFIG_NAND_MXS=y diff --git a/configs/birdland_bav335a_defconfig b/configs/birdland_bav335a_defconfig index eea1223a85..422d093328 100644 --- a/configs/birdland_bav335a_defconfig +++ b/configs/birdland_bav335a_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y diff --git a/configs/birdland_bav335b_defconfig b/configs/birdland_bav335b_defconfig index 7358fe5278..5b4f9b7b99 100644 --- a/configs/birdland_bav335b_defconfig +++ b/configs/birdland_bav335b_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y diff --git a/configs/blanche_defconfig b/configs/blanche_defconfig index c2d53a3d11..58ee355db4 100644 --- a/configs/blanche_defconfig +++ b/configs/blanche_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y CONFIG_ARCH_RMOBILE=y CONFIG_SYS_TEXT_BASE=0x00000000 diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig index 94b9babf5e..d0ee6194cf 100644 --- a/configs/brppt1_mmc_defconfig +++ b/configs/brppt1_mmc_defconfig @@ -12,7 +12,6 @@ CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x40000 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y -CONFIG_TPL_SYS_MALLOC_F_LEN=0x0 # CONFIG_EXPERT is not set # CONFIG_FIT is not set CONFIG_OF_BOARD_SETUP=y diff --git a/configs/brppt1_nand_defconfig b/configs/brppt1_nand_defconfig index 75fc6b7dcd..ff227de4b7 100644 --- a/configs/brppt1_nand_defconfig +++ b/configs/brppt1_nand_defconfig @@ -11,7 +11,6 @@ CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x60000 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y -CONFIG_TPL_SYS_MALLOC_F_LEN=0x0 # CONFIG_EXPERT is not set # CONFIG_FIT is not set CONFIG_OF_BOARD_SETUP=y diff --git a/configs/brppt1_spi_defconfig b/configs/brppt1_spi_defconfig index 9d629f69c5..a29dc0385e 100644 --- a/configs/brppt1_spi_defconfig +++ b/configs/brppt1_spi_defconfig @@ -14,7 +14,6 @@ CONFIG_SPL=y CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y -CONFIG_TPL_SYS_MALLOC_F_LEN=0x0 # CONFIG_EXPERT is not set # CONFIG_FIT is not set CONFIG_OF_BOARD_SETUP=y @@ -38,6 +37,7 @@ CONFIG_SPL_I2C_SUPPORT=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y diff --git a/configs/brsmarc1_defconfig b/configs/brsmarc1_defconfig index 7882def964..8863a2d5cc 100644 --- a/configs/brsmarc1_defconfig +++ b/configs/brsmarc1_defconfig @@ -15,7 +15,6 @@ CONFIG_SPL=y CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y -CONFIG_TPL_SYS_MALLOC_F_LEN=0x0 # CONFIG_EXPERT is not set # CONFIG_FIT is not set CONFIG_OF_BOARD_SETUP=y @@ -37,6 +36,7 @@ CONFIG_SPL_I2C_SUPPORT=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_BOOTD is not set diff --git a/configs/brxre1_defconfig b/configs/brxre1_defconfig index 1ca7099e90..d4169c0327 100644 --- a/configs/brxre1_defconfig +++ b/configs/brxre1_defconfig @@ -13,7 +13,6 @@ CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x40000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000 CONFIG_SPL=y -CONFIG_TPL_SYS_MALLOC_F_LEN=0x0 # CONFIG_EXPERT is not set # CONFIG_FIT is not set CONFIG_OF_BOARD_SETUP=y @@ -30,7 +29,6 @@ CONFIG_VERSION_VARIABLE=y CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y -# CONFIG_TPL_BANNER_PRINT is not set CONFIG_SPL_I2C_SUPPORT=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_POWER_SUPPORT=y diff --git a/configs/cgtqmx6eval_defconfig b/configs/cgtqmx6eval_defconfig index ec042d7912..fd4e3077ac 100644 --- a/configs/cgtqmx6eval_defconfig +++ b/configs/cgtqmx6eval_defconfig @@ -25,6 +25,7 @@ CONFIG_SPL_TEXT_BASE=0x00908000 CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="CGT-QMX6-Quad U-Boot > " @@ -55,7 +56,7 @@ CONFIG_DFU_MMC=y CONFIG_DFU_SF=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig index e208a2191d..f275d21d16 100644 --- a/configs/chiliboard_defconfig +++ b/configs/chiliboard_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index f7beb790d2..18f6c388c6 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -24,6 +24,7 @@ CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 # CONFIG_SPL_CRC32_SUPPORT is not set CONFIG_SPL_PAYLOAD="u-boot.img" CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index d6fc7e3b63..967162248c 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -18,9 +18,11 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff8c2000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index 10b041e73f..3d2188a23a 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -26,6 +26,7 @@ CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 # CONFIG_SPL_CRC32_SUPPORT is not set CONFIG_SPL_PAYLOAD="u-boot.img" CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index a133276559..7047440e74 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -25,6 +25,7 @@ CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 # CONFIG_SPL_CRC32_SUPPORT is not set CONFIG_SPL_PAYLOAD="u-boot.img" CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig index 7891d62af1..5319ecb253 100644 --- a/configs/chromebook_speedy_defconfig +++ b/configs/chromebook_speedy_defconfig @@ -26,6 +26,7 @@ CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 # CONFIG_SPL_CRC32_SUPPORT is not set CONFIG_SPL_PAYLOAD="u-boot.img" CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/ci20_mmc_defconfig b/configs/ci20_mmc_defconfig index 56fd44647a..69a449f9e7 100644 --- a/configs/ci20_mmc_defconfig +++ b/configs/ci20_mmc_defconfig @@ -17,7 +17,6 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_TEXT_BASE=0xf4000a00 # CONFIG_SPL_BANNER_PRINT is not set -# CONFIG_TPL_BANNER_PRINT is not set CONFIG_SPL_MMC_TINY=y CONFIG_HUSH_PARSER=y CONFIG_CMD_DM=y diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig index cad8f4bc5b..04d1042060 100644 --- a/configs/cl-som-imx7_defconfig +++ b/configs/cl-som-imx7_defconfig @@ -51,7 +51,7 @@ CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig index 280c981a36..040e6b9969 100644 --- a/configs/clearfog_defconfig +++ b/configs/clearfog_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00800000 diff --git a/configs/clearfog_gt_8k_defconfig b/configs/clearfog_gt_8k_defconfig index a4f6f096fb..cbca2de13b 100644 --- a/configs/clearfog_gt_8k_defconfig +++ b/configs/clearfog_gt_8k_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig index 6f4fe45760..fd0db4db5c 100644 --- a/configs/cm_fx6_defconfig +++ b/configs/cm_fx6_defconfig @@ -26,6 +26,7 @@ CONFIG_SPL_TEXT_BASE=0x00908000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80 CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SYS_PROMPT="CM-FX6 # " # CONFIG_CMD_XIMG is not set @@ -57,7 +58,7 @@ CONFIG_DWC_AHSATA=y # CONFIG_DWC_AHSATA_AHCI is not set CONFIG_DM_KEYBOARD=y CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_NAND=y CONFIG_NAND_MXS=y CONFIG_SPI_FLASH=y diff --git a/configs/cm_t335_defconfig b/configs/cm_t335_defconfig index 550ee2b5fc..ab9f1fde44 100644 --- a/configs/cm_t335_defconfig +++ b/configs/cm_t335_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig index 204e641c43..214a054ac4 100644 --- a/configs/cm_t43_defconfig +++ b/configs/cm_t43_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -29,6 +30,7 @@ CONFIG_SPL_MTD_SUPPORT=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_SYS_PROMPT="CM-T43 # " CONFIG_CMD_ASKENV=y CONFIG_CMD_EEPROM=y diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig index e184223773..25a8ba533f 100644 --- a/configs/colibri-imx6ull_defconfig +++ b/configs/colibri-imx6ull_defconfig @@ -52,9 +52,10 @@ CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_NAND=y +CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_MXS=y CONFIG_NAND_MXS_DT=y CONFIG_MTD_UBI_FASTMAP=y diff --git a/configs/colibri-imx8qxp_defconfig b/configs/colibri-imx8qxp_defconfig index b35ec5841d..a223a16ddd 100644 --- a/configs/colibri-imx8qxp_defconfig +++ b/configs/colibri-imx8qxp_defconfig @@ -34,7 +34,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_IMX_LPI2C=y CONFIG_MISC=y CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_MICREL=y diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig index f792a9ef5c..6f8b63949c 100644 --- a/configs/colibri_imx6_defconfig +++ b/configs/colibri_imx6_defconfig @@ -58,7 +58,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index 8e769cd70e..c1bee450f6 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -52,7 +52,7 @@ CONFIG_DFU_NAND=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_NAND=y CONFIG_NAND_MXS_DT=y diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig index 5a5104c2ee..1a012d851e 100644 --- a/configs/colibri_imx7_emmc_defconfig +++ b/configs/colibri_imx7_emmc_defconfig @@ -52,7 +52,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y diff --git a/configs/colibri_pxa270_defconfig b/configs/colibri_pxa270_defconfig index 7c420582c5..ab2d1851c6 100644 --- a/configs/colibri_pxa270_defconfig +++ b/configs/colibri_pxa270_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_TARGET_COLIBRI_PXA270=y CONFIG_SYS_TEXT_BASE=0x0 CONFIG_SYS_MALLOC_F_LEN=0x2000 diff --git a/configs/controlcenterdc_defconfig b/configs/controlcenterdc_defconfig index 93abad2a81..46fe75365b 100644 --- a/configs/controlcenterdc_defconfig +++ b/configs/controlcenterdc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00800000 CONFIG_SPL_GPIO_SUPPORT=y @@ -24,6 +25,7 @@ CONFIG_SPL_TEXT_BASE=0x40000030 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x30000 CONFIG_HUSH_PARSER=y # CONFIG_CMD_ELF is not set # CONFIG_CMD_GO is not set diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig index 3894d19264..f4d45272ba 100644 --- a/configs/corvus_defconfig +++ b/configs/corvus_defconfig @@ -47,6 +47,7 @@ CONFIG_CLK_AT91=y CONFIG_DFU_NAND=y # CONFIG_MMC is not set CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_PHYLIB=y CONFIG_ATMEL_USART=y diff --git a/configs/crs305-1g-4s_defconfig b/configs/crs305-1g-4s_defconfig index c5e2d890cd..c396a7c5ba 100644 --- a/configs/crs305-1g-4s_defconfig +++ b/configs/crs305-1g-4s_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00800000 CONFIG_SYS_MALLOC_F_LEN=0x2000 diff --git a/configs/d2net_v2_defconfig b/configs/d2net_v2_defconfig index 2723c56068..b4cf22c4d7 100644 --- a/configs/d2net_v2_defconfig +++ b/configs/d2net_v2_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_NET2BIG_V2=y diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig index 7cbc9fb656..cfd910ad26 100644 --- a/configs/da850evm_defconfig +++ b/configs/da850evm_defconfig @@ -24,9 +24,11 @@ CONFIG_SPL_TEXT_BASE=0x80000000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CRC32_VERIFY=y +CONFIG_MX_CYCLIC=y CONFIG_CMD_DM=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_GPT is not set diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig index 407a30fbbf..698ac13a28 100644 --- a/configs/da850evm_direct_nor_defconfig +++ b/configs/da850evm_direct_nor_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_DAVINCI=y CONFIG_SYS_TEXT_BASE=0x60000000 CONFIG_TARGET_DA850EVM=y @@ -20,6 +21,7 @@ CONFIG_SYS_PROMPT="U-Boot > " # CONFIG_CMD_BOOTZ is not set CONFIG_CMD_IMLS=y CONFIG_CRC32_VERIFY=y +CONFIG_MX_CYCLIC=y CONFIG_CMD_DM=y # CONFIG_CMD_GPT is not set # CONFIG_CMD_MMC is not set @@ -38,6 +40,7 @@ CONFIG_DEFAULT_DEVICE_TREE="da850-evm" CONFIG_ENV_IS_IN_FLASH=y CONFIG_DM=y CONFIG_BLK=y +CONFIG_DM_GPIO=y CONFIG_DA8XX_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DAVINCI=y diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig index 0ad4b66991..701093977e 100644 --- a/configs/da850evm_nand_defconfig +++ b/configs/da850evm_nand_defconfig @@ -23,9 +23,11 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CRC32_VERIFY=y +CONFIG_MX_CYCLIC=y CONFIG_CMD_DM=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_GPT is not set @@ -51,6 +53,7 @@ CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_MTD=y CONFIG_NAND=y +CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x28000 @@ -61,6 +64,8 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_DRIVER_TI_EMAC=y CONFIG_PHY=y CONFIG_PHY_DA8XX_USB=y CONFIG_PINCTRL=y diff --git a/configs/db-88f6281-bp-nand_defconfig b/configs/db-88f6281-bp-nand_defconfig index ffb24eaf58..0d046834a4 100644 --- a/configs/db-88f6281-bp-nand_defconfig +++ b/configs/db-88f6281-bp-nand_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_SYS_THUMB_BUILD=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x600000 diff --git a/configs/db-88f6281-bp-spi_defconfig b/configs/db-88f6281-bp-spi_defconfig index 4b1b158d4d..01ef497682 100644 --- a/configs/db-88f6281-bp-spi_defconfig +++ b/configs/db-88f6281-bp-spi_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_SYS_THUMB_BUILD=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x600000 diff --git a/configs/db-88f6720_defconfig b/configs/db-88f6720_defconfig index a2d27efd80..8270b77309 100644 --- a/configs/db-88f6720_defconfig +++ b/configs/db-88f6720_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00800000 CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -22,6 +23,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0x40004030 CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_SF=y diff --git a/configs/db-88f6820-amc_defconfig b/configs/db-88f6820-amc_defconfig index 38d519237f..82308b4196 100644 --- a/configs/db-88f6820-amc_defconfig +++ b/configs/db-88f6820-amc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00800000 CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -23,6 +24,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0x40000030 CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x24000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_PCI=y @@ -55,6 +57,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_MVTWSI=y # CONFIG_MMC is not set CONFIG_NAND=y +CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_PXA3XX=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=1 diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig index f54538ab11..7beca5d80b 100644 --- a/configs/db-88f6820-gp_defconfig +++ b/configs/db-88f6820-gp_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00800000 CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -23,6 +24,7 @@ CONFIG_SPL_TEXT_BASE=0x40000030 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x24000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig index 5654fd7b44..7d86e065e3 100644 --- a/configs/db-mv784mp-gp_defconfig +++ b/configs/db-mv784mp-gp_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00800000 CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -22,6 +23,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0x40004030 CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_PCI=y @@ -51,6 +53,7 @@ CONFIG_SATA_MV=y CONFIG_BLK=y # CONFIG_MMC is not set CONFIG_NAND=y +CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_PXA3XX=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/db-xc3-24g4xg_defconfig b/configs/db-xc3-24g4xg_defconfig index 3a311ebdf2..de34d1fd6f 100644 --- a/configs/db-xc3-24g4xg_defconfig +++ b/configs/db-xc3-24g4xg_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00800000 CONFIG_SYS_MALLOC_F_LEN=0x2000 @@ -37,6 +38,7 @@ CONFIG_SYS_I2C_MVTWSI=y CONFIG_MTD=y CONFIG_MTD_DEVICE=y CONFIG_NAND=y +CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_PXA3XX=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SFDP_SUPPORT=y diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig index a47cf02b8f..ae7be20f99 100644 --- a/configs/devkit3250_defconfig +++ b/configs/devkit3250_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_SYS_ICACHE_OFF=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_LPC32XX=y CONFIG_SYS_TEXT_BASE=0x83F00000 CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -37,6 +38,7 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_NAND=y +CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_LPC32XX_SLC=y CONFIG_SPL_NAND_SIMPLE=y CONFIG_PHYLIB=y diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index 3022a187cc..f59f2e78ae 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -24,6 +24,7 @@ CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_BOUNCE_BUFFER=y CONFIG_SPL_TEXT_BASE=0x00908000 CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400 CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_UNZIP=y @@ -52,7 +53,7 @@ CONFIG_SYS_I2C_MXC=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 diff --git a/configs/display5_defconfig b/configs/display5_defconfig index 2275ee7d1b..8609cd5a8c 100644 --- a/configs/display5_defconfig +++ b/configs/display5_defconfig @@ -16,7 +16,6 @@ CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y -CONFIG_TPL_SYS_MALLOC_F_LEN=0x400 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y CONFIG_OF_BOARD_SETUP=y @@ -33,6 +32,7 @@ CONFIG_SPL_SAVEENV=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="display5 > " @@ -67,7 +67,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_MTD_DEVICE=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=1 diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig index 40df91a59b..70c64260d8 100644 --- a/configs/display5_factory_defconfig +++ b/configs/display5_factory_defconfig @@ -26,6 +26,7 @@ CONFIG_SPL_DMA_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_SPL_USB_HOST_SUPPORT=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y @@ -65,7 +66,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DFU_MMC=y CONFIG_DFU_SF=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_MTD_DEVICE=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=1 diff --git a/configs/dms-ba16-1g_defconfig b/configs/dms-ba16-1g_defconfig index 91b6a7424f..fe23657107 100644 --- a/configs/dms-ba16-1g_defconfig +++ b/configs/dms-ba16-1g_defconfig @@ -33,7 +33,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DWC_AHSATA=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 diff --git a/configs/dms-ba16_defconfig b/configs/dms-ba16_defconfig index fbf1f89ece..a4c93a5805 100644 --- a/configs/dms-ba16_defconfig +++ b/configs/dms-ba16_defconfig @@ -32,7 +32,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DWC_AHSATA=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig index 6dec69d73a..6e95fb265e 100644 --- a/configs/dns325_defconfig +++ b/configs/dns325_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_DNS325=y diff --git a/configs/dockstar_defconfig b/configs/dockstar_defconfig index 70fbb3660a..18df663b7b 100644 --- a/configs/dockstar_defconfig +++ b/configs/dockstar_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_DOCKSTAR=y diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index 682e301822..ad8868e512 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -26,6 +26,7 @@ CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DMA_SUPPORT=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_CMD_SPL=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index 7b50d2cbc6..7a5c3e72d4 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -31,6 +31,7 @@ CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DMA_SUPPORT=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y CONFIG_CMD_MTDPARTS=y diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig index 6d6bfbc493..040e6f7fdd 100644 --- a/configs/dra7xx_hs_evm_usb_defconfig +++ b/configs/dra7xx_hs_evm_usb_defconfig @@ -34,6 +34,7 @@ CONFIG_SPL_DMA_SUPPORT=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_SPL_USB_GADGET=y CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y diff --git a/configs/draco_defconfig b/configs/draco_defconfig index d6b2b4a42b..4ba3bde2e6 100644 --- a/configs/draco_defconfig +++ b/configs/draco_defconfig @@ -25,6 +25,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y # CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig index 5762c70a4a..206539da5b 100644 --- a/configs/dreamplug_defconfig +++ b/configs/dreamplug_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_DREAMPLUG=y diff --git a/configs/ds109_defconfig b/configs/ds109_defconfig index a22c067a3e..8f332a021d 100644 --- a/configs/ds109_defconfig +++ b/configs/ds109_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_DS109=y diff --git a/configs/ds414_defconfig b/configs/ds414_defconfig index 3f8c1773c4..2f365ddfb2 100644 --- a/configs/ds414_defconfig +++ b/configs/ds414_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00800000 CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -23,6 +24,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0x40004030 CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x24000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_PCI=y diff --git a/configs/edminiv2_defconfig b/configs/edminiv2_defconfig index fae0874ca5..d663090992 100644 --- a/configs/edminiv2_defconfig +++ b/configs/edminiv2_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ORION5X=y CONFIG_SYS_TEXT_BASE=0x00800000 CONFIG_SPL_LIBCOMMON_SUPPORT=y diff --git a/configs/espresso7420_defconfig b/configs/espresso7420_defconfig index 2031f18616..1b35881476 100644 --- a/configs/espresso7420_defconfig +++ b/configs/espresso7420_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_EXYNOS=y CONFIG_SYS_TEXT_BASE=0x43E00000 CONFIG_ARCH_EXYNOS7=y diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig index cec52592ef..31e711d32f 100644 --- a/configs/etamin_defconfig +++ b/configs/etamin_defconfig @@ -26,6 +26,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y # CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set diff --git a/configs/ethernut5_defconfig b/configs/ethernut5_defconfig index 04f8668fce..45a9175dac 100644 --- a/configs/ethernut5_defconfig +++ b/configs/ethernut5_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x27000000 CONFIG_TARGET_ETHERNUT5=y @@ -57,6 +58,7 @@ CONFIG_DM_GPIO=y CONFIG_AT91_GPIO=y CONFIG_MTD_NOR_FLASH=y CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig index 46a42a7df6..5a06b2a99f 100644 --- a/configs/evb-px5_defconfig +++ b/configs/evb-px5_defconfig @@ -29,6 +29,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-px5-evb.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_ARCH_EARLY_INIT_R=y CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig index 3f9a94d517..128fbcd64c 100644 --- a/configs/evb-rk3229_defconfig +++ b/configs/evb-rk3229_defconfig @@ -68,6 +68,5 @@ CONFIG_USB_GADGET_MANUFACTURER="Rockchip" CONFIG_USB_GADGET_VENDOR_NUM=0x2207 CONFIG_USB_GADGET_PRODUCT_NUM=0x320a CONFIG_USB_GADGET_DWC2_OTG=y -CONFIG_USB_FUNCTION_MASS_STORAGE=y CONFIG_TPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 2868f0f133..37610774c1 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -20,6 +20,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y CONFIG_TPL_DRIVERS_MISC_SUPPORT=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 14cca5bf2e..a0d215a5f1 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y diff --git a/configs/fennec-rk3288_defconfig b/configs/fennec-rk3288_defconfig deleted file mode 100644 index c6d1ddbd6b..0000000000 --- a/configs/fennec-rk3288_defconfig +++ /dev/null @@ -1,84 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_ROCKCHIP=y -CONFIG_SYS_TEXT_BASE=0x00000000 -CONFIG_ROCKCHIP_RK3288=y -CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y -CONFIG_TARGET_FENNEC_RK3288=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SPL_STACK_R_ADDR=0x80000 -CONFIG_DEBUG_UART_BASE=0xff690000 -CONFIG_DEBUG_UART_CLOCK=24000000 -CONFIG_DEBUG_UART=y -# CONFIG_ANDROID_BOOT_IMAGE is not set -CONFIG_USE_PREBOOT=y -CONFIG_SILENT_CONSOLE=y -CONFIG_CONSOLE_MUX=y -CONFIG_DEFAULT_FDT_FILE="rk3288-fennec.dtb" -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_TEXT_BASE=0xff704000 -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_CACHE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_PMIC=y -CONFIG_CMD_REGULATOR=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set -CONFIG_SPL_PARTITION_UUIDS=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="rk3288-fennec" -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_ENV_IS_IN_MMC=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -# CONFIG_SPL_SIMPLE_BUS is not set -CONFIG_CLK=y -CONFIG_SPL_CLK=y -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -CONFIG_ROCKCHIP_GPIO=y -CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_MMC_DW=y -CONFIG_MMC_DW_ROCKCHIP=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_DM_ETH=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_GMAC_ROCKCHIP=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y -CONFIG_PMIC_RK8XX=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_REGULATOR_RK8XX=y -CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y -CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_SYSRESET=y -CONFIG_USB=y -CONFIG_USB_DWC2=y -CONFIG_ROCKCHIP_USB2_PHY=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Rockchip" -CONFIG_USB_GADGET_VENDOR_NUM=0x2207 -CONFIG_USB_GADGET_PRODUCT_NUM=0x320a -CONFIG_USB_GADGET_DWC2_OTG=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y -CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_CMD_DHRYSTONE=y -CONFIG_ERRNO_STR=y diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index c3d8656d71..8b3692cdf0 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff8c2000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_CMD_BOOTZ=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 38ac8a32c3..d022631465 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y diff --git a/configs/gardena-smart-gateway-at91sam_defconfig b/configs/gardena-smart-gateway-at91sam_defconfig index ddfebc8ea0..c495ba4612 100644 --- a/configs/gardena-smart-gateway-at91sam_defconfig +++ b/configs/gardena-smart-gateway-at91sam_defconfig @@ -27,7 +27,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SPL_TEXT_BASE=0x300000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y -# CONFIG_TPL_BANNER_PRINT is not set # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_NAND_SUPPORT=y CONFIG_HUSH_PARSER=y @@ -67,6 +66,7 @@ CONFIG_AT91_GPIO=y CONFIG_LED=y CONFIG_LED_GPIO=y # CONFIG_MMC is not set +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_DM_ETH=y diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig index 54197f7541..735165916a 100644 --- a/configs/ge_bx50v3_defconfig +++ b/configs/ge_bx50v3_defconfig @@ -43,7 +43,7 @@ CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="1:5" CONFIG_DM_GPIO=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig index 5984bee1ae..5fa8b4d1f5 100644 --- a/configs/goflexhome_defconfig +++ b/configs/goflexhome_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_GOFLEXHOME=y diff --git a/configs/gose_defconfig b/configs/gose_defconfig index f591bd845b..f9906ebfb8 100644 --- a/configs/gose_defconfig +++ b/configs/gose_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set @@ -25,6 +26,7 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/gplugd_defconfig b/configs/gplugd_defconfig index d0c1abf080..4766be03b8 100644 --- a/configs/gplugd_defconfig +++ b/configs/gplugd_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_TARGET_GPLUGD=y CONFIG_SYS_TEXT_BASE=0x00f00000 CONFIG_NR_DRAM_BANKS=2 diff --git a/configs/grpeach_defconfig b/configs/grpeach_defconfig index adabfbc085..4a243d679f 100644 --- a/configs/grpeach_defconfig +++ b/configs/grpeach_defconfig @@ -1,5 +1,5 @@ CONFIG_ARM=y -# CONFIG_SPL_SYS_THUMB_BUILD is not set +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_RMOBILE=y CONFIG_SYS_TEXT_BASE=0x18000000 CONFIG_RZA1=y diff --git a/configs/gurnard_defconfig b/configs/gurnard_defconfig index 5001385426..f461d92980 100644 --- a/configs/gurnard_defconfig +++ b/configs/gurnard_defconfig @@ -28,6 +28,7 @@ CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-gurnard" CONFIG_ENV_IS_IN_NAND=y CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_ATMEL_NAND_HWECC=y CONFIG_PHYLIB=y diff --git a/configs/guruplug_defconfig b/configs/guruplug_defconfig index c1827a16f2..12ca8b35a8 100644 --- a/configs/guruplug_defconfig +++ b/configs/guruplug_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_GURUPLUG=y diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index 64516bbb8b..5d869c08e1 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -63,7 +63,7 @@ CONFIG_DM=y CONFIG_DWC_AHSATA=y CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_MTD_DEVICE=y CONFIG_PHYLIB=y CONFIG_E1000=y diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index cf47190938..df3d35acc4 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -63,7 +63,7 @@ CONFIG_DM=y CONFIG_DWC_AHSATA=y CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_MTD_DEVICE=y CONFIG_PHYLIB=y CONFIG_MV88E61XX_SWITCH=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index e511fd3cb3..a0d38ae97b 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -66,7 +66,7 @@ CONFIG_DM=y CONFIG_DWC_AHSATA=y CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_NAND=y CONFIG_NAND_MXS=y CONFIG_PHYLIB=y diff --git a/configs/helios4_defconfig b/configs/helios4_defconfig index 9710c3af72..cd6b476e10 100644 --- a/configs/helios4_defconfig +++ b/configs/helios4_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00800000 CONFIG_SPL_LIBCOMMON_SUPPORT=y diff --git a/configs/ib62x0_defconfig b/configs/ib62x0_defconfig index 4998db3669..13a2e83a0b 100644 --- a/configs/ib62x0_defconfig +++ b/configs/ib62x0_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_IB62X0=y diff --git a/configs/iconnect_defconfig b/configs/iconnect_defconfig index 53ba459965..aa67a6cef0 100644 --- a/configs/iconnect_defconfig +++ b/configs/iconnect_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_ICONNECT=y diff --git a/configs/imx6dl_icore_nand_defconfig b/configs/imx6dl_icore_nand_defconfig index b86b9e8773..6eb7c7ab3a 100644 --- a/configs/imx6dl_icore_nand_defconfig +++ b/configs/imx6dl_icore_nand_defconfig @@ -39,7 +39,7 @@ CONFIG_CMD_UBI=y CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore" CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_I2C_MXC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_NAND=y CONFIG_NAND_MXS=y CONFIG_PHYLIB=y diff --git a/configs/imx6dl_mamoj_defconfig b/configs/imx6dl_mamoj_defconfig index dbf230c7d6..44486cbfa3 100644 --- a/configs/imx6dl_mamoj_defconfig +++ b/configs/imx6dl_mamoj_defconfig @@ -32,7 +32,7 @@ CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=2 CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y diff --git a/configs/imx6q_icore_nand_defconfig b/configs/imx6q_icore_nand_defconfig index 4ea0803ab5..fc990a8add 100644 --- a/configs/imx6q_icore_nand_defconfig +++ b/configs/imx6q_icore_nand_defconfig @@ -40,7 +40,7 @@ CONFIG_CMD_UBI=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore" CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_I2C_MXC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_NAND=y CONFIG_NAND_MXS=y CONFIG_PHYLIB=y diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig index 290e1a7558..12f49db790 100644 --- a/configs/imx6q_logic_defconfig +++ b/configs/imx6q_logic_defconfig @@ -20,7 +20,6 @@ CONFIG_BOUNCE_BUFFER=y CONFIG_SPL_TEXT_BASE=0x00908000 CONFIG_SPL_RAW_IMAGE_SUPPORT=y CONFIG_SPL_SEPARATE_BSS=y -# CONFIG_TPL_BANNER_PRINT is not set # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_DMA_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y @@ -67,9 +66,10 @@ CONFIG_SPL_OF_TRANSLATE=y CONFIG_PCF8575_GPIO=y CONFIG_LED=y CONFIG_LED_GPIO=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_NAND=y +CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_MXS=y CONFIG_NAND_MXS_DT=y CONFIG_PHYLIB=y diff --git a/configs/imx6qdl_icore_mipi_defconfig b/configs/imx6qdl_icore_mipi_defconfig index 268c909882..5442ce7db4 100644 --- a/configs/imx6qdl_icore_mipi_defconfig +++ b/configs/imx6qdl_icore_mipi_defconfig @@ -44,7 +44,7 @@ CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore-mipi" CONFIG_OF_LIST="imx6q-icore-mipi imx6dl-icore-mipi" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_I2C_MXC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_SMSC=y CONFIG_FEC_MXC=y diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig index b15c547e37..c7544c68c8 100644 --- a/configs/imx6qdl_icore_mmc_defconfig +++ b/configs/imx6qdl_icore_mmc_defconfig @@ -54,7 +54,7 @@ CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041 CONFIG_SYS_I2C_MXC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_NAND=y CONFIG_NAND_MXS=y CONFIG_PHYLIB=y diff --git a/configs/imx6qdl_icore_nand_defconfig b/configs/imx6qdl_icore_nand_defconfig index 4ea0803ab5..fc990a8add 100644 --- a/configs/imx6qdl_icore_nand_defconfig +++ b/configs/imx6qdl_icore_nand_defconfig @@ -40,7 +40,7 @@ CONFIG_CMD_UBI=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore" CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_I2C_MXC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_NAND=y CONFIG_NAND_MXS=y CONFIG_PHYLIB=y diff --git a/configs/imx6qdl_icore_rqs_defconfig b/configs/imx6qdl_icore_rqs_defconfig index 712c79f54e..9f0cc0ffed 100644 --- a/configs/imx6qdl_icore_rqs_defconfig +++ b/configs/imx6qdl_icore_rqs_defconfig @@ -41,7 +41,7 @@ CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore-rqs" CONFIG_OF_LIST="imx6q-icore-rqs imx6dl-icore-rqs" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_I2C_MXC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y diff --git a/configs/imx6ul_geam_mmc_defconfig b/configs/imx6ul_geam_mmc_defconfig index 8a7b1ad6d5..620d979342 100644 --- a/configs/imx6ul_geam_mmc_defconfig +++ b/configs/imx6ul_geam_mmc_defconfig @@ -38,7 +38,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_I2C_MXC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_SMSC=y CONFIG_FEC_MXC=y diff --git a/configs/imx6ul_geam_nand_defconfig b/configs/imx6ul_geam_nand_defconfig index d24027cd69..94d43fdd04 100644 --- a/configs/imx6ul_geam_nand_defconfig +++ b/configs/imx6ul_geam_nand_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_UBI=y CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam" CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_I2C_MXC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_NAND=y CONFIG_NAND_MXS=y CONFIG_PHYLIB=y diff --git a/configs/imx6ul_isiot_emmc_defconfig b/configs/imx6ul_isiot_emmc_defconfig index 584d766262..f0f53bada7 100644 --- a/configs/imx6ul_isiot_emmc_defconfig +++ b/configs/imx6ul_isiot_emmc_defconfig @@ -38,7 +38,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_DEFAULT_DEVICE_TREE="imx6ul-isiot-emmc" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_I2C_MXC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_SMSC=y CONFIG_FEC_MXC=y diff --git a/configs/imx6ul_isiot_nand_defconfig b/configs/imx6ul_isiot_nand_defconfig index 80f7cb3e03..05e0498a5e 100644 --- a/configs/imx6ul_isiot_nand_defconfig +++ b/configs/imx6ul_isiot_nand_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_UBI=y CONFIG_DEFAULT_DEVICE_TREE="imx6ul-isiot-nand" CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_I2C_MXC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_NAND=y CONFIG_NAND_MXS=y CONFIG_PHYLIB=y diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index 2f86c23166..48b16a4e24 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -31,7 +31,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_DM_ETH=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX8M=y diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig index aa23b9caa3..3294931ef8 100644 --- a/configs/imx8qm_mek_defconfig +++ b/configs/imx8qm_mek_defconfig @@ -51,7 +51,7 @@ CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y CONFIG_MISC=y CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_ATHEROS=y diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig index 3740f17de2..d7974e8fad 100644 --- a/configs/imx8qxp_mek_defconfig +++ b/configs/imx8qxp_mek_defconfig @@ -56,7 +56,7 @@ CONFIG_I2C_MUX_PCA954x=y CONFIG_MISC=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_ATHEROS=y diff --git a/configs/inetspace_v2_defconfig b/configs/inetspace_v2_defconfig index daf6662abf..95dfa9c571 100644 --- a/configs/inetspace_v2_defconfig +++ b/configs/inetspace_v2_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_NETSPACE_V2=y diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 917e33d683..6e355f5247 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -29,6 +29,7 @@ CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_ASKENV=y # CONFIG_CMD_FLASH is not set diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig index 60b7c4031d..b516f9d0e5 100644 --- a/configs/j721e_evm_r5_defconfig +++ b/configs/j721e_evm_r5_defconfig @@ -32,6 +32,7 @@ CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_REMOTEPROC=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_FLASH is not set diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig index 78864f2419..260605533e 100644 --- a/configs/k2e_evm_defconfig +++ b/configs/k2e_evm_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KEYSTONE=y CONFIG_ISW_ENTRY_ADDR=0xC100000 CONFIG_SYS_TEXT_BASE=0xC000000 @@ -21,6 +22,8 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 +CONFIG_MX_CYCLIC=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_GPIO is not set # CONFIG_CMD_GPT is not set @@ -42,6 +45,7 @@ CONFIG_TI_AEMIF=y CONFIG_MISC=y # CONFIG_MMC is not set CONFIG_NAND=y +CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig index 5fabbb42d9..98e3cdeb90 100644 --- a/configs/k2e_hs_evm_defconfig +++ b/configs/k2e_hs_evm_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KEYSTONE=y CONFIG_TI_SECURE_DEVICE=y CONFIG_ISW_ENTRY_ADDR=0xC100000 @@ -14,6 +15,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_MX_CYCLIC=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_GPIO is not set # CONFIG_CMD_GPT is not set @@ -35,6 +37,7 @@ CONFIG_TI_AEMIF=y CONFIG_MISC=y # CONFIG_MMC is not set CONFIG_NAND=y +CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig index 48d7fdc0af..27804517fe 100644 --- a/configs/k2g_evm_defconfig +++ b/configs/k2g_evm_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KEYSTONE=y CONFIG_ISW_ENTRY_ADDR=0xC0A0000 CONFIG_SYS_TEXT_BASE=0xC000000 @@ -21,6 +22,8 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 +CONFIG_MX_CYCLIC=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_GPIO is not set # CONFIG_CMD_GPT is not set @@ -42,6 +45,7 @@ CONFIG_MISC=y CONFIG_DM_MMC=y CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y +CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig index 05f535b8d0..f5f3678bbe 100644 --- a/configs/k2g_hs_evm_defconfig +++ b/configs/k2g_hs_evm_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KEYSTONE=y CONFIG_TI_SECURE_DEVICE=y CONFIG_ISW_ENTRY_ADDR=0xC0A0000 @@ -14,6 +15,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_MX_CYCLIC=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_GPIO is not set # CONFIG_CMD_GPT is not set @@ -36,6 +38,7 @@ CONFIG_MISC=y CONFIG_DM_MMC=y CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y +CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig index 12358d15a9..2d5f1934d0 100644 --- a/configs/k2hk_evm_defconfig +++ b/configs/k2hk_evm_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KEYSTONE=y CONFIG_ISW_ENTRY_ADDR=0xC200000 CONFIG_SYS_TEXT_BASE=0xC000000 @@ -21,6 +22,8 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 +CONFIG_MX_CYCLIC=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_GPIO is not set # CONFIG_CMD_GPT is not set @@ -42,6 +45,7 @@ CONFIG_TI_AEMIF=y CONFIG_MISC=y # CONFIG_MMC is not set CONFIG_NAND=y +CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig index 64537cea0a..8d679208b0 100644 --- a/configs/k2hk_hs_evm_defconfig +++ b/configs/k2hk_hs_evm_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KEYSTONE=y CONFIG_TI_SECURE_DEVICE=y CONFIG_ISW_ENTRY_ADDR=0xC200000 @@ -14,6 +15,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_MX_CYCLIC=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_GPIO is not set # CONFIG_CMD_GPT is not set @@ -35,6 +37,7 @@ CONFIG_TI_AEMIF=y CONFIG_MISC=y # CONFIG_MMC is not set CONFIG_NAND=y +CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig index 1eef7f8997..b0898b0000 100644 --- a/configs/k2l_evm_defconfig +++ b/configs/k2l_evm_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KEYSTONE=y CONFIG_ISW_ENTRY_ADDR=0xC100000 CONFIG_SYS_TEXT_BASE=0xC000000 @@ -21,6 +22,8 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 +CONFIG_MX_CYCLIC=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_GPIO is not set # CONFIG_CMD_GPT is not set @@ -42,6 +45,7 @@ CONFIG_TI_AEMIF=y CONFIG_MISC=y # CONFIG_MMC is not set CONFIG_NAND=y +CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig index c412c6f51b..8b7089bbc7 100644 --- a/configs/k2l_hs_evm_defconfig +++ b/configs/k2l_hs_evm_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KEYSTONE=y CONFIG_TI_SECURE_DEVICE=y CONFIG_ISW_ENTRY_ADDR=0xC100000 @@ -13,6 +14,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y +CONFIG_MX_CYCLIC=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_GPIO is not set # CONFIG_CMD_GPT is not set @@ -34,6 +36,7 @@ CONFIG_TI_AEMIF=y CONFIG_MISC=y # CONFIG_MMC is not set CONFIG_NAND=y +CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig index 11ec2dab13..acfd91dbe7 100644 --- a/configs/khadas-edge-captain-rk3399_defconfig +++ b/configs/khadas-edge-captain-rk3399_defconfig @@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-captain.dtbi" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig index c31360af86..b71fd3a286 100644 --- a/configs/khadas-edge-rk3399_defconfig +++ b/configs/khadas-edge-rk3399_defconfig @@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig index 8c9e9fc7b9..0a789872dc 100644 --- a/configs/khadas-edge-v-rk3399_defconfig +++ b/configs/khadas-edge-v-rk3399_defconfig @@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-v.dtbi" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y diff --git a/configs/km_kirkwood_128m16_defconfig b/configs/km_kirkwood_128m16_defconfig index 0bd9a7f4a3..1ba69fc614 100644 --- a/configs/km_kirkwood_128m16_defconfig +++ b/configs/km_kirkwood_128m16_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x07d00000 CONFIG_TARGET_KM_KIRKWOOD=y diff --git a/configs/km_kirkwood_defconfig b/configs/km_kirkwood_defconfig index 08b8825196..df0c9d322c 100644 --- a/configs/km_kirkwood_defconfig +++ b/configs/km_kirkwood_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x07d00000 CONFIG_TARGET_KM_KIRKWOOD=y diff --git a/configs/km_kirkwood_pci_defconfig b/configs/km_kirkwood_pci_defconfig index b8c8445c34..c5020caab0 100644 --- a/configs/km_kirkwood_pci_defconfig +++ b/configs/km_kirkwood_pci_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x07d00000 CONFIG_TARGET_KM_KIRKWOOD=y diff --git a/configs/kmcoge5un_defconfig b/configs/kmcoge5un_defconfig index 519402ed48..c3510c473b 100644 --- a/configs/kmcoge5un_defconfig +++ b/configs/kmcoge5un_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x07d00000 CONFIG_TARGET_KM_KIRKWOOD=y diff --git a/configs/kmnusa_defconfig b/configs/kmnusa_defconfig index 1496882163..bcdf97ce1a 100644 --- a/configs/kmnusa_defconfig +++ b/configs/kmnusa_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x07d00000 CONFIG_TARGET_KM_KIRKWOOD=y diff --git a/configs/kmsugp1_defconfig b/configs/kmsugp1_defconfig index 5da967ad2a..2f123bd3f2 100644 --- a/configs/kmsugp1_defconfig +++ b/configs/kmsugp1_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x07d00000 CONFIG_TARGET_KM_KIRKWOOD=y diff --git a/configs/kmsuv31_defconfig b/configs/kmsuv31_defconfig index ced1be5c0b..2c9c9bb3fa 100644 --- a/configs/kmsuv31_defconfig +++ b/configs/kmsuv31_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x07d00000 CONFIG_TARGET_KM_KIRKWOOD=y diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig index 23d11dfe0e..86c8dba9fe 100644 --- a/configs/koelsch_defconfig +++ b/configs/koelsch_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set @@ -25,6 +26,7 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig index 87b25e6e1d..578e7010e5 100644 --- a/configs/kp_imx6q_tpc_defconfig +++ b/configs/kp_imx6q_tpc_defconfig @@ -34,7 +34,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_ATHEROS=y CONFIG_FEC_MXC=y diff --git a/configs/kzm9g_defconfig b/configs/kzm9g_defconfig index 032246a48b..94f77cf733 100644 --- a/configs/kzm9g_defconfig +++ b/configs/kzm9g_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y # CONFIG_SYS_THUMB_BUILD is not set CONFIG_ARCH_RMOBILE=y CONFIG_SYS_TEXT_BASE=0x00000000 diff --git a/configs/lager_defconfig b/configs/lager_defconfig index c0560543a7..1d10b373e0 100644 --- a/configs/lager_defconfig +++ b/configs/lager_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set @@ -25,6 +26,7 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/legoev3_defconfig b/configs/legoev3_defconfig index 78cca8eb56..0f9f62450d 100644 --- a/configs/legoev3_defconfig +++ b/configs/legoev3_defconfig @@ -14,6 +14,7 @@ CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds - press 'l' to stop...\n" CONFIG_AUTOBOOT_STOP_STR="l" CONFIG_CMD_ASKENV=y CONFIG_CRC32_VERIFY=y +CONFIG_MX_CYCLIC=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/liteboard_defconfig b/configs/liteboard_defconfig index 456f1e3fa9..03a0e88635 100644 --- a/configs/liteboard_defconfig +++ b/configs/liteboard_defconfig @@ -39,7 +39,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_DM_ETH=y CONFIG_MII=y diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig index c5c5190f9a..3170d81aaf 100644 --- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1028AQDS=y CONFIG_TFABOOT=y +CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_SECURE_BOOT=y CONFIG_SYS_FSL_SDHC_CLK_DIV=1 CONFIG_NR_DRAM_BANKS=2 @@ -8,7 +9,6 @@ CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y -# CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -31,6 +31,12 @@ CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0 +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y @@ -51,6 +57,8 @@ CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_ECAM_GENERIC=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_RTC=y +CONFIG_RTC_PCF2127=y CONFIG_SCSI=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig index 7cfcaf069a..2da7b1d94e 100644 --- a/configs/ls1028aqds_tfa_defconfig +++ b/configs/ls1028aqds_tfa_defconfig @@ -1,13 +1,13 @@ CONFIG_ARM=y CONFIG_TARGET_LS1028AQDS=y CONFIG_TFABOOT=y +CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_SYS_FSL_SDHC_CLK_DIV=1 CONFIG_NR_DRAM_BANKS=2 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y -# CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -34,6 +34,12 @@ CONFIG_DM=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0 +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y @@ -54,6 +60,8 @@ CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_ECAM_GENERIC=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_RTC=y +CONFIG_RTC_PCF2127=y CONFIG_SCSI=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig index e59ab580d5..c1e88b5465 100644 --- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1028ARDB=y CONFIG_TFABOOT=y +CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_SECURE_BOOT=y CONFIG_SYS_FSL_SDHC_CLK_DIV=1 CONFIG_NR_DRAM_BANKS=2 @@ -8,7 +9,6 @@ CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y -# CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -31,6 +31,12 @@ CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0 +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y @@ -51,6 +57,8 @@ CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_ECAM_GENERIC=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_RTC=y +CONFIG_RTC_PCF2127=y CONFIG_SCSI=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index ddb1453aa9..4d0c12f96f 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -1,13 +1,13 @@ CONFIG_ARM=y CONFIG_TARGET_LS1028ARDB=y CONFIG_TFABOOT=y +CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_SYS_FSL_SDHC_CLK_DIV=1 CONFIG_NR_DRAM_BANKS=2 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y -# CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -34,6 +34,12 @@ CONFIG_DM=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0 +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y @@ -54,6 +60,8 @@ CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_ECAM_GENERIC=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_RTC=y +CONFIG_RTC_PCF2127=y CONFIG_SCSI=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig index ff37969748..cc998775bd 100644 --- a/configs/ls1043aqds_qspi_defconfig +++ b/configs/ls1043aqds_qspi_defconfig @@ -35,6 +35,7 @@ CONFIG_FSL_CAAM=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_BAR is not set CONFIG_PHYLIB=y CONFIG_E1000=y CONFIG_FMAN_ENET=y @@ -47,6 +48,7 @@ CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig index 3f5af930a3..ecd30238af 100644 --- a/configs/ls1043aqds_sdcard_qspi_defconfig +++ b/configs/ls1043aqds_sdcard_qspi_defconfig @@ -49,6 +49,7 @@ CONFIG_FSL_CAAM=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_BAR is not set CONFIG_PHYLIB=y CONFIG_E1000=y CONFIG_FMAN_ENET=y @@ -61,6 +62,7 @@ CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig index f935087526..b49ac2cb5d 100644 --- a/configs/ls1043aqds_tfa_defconfig +++ b/configs/ls1043aqds_tfa_defconfig @@ -47,6 +47,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=1 +# CONFIG_SPI_FLASH_BAR is not set CONFIG_PHYLIB=y CONFIG_E1000=y CONFIG_FMAN_ENET=y @@ -58,6 +59,7 @@ CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig index a0ea69672d..145beea761 100644 --- a/configs/ls1088aqds_tfa_defconfig +++ b/configs/ls1088aqds_tfa_defconfig @@ -2,13 +2,13 @@ CONFIG_ARM=y CONFIG_TARGET_LS1088AQDS=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_QSPI_AHB_INIT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y -# CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -36,6 +36,12 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0 +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y @@ -53,6 +59,8 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_RTC=y +CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig index 4f22a44dd3..45df1347fa 100644 --- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1088ARDB=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_SECURE_BOOT=y CONFIG_QSPI_AHB_INIT=y CONFIG_NR_DRAM_BANKS=2 @@ -9,7 +10,6 @@ CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y -# CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -34,6 +34,12 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0 +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y @@ -47,6 +53,8 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_RTC=y +CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig index 3a992397ea..b7c40a4d6c 100644 --- a/configs/ls1088ardb_tfa_defconfig +++ b/configs/ls1088ardb_tfa_defconfig @@ -2,13 +2,13 @@ CONFIG_ARM=y CONFIG_TARGET_LS1088ARDB=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_QSPI_AHB_INIT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y -# CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -35,6 +35,12 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0 +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y @@ -48,6 +54,8 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_RTC=y +CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig index 180fdc077c..f0ebe7bc35 100644 --- a/configs/ls2088aqds_tfa_defconfig +++ b/configs/ls2088aqds_tfa_defconfig @@ -26,7 +26,6 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y CONFIG_MP=y # CONFIG_ISO_PARTITION is not set CONFIG_OF_CONTROL=y @@ -38,6 +37,12 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0 +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y @@ -53,6 +58,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_RTC=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig index e062d6bd81..0f84055993 100644 --- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig @@ -2,13 +2,13 @@ CONFIG_ARM=y CONFIG_TARGET_LS2080ARDB=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_SECURE_BOOT=y CONFIG_QSPI_AHB_INIT=y CONFIG_NR_DRAM_BANKS=3 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y -# CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -29,13 +29,18 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y CONFIG_MP=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0 +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y @@ -54,6 +59,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_RTC=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550=y diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig index 7654948c11..014acc5e91 100644 --- a/configs/ls2088ardb_tfa_defconfig +++ b/configs/ls2088ardb_tfa_defconfig @@ -2,12 +2,12 @@ CONFIG_ARM=y CONFIG_TARGET_LS2080ARDB=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_QSPI_AHB_INIT=y CONFIG_NR_DRAM_BANKS=3 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y -# CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -28,7 +28,6 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y CONFIG_MP=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi" @@ -39,6 +38,12 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0 +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y @@ -58,6 +63,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_RTC=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550=y diff --git a/configs/lschlv2_defconfig b/configs/lschlv2_defconfig index 010beaebdb..03498480f1 100644 --- a/configs/lschlv2_defconfig +++ b/configs/lschlv2_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_LSXL=y diff --git a/configs/lsxhl_defconfig b/configs/lsxhl_defconfig index 1223d7131a..a0662815e2 100644 --- a/configs/lsxhl_defconfig +++ b/configs/lsxhl_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_LSXL=y diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig index 71050958c9..3d4506bbff 100644 --- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig @@ -29,6 +29,12 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0 +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y @@ -48,6 +54,8 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_GEN4=y +CONFIG_DM_RTC=y +CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y CONFIG_DM_SERIAL=y CONFIG_SPI=y diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index caa411fad0..4e85543649 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -31,6 +31,12 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0 +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y @@ -48,6 +54,8 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_GEN4=y +CONFIG_DM_RTC=y +CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y CONFIG_DM_SERIAL=y CONFIG_SPI=y diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig index 92e7c54c31..ede4e0f75f 100644 --- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig @@ -30,6 +30,10 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0 CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y @@ -46,6 +50,8 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_GEN4=y +CONFIG_DM_RTC=y +CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y CONFIG_DM_SERIAL=y CONFIG_SPI=y diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index 2639f7683c..7bcb7921d1 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -32,6 +32,10 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0 CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y @@ -48,6 +52,8 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_GEN4=y +CONFIG_DM_RTC=y +CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y CONFIG_DM_SERIAL=y CONFIG_SPI=y diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig index 49cb37e810..6d7a3dde9f 100644 --- a/configs/m53menlo_defconfig +++ b/configs/m53menlo_defconfig @@ -64,6 +64,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC_IMX=y CONFIG_NAND=y +CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_MXC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig index f6e351f50a..27f1e09922 100644 --- a/configs/marsboard_defconfig +++ b/configs/marsboard_defconfig @@ -21,7 +21,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DM=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 diff --git a/configs/maxbcm_defconfig b/configs/maxbcm_defconfig index 581e5bf756..54f2c14aa0 100644 --- a/configs/maxbcm_defconfig +++ b/configs/maxbcm_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00800000 CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -21,6 +22,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0x40004030 CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_SF=y diff --git a/configs/mccmon6_nor_defconfig b/configs/mccmon6_nor_defconfig index cd78c5cb33..66f49c0e54 100644 --- a/configs/mccmon6_nor_defconfig +++ b/configs/mccmon6_nor_defconfig @@ -28,7 +28,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nor:32m@0x0(mccmon6-image.nor),256k@0x CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_MTD_DEVICE=y diff --git a/configs/mccmon6_sd_defconfig b/configs/mccmon6_sd_defconfig index 17947860ee..501eaf6942 100644 --- a/configs/mccmon6_sd_defconfig +++ b/configs/mccmon6_sd_defconfig @@ -29,7 +29,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nor:32m@0x0(mccmon6-image.nor),256k@0x CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_MTD_DEVICE=y diff --git a/configs/meesc_dataflash_defconfig b/configs/meesc_dataflash_defconfig index 479466286f..5d0f2471c0 100644 --- a/configs/meesc_dataflash_defconfig +++ b/configs/meesc_dataflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21F00000 CONFIG_TARGET_MEESC=y diff --git a/configs/meesc_defconfig b/configs/meesc_defconfig index 74426677d4..5312974c3b 100644 --- a/configs/meesc_defconfig +++ b/configs/meesc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21F00000 CONFIG_TARGET_MEESC=y @@ -30,6 +31,7 @@ CONFIG_DM_GPIO=y CONFIG_AT91_GPIO=y # CONFIG_MMC is not set CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/mgcoge3un_defconfig b/configs/mgcoge3un_defconfig index 6dd21bcdc1..15a6dd5b08 100644 --- a/configs/mgcoge3un_defconfig +++ b/configs/mgcoge3un_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x07d00000 CONFIG_TARGET_KM_KIRKWOOD=y diff --git a/configs/mt7623n_bpir2_defconfig b/configs/mt7623n_bpir2_defconfig index ae8209831b..f79850f849 100644 --- a/configs/mt7623n_bpir2_defconfig +++ b/configs/mt7623n_bpir2_defconfig @@ -31,7 +31,6 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y CONFIG_SYSCON=y -# CONFIG_BLOCK_CACHE is not set CONFIG_CLK=y CONFIG_DM_MMC=y # CONFIG_MMC_QUIRKS is not set diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig index 900c98de35..8aa864d834 100644 --- a/configs/mvebu_db-88f3720_defconfig +++ b/configs/mvebu_db-88f3720_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 diff --git a/configs/mvebu_db_armada8k_defconfig b/configs/mvebu_db_armada8k_defconfig index 875db3b40b..42d10ed5df 100644 --- a/configs/mvebu_db_armada8k_defconfig +++ b/configs/mvebu_db_armada8k_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig index 2d834e5170..69b4981580 100644 --- a/configs/mvebu_espressobin-88f3720_defconfig +++ b/configs/mvebu_espressobin-88f3720_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 diff --git a/configs/mvebu_mcbin-88f8040_defconfig b/configs/mvebu_mcbin-88f8040_defconfig index 6b05522870..b411810d39 100644 --- a/configs/mvebu_mcbin-88f8040_defconfig +++ b/configs/mvebu_mcbin-88f8040_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 diff --git a/configs/mx23_olinuxino_defconfig b/configs/mx23_olinuxino_defconfig index 3e4b7ab1c3..fd045ad162 100644 --- a/configs/mx23_olinuxino_defconfig +++ b/configs/mx23_olinuxino_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_MXS_GPIO=y CONFIG_LED_STATUS=y CONFIG_LED_STATUS_GPIO=y CONFIG_LED_STATUS0=y diff --git a/configs/mx23evk_defconfig b/configs/mx23evk_defconfig index 773aff4bdc..bb04623a8f 100644 --- a/configs/mx23evk_defconfig +++ b/configs/mx23evk_defconfig @@ -28,6 +28,7 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_ENV_IS_IN_MMC=y # CONFIG_NET is not set +CONFIG_MXS_GPIO=y CONFIG_MMC_MXS=y CONFIG_CONS_INDEX=0 CONFIG_USB=y diff --git a/configs/mx28evk_auart_console_defconfig b/configs/mx28evk_auart_console_defconfig index 27c152571a..d7909e2fa9 100644 --- a/configs/mx28evk_auart_console_defconfig +++ b/configs/mx28evk_auart_console_defconfig @@ -38,6 +38,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),512k(redundant-environment),4m(kernel),512k(fdt),8m(ramdisk),-(filesystem)" CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_MXS_GPIO=y CONFIG_MMC_MXS=y CONFIG_NAND=y CONFIG_NAND_MXS=y diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig index 4cee901d83..7f000c8c38 100644 --- a/configs/mx28evk_defconfig +++ b/configs/mx28evk_defconfig @@ -38,6 +38,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),512k(redundant-environment),4m(kernel),512k(fdt),8m(ramdisk),-(filesystem)" CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_MXS_GPIO=y CONFIG_MMC_MXS=y CONFIG_NAND=y CONFIG_NAND_MXS=y diff --git a/configs/mx28evk_nand_defconfig b/configs/mx28evk_nand_defconfig index 3875da733a..248d8b1fc9 100644 --- a/configs/mx28evk_nand_defconfig +++ b/configs/mx28evk_nand_defconfig @@ -37,6 +37,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),512k(redundant-environment),4m(kernel),512k(fdt),8m(ramdisk),-(filesystem)" CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_MXS_GPIO=y CONFIG_MMC_MXS=y CONFIG_NAND=y CONFIG_NAND_MXS=y diff --git a/configs/mx28evk_spi_defconfig b/configs/mx28evk_spi_defconfig index 37477b35f1..3097e090a0 100644 --- a/configs/mx28evk_spi_defconfig +++ b/configs/mx28evk_spi_defconfig @@ -36,6 +36,7 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),512k(redundant-environment),4m(kernel),512k(fdt),8m(ramdisk),-(filesystem)" CONFIG_CMD_UBI=y +CONFIG_MXS_GPIO=y CONFIG_MMC_MXS=y CONFIG_NAND=y CONFIG_NAND_MXS=y diff --git a/configs/mx53ard_defconfig b/configs/mx53ard_defconfig index cf85c4248e..429a78ffa5 100644 --- a/configs/mx53ard_defconfig +++ b/configs/mx53ard_defconfig @@ -17,6 +17,7 @@ CONFIG_CMD_FAT=y CONFIG_ENV_IS_IN_MMC=y CONFIG_FSL_ESDHC_IMX=y CONFIG_NAND=y +CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_MXC=y CONFIG_MII=y CONFIG_SMC911X=y diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig index 9fc443c386..3d73734609 100644 --- a/configs/mx6cuboxi_defconfig +++ b/configs/mx6cuboxi_defconfig @@ -35,7 +35,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y CONFIG_DWC_AHSATA=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_MII=y CONFIG_DM_THERMAL=y diff --git a/configs/mx6dlarm2_defconfig b/configs/mx6dlarm2_defconfig index 866e0b5baa..4675c9d33c 100644 --- a/configs/mx6dlarm2_defconfig +++ b/configs/mx6dlarm2_defconfig @@ -26,7 +26,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_MII=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6dlarm2_lpddr2_defconfig b/configs/mx6dlarm2_lpddr2_defconfig index 98ae70e026..cdca47e06d 100644 --- a/configs/mx6dlarm2_lpddr2_defconfig +++ b/configs/mx6dlarm2_lpddr2_defconfig @@ -26,7 +26,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_MII=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6memcal_defconfig b/configs/mx6memcal_defconfig index ebb48c3aa3..d20e3dbbe1 100644 --- a/configs/mx6memcal_defconfig +++ b/configs/mx6memcal_defconfig @@ -36,6 +36,7 @@ CONFIG_CMD_MEMTEST=y CONFIG_CMD_CACHE=y # CONFIG_NET is not set # CONFIG_MMC is not set +CONFIG_FSL_USDHC=y CONFIG_USB=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" diff --git a/configs/mx6qarm2_defconfig b/configs/mx6qarm2_defconfig index 8056e53da1..5f2b40f4a1 100644 --- a/configs/mx6qarm2_defconfig +++ b/configs/mx6qarm2_defconfig @@ -26,7 +26,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_MII=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6qarm2_lpddr2_defconfig b/configs/mx6qarm2_lpddr2_defconfig index 27c215f6f7..3ca42d7344 100644 --- a/configs/mx6qarm2_lpddr2_defconfig +++ b/configs/mx6qarm2_lpddr2_defconfig @@ -26,7 +26,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_MII=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig index 65e9c4f117..379407ab43 100644 --- a/configs/mx6qsabrelite_defconfig +++ b/configs/mx6qsabrelite_defconfig @@ -35,7 +35,7 @@ CONFIG_DM=y CONFIG_DWC_AHSATA=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig index 02f972af0d..516aac1f14 100644 --- a/configs/mx6sabreauto_defconfig +++ b/configs/mx6sabreauto_defconfig @@ -62,7 +62,7 @@ CONFIG_DFU_MMC=y CONFIG_DFU_SF=y CONFIG_DM_GPIO=y CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_NAND=y CONFIG_NAND_MXS=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index 9400805831..2c88fe67c2 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -74,7 +74,7 @@ CONFIG_FASTBOOT_FLASH_MMC_DEV=2 CONFIG_DM_GPIO=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig index 643cad4a65..e614ef29ea 100644 --- a/configs/mx6slevk_defconfig +++ b/configs/mx6slevk_defconfig @@ -34,7 +34,7 @@ CONFIG_DM=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig index 3dada9961a..6ade0ef142 100644 --- a/configs/mx6slevk_spinor_defconfig +++ b/configs/mx6slevk_spinor_defconfig @@ -34,7 +34,7 @@ CONFIG_DM=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig index 63a7a74b0a..9b3f2252de 100644 --- a/configs/mx6slevk_spl_defconfig +++ b/configs/mx6slevk_spl_defconfig @@ -43,7 +43,7 @@ CONFIG_DM=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 diff --git a/configs/mx6sllevk_defconfig b/configs/mx6sllevk_defconfig index 81f5fa5e76..7efe321b88 100644 --- a/configs/mx6sllevk_defconfig +++ b/configs/mx6sllevk_defconfig @@ -30,7 +30,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_PMIC=y diff --git a/configs/mx6sllevk_plugin_defconfig b/configs/mx6sllevk_plugin_defconfig index 565dc890a7..4e6f1ed554 100644 --- a/configs/mx6sllevk_plugin_defconfig +++ b/configs/mx6sllevk_plugin_defconfig @@ -31,7 +31,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_PMIC=y diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig index 11c2a82779..fa9853def6 100644 --- a/configs/mx6sxsabreauto_defconfig +++ b/configs/mx6sxsabreauto_defconfig @@ -34,7 +34,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_NAND=y CONFIG_NAND_MXS=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig index 135961a0c4..c5fabf9950 100644 --- a/configs/mx6sxsabresd_defconfig +++ b/configs/mx6sxsabresd_defconfig @@ -38,7 +38,7 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=1 diff --git a/configs/mx6sxsabresd_spl_defconfig b/configs/mx6sxsabresd_spl_defconfig index 21c936648c..82093af750 100644 --- a/configs/mx6sxsabresd_spl_defconfig +++ b/configs/mx6sxsabresd_spl_defconfig @@ -47,7 +47,7 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_MII=y CONFIG_PCI=y diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig index 1d777b5fb2..c848c530a8 100644 --- a/configs/mx6ul_14x14_evk_defconfig +++ b/configs/mx6ul_14x14_evk_defconfig @@ -44,7 +44,7 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig index 1014bd8a02..274fec0e58 100644 --- a/configs/mx6ul_9x9_evk_defconfig +++ b/configs/mx6ul_9x9_evk_defconfig @@ -44,7 +44,7 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig index f4681a630c..2528ba8061 100644 --- a/configs/mx6ull_14x14_evk_defconfig +++ b/configs/mx6ull_14x14_evk_defconfig @@ -30,7 +30,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_74X164=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig index 6fb30ce4f1..f71a495183 100644 --- a/configs/mx6ull_14x14_evk_plugin_defconfig +++ b/configs/mx6ull_14x14_evk_plugin_defconfig @@ -31,7 +31,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_74X164=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig index 45901f041f..1107507b51 100644 --- a/configs/mx7dsabresd_defconfig +++ b/configs/mx7dsabresd_defconfig @@ -48,7 +48,7 @@ CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_EON=y CONFIG_PHYLIB=y diff --git a/configs/mx7dsabresd_qspi_defconfig b/configs/mx7dsabresd_qspi_defconfig index 2f566984d5..b8ced1994a 100644 --- a/configs/mx7dsabresd_qspi_defconfig +++ b/configs/mx7dsabresd_qspi_defconfig @@ -48,7 +48,7 @@ CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 diff --git a/configs/mx7ulp_evk_defconfig b/configs/mx7ulp_evk_defconfig index d4eba65ac0..df854436a0 100644 --- a/configs/mx7ulp_evk_defconfig +++ b/configs/mx7ulp_evk_defconfig @@ -22,7 +22,7 @@ CONFIG_IMX_RGPIO2P=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7ULP=y CONFIG_DM_REGULATOR=y diff --git a/configs/mx7ulp_evk_plugin_defconfig b/configs/mx7ulp_evk_plugin_defconfig index ae8d4b4d39..b2451adce7 100644 --- a/configs/mx7ulp_evk_plugin_defconfig +++ b/configs/mx7ulp_evk_plugin_defconfig @@ -21,7 +21,7 @@ CONFIG_IMX_RGPIO2P=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7ULP=y CONFIG_DM_REGULATOR=y diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig index 8afa5e1986..1d4c8f8a02 100644 --- a/configs/nanopc-t4-rk3399_defconfig +++ b/configs/nanopc-t4-rk3399_defconfig @@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopc-t4.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig index e708a4fd8c..7375b758a2 100644 --- a/configs/nanopi-m4-rk3399_defconfig +++ b/configs/nanopi-m4-rk3399_defconfig @@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig index 62cdddde68..874ee5efb6 100644 --- a/configs/nanopi-neo4-rk3399_defconfig +++ b/configs/nanopi-neo4-rk3399_defconfig @@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-neo4.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig index 4672e78c3f..9b5d594c81 100644 --- a/configs/nas220_defconfig +++ b/configs/nas220_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_NAS220=y diff --git a/configs/net2big_v2_defconfig b/configs/net2big_v2_defconfig index e5dd072347..2a309f5441 100644 --- a/configs/net2big_v2_defconfig +++ b/configs/net2big_v2_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_NET2BIG_V2=y diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig index 3d2a95a0e7..ee58114b94 100644 --- a/configs/netspace_lite_v2_defconfig +++ b/configs/netspace_lite_v2_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_NETSPACE_V2=y diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig index 5fc9e94a4d..2a95a55752 100644 --- a/configs/netspace_max_v2_defconfig +++ b/configs/netspace_max_v2_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_NETSPACE_V2=y diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig index c6460dd324..6933a9ba86 100644 --- a/configs/netspace_mini_v2_defconfig +++ b/configs/netspace_mini_v2_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_NETSPACE_V2=y diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig index 6427c79215..fc806e445e 100644 --- a/configs/netspace_v2_defconfig +++ b/configs/netspace_v2_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_NETSPACE_V2=y diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig index c50e79aba8..11bee9b550 100644 --- a/configs/nitrogen6dl2g_defconfig +++ b/configs/nitrogen6dl2g_defconfig @@ -37,7 +37,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig index 85a8a8d708..141289f174 100644 --- a/configs/nitrogen6dl_defconfig +++ b/configs/nitrogen6dl_defconfig @@ -37,7 +37,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig index 5a2df361fd..841418350b 100644 --- a/configs/nitrogen6q2g_defconfig +++ b/configs/nitrogen6q2g_defconfig @@ -39,7 +39,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DWC_AHSATA=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig index fdc0f2b03f..e0af34c8a7 100644 --- a/configs/nitrogen6q_defconfig +++ b/configs/nitrogen6q_defconfig @@ -39,7 +39,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DWC_AHSATA=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig index 230b12f7e6..53eb96a986 100644 --- a/configs/nitrogen6s1g_defconfig +++ b/configs/nitrogen6s1g_defconfig @@ -37,7 +37,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig index 72e590a4fe..e60c237857 100644 --- a/configs/nitrogen6s_defconfig +++ b/configs/nitrogen6s_defconfig @@ -37,7 +37,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x12000000 -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 diff --git a/configs/novena_defconfig b/configs/novena_defconfig index 93374282a6..c928b258b1 100644 --- a/configs/novena_defconfig +++ b/configs/novena_defconfig @@ -49,7 +49,7 @@ CONFIG_DM=y CONFIG_DWC_AHSATA=y CONFIG_DM_GPIO=y CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig index d74149e3c5..064ea0523d 100644 --- a/configs/nsa310s_defconfig +++ b/configs/nsa310s_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_NSA310S=y diff --git a/configs/oceanic_5205_5inmfd_defconfig b/configs/oceanic_5205_5inmfd_defconfig index 23a181335b..854ada3ee2 100644 --- a/configs/oceanic_5205_5inmfd_defconfig +++ b/configs/oceanic_5205_5inmfd_defconfig @@ -11,6 +11,7 @@ CONFIG_MMC0_CD_PIN="" CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_USE_PREBOOT=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig index b8ebd56bf9..8493312837 100644 --- a/configs/odroid-xu3_defconfig +++ b/configs/odroid-xu3_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_EXYNOS=y CONFIG_SYS_TEXT_BASE=0x43E00000 CONFIG_ARCH_EXYNOS5=y diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig index cdf01473f4..95d77b7ebc 100644 --- a/configs/odroid_defconfig +++ b/configs/odroid_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_EXYNOS=y CONFIG_SYS_TEXT_BASE=0x43e00000 CONFIG_ARCH_EXYNOS4=y diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig index 4a2bbdc339..44bfd5e0d4 100644 --- a/configs/omap3_beagle_defconfig +++ b/configs/omap3_beagle_defconfig @@ -8,7 +8,6 @@ CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 CONFIG_NR_DRAM_BANKS=2 CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_TPL_SYS_MALLOC_F_LEN=0x400 CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd" CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="usb start" diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig index 8b1719280b..9763b6aca1 100644 --- a/configs/omap3_evm_defconfig +++ b/configs/omap3_evm_defconfig @@ -8,7 +8,6 @@ CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 CONFIG_NR_DRAM_BANKS=2 CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_TPL_SYS_MALLOC_F_LEN=0x400 CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DEFAULT_FDT_FILE="omap3-evm.dtb" diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig index 76c7ed6aaa..d2342c37cf 100644 --- a/configs/omapl138_lcdk_defconfig +++ b/configs/omapl138_lcdk_defconfig @@ -24,6 +24,7 @@ CONFIG_SPL_NAND_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CRC32_VERIFY=y # CONFIG_CMD_EEPROM is not set +CONFIG_MX_CYCLIC=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_GPIO is not set CONFIG_CMD_NAND=y @@ -44,6 +45,7 @@ CONFIG_SYS_I2C_DAVINCI=y CONFIG_DM_MMC=y CONFIG_MTD=y CONFIG_NAND=y +CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y @@ -57,7 +59,6 @@ CONFIG_PHY_DA8XX_USB=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y -CONFIG_USE_TINY_PRINTF=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig index 2b9fd16182..43dc6c5c1a 100644 --- a/configs/openrd_base_defconfig +++ b/configs/openrd_base_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_SYS_THUMB_BUILD=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x600000 diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig index 4e9a99f7ba..71c4475466 100644 --- a/configs/openrd_client_defconfig +++ b/configs/openrd_client_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_SYS_THUMB_BUILD=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x600000 diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig index aeae24b1f5..bdfa4ac862 100644 --- a/configs/openrd_ultimate_defconfig +++ b/configs/openrd_ultimate_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_SYS_THUMB_BUILD=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x600000 diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig index 14e15b03b2..1b68b8e12f 100644 --- a/configs/opos6uldev_defconfig +++ b/configs/opos6uldev_defconfig @@ -12,7 +12,6 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y # CONFIG_CMD_BMODE is not set -CONFIG_TPL_SYS_MALLOC_F_LEN=0x400 CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttymxc0,115200" @@ -70,7 +69,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_PWRSEQ=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index b1afeaeef8..7b02c59f08 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig index 84801a6586..ba0f2d562b 100644 --- a/configs/orangepi_pc2_defconfig +++ b/configs/orangepi_pc2_defconfig @@ -10,6 +10,7 @@ CONFIG_MACPWR="PD6" CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_USE_PREBOOT=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/orangepi_r1_defconfig b/configs/orangepi_r1_defconfig index b2aa3eef3f..e0a530d4b8 100644 --- a/configs/orangepi_r1_defconfig +++ b/configs/orangepi_r1_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_USE_PREBOOT=y CONFIG_CONSOLE_MUX=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000 # CONFIG_CMD_FLASH is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-r1" CONFIG_SUN8I_EMAC=y diff --git a/configs/orangepi_win_defconfig b/configs/orangepi_win_defconfig index 8a9cc40095..28395031b7 100644 --- a/configs/orangepi_win_defconfig +++ b/configs/orangepi_win_defconfig @@ -7,6 +7,7 @@ CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_USE_PREBOOT=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/orangepi_zero_defconfig b/configs/orangepi_zero_defconfig index a7c72f7c80..f8dda05c08 100644 --- a/configs/orangepi_zero_defconfig +++ b/configs/orangepi_zero_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_USE_PREBOOT=y CONFIG_CONSOLE_MUX=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000 # CONFIG_CMD_FLASH is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-zero" CONFIG_SUN8I_EMAC=y diff --git a/configs/origen_defconfig b/configs/origen_defconfig index e7d2f455f8..d9e9931e91 100644 --- a/configs/origen_defconfig +++ b/configs/origen_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_EXYNOS=y CONFIG_SYS_TEXT_BASE=0x43E00000 CONFIG_ARCH_EXYNOS4=y diff --git a/configs/ot1200_defconfig b/configs/ot1200_defconfig index b33b0c4028..0fbfc61754 100644 --- a/configs/ot1200_defconfig +++ b/configs/ot1200_defconfig @@ -32,7 +32,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DM=y CONFIG_DWC_AHSATA=y CONFIG_CMD_PCA953X=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=2 CONFIG_SF_DEFAULT_MODE=0 diff --git a/configs/ot1200_spl_defconfig b/configs/ot1200_spl_defconfig index 82ee6d0fc6..35bbbfd314 100644 --- a/configs/ot1200_spl_defconfig +++ b/configs/ot1200_spl_defconfig @@ -20,6 +20,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_TEXT_BASE=0x00908000 CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y @@ -42,7 +43,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DM=y CONFIG_DWC_AHSATA=y CONFIG_CMD_PCA953X=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=2 CONFIG_SF_DEFAULT_MODE=0 diff --git a/configs/pcm051_rev1_defconfig b/configs/pcm051_rev1_defconfig index 718c33fd82..17433768f7 100644 --- a/configs/pcm051_rev1_defconfig +++ b/configs/pcm051_rev1_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig index 05ebe66251..d85e3fc8de 100644 --- a/configs/pcm051_rev3_defconfig +++ b/configs/pcm051_rev3_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y diff --git a/configs/pcm058_defconfig b/configs/pcm058_defconfig index f7e5faa27e..3a2b35f461 100644 --- a/configs/pcm058_defconfig +++ b/configs/pcm058_defconfig @@ -26,6 +26,7 @@ CONFIG_SPL_DMA_SUPPORT=y CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y # CONFIG_CMD_FLASH is not set @@ -43,9 +44,10 @@ CONFIG_CMD_UBI=y # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DM=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_NAND=y +CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_MXS=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig index c1904f102b..a4848d5c7b 100644 --- a/configs/peach-pi_defconfig +++ b/configs/peach-pi_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_EXYNOS=y CONFIG_SYS_TEXT_BASE=0x23E00000 CONFIG_ARCH_EXYNOS5=y diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig index da4155b286..e3bca5f61a 100644 --- a/configs/peach-pit_defconfig +++ b/configs/peach-pit_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_EXYNOS=y CONFIG_SYS_TEXT_BASE=0x23E00000 CONFIG_ARCH_EXYNOS5=y diff --git a/configs/pengwyn_defconfig b/configs/pengwyn_defconfig index c4539e90f8..bd7d0a6d8b 100644 --- a/configs/pengwyn_defconfig +++ b/configs/pengwyn_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y diff --git a/configs/pepper_defconfig b/configs/pepper_defconfig index a1dbf5f2f3..85349f4044 100644 --- a/configs/pepper_defconfig +++ b/configs/pepper_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y diff --git a/configs/pfla02_defconfig b/configs/pfla02_defconfig index f710d0dece..a45322dbbb 100644 --- a/configs/pfla02_defconfig +++ b/configs/pfla02_defconfig @@ -26,6 +26,7 @@ CONFIG_SPL_DMA_SUPPORT=y CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y # CONFIG_CMD_FLASH is not set @@ -42,7 +43,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:-(nand);spi2.0:1024k(bootloader),64k CONFIG_CMD_UBI=y # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_DM=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_NAND=y CONFIG_NAND_MXS=y diff --git a/configs/phycore-am335x-r2-wega_defconfig b/configs/phycore-am335x-r2-wega_defconfig index 608544d469..43acb55c41 100644 --- a/configs/phycore-am335x-r2-wega_defconfig +++ b/configs/phycore-am335x-r2-wega_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y diff --git a/configs/phycore_pcl063_defconfig b/configs/phycore_pcl063_defconfig index cf43b43924..91fdd5c53b 100644 --- a/configs/phycore_pcl063_defconfig +++ b/configs/phycore_pcl063_defconfig @@ -35,7 +35,7 @@ CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="imx6ul-phycore-segin" CONFIG_DM_I2C_GPIO=y CONFIG_SYS_I2C_MXC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_NAND=y CONFIG_NAND_MXS=y diff --git a/configs/phycore_pcl063_ull_defconfig b/configs/phycore_pcl063_ull_defconfig index ff0cd6c3aa..4b9bb36984 100644 --- a/configs/phycore_pcl063_ull_defconfig +++ b/configs/phycore_pcl063_ull_defconfig @@ -30,7 +30,7 @@ CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="imx6ull-phycore-segin" CONFIG_DM_I2C_GPIO=y CONFIG_SYS_I2C_MXC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_FEC_MXC=y diff --git a/configs/pico-hobbit-imx6ul_defconfig b/configs/pico-hobbit-imx6ul_defconfig index 55f25d5c24..7395598599 100644 --- a/configs/pico-hobbit-imx6ul_defconfig +++ b/configs/pico-hobbit-imx6ul_defconfig @@ -46,7 +46,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig index 71350fb87e..3869eb70cc 100644 --- a/configs/pico-hobbit-imx7d_defconfig +++ b/configs/pico-hobbit-imx7d_defconfig @@ -52,7 +52,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_DM_GPIO=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_MII=y CONFIG_PINCTRL=y diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig index 03452635e9..ad29af1b71 100644 --- a/configs/pico-imx6ul_defconfig +++ b/configs/pico-imx6ul_defconfig @@ -48,7 +48,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig index 86f4280de7..a2cddfcf4f 100644 --- a/configs/pico-imx7d_bl33_defconfig +++ b/configs/pico-imx7d_bl33_defconfig @@ -43,7 +43,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DFU_MMC=y CONFIG_DM_GPIO=y CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_MII=y CONFIG_PINCTRL=y diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index 43c5d9e002..3d45872a84 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -52,7 +52,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_DM_GPIO=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_MII=y CONFIG_PINCTRL=y diff --git a/configs/pico-pi-imx6ul_defconfig b/configs/pico-pi-imx6ul_defconfig index 2e23c7b491..1a8a4541c6 100644 --- a/configs/pico-pi-imx6ul_defconfig +++ b/configs/pico-pi-imx6ul_defconfig @@ -46,7 +46,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig index 956bb35c9b..b864b537c3 100644 --- a/configs/pico-pi-imx7d_defconfig +++ b/configs/pico-pi-imx7d_defconfig @@ -52,7 +52,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_DM_GPIO=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_MII=y CONFIG_PINCTRL=y diff --git a/configs/pine64-lts_defconfig b/configs/pine64-lts_defconfig index 35c05f7f28..283c1dcdf3 100644 --- a/configs/pine64-lts_defconfig +++ b/configs/pine64-lts_defconfig @@ -11,6 +11,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_USE_PREBOOT=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/platinum_picon_defconfig b/configs/platinum_picon_defconfig index 4cc4954e84..886ddacba2 100644 --- a/configs/platinum_picon_defconfig +++ b/configs/platinum_picon_defconfig @@ -48,7 +48,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:14M(spl),2M(uboot),512k(env1),512k(env2),495M(ubi0),14M(res0),2M(res1),512k(res2),512k(res3),-(ubi1)" CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_NAND=y CONFIG_NAND_MXS=y CONFIG_PHYLIB=y diff --git a/configs/platinum_titanium_defconfig b/configs/platinum_titanium_defconfig index 1410bf8c8d..2367a17dd1 100644 --- a/configs/platinum_titanium_defconfig +++ b/configs/platinum_titanium_defconfig @@ -48,7 +48,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:14M(spl),2M(uboot),512k(env1),512k(env2),-(ubi)" CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_NAND=y CONFIG_NAND_MXS=y CONFIG_PHYLIB=y diff --git a/configs/pm9261_defconfig b/configs/pm9261_defconfig index cd4326d417..d087699f13 100644 --- a/configs/pm9261_defconfig +++ b/configs/pm9261_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0 CONFIG_TARGET_PM9261=y @@ -43,6 +44,7 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI=y CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/pm9263_defconfig b/configs/pm9263_defconfig index 1e8a520061..76476e38da 100644 --- a/configs/pm9263_defconfig +++ b/configs/pm9263_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0 CONFIG_TARGET_PM9263=y @@ -43,6 +44,7 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI=y CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/pm9g45_defconfig b/configs/pm9g45_defconfig index ecfa417a1a..b5304b963c 100644 --- a/configs/pm9g45_defconfig +++ b/configs/pm9g45_defconfig @@ -40,6 +40,7 @@ CONFIG_DM_GPIO=y CONFIG_AT91_GPIO=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_ETH=y CONFIG_MACB=y diff --git a/configs/pogo_e02_defconfig b/configs/pogo_e02_defconfig index 7207eb41bc..08c52ffdf1 100644 --- a/configs/pogo_e02_defconfig +++ b/configs/pogo_e02_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_POGO_E02=y diff --git a/configs/porter_defconfig b/configs/porter_defconfig index c42754b284..8c802b0d19 100644 --- a/configs/porter_defconfig +++ b/configs/porter_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set @@ -25,6 +26,7 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 5d2a28a72d..faf95c5505 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -25,6 +25,7 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig index a34620b6f7..201b9c9357 100644 --- a/configs/pxm2_defconfig +++ b/configs/pxm2_defconfig @@ -27,6 +27,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig new file mode 100644 index 0000000000..78e755b36a --- /dev/null +++ b/configs/qemu-riscv32_spl_defconfig @@ -0,0 +1,11 @@ +CONFIG_RISCV=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL=y +CONFIG_TARGET_QEMU_VIRT=y +CONFIG_RISCV_SMODE=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_CMD_MII is not set +CONFIG_OF_PRIOR_STAGE=y diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig new file mode 100644 index 0000000000..a3f5e29d58 --- /dev/null +++ b/configs/qemu-riscv64_spl_defconfig @@ -0,0 +1,12 @@ +CONFIG_RISCV=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL=y +CONFIG_TARGET_QEMU_VIRT=y +CONFIG_ARCH_RV64I=y +CONFIG_RISCV_SMODE=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_CMD_MII is not set +CONFIG_OF_PRIOR_STAGE=y diff --git a/configs/r8a7795_salvator-x_defconfig b/configs/r8a7795_salvator-x_defconfig index dfe993a125..a33338a69f 100644 --- a/configs/r8a7795_salvator-x_defconfig +++ b/configs/r8a7795_salvator-x_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_RMOBILE=y CONFIG_SYS_TEXT_BASE=0x50000000 CONFIG_RCAR_GEN3=y diff --git a/configs/r8a7795_ulcb_defconfig b/configs/r8a7795_ulcb_defconfig index f85d37c782..5fa760c057 100644 --- a/configs/r8a7795_ulcb_defconfig +++ b/configs/r8a7795_ulcb_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_RMOBILE=y CONFIG_SYS_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 diff --git a/configs/r8a77965_salvator-x_defconfig b/configs/r8a77965_salvator-x_defconfig index dc2d49547c..14a10f0865 100644 --- a/configs/r8a77965_salvator-x_defconfig +++ b/configs/r8a77965_salvator-x_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_RMOBILE=y CONFIG_SYS_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 diff --git a/configs/r8a77965_ulcb_defconfig b/configs/r8a77965_ulcb_defconfig index d8d915b239..d9b83c5abd 100644 --- a/configs/r8a77965_ulcb_defconfig +++ b/configs/r8a77965_ulcb_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_RMOBILE=y CONFIG_SYS_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 diff --git a/configs/r8a7796_salvator-x_defconfig b/configs/r8a7796_salvator-x_defconfig index c6f713a8ba..d909aeb2b9 100644 --- a/configs/r8a7796_salvator-x_defconfig +++ b/configs/r8a7796_salvator-x_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_RMOBILE=y CONFIG_SYS_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 diff --git a/configs/r8a7796_ulcb_defconfig b/configs/r8a7796_ulcb_defconfig index 5c11d5c44a..54495394ef 100644 --- a/configs/r8a7796_ulcb_defconfig +++ b/configs/r8a7796_ulcb_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_RMOBILE=y CONFIG_SYS_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 diff --git a/configs/r8a77970_eagle_defconfig b/configs/r8a77970_eagle_defconfig index d9e23426b3..6a5de19b22 100644 --- a/configs/r8a77970_eagle_defconfig +++ b/configs/r8a77970_eagle_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_RMOBILE=y CONFIG_SYS_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 diff --git a/configs/r8a77980_condor_defconfig b/configs/r8a77980_condor_defconfig index a403a67a45..f3c7948328 100644 --- a/configs/r8a77980_condor_defconfig +++ b/configs/r8a77980_condor_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_RMOBILE=y CONFIG_SYS_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig index edc7478784..7fd513483c 100644 --- a/configs/r8a77990_ebisu_defconfig +++ b/configs/r8a77990_ebisu_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_RMOBILE=y CONFIG_SYS_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 diff --git a/configs/r8a77995_draak_defconfig b/configs/r8a77995_draak_defconfig index 39daf98315..8e54013560 100644 --- a/configs/r8a77995_draak_defconfig +++ b/configs/r8a77995_draak_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_RMOBILE=y CONFIG_SYS_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig index fa1d0daa59..452e761412 100644 --- a/configs/rastaban_defconfig +++ b/configs/rastaban_defconfig @@ -25,6 +25,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y # CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig index 0b6304eb4d..8938b39c7f 100644 --- a/configs/riotboard_defconfig +++ b/configs/riotboard_defconfig @@ -22,7 +22,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 diff --git a/configs/riotboard_spl_defconfig b/configs/riotboard_spl_defconfig index 427bd9dae3..cf3647a8f1 100644 --- a/configs/riotboard_spl_defconfig +++ b/configs/riotboard_spl_defconfig @@ -32,7 +32,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 diff --git a/configs/roc-rk3399-pc_defconfig b/configs/roc-rk3399-pc_defconfig index 09e9b8a756..28b18333d7 100644 --- a/configs/roc-rk3399-pc_defconfig +++ b/configs/roc-rk3399-pc_defconfig @@ -1,21 +1,20 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 -CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y @@ -26,9 +25,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-roc-pc" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_TPL=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_RAM_RK3399_LPDDR4=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y @@ -42,6 +39,7 @@ CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM_RK3399_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y @@ -56,6 +54,5 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_USE_TINY_PRINTF=y CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index d9d576c46f..554945dd19 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -9,8 +9,10 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4.dtb" +CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index e8958590f4..3ab0af1158 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -21,6 +21,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock64.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_TPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 7413e4bf4c..abcc53fc8e 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -12,6 +12,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff8c2000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SYS_PROMPT="rock960 => " diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 5bc6d5d9c6..40ebad5abb 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig index 3d56b4ac7c..fe5a7763a6 100644 --- a/configs/rpi_0_w_defconfig +++ b/configs/rpi_0_w_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_BCM283X=y CONFIG_SYS_TEXT_BASE=0x00008000 CONFIG_TARGET_RPI_0_W=y diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig index 3cb2bb6713..bf331c0ad0 100644 --- a/configs/rpi_2_defconfig +++ b/configs/rpi_2_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_BCM283X=y CONFIG_SYS_TEXT_BASE=0x00008000 CONFIG_TARGET_RPI_2=y diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig index 9d9d12074e..c2417a0ec9 100644 --- a/configs/rpi_3_32b_defconfig +++ b/configs/rpi_3_32b_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_BCM283X=y CONFIG_SYS_TEXT_BASE=0x00008000 CONFIG_TARGET_RPI_3_32B=y diff --git a/configs/rpi_3_b_plus_defconfig b/configs/rpi_3_b_plus_defconfig index 7655fe7060..a7904fff06 100644 --- a/configs/rpi_3_b_plus_defconfig +++ b/configs/rpi_3_b_plus_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_BCM283X=y CONFIG_SYS_TEXT_BASE=0x00080000 CONFIG_TARGET_RPI_3=y diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig index af8718a1ee..4fa682539c 100644 --- a/configs/rpi_3_defconfig +++ b/configs/rpi_3_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_BCM283X=y CONFIG_SYS_TEXT_BASE=0x00080000 CONFIG_TARGET_RPI_3=y diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig index 55d70eb68a..2c04b3334e 100644 --- a/configs/rpi_defconfig +++ b/configs/rpi_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_BCM283X=y CONFIG_SYS_TEXT_BASE=0x00008000 CONFIG_TARGET_RPI=y diff --git a/configs/rut_defconfig b/configs/rut_defconfig index cc49c2e7dc..ec31d52377 100644 --- a/configs/rut_defconfig +++ b/configs/rut_defconfig @@ -28,6 +28,7 @@ CONFIG_ARCH_EARLY_INIT_R=y CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y diff --git a/configs/s32v234evb_defconfig b/configs/s32v234evb_defconfig index 9eaa894300..7ccb9f132c 100644 --- a/configs/s32v234evb_defconfig +++ b/configs/s32v234evb_defconfig @@ -11,7 +11,7 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_DM_SERIAL=y CONFIG_FSL_LINFLEXUART=y CONFIG_OF_LIBFDT=y diff --git a/configs/s5p_goni_defconfig b/configs/s5p_goni_defconfig index 22c7f9fca5..edcb24cd3b 100644 --- a/configs/s5p_goni_defconfig +++ b/configs/s5p_goni_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_S5PC1XX=y CONFIG_SYS_TEXT_BASE=0x34800000 CONFIG_TARGET_S5P_GONI=y diff --git a/configs/s5pc210_universal_defconfig b/configs/s5pc210_universal_defconfig index f7ae484b95..ad52e3a2cb 100644 --- a/configs/s5pc210_universal_defconfig +++ b/configs/s5pc210_universal_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_EXYNOS=y CONFIG_SYS_TEXT_BASE=0x44800000 CONFIG_ARCH_EXYNOS4=y diff --git a/configs/sama5d27_som1_ek_mmc1_defconfig b/configs/sama5d27_som1_ek_mmc1_defconfig index 85a8fe5f09..29d364ce17 100644 --- a/configs/sama5d27_som1_ek_mmc1_defconfig +++ b/configs/sama5d27_som1_ek_mmc1_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x23f00000 CONFIG_TARGET_SAMA5D27_SOM1_EK=y diff --git a/configs/sama5d27_som1_ek_mmc_defconfig b/configs/sama5d27_som1_ek_mmc_defconfig index ae2a4e6ae1..bb74c63993 100644 --- a/configs/sama5d27_som1_ek_mmc_defconfig +++ b/configs/sama5d27_som1_ek_mmc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x23f00000 CONFIG_TARGET_SAMA5D27_SOM1_EK=y diff --git a/configs/sama5d27_som1_ek_qspiflash_defconfig b/configs/sama5d27_som1_ek_qspiflash_defconfig index 7c2eb774a4..50b7983850 100644 --- a/configs/sama5d27_som1_ek_qspiflash_defconfig +++ b/configs/sama5d27_som1_ek_qspiflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x23f00000 CONFIG_TARGET_SAMA5D27_SOM1_EK=y diff --git a/configs/sama5d2_icp_mmc_defconfig b/configs/sama5d2_icp_mmc_defconfig index dce480913a..535aab5a12 100644 --- a/configs/sama5d2_icp_mmc_defconfig +++ b/configs/sama5d2_icp_mmc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 CONFIG_TARGET_SAMA5D2_ICP=y diff --git a/configs/sama5d2_ptc_ek_mmc_defconfig b/configs/sama5d2_ptc_ek_mmc_defconfig index 266c6d2ef9..17699dec52 100644 --- a/configs/sama5d2_ptc_ek_mmc_defconfig +++ b/configs/sama5d2_ptc_ek_mmc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 CONFIG_TARGET_SAMA5D2_PTC_EK=y @@ -50,6 +51,7 @@ CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ATMEL=y CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_ATMEL_NAND_HW_PMECC=y CONFIG_PMECC_CAP=4 diff --git a/configs/sama5d2_ptc_ek_nandflash_defconfig b/configs/sama5d2_ptc_ek_nandflash_defconfig index 3f7e6270d0..0b18bd41fc 100644 --- a/configs/sama5d2_ptc_ek_nandflash_defconfig +++ b/configs/sama5d2_ptc_ek_nandflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 CONFIG_TARGET_SAMA5D2_PTC_EK=y @@ -48,6 +49,7 @@ CONFIG_I2C_EEPROM=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ATMEL=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_ATMEL_NAND_HW_PMECC=y CONFIG_PMECC_CAP=4 diff --git a/configs/sama5d2_xplained_emmc_defconfig b/configs/sama5d2_xplained_emmc_defconfig index b6b3730324..92d7c5e9cf 100644 --- a/configs/sama5d2_xplained_emmc_defconfig +++ b/configs/sama5d2_xplained_emmc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 CONFIG_TARGET_SAMA5D2_XPLAINED=y diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig index 2e80ab4eed..43990336fa 100644 --- a/configs/sama5d2_xplained_mmc_defconfig +++ b/configs/sama5d2_xplained_mmc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 CONFIG_TARGET_SAMA5D2_XPLAINED=y diff --git a/configs/sama5d2_xplained_qspiflash_defconfig b/configs/sama5d2_xplained_qspiflash_defconfig index 7395d12787..f24dac6c4f 100644 --- a/configs/sama5d2_xplained_qspiflash_defconfig +++ b/configs/sama5d2_xplained_qspiflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 CONFIG_TARGET_SAMA5D2_XPLAINED=y diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig index d35d05f085..6958621cdf 100644 --- a/configs/sama5d2_xplained_spiflash_defconfig +++ b/configs/sama5d2_xplained_spiflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 CONFIG_TARGET_SAMA5D2_XPLAINED=y @@ -29,6 +30,7 @@ CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL_TEXT_BASE=0x200000 CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set diff --git a/configs/sama5d36ek_cmp_mmc_defconfig b/configs/sama5d36ek_cmp_mmc_defconfig index bc20f17a1f..2f0415d97f 100644 --- a/configs/sama5d36ek_cmp_mmc_defconfig +++ b/configs/sama5d36ek_cmp_mmc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 CONFIG_TARGET_SAMA5D3XEK=y @@ -43,6 +44,7 @@ CONFIG_AT91_GPIO=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/sama5d36ek_cmp_nandflash_defconfig b/configs/sama5d36ek_cmp_nandflash_defconfig index 9c4ce292f5..3bcfbf071e 100644 --- a/configs/sama5d36ek_cmp_nandflash_defconfig +++ b/configs/sama5d36ek_cmp_nandflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 CONFIG_TARGET_SAMA5D3XEK=y @@ -41,6 +42,7 @@ CONFIG_DM_GPIO=y CONFIG_AT91_GPIO=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/sama5d36ek_cmp_spiflash_defconfig b/configs/sama5d36ek_cmp_spiflash_defconfig index 1004ad6876..3fbdd54c04 100644 --- a/configs/sama5d36ek_cmp_spiflash_defconfig +++ b/configs/sama5d36ek_cmp_spiflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 CONFIG_TARGET_SAMA5D3XEK=y @@ -45,6 +46,7 @@ CONFIG_AT91_GPIO=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig index 6e9d65c04c..ebd3a402ac 100644 --- a/configs/sama5d3_xplained_mmc_defconfig +++ b/configs/sama5d3_xplained_mmc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 CONFIG_TARGET_SAMA5D3_XPLAINED=y @@ -62,6 +63,7 @@ CONFIG_AT91_GPIO=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_ETH=y CONFIG_MACB=y diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig index eaeb000d18..2ebba96c23 100644 --- a/configs/sama5d3_xplained_nandflash_defconfig +++ b/configs/sama5d3_xplained_nandflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 CONFIG_TARGET_SAMA5D3_XPLAINED=y @@ -56,6 +57,7 @@ CONFIG_DM_GPIO=y CONFIG_AT91_GPIO=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_PMECC_CAP=4 CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig index ea565ecd13..86b375f7cc 100644 --- a/configs/sama5d3xek_mmc_defconfig +++ b/configs/sama5d3xek_mmc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 CONFIG_TARGET_SAMA5D3XEK=y @@ -68,6 +69,7 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig index dc8aaeb72f..120461add3 100644 --- a/configs/sama5d3xek_nandflash_defconfig +++ b/configs/sama5d3xek_nandflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 CONFIG_TARGET_SAMA5D3XEK=y @@ -61,6 +62,7 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_PMECC_CAP=4 CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig index c38b3973d0..b27a288b4a 100644 --- a/configs/sama5d3xek_spiflash_defconfig +++ b/configs/sama5d3xek_spiflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 CONFIG_TARGET_SAMA5D3XEK=y @@ -28,6 +29,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(boots # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL_TEXT_BASE=0x300000 CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -65,6 +67,7 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig index 755ff0b8f1..f9d7389613 100644 --- a/configs/sama5d4_xplained_mmc_defconfig +++ b/configs/sama5d4_xplained_mmc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 CONFIG_TARGET_SAMA5D4_XPLAINED=y @@ -59,6 +60,7 @@ CONFIG_I2C_EEPROM=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_ATMEL_NAND_HW_PMECC=y CONFIG_PMECC_CAP=8 diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig index 1a481217c7..d25cd615d6 100644 --- a/configs/sama5d4_xplained_nandflash_defconfig +++ b/configs/sama5d4_xplained_nandflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 CONFIG_TARGET_SAMA5D4_XPLAINED=y @@ -54,6 +55,7 @@ CONFIG_SYS_I2C_AT91=y CONFIG_I2C_EEPROM=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_PMECC_CAP=8 CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig index a232b741ec..a2e9595088 100644 --- a/configs/sama5d4_xplained_spiflash_defconfig +++ b/configs/sama5d4_xplained_spiflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 CONFIG_TARGET_SAMA5D4_XPLAINED=y @@ -29,6 +30,7 @@ CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL_TEXT_BASE=0x200000 CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set @@ -61,6 +63,7 @@ CONFIG_I2C_EEPROM=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig index 2dd75c3652..711de5572a 100644 --- a/configs/sama5d4ek_mmc_defconfig +++ b/configs/sama5d4ek_mmc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 CONFIG_TARGET_SAMA5D4EK=y @@ -59,6 +60,7 @@ CONFIG_AT91_GPIO=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig index e3b3f86eb5..7b1f44c451 100644 --- a/configs/sama5d4ek_nandflash_defconfig +++ b/configs/sama5d4ek_nandflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 CONFIG_TARGET_SAMA5D4EK=y @@ -54,6 +55,7 @@ CONFIG_DM_GPIO=y CONFIG_AT91_GPIO=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_PMECC_CAP=8 CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig index 67a9dfe9c2..aa1a492997 100644 --- a/configs/sama5d4ek_spiflash_defconfig +++ b/configs/sama5d4ek_spiflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 CONFIG_TARGET_SAMA5D4EK=y @@ -28,6 +29,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(boots # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL_TEXT_BASE=0x200000 CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -58,6 +60,7 @@ CONFIG_AT91_GPIO=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/sansa_fuze_plus_defconfig b/configs/sansa_fuze_plus_defconfig index 9d2b28d3bb..6f63288505 100644 --- a/configs/sansa_fuze_plus_defconfig +++ b/configs/sansa_fuze_plus_defconfig @@ -30,6 +30,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_MXS_GPIO=y CONFIG_MMC_MXS=y CONFIG_CONS_INDEX=0 CONFIG_USB=y diff --git a/configs/sc_sps_1_defconfig b/configs/sc_sps_1_defconfig index c7cdc3c0e9..e3fd8be605 100644 --- a/configs/sc_sps_1_defconfig +++ b/configs/sc_sps_1_defconfig @@ -29,6 +29,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_MXS_GPIO=y CONFIG_MMC_MXS=y CONFIG_PHYLIB=y CONFIG_MII=y diff --git a/configs/secomx6quq7_defconfig b/configs/secomx6quq7_defconfig index 40ca954487..0b690f1ae7 100644 --- a/configs/secomx6quq7_defconfig +++ b/configs/secomx6quq7_defconfig @@ -26,7 +26,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig index 73f567f0c9..734e894c98 100644 --- a/configs/sheevaplug_defconfig +++ b/configs/sheevaplug_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_SYS_THUMB_BUILD=y CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x600000 diff --git a/configs/silk_defconfig b/configs/silk_defconfig index e38f634371..64a01651ac 100644 --- a/configs/silk_defconfig +++ b/configs/silk_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set @@ -25,6 +26,7 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/sksimx6_defconfig b/configs/sksimx6_defconfig index 748b13ea84..7bc687f64d 100644 --- a/configs/sksimx6_defconfig +++ b/configs/sksimx6_defconfig @@ -33,7 +33,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig index e8d846f17c..9e73051def 100644 --- a/configs/smartweb_defconfig +++ b/configs/smartweb_defconfig @@ -48,6 +48,7 @@ CONFIG_CLK_AT91=y CONFIG_DFU_NAND=y # CONFIG_MMC is not set CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_PHYLIB=y CONFIG_USB=y diff --git a/configs/smdk5250_defconfig b/configs/smdk5250_defconfig index 1bdcc4797b..6c7eb9315c 100644 --- a/configs/smdk5250_defconfig +++ b/configs/smdk5250_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_EXYNOS=y diff --git a/configs/smdk5420_defconfig b/configs/smdk5420_defconfig index 7510f80c2e..714c9636cd 100644 --- a/configs/smdk5420_defconfig +++ b/configs/smdk5420_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_EXYNOS=y CONFIG_SYS_TEXT_BASE=0x23E00000 CONFIG_ARCH_EXYNOS5=y diff --git a/configs/smdkc100_defconfig b/configs/smdkc100_defconfig index 3e2161611c..88b56cbb81 100644 --- a/configs/smdkc100_defconfig +++ b/configs/smdkc100_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_S5PC1XX=y CONFIG_SYS_TEXT_BASE=0x34800000 CONFIG_TARGET_SMDKC100=y diff --git a/configs/smdkv310_defconfig b/configs/smdkv310_defconfig index 17257692b9..880867fdca 100644 --- a/configs/smdkv310_defconfig +++ b/configs/smdkv310_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_EXYNOS=y CONFIG_SYS_TEXT_BASE=0x43E00000 CONFIG_ARCH_EXYNOS4=y diff --git a/configs/snapper9260_defconfig b/configs/snapper9260_defconfig index be71dc84d7..d3d51c52e0 100644 --- a/configs/snapper9260_defconfig +++ b/configs/snapper9260_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21f00000 CONFIG_TARGET_SNAPPER9260=y @@ -31,6 +32,7 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_CMD_PCA953X=y # CONFIG_MMC is not set CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/snapper9g20_defconfig b/configs/snapper9g20_defconfig index aca456e59f..6466ee80f2 100644 --- a/configs/snapper9g20_defconfig +++ b/configs/snapper9g20_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x21f00000 CONFIG_TARGET_SNAPPER9260=y @@ -30,6 +31,7 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_CMD_PCA953X=y # CONFIG_MMC is not set CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/snow_defconfig b/configs/snow_defconfig index f474409516..e4d3703e00 100644 --- a/configs/snow_defconfig +++ b/configs/snow_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_EXYNOS=y diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index 3ab3cc4487..89e5ff8c71 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -13,6 +13,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xFFFF0000 CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DFU=y diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index a309e5bdc1..00f2104276 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -13,6 +13,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xFFFF0000 CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DFU=y diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig index 66f894efd2..1877010a19 100644 --- a/configs/socfpga_dbm_soc1_defconfig +++ b/configs/socfpga_dbm_soc1_defconfig @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xFFFF0000 CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_ASKENV=y diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index ebaf24761f..de50f17174 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -14,6 +14,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xFFFF0000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DFU=y diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig index 0ac97c78f2..03961195ac 100644 --- a/configs/socfpga_de10_nano_defconfig +++ b/configs/socfpga_de10_nano_defconfig @@ -13,6 +13,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xFFFF0000 CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DFU=y diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig index f3693011b0..6ea06c1104 100644 --- a/configs/socfpga_is1_defconfig +++ b/configs/socfpga_is1_defconfig @@ -15,6 +15,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xFFFF0000 CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y # CONFIG_CMD_FLASH is not set diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig index 7feedbe755..161bd6fca3 100644 --- a/configs/socfpga_mcvevk_defconfig +++ b/configs/socfpga_mcvevk_defconfig @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xFFFF0000 CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DFU=y diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index dd03bc62fe..8ec1c05571 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -13,6 +13,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xFFFF0000 CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DFU=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index 9e93281885..15f81d1a4b 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -13,6 +13,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xFFFF0000 CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DFU=y diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index 741525fead..941bf1124a 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -16,6 +16,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_TEXT_BASE=0xFFFF0000 CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index fbab388b43..ad83f50032 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_FS_FAT=y CONFIG_BOOTDELAY=5 CONFIG_SPL_TEXT_BASE=0xFFE00000 CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x3C00000 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # " CONFIG_CMD_MEMTEST=y diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index 9e86a23704..96f806ab5f 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -18,6 +18,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xFFFF0000 CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y diff --git a/configs/sopine_baseboard_defconfig b/configs/sopine_baseboard_defconfig index b78f9e8807..5833234b63 100644 --- a/configs/sopine_baseboard_defconfig +++ b/configs/sopine_baseboard_defconfig @@ -12,6 +12,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_USE_PREBOOT=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000 # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/spear300_defconfig b/configs/spear300_defconfig index 78da2a6c2d..8e22c1e9d1 100644 --- a/configs/spear300_defconfig +++ b/configs/spear300_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_TARGET_SPEAR300=y CONFIG_SYS_TEXT_BASE=0x00700000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/spear300_nand_defconfig b/configs/spear300_nand_defconfig index 7ef97ceb26..154a5cac03 100644 --- a/configs/spear300_nand_defconfig +++ b/configs/spear300_nand_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_TARGET_SPEAR300=y CONFIG_SYS_TEXT_BASE=0x00700000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/spear300_usbtty_defconfig b/configs/spear300_usbtty_defconfig index 1b0034dede..fbdd4a31af 100644 --- a/configs/spear300_usbtty_defconfig +++ b/configs/spear300_usbtty_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_TARGET_SPEAR300=y CONFIG_SYS_TEXT_BASE=0x00700000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/spear300_usbtty_nand_defconfig b/configs/spear300_usbtty_nand_defconfig index d37f6f4b4b..77926c1bb7 100644 --- a/configs/spear300_usbtty_nand_defconfig +++ b/configs/spear300_usbtty_nand_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_TARGET_SPEAR300=y CONFIG_SYS_TEXT_BASE=0x00700000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/spear310_defconfig b/configs/spear310_defconfig index 615f995962..423e1ff009 100644 --- a/configs/spear310_defconfig +++ b/configs/spear310_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_TARGET_SPEAR310=y CONFIG_SYS_TEXT_BASE=0x00700000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/spear310_nand_defconfig b/configs/spear310_nand_defconfig index 3c198980e6..29cf8f889f 100644 --- a/configs/spear310_nand_defconfig +++ b/configs/spear310_nand_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_TARGET_SPEAR310=y CONFIG_SYS_TEXT_BASE=0x00700000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/spear310_pnor_defconfig b/configs/spear310_pnor_defconfig index 8ec758e207..dea51b9efe 100644 --- a/configs/spear310_pnor_defconfig +++ b/configs/spear310_pnor_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_TARGET_SPEAR310=y CONFIG_SYS_TEXT_BASE=0x00700000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/spear310_usbtty_defconfig b/configs/spear310_usbtty_defconfig index fb238551f8..722c84804d 100644 --- a/configs/spear310_usbtty_defconfig +++ b/configs/spear310_usbtty_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_TARGET_SPEAR310=y CONFIG_SYS_TEXT_BASE=0x00700000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/spear310_usbtty_nand_defconfig b/configs/spear310_usbtty_nand_defconfig index 33599e9841..87baf30559 100644 --- a/configs/spear310_usbtty_nand_defconfig +++ b/configs/spear310_usbtty_nand_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_TARGET_SPEAR310=y CONFIG_SYS_TEXT_BASE=0x00700000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/spear310_usbtty_pnor_defconfig b/configs/spear310_usbtty_pnor_defconfig index 75cdfaf64f..7fd7dda431 100644 --- a/configs/spear310_usbtty_pnor_defconfig +++ b/configs/spear310_usbtty_pnor_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_TARGET_SPEAR310=y CONFIG_SYS_TEXT_BASE=0x00700000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/spear320_defconfig b/configs/spear320_defconfig index 07a2fc22ab..979bf04121 100644 --- a/configs/spear320_defconfig +++ b/configs/spear320_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_TARGET_SPEAR320=y CONFIG_SYS_TEXT_BASE=0x00700000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/spear320_nand_defconfig b/configs/spear320_nand_defconfig index b6b666ce90..86addccd37 100644 --- a/configs/spear320_nand_defconfig +++ b/configs/spear320_nand_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_TARGET_SPEAR320=y CONFIG_SYS_TEXT_BASE=0x00700000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/spear320_pnor_defconfig b/configs/spear320_pnor_defconfig index c5cc4657c3..f7dd487115 100644 --- a/configs/spear320_pnor_defconfig +++ b/configs/spear320_pnor_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_TARGET_SPEAR320=y CONFIG_SYS_TEXT_BASE=0x00700000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/spear320_usbtty_defconfig b/configs/spear320_usbtty_defconfig index 0d0001e842..9fab406f13 100644 --- a/configs/spear320_usbtty_defconfig +++ b/configs/spear320_usbtty_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_TARGET_SPEAR320=y CONFIG_SYS_TEXT_BASE=0x00700000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/spear320_usbtty_nand_defconfig b/configs/spear320_usbtty_nand_defconfig index c16de53838..694c51bcab 100644 --- a/configs/spear320_usbtty_nand_defconfig +++ b/configs/spear320_usbtty_nand_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_TARGET_SPEAR320=y CONFIG_SYS_TEXT_BASE=0x00700000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/spear320_usbtty_pnor_defconfig b/configs/spear320_usbtty_pnor_defconfig index b033a503f5..1dfac113d3 100644 --- a/configs/spear320_usbtty_pnor_defconfig +++ b/configs/spear320_usbtty_pnor_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_TARGET_SPEAR320=y CONFIG_SYS_TEXT_BASE=0x00700000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/spear600_defconfig b/configs/spear600_defconfig index b9a4c6693c..eeb2746a9e 100644 --- a/configs/spear600_defconfig +++ b/configs/spear600_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_TARGET_SPEAR600=y CONFIG_SYS_TEXT_BASE=0x00700000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/spear600_nand_defconfig b/configs/spear600_nand_defconfig index a48927011a..978204ecfa 100644 --- a/configs/spear600_nand_defconfig +++ b/configs/spear600_nand_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_TARGET_SPEAR600=y CONFIG_SYS_TEXT_BASE=0x00700000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/spear600_usbtty_defconfig b/configs/spear600_usbtty_defconfig index 5618505afc..2e6f3f159c 100644 --- a/configs/spear600_usbtty_defconfig +++ b/configs/spear600_usbtty_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_TARGET_SPEAR600=y CONFIG_SYS_TEXT_BASE=0x00700000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/spear600_usbtty_nand_defconfig b/configs/spear600_usbtty_nand_defconfig index 5add352d39..cc490f0e3d 100644 --- a/configs/spear600_usbtty_nand_defconfig +++ b/configs/spear600_usbtty_nand_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_TARGET_SPEAR600=y CONFIG_SYS_TEXT_BASE=0x00700000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/spring_defconfig b/configs/spring_defconfig index bfc7495a73..bdbfc64b4c 100644 --- a/configs/spring_defconfig +++ b/configs/spring_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_EXYNOS=y diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 27b8525fa2..09785b5dc1 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL=y CONFIG_TARGET_STM32MP1=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y +# CONFIG_ARMV7_VIRT is not set CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" @@ -15,6 +16,7 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3 CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 CONFIG_SYS_PROMPT="STM32MP> " # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set @@ -32,10 +34,12 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y @@ -80,7 +84,6 @@ CONFIG_NAND=y CONFIG_NAND_STM32_FMC2=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y @@ -105,7 +108,6 @@ CONFIG_REMOTEPROC_STM32_COPRO=y CONFIG_DM_RTC=y CONFIG_RTC_STM32=y CONFIG_SERIAL_RX_BUFFER=y -CONFIG_STM32_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_STM32_QSPI=y @@ -120,4 +122,6 @@ CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics" CONFIG_USB_GADGET_VENDOR_NUM=0x0483 CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_DM_VIDEO=y +CONFIG_BACKLIGHT_GPIO=y CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/stm32mp15_optee_defconfig b/configs/stm32mp15_optee_defconfig index 0565e5ec12..177cbc7d5f 100644 --- a/configs/stm32mp15_optee_defconfig +++ b/configs/stm32mp15_optee_defconfig @@ -23,10 +23,12 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y @@ -69,7 +71,6 @@ CONFIG_NAND=y CONFIG_NAND_STM32_FMC2=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y @@ -92,7 +93,6 @@ CONFIG_REMOTEPROC_STM32_COPRO=y CONFIG_DM_RTC=y CONFIG_RTC_STM32=y CONFIG_SERIAL_RX_BUFFER=y -CONFIG_STM32_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_STM32_QSPI=y @@ -107,4 +107,6 @@ CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics" CONFIG_USB_GADGET_VENDOR_NUM=0x0483 CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_DM_VIDEO=y +CONFIG_BACKLIGHT_GPIO=y CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index 844cbcd076..71ad1157ec 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -22,10 +22,12 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y @@ -68,7 +70,6 @@ CONFIG_NAND=y CONFIG_NAND_STM32_FMC2=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y @@ -91,7 +92,6 @@ CONFIG_REMOTEPROC_STM32_COPRO=y CONFIG_DM_RTC=y CONFIG_RTC_STM32=y CONFIG_SERIAL_RX_BUFFER=y -CONFIG_STM32_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_STM32_QSPI=y @@ -106,4 +106,6 @@ CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics" CONFIG_USB_GADGET_VENDOR_NUM=0x0483 CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_DM_VIDEO=y +CONFIG_BACKLIGHT_GPIO=y CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/stout_defconfig b/configs/stout_defconfig index d6d9e690a0..309709f6c5 100644 --- a/configs/stout_defconfig +++ b/configs/stout_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set @@ -25,6 +26,7 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig index 77d71ef764..3676ecd419 100644 --- a/configs/taurus_defconfig +++ b/configs/taurus_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_SPL_SYS_ICACHE_OFF=y CONFIG_SPL_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_SYS_THUMB_BUILD=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set @@ -22,7 +23,6 @@ CONFIG_DEBUG_UART_CLOCK=18432000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y -CONFIG_TPL_SYS_MALLOC_F_LEN=0x1000 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2067" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -33,7 +33,6 @@ CONFIG_BOOTCOMMAND="nand read 0x22000000 0x200000 0x300000; bootm" CONFIG_BOARD_EARLY_INIT_F=y # CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y -# CONFIG_TPL_BANNER_PRINT is not set CONFIG_SPL_CRC32_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_HUSH_PARSER=y @@ -67,6 +66,7 @@ CONFIG_CLK_AT91=y CONFIG_DFU_NAND=y # CONFIG_MMC is not set CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig index 88fbbf4bc0..f5859038be 100644 --- a/configs/tbs2910_defconfig +++ b/configs/tbs2910_defconfig @@ -50,7 +50,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_DM_KEYBOARD=y CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_MII=y CONFIG_PCI=y diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig index 9b003870e5..b88a922678 100644 --- a/configs/theadorable_debug_defconfig +++ b/configs/theadorable_debug_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00800000 CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -24,6 +25,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0x40004030 CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x1a000 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig index 4c52610271..ade82c86e3 100644 --- a/configs/thuban_defconfig +++ b/configs/thuban_defconfig @@ -25,6 +25,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y # CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set diff --git a/configs/ti814x_evm_defconfig b/configs/ti814x_evm_defconfig index e171ff846d..031fead67f 100644 --- a/configs/ti814x_evm_defconfig +++ b/configs/ti814x_evm_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y diff --git a/configs/titanium_defconfig b/configs/titanium_defconfig index 2816f66c8e..86d1da3324 100644 --- a/configs/titanium_defconfig +++ b/configs/titanium_defconfig @@ -34,7 +34,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:16M(uboot),512k(env1),512k(env2),-(ubi)" CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_NAND=y CONFIG_NAND_MXS=y CONFIG_PHYLIB=y diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig index daab4b2998..ddd43faedf 100644 --- a/configs/topic_miami_defconfig +++ b/configs/topic_miami_defconfig @@ -17,6 +17,7 @@ CONFIG_BOOTDELAY=0 CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_SYS_PROMPT="zynq-uboot> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig index f92014224a..17cc15d3c3 100644 --- a/configs/topic_miamilite_defconfig +++ b/configs/topic_miamilite_defconfig @@ -17,6 +17,7 @@ CONFIG_BOOTDELAY=0 CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_SYS_PROMPT="zynq-uboot> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig index 9ba7282c6f..3d0699d9f0 100644 --- a/configs/topic_miamiplus_defconfig +++ b/configs/topic_miamiplus_defconfig @@ -17,6 +17,7 @@ CONFIG_BOOTDELAY=0 CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_SYS_PROMPT="zynq-uboot> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y diff --git a/configs/tqma6dl_mba6_mmc_defconfig b/configs/tqma6dl_mba6_mmc_defconfig index 887f938c70..4f2d4141c8 100644 --- a/configs/tqma6dl_mba6_mmc_defconfig +++ b/configs/tqma6dl_mba6_mmc_defconfig @@ -32,7 +32,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=50000000 diff --git a/configs/tqma6dl_mba6_spi_defconfig b/configs/tqma6dl_mba6_spi_defconfig index 6abefa3bdd..9ad9ea3c2d 100644 --- a/configs/tqma6dl_mba6_spi_defconfig +++ b/configs/tqma6dl_mba6_spi_defconfig @@ -33,7 +33,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=50000000 diff --git a/configs/tqma6q_mba6_mmc_defconfig b/configs/tqma6q_mba6_mmc_defconfig index 67aae058ae..36b4b3cae8 100644 --- a/configs/tqma6q_mba6_mmc_defconfig +++ b/configs/tqma6q_mba6_mmc_defconfig @@ -31,7 +31,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=50000000 diff --git a/configs/tqma6q_mba6_spi_defconfig b/configs/tqma6q_mba6_spi_defconfig index 6ecba56ea2..21bc3fab75 100644 --- a/configs/tqma6q_mba6_spi_defconfig +++ b/configs/tqma6q_mba6_spi_defconfig @@ -32,7 +32,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=50000000 diff --git a/configs/tqma6s_mba6_mmc_defconfig b/configs/tqma6s_mba6_mmc_defconfig index d291d0fd98..0a8cc6d171 100644 --- a/configs/tqma6s_mba6_mmc_defconfig +++ b/configs/tqma6s_mba6_mmc_defconfig @@ -32,7 +32,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=50000000 diff --git a/configs/tqma6s_mba6_spi_defconfig b/configs/tqma6s_mba6_spi_defconfig index b5acd0e856..e02b8a5c10 100644 --- a/configs/tqma6s_mba6_spi_defconfig +++ b/configs/tqma6s_mba6_spi_defconfig @@ -33,7 +33,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=50000000 diff --git a/configs/tqma6s_wru4_mmc_defconfig b/configs/tqma6s_wru4_mmc_defconfig index f2a8376111..03e893044b 100644 --- a/configs/tqma6s_wru4_mmc_defconfig +++ b/configs/tqma6s_wru4_mmc_defconfig @@ -59,7 +59,7 @@ CONFIG_LED_STATUS_BIT5=5 CONFIG_LED_STATUS_STATE5=2 CONFIG_LED_STATUS_CMD=y CONFIG_PCA9551_LED=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_MII=y CONFIG_USB=y diff --git a/configs/trats2_defconfig b/configs/trats2_defconfig index 7907849cd3..86075946ed 100644 --- a/configs/trats2_defconfig +++ b/configs/trats2_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_EXYNOS=y CONFIG_SYS_TEXT_BASE=0x43e00000 CONFIG_ARCH_EXYNOS4=y diff --git a/configs/trats_defconfig b/configs/trats_defconfig index b289b82486..c8f1e29d3e 100644 --- a/configs/trats_defconfig +++ b/configs/trats_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_EXYNOS=y CONFIG_SYS_TEXT_BASE=0x63300000 CONFIG_ARCH_EXYNOS4=y diff --git a/configs/ts4600_defconfig b/configs/ts4600_defconfig index d5816f7612..b52ec639d7 100644 --- a/configs/ts4600_defconfig +++ b/configs/ts4600_defconfig @@ -22,6 +22,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_MXS_GPIO=y CONFIG_MMC_MXS=y CONFIG_CONS_INDEX=0 CONFIG_OF_LIBFDT=y diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig index 4d3f7ba8ef..36243a3016 100644 --- a/configs/turris_mox_defconfig +++ b/configs/turris_mox_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index 4c8ec3207a..c0bedf4999 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_SPL_SYS_THUMB_BUILD=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00800000 @@ -28,6 +29,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0x40000030 CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x24000 CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_SHA1SUM=y diff --git a/configs/uDPU_defconfig b/configs/uDPU_defconfig index c312b1af6a..f8d5a14397 100644 --- a/configs/uDPU_defconfig +++ b/configs/uDPU_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig index 259ffee043..ea6da7aa65 100644 --- a/configs/udoo_defconfig +++ b/configs/udoo_defconfig @@ -29,7 +29,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y CONFIG_DWC_AHSATA=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig index 4f00e48110..597f557f7b 100644 --- a/configs/udoo_neo_defconfig +++ b/configs/udoo_neo_defconfig @@ -28,7 +28,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y diff --git a/configs/usb_a9263_dataflash_defconfig b/configs/usb_a9263_dataflash_defconfig index c278a5b48c..5779aeb053 100644 --- a/configs/usb_a9263_dataflash_defconfig +++ b/configs/usb_a9263_dataflash_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x23f00000 CONFIG_TARGET_USB_A9263=y @@ -37,6 +38,7 @@ CONFIG_DM_GPIO=y CONFIG_AT91_GPIO=y # CONFIG_MMC is not set CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/variscite_dart6ul_defconfig b/configs/variscite_dart6ul_defconfig index 55f4ff59d2..cb1b17c424 100644 --- a/configs/variscite_dart6ul_defconfig +++ b/configs/variscite_dart6ul_defconfig @@ -30,7 +30,7 @@ CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="imx6ull-dart-6ul" CONFIG_DM_I2C_GPIO=y CONFIG_SYS_I2C_MXC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_FEC_MXC=y diff --git a/configs/vexpress_aemv8a_dram_defconfig b/configs/vexpress_aemv8a_dram_defconfig deleted file mode 100644 index 2ff9e4b9f2..0000000000 --- a/configs/vexpress_aemv8a_dram_defconfig +++ /dev/null @@ -1,39 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM=y -CONFIG_SYS_TEXT_BASE=0x88000000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_IDENT_STRING=" vexpress_aemv8a" -CONFIG_DISTRO_DEFAULTS=y -CONFIG_BOOTDELAY=1 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyAMA0 earlyprintk=pl011,0x1c090000 debug user_debug=31 androidboot.hardware=fvpbase root=/dev/vda2 rw rootwait loglevel=9" -# CONFIG_USE_BOOTCOMMAND is not set -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SYS_PROMPT="VExpress64# " -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_ARMFLASH=y -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NFS is not set -CONFIG_CMD_CACHE=y -# CONFIG_CMD_MISC is not set -CONFIG_CMD_UBI=y -# CONFIG_ISO_PARTITION is not set -# CONFIG_EFI_PARTITION is not set -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_DM=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_MTD_DEVICE=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_DM_SERIAL=y -CONFIG_OF_LIBFDT=y diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig index fd306f9f6b..0823d17c11 100644 --- a/configs/vexpress_aemv8a_juno_defconfig +++ b/configs/vexpress_aemv8a_juno_defconfig @@ -7,7 +7,7 @@ CONFIG_IDENT_STRING=" vexpress_aemv8a" CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyAMA0,115200n8 root=/dev/sda2 rw rootwait earlyprintk=pl011,0x7ff80000 debug user_debug=31 androidboot.hardware=juno loglevel=9" +CONFIG_BOOTARGS="console=ttyAMA0,115200n8 root=/dev/sda2 rw rootwait earlycon=pl011,0x7ff80000 debug user_debug=31 androidboot.hardware=juno loglevel=9" # CONFIG_USE_BOOTCOMMAND is not set # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig index bff52f7038..db5ad3dfa5 100644 --- a/configs/vexpress_aemv8a_semi_defconfig +++ b/configs/vexpress_aemv8a_semi_defconfig @@ -7,7 +7,7 @@ CONFIG_IDENT_STRING=" vexpress_aemv8a" CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyAMA0 earlyprintk=pl011,0x1c090000 debug user_debug=31 loglevel=9" +CONFIG_BOOTARGS="console=ttyAMA0 earlycon=pl011,0x1c090000 debug user_debug=31 loglevel=9" # CONFIG_USE_BOOTCOMMAND is not set # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/vf610twr_defconfig b/configs/vf610twr_defconfig index 3ad60e68b7..f3e55b87bd 100644 --- a/configs/vf610twr_defconfig +++ b/configs/vf610twr_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_SYS_THUMB_BUILD=y -# CONFIG_SPL_SYS_THUMB_BUILD is not set CONFIG_ARCH_VF610=y CONFIG_SYS_TEXT_BASE=0x3f401000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/vf610twr_nand_defconfig b/configs/vf610twr_nand_defconfig index d7598c47c5..64b108d41d 100644 --- a/configs/vf610twr_nand_defconfig +++ b/configs/vf610twr_nand_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_SYS_THUMB_BUILD=y -# CONFIG_SPL_SYS_THUMB_BUILD is not set CONFIG_ARCH_VF610=y CONFIG_SYS_TEXT_BASE=0x3f401000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/vinco_defconfig b/configs/vinco_defconfig index 4d71908767..4ab62e74ae 100644 --- a/configs/vinco_defconfig +++ b/configs/vinco_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x20f00000 CONFIG_TARGET_VINCO=y diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig index c731d96e9c..b007a76035 100644 --- a/configs/vining_2000_defconfig +++ b/configs/vining_2000_defconfig @@ -3,10 +3,8 @@ CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_TARGET_SOFTING_VINING_2000=y -CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 CONFIG_NR_DRAM_BANKS=1 # CONFIG_CMD_BMODE is not set -CONFIG_TPL_SYS_MALLOC_F_LEN=0x400 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/softing/vining_2000/imximage.cfg" CONFIG_BOOTDELAY=0 CONFIG_SYS_CONSOLE_IS_IN_ENV=y @@ -42,7 +40,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_MII=y CONFIG_PCI=y diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig index c4a9624f4b..f07ec5f651 100644 --- a/configs/wandboard_defconfig +++ b/configs/wandboard_defconfig @@ -54,7 +54,7 @@ CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_MII=y CONFIG_PINCTRL=y diff --git a/configs/warp7_bl33_defconfig b/configs/warp7_bl33_defconfig index a0289421ff..80accfb509 100644 --- a/configs/warp7_bl33_defconfig +++ b/configs/warp7_bl33_defconfig @@ -33,7 +33,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_DM_PMIC=y diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig index 11f16cf47d..a022454976 100644 --- a/configs/warp7_defconfig +++ b/configs/warp7_defconfig @@ -39,7 +39,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_DM_PMIC=y diff --git a/configs/warp_defconfig b/configs/warp_defconfig index 0f911a9669..7a6ea6f8c6 100644 --- a/configs/warp_defconfig +++ b/configs/warp_defconfig @@ -30,7 +30,7 @@ CONFIG_ENV_IS_IN_MMC=y # CONFIG_NET is not set CONFIG_DFU_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y diff --git a/configs/wb45n_defconfig b/configs/wb45n_defconfig index 16fb4449a3..be6744b82b 100644 --- a/configs/wb45n_defconfig +++ b/configs/wb45n_defconfig @@ -29,6 +29,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_MTDPARTS=y CONFIG_ENV_IS_IN_NAND=y CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_PMECC_CAP=4 CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y diff --git a/configs/wb50n_defconfig b/configs/wb50n_defconfig index 417eda36e9..ef427f350d 100644 --- a/configs/wb50n_defconfig +++ b/configs/wb50n_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x23f00000 CONFIG_TARGET_WB50N=y @@ -28,6 +29,7 @@ CONFIG_CMD_PING=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NAND=y +# CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_PMECC_CAP=8 CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig index 01c8884f2b..5131805c4a 100644 --- a/configs/work_92105_defconfig +++ b/configs/work_92105_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_SYS_ICACHE_OFF=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_LPC32XX=y CONFIG_SYS_TEXT_BASE=0x80100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y diff --git a/configs/x530_defconfig b/configs/x530_defconfig index 7db8de4a02..05526fe8ee 100644 --- a/configs/x530_defconfig +++ b/configs/x530_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00800000 CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -21,6 +22,8 @@ CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC=y CONFIG_MISC_INIT_R=y CONFIG_SPL_TEXT_BASE=0x40000030 CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x24000 CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_CMD_MEMINFO=y # CONFIG_CMD_FLASH is not set @@ -51,6 +54,7 @@ CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y # CONFIG_MMC is not set CONFIG_NAND=y +CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_PXA3XX=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=1 diff --git a/configs/x600_defconfig b/configs/x600_defconfig index 203e91f77e..e4e5c57a74 100644 --- a/configs/x600_defconfig +++ b/configs/x600_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y CONFIG_SYS_THUMB_BUILD=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set @@ -24,6 +25,7 @@ CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_CMD_IMLS=y CONFIG_LOOPW=y +CONFIG_MX_CYCLIC=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_NAND=y diff --git a/configs/xfi3_defconfig b/configs/xfi3_defconfig index 054e3a7e3a..6e0edb05ad 100644 --- a/configs/xfi3_defconfig +++ b/configs/xfi3_defconfig @@ -29,6 +29,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_MXS_GPIO=y CONFIG_MMC_MXS=y CONFIG_CONS_INDEX=0 CONFIG_USB=y diff --git a/configs/xpress_defconfig b/configs/xpress_defconfig index 64fed1dc72..70cdd792b7 100644 --- a/configs/xpress_defconfig +++ b/configs/xpress_defconfig @@ -26,7 +26,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_MII=y CONFIG_USB=y diff --git a/configs/xpress_spl_defconfig b/configs/xpress_spl_defconfig index c203353f58..913d577bcd 100644 --- a/configs/xpress_spl_defconfig +++ b/configs/xpress_spl_defconfig @@ -37,7 +37,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_MII=y CONFIG_USB=y diff --git a/configs/xtfpga_defconfig b/configs/xtfpga_defconfig index deb979944a..051bba0ceb 100644 --- a/configs/xtfpga_defconfig +++ b/configs/xtfpga_defconfig @@ -13,6 +13,7 @@ CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_CMD_IMLS=y CONFIG_CMD_ASKENV=y CONFIG_CRC32_VERIFY=y +CONFIG_MX_CYCLIC=y CONFIG_CMD_SAVES=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y diff --git a/configs/zc5202_defconfig b/configs/zc5202_defconfig index 1aee743590..6ba4bd54f7 100644 --- a/configs/zc5202_defconfig +++ b/configs/zc5202_defconfig @@ -23,6 +23,7 @@ CONFIG_SPL_TEXT_BASE=0x00908000 CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -35,7 +36,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=3 CONFIG_SF_DEFAULT_MODE=0 diff --git a/configs/zc5601_defconfig b/configs/zc5601_defconfig index f361ad93a8..676691d19e 100644 --- a/configs/zc5601_defconfig +++ b/configs/zc5601_defconfig @@ -23,6 +23,7 @@ CONFIG_SPL_TEXT_BASE=0x00908000 CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y @@ -34,7 +35,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=3 CONFIG_SF_DEFAULT_MODE=0 diff --git a/configs/zynq_cc108_defconfig b/configs/zynq_cc108_defconfig index 76a9a120ca..9bfe5ce996 100644 --- a/configs/zynq_cc108_defconfig +++ b/configs/zynq_cc108_defconfig @@ -17,6 +17,7 @@ CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig index e12306f844..4972d70805 100644 --- a/configs/zynq_cse_qspi_defconfig +++ b/configs/zynq_cse_qspi_defconfig @@ -22,6 +22,7 @@ CONFIG_USE_PREBOOT=y # CONFIG_ARCH_EARLY_INIT_R is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set # CONFIG_SYS_LONGHELP is not set diff --git a/configs/zynq_dlc20_rev1_0_defconfig b/configs/zynq_dlc20_rev1_0_defconfig index 1b4233ca9a..b6751ad35b 100644 --- a/configs/zynq_dlc20_rev1_0_defconfig +++ b/configs/zynq_dlc20_rev1_0_defconfig @@ -20,6 +20,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_DFU=y diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig index 3de1928e75..d30581b241 100644 --- a/configs/zynq_microzed_defconfig +++ b/configs/zynq_microzed_defconfig @@ -15,6 +15,7 @@ CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_DFU=y diff --git a/configs/zynq_z_turn_defconfig b/configs/zynq_z_turn_defconfig index ea24915203..d133fea395 100644 --- a/configs/zynq_z_turn_defconfig +++ b/configs/zynq_z_turn_defconfig @@ -18,6 +18,7 @@ CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_DFU=y diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig index caf97d83f1..6b670aefc9 100644 --- a/configs/zynq_zc702_defconfig +++ b/configs/zynq_zc702_defconfig @@ -19,6 +19,7 @@ CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig index d4fcf9da04..3d0cd314c6 100644 --- a/configs/zynq_zc706_defconfig +++ b/configs/zynq_zc706_defconfig @@ -22,6 +22,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_FPGA_SUPPORT=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_DFU=y diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig index 6458e62e1e..53108ff03c 100644 --- a/configs/zynq_zc770_xm010_defconfig +++ b/configs/zynq_zc770_xm010_defconfig @@ -19,6 +19,7 @@ CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig index 5195ec3d8c..30bb0ef3f2 100644 --- a/configs/zynq_zc770_xm013_defconfig +++ b/configs/zynq_zc770_xm013_defconfig @@ -17,6 +17,7 @@ CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig index 1254b4efe9..9b6d754872 100644 --- a/configs/zynq_zed_defconfig +++ b/configs/zynq_zed_defconfig @@ -18,6 +18,7 @@ CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_DFU=y diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index 078b436add..2abc6db0d0 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -18,6 +18,7 @@ CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_DFU=y diff --git a/configs/zynq_zybo_z7_defconfig b/configs/zynq_zybo_z7_defconfig index 3c974925c4..eda1416a9b 100644 --- a/configs/zynq_zybo_z7_defconfig +++ b/configs/zynq_zybo_z7_defconfig @@ -18,6 +18,7 @@ CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_DFU=y diff --git a/disk/part_efi.c b/disk/part_efi.c index 359b55a818..51fa4a74ab 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -51,6 +51,8 @@ static int is_gpt_valid(struct blk_desc *dev_desc, u64 lba, static gpt_entry *alloc_read_gpt_entries(struct blk_desc *dev_desc, gpt_header *pgpt_head); static int is_pte_valid(gpt_entry * pte); +static int find_valid_gpt(struct blk_desc *dev_desc, gpt_header *gpt_head, + gpt_entry **pgpt_pte); static char *print_efiname(gpt_entry *pte) { @@ -192,19 +194,8 @@ int get_disk_guid(struct blk_desc * dev_desc, char *guid) unsigned char *guid_bin; /* This function validates AND fills in the GPT header and PTE */ - if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA, - gpt_head, &gpt_pte) != 1) { - printf("%s: *** ERROR: Invalid GPT ***\n", __func__); - if (is_gpt_valid(dev_desc, dev_desc->lba - 1, - gpt_head, &gpt_pte) != 1) { - printf("%s: *** ERROR: Invalid Backup GPT ***\n", - __func__); - return -EINVAL; - } else { - printf("%s: *** Using Backup GPT ***\n", - __func__); - } - } + if (find_valid_gpt(dev_desc, gpt_head, &gpt_pte) != 1) + return -EINVAL; guid_bin = gpt_head->disk_guid.b; uuid_bin_to_str(guid_bin, guid, UUID_STR_FORMAT_GUID); @@ -223,19 +214,8 @@ void part_print_efi(struct blk_desc *dev_desc) unsigned char *uuid_bin; /* This function validates AND fills in the GPT header and PTE */ - if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA, - gpt_head, &gpt_pte) != 1) { - printf("%s: *** ERROR: Invalid GPT ***\n", __func__); - if (is_gpt_valid(dev_desc, (dev_desc->lba - 1), - gpt_head, &gpt_pte) != 1) { - printf("%s: *** ERROR: Invalid Backup GPT ***\n", - __func__); - return; - } else { - printf("%s: *** Using Backup GPT ***\n", - __func__); - } - } + if (find_valid_gpt(dev_desc, gpt_head, &gpt_pte) != 1) + return; debug("%s: gpt-entry at %p\n", __func__, gpt_pte); @@ -284,19 +264,8 @@ int part_get_info_efi(struct blk_desc *dev_desc, int part, } /* This function validates AND fills in the GPT header and PTE */ - if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA, - gpt_head, &gpt_pte) != 1) { - printf("%s: *** ERROR: Invalid GPT ***\n", __func__); - if (is_gpt_valid(dev_desc, (dev_desc->lba - 1), - gpt_head, &gpt_pte) != 1) { - printf("%s: *** ERROR: Invalid Backup GPT ***\n", - __func__); - return -1; - } else { - printf("%s: *** Using Backup GPT ***\n", - __func__); - } - } + if (find_valid_gpt(dev_desc, gpt_head, &gpt_pte) != 1) + return -1; if (part > le32_to_cpu(gpt_head->num_partition_entries) || !is_pte_valid(&gpt_pte[part - 1])) { @@ -939,7 +908,7 @@ static int is_pmbr_valid(legacy_mbr * mbr) * gpt is a GPT header ptr, filled on return. * ptes is a PTEs ptr, filled on return. * - * Description: returns 1 if valid, 0 on error. + * Description: returns 1 if valid, 0 on error, 2 if ignored header * If valid, returns pointers to PTEs. */ static int is_gpt_valid(struct blk_desc *dev_desc, u64 lba, @@ -965,6 +934,12 @@ static int is_gpt_valid(struct blk_desc *dev_desc, u64 lba, return 0; } + /* Invalid but nothing to yell about. */ + if (le64_to_cpu(pgpt_head->signature) == GPT_HEADER_CHROMEOS_IGNORE) { + debug("ChromeOS 'IGNOREME' GPT header found and ignored\n"); + return 2; + } + if (validate_gpt_header(pgpt_head, (lbaint_t)lba, dev_desc->lba)) return 0; @@ -997,6 +972,40 @@ static int is_gpt_valid(struct blk_desc *dev_desc, u64 lba, } /** + * find_valid_gpt() - finds a valid GPT header and PTEs + * + * gpt is a GPT header ptr, filled on return. + * ptes is a PTEs ptr, filled on return. + * + * Description: returns 1 if found a valid gpt, 0 on error. + * If valid, returns pointers to PTEs. + */ +static int find_valid_gpt(struct blk_desc *dev_desc, gpt_header *gpt_head, + gpt_entry **pgpt_pte) +{ + int r; + + r = is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA, gpt_head, + pgpt_pte); + + if (r != 1) { + if (r != 2) + printf("%s: *** ERROR: Invalid GPT ***\n", __func__); + + if (is_gpt_valid(dev_desc, (dev_desc->lba - 1), gpt_head, + pgpt_pte) != 1) { + printf("%s: *** ERROR: Invalid Backup GPT ***\n", + __func__); + return 0; + } + if (r != 2) + printf("%s: *** Using Backup GPT ***\n", + __func__); + } + return 1; +} + +/** * alloc_read_gpt_entries(): reads partition entries from disk * @dev_desc * @gpt - GPT header diff --git a/doc/README.rockchip b/doc/README.rockchip index 7d4dc1b33b..531a062c9e 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -28,10 +28,9 @@ You will need: Building ======== -At present 12 RK3288 boards are supported: +At present 11 RK3288 boards are supported: - EVB RK3288 - use evb-rk3288 configuration - - Fennec RK3288 - use fennec-rk3288 configuration - Firefly RK3288 - use firefly-rk3288 configuration - Hisense Chromebook - use chromebook_jerry configuration - Asus C100P Chromebook - use chromebook_minnie configuration @@ -560,7 +559,7 @@ header and skipping every second 2KB block. Then the U-Boot image is written at offset 128KB and the whole image is padded to 4MB which is the SPI flash size. The position of U-Boot is controlled with this setting in U-Boot: - #define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10) + #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 If you have a Dediprog em100pro connected then you can write the image with: diff --git a/doc/board/emulation/qemu-riscv.rst b/doc/board/emulation/qemu-riscv.rst index 214833496b..fe7505e201 100644 --- a/doc/board/emulation/qemu-riscv.rst +++ b/doc/board/emulation/qemu-riscv.rst @@ -6,7 +6,8 @@ QEMU RISC-V QEMU for RISC-V supports a special 'virt' machine designed for emulation and virtualization purposes. This document describes how to run U-Boot under it. -Both 32-bit 64-bit targets are supported. +Both 32-bit and 64-bit targets are supported, running in either machine or +supervisor mode. The QEMU virt machine models a generic RISC-V virtual machine with support for the VirtIO standard networking and block storage devices. It has CLINT, PLIC, @@ -28,6 +29,11 @@ Set the CROSS_COMPILE environment variable as usual, and run: make qemu-riscv64_defconfig make +This will compile U-Boot for machine mode. To build supervisor mode binaries, +use the configurations qemu-riscv32_smode_defconfig and +qemu-riscv64_smode_defconfig instead. Note that U-Boot running in supervisor +mode requires a supervisor binary interface (SBI), such as RISC-V OpenSBI. + Running U-Boot -------------- The minimal QEMU command line to get U-Boot up and running is: @@ -46,4 +52,56 @@ parameter. For example, '-m 2G' creates 2GiB memory for the target, and the memory node in the embedded DTB created by QEMU reflects the new setting. +For instructions on how to run U-Boot in supervisor mode on QEMU +with OpenSBI, see the documentation available with OpenSBI: +https://github.com/riscv/opensbi/blob/master/docs/platform/qemu_virt.md + These have been tested in QEMU 3.0.0. + +Running U-Boot SPL +------------------ +In the default SPL configuration, U-Boot SPL starts in machine mode. U-Boot +proper and OpenSBI (FW_DYNAMIC firmware) are bundled as FIT image and made +available to U-Boot SPL. Both are then loaded by U-Boot SPL and the location +of U-Boot proper is passed to OpenSBI. After initialization, U-Boot proper is +started in supervisor mode by OpenSBI. + +OpenSBI must be compiled before compiling U-Boot. Version 0.4 and higher is +supported by U-Boot. Clone the OpenSBI repository and run the following command. + +.. code-block:: console + + git clone https://github.com/riscv/opensbi.git + cd opensbi + make PLATFORM=qemu/virt + +See the OpenSBI documentation for full details: +https://github.com/riscv/opensbi/blob/master/docs/platform/qemu_virt.md + +To make the FW_DYNAMIC binary (build/platform/qemu/virt/firmware/fw_dynamic.bin) +available to U-Boot, either copy it into the U-Boot root directory or specify +its location with the OPENSBI environment variable. Afterwards, compile U-Boot +with the following commands. + +- For 32-bit RISC-V:: + + make qemu-riscv32_spl_defconfig + make + +- For 64-bit RISC-V:: + + make qemu-riscv64_spl_defconfig + make + +The minimal QEMU commands to run U-Boot SPL in both 32-bit and 64-bit +configurations are: + +- For 32-bit RISC-V:: + + qemu-system-riscv32 -nographic -machine virt -kernel spl/u-boot-spl \ + -device loader,file=u-boot.itb,addr=0x80200000 + +- For 64-bit RISC-V:: + + qemu-system-riscv64 -nographic -machine virt -kernel spl/u-boot-spl \ + -device loader,file=u-boot.itb,addr=0x80200000 diff --git a/doc/device-tree-bindings/clock/st,stm32mp1.txt b/doc/device-tree-bindings/clock/st,stm32mp1.txt index 02e14609bb..ec1d703f34 100644 --- a/doc/device-tree-bindings/clock/st,stm32mp1.txt +++ b/doc/device-tree-bindings/clock/st,stm32mp1.txt @@ -164,8 +164,10 @@ used to define the state of associated ST32MP1 oscillators: - clk-csi At boot the clock tree initialization will - - enable oscillators present in device tree + - enable oscillators present in device tree and not disabled + (node with status="disabled"), - disable HSI oscillator if the node is absent (always activated by bootrom) + and not disabled (node with status="disabled"). Optional properties : diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index e3135bb75f..9a08575053 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -1167,6 +1167,14 @@ int ahci_probe_scsi(struct udevice *ahci_dev, ulong base) if (ret) return ret; + /* + * scsi_scan_dev() scans devices up-to the number of max_id. + * Update max_id if the number of detected ports exceeds max_id. + * This allows SCSI to scan all detected ports. + */ + uc_plat->max_id = max_t(unsigned long, uc_priv->n_ports, + uc_plat->max_id); + return 0; } diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c index c23b6682a6..baaf431e5e 100644 --- a/drivers/block/blk-uclass.c +++ b/drivers/block/blk-uclass.c @@ -208,11 +208,7 @@ int blk_select_hwpart_devnum(enum if_type if_type, int devnum, int hwpart) if (ret) return ret; - ret = blk_select_hwpart(dev, hwpart); - if (!ret) - blkcache_invalidate(if_type, devnum); - - return ret; + return blk_select_hwpart(dev, hwpart); } int blk_list_part(enum if_type if_type) @@ -352,13 +348,7 @@ int blk_select_hwpart(struct udevice *dev, int hwpart) int blk_dselect_hwpart(struct blk_desc *desc, int hwpart) { - int ret; - - ret = blk_select_hwpart(desc->bdev, hwpart); - if (!ret) - blkcache_invalidate(desc->if_type, desc->devnum); - - return ret; + return blk_select_hwpart(desc->bdev, hwpart); } int blk_first_device(int if_type, struct udevice **devp) diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index a3f0171b45..95fe0aea2c 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -48,7 +48,7 @@ config CLK_BOSTON config SPL_CLK_CCF bool "SPL Common Clock Framework [CCF] support " - depends on SPL_CLK_IMX6Q + depends on SPL help Enable this option if you want to (re-)use the Linux kernel's Common Clock Framework [CCF] code in U-Boot's SPL. @@ -62,7 +62,6 @@ config SPL_CLK_COMPOSITE_CCF config CLK_CCF bool "Common Clock Framework [CCF] support " - depends on CLK_IMX6Q || SANDBOX_CLK_CCF help Enable this option if you want to (re-)use the Linux kernel's Common Clock Framework [CCF] code in U-Boot's clock driver. diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index c66b6f3c4e..64c181f4ad 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -449,13 +449,45 @@ int clk_set_parent(struct clk *clk, struct clk *parent) int clk_enable(struct clk *clk) { const struct clk_ops *ops = clk_dev_ops(clk->dev); + struct clk *clkp = NULL; + int ret; debug("%s(clk=%p)\n", __func__, clk); - if (!ops->enable) - return -ENOSYS; + if (CONFIG_IS_ENABLED(CLK_CCF)) { + /* Take id 0 as a non-valid clk, such as dummy */ + if (clk->id && !clk_get_by_id(clk->id, &clkp)) { + if (clkp->enable_count) { + clkp->enable_count++; + return 0; + } + if (clkp->dev->parent && + device_get_uclass_id(clkp->dev) == UCLASS_CLK) { + ret = clk_enable(dev_get_clk_ptr(clkp->dev->parent)); + if (ret) { + printf("Enable %s failed\n", + clkp->dev->parent->name); + return ret; + } + } + } - return ops->enable(clk); + if (ops->enable) { + ret = ops->enable(clk); + if (ret) { + printf("Enable %s failed\n", clk->dev->name); + return ret; + } + } + if (clkp) + clkp->enable_count++; + } else { + if (!ops->enable) + return -ENOSYS; + return ops->enable(clk); + } + + return 0; } int clk_enable_bulk(struct clk_bulk *bulk) @@ -474,13 +506,46 @@ int clk_enable_bulk(struct clk_bulk *bulk) int clk_disable(struct clk *clk) { const struct clk_ops *ops = clk_dev_ops(clk->dev); + struct clk *clkp = NULL; + int ret; debug("%s(clk=%p)\n", __func__, clk); - if (!ops->disable) - return -ENOSYS; + if (CONFIG_IS_ENABLED(CLK_CCF)) { + if (clk->id && !clk_get_by_id(clk->id, &clkp)) { + if (clkp->enable_count == 0) { + printf("clk %s already disabled\n", + clkp->dev->name); + return 0; + } - return ops->disable(clk); + if (--clkp->enable_count > 0) + return 0; + } + + if (ops->disable) { + ret = ops->disable(clk); + if (ret) + return ret; + } + + if (clkp && clkp->dev->parent && + device_get_uclass_id(clkp->dev) == UCLASS_CLK) { + ret = clk_disable(dev_get_clk_ptr(clkp->dev->parent)); + if (ret) { + printf("Disable %s failed\n", + clkp->dev->parent->name); + return ret; + } + } + } else { + if (!ops->disable) + return -ENOSYS; + + return ops->disable(clk); + } + + return 0; } int clk_disable_bulk(struct clk_bulk *bulk) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 39b3087067..1cf9987f6c 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -40,6 +40,7 @@ int clk_register(struct clk *clk, const char *drv_name, return ret; } + clk->enable_count = 0; /* Store back pointer to clk from udevice */ clk->dev->uclass_priv = clk; diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c index 08cce0d79b..f51126793e 100644 --- a/drivers/clk/clk_fixed_rate.c +++ b/drivers/clk/clk_fixed_rate.c @@ -27,6 +27,7 @@ static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev) /* Make fixed rate clock accessible from higher level struct clk */ dev->uclass_priv = clk; clk->dev = dev; + clk->enable_count = 0; return 0; } diff --git a/drivers/clk/clk_sandbox_ccf.c b/drivers/clk/clk_sandbox_ccf.c index e126f18d8e..9fa27229e1 100644 --- a/drivers/clk/clk_sandbox_ccf.c +++ b/drivers/clk/clk_sandbox_ccf.c @@ -25,6 +25,18 @@ struct clk_pllv3 { u32 div_shift; }; +int sandbox_clk_enable_count(struct clk *clk) +{ + struct clk *clkp = NULL; + int ret; + + ret = clk_get_by_id(clk->id, &clkp); + if (ret) + return 0; + + return clkp->enable_count; +} + static ulong clk_pllv3_get_rate(struct clk *clk) { unsigned long parent_rate = clk_get_parent_rate(clk); @@ -254,6 +266,9 @@ static int sandbox_clk_ccf_probe(struct udevice *dev) sandbox_clk_composite("i2c", i2c_sels, ARRAY_SIZE(i2c_sels), ®, 0)); + clk_dm(SANDBOX_CLK_I2C_ROOT, + sandbox_clk_gate2("i2c_root", "i2c", base + 0x7c, 0)); + return 0; } diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index 5806d48696..e87307fa60 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -15,6 +15,8 @@ #include <dt-bindings/clock/stm32mp1-clks.h> #include <dt-bindings/clock/stm32mp1-clksrc.h> +DECLARE_GLOBAL_DATA_PTR; + #ifndef CONFIG_STM32MP1_TRUSTED #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) /* activate clock tree initialization in the driver */ @@ -759,9 +761,6 @@ static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx) return 0; } - debug("%s: clk id %d = %x : %ld kHz\n", __func__, idx, - (u32)priv->osc[idx], priv->osc[idx] / 1000); - return priv->osc[idx]; } @@ -863,8 +862,6 @@ static ulong pll_get_fref_ck(struct stm32mp1_clk_priv *priv, src = selr & RCC_SELR_SRC_MASK; refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]); - debug("PLL%d : selr=%x refclk = %d kHz\n", - pll_id, selr, (u32)(refclk / 1000)); return refclk; } @@ -889,9 +886,6 @@ static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv, divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; - debug("PLL%d : cfgr1=%x fracr=%x DIVN=%d DIVM=%d\n", - pll_id, cfgr1, fracr, divn, divm); - refclk = pll_get_fref_ck(priv, pll_id); /* with FRACV : @@ -908,7 +902,6 @@ static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv, } else { fvco = (ulong)(refclk * (divn + 1) / (divm + 1)); } - debug("PLL%d : %s = %ld\n", pll_id, __func__, fvco); return fvco; } @@ -921,17 +914,13 @@ static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv, ulong dfout; u32 cfgr2; - debug("%s(%d, %d)\n", __func__, pll_id, div_id); if (div_id >= _DIV_NB) return 0; cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2); divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK; - debug("PLL%d : cfgr2=%x DIVY=%d\n", pll_id, cfgr2, divy); - dfout = pll_get_fvco(priv, pll_id) / (divy + 1); - debug(" => dfout = %d kHz\n", (u32)(dfout / 1000)); return dfout; } @@ -1574,9 +1563,6 @@ static void stgen_config(struct stm32mp1_clk_priv *priv) /* need to update gd->arch.timer_rate_hz with new frequency */ timer_init(); - pr_debug("gd->arch.timer_rate_hz = %x\n", - (u32)gd->arch.timer_rate_hz); - pr_debug("Tick = %x\n", (u32)(get_ticks())); } } @@ -1882,7 +1868,6 @@ static int pll_set_output_rate(struct udevice *dev, if (div > 128) div = 128; - debug("fvco = %ld, clk_rate = %ld, div=%d\n", fvco, clk_rate, div); /* stop the requested output */ clrbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT); /* change divider */ @@ -1915,6 +1900,9 @@ static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate) } p = stm32mp1_clk_get_parent(priv, clk->id); +#ifdef DEBUG + debug("%s: parent = %d:%s\n", __func__, p, stm32mp1_clk_parent_name[p]); +#endif if (p < 0) return -EINVAL; @@ -1932,6 +1920,7 @@ static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate) return result; } #endif + case _PLL4_Q: /* for LTDC_PX and DSI_PX case */ return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate); @@ -2055,22 +2044,22 @@ static int stm32mp1_clk_probe(struct udevice *dev) stm32mp1_clk_dump(priv); #endif + gd->cpu_clk = stm32mp1_clk_get(priv, _CK_MPU); + gd->bus_clk = stm32mp1_clk_get(priv, _ACLK); + /* DDRPHYC father */ + gd->mem_clk = stm32mp1_clk_get(priv, _PLL2_R); #if defined(CONFIG_DISPLAY_CPUINFO) if (gd->flags & GD_FLG_RELOC) { char buf[32]; printf("Clocks:\n"); - printf("- MPU : %s MHz\n", - strmhz(buf, stm32mp1_clk_get(priv, _CK_MPU))); + printf("- MPU : %s MHz\n", strmhz(buf, gd->cpu_clk)); printf("- MCU : %s MHz\n", strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU))); - printf("- AXI : %s MHz\n", - strmhz(buf, stm32mp1_clk_get(priv, _ACLK))); + printf("- AXI : %s MHz\n", strmhz(buf, gd->bus_clk)); printf("- PER : %s MHz\n", strmhz(buf, stm32mp1_clk_get(priv, _CK_PER))); - /* DDRPHYC father */ - printf("- DDR : %s MHz\n", - strmhz(buf, stm32mp1_clk_get(priv, _PLL2_R))); + printf("- DDR : %s MHz\n", strmhz(buf, gd->mem_clk)); } #endif /* CONFIG_DISPLAY_CPUINFO */ #endif diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig index 3e6a980c8c..aae69cf9b0 100644 --- a/drivers/clk/imx/Kconfig +++ b/drivers/clk/imx/Kconfig @@ -20,3 +20,19 @@ config CLK_IMX8 select CLK help This enables support clock driver for i.MX8 platforms. + +config SPL_CLK_IMX8MM + bool "SPL clock support for i.MX8MM" + depends on ARCH_IMX8M && SPL + select SPL_CLK + select SPL_CLK_CCF + help + This enables SPL DM/DTS support for clock driver in i.MX8MM + +config CLK_IMX8MM + bool "Clock support for i.MX8MM" + depends on ARCH_IMX8M + select CLK + select CLK_CCF + help + This enables support clock driver for i.MX8MM platforms. diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 105a58ca90..5ad7967fe9 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -10,3 +10,5 @@ ifdef CONFIG_CLK_IMX8 obj-$(CONFIG_IMX8QXP) += clk-imx8qxp.o obj-$(CONFIG_IMX8QM) += clk-imx8qm.o endif +obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MM) += clk-imx8mm.o clk-pll14xx.o \ + clk-composite-8m.o diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c new file mode 100644 index 0000000000..95120d6559 --- /dev/null +++ b/drivers/clk/imx/clk-composite-8m.c @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <clk-uclass.h> +#include <dm/device.h> +#include <linux/clk-provider.h> +#include <clk.h> +#include "clk.h" + +#define UBOOT_DM_CLK_IMX_COMPOSITE "imx_clk_composite" + +#define PCG_PREDIV_SHIFT 16 +#define PCG_PREDIV_WIDTH 3 +#define PCG_PREDIV_MAX 8 + +#define PCG_DIV_SHIFT 0 +#define PCG_DIV_WIDTH 6 +#define PCG_DIV_MAX 64 + +#define PCG_PCS_SHIFT 24 +#define PCG_PCS_MASK 0x7 + +#define PCG_CGC_SHIFT 28 + +static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk *clk) +{ + struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk); + struct clk_composite *composite = (struct clk_composite *)clk->data; + ulong parent_rate = clk_get_parent_rate(&composite->clk); + unsigned long prediv_rate; + unsigned int prediv_value; + unsigned int div_value; + + debug("%s: name %s prate: %lu reg: %p\n", __func__, + (&composite->clk)->dev->name, parent_rate, divider->reg); + prediv_value = readl(divider->reg) >> divider->shift; + prediv_value &= clk_div_mask(divider->width); + + prediv_rate = divider_recalc_rate(clk, parent_rate, prediv_value, + NULL, divider->flags, + divider->width); + + div_value = readl(divider->reg) >> PCG_DIV_SHIFT; + div_value &= clk_div_mask(PCG_DIV_WIDTH); + + return divider_recalc_rate(clk, prediv_rate, div_value, NULL, + divider->flags, PCG_DIV_WIDTH); +} + +static int imx8m_clk_composite_compute_dividers(unsigned long rate, + unsigned long parent_rate, + int *prediv, int *postdiv) +{ + int div1, div2; + int error = INT_MAX; + int ret = -EINVAL; + + *prediv = 1; + *postdiv = 1; + + for (div1 = 1; div1 <= PCG_PREDIV_MAX; div1++) { + for (div2 = 1; div2 <= PCG_DIV_MAX; div2++) { + int new_error = ((parent_rate / div1) / div2) - rate; + + if (abs(new_error) < abs(error)) { + *prediv = div1; + *postdiv = div2; + error = new_error; + ret = 0; + } + } + } + return ret; +} + +/* + * The clk are bound to a dev, because it is part of composite clk + * use composite clk to get dev + */ +static ulong imx8m_clk_composite_divider_set_rate(struct clk *clk, + unsigned long rate) +{ + struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk); + struct clk_composite *composite = (struct clk_composite *)clk->data; + ulong parent_rate = clk_get_parent_rate(&composite->clk); + int prediv_value; + int div_value; + int ret; + u32 val; + + ret = imx8m_clk_composite_compute_dividers(rate, parent_rate, + &prediv_value, &div_value); + if (ret) + return ret; + + val = readl(divider->reg); + val &= ~((clk_div_mask(divider->width) << divider->shift) | + (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT)); + + val |= (u32)(prediv_value - 1) << divider->shift; + val |= (u32)(div_value - 1) << PCG_DIV_SHIFT; + writel(val, divider->reg); + + return clk_get_rate(&composite->clk); +} + +static const struct clk_ops imx8m_clk_composite_divider_ops = { + .get_rate = imx8m_clk_composite_divider_recalc_rate, + .set_rate = imx8m_clk_composite_divider_set_rate, +}; + +struct clk *imx8m_clk_composite_flags(const char *name, + const char * const *parent_names, + int num_parents, void __iomem *reg, + unsigned long flags) +{ + struct clk *clk = ERR_PTR(-ENOMEM); + struct clk_divider *div = NULL; + struct clk_gate *gate = NULL; + struct clk_mux *mux = NULL; + + mux = kzalloc(sizeof(*mux), GFP_KERNEL); + if (!mux) + goto fail; + + mux->reg = reg; + mux->shift = PCG_PCS_SHIFT; + mux->mask = PCG_PCS_MASK; + mux->num_parents = num_parents; + mux->flags = flags; + mux->parent_names = parent_names; + + div = kzalloc(sizeof(*div), GFP_KERNEL); + if (!div) + goto fail; + + div->reg = reg; + div->shift = PCG_PREDIV_SHIFT; + div->width = PCG_PREDIV_WIDTH; + div->flags = CLK_DIVIDER_ROUND_CLOSEST | flags; + + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + goto fail; + + gate->reg = reg; + gate->bit_idx = PCG_CGC_SHIFT; + gate->flags = flags; + + clk = clk_register_composite(NULL, name, + parent_names, num_parents, + &mux->clk, &clk_mux_ops, &div->clk, + &imx8m_clk_composite_divider_ops, + &gate->clk, &clk_gate_ops, flags); + if (IS_ERR(clk)) + goto fail; + + return clk; + +fail: + kfree(gate); + kfree(div); + kfree(mux); + return ERR_CAST(clk); +} diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c new file mode 100644 index 0000000000..f4913e70ab --- /dev/null +++ b/drivers/clk/imx/clk-imx8mm.c @@ -0,0 +1,415 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 NXP + * Peng Fan <peng.fan@nxp.com> + */ + +#include <common.h> +#include <clk.h> +#include <clk-uclass.h> +#include <dm.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <dt-bindings/clock/imx8mm-clock.h> + +#include "clk.h" + +#define PLL_1416X_RATE(_rate, _m, _p, _s) \ + { \ + .rate = (_rate), \ + .mdiv = (_m), \ + .pdiv = (_p), \ + .sdiv = (_s), \ + } + +#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \ + { \ + .rate = (_rate), \ + .mdiv = (_m), \ + .pdiv = (_p), \ + .sdiv = (_s), \ + .kdiv = (_k), \ + } + +static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = { + PLL_1416X_RATE(1800000000U, 225, 3, 0), + PLL_1416X_RATE(1600000000U, 200, 3, 0), + PLL_1416X_RATE(1200000000U, 300, 3, 1), + PLL_1416X_RATE(1000000000U, 250, 3, 1), + PLL_1416X_RATE(800000000U, 200, 3, 1), + PLL_1416X_RATE(750000000U, 250, 2, 2), + PLL_1416X_RATE(700000000U, 350, 3, 2), + PLL_1416X_RATE(600000000U, 300, 3, 2), +}; + +static const struct imx_pll14xx_rate_table imx8mm_drampll_tbl[] = { + PLL_1443X_RATE(650000000U, 325, 3, 2, 0), +}; + +static struct imx_pll14xx_clk imx8mm_dram_pll __initdata = { + .type = PLL_1443X, + .rate_table = imx8mm_drampll_tbl, + .rate_count = ARRAY_SIZE(imx8mm_drampll_tbl), +}; + +static struct imx_pll14xx_clk imx8mm_arm_pll __initdata = { + .type = PLL_1416X, + .rate_table = imx8mm_pll1416x_tbl, + .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl), +}; + +static struct imx_pll14xx_clk imx8mm_sys_pll __initdata = { + .type = PLL_1416X, + .rate_table = imx8mm_pll1416x_tbl, + .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl), +}; + +static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", }; +static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", }; +static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; +static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", }; +static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", }; +static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", }; + +static const char *imx8mm_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m", + "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", }; + +static const char *imx8mm_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m", + "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", }; + +static const char *imx8mm_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m", + "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", }; + +static const char *imx8mm_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m", + "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", }; + +static const char *imx8mm_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", + "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", }; + +static const char *imx8mm_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", + "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", }; + +static const char *imx8mm_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; + +static const char *imx8mm_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; + +static const char *imx8mm_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; + +static const char *imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; + +static const char *imx8mm_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out", + "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", }; + +static const char *imx8mm_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", + "sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", }; + +static ulong imx8mm_clk_get_rate(struct clk *clk) +{ + struct clk *c; + int ret; + + debug("%s(#%lu)\n", __func__, clk->id); + + ret = clk_get_by_id(clk->id, &c); + if (ret) + return ret; + + return clk_get_rate(c); +} + +static ulong imx8mm_clk_set_rate(struct clk *clk, unsigned long rate) +{ + struct clk *c; + int ret; + + debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate); + + ret = clk_get_by_id(clk->id, &c); + if (ret) + return ret; + + return clk_set_rate(c, rate); +} + +static int __imx8mm_clk_enable(struct clk *clk, bool enable) +{ + struct clk *c; + int ret; + + debug("%s(#%lu) en: %d\n", __func__, clk->id, enable); + + ret = clk_get_by_id(clk->id, &c); + if (ret) + return ret; + + if (enable) + ret = clk_enable(c); + else + ret = clk_disable(c); + + return ret; +} + +static int imx8mm_clk_disable(struct clk *clk) +{ + return __imx8mm_clk_enable(clk, 0); +} + +static int imx8mm_clk_enable(struct clk *clk) +{ + return __imx8mm_clk_enable(clk, 1); +} + +static struct clk_ops imx8mm_clk_ops = { + .set_rate = imx8mm_clk_set_rate, + .get_rate = imx8mm_clk_get_rate, + .enable = imx8mm_clk_enable, + .disable = imx8mm_clk_disable, +}; + +static int imx8mm_clk_probe(struct udevice *dev) +{ + void __iomem *base; + + base = (void *)ANATOP_BASE_ADDR; + + clk_dm(IMX8MM_DRAM_PLL_REF_SEL, + imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); + clk_dm(IMX8MM_ARM_PLL_REF_SEL, + imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); + clk_dm(IMX8MM_SYS_PLL1_REF_SEL, + imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); + clk_dm(IMX8MM_SYS_PLL2_REF_SEL, + imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); + clk_dm(IMX8MM_SYS_PLL3_REF_SEL, + imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); + + clk_dm(IMX8MM_DRAM_PLL, + imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", + base + 0x50, &imx8mm_dram_pll)); + clk_dm(IMX8MM_ARM_PLL, + imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", + base + 0x84, &imx8mm_arm_pll)); + clk_dm(IMX8MM_SYS_PLL1, + imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel", + base + 0x94, &imx8mm_sys_pll)); + clk_dm(IMX8MM_SYS_PLL2, + imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel", + base + 0x104, &imx8mm_sys_pll)); + clk_dm(IMX8MM_SYS_PLL3, + imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", + base + 0x114, &imx8mm_sys_pll)); + + /* PLL bypass out */ + clk_dm(IMX8MM_DRAM_PLL_BYPASS, + imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1, + dram_pll_bypass_sels, + ARRAY_SIZE(dram_pll_bypass_sels), + CLK_SET_RATE_PARENT)); + clk_dm(IMX8MM_ARM_PLL_BYPASS, + imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1, + arm_pll_bypass_sels, + ARRAY_SIZE(arm_pll_bypass_sels), + CLK_SET_RATE_PARENT)); + clk_dm(IMX8MM_SYS_PLL1_BYPASS, + imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1, + sys_pll1_bypass_sels, + ARRAY_SIZE(sys_pll1_bypass_sels), + CLK_SET_RATE_PARENT)); + clk_dm(IMX8MM_SYS_PLL2_BYPASS, + imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1, + sys_pll2_bypass_sels, + ARRAY_SIZE(sys_pll2_bypass_sels), + CLK_SET_RATE_PARENT)); + clk_dm(IMX8MM_SYS_PLL3_BYPASS, + imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1, + sys_pll3_bypass_sels, + ARRAY_SIZE(sys_pll3_bypass_sels), + CLK_SET_RATE_PARENT)); + + /* PLL out gate */ + clk_dm(IMX8MM_DRAM_PLL_OUT, + imx_clk_gate("dram_pll_out", "dram_pll_bypass", + base + 0x50, 13)); + clk_dm(IMX8MM_ARM_PLL_OUT, + imx_clk_gate("arm_pll_out", "arm_pll_bypass", + base + 0x84, 11)); + clk_dm(IMX8MM_SYS_PLL1_OUT, + imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", + base + 0x94, 11)); + clk_dm(IMX8MM_SYS_PLL2_OUT, + imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", + base + 0x104, 11)); + clk_dm(IMX8MM_SYS_PLL3_OUT, + imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", + base + 0x114, 11)); + + /* SYS PLL fixed output */ + clk_dm(IMX8MM_SYS_PLL1_40M, + imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20)); + clk_dm(IMX8MM_SYS_PLL1_80M, + imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10)); + clk_dm(IMX8MM_SYS_PLL1_100M, + imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8)); + clk_dm(IMX8MM_SYS_PLL1_133M, + imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6)); + clk_dm(IMX8MM_SYS_PLL1_160M, + imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5)); + clk_dm(IMX8MM_SYS_PLL1_200M, + imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4)); + clk_dm(IMX8MM_SYS_PLL1_266M, + imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3)); + clk_dm(IMX8MM_SYS_PLL1_400M, + imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2)); + clk_dm(IMX8MM_SYS_PLL1_800M, + imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1)); + + clk_dm(IMX8MM_SYS_PLL2_50M, + imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20)); + clk_dm(IMX8MM_SYS_PLL2_100M, + imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10)); + clk_dm(IMX8MM_SYS_PLL2_125M, + imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8)); + clk_dm(IMX8MM_SYS_PLL2_166M, + imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6)); + clk_dm(IMX8MM_SYS_PLL2_200M, + imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5)); + clk_dm(IMX8MM_SYS_PLL2_250M, + imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4)); + clk_dm(IMX8MM_SYS_PLL2_333M, + imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3)); + clk_dm(IMX8MM_SYS_PLL2_500M, + imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2)); + clk_dm(IMX8MM_SYS_PLL2_1000M, + imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1)); + + base = dev_read_addr_ptr(dev); + if (base == (void *)FDT_ADDR_T_NONE) + return -EINVAL; + + clk_dm(IMX8MM_CLK_A53_SRC, + imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, + imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels))); + clk_dm(IMX8MM_CLK_A53_CG, + imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28)); + clk_dm(IMX8MM_CLK_A53_DIV, + imx_clk_divider2("arm_a53_div", "arm_a53_cg", + base + 0x8000, 0, 3)); + + clk_dm(IMX8MM_CLK_AHB, + imx8m_clk_composite_critical("ahb", imx8mm_ahb_sels, + base + 0x9000)); + clk_dm(IMX8MM_CLK_IPG_ROOT, + imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1)); + + clk_dm(IMX8MM_CLK_ENET_AXI, + imx8m_clk_composite("enet_axi", imx8mm_enet_axi_sels, + base + 0x8880)); + clk_dm(IMX8MM_CLK_NAND_USDHC_BUS, + imx8m_clk_composite_critical("nand_usdhc_bus", + imx8mm_nand_usdhc_sels, + base + 0x8900)); + + /* IP */ + clk_dm(IMX8MM_CLK_USDHC1, + imx8m_clk_composite("usdhc1", imx8mm_usdhc1_sels, + base + 0xac00)); + clk_dm(IMX8MM_CLK_USDHC2, + imx8m_clk_composite("usdhc2", imx8mm_usdhc2_sels, + base + 0xac80)); + clk_dm(IMX8MM_CLK_I2C1, + imx8m_clk_composite("i2c1", imx8mm_i2c1_sels, base + 0xad00)); + clk_dm(IMX8MM_CLK_I2C2, + imx8m_clk_composite("i2c2", imx8mm_i2c2_sels, base + 0xad80)); + clk_dm(IMX8MM_CLK_I2C3, + imx8m_clk_composite("i2c3", imx8mm_i2c3_sels, base + 0xae00)); + clk_dm(IMX8MM_CLK_I2C4, + imx8m_clk_composite("i2c4", imx8mm_i2c4_sels, base + 0xae80)); + clk_dm(IMX8MM_CLK_WDOG, + imx8m_clk_composite("wdog", imx8mm_wdog_sels, base + 0xb900)); + clk_dm(IMX8MM_CLK_USDHC3, + imx8m_clk_composite("usdhc3", imx8mm_usdhc3_sels, + base + 0xbc80)); + + clk_dm(IMX8MM_CLK_I2C1_ROOT, + imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0)); + clk_dm(IMX8MM_CLK_I2C2_ROOT, + imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0)); + clk_dm(IMX8MM_CLK_I2C3_ROOT, + imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0)); + clk_dm(IMX8MM_CLK_I2C4_ROOT, + imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0)); + clk_dm(IMX8MM_CLK_OCOTP_ROOT, + imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0)); + clk_dm(IMX8MM_CLK_USDHC1_ROOT, + imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); + clk_dm(IMX8MM_CLK_USDHC2_ROOT, + imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0)); + clk_dm(IMX8MM_CLK_WDOG1_ROOT, + imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0)); + clk_dm(IMX8MM_CLK_WDOG2_ROOT, + imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0)); + clk_dm(IMX8MM_CLK_WDOG3_ROOT, + imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0)); + clk_dm(IMX8MM_CLK_USDHC3_ROOT, + imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0)); + +#ifdef CONFIG_SPL_BUILD + struct clk *clkp, *clkp1; + + clk_get_by_id(IMX8MM_CLK_WDOG1_ROOT, &clkp); + clk_enable(clkp); + clk_get_by_id(IMX8MM_CLK_WDOG2_ROOT, &clkp); + clk_enable(clkp); + clk_get_by_id(IMX8MM_CLK_WDOG3_ROOT, &clkp); + clk_enable(clkp); + + /* Configure SYS_PLL3 to 750MHz */ + clk_get_by_id(IMX8MM_SYS_PLL3, &clkp); + clk_set_rate(clkp, 750000000UL); + clk_enable(clkp); + + /* Configure ARM to sys_pll2_500m */ + clk_get_by_id(IMX8MM_CLK_A53_SRC, &clkp); + clk_get_by_id(IMX8MM_SYS_PLL2_OUT, &clkp1); + clk_enable(clkp1); + clk_get_by_id(IMX8MM_SYS_PLL2_500M, &clkp1); + clk_set_parent(clkp, clkp1); + + /* Configure ARM PLL to 1.2GHz */ + clk_get_by_id(IMX8MM_ARM_PLL, &clkp1); + clk_set_rate(clkp1, 1200000000UL); + clk_get_by_id(IMX8MM_ARM_PLL_OUT, &clkp1); + clk_enable(clkp1); + clk_set_parent(clkp, clkp1); + + /* Configure DIV to 1.2GHz */ + clk_get_by_id(IMX8MM_CLK_A53_DIV, &clkp1); + clk_set_rate(clkp1, 1200000000UL); +#endif + + return 0; +} + +static const struct udevice_id imx8mm_clk_ids[] = { + { .compatible = "fsl,imx8mm-ccm" }, + { }, +}; + +U_BOOT_DRIVER(imx8mm_clk) = { + .name = "clk_imx8mm", + .id = UCLASS_CLK, + .of_match = imx8mm_clk_ids, + .ops = &imx8mm_clk_ops, + .probe = imx8mm_clk_probe, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c new file mode 100644 index 0000000000..2246beb21b --- /dev/null +++ b/drivers/clk/imx/clk-pll14xx.c @@ -0,0 +1,381 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2017-2019 NXP. + * + * Peng Fan <peng.fan@nxp.com> + */ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <clk-uclass.h> +#include <dm/device.h> +#include <linux/clk-provider.h> +#include <linux/iopoll.h> +#include <clk.h> +#include <div64.h> + +#include "clk.h" + +#define UBOOT_DM_CLK_IMX_PLL1443X "imx_clk_pll1443x" +#define UBOOT_DM_CLK_IMX_PLL1416X "imx_clk_pll1416x" + +#define GNRL_CTL 0x0 +#define DIV_CTL 0x4 +#define LOCK_STATUS BIT(31) +#define LOCK_SEL_MASK BIT(29) +#define CLKE_MASK BIT(11) +#define RST_MASK BIT(9) +#define BYPASS_MASK BIT(4) +#define MDIV_SHIFT 12 +#define MDIV_MASK GENMASK(21, 12) +#define PDIV_SHIFT 4 +#define PDIV_MASK GENMASK(9, 4) +#define SDIV_SHIFT 0 +#define SDIV_MASK GENMASK(2, 0) +#define KDIV_SHIFT 0 +#define KDIV_MASK GENMASK(15, 0) + +#define LOCK_TIMEOUT_US 10000 + +struct clk_pll14xx { + struct clk clk; + void __iomem *base; + enum imx_pll14xx_type type; + const struct imx_pll14xx_rate_table *rate_table; + int rate_count; +}; + +#define to_clk_pll14xx(_clk) container_of(_clk, struct clk_pll14xx, clk) + +static const struct imx_pll14xx_rate_table *imx_get_pll_settings( + struct clk_pll14xx *pll, unsigned long rate) +{ + const struct imx_pll14xx_rate_table *rate_table = pll->rate_table; + int i; + + for (i = 0; i < pll->rate_count; i++) + if (rate == rate_table[i].rate) + return &rate_table[i]; + + return NULL; +} + +static unsigned long clk_pll1416x_recalc_rate(struct clk *clk) +{ + struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev)); + u64 fvco = clk_get_parent_rate(clk); + u32 mdiv, pdiv, sdiv, pll_div; + + pll_div = readl(pll->base + 4); + mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; + pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT; + sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; + + fvco *= mdiv; + do_div(fvco, pdiv << sdiv); + + return fvco; +} + +static unsigned long clk_pll1443x_recalc_rate(struct clk *clk) +{ + struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev)); + u64 fvco = clk_get_parent_rate(clk); + u32 mdiv, pdiv, sdiv, pll_div_ctl0, pll_div_ctl1; + short int kdiv; + + pll_div_ctl0 = readl(pll->base + 4); + pll_div_ctl1 = readl(pll->base + 8); + mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; + pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT; + sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; + kdiv = pll_div_ctl1 & KDIV_MASK; + + /* fvco = (m * 65536 + k) * Fin / (p * 65536) */ + fvco *= (mdiv * 65536 + kdiv); + pdiv *= 65536; + + do_div(fvco, pdiv << sdiv); + + return fvco; +} + +static inline bool clk_pll1416x_mp_change(const struct imx_pll14xx_rate_table *rate, + u32 pll_div) +{ + u32 old_mdiv, old_pdiv; + + old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; + old_pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT; + + return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv; +} + +static inline bool clk_pll1443x_mpk_change(const struct imx_pll14xx_rate_table *rate, + u32 pll_div_ctl0, u32 pll_div_ctl1) +{ + u32 old_mdiv, old_pdiv, old_kdiv; + + old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; + old_pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT; + old_kdiv = (pll_div_ctl1 & KDIV_MASK) >> KDIV_SHIFT; + + return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv || + rate->kdiv != old_kdiv; +} + +static inline bool clk_pll1443x_mp_change(const struct imx_pll14xx_rate_table *rate, + u32 pll_div_ctl0, u32 pll_div_ctl1) +{ + u32 old_mdiv, old_pdiv, old_kdiv; + + old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; + old_pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT; + old_kdiv = (pll_div_ctl1 & KDIV_MASK) >> KDIV_SHIFT; + + return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv || + rate->kdiv != old_kdiv; +} + +static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll) +{ + u32 val; + + return readl_poll_timeout(pll->base, val, val & LOCK_TIMEOUT_US, + LOCK_TIMEOUT_US); +} + +static ulong clk_pll1416x_set_rate(struct clk *clk, unsigned long drate) +{ + struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev)); + const struct imx_pll14xx_rate_table *rate; + u32 tmp, div_val; + int ret; + + rate = imx_get_pll_settings(pll, drate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, + drate, "xxxx"); + return -EINVAL; + } + + tmp = readl(pll->base + 4); + + if (!clk_pll1416x_mp_change(rate, tmp)) { + tmp &= ~(SDIV_MASK) << SDIV_SHIFT; + tmp |= rate->sdiv << SDIV_SHIFT; + writel(tmp, pll->base + 4); + + return clk_pll1416x_recalc_rate(clk); + } + + /* Bypass clock and set lock to pll output lock */ + tmp = readl(pll->base); + tmp |= LOCK_SEL_MASK; + writel(tmp, pll->base); + + /* Enable RST */ + tmp &= ~RST_MASK; + writel(tmp, pll->base); + + /* Enable BYPASS */ + tmp |= BYPASS_MASK; + writel(tmp, pll->base); + + + div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | + (rate->sdiv << SDIV_SHIFT); + writel(div_val, pll->base + 0x4); + + /* + * According to SPEC, t3 - t2 need to be greater than + * 1us and 1/FREF, respectively. + * FREF is FIN / Prediv, the prediv is [1, 63], so choose + * 3us. + */ + udelay(3); + + /* Disable RST */ + tmp |= RST_MASK; + writel(tmp, pll->base); + + /* Wait Lock */ + ret = clk_pll14xx_wait_lock(pll); + if (ret) + return ret; + + /* Bypass */ + tmp &= ~BYPASS_MASK; + writel(tmp, pll->base); + + return clk_pll1416x_recalc_rate(clk); +} + +static ulong clk_pll1443x_set_rate(struct clk *clk, unsigned long drate) +{ + struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev)); + const struct imx_pll14xx_rate_table *rate; + u32 tmp, div_val; + int ret; + + rate = imx_get_pll_settings(pll, drate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, + drate, "==="); + return -EINVAL; + } + + tmp = readl(pll->base + 4); + div_val = readl(pll->base + 8); + + if (!clk_pll1443x_mpk_change(rate, tmp, div_val)) { + tmp &= ~(SDIV_MASK) << SDIV_SHIFT; + tmp |= rate->sdiv << SDIV_SHIFT; + writel(tmp, pll->base + 4); + + return clk_pll1443x_recalc_rate(clk); + } + + tmp = readl(pll->base); + + /* Enable RST */ + tmp &= ~RST_MASK; + writel(tmp, pll->base); + + /* Enable BYPASS */ + tmp |= BYPASS_MASK; + writel(tmp, pll->base); + + div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | + (rate->sdiv << SDIV_SHIFT); + writel(div_val, pll->base + 0x4); + writel(rate->kdiv << KDIV_SHIFT, pll->base + 0x8); + + /* + * According to SPEC, t3 - t2 need to be greater than + * 1us and 1/FREF, respectively. + * FREF is FIN / Prediv, the prediv is [1, 63], so choose + * 3us. + */ + udelay(3); + + /* Disable RST */ + tmp |= RST_MASK; + writel(tmp, pll->base); + + /* Wait Lock*/ + ret = clk_pll14xx_wait_lock(pll); + if (ret) + return ret; + + /* Bypass */ + tmp &= ~BYPASS_MASK; + writel(tmp, pll->base); + + return clk_pll1443x_recalc_rate(clk); +} + +static int clk_pll14xx_prepare(struct clk *clk) +{ + struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev)); + u32 val; + + /* + * RESETB = 1 from 0, PLL starts its normal + * operation after lock time + */ + val = readl(pll->base + GNRL_CTL); + val |= RST_MASK; + writel(val, pll->base + GNRL_CTL); + + return clk_pll14xx_wait_lock(pll); +} + +static int clk_pll14xx_unprepare(struct clk *clk) +{ + struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev)); + u32 val; + + /* + * Set RST to 0, power down mode is enabled and + * every digital block is reset + */ + val = readl(pll->base + GNRL_CTL); + val &= ~RST_MASK; + writel(val, pll->base + GNRL_CTL); + + return 0; +} + +static const struct clk_ops clk_pll1416x_ops = { + .enable = clk_pll14xx_prepare, + .disable = clk_pll14xx_unprepare, + .set_rate = clk_pll1416x_set_rate, + .get_rate = clk_pll1416x_recalc_rate, +}; + +static const struct clk_ops clk_pll1443x_ops = { + .enable = clk_pll14xx_prepare, + .disable = clk_pll14xx_unprepare, + .set_rate = clk_pll1443x_set_rate, + .get_rate = clk_pll1443x_recalc_rate, +}; + +struct clk *imx_clk_pll14xx(const char *name, const char *parent_name, + void __iomem *base, + const struct imx_pll14xx_clk *pll_clk) +{ + struct clk_pll14xx *pll; + struct clk *clk; + char *type_name; + int ret; + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + switch (pll_clk->type) { + case PLL_1416X: + type_name = UBOOT_DM_CLK_IMX_PLL1416X; + break; + case PLL_1443X: + type_name = UBOOT_DM_CLK_IMX_PLL1443X; + break; + default: + pr_err("%s: Unknown pll type for pll clk %s\n", + __func__, name); + return ERR_PTR(-EINVAL); + }; + + pll->base = base; + pll->type = pll_clk->type; + pll->rate_table = pll_clk->rate_table; + pll->rate_count = pll_clk->rate_count; + + clk = &pll->clk; + + ret = clk_register(clk, type_name, name, parent_name); + if (ret) { + pr_err("%s: failed to register pll %s %d\n", + __func__, name, ret); + kfree(pll); + return ERR_PTR(ret); + } + + return clk; +} + +U_BOOT_DRIVER(clk_pll1443x) = { + .name = UBOOT_DM_CLK_IMX_PLL1443X, + .id = UCLASS_CLK, + .ops = &clk_pll1443x_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(clk_pll1416x) = { + .name = UBOOT_DM_CLK_IMX_PLL1416X, + .id = UCLASS_CLK, + .ops = &clk_pll1416x_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 1d480d8722..4956e04a92 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -20,6 +20,31 @@ enum imx_pllv3_type { IMX_PLLV3_DDR_IMX7, }; +enum imx_pll14xx_type { + PLL_1416X, + PLL_1443X, +}; + +/* NOTE: Rate table should be kept sorted in descending order. */ +struct imx_pll14xx_rate_table { + unsigned int rate; + unsigned int pdiv; + unsigned int mdiv; + unsigned int sdiv; + unsigned int kdiv; +}; + +struct imx_pll14xx_clk { + enum imx_pll14xx_type type; + const struct imx_pll14xx_rate_table *rate_table; + int rate_count; + int flags; +}; + +struct clk *imx_clk_pll14xx(const char *name, const char *parent_name, + void __iomem *base, + const struct imx_pll14xx_clk *pll_clk); + struct clk *clk_register_gate2(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 cgr_val, diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index 112326e553..43dac1aa37 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -405,6 +405,7 @@ static struct clk_ops meson_clk_ops = { static const struct udevice_id meson_clk_ids[] = { { .compatible = "amlogic,g12a-clkc" }, + { .compatible = "amlogic,g12b-clkc" }, { } }; diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index a89e2ecc4a..5957a00402 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -745,10 +745,22 @@ static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent) return -ENOENT; } +static int rk3328_clk_enable(struct clk *clk) +{ + switch (clk->id) { + case HCLK_HOST0: + /* Required to successfully probe the ehci generic driver */ + return 0; + } + + return -ENOENT; +} + static struct clk_ops rk3328_clk_ops = { .get_rate = rk3328_clk_get_rate, .set_rate = rk3328_clk_set_rate, .set_parent = rk3328_clk_set_parent, + .enable = rk3328_clk_enable, }; static int rk3328_clk_probe(struct udevice *dev) diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index 2d195ae35e..3b95b5387b 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -92,7 +92,7 @@ config DM_SEQ_ALIAS config SPL_DM_SEQ_ALIAS bool "Support numbered aliases in device tree in SPL" - depends on DM + depends on SPL_DM default n help Most boards will have a '/aliases' node containing the path to diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index e1f69a1d25..0aa6aedae7 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -10,6 +10,7 @@ */ #include <common.h> +#include <dm.h> #include <i2c.h> #include <fsl_ddr_sdram.h> #include <fsl_ddr.h> @@ -82,17 +83,82 @@ u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = { #endif +#if defined(CONFIG_DM_I2C) +#define DEV_TYPE struct udevice +#else +/* Local udevice */ +struct ludevice { + u8 chip; +}; + +#define DEV_TYPE struct ludevice + +#endif + #define SPD_SPA0_ADDRESS 0x36 #define SPD_SPA1_ADDRESS 0x37 -static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) +static int ddr_i2c_read(DEV_TYPE *dev, unsigned int addr, + int alen, uint8_t *buf, int len) { int ret; + +#ifdef CONFIG_DM_I2C + ret = dm_i2c_read(dev, 0, buf, len); +#else + ret = i2c_read(dev->chip, addr, alen, buf, len); +#endif + + return ret; +} + #ifdef CONFIG_SYS_FSL_DDR4 - uint8_t dummy = 0; +static int ddr_i2c_dummy_write(unsigned int chip_addr) +{ + uint8_t buf = 0; + +#ifdef CONFIG_DM_I2C + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(CONFIG_SYS_SPD_BUS_NUM, chip_addr, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + CONFIG_SYS_SPD_BUS_NUM); + return ret; + } + + return dm_i2c_write(dev, 0, &buf, 1); +#else + return i2c_write(chip_addr, 0, 1, &buf, 1); #endif + return 0; +} +#endif + +static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) +{ + int ret; + DEV_TYPE *dev; + +#if defined(CONFIG_DM_I2C) + ret = i2c_get_chip_for_busnum(CONFIG_SYS_SPD_BUS_NUM, i2c_address, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + CONFIG_SYS_SPD_BUS_NUM); + return; + } +#else /* Non DM I2C support - will be removed */ + struct ludevice ldev = { + .chip = i2c_address, + }; + dev = &ldev; + i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM); +#endif #ifdef CONFIG_SYS_FSL_DDR4 /* @@ -101,18 +167,19 @@ static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) * To access the upper 256 bytes, we need to set EE page address to 1 * See Jedec standar No. 21-C for detail */ - i2c_write(SPD_SPA0_ADDRESS, 0, 1, &dummy, 1); - ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, 256); + ddr_i2c_dummy_write(SPD_SPA0_ADDRESS); + ret = ddr_i2c_read(dev, 0, 1, (uchar *)spd, 256); if (!ret) { - i2c_write(SPD_SPA1_ADDRESS, 0, 1, &dummy, 1); - ret = i2c_read(i2c_address, 0, 1, - (uchar *)((ulong)spd + 256), - min(256, - (int)sizeof(generic_spd_eeprom_t) - 256)); + ddr_i2c_dummy_write(SPD_SPA1_ADDRESS); + ret = ddr_i2c_read(dev, 0, 1, (uchar *)((ulong)spd + 256), + min(256, + (int)sizeof(generic_spd_eeprom_t) + - 256)); } + #else - ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, - sizeof(generic_spd_eeprom_t)); + ret = ddr_i2c_read(dev, 0, 1, (uchar *)spd, + sizeof(generic_spd_eeprom_t)); #endif if (ret) { diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 7d9c97f537..f2dabb554f 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -139,6 +139,11 @@ config MXC_GPIO help Support GPIO controllers on various i.MX platforms +config MXS_GPIO + bool "Freescale/NXP MXS GPIO driver" + help + Support GPIO controllers on i.MX23 and i.MX28 platforms + config OMAP_GPIO bool "TI OMAP GPIO driver" depends on ARCH_OMAP2PLUS diff --git a/drivers/i2c/muxes/i2c-mux-gpio.c b/drivers/i2c/muxes/i2c-mux-gpio.c index 28f640042f..e8b124f4f5 100644 --- a/drivers/i2c/muxes/i2c-mux-gpio.c +++ b/drivers/i2c/muxes/i2c-mux-gpio.c @@ -106,7 +106,7 @@ static int i2c_mux_gpio_probe(struct udevice *dev) } ret = gpio_request_list_by_name(dev, "mux-gpios", gpios, mux->n_gpios, - GPIOD_IS_OUT_ACTIVE); + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); if (ret <= 0) { dev_err(dev, "Failed to request mux-gpios\n"); return ret; diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 23119cce65..20f6dc4ecb 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -558,6 +558,14 @@ static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf, return 0; } +int __enable_i2c_clk(unsigned char enable, unsigned int i2c_num) +{ + return 1; +} + +int enable_i2c_clk(unsigned char enable, unsigned int i2c_num) + __attribute__((weak, alias("__enable_i2c_clk"))); + #ifndef CONFIG_DM_I2C /* * Read data from I2C device @@ -723,13 +731,6 @@ static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip) return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0); } -int __enable_i2c_clk(unsigned char enable, unsigned i2c_num) -{ - return 1; -} -int enable_i2c_clk(unsigned char enable, unsigned i2c_num) - __attribute__((weak, alias("__enable_i2c_clk"))); - void bus_i2c_init(int index, int speed, int unused, int (*idle_bus_fn)(void *p), void *idle_bus_data) { @@ -916,13 +917,6 @@ static int mxc_i2c_probe(struct udevice *bus) } } - ret = i2c_idle_bus(i2c_bus); - if (ret < 0) { - /* Disable clk */ - enable_i2c_clk(0, bus->seq); - return ret; - } - /* * Pinmux settings are in board file now, until pinmux is supported, * we can set pinmux here in probe function. diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index cb8b5c04db..8037b6ee2d 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -88,6 +88,7 @@ config CROS_EC config SPL_CROS_EC bool "Enable Chrome OS EC in SPL" + depends on SPL help Enable access to the Chrome OS EC in SPL. This is a separate microcontroller typically available on a SPI bus on Chromebooks. It @@ -97,6 +98,7 @@ config SPL_CROS_EC config TPL_CROS_EC bool "Enable Chrome OS EC in TPL" + depends on TPL help Enable access to the Chrome OS EC in TPL. This is a separate microcontroller typically available on a SPI bus on Chromebooks. It diff --git a/drivers/misc/i2c_eeprom.c b/drivers/misc/i2c_eeprom.c index f25d054007..8f2349ad5a 100644 --- a/drivers/misc/i2c_eeprom.c +++ b/drivers/misc/i2c_eeprom.c @@ -84,6 +84,14 @@ static int i2c_eeprom_std_ofdata_to_platdata(struct udevice *dev) static int i2c_eeprom_std_probe(struct udevice *dev) { + u8 test_byte; + int ret; + + /* Verify that the chip is functional */ + ret = i2c_eeprom_read(dev, 0, &test_byte, 1); + if (ret) + return -ENODEV; + return 0; } diff --git a/drivers/misc/stm32_rcc.c b/drivers/misc/stm32_rcc.c index 13d70696f6..e7efcdeafa 100644 --- a/drivers/misc/stm32_rcc.c +++ b/drivers/misc/stm32_rcc.c @@ -68,8 +68,6 @@ static int stm32_rcc_bind(struct udevice *dev) dev_ofnode(dev), &child); } -static const struct misc_ops stm32_rcc_ops = { -}; static const struct udevice_id stm32_rcc_ids[] = { {.compatible = "st,stm32f42xx-rcc", .data = (ulong)&stm32_rcc_clk_f42x }, @@ -82,8 +80,7 @@ static const struct udevice_id stm32_rcc_ids[] = { U_BOOT_DRIVER(stm32_rcc) = { .name = "stm32-rcc", - .id = UCLASS_MISC, + .id = UCLASS_NOP, .of_match = stm32_rcc_ids, .bind = stm32_rcc_bind, - .ops = &stm32_rcc_ops, }; diff --git a/drivers/misc/stm32mp_fuse.c b/drivers/misc/stm32mp_fuse.c index 801d946b77..0eed345973 100644 --- a/drivers/misc/stm32mp_fuse.c +++ b/drivers/misc/stm32mp_fuse.c @@ -20,7 +20,7 @@ */ int fuse_read(u32 bank, u32 word, u32 *val) { - int ret = 0; + int ret; struct udevice *dev; switch (bank) { @@ -32,15 +32,25 @@ int fuse_read(u32 bank, u32 word, u32 *val) return ret; ret = misc_read(dev, word * 4 + STM32_BSEC_SHADOW_OFFSET, val, 4); - if (ret < 0) - return ret; - ret = 0; + if (ret != 4) + ret = -EINVAL; + else + ret = 0; break; #ifdef CONFIG_PMIC_STPMIC1 case STM32MP_NVM_BANK: + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(stpmic1_nvm), + &dev); + if (ret) + return ret; *val = 0; - ret = stpmic1_shadow_read_byte(word, (u8 *)val); + ret = misc_read(dev, -word, val, 1); + if (ret != 1) + ret = -EINVAL; + else + ret = 0; break; #endif /* CONFIG_PMIC_STPMIC1 */ @@ -67,14 +77,24 @@ int fuse_prog(u32 bank, u32 word, u32 val) return ret; ret = misc_write(dev, word * 4 + STM32_BSEC_OTP_OFFSET, &val, 4); - if (ret < 0) - return ret; - ret = 0; + if (ret != 4) + ret = -EINVAL; + else + ret = 0; break; #ifdef CONFIG_PMIC_STPMIC1 case STM32MP_NVM_BANK: - ret = stpmic1_nvm_write_byte(word, (u8 *)&val); + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(stpmic1_nvm), + &dev); + if (ret) + return ret; + ret = misc_write(dev, word, &val, 1); + if (ret != 1) + ret = -EINVAL; + else + ret = 0; break; #endif /* CONFIG_PMIC_STPMIC1 */ @@ -100,15 +120,25 @@ int fuse_sense(u32 bank, u32 word, u32 *val) if (ret) return ret; ret = misc_read(dev, word * 4 + STM32_BSEC_OTP_OFFSET, val, 4); - if (ret < 0) - return ret; - ret = 0; + if (ret != 4) + ret = -EINVAL; + else + ret = 0; break; #ifdef CONFIG_PMIC_STPMIC1 case STM32MP_NVM_BANK: + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(stpmic1_nvm), + &dev); + if (ret) + return ret; *val = 0; - ret = stpmic1_nvm_read_byte(word, (u8 *)val); + ret = misc_read(dev, word, val, 1); + if (ret != 1) + ret = -EINVAL; + else + ret = 0; break; #endif /* CONFIG_PMIC_STPMIC1 */ @@ -135,14 +165,24 @@ int fuse_override(u32 bank, u32 word, u32 val) return ret; ret = misc_write(dev, word * 4 + STM32_BSEC_SHADOW_OFFSET, &val, 4); - if (ret < 0) - return ret; - ret = 0; + if (ret != 4) + ret = -EINVAL; + else + ret = 0; break; #ifdef CONFIG_PMIC_STPMIC1 case STM32MP_NVM_BANK: - ret = stpmic1_shadow_write_byte(word, (u8 *)&val); + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(stpmic1_nvm), + &dev); + if (ret) + return ret; + ret = misc_write(dev, -word, &val, 1); + if (ret != 1) + ret = -EINVAL; + else + ret = 0; break; #endif /* CONFIG_PMIC_STPMIC1 */ diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index c6812f6517..0ccb1ea701 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -694,6 +694,13 @@ config FSL_ESDHC_IMX This selects support for the i.MX eSDHC (Enhanced Secure Digital Host Controller) found on numerous Freescale/NXP SoCs. +config FSL_USDHC + bool "Freescale/NXP i.MX uSDHC controller support" + depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || TARGET_S32V234EVB + select FSL_ESDHC_IMX + help + This enables the Ultra Secured Digital Host Controller enhancements + endmenu config SYS_FSL_ERRATUM_ESDHC111 diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c index 551007905c..2b146ea43c 100644 --- a/drivers/mmc/mmc-uclass.c +++ b/drivers/mmc/mmc-uclass.c @@ -360,6 +360,7 @@ static int mmc_select_hwpart(struct udevice *bdev, int hwpart) struct udevice *mmc_dev = dev_get_parent(bdev); struct mmc *mmc = mmc_get_mmc_dev(mmc_dev); struct blk_desc *desc = dev_get_uclass_platdata(bdev); + int ret; if (desc->hwpart == hwpart) return 0; @@ -367,7 +368,11 @@ static int mmc_select_hwpart(struct udevice *bdev, int hwpart) if (mmc->part_config == MMCPART_NOAVAILABLE) return -EMEDIUMTYPE; - return mmc_switch_part(mmc, hwpart); + ret = mmc_switch_part(mmc, hwpart); + if (!ret) + blkcache_invalidate(desc->if_type, desc->devnum); + + return ret; } static int mmc_blk_probe(struct udevice *dev) diff --git a/drivers/mmc/sti_sdhci.c b/drivers/mmc/sti_sdhci.c index 8ed47e113d..d6c75ea601 100644 --- a/drivers/mmc/sti_sdhci.c +++ b/drivers/mmc/sti_sdhci.c @@ -97,14 +97,14 @@ static int sti_sdhci_probe(struct udevice *dev) SDHCI_QUIRK_NO_HISPD_BIT; host->host_caps = MMC_MODE_DDR_52MHz; + host->mmc = &plat->mmc; + host->mmc->dev = dev; + host->mmc->priv = host; ret = sdhci_setup_cfg(&plat->cfg, host, 50000000, 400000); if (ret) return ret; - host->mmc = &plat->mmc; - host->mmc->priv = host; - host->mmc->dev = dev; upriv->mmc = host->mmc; return sdhci_probe(dev); diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c index 867ed569eb..32434a4762 100644 --- a/drivers/mmc/stm32_sdmmc2.c +++ b/drivers/mmc/stm32_sdmmc2.c @@ -14,6 +14,7 @@ #include <asm/io.h> #include <asm/gpio.h> #include <linux/iopoll.h> +#include <watchdog.h> struct stm32_sdmmc2_plat { struct mmc_config cfg; @@ -190,7 +191,7 @@ struct stm32_sdmmc2_ctx { #define SDMMC_IDMACTRL_IDMAEN BIT(0) #define SDMMC_CMD_TIMEOUT 0xFFFFFFFF -#define SDMMC_BUSYD0END_TIMEOUT_US 1000000 +#define SDMMC_BUSYD0END_TIMEOUT_US 2000000 static void stm32_sdmmc2_start_data(struct stm32_sdmmc2_priv *priv, struct mmc_data *data, @@ -432,6 +433,8 @@ static int stm32_sdmmc2_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, u32 cmdat = data ? SDMMC_CMD_CMDTRANS : 0; int ret, retry = 3; + WATCHDOG_RESET(); + retry_cmd: ctx.data_length = 0; ctx.dpsm_abort = false; diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index f86035bcce..a129f44869 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -15,6 +15,11 @@ config SYS_NAND_DRIVER_ECC_LAYOUT Omit standard ECC layouts to safe space. Select this if your driver is known to provide its own ECC layout. +config SYS_NAND_USE_FLASH_BBT + bool "Enable BBT (Bad Block Table) support" + help + Enable the BBT (Bad Block Table) usage. + config NAND_ATMEL bool "Support Atmel NAND controller" imply SYS_NAND_USE_FLASH_BBT diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index 1d96e4bdc2..c980ba4edb 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -282,6 +282,16 @@ static int mc_fixup_dpl_mac_addr(void *blob, int dpmac_id, MC_FIXUP_DPL); } +void fdt_fixup_mc_ddr(u64 *base, u64 *size) +{ + u64 mc_size = mc_get_dram_block_size(); + + if (mc_size < MC_DRAM_BLOCK_DEFAULT_SIZE) { + *base = mc_get_dram_addr() + mc_size; + *size = MC_DRAM_BLOCK_DEFAULT_SIZE - mc_size; + } +} + void fdt_fsl_mc_fixup_iommu_map_entry(void *blob) { u32 *prop; diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c index d4965e2ef6..47f101e280 100644 --- a/drivers/nvme/nvme.c +++ b/drivers/nvme/nvme.c @@ -73,6 +73,9 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2, u64 *prp_pool; int length = total_len; int i, nprps; + u32 prps_per_page = (page_size >> 3) - 1; + u32 num_pages; + length -= (page_size - offset); if (length <= 0) { @@ -89,15 +92,20 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2, } nprps = DIV_ROUND_UP(length, page_size); + num_pages = DIV_ROUND_UP(nprps, prps_per_page); if (nprps > dev->prp_entry_num) { free(dev->prp_pool); - dev->prp_pool = malloc(nprps << 3); + /* + * Always increase in increments of pages. It doesn't waste + * much memory and reduces the number of allocations. + */ + dev->prp_pool = memalign(page_size, num_pages * page_size); if (!dev->prp_pool) { printf("Error: malloc prp_pool fail\n"); return -ENOMEM; } - dev->prp_entry_num = nprps; + dev->prp_entry_num = prps_per_page * num_pages; } prp_pool = dev->prp_pool; @@ -788,14 +796,6 @@ static int nvme_probe(struct udevice *udev) } memset(ndev->queues, 0, NVME_Q_NUM * sizeof(struct nvme_queue *)); - ndev->prp_pool = malloc(MAX_PRP_POOL); - if (!ndev->prp_pool) { - ret = -ENOMEM; - printf("Error: %s: Out of memory!\n", udev->name); - goto free_nvme; - } - ndev->prp_entry_num = MAX_PRP_POOL >> 3; - ndev->cap = nvme_readq(&ndev->bar->cap); ndev->q_depth = min_t(int, NVME_CAP_MQES(ndev->cap) + 1, NVME_Q_DEPTH); ndev->db_stride = 1 << NVME_CAP_STRIDE(ndev->cap); @@ -805,6 +805,15 @@ static int nvme_probe(struct udevice *udev) if (ret) goto free_queue; + /* Allocate after the page size is known */ + ndev->prp_pool = memalign(ndev->page_size, MAX_PRP_POOL); + if (!ndev->prp_pool) { + ret = -ENOMEM; + printf("Error: %s: Out of memory!\n", udev->name); + goto free_nvme; + } + ndev->prp_entry_num = MAX_PRP_POOL >> 3; + ret = nvme_setup_io_queues(ndev); if (ret) goto free_queue; diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 4d61a46cef..ab25aeee73 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -299,8 +299,9 @@ static int fsl_pcie_setup_inbound_win(struct fsl_pcie *pcie, int idx, out_be32(&pi->piwbear, 0); #endif - if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A005434)) - flag = 0; +#ifdef CONFIG_SYS_FSL_ERRATUM_A005434 + flag = 0; +#endif flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; if (pf) @@ -401,47 +402,47 @@ static int fsl_pcie_init_port(struct fsl_pcie *pcie) fsl_pcie_init_atmu(pcie); - if (IS_ENABLED(CONFIG_FSL_PCIE_DISABLE_ASPM)) { - val_32 = 0; - fsl_pcie_hose_read_config_dword(pcie, PCI_LCR, &val_32); - val_32 &= ~0x03; - fsl_pcie_hose_write_config_dword(pcie, PCI_LCR, val_32); - udelay(1); - } +#ifdef CONFIG_FSL_PCIE_DISABLE_ASPM + val_32 = 0; + fsl_pcie_hose_read_config_dword(pcie, PCI_LCR, &val_32); + val_32 &= ~0x03; + fsl_pcie_hose_write_config_dword(pcie, PCI_LCR, val_32); + udelay(1); +#endif - if (IS_ENABLED(CONFIG_FSL_PCIE_RESET)) { - u16 ltssm; - int i; +#ifdef CONFIG_FSL_PCIE_RESET + u16 ltssm; + int i; - if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) { + if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) { + /* assert PCIe reset */ + setbits_be32(®s->pdb_stat, 0x08000000); + (void)in_be32(®s->pdb_stat); + udelay(1000); + /* clear PCIe reset */ + clrbits_be32(®s->pdb_stat, 0x08000000); + asm("sync;isync"); + for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++) + udelay(1000); + } else { + fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, <ssm); + if (ltssm == 1) { /* assert PCIe reset */ setbits_be32(®s->pdb_stat, 0x08000000); (void)in_be32(®s->pdb_stat); - udelay(1000); + udelay(100); /* clear PCIe reset */ clrbits_be32(®s->pdb_stat, 0x08000000); asm("sync;isync"); - for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++) + for (i = 0; i < 100 && + !fsl_pcie_link_up(pcie); i++) udelay(1000); - } else { - fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, <ssm); - if (ltssm == 1) { - /* assert PCIe reset */ - setbits_be32(®s->pdb_stat, 0x08000000); - (void)in_be32(®s->pdb_stat); - udelay(100); - /* clear PCIe reset */ - clrbits_be32(®s->pdb_stat, 0x08000000); - asm("sync;isync"); - for (i = 0; i < 100 && - !fsl_pcie_link_up(pcie); i++) - udelay(1000); - } } } +#endif - if (IS_ENABLED(CONFIG_SYS_P4080_ERRATUM_PCIE_A003) && - !fsl_pcie_link_up(pcie)) { +#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003 + if (!fsl_pcie_link_up(pcie)) { serdes_corenet_t *srds_regs; srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; @@ -460,13 +461,15 @@ static int fsl_pcie_init_port(struct fsl_pcie *pcie) udelay(1000); } } +#endif /* * The Read-Only Write Enable bit defaults to 1 instead of 0. * Set to 0 to protect the read-only registers. */ - if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A007815)) - clrbits_be32(®s->dbi_ro_wr_en, 0x01); +#ifdef CONFIG_SYS_FSL_ERRATUM_A007815 + clrbits_be32(®s->dbi_ro_wr_en, 0x01); +#endif /* * Enable All Error Interrupts except @@ -500,14 +503,23 @@ static int fsl_pcie_init_port(struct fsl_pcie *pcie) static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie) { ccsr_fsl_pci_t *regs = pcie->regs; + u32 classcode_reg; u32 val; - setbits_be32(®s->dbi_ro_wr_en, 0x01); - fsl_pcie_hose_read_config_dword(pcie, PCI_CLASS_REVISION, &val); + if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) { + classcode_reg = PCI_CLASS_REVISION; + setbits_be32(®s->dbi_ro_wr_en, 0x01); + } else { + classcode_reg = CSR_CLASSCODE; + } + + fsl_pcie_hose_read_config_dword(pcie, classcode_reg, &val); val &= 0xff; val |= PCI_CLASS_BRIDGE_PCI << 16; - fsl_pcie_hose_write_config_dword(pcie, PCI_CLASS_REVISION, val); - clrbits_be32(®s->dbi_ro_wr_en, 0x01); + fsl_pcie_hose_write_config_dword(pcie, classcode_reg, val); + + if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) + clrbits_be32(®s->dbi_ro_wr_en, 0x01); return 0; } @@ -570,6 +582,7 @@ static int fsl_pcie_probe(struct udevice *dev) static int fsl_pcie_ofdata_to_platdata(struct udevice *dev) { struct fsl_pcie *pcie = dev_get_priv(dev); + struct fsl_pcie_data *info; int ret; pcie->regs = dev_remap_addr(dev); @@ -584,7 +597,10 @@ static int fsl_pcie_ofdata_to_platdata(struct udevice *dev) return ret; } - pcie->idx = (dev_read_addr(dev) - 0xffe240000) / 0x10000; + info = (struct fsl_pcie_data *)dev_get_driver_data(dev); + pcie->info = info; + pcie->idx = abs((u32)(dev_read_addr(dev) & info->block_offset_mask) - + info->block_offset) / info->stride; return 0; } @@ -594,8 +610,35 @@ static const struct dm_pci_ops fsl_pcie_ops = { .write_config = fsl_pcie_write_config, }; +static struct fsl_pcie_data p1_p2_data = { + .block_offset = 0xa000, + .block_offset_mask = 0xffff, + .stride = 0x1000, +}; + +static struct fsl_pcie_data p2041_data = { + .block_offset = 0x200000, + .block_offset_mask = 0x3fffff, + .stride = 0x1000, +}; + +static struct fsl_pcie_data t2080_data = { + .block_offset = 0x240000, + .block_offset_mask = 0x3fffff, + .stride = 0x10000, +}; + static const struct udevice_id fsl_pcie_ids[] = { - { .compatible = "fsl,pcie-t2080" }, + { .compatible = "fsl,pcie-mpc8548", .data = (ulong)&p1_p2_data }, + { .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data }, + { .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data }, + { .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data }, + { .compatible = "fsl,pcie-p4080", .data = (ulong)&p2041_data }, + { .compatible = "fsl,pcie-p5040", .data = (ulong)&p2041_data }, + { .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data }, + { .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data }, + { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data }, + { .compatible = "fsl,pcie-t4240", .data = (ulong)&t2080_data }, { } }; diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h index 5eefc31fa9..dc8368d559 100644 --- a/drivers/pci/pcie_fsl.h +++ b/drivers/pci/pcie_fsl.h @@ -9,6 +9,9 @@ #ifndef _PCIE_FSL_H_ #define _PCIE_FSL_H_ +/* GPEX CSR */ +#define CSR_CLASSCODE 0x474 + #ifdef CONFIG_SYS_FSL_PCI_VER_3_X #define FSL_PCIE_CAP_ID 0x70 #else @@ -40,6 +43,12 @@ #define LTSSM_L0_REV3 0x11 #define LTSSM_L0 0x16 +struct fsl_pcie_data { + u32 block_offset; /* Offset from CCSR of 1st controller */ + u32 block_offset_mask; /* Mask out the CCSR base */ + u32 stride; /* Offset stride between controllers */ +}; + struct fsl_pcie { int idx; struct udevice *bus; @@ -49,6 +58,7 @@ struct fsl_pcie { bool mode; /* RC&EP mode flag */ bool enabled; /* Enable status */ struct list_head list; + struct fsl_pcie_data *info; }; extern struct list_head fsl_pcie_list; diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 3942f035eb..02312273e2 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -19,7 +19,7 @@ config PHY config SPL_PHY bool "PHY Core in SPL" - depends on DM + depends on DM && SPL help PHY support in SPL. diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmfx.c index 5431df9813..0b5a0433cd 100644 --- a/drivers/pinctrl/pinctrl-stmfx.c +++ b/drivers/pinctrl/pinctrl-stmfx.c @@ -231,23 +231,23 @@ static int stmfx_pinctrl_conf_set(struct udevice *dev, unsigned int pin, switch (param) { case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_DRIVE_PUSH_PULL: + ret = stmfx_pinctrl_set_type(dev, pin, 0); + break; case PIN_CONFIG_BIAS_PULL_DOWN: + ret = stmfx_pinctrl_set_type(dev, pin, 1); + if (ret) + return ret; ret = stmfx_pinctrl_set_pupd(dev, pin, 0); break; case PIN_CONFIG_BIAS_PULL_UP: + ret = stmfx_pinctrl_set_type(dev, pin, 1); + if (ret) + return ret; ret = stmfx_pinctrl_set_pupd(dev, pin, 1); break; case PIN_CONFIG_DRIVE_OPEN_DRAIN: - if (dir == GPIOF_OUTPUT) - ret = stmfx_pinctrl_set_type(dev, pin, 1); - else - ret = stmfx_pinctrl_set_type(dev, pin, 0); - break; - case PIN_CONFIG_DRIVE_PUSH_PULL: - if (dir == GPIOF_OUTPUT) - ret = stmfx_pinctrl_set_type(dev, pin, 0); - else - ret = stmfx_pinctrl_set_type(dev, pin, 1); + ret = stmfx_pinctrl_set_type(dev, pin, 1); break; case PIN_CONFIG_OUTPUT: ret = stmfx_gpio_direction_output(plat->gpio, pin, arg); diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index cdbe463cff..3a235ae5a7 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -1,11 +1,11 @@ #include <common.h> #include <dm.h> -#include <dm/lists.h> -#include <dm/pinctrl.h> #include <hwspinlock.h> #include <asm/arch/gpio.h> #include <asm/gpio.h> #include <asm/io.h> +#include <dm/lists.h> +#include <dm/pinctrl.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/power/pmic/stpmic1.c b/drivers/power/pmic/stpmic1.c index c3381489dd..de31934f41 100644 --- a/drivers/power/pmic/stpmic1.c +++ b/drivers/power/pmic/stpmic1.c @@ -7,6 +7,7 @@ #include <dm.h> #include <errno.h> #include <i2c.h> +#include <misc.h> #include <sysreset.h> #include <dm/device.h> #include <dm/lists.h> @@ -69,6 +70,7 @@ static int stpmic1_read(struct udevice *dev, uint reg, uint8_t *buff, int len) static int stpmic1_bind(struct udevice *dev) { + int ret; #if CONFIG_IS_ENABLED(DM_REGULATOR) ofnode regulators_node; int children; @@ -86,6 +88,13 @@ static int stpmic1_bind(struct udevice *dev) dev_dbg(dev, "no child found\n"); #endif /* DM_REGULATOR */ + if (!IS_ENABLED(CONFIG_SPL_BUILD)) { + ret = device_bind_driver(dev, "stpmic1-nvm", + "stpmic1-nvm", NULL); + if (ret) + return ret; + } + if (CONFIG_IS_ENABLED(SYSRESET)) return device_bind_driver(dev, "stpmic1-sysreset", "stpmic1-sysreset", NULL); @@ -113,32 +122,38 @@ U_BOOT_DRIVER(pmic_stpmic1) = { }; #ifndef CONFIG_SPL_BUILD -static int stpmic1_nvm_rw(u8 addr, u8 *buf, int buf_len, enum pmic_nvm_op op) +static int stpmic1_nvm_rw(struct udevice *dev, u8 addr, u8 *buf, int buf_len, + enum pmic_nvm_op op) { - struct udevice *dev; unsigned long timeout; u8 cmd = STPMIC1_NVM_CMD_READ; - int ret; - - ret = uclass_get_device_by_driver(UCLASS_PMIC, - DM_GET_DRIVER(pmic_stpmic1), &dev); - if (ret) - /* No PMIC on power discrete board */ - return -EOPNOTSUPP; + int ret, len = buf_len; if (addr < STPMIC1_NVM_START_ADDRESS) return -EACCES; + if (addr + buf_len > STPMIC1_NVM_START_ADDRESS + STPMIC1_NVM_SIZE) + len = STPMIC1_NVM_START_ADDRESS + STPMIC1_NVM_SIZE - addr; - if (op == SHADOW_READ) - return pmic_read(dev, addr, buf, buf_len); + if (op == SHADOW_READ) { + ret = pmic_read(dev, addr, buf, len); + if (ret < 0) + return ret; + else + return len; + } - if (op == SHADOW_WRITE) - return pmic_write(dev, addr, buf, buf_len); + if (op == SHADOW_WRITE) { + ret = pmic_write(dev, addr, buf, len); + if (ret < 0) + return ret; + else + return len; + } if (op == NVM_WRITE) { cmd = STPMIC1_NVM_CMD_PROGRAM; - ret = pmic_write(dev, addr, buf, buf_len); + ret = pmic_write(dev, addr, buf, len); if (ret < 0) return ret; } @@ -168,69 +183,61 @@ static int stpmic1_nvm_rw(u8 addr, u8 *buf, int buf_len, enum pmic_nvm_op op) return -ETIMEDOUT; if (op == NVM_READ) { - ret = pmic_read(dev, addr, buf, buf_len); + ret = pmic_read(dev, addr, buf, len); if (ret < 0) return ret; } - return 0; + return len; } -int stpmic1_shadow_read_byte(u8 addr, u8 *buf) +static int stpmic1_nvm_read(struct udevice *dev, int offset, + void *buf, int size) { - return stpmic1_nvm_rw(addr, buf, 1, SHADOW_READ); -} + enum pmic_nvm_op op = NVM_READ; -int stpmic1_shadow_write_byte(u8 addr, u8 *buf) -{ - return stpmic1_nvm_rw(addr, buf, 1, SHADOW_WRITE); -} + if (offset < 0) { + op = SHADOW_READ; + offset = -offset; + } -int stpmic1_nvm_read_byte(u8 addr, u8 *buf) -{ - return stpmic1_nvm_rw(addr, buf, 1, NVM_READ); + return stpmic1_nvm_rw(dev->parent, offset, buf, size, op); } -int stpmic1_nvm_write_byte(u8 addr, u8 *buf) +static int stpmic1_nvm_write(struct udevice *dev, int offset, + const void *buf, int size) { - return stpmic1_nvm_rw(addr, buf, 1, NVM_WRITE); -} + enum pmic_nvm_op op = NVM_WRITE; -int stpmic1_nvm_read_all(u8 *buf, int buf_len) -{ - if (buf_len != STPMIC1_NVM_SIZE) - return -EINVAL; + if (offset < 0) { + op = SHADOW_WRITE; + offset = -offset; + } - return stpmic1_nvm_rw(STPMIC1_NVM_START_ADDRESS, - buf, buf_len, NVM_READ); + return stpmic1_nvm_rw(dev->parent, offset, (void *)buf, size, op); } -int stpmic1_nvm_write_all(u8 *buf, int buf_len) -{ - if (buf_len != STPMIC1_NVM_SIZE) - return -EINVAL; +static const struct misc_ops stpmic1_nvm_ops = { + .read = stpmic1_nvm_read, + .write = stpmic1_nvm_write, +}; - return stpmic1_nvm_rw(STPMIC1_NVM_START_ADDRESS, - buf, buf_len, NVM_WRITE); -} +U_BOOT_DRIVER(stpmic1_nvm) = { + .name = "stpmic1-nvm", + .id = UCLASS_MISC, + .ops = &stpmic1_nvm_ops, +}; #endif /* CONFIG_SPL_BUILD */ #ifdef CONFIG_SYSRESET static int stpmic1_sysreset_request(struct udevice *dev, enum sysreset_t type) { - struct udevice *pmic_dev; + struct udevice *pmic_dev = dev->parent; int ret; if (type != SYSRESET_POWER && type != SYSRESET_POWER_OFF) return -EPROTONOSUPPORT; - ret = uclass_get_device_by_driver(UCLASS_PMIC, - DM_GET_DRIVER(pmic_stpmic1), - &pmic_dev); - - if (ret) - return -EOPNOTSUPP; - ret = pmic_reg_read(pmic_dev, STPMIC1_MAIN_CR); if (ret < 0) return ret; diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 81fc71c051..ed70137ce7 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -1488,6 +1488,84 @@ static void dram_all_config(struct dram_info *dram, clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3); } +static void set_cap_relate_config(const struct chan_info *chan, + struct rk3399_sdram_params *params, + unsigned int channel) +{ + u32 *denali_ctl = chan->pctl->denali_ctl; + u32 tmp; + struct rk3399_msch_timings *noc_timing; + + if (params->base.dramtype == LPDDR3) { + tmp = (8 << params->ch[channel].cap_info.bw) / + (8 << params->ch[channel].cap_info.dbw); + + /** + * memdata_ratio + * 1 -> 0, 2 -> 1, 4 -> 2 + */ + clrsetbits_le32(&denali_ctl[197], 0x7, + (tmp >> 1)); + clrsetbits_le32(&denali_ctl[198], 0x7 << 8, + (tmp >> 1) << 8); + } + + noc_timing = ¶ms->ch[channel].noc_timings; + + /* + * noc timing bw relate timing is 32 bit, and real bw is 16bit + * actually noc reg is setting at function dram_all_config + */ + if (params->ch[channel].cap_info.bw == 16 && + noc_timing->ddrmode.b.mwrsize == 2) { + if (noc_timing->ddrmode.b.burstsize) + noc_timing->ddrmode.b.burstsize -= 1; + noc_timing->ddrmode.b.mwrsize -= 1; + noc_timing->ddrtimingc0.b.burstpenalty *= 2; + noc_timing->ddrtimingc0.b.wrtomwr *= 2; + } +} + +static u32 calculate_ddrconfig(struct rk3399_sdram_params *params, u32 channel) +{ + unsigned int cs0_row = params->ch[channel].cap_info.cs0_row; + unsigned int col = params->ch[channel].cap_info.col; + unsigned int bw = params->ch[channel].cap_info.bw; + u16 ddr_cfg_2_rbc[] = { + /* + * [6] highest bit col + * [5:3] max row(14+n) + * [2] insertion row + * [1:0] col(9+n),col, data bus 32bit + * + * highbitcol, max_row, insertion_row, col + */ + ((0 << 6) | (2 << 3) | (0 << 2) | 0), /* 0 */ + ((0 << 6) | (2 << 3) | (0 << 2) | 1), /* 1 */ + ((0 << 6) | (1 << 3) | (0 << 2) | 2), /* 2 */ + ((0 << 6) | (0 << 3) | (0 << 2) | 3), /* 3 */ + ((0 << 6) | (2 << 3) | (1 << 2) | 1), /* 4 */ + ((0 << 6) | (1 << 3) | (1 << 2) | 2), /* 5 */ + ((1 << 6) | (0 << 3) | (0 << 2) | 2), /* 6 */ + ((1 << 6) | (1 << 3) | (0 << 2) | 2), /* 7 */ + }; + u32 i; + + col -= (bw == 2) ? 0 : 1; + col -= 9; + + for (i = 0; i < 4; i++) { + if ((col == (ddr_cfg_2_rbc[i] & 0x3)) && + (cs0_row <= (((ddr_cfg_2_rbc[i] >> 3) & 0x7) + 14))) + break; + } + + if (i >= 4) + i = -EINVAL; + + return i; +} + #if !defined(CONFIG_RAM_RK3399_LPDDR4) static int default_data_training(struct dram_info *dram, u32 channel, u8 rank, struct rk3399_sdram_params *params) @@ -1588,84 +1666,6 @@ static void set_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf, u32 stride) rk_clrsetreg(&pmusgrf->soc_con4, 0x1f << 10, stride << 10); } -static void set_cap_relate_config(const struct chan_info *chan, - struct rk3399_sdram_params *params, - unsigned int channel) -{ - u32 *denali_ctl = chan->pctl->denali_ctl; - u32 tmp; - struct rk3399_msch_timings *noc_timing; - - if (params->base.dramtype == LPDDR3) { - tmp = (8 << params->ch[channel].cap_info.bw) / - (8 << params->ch[channel].cap_info.dbw); - - /** - * memdata_ratio - * 1 -> 0, 2 -> 1, 4 -> 2 - */ - clrsetbits_le32(&denali_ctl[197], 0x7, - (tmp >> 1)); - clrsetbits_le32(&denali_ctl[198], 0x7 << 8, - (tmp >> 1) << 8); - } - - noc_timing = ¶ms->ch[channel].noc_timings; - - /* - * noc timing bw relate timing is 32 bit, and real bw is 16bit - * actually noc reg is setting at function dram_all_config - */ - if (params->ch[channel].cap_info.bw == 16 && - noc_timing->ddrmode.b.mwrsize == 2) { - if (noc_timing->ddrmode.b.burstsize) - noc_timing->ddrmode.b.burstsize -= 1; - noc_timing->ddrmode.b.mwrsize -= 1; - noc_timing->ddrtimingc0.b.burstpenalty *= 2; - noc_timing->ddrtimingc0.b.wrtomwr *= 2; - } -} - -static u32 calculate_ddrconfig(struct rk3399_sdram_params *params, u32 channel) -{ - unsigned int cs0_row = params->ch[channel].cap_info.cs0_row; - unsigned int col = params->ch[channel].cap_info.col; - unsigned int bw = params->ch[channel].cap_info.bw; - u16 ddr_cfg_2_rbc[] = { - /* - * [6] highest bit col - * [5:3] max row(14+n) - * [2] insertion row - * [1:0] col(9+n),col, data bus 32bit - * - * highbitcol, max_row, insertion_row, col - */ - ((0 << 6) | (2 << 3) | (0 << 2) | 0), /* 0 */ - ((0 << 6) | (2 << 3) | (0 << 2) | 1), /* 1 */ - ((0 << 6) | (1 << 3) | (0 << 2) | 2), /* 2 */ - ((0 << 6) | (0 << 3) | (0 << 2) | 3), /* 3 */ - ((0 << 6) | (2 << 3) | (1 << 2) | 1), /* 4 */ - ((0 << 6) | (1 << 3) | (1 << 2) | 2), /* 5 */ - ((1 << 6) | (0 << 3) | (0 << 2) | 2), /* 6 */ - ((1 << 6) | (1 << 3) | (0 << 2) | 2), /* 7 */ - }; - u32 i; - - col -= (bw == 2) ? 0 : 1; - col -= 9; - - for (i = 0; i < 4; i++) { - if ((col == (ddr_cfg_2_rbc[i] & 0x3)) && - (cs0_row <= (((ddr_cfg_2_rbc[i] >> 3) & 0x7) + 14))) - break; - } - - if (i >= 4) - i = -EINVAL; - - return i; -} - /** * read mr_num mode register * rank = 1: cs0 @@ -2592,8 +2592,11 @@ static int sdram_init(struct dram_info *dram, } sdram_print_ddr_info(cap_info, ¶ms->base); + set_memory_map(chan, channel, params); + cap_info->ddrconfig = calculate_ddrconfig(params, channel); set_ddrconfig(chan, params, channel, cap_info->ddrconfig); + set_cap_relate_config(chan, params, channel); } if (params->base.num_channels == 0) { diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.h b/drivers/ram/stm32mp1/stm32mp1_ddr.h index a8eed89e3c..52b748f3ca 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ddr.h +++ b/drivers/ram/stm32mp1/stm32mp1_ddr.h @@ -197,10 +197,6 @@ void stm32mp1_edit_param(const struct stm32mp1_ddr_config *config, char *name, char *string); -void stm32mp1_dump_info( - const struct ddr_info *priv, - const struct stm32mp1_ddr_config *config); - bool stm32mp1_ddr_interactive( void *priv, enum stm32mp1_ddr_interact_step step, diff --git a/drivers/ram/stm32mp1/stm32mp1_tests.c b/drivers/ram/stm32mp1/stm32mp1_tests.c index b6fb2a9c58..581ee4897f 100644 --- a/drivers/ram/stm32mp1/stm32mp1_tests.c +++ b/drivers/ram/stm32mp1/stm32mp1_tests.c @@ -4,6 +4,7 @@ */ #include <common.h> #include <console.h> +#include <watchdog.h> #include <asm/io.h> #include <linux/log2.h> #include "stm32mp1_tests.h" @@ -154,6 +155,8 @@ static int test_loop_end(u32 *loop, u32 nb_loop, u32 progress) return 1; } printf("loop #%d\n", *loop); + WATCHDOG_RESET(); + return 0; } @@ -578,27 +581,29 @@ static enum test_result test_random(struct stm32mp1_ddrctl *ctl, u32 error = 0; unsigned int seed; - if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024)) + if (get_bufsize(string, argc, argv, 0, &bufsize, 8 * 1024)) return TEST_ERROR; if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1)) return TEST_ERROR; if (get_addr(string, argc, argv, 2, &addr)) return TEST_ERROR; - printf("running %d loops at 0x%x\n", nb_loop, addr); + bufsize /= 2; + printf("running %d loops copy from 0x%x to 0x%x (buffer size=0x%x)\n", + nb_loop, addr, addr + bufsize, bufsize); while (!error) { seed = rand(); - for (offset = addr; offset < addr + bufsize; offset += 4) - writel(rand(), offset); + for (offset = 0; offset < bufsize; offset += 4) + writel(rand(), addr + offset); memcpy((void *)addr + bufsize, (void *)addr, bufsize); srand(seed); - for (offset = addr; offset < addr + 2 * bufsize; offset += 4) { - if (offset == (addr + bufsize)) + for (offset = 0; offset < 2 * bufsize; offset += 4) { + if (offset == bufsize) srand(seed); value = rand(); - error = check_addr(offset, value); + error = check_addr(addr + offset, value); if (error) break; if (progress(offset)) @@ -607,6 +612,7 @@ static enum test_result test_random(struct stm32mp1_ddrctl *ctl, if (test_loop_end(&loop, nb_loop, 100)) break; } + putc('\n'); if (error) { sprintf(string, @@ -791,9 +797,9 @@ static enum test_result test_loop(const u32 *pattern, u32 *address, int i; int j; enum test_result res = TEST_PASSED; - u32 *offset, testsize, remaining; + u32 offset, testsize, remaining; - offset = address; + offset = (u32)address; remaining = bufsize; while (remaining) { testsize = bufsize > 0x1000000 ? 0x1000000 : bufsize; @@ -809,7 +815,7 @@ static enum test_result test_loop(const u32 *pattern, u32 *address, __asm__("stmia r1!, {R3-R10}"); __asm__("stmia r1!, {R3-R10}"); __asm__("stmia r1!, {R3-R10}"); - __asm__("subs r2, r2, #8"); + __asm__("subs r2, r2, #128"); __asm__("bge loop2"); __asm__("pop {R0-R10}"); @@ -1238,27 +1244,38 @@ static enum test_result test_read(struct stm32mp1_ddrctl *ctl, u32 *addr; u32 data; u32 loop = 0; + int i, size = 1024 * 1024; bool random = false; if (get_addr(string, argc, argv, 0, (u32 *)&addr)) return TEST_ERROR; + if (get_pattern(string, argc, argv, 1, &data, 0xA5A5AA55)) + return TEST_ERROR; + if ((u32)addr == ADDR_INVALID) { - printf("random "); + printf("running random\n"); random = true; + } else { + printf("running at 0x%08x with pattern=0x%08x\n", + (u32)addr, data); + writel(data, addr); } - printf("running at 0x%08x\n", (u32)addr); - while (1) { - if (random) - addr = (u32 *)(STM32_DDR_BASE + - (rand() & (STM32_DDR_SIZE - 1) & ~0x3)); - data = readl(addr); - if (test_loop_end(&loop, 0, 1000)) + for (i = 0; i < size; i++) { + if (random) + addr = (u32 *)(STM32_DDR_BASE + + (rand() & (STM32_DDR_SIZE - 1) & ~0x3)); + data = readl(addr); + } + if (test_loop_end(&loop, 0, 1)) break; } - sprintf(string, "0x%x: %x", (u32)addr, data); + if (random) + sprintf(string, "%d loops random", loop); + else + sprintf(string, "%d loops at 0x%x: %x", loop, (u32)addr, data); return TEST_PASSED; } @@ -1275,31 +1292,41 @@ static enum test_result test_write(struct stm32mp1_ddrctl *ctl, char *string, int argc, char *argv[]) { u32 *addr; - u32 data = 0xA5A5AA55; + u32 data; u32 loop = 0; + int i, size = 1024 * 1024; bool random = false; if (get_addr(string, argc, argv, 0, (u32 *)&addr)) return TEST_ERROR; + if (get_pattern(string, argc, argv, 1, &data, 0xA5A5AA55)) + return TEST_ERROR; + if ((u32)addr == ADDR_INVALID) { - printf("random "); + printf("running random\n"); random = true; + } else { + printf("running at 0x%08x with pattern 0x%08x\n", + (u32)addr, data); } - printf("running at 0x%08x\n", (u32)addr); - while (1) { - if (random) { - addr = (u32 *)(STM32_DDR_BASE + - (rand() & (STM32_DDR_SIZE - 1) & ~0x3)); - data = rand(); + for (i = 0; i < size; i++) { + if (random) { + addr = (u32 *)(STM32_DDR_BASE + + (rand() & (STM32_DDR_SIZE - 1) & ~0x3)); + data = rand(); + } + writel(data, addr); } - writel(data, addr); - if (test_loop_end(&loop, 0, 1000)) + if (test_loop_end(&loop, 0, 1)) break; } - sprintf(string, "0x%x: %x", (u32)addr, data); + if (random) + sprintf(string, "%d loops random", loop); + else + sprintf(string, "%d loops at 0x%x: %x", loop, (u32)addr, data); return TEST_PASSED; } @@ -1388,7 +1415,7 @@ const struct test_desc test[] = { "Verifies r/w and memcopy(burst for pseudo random value.", 3 }, - {test_freq_pattern, "FrequencySelectivePattern ", "[size]", + {test_freq_pattern, "FrequencySelectivePattern", "[size]", "write & test patterns: Mostly Zero, Mostly One and F/n", 1 }, @@ -1417,10 +1444,10 @@ const struct test_desc test[] = { 3 }, /* need to the the 2 last one (infinite) : skipped for test all */ - {test_read, "infinite read", "[addr]", - "basic test : infinite read access", 1}, - {test_write, "infinite write", "[addr]", - "basic test : infinite write access", 1}, + {test_read, "infinite read", "[addr] [pattern]", + "basic test : infinite read access (random: addr=0xFFFFFFFF)", 2}, + {test_write, "infinite write", "[addr] [pattern]", + "basic test : infinite write access (random: addr=0xFFFFFFFF)", 2}, }; const int test_nb = ARRAY_SIZE(test); diff --git a/drivers/remoteproc/stm32_copro.c b/drivers/remoteproc/stm32_copro.c index de3b9729f3..ad941f67e8 100644 --- a/drivers/remoteproc/stm32_copro.c +++ b/drivers/remoteproc/stm32_copro.c @@ -243,7 +243,7 @@ static const struct dm_rproc_ops stm32_copro_ops = { }; static const struct udevice_id stm32_copro_ids[] = { - {.compatible = "st,stm32mp1-rproc"}, + {.compatible = "st,stm32mp1-m4"}, {} }; diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 860b73d369..8778cc7b26 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -31,6 +31,12 @@ config TPL_DM_RTC drivers to perform the actual functions. See rtc.h for a description of the API. +config RTC_ENABLE_32KHZ_OUTPUT + bool "Enable RTC 32Khz output" + help + Some real-time clocks support the output of 32kHz square waves (such as ds3231), + the config symbol choose Real Time Clock device 32Khz output feature. + config RTC_PCF2127 bool "Enable PCF2127 driver" depends on DM_RTC diff --git a/drivers/rtc/ds3231.c b/drivers/rtc/ds3231.c index 79b026af4b..fde4d860ec 100644 --- a/drivers/rtc/ds3231.c +++ b/drivers/rtc/ds3231.c @@ -148,11 +148,13 @@ void rtc_reset (void) /* * Enable 32KHz output */ +#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT void rtc_enable_32khz_output(void) { rtc_write(RTC_STAT_REG_ADDR, RTC_STAT_BIT_BB32KHZ | RTC_STAT_BIT_EN32KHZ); } +#endif /* * Helper functions @@ -251,6 +253,21 @@ static int ds3231_probe(struct udevice *dev) return 0; } +#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT +int rtc_enable_32khz_output(int busnum, int chip_addr) +{ + int ret; + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(busnum, chip_addr, 1, &dev); + if (!ret) + ret = dm_i2c_reg_write(dev, RTC_STAT_REG_ADDR, + RTC_STAT_BIT_BB32KHZ | + RTC_STAT_BIT_EN32KHZ); + return ret; +} +#endif + static const struct rtc_ops ds3231_rtc_ops = { .get = ds3231_rtc_get, .set = ds3231_rtc_set, diff --git a/drivers/rtc/stm32_rtc.c b/drivers/rtc/stm32_rtc.c index abd339076a..2674714442 100644 --- a/drivers/rtc/stm32_rtc.c +++ b/drivers/rtc/stm32_rtc.c @@ -72,7 +72,8 @@ static int stm32_rtc_get(struct udevice *dev, struct rtc_time *tm) tm->tm_mday = bcd2bin((dr & STM32_RTC_DATE) >> STM32_RTC_DATE_SHIFT); tm->tm_mon = bcd2bin((dr & STM32_RTC_MONTH) >> STM32_RTC_MONTH_SHIFT); - tm->tm_year = bcd2bin((dr & STM32_RTC_YEAR) >> STM32_RTC_YEAR_SHIFT); + tm->tm_year = 2000 + + bcd2bin((dr & STM32_RTC_YEAR) >> STM32_RTC_YEAR_SHIFT); tm->tm_wday = bcd2bin((dr & STM32_RTC_WDAY) >> STM32_RTC_WDAY_SHIFT); tm->tm_yday = 0; tm->tm_isdst = 0; @@ -174,6 +175,9 @@ static int stm32_rtc_set(struct udevice *dev, const struct rtc_time *tm) tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, tm->tm_hour, tm->tm_min, tm->tm_sec); + if (tm->tm_year < 2000 || tm->tm_year > 2099) + return -EINVAL; + /* Time in BCD format */ t = (bin2bcd(tm->tm_sec) << STM32_RTC_SEC_SHIFT) & STM32_RTC_SEC; t |= (bin2bcd(tm->tm_min) << STM32_RTC_MIN_SHIFT) & STM32_RTC_MIN; @@ -182,7 +186,8 @@ static int stm32_rtc_set(struct udevice *dev, const struct rtc_time *tm) /* Date in BCD format */ d = (bin2bcd(tm->tm_mday) << STM32_RTC_DATE_SHIFT) & STM32_RTC_DATE; d |= (bin2bcd(tm->tm_mon) << STM32_RTC_MONTH_SHIFT) & STM32_RTC_MONTH; - d |= (bin2bcd(tm->tm_year) << STM32_RTC_YEAR_SHIFT) & STM32_RTC_YEAR; + d |= (bin2bcd(tm->tm_year - 2000) << STM32_RTC_YEAR_SHIFT) & + STM32_RTC_YEAR; d |= (bin2bcd(tm->tm_wday) << STM32_RTC_WDAY_SHIFT) & STM32_RTC_WDAY; return stm32_rtc_set_time(dev, t, d); diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 8a447fd6e3..ae2d819ba9 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -45,7 +45,7 @@ config SERIAL_PRESENT config SPL_SERIAL_PRESENT bool "Provide a serial driver in SPL" - depends on DM_SERIAL + depends on DM_SERIAL && SPL default y help In very space-constrained devices even the full UART driver is too @@ -55,7 +55,7 @@ config SPL_SERIAL_PRESENT config TPL_SERIAL_PRESENT bool "Provide a serial driver in TPL" - depends on DM_SERIAL + depends on DM_SERIAL && TPL default y help In very space-constrained devices even the full UART driver is too diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c index 3ab536a52a..00a8e7249b 100644 --- a/drivers/serial/serial_stm32.c +++ b/drivers/serial/serial_stm32.c @@ -106,10 +106,11 @@ static int stm32_serial_getc(struct udevice *dev) if ((isr & USART_ISR_RXNE) == 0) return -EAGAIN; - if (isr & (USART_ISR_PE | USART_ISR_ORE)) { + if (isr & (USART_ISR_PE | USART_ISR_ORE | USART_ISR_FE)) { if (!stm32f4) setbits_le32(base + ICR_OFFSET, - USART_ICR_PCECF | USART_ICR_ORECF); + USART_ICR_PCECF | USART_ICR_ORECF | + USART_ICR_FECF); else readl(base + RDR_OFFSET(stm32f4)); return -EIO; diff --git a/drivers/serial/serial_stm32.h b/drivers/serial/serial_stm32.h index 5549f8c536..7b0c53145e 100644 --- a/drivers/serial/serial_stm32.h +++ b/drivers/serial/serial_stm32.h @@ -67,6 +67,7 @@ struct stm32x7_serial_platdata { #define USART_ISR_TXE BIT(7) #define USART_ISR_RXNE BIT(5) #define USART_ISR_ORE BIT(3) +#define USART_ISR_FE BIT(1) #define USART_ISR_PE BIT(0) #define USART_BRR_F_MASK GENMASK(7, 0) @@ -74,6 +75,7 @@ struct stm32x7_serial_platdata { #define USART_BRR_M_MASK GENMASK(15, 4) #define USART_ICR_ORECF BIT(3) +#define USART_ICR_FECF BIT(1) #define USART_ICR_PCECF BIT(0) #endif diff --git a/fs/fat/fat.c b/fs/fat/fat.c index 06c8ed14bd..29cae8d391 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -1174,10 +1174,6 @@ int file_fat_read_at(const char *filename, loff_t pos, void *buffer, /* For saving default max clustersize memory allocated to malloc pool */ dir_entry *dentptr = itr->dent; - free(itr); - - itr = NULL; - ret = get_contents(&fsdata, dentptr, pos, buffer, maxsize, actread); out_free_both: diff --git a/include/clk.h b/include/clk.h index 3ca2796b57..18b2e3ca54 100644 --- a/include/clk.h +++ b/include/clk.h @@ -61,6 +61,7 @@ struct clk { struct udevice *dev; long long rate; /* in HZ */ u32 flags; + int enable_count; /* * Written by of_xlate. In the future, we might add more fields here. */ diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h index 49ed668f17..f214dc90bc 100644 --- a/include/configs/M5249EVB.h +++ b/include/configs/M5249EVB.h @@ -36,7 +36,6 @@ */ #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ #define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index b37601c794..3a8c074dc5 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -18,8 +18,6 @@ #define CONFIG_PCI1 /* PCI controller 1 */ #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #undef CONFIG_PCI2 -#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE @@ -289,7 +287,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ /* Serial Port */ @@ -343,24 +341,18 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ #ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_NAME "Slot" #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 #endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull #else #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 #endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ #endif /* @@ -386,6 +378,20 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_EEPRO100 #undef CONFIG_TULIP +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_PCI_INDIRECT_BRIDGE 1 +#define CONFIG_SYS_PCIE1_NAME "Slot" +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 +#endif +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ +#endif + #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index e196f3ce33..f8cfef7b2d 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -37,7 +37,6 @@ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_SYS_SRIO @@ -354,60 +353,21 @@ unsigned long get_board_sys_clk(unsigned long dummy); /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 -#endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#else -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 -#endif -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 -#endif -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull -#else -#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 -#endif -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#else -#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 -#endif -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* Qman/Bman */ #define CONFIG_SYS_BMAN_NUM_PORTALS 10 @@ -483,7 +443,22 @@ unsigned long get_board_sys_clk(unsigned long dummy); #endif #ifdef CONFIG_PCI +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h index 1539e8fabb..f24cd23af2 100644 --- a/include/configs/SBx81LIFKW.h +++ b/include/configs/SBx81LIFKW.h @@ -83,7 +83,6 @@ /* * Other required minimal configurations */ -#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ #define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ #define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h index af19193052..b602323262 100644 --- a/include/configs/SBx81LIFXCAT.h +++ b/include/configs/SBx81LIFXCAT.h @@ -83,7 +83,6 @@ /* * Other required minimal configurations */ -#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ #define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ #define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 5ab51e3233..8c1434fb10 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -494,96 +494,48 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ -#ifdef CONFIG_ARCH_T1040 -#define CONFIG_PCIE4 /* PCIE controller 4 */ -#endif -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#define CONFIG_PCI_INDIRECT_BRIDGE #ifdef CONFIG_PCI /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #ifdef CONFIG_PCIE1 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 -#endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ #endif /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #ifdef CONFIG_PCIE2 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull -#else -#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 -#endif -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 -#endif -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ #endif /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #ifdef CONFIG_PCIE3 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull -#else -#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 -#endif -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#else -#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 -#endif -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ #endif -/* controller 4, Base address 203000, to be removed */ -#ifdef CONFIG_PCIE4 -#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull -#else -#define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 -#endif -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#else -#define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 -#endif -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_PCI_INDIRECT_BRIDGE #endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 56ddef07f5..53ee1484d0 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -145,13 +145,11 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_PCIE4 /* PCIE controller 4 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE @@ -524,51 +522,55 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #ifdef CONFIG_PCIE1 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ #endif /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #ifdef CONFIG_PCIE2 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ #endif /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #ifdef CONFIG_PCIE3 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ #endif /* controller 4, Base address 203000 */ #ifdef CONFIG_PCIE4 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ #endif +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_PCI_INDIRECT_BRIDGE +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index ab92ca3b68..3d95c4afa2 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -433,49 +433,51 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_PCIE4 /* PCIE controller 4 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* controller 4, Base address 203000 */ #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ #ifdef CONFIG_PCI +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ #define CONFIG_PCI_INDIRECT_BRIDGE +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 0accdc6119..57d8d171a7 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -61,7 +61,6 @@ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE @@ -176,44 +175,48 @@ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* controller 4, Base address 203000 */ #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ #ifdef CONFIG_PCI +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ #define CONFIG_PCI_INDIRECT_BRIDGE +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ diff --git a/include/configs/advantech_dms-ba16.h b/include/configs/advantech_dms-ba16.h index a037349162..1298859812 100644 --- a/include/configs/advantech_dms-ba16.h +++ b/include/configs/advantech_dms-ba16.h @@ -39,7 +39,6 @@ #define CONFIG_LBA48 /* MMC Configs */ -#define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 /* USB Configs */ diff --git a/include/configs/alt.h b/include/configs/alt.h index eb7eb551ae..bb5267517c 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -45,7 +45,6 @@ /* SPL support */ #define CONFIG_SPL_STACK 0xe6340000 #define CONFIG_SPL_MAX_SIZE 0x4000 -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000 #ifdef CONFIG_SPL_BUILD #define CONFIG_CONS_SCIF2 #define CONFIG_SH_SCIF_CLK_FREQ 65000000 diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 1885ac8e36..be571066f2 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -274,7 +274,6 @@ */ #if defined(CONFIG_SPI_BOOT) /* SPL related */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */ diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 63489133a8..3e5f0b1992 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -26,8 +26,11 @@ * Enable CONFIG_USB_MUSB_HOST for Host functionalities MSC, keyboard * Enable CONFIG_USB_MUSB_GADGET for Device functionalities. */ - +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_USB_EHCI_OMAP +#else #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57 +#endif /* I2C */ diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index b0d9559962..d355b80c2f 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -8,7 +8,6 @@ #ifndef __CONFIG_AM43XX_EVM_H #define __CONFIG_AM43XX_EVM_H -#define CONFIG_ARCH_CPU_INIT #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index e181b30564..531f79ee70 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -90,6 +90,5 @@ #define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 /* SPI SPL */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 #endif /* __CONFIG_AM57XX_EVM_H */ diff --git a/include/configs/amcore.h b/include/configs/amcore.h index 4daa0bafe8..26d6fef290 100644 --- a/include/configs/amcore.h +++ b/include/configs/amcore.h @@ -30,8 +30,6 @@ /* undef to save memory */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ - #define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */ #define CONFIG_SYS_MEMTEST_START 0x0 diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h index 32623c263a..6eb8395162 100644 --- a/include/configs/apalis-imx8.h +++ b/include/configs/apalis-imx8.h @@ -15,7 +15,6 @@ #undef CONFIG_BOOTM_NETBSD -#define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define USDHC1_BASE_ADDR 0x5b010000 #define USDHC2_BASE_ADDR 0x5b020000 diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 974571df43..4eceb10e8f 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -42,7 +42,6 @@ #define CONFIG_SYS_MXC_I2C3_SPEED 400000 /* MMC Configs */ -#define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 3 diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h index 0d170ec993..c3ccceedca 100644 --- a/include/configs/armadillo-800eva.h +++ b/include/configs/armadillo-800eva.h @@ -14,7 +14,6 @@ #define BOARD_LATE_INIT -#define CONFIG_ARCH_CPU_INIT #define CONFIG_TMU_TIMER #define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h index 1b8373fbc6..7af6b8b843 100644 --- a/include/configs/at91-sama5_common.h +++ b/include/configs/at91-sama5_common.h @@ -13,8 +13,6 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ -#define CONFIG_ARCH_CPU_INIT - #ifndef CONFIG_SPL_BUILD #define CONFIG_SKIP_LOWLEVEL_INIT #endif diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 95710fb4c8..b283c9d873 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -35,7 +35,6 @@ #endif /* Misc CPU related */ -#define CONFIG_ARCH_CPU_INIT #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index 6b1db9ff1e..3e7adf63f3 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -20,8 +20,6 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_ARCH_CPU_INIT - #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index e9b97b6e97..bc79e1739b 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -151,11 +151,6 @@ #ifdef CONFIG_SD_BOOT #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#elif CONFIG_SYS_USE_NANDFLASH -#elif CONFIG_SPI_BOOT -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400 - #elif CONFIG_NAND_BOOT #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_BASE diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index 3e18716e20..1c67be56b0 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -16,7 +16,6 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */ -#define CONFIG_ARCH_CPU_INIT #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 9353de76f2..ad7d281dd6 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -124,10 +124,6 @@ #ifdef CONFIG_SD_BOOT #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#elif CONFIG_SPI_BOOT -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400 - #elif CONFIG_NAND_BOOT #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_BASE diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h index bfa9fc9a52..db21a473f1 100644 --- a/include/configs/bav335x.h +++ b/include/configs/bav335x.h @@ -443,7 +443,6 @@ DEFAULT_LINUX_BOOT_ENV \ */ #if defined(CONFIG_SPI_BOOT) /* SPL related */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */ diff --git a/include/configs/bcm23550_w1d.h b/include/configs/bcm23550_w1d.h index deafb7b702..f59cd75d68 100644 --- a/include/configs/bcm23550_w1d.h +++ b/include/configs/bcm23550_w1d.h @@ -93,8 +93,6 @@ /* version string, parser, etc */ -#define CONFIG_MX_CYCLIC - /* Initial upstream - boot to cmd prompt only */ #define CONFIG_BOOTCOMMAND "" diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h index 781689a991..111858ffb0 100644 --- a/include/configs/bcm28155_ap.h +++ b/include/configs/bcm28155_ap.h @@ -92,8 +92,6 @@ /* version string, parser, etc */ -#define CONFIG_MX_CYCLIC - /* Initial upstream - boot to cmd prompt only */ #define CONFIG_BOOTCOMMAND "" diff --git a/include/configs/bcm_ep_board.h b/include/configs/bcm_ep_board.h index 09a5804e7a..b67100aa3a 100644 --- a/include/configs/bcm_ep_board.h +++ b/include/configs/bcm_ep_board.h @@ -51,8 +51,6 @@ /* version string, parser, etc */ -#define CONFIG_MX_CYCLIC - /* Enable Time Command */ #endif /* __BCM_EP_BOARD_H */ diff --git a/include/configs/brppt1.h b/include/configs/brppt1.h index 5a40f3abd1..bc0dabb51b 100644 --- a/include/configs/brppt1.h +++ b/include/configs/brppt1.h @@ -181,7 +181,6 @@ NANDTGTS \ #if defined(CONFIG_SPI) /* SPI Flash */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 /* Environment */ #define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ diff --git a/include/configs/brsmarc1.h b/include/configs/brsmarc1.h index c18445816e..c3eb5baacc 100644 --- a/include/configs/brsmarc1.h +++ b/include/configs/brsmarc1.h @@ -72,7 +72,6 @@ BUR_COMMON_ENV \ #define CONFIG_INITRD_TAG /* SPI Flash */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 /* Environment */ #define CONFIG_SYS_REDUNDAND_ENVIRONMENT diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index 07c6409e8f..f109b22fda 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -17,7 +17,6 @@ #define CONFIG_MACH_TYPE 4122 #ifdef CONFIG_SPL -#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) #include "imx6_spl.h" #endif diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index 4c93fc6cbe..7f3fdea039 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -147,7 +147,6 @@ #define CONFIG_ENV_SECT_SIZE (64 * 1024) /* MMC Config*/ -#define CONFIG_FSL_USDHC #ifdef CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR @@ -166,8 +165,5 @@ /* SPL */ #include "imx7_spl.h" -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) -#endif /* CONFIG_SPL_BUILD */ #endif /* __CONFIG_H */ diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h index 15c402b542..9d20a5e88c 100644 --- a/include/configs/clearfog.h +++ b/include/configs/clearfog.h @@ -83,7 +83,6 @@ #if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI) /* SPL related SPI defines */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS #elif defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC) || defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SATA) /* SPL related MMC defines */ diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 60bac9adc8..b957e9cba4 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -207,7 +207,6 @@ /* SPL */ #include "imx6_spl.h" -#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) /* Display */ #define CONFIG_IMX_HDMI diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index b2c1300427..1314cf96a2 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -9,7 +9,6 @@ #define __CONFIG_CM_T43_H #define CONFIG_CM_T43 -#define CONFIG_ARCH_CPU_INIT #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ @@ -115,7 +114,6 @@ /* SPL defines. */ #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + (128 << 20)) -#define CONFIG_SYS_SPI_U_BOOT_OFFS (256 * 1024) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* EEPROM */ diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index 05af222a1f..736717486b 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -153,7 +153,6 @@ /* used to initialize CONFIG_SYS_NAND_BASE_LIST which is unused */ #define CONFIG_SYS_NAND_BASE -1 #define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_SYS_NAND_USE_FLASH_BBT /* USB Configs */ #define CONFIG_EHCI_HCD_INIT_AFTER_RESET diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h index 2469066849..6f3c34d1ad 100644 --- a/include/configs/colibri-imx8x.h +++ b/include/configs/colibri-imx8x.h @@ -15,7 +15,6 @@ #undef CONFIG_BOOTM_NETBSD -#define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define USDHC1_BASE_ADDR 0x5b010000 #define USDHC2_BASE_ADDR 0x5b020000 diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 147f801353..aee9f2f1d0 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -40,7 +40,6 @@ #define CONFIG_SYS_MXC_I2C3_SPEED 400000 /* MMC Configs */ -#define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h index d4802f9914..bc3d40e667 100644 --- a/include/configs/colibri_pxa270.h +++ b/include/configs/colibri_pxa270.h @@ -21,7 +21,6 @@ */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SYS_MALLOC_LEN (128 * 1024) -#define CONFIG_ARCH_CPU_INIT #define CONFIG_BOOTCOMMAND \ "if fatload mmc 0 0xa0000000 uImage; then " \ "bootm 0xa0000000; " \ diff --git a/include/configs/controlcenterdc.h b/include/configs/controlcenterdc.h index 54bbfe3f55..f6d53284d7 100644 --- a/include/configs/controlcenterdc.h +++ b/include/configs/controlcenterdc.h @@ -97,7 +97,6 @@ #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH /* SPL related SPI defines */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x30000 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS #endif diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index e5c3a0c3f2..60e09c1939 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -54,7 +54,6 @@ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE @@ -362,68 +361,25 @@ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 -#endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#else -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 -#endif -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 -#endif -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull -#else -#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 -#endif -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#else -#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 -#endif -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* controller 4, Base address 203000 */ -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ /* Qman/Bman */ #define CONFIG_SYS_BMAN_NUM_PORTALS 10 @@ -499,7 +455,26 @@ #endif #ifdef CONFIG_PCI +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index b87b6b208b..41f0813a01 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -29,7 +29,6 @@ #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY #ifdef CONFIG_DIRECT_NOR_BOOT -#define CONFIG_ARCH_CPU_INIT #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) #endif @@ -111,7 +110,6 @@ #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) #ifdef CONFIG_USE_SPIFLASH -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 #endif @@ -131,7 +129,6 @@ #define CONFIG_ENV_SIZE (128 << 10) #define CONFIG_ENV_SECT_SIZE (128 << 10) #endif -#define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST #define CONFIG_SYS_NAND_PAGE_2K #define CONFIG_SYS_NAND_CS 3 @@ -211,7 +208,6 @@ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) -#define CONFIG_MX_CYCLIC /* * Linux Information diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h index fb1b899d71..4f99805ee2 100644 --- a/include/configs/dart_6ul.h +++ b/include/configs/dart_6ul.h @@ -55,7 +55,6 @@ #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ -#define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR #define CONFIG_SUPPORT_EMMC_BOOT diff --git a/include/configs/db-88f6281-bp.h b/include/configs/db-88f6281-bp.h index 97af9a6258..1b5541e49e 100644 --- a/include/configs/db-88f6281-bp.h +++ b/include/configs/db-88f6281-bp.h @@ -72,7 +72,6 @@ /* * Other required minimal configurations */ -#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ #define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ #define CONFIG_SYS_MEMTEST_END 0x007fffff /* (_8M - 1) */ #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ diff --git a/include/configs/db-88f6720.h b/include/configs/db-88f6720.h index a1780fa3da..79b9ccfaa0 100644 --- a/include/configs/db-88f6720.h +++ b/include/configs/db-88f6720.h @@ -73,7 +73,6 @@ #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) /* SPL related SPI defines */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS #endif /* _CONFIG_DB_88F6720_H */ diff --git a/include/configs/db-88f6820-amc.h b/include/configs/db-88f6820-amc.h index 5b59a92cb9..61b91dd91f 100644 --- a/include/configs/db-88f6820-amc.h +++ b/include/configs/db-88f6820-amc.h @@ -32,7 +32,6 @@ #endif /* NAND */ -#define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_ONFI_DETECTION /* Keep device tree and initrd in lower memory so the kernel can access them */ @@ -69,7 +68,6 @@ #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH /* SPL related SPI defines */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS #endif diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h index c98679e109..900c962679 100644 --- a/include/configs/db-88f6820-gp.h +++ b/include/configs/db-88f6820-gp.h @@ -85,7 +85,6 @@ #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH /* SPL related SPI defines */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS #endif diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index 6ed58ce91b..907bd0d032 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -46,7 +46,6 @@ #endif /* NAND */ -#define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_ONFI_DETECTION /* @@ -83,7 +82,6 @@ #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) /* SPL related SPI defines */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ diff --git a/include/configs/db-xc3-24g4xg.h b/include/configs/db-xc3-24g4xg.h index 0f75ad7185..86d11e40b1 100644 --- a/include/configs/db-xc3-24g4xg.h +++ b/include/configs/db-xc3-24g4xg.h @@ -22,7 +22,6 @@ #define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ /* NAND */ -#define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_ONFI_DETECTION /* Keep device tree and initrd in lower memory so the kernel can access them */ diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index c93a5deb99..16031c1da6 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -98,7 +98,6 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 #define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE -#define CONFIG_SYS_NAND_USE_FLASH_BBT /* * USB diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 7d2e573846..c516e6ed4c 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -23,7 +23,6 @@ /* SPL */ #include "imx6_spl.h" /* common IMX6 SPL configuration */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x11400 #define CONFIG_SPL_TARGET "u-boot-with-spl.imx" /* Miscellaneous configurable options */ @@ -49,7 +48,6 @@ #define CONFIG_ARP_TIMEOUT 200UL /* MMC Configs */ -#define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 3 #define CONFIG_SYS_MMC_ENV_DEV 2 /* 1 = SDHC3, 2 = SDHC4 (eMMC) */ diff --git a/include/configs/display5.h b/include/configs/display5.h index 1d3334ff12..e503e4a0ce 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -45,7 +45,6 @@ #define CONFIG_SYS_SPI_ARGS_SIZE 0x10000 #include "imx6_spl.h" -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS @@ -77,7 +76,6 @@ #endif /* MMC Configs */ -#define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 7ec6e691c7..3487b8ac1b 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -92,7 +92,6 @@ #endif /* SPI SPL */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 /* USB xHCI HOST */ #define CONFIG_USB_XHCI_OMAP diff --git a/include/configs/ds414.h b/include/configs/ds414.h index b175e9d574..552c7449d5 100644 --- a/include/configs/ds414.h +++ b/include/configs/ds414.h @@ -91,7 +91,6 @@ #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) /* SPL related SPI defines */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000 /* DS414 bus width is 32bits */ #define CONFIG_DDR_32BIT diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index a608c0f0a5..f071718944 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -183,7 +183,6 @@ /* * Other required minimal configurations */ -#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ #define CONFIG_SYS_LOAD_ADDR 0x00800000 #define CONFIG_SYS_MEMTEST_START 0x00400000 diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h index bf70ea0029..fe28154dc1 100644 --- a/include/configs/el6x_common.h +++ b/include/configs/el6x_common.h @@ -20,7 +20,6 @@ #define CONFIG_MXC_UART #ifdef CONFIG_SPL -#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) #include "imx6_spl.h" #endif diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index 24aaae5640..c9e7c8c0e2 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -20,7 +20,6 @@ #define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5 /* CPU information */ -#define CONFIG_ARCH_CPU_INIT /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ diff --git a/include/configs/evb_rk3399.h b/include/configs/evb_rk3399.h index a99eeab484..b9c4d683f4 100644 --- a/include/configs/evb_rk3399.h +++ b/include/configs/evb_rk3399.h @@ -8,7 +8,7 @@ #include <configs/rk3399_common.h> -#define CONFIG_SYS_MMC_ENV_DEV 1 +#define CONFIG_SYS_MMC_ENV_DEV 0 #define SDRAM_BANK_SIZE (2UL << 30) diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h index 752acc58d0..5ae2b427ca 100644 --- a/include/configs/exynos-common.h +++ b/include/configs/exynos-common.h @@ -15,7 +15,6 @@ #include <asm/arch/cpu.h> /* get chip and board defs */ #include <linux/sizes.h> -#define CONFIG_ARCH_CPU_INIT #define CONFIG_SKIP_LOWLEVEL_INIT /* Keep L2 Cache Disabled */ diff --git a/include/configs/exynos7420-common.h b/include/configs/exynos7420-common.h index 2885cd7092..157260ca03 100644 --- a/include/configs/exynos7420-common.h +++ b/include/configs/exynos7420-common.h @@ -16,8 +16,6 @@ #include <asm/arch/cpu.h> /* get chip and board defs */ #include <linux/sizes.h> -#define CONFIG_ARCH_CPU_INIT - /* Size of malloc() pool before and after relocation */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20)) diff --git a/include/configs/fennec_rk3288.h b/include/configs/fennec_rk3288.h deleted file mode 100644 index ddd7012c8f..0000000000 --- a/include/configs/fennec_rk3288.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define ROCKCHIP_DEVICE_SETTINGS -#include <configs/rk3288_common.h> - -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#endif diff --git a/include/configs/gose.h b/include/configs/gose.h index 0de0a362e3..fcb9f17750 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -40,7 +40,6 @@ /* SPL support */ #define CONFIG_SPL_STACK 0xe6340000 #define CONFIG_SPL_MAX_SIZE 0x4000 -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000 #ifdef CONFIG_SPL_BUILD #define CONFIG_CONS_SCIF0 #define CONFIG_SH_SCIF_CLK_FREQ 65000000 diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index b7271ab1f6..26ca6943b1 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -18,7 +18,6 @@ #define CONFIG_SYS_PBSIZE 256 #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH #define CONFIG_CMDLINE_TAG -#define CONFIG_ARCH_CPU_INIT /* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */ #define CONFIG_SYS_SDRAM_BASE 0x20000000 diff --git a/include/configs/helios4.h b/include/configs/helios4.h index e03d8409ad..4df32002e0 100644 --- a/include/configs/helios4.h +++ b/include/configs/helios4.h @@ -104,7 +104,6 @@ #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_LOAD #define CONFIG_SPL_SPI_SUPPORT -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x30000 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS #endif diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index dbf566522f..d6b7477ee9 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -144,7 +144,6 @@ #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00500000 -#define CONFIG_SYS_NAND_USE_FLASH_BBT /* MTD device */ diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index 16e4136fa9..c2113439c3 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -216,7 +216,6 @@ #define CONFIG_IMX_BOOTAUX #define CONFIG_CMD_MMC -#define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h index 8fdf677573..5a9fd57060 100644 --- a/include/configs/imx8qm_mek.h +++ b/include/configs/imx8qm_mek.h @@ -47,7 +47,6 @@ #undef CONFIG_CMD_CRC32 #undef CONFIG_BOOTM_NETBSD -#define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define USDHC1_BASE_ADDR 0x5B010000 #define USDHC2_BASE_ADDR 0x5B020000 diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index c1f193487e..02c4e9f8f6 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -46,7 +46,6 @@ #undef CONFIG_CMD_CRC32 #undef CONFIG_BOOTM_NETBSD -#define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define USDHC1_BASE_ADDR 0x5B010000 #define USDHC2_BASE_ADDR 0x5B020000 diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h index f8d4d7bdf8..5fe77ef16d 100644 --- a/include/configs/j721e_evm.h +++ b/include/configs/j721e_evm.h @@ -22,7 +22,6 @@ #ifdef CONFIG_TARGET_J721E_A72_EVM #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \ CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE) -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x280000 #else /* * Maximum size in memory allocated to the SPL BSS. Keep it as tight as @@ -45,7 +44,6 @@ /* Configure R5 SPL post-relocation malloc pool in DDR */ #define CONFIG_SYS_SPL_MALLOC_START 0x84000000 #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x80000 #endif #ifdef CONFIG_SYS_K3_SPL_ATF diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index d12d18770d..829a5c7825 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -77,7 +77,6 @@ /* * Other required minimal configurations */ -#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ /* * Ethernet Driver configuration diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index c42139dc3a..140076a54e 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -40,7 +40,6 @@ /* SPL support */ #define CONFIG_SPL_STACK 0xe6340000 #define CONFIG_SPL_MAX_SIZE 0x4000 -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000 #ifdef CONFIG_SPL_BUILD #define CONFIG_CONS_SCIF0 #define CONFIG_SH_SCIF_CLK_FREQ 65000000 diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h index dbae276121..2435ebbc7f 100644 --- a/include/configs/kp_imx6q_tpc.h +++ b/include/configs/kp_imx6q_tpc.h @@ -39,7 +39,6 @@ #define CONFIG_SYS_I2C_SPEED 100000 /* MMC Configs */ -#define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_MMC_ENV_DEV 1 /* 0 = SDHC2, 1 = SDHC4 (eMMC) */ diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index a2c8224da7..5a2b040225 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -12,8 +12,6 @@ #include <asm/arch/rmobile.h> -#define CONFIG_ARCH_CPU_INIT - #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG diff --git a/include/configs/lager.h b/include/configs/lager.h index 5acd5a2118..db1dbc0ee8 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -41,7 +41,6 @@ /* SPL support */ #define CONFIG_SPL_STACK 0xe6340000 #define CONFIG_SPL_MAX_SIZE 0x4000 -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000 #ifdef CONFIG_SPL_BUILD #define CONFIG_CONS_SCIF0 #define CONFIG_SH_SCIF_CLK_FREQ 65000000 diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index c97e6a0ebb..c1eeca0c60 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -60,7 +60,6 @@ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) -#define CONFIG_MX_CYCLIC /* * Linux Information diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index a6c7c3753d..40fcd22582 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -42,7 +42,9 @@ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) /* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C +#endif /* Serial Port */ #define CONFIG_CONS_INDEX 1 diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h index be018ef2be..b0e9441a48 100644 --- a/include/configs/ls1028aqds.h +++ b/include/configs/ls1028aqds.h @@ -16,7 +16,6 @@ #define CONFIG_DIMM_SLOTS_PER_CTLR 2 #define CONFIG_QIXIS_I2C_ACCESS -#define CONFIG_SYS_I2C_EARLY_INIT /* * QIXIS Definitions diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h index 10791be824..b77c36d279 100644 --- a/include/configs/ls1028ardb.h +++ b/include/configs/ls1028ardb.h @@ -22,7 +22,6 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_QIXIS_I2C_ACCESS -#define CONFIG_SYS_I2C_EARLY_INIT /* * QIXIS Definitions diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 0e4e370109..0ea3ca0332 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -382,7 +382,6 @@ unsigned long get_board_ddr_clk(void); /* QSPI device */ #if defined(CONFIG_TFABOOT) || \ (defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)) -#define CONFIG_FSL_QSPI #ifdef CONFIG_FSL_QSPI #define CONFIG_SPI_FLASH_SPANSION #define FSL_QSPI_FLASH_SIZE (1 << 24) diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h index 791bb8dc47..8609ebfecc 100644 --- a/include/configs/ls1046afrwy.h +++ b/include/configs/ls1046afrwy.h @@ -103,6 +103,9 @@ #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ #define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ +#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FSL_QSPI_BASE + \ + CONFIG_ENV_OFFSET) /* FMan */ #ifdef CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index e8e1dc2d92..6f04dbaccd 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -67,7 +67,10 @@ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) /* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C +#endif + /* Serial Port */ #define CONFIG_SYS_NS16550_SERIAL diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index 4387862582..85e20617e6 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -17,6 +17,8 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_TFABOOT #define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_MISC_INIT_R + #define CONFIG_ENV_SIZE 0x20000 #define CONFIG_ENV_OFFSET 0x500000 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ @@ -46,7 +48,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_DDR_CLK_FREQ 100000000 #else #define CONFIG_QIXIS_I2C_ACCESS +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C_EARLY_INIT +#endif #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() #endif @@ -357,9 +361,7 @@ unsigned long get_board_ddr_clk(void); * RTC configuration */ #define RTC -#define CONFIG_RTC_PCF8563 1 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ -#define CONFIG_CMD_DATE /* EEPROM */ #define CONFIG_ID_EEPROM diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index 322adb530a..b71f70426c 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -269,9 +269,7 @@ * RTC configuration */ #define RTC -#define CONFIG_RTC_PCF8563 1 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ -#define CONFIG_CMD_DATE #endif /* EEPROM */ diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index c7d8a3b6eb..6be581a229 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -75,7 +75,9 @@ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) /* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C +#endif /* Serial Port */ #define CONFIG_SYS_NS16550_SERIAL diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 18f30b585c..e2a897557d 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -16,7 +16,9 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_FSL_QSPI #define CONFIG_QIXIS_I2C_ACCESS +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C_EARLY_INIT +#endif #define CONFIG_SYS_I2C_IFDR_DIV 0x7e #endif @@ -324,7 +326,9 @@ unsigned long get_board_ddr_clk(void); */ #define RTC #define CONFIG_RTC_DS3231 1 +#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT #define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT /* EEPROM */ #define CONFIG_ID_EEPROM diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index bfb54be79b..2bf8217685 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -13,8 +13,10 @@ #ifdef CONFIG_TARGET_LS2081ARDB #define CONFIG_QIXIS_I2C_ACCESS #endif +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C_EARLY_INIT #endif +#endif #define I2C_MUX_CH_VOL_MONITOR 0xa #define I2C_VOL_MONITOR_ADDR 0x38 diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index a432259cfe..49f11ea4b8 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -70,7 +70,6 @@ #define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR #define CONFIG_SYS_NAND_LARGEPAGE #define CONFIG_MXC_NAND_HWECC -#define CONFIG_SYS_NAND_USE_FLASH_BBT /* Environment is in NAND */ #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h index a017d92cc9..9d5fbcd516 100644 --- a/include/configs/maxbcm.h +++ b/include/configs/maxbcm.h @@ -71,7 +71,6 @@ #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) /* SPL related SPI defines */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ #define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */ diff --git a/include/configs/meesc.h b/include/configs/meesc.h index aeab2e983b..3a173a2665 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -33,7 +33,6 @@ /* Misc CPU related */ #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_ARCH_CPU_INIT #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG #define CONFIG_SERIAL_TAG diff --git a/include/configs/mt7629.h b/include/configs/mt7629.h index 6e9b868aa4..741b6fbc1b 100644 --- a/include/configs/mt7629.h +++ b/include/configs/mt7629.h @@ -38,7 +38,6 @@ #define CONFIG_SPL_PAD_TO 0x10000 #define CONFIG_SPI_ADDR 0x30000000 -#define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO #define CONFIG_SYS_UBOOT_BASE (CONFIG_SPI_ADDR + CONFIG_SPL_PAD_TO) /* SPL -> Uboot */ diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index e6d5c680d7..a041ddb79b 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -58,7 +58,6 @@ /* * Other required minimal configurations */ -#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ #define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ #define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */ #define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */ diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h index ff8cc3c770..bc249039c8 100644 --- a/include/configs/mvebu_armada-37xx.h +++ b/include/configs/mvebu_armada-37xx.h @@ -37,7 +37,6 @@ /* * Other required minimal configurations */ -#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ #define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ #define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */ #define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */ diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h index f3f8538541..3be36833de 100644 --- a/include/configs/mvebu_armada-8k.h +++ b/include/configs/mvebu_armada-8k.h @@ -38,7 +38,6 @@ /* * Other required minimal configurations */ -#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ #define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ #define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */ #define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */ @@ -58,7 +57,6 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_SYS_NAND_USE_FLASH_BBT /* * Ethernet Driver configuration diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h index 46ff99b449..d25629f415 100644 --- a/include/configs/mx53ard.h +++ b/include/configs/mx53ard.h @@ -28,7 +28,6 @@ #define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR #define CONFIG_SYS_NAND_LARGEPAGE #define CONFIG_MXC_NAND_HWECC -#define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 2b8ce9d71d..f6c0e21d07 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -55,7 +55,6 @@ #define CONFIG_SYS_MAXARGS 32 /* MMC */ -#define CONFIG_FSL_USDHC /* Secure boot (HAB) support */ #ifdef CONFIG_SECURE_BOOT diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index 4f822ef9a0..70dda35eb0 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -40,7 +40,6 @@ #define CONFIG_MXC_UART /* MMC */ -#define CONFIG_FSL_USDHC #define CONFIG_ARMV7_SECURE_BASE 0x00900000 diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index 2af5a4fe3e..763a46b47f 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -27,8 +27,6 @@ #define IRAM_BASE_ADDR OCRAM_0_BASE #define IOMUXC_BASE_ADDR IOMUXC1_RBASE -#define CONFIG_FSL_USDHC - #define CONFIG_SYS_FSL_USDHC_NUM 1 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/mxs.h b/include/configs/mxs.h index cc5d4c85fe..6cadd720d2 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -94,12 +94,6 @@ /* * Drivers */ - -/* APBH DMA */ - -/* GPIO */ -#define CONFIG_MXS_GPIO - /* * DUART Serial Driver. * Conflicts with AUART driver which can be set by board. diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index b7c3ddf564..90292ae312 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -30,6 +30,9 @@ /* I2C */ #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */ +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_USB_EHCI_OMAP +#endif #ifdef CONFIG_USB_EHCI_OMAP #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 4 #endif diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index d4f404a78b..cab402a484 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -116,7 +116,6 @@ #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) #ifdef CONFIG_USE_SPIFLASH -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000 #endif @@ -133,7 +132,6 @@ #ifdef CONFIG_NAND #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ #define CONFIG_ENV_SIZE (128 << 9) -#define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST #define CONFIG_SYS_NAND_PAGE_2K #define CONFIG_SYS_NAND_CS 3 @@ -206,7 +204,6 @@ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) -#define CONFIG_MX_CYCLIC /* * USB Configs diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h index 7dfcccb82b..4efef892a8 100644 --- a/include/configs/ot1200.h +++ b/include/configs/ot1200.h @@ -59,7 +59,6 @@ /* SPL */ #ifdef CONFIG_SPL #include "imx6_spl.h" -#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) #endif #define CONFIG_FEC_MXC diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index e07d2a178f..1481d683e5 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -207,8 +207,6 @@ #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE @@ -572,44 +570,56 @@ */ /* controller 2, direct to uli, tgtid 2, Base address 9000 */ -#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 #endif -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull #else #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 #endif -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 2, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull #else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 #endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull #else #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 #endif + +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 +#else +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#endif +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#endif +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h index 8fef250ac4..943fca9377 100644 --- a/include/configs/pcl063.h +++ b/include/configs/pcl063.h @@ -31,7 +31,6 @@ #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ -#define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h index 0f1a010b4e..650caaa573 100644 --- a/include/configs/pcl063_ull.h +++ b/include/configs/pcl063_ull.h @@ -37,7 +37,6 @@ #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ -#define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR #define CONFIG_SUPPORT_EMMC_BOOT diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h index 153e567c2f..fdbc07575c 100644 --- a/include/configs/pcm051.h +++ b/include/configs/pcm051.h @@ -117,7 +117,6 @@ /* CPU */ #ifdef CONFIG_SPI_BOOT -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 #endif diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h index b0415b28ad..855bc445fe 100644 --- a/include/configs/pcm058.h +++ b/include/configs/pcm058.h @@ -8,7 +8,6 @@ #define __PCM058_CONFIG_H #ifdef CONFIG_SPL -#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) #include "imx6_spl.h" #endif @@ -51,7 +50,6 @@ #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_SYS_NAND_USE_FLASH_BBT #endif /* DMA stuff, needed for GPMI/MXS NAND support */ diff --git a/include/configs/pfla02.h b/include/configs/pfla02.h index 3a9b85acd8..8731d89af2 100644 --- a/include/configs/pfla02.h +++ b/include/configs/pfla02.h @@ -8,7 +8,6 @@ #define __PCM058_CONFIG_H #ifdef CONFIG_SPL -#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) #include "imx6_spl.h" #endif diff --git a/include/configs/phycore_am335x_r2.h b/include/configs/phycore_am335x_r2.h index 78d265d1d2..ca28b6ff1b 100644 --- a/include/configs/phycore_am335x_r2.h +++ b/include/configs/phycore_am335x_r2.h @@ -119,7 +119,6 @@ /* CPU */ #ifdef CONFIG_SPI_BOOT -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 #elif defined(CONFIG_ENV_IS_IN_NAND) #define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index c1ce12217a..99ca1f730e 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -26,7 +26,6 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261" -#define CONFIG_ARCH_CPU_INIT #define CONFIG_MACH_TYPE MACH_TYPE_PM9261 diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index b09d8515d3..595acf1b94 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -26,7 +26,6 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263" -#define CONFIG_ARCH_CPU_INIT #define CONFIG_MACH_TYPE MACH_TYPE_PM9263 diff --git a/include/configs/porter.h b/include/configs/porter.h index 1db28869cd..db42176d28 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -45,7 +45,6 @@ /* SPL support */ #define CONFIG_SPL_STACK 0xe6340000 #define CONFIG_SPL_MAX_SIZE 0x4000 -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000 #ifdef CONFIG_SPL_BUILD #define CONFIG_CONS_SCIF0 #define CONFIG_SH_SCIF_CLK_FREQ 65000000 diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index ecea1d4765..fa9b9af934 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -8,6 +8,18 @@ #include <linux/sizes.h> +#ifdef CONFIG_SPL + +#define CONFIG_SPL_MAX_SIZE 0x00100000 +#define CONFIG_SPL_BSS_START_ADDR 0x84000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 +#define CONFIG_SYS_SPL_MALLOC_START 0x84100000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 + +#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80200000 + +#endif + #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) @@ -22,6 +34,7 @@ /* Environment options */ #define CONFIG_ENV_SIZE SZ_128K +#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(QEMU, qemu, na) \ func(VIRTIO, virtio, 0) \ @@ -47,5 +60,6 @@ "pxefile_addr_r=0x88200000\0" \ "ramdisk_addr_r=0x88300000\0" \ BOOTENV +#endif #endif /* __CONFIG_H */ diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index 146a30b4c2..71a5909045 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -18,8 +18,6 @@ #define CONFIG_SPL_TARGET "spl/u-boot-spl.srec" #endif -#define CONFIG_ARCH_CPU_INIT - #ifndef CONFIG_PINCTRL_PFC #define CONFIG_SH_GPIO_PFC #endif diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 11bf16b054..95bd97c0ec 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -23,8 +23,6 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG -#define CONFIG_ARCH_CPU_INIT - /* Generic Interrupt Controller Definitions */ #define CONFIG_GICV2 #define GICD_BASE 0xF1010000 diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index 66331a1376..7f148eff87 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -8,7 +8,6 @@ #include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h index d12696d6b3..d0c9e5c809 100644 --- a/include/configs/rk3128_common.h +++ b/include/configs/rk3128_common.h @@ -10,7 +10,6 @@ #define CONFIG_SYS_MAXARGS 16 #define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT @@ -27,7 +26,6 @@ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ /* RAW SD card / eMMC locations. */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10) #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SYS_SDRAM_BASE 0x60000000 diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index 44e8d0ccd2..3bcc04808a 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -12,7 +12,6 @@ #include "rockchip-common.h" #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index f2fb7e07b9..7e0c831174 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -9,7 +9,6 @@ #include "rockchip-common.h" #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 84b474ac7b..bcda769af5 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -12,7 +12,6 @@ #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* 16MB */ #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_ROCKCHIP_STIMER_BASE 0xff810020 @@ -30,7 +29,6 @@ #define CONFIG_IRAM_BASE 0xff700000 /* RAW SD card / eMMC locations. */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10) /* FAT sd card locations. */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 6ed7525304..3ff3331c80 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -12,7 +12,6 @@ #define CONFIG_ROCKCHIP_STIMER_BASE 0xff1d0020 -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT @@ -25,8 +24,6 @@ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10) - /* FAT sd card locations. */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SYS_SDRAM_BASE 0 diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index 340413dbba..e4b2114a0d 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -16,7 +16,6 @@ #define CONFIG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 #define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 12ad60d443..126c34763e 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -8,7 +8,6 @@ #include "rockchip-common.h" -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT @@ -39,7 +38,6 @@ #define CONFIG_ROCKCHIP_SDHCI_MAX_FREQ 200000000 /* RAW SD card / eMMC locations. */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10) /* FAT sd card locations. */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 diff --git a/include/configs/rpi.h b/include/configs/rpi.h index e706bea8cc..8473cecd94 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -14,7 +14,6 @@ #endif /* Architecture, CPU, etc.*/ -#define CONFIG_ARCH_CPU_INIT /* Use SoC timer for AArch32, but architected timer for AArch64 */ #ifndef CONFIG_ARM64 diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h index 691aa51e98..758e85e89d 100644 --- a/include/configs/rv1108_common.h +++ b/include/configs/rv1108_common.h @@ -10,7 +10,6 @@ #define CONFIG_IRAM_BASE 0x10080000 -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT diff --git a/include/configs/s32v234evb.h b/include/configs/s32v234evb.h index 216932046b..cc6d920637 100644 --- a/include/configs/s32v234evb.h +++ b/include/configs/s32v234evb.h @@ -65,7 +65,6 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_SYS_UART_PORT (1) -#define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC_BASE_ADDR #define CONFIG_SYS_FSL_ESDHC_NUM 1 diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index ff634d91dd..be6f011ab0 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -18,8 +18,6 @@ #include <linux/sizes.h> #include <asm/arch/cpu.h> /* get chip and board defs */ -#define CONFIG_ARCH_CPU_INIT - /* input clock of PLL: has 24MHz input clock at S5PC110 */ #define CONFIG_SYS_CLK_FREQ_C110 24000000 diff --git a/include/configs/sama5d27_som1_ek.h b/include/configs/sama5d27_som1_ek.h index 90846c4bfd..9b33acd40d 100644 --- a/include/configs/sama5d27_som1_ek.h +++ b/include/configs/sama5d27_som1_ek.h @@ -62,8 +62,4 @@ #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #endif -#ifdef CONFIG_QSPI_BOOT -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000 -#endif - #endif diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h index 3dea359127..487339594e 100644 --- a/include/configs/sama5d2_xplained.h +++ b/include/configs/sama5d2_xplained.h @@ -69,10 +69,6 @@ #ifdef CONFIG_SD_BOOT #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#elif CONFIG_SPI_BOOT -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000 - #endif #endif diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index db840e927e..3a712b51bd 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -83,10 +83,6 @@ #ifdef CONFIG_SD_BOOT #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#elif CONFIG_SPI_BOOT -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000 - #elif CONFIG_NAND_BOOT #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_BASE diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h index 5e6f59f756..1773412819 100644 --- a/include/configs/sama5d4_xplained.h +++ b/include/configs/sama5d4_xplained.h @@ -47,11 +47,6 @@ #ifdef CONFIG_SD_BOOT #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#elif CONFIG_SYS_USE_NANDFLASH -#elif CONFIG_SPI_BOOT -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000 - #elif CONFIG_NAND_BOOT #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_BASE diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h index c1f22f7016..6cf07a1127 100644 --- a/include/configs/sama5d4ek.h +++ b/include/configs/sama5d4ek.h @@ -47,10 +47,6 @@ #ifdef CONFIG_SD_BOOT #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#elif CONFIG_SPI_BOOT -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000 - #elif CONFIG_NAND_BOOT #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_BASE diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index dd63adb6db..ea6cc38fc1 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -94,8 +94,6 @@ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 - #define CONFIG_SPL_NAND_BASE #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC diff --git a/include/configs/silk.h b/include/configs/silk.h index c42b57ab2a..a78da46a17 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -45,7 +45,6 @@ /* SPL support */ #define CONFIG_SPL_STACK 0xe6340000 #define CONFIG_SPL_MAX_SIZE 0x4000 -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000 #ifdef CONFIG_SPL_BUILD #define CONFIG_CONS_SCIF2 #define CONFIG_SH_SCIF_CLK_FREQ 65000000 diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index b934ee70d5..1d09792ce9 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -21,8 +21,6 @@ #include <asm/arch/cpu.h> /* get chip and board defs */ -#define CONFIG_ARCH_CPU_INIT - /* input clock of PLL: SMDKC100 has 12MHz input clock */ #define CONFIG_SYS_CLK_FREQ 12000000 diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h index 7c2c5fb6ca..b0408a5592 100644 --- a/include/configs/snapper9260.h +++ b/include/configs/snapper9260.h @@ -19,7 +19,6 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* CPU */ -#define CONFIG_ARCH_CPU_INIT #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 36b0ed5459..b11fe021a7 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -213,13 +213,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #endif /* SPL QSPI boot support */ -#ifdef CONFIG_SPL_SPI_SUPPORT -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x100000 -#endif -#endif /* SPL NAND boot support */ #ifdef CONFIG_SPL_NAND_SUPPORT diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h index 90ad8172e2..7b55dd14da 100644 --- a/include/configs/socfpga_stratix10_socdk.h +++ b/include/configs/socfpga_stratix10_socdk.h @@ -201,7 +201,6 @@ unsigned int cm_get_l4_sys_free_clk_hz(void); #define CONFIG_SYS_SPL_MALLOC_SIZE (CONFIG_SYS_MALLOC_LEN) #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR \ - CONFIG_SYS_SPL_MALLOC_SIZE) -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x3C00000 /* SPL SDMMC boot support */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index ea5996fe1e..d21ff97716 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -150,7 +150,6 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Miscellaneous configurable options */ -#define CONFIG_ARCH_CPU_INIT #define CONFIG_BOOT_PARAMS_ADDR 0x00000100 #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h index 24f7b9d463..92660fe2a0 100644 --- a/include/configs/stm32mp1.h +++ b/include/configs/stm32mp1.h @@ -10,11 +10,6 @@ #include <linux/sizes.h> #include <asm/arch/stm32.h> -/* - * Number of clock ticks in 1 sec - */ -#define CONFIG_SYS_HZ 1000 - #ifndef CONFIG_STM32MP1_TRUSTED /* PSCI support */ #define CONFIG_ARMV7_PSCI_1_0 @@ -52,7 +47,6 @@ /* SPL support */ #ifdef CONFIG_SPL -/* BOOTROM load address */ /* SPL use DDR */ #define CONFIG_SPL_BSS_START_ADDR 0xC0200000 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 @@ -85,7 +79,9 @@ #endif /* Dynamic MTD partition support */ +#if defined(CONFIG_STM32_QSPI) || defined(CONFIG_NAND_STM32_FMC2) #define CONFIG_SYS_MTDPARTS_RUNTIME +#endif /*****************************************************************************/ #ifdef CONFIG_DISTRO_DEFAULTS @@ -146,6 +142,7 @@ * and the ramdisk at the end. */ #define CONFIG_EXTRA_ENV_SETTINGS \ + "bootdelay=1\0" \ "kernel_addr_r=0xc2000000\0" \ "fdt_addr_r=0xc4000000\0" \ "scriptaddr=0xc4100000\0" \ @@ -154,7 +151,8 @@ "ramdisk_addr_r=0xc4400000\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ - "env_default=1\0" \ + "altbootcmd=run bootcmd\0" \ + "env_default=1\0" \ "env_check=if test $env_default -eq 1;"\ " then env set env_default 0;env save;fi\0" \ STM32MP_BOOTCMD \ diff --git a/include/configs/stout.h b/include/configs/stout.h index 4a465e01bd..67345958be 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -49,7 +49,6 @@ /* SPL support */ #define CONFIG_SPL_STACK 0xe6340000 #define CONFIG_SPL_MAX_SIZE 0x4000 -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000 #ifdef CONFIG_SPL_BUILD #define CONFIG_CONS_SCIFA0 #define CONFIG_SH_SCIF_CLK_FREQ 52000000 diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index d7133a73fc..0ef289fd64 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -118,10 +118,6 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 8 #endif -#ifdef CONFIG_SPL_SPI_SUNXI -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 -#endif - /* mmc config */ #ifdef CONFIG_MMC #define CONFIG_MMC_SUNXI_SLOT 0 diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 36a41fff18..fdd1c5224b 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -33,7 +33,6 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */ /* Misc CPU related */ -#define CONFIG_ARCH_CPU_INIT #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG @@ -103,7 +102,6 @@ #if defined(CONFIG_SPL_BUILD) /* SPL related */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #endif /* load address */ diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h index 3562a14261..45cd7e2b83 100644 --- a/include/configs/theadorable.h +++ b/include/configs/theadorable.h @@ -106,7 +106,6 @@ #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) /* SPL related SPI defines */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x1a000 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index 90b424f499..46b1b41ef9 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -116,7 +116,6 @@ #define CONFIG_SYS_NS16550_COM1 0x48020000 /* Base EVM has UART0 */ /* CPU */ -#define CONFIG_ARCH_CPU_INIT #define CONFIG_ENV_OVERWRITE @@ -130,7 +129,6 @@ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 /* diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index 0b9930e884..19e1e2249e 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -11,7 +11,6 @@ #ifndef __CONFIG_TI_AM335X_COMMON_H__ #define __CONFIG_TI_AM335X_COMMON_H__ -#define CONFIG_ARCH_CPU_INIT #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 03753c5b52..d7bb1efcbf 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -15,7 +15,6 @@ #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */ /* SoC Configuration */ -#define CONFIG_ARCH_CPU_INIT #define CONFIG_SPL_TARGET "u-boot-spi.gph" /* Memory Configuration */ @@ -44,7 +43,6 @@ CONFIG_SYS_SPL_MALLOC_SIZE + \ SPL_MALLOC_F_SIZE + \ KEYSTONE_SPL_STACK_SIZE - 4) -#define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO /* SRAM scratch space entries */ #define SRAM_SCRATCH_SPACE_ADDR CONFIG_SPL_STACK + 0x8 @@ -154,7 +152,6 @@ #define CONFIG_SYS_NAND_MASK_CLE 0x4000 #define CONFIG_SYS_NAND_MASK_ALE 0x2000 #define CONFIG_SYS_NAND_CS 2 -#define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST #define CONFIG_SYS_NAND_LARGEPAGE @@ -175,7 +172,6 @@ DFU_ALT_INFO_MMC \ /* U-Boot general configuration */ -#define CONFIG_MX_CYCLIC #define CONFIG_TIMESTAMP /* EDMA3 */ diff --git a/include/configs/topic_miami.h b/include/configs/topic_miami.h index a915c32607..b98656dd4c 100644 --- a/include/configs/topic_miami.h +++ b/include/configs/topic_miami.h @@ -22,8 +22,6 @@ /* SPL settings */ #undef CONFIG_SPL_ETH_SUPPORT -#undef CONFIG_SYS_SPI_U_BOOT_OFFS -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #undef CONFIG_SPL_MAX_FOOTPRINT #define CONFIG_SPL_MAX_FOOTPRINT CONFIG_SYS_SPI_U_BOOT_OFFS #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/turris_mox.h b/include/configs/turris_mox.h index 7d5f5fa409..16a49c766f 100644 --- a/include/configs/turris_mox.h +++ b/include/configs/turris_mox.h @@ -44,7 +44,6 @@ /* * Other required minimal configurations */ -#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ #define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ #define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */ #define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */ diff --git a/include/configs/turris_omnia.h b/include/configs/turris_omnia.h index edd776ec70..abe1e99acd 100644 --- a/include/configs/turris_omnia.h +++ b/include/configs/turris_omnia.h @@ -50,7 +50,6 @@ #ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI /* SPL related SPI defines */ -# define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000 # define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS #endif diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h index ee72354dd5..c0ba647d09 100644 --- a/include/configs/usb_a9263.h +++ b/include/configs/usb_a9263.h @@ -22,8 +22,6 @@ #define CONFIG_MACH_TYPE MACH_TYPE_USB_A9263 -#define CONFIG_ARCH_CPU_INIT - #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 89cd8b550a..b2c14f9e10 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -11,14 +11,12 @@ #ifndef CONFIG_SEMIHOSTING #error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING #endif -#define CONFIG_ARMV8_SWITCH_TO_EL1 #endif #define CONFIG_REMAKE_ELF /* Link Definitions */ -#if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \ - defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM) +#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP /* ATF loads u-boot here for BASE_FVP model */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) #elif CONFIG_TARGET_VEXPRESS64_JUNO @@ -84,8 +82,7 @@ #define GICR_BASE (0x2f100000) #else -#if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \ - defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM) +#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP #define GICD_BASE (0x2f000000) #define GICC_BASE (0x2c000000) #elif CONFIG_TARGET_VEXPRESS64_JUNO @@ -192,17 +189,6 @@ "booti $kernel_addr - $fdt_addr" -#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_addr=0x80080000\0" \ - "initrd_addr=0x84000000\0" \ - "fdt_addr=0x83000000\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" - -#define CONFIG_BOOTCOMMAND "booti $kernel_addr $initrd_addr $fdt_addr" - - #endif /* Monitor Command Prompt */ diff --git a/include/configs/wb50n.h b/include/configs/wb50n.h index 81d30a6114..6e471f62e6 100644 --- a/include/configs/wb50n.h +++ b/include/configs/wb50n.h @@ -12,8 +12,6 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ -#define CONFIG_ARCH_CPU_INIT - #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG diff --git a/include/configs/x530.h b/include/configs/x530.h index 80ae15bd4e..2269d1ed8c 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -39,7 +39,6 @@ /* NAND */ #define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define BBT_CUSTOM_SCAN @@ -74,7 +73,6 @@ #endif /* NAND */ -#define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_ONFI_DETECTION #define CONFIG_CMD_UBI #define CONFIG_CMD_UBIFS @@ -89,7 +87,6 @@ /* * Other required minimal configurations */ -#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ #define CONFIG_SYS_ALT_MEMTEST @@ -120,8 +117,6 @@ #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) /* SPL related SPI defines */ -#define CONFIG_SPL_SPI_LOAD -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS #endif /* _CONFIG_X530_H */ diff --git a/include/configs/x600.h b/include/configs/x600.h index c893752dcd..d4bbdcdb13 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -96,11 +96,9 @@ #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) /* Miscellaneous configurable options */ -#define CONFIG_ARCH_CPU_INIT #define CONFIG_BOOT_PARAMS_ADDR 0x00000100 #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ #define CONFIG_SYS_MEMTEST_START 0x00800000 #define CONFIG_SYS_MEMTEST_END 0x04000000 diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index bbcb20737b..a1c55a8306 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -217,8 +217,6 @@ # define CONFIG_SYS_SPI_KERNEL_OFFS 0x80000 # define CONFIG_SYS_SPI_ARGS_OFFS 0xa0000 # define CONFIG_SYS_SPI_ARGS_SIZE 0xa0000 - -# define CONFIG_SYS_SPI_U_BOOT_OFFS 0x170000 #endif /* u-boot is like dtb */ diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h index b8de931d2c..2f20273572 100644 --- a/include/configs/xtfpga.h +++ b/include/configs/xtfpga.h @@ -119,8 +119,6 @@ /* U-Boot autoboot configuration */ /*==============================*/ -#define CONFIG_MX_CYCLIC - /*=========================================*/ /* FPGA Registers (board info and control) */ diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index bb6a835ece..ae08ebf2af 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -293,7 +293,6 @@ /* qspi mode is working fine */ #ifdef CONFIG_ZYNQ_QSPI -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x100000 #define CONFIG_SYS_SPI_ARGS_OFFS 0x200000 #define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 #define CONFIG_SYS_SPI_KERNEL_OFFS (CONFIG_SYS_SPI_ARGS_OFFS + \ diff --git a/include/dm/platform_data/serial_stm32.h b/include/dm/platform_data/serial_stm32.h deleted file mode 100644 index 85153df527..0000000000 --- a/include/dm/platform_data/serial_stm32.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 - * Kamil Lulko, <kamil.lulko@gmail.com> - */ - -#ifndef __SERIAL_STM32_H -#define __SERIAL_STM32_H - -/* Information about a serial port */ -struct stm32_serial_platdata { - struct stm32_usart *base; /* address of registers in physical memory */ -}; - -#endif /* __SERIAL_STM32_H */ diff --git a/include/environment/ti/mmc.h b/include/environment/ti/mmc.h index 785fc15345..ef05376608 100644 --- a/include/environment/ti/mmc.h +++ b/include/environment/ti/mmc.h @@ -56,7 +56,7 @@ "bootz; " \ "fi;\0" \ "mmcboot=mmc dev ${mmcdev}; " \ - "setenv devnum ${mmcdev}; " \ + "devnum ${mmcdev}; " \ "setenv devtype mmc; " \ "if mmc rescan; then " \ "echo SD/MMC found on device ${mmcdev};" \ diff --git a/include/fdtdec.h b/include/fdtdec.h index e6c22dd5cd..635f53083b 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -54,7 +54,7 @@ struct bd_info; #define SPL_BUILD 0 #endif -#if CONFIG_IS_ENABLED(OF_PRIOR_STAGE) +#ifdef CONFIG_OF_PRIOR_STAGE extern phys_addr_t prior_stage_fdt_address; #endif diff --git a/include/fsl-mc/fsl_mc.h b/include/fsl-mc/fsl_mc.h index 0abd797cc4..a4d7d85fce 100644 --- a/include/fsl-mc/fsl_mc.h +++ b/include/fsl-mc/fsl_mc.h @@ -55,6 +55,7 @@ void fdt_fsl_mc_fixup_iommu_map_entry(void *blob); int get_mc_boot_status(void); int get_dpl_apply_status(void); int is_lazy_dpl_addr_valid(void); +void fdt_fixup_mc_ddr(u64 *base, u64 *size); #ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET int get_aiop_apply_status(void); #endif diff --git a/include/image.h b/include/image.h index 27d7cb9d1e..c1065c06f9 100644 --- a/include/image.h +++ b/include/image.h @@ -156,6 +156,7 @@ enum { IH_OS_OPENRTOS, /* OpenRTOS */ IH_OS_ARM_TRUSTED_FIRMWARE, /* ARM Trusted Firmware */ IH_OS_TEE, /* Trusted Execution Environment */ + IH_OS_OPENSBI, /* RISC-V OpenSBI */ IH_OS_COUNT, }; @@ -283,6 +284,7 @@ enum { IH_TYPE_MTKIMAGE, /* MediaTek BootROM loadable Image */ IH_TYPE_IMX8MIMAGE, /* Freescale IMX8MBoot Image */ IH_TYPE_IMX8IMAGE, /* Freescale IMX8Boot Image */ + IH_TYPE_COPRO, /* Coprocessor Image for remoteproc*/ IH_TYPE_COUNT, /* Number of image types */ }; diff --git a/include/opensbi.h b/include/opensbi.h new file mode 100644 index 0000000000..9f1d62e7dd --- /dev/null +++ b/include/opensbi.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ +/* + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * + * Based on include/sbi/{fw_dynamic.h,sbi_scratch.h} from the OpenSBI project. + */ +#ifndef OPENSBI_H +#define OPENSBI_H + +/** Expected value of info magic ('OSBI' ascii string in hex) */ +#define FW_DYNAMIC_INFO_MAGIC_VALUE 0x4942534f + +/** Maximum supported info version */ +#define FW_DYNAMIC_INFO_VERSION 0x1 + +/** Possible next mode values */ +#define FW_DYNAMIC_INFO_NEXT_MODE_U 0x0 +#define FW_DYNAMIC_INFO_NEXT_MODE_S 0x1 +#define FW_DYNAMIC_INFO_NEXT_MODE_M 0x3 + +enum sbi_scratch_options { + /** Disable prints during boot */ + SBI_SCRATCH_NO_BOOT_PRINTS = (1 << 0), +}; + +/** Representation dynamic info passed by previous booting stage */ +struct fw_dynamic_info { + /** Info magic */ + unsigned long magic; + /** Info version */ + unsigned long version; + /** Next booting stage address */ + unsigned long next_addr; + /** Next booting stage mode */ + unsigned long next_mode; + /** Options for OpenSBI library */ + unsigned long options; +} __packed; + +#endif diff --git a/include/part_efi.h b/include/part_efi.h index 7170b61c95..eb5797af74 100644 --- a/include/part_efi.h +++ b/include/part_efi.h @@ -25,6 +25,8 @@ #define EFI_PMBR_OSTYPE_EFI_GPT 0xEE #define GPT_HEADER_SIGNATURE_UBOOT 0x5452415020494645ULL +#define GPT_HEADER_CHROMEOS_IGNORE 0x454d45524f4e4749ULL // 'IGNOREME' + #define GPT_HEADER_REVISION_V1 0x00010000 #define GPT_PRIMARY_PARTITION_TABLE_LBA 1ULL #define GPT_ENTRY_NUMBERS CONFIG_EFI_PARTITION_ENTRIES_NUMBERS diff --git a/include/power/stpmic1.h b/include/power/stpmic1.h index 0e6721d852..dc8b5a7459 100644 --- a/include/power/stpmic1.h +++ b/include/power/stpmic1.h @@ -22,11 +22,12 @@ /* BUCKS_MRST_CR */ #define STPMIC1_MRST_BUCK(buck) BIT(buck) -#define STPMIC1_MRST_BUCK_ALL GENMASK(3, 0) +#define STPMIC1_MRST_BUCK_DEBUG (STPMIC1_MRST_BUCK(STPMIC1_BUCK1) | \ + STPMIC1_MRST_BUCK(STPMIC1_BUCK3)) /* LDOS_MRST_CR */ #define STPMIC1_MRST_LDO(ldo) BIT(ldo) -#define STPMIC1_MRST_LDO_ALL GENMASK(6, 0) +#define STPMIC1_MRST_LDO_DEBUG 0 /* BUCKx_MAIN_CR (x=1...4) */ #define STPMIC1_BUCK_ENA BIT(0) @@ -107,11 +108,4 @@ enum { STPMIC1_PWR_SW2, STPMIC1_MAX_PWR_SW, }; - -int stpmic1_shadow_read_byte(u8 addr, u8 *buf); -int stpmic1_shadow_write_byte(u8 addr, u8 *buf); -int stpmic1_nvm_read_byte(u8 addr, u8 *buf); -int stpmic1_nvm_write_byte(u8 addr, u8 *buf); -int stpmic1_nvm_read_all(u8 *buf, int buf_len); -int stpmic1_nvm_write_all(u8 *buf, int buf_len); #endif diff --git a/include/rtc.h b/include/rtc.h index b255bdc7a3..7386d52db1 100644 --- a/include/rtc.h +++ b/include/rtc.h @@ -166,11 +166,17 @@ int rtc_read32(struct udevice *dev, unsigned int reg, u32 *valuep); */ int rtc_write32(struct udevice *dev, unsigned int reg, u32 value); +#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT +int rtc_enable_32khz_output(int busnum, int chip_addr); +#endif + #else int rtc_get (struct rtc_time *); int rtc_set (struct rtc_time *); void rtc_reset (void); +#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT void rtc_enable_32khz_output(void); +#endif /** * rtc_read8() - Read an 8-bit register diff --git a/include/sandbox-clk.h b/include/sandbox-clk.h index f449de1364..296cddfbb0 100644 --- a/include/sandbox-clk.h +++ b/include/sandbox-clk.h @@ -20,6 +20,7 @@ enum { SANDBOX_CLK_USDHC1_SEL, SANDBOX_CLK_USDHC2_SEL, SANDBOX_CLK_I2C, + SANDBOX_CLK_I2C_ROOT, }; enum sandbox_pllv3_type { @@ -74,4 +75,6 @@ static inline struct clk *sandbox_clk_mux(const char *name, void __iomem *reg, width, 0); } +int sandbox_clk_enable_count(struct clk *clk); + #endif /* __SANDBOX_CLK_H__ */ diff --git a/include/spl.h b/include/spl.h index a90f971a23..e4640f3830 100644 --- a/include/spl.h +++ b/include/spl.h @@ -375,6 +375,11 @@ void spl_invoke_atf(struct spl_image_info *spl_image); void spl_optee_entry(void *arg0, void *arg1, void *arg2, void *arg3); /** + * spl_invoke_opensbi - boot using a RISC-V OpenSBI image + */ +void spl_invoke_opensbi(struct spl_image_info *spl_image); + +/** * board_return_to_bootrom - allow for boards to continue with the boot ROM * * If a board (e.g. the Rockchip RK3368 boards) provide some diff --git a/include/video_logo.h b/include/video_logo.h deleted file mode 100644 index a0d2da4302..0000000000 --- a/include/video_logo.h +++ /dev/null @@ -1,1951 +0,0 @@ -/* */ -/* Generated by EasyLogo, (C) 2000 by Paolo Scaffardi */ -/* */ -/* To use this, include it and call: easylogo_plot(screen,&u_boot_logo, width,x,y) */ -/* */ -/* Where: 'screen' is the pointer to the frame buffer */ -/* 'width' is the screen width */ -/* 'x' is the horizontal position */ -/* 'y' is the vertical position */ -/* */ - -#include <video_easylogo.h> - -#define DEF_U_BOOT_LOGO_WIDTH 160 -#define DEF_U_BOOT_LOGO_HEIGHT 96 -#define DEF_U_BOOT_LOGO_PIXELS 15360 -#define DEF_U_BOOT_LOGO_BPP 16 -#define DEF_U_BOOT_LOGO_PIXEL_SIZE 2 -#define DEF_U_BOOT_LOGO_SIZE 30720 - -unsigned char DEF_U_BOOT_LOGO_DATA[DEF_U_BOOT_LOGO_SIZE] = { - 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, - 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, - 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 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0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, - 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7e, 0xaa, 0x7a, 0x3f, 0x7e, 0xa0, 0x80, 0xe1, - 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0x4b, 0x7a, 0x3f, 0x80, 0xe1, - 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, - 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, - 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, - 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, - 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x4b, 0x7c, 0x69, - 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, - 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, - 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, - 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, - 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, - 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, - 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, - 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, - 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, - 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, - 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, - 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, - 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, - 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7d, 0x80, 0x7a, 0x3f, 0x7a, 0x3f, - 0x7a, 0x3f, 0x7c, 0x69, 0x7b, 0x60, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1 -}; - -fastimage_t u_boot_logo = { - DEF_U_BOOT_LOGO_DATA, - DEF_U_BOOT_LOGO_WIDTH, - DEF_U_BOOT_LOGO_HEIGHT, - DEF_U_BOOT_LOGO_BPP, - DEF_U_BOOT_LOGO_PIXEL_SIZE, - DEF_U_BOOT_LOGO_SIZE -}; diff --git a/lib/efi_selftest/Makefile b/lib/efi_selftest/Makefile index 5d7a1643ef..8348014077 100644 --- a/lib/efi_selftest/Makefile +++ b/lib/efi_selftest/Makefile @@ -20,7 +20,6 @@ efi_selftest_crc32.o \ efi_selftest_devicepath_util.o \ efi_selftest_events.o \ efi_selftest_event_groups.o \ -efi_selftest_exception.o \ efi_selftest_exitbootservices.o \ efi_selftest_gop.o \ efi_selftest_loaded_image.o \ @@ -55,21 +54,28 @@ ifeq ($(CONFIG_BLK)$(CONFIG_PARTITIONS),yy) obj-y += efi_selftest_block_device.o endif -# TODO: As of v2019.01 the relocation code for the EFI application cannot -# be built on ARMv7-M, Sandbox, and x86_64. -ifeq ($(CONFIG_SANDBOX)$(CONFIG_CPU_V7M)$(CONFIG_X86_64),) +# TODO: As of v2019.10 the relocation code for the EFI application cannot +# be built on ARMv7-M and Sandbox. +ifeq ($(CONFIG_SANDBOX)$(CONFIG_CPU_V7M),) obj-y += \ +efi_selftest_exception.o \ efi_selftest_loadimage.o \ efi_selftest_startimage_exit.o \ efi_selftest_startimage_return.o targets += \ +efi_miniapp_file_image_exception.h \ efi_miniapp_file_image_exit.h \ efi_miniapp_file_image_return.h \ +efi_selftest_miniapp_exception.efi \ efi_selftest_miniapp_exit.efi \ efi_selftest_miniapp_return.efi +$(obj)/efi_miniapp_file_image_exception.h: $(obj)/efi_selftest_miniapp_exception.efi + $(obj)/../../tools/file2include $(obj)/efi_selftest_miniapp_exception.efi > \ + $(obj)/efi_miniapp_file_image_exception.h + $(obj)/efi_miniapp_file_image_exit.h: $(obj)/efi_selftest_miniapp_exit.efi $(obj)/../../tools/file2include $(obj)/efi_selftest_miniapp_exit.efi > \ $(obj)/efi_miniapp_file_image_exit.h @@ -80,6 +86,8 @@ $(obj)/efi_miniapp_file_image_return.h: $(obj)/efi_selftest_miniapp_return.efi $(obj)/efi_selftest_loadimage.o: $(obj)/efi_miniapp_file_image_exit.h +$(obj)/efi_selftest_exception.o: $(obj)/efi_miniapp_file_image_exception.h + $(obj)/efi_selftest_startimage_exit.o: $(obj)/efi_miniapp_file_image_exit.h $(obj)/efi_selftest_startimage_return.o: $(obj)/efi_miniapp_file_image_return.h diff --git a/lib/efi_selftest/efi_selftest_exception.c b/lib/efi_selftest/efi_selftest_exception.c index 76cfb88d7c..6e900a35dc 100644 --- a/lib/efi_selftest/efi_selftest_exception.c +++ b/lib/efi_selftest/efi_selftest_exception.c @@ -2,42 +2,138 @@ /* * efi_selftest_exception * - * Copyright (c) 2018 Heinrich Schuchardt <xypron.glpk@gmx.de> + * Copyright (c) 2019 Heinrich Schuchardt <xypron.glpk@gmx.de> * - * Test the handling of exceptions by trying to execute an undefined - * instruction. + * This test checks the handling of exceptions. + * + * The efi_selftest_miniapp_exception.efi application is loaded into memory + * and started. */ #include <efi_selftest.h> +/* Include containing the UEFI application */ +#include "efi_miniapp_file_image_exception.h" + +/* Block size of compressed disk image */ +#define COMPRESSED_DISK_IMAGE_BLOCK_SIZE 8 + +/* Binary logarithm of the block size */ +#define LB_BLOCK_SIZE 9 + +/* File device path for LoadImage() */ +static struct { + struct efi_device_path dp; + u16 filename[8]; + struct efi_device_path end; +} dp = { + { + DEVICE_PATH_TYPE_MEDIA_DEVICE, + DEVICE_PATH_SUB_TYPE_FILE_PATH, + sizeof(dp.dp) + sizeof(dp.filename), + }, + L"bug.efi", + { + DEVICE_PATH_TYPE_END, + DEVICE_PATH_SUB_TYPE_END, + sizeof(dp.end), + } +}; + +static efi_handle_t image_handle; +static struct efi_boot_services *boottime; + +/* One 8 byte block of the compressed disk image */ +struct line { + size_t addr; + char *line; +}; + +/* Compressed file image */ +struct compressed_file_image { + size_t length; + struct line lines[]; +}; + +static struct compressed_file_image img = EFI_ST_DISK_IMG; -/** - * undefined_instruction() - try to executed an undefined instruction +/* Decompressed file image */ +static u8 *image; + +/* + * Decompress the disk image. + * + * @image decompressed disk image + * @return status code */ -static void undefined_instruction(void) +static efi_status_t decompress(u8 **image) { -#if defined(CONFIG_ARM) - /* - * 0xe7f...f. is undefined in ARM mode - * 0xde.. is undefined in Thumb mode - */ - asm volatile (".word 0xe7f7defb\n"); -#elif defined(CONFIG_RISCV) - asm volatile (".word 0xffffffff\n"); -#elif defined(CONFIG_X86) - asm volatile (".word 0xffff\n"); -#endif + u8 *buf; + size_t i; + size_t addr; + size_t len; + efi_status_t ret; + + ret = boottime->allocate_pool(EFI_LOADER_DATA, img.length, + (void **)&buf); + if (ret != EFI_SUCCESS) { + efi_st_error("Out of memory\n"); + return ret; + } + boottime->set_mem(buf, img.length, 0); + + for (i = 0; ; ++i) { + if (!img.lines[i].line) + break; + addr = img.lines[i].addr; + len = COMPRESSED_DISK_IMAGE_BLOCK_SIZE; + if (addr + len > img.length) + len = img.length - addr; + boottime->copy_mem(buf + addr, img.lines[i].line, len); + } + *image = buf; + return ret; } -/** - * execute() - execute unit test +/* + * Setup unit test. * - * Return: EFI_ST_SUCCESS for success + * @handle: handle of the loaded image + * @systable: system table + * @return: EFI_ST_SUCCESS for success + */ +static int setup(const efi_handle_t handle, + const struct efi_system_table *systable) +{ + image_handle = handle; + boottime = systable->boottime; + + /* Load the application image into memory */ + decompress(&image); + + return EFI_ST_SUCCESS; +} + +/* + * Execute unit test. + * + * Load and start the application image. + * + * @return: EFI_ST_SUCCESS for success */ static int execute(void) { - undefined_instruction(); + efi_status_t ret; + efi_handle_t handle; + + ret = boottime->load_image(false, image_handle, &dp.dp, image, + img.length, &handle); + if (ret != EFI_SUCCESS) { + efi_st_error("Failed to load image\n"); + return EFI_ST_FAILURE; + } + ret = boottime->start_image(handle, NULL, NULL); - efi_st_error("An undefined instruction exception was not raised\n"); + efi_st_error("Exception not triggered\n"); return EFI_ST_FAILURE; } @@ -45,6 +141,7 @@ static int execute(void) EFI_UNIT_TEST(exception) = { .name = "exception", .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT, + .setup = setup, .execute = execute, .on_request = true, }; diff --git a/lib/efi_selftest/efi_selftest_miniapp_exception.c b/lib/efi_selftest/efi_selftest_miniapp_exception.c new file mode 100644 index 0000000000..63c63d75f1 --- /dev/null +++ b/lib/efi_selftest/efi_selftest_miniapp_exception.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * efi_selftest_miniapp_return + * + * Copyright (c) 2019 Heinrich Schuchardt + * + * This EFI application triggers an exception. + */ + +#include <common.h> +#include <efi_api.h> + +/* + * Entry point of the EFI application. + * + * @handle handle of the loaded image + * @systable system table + * @return status code + */ +efi_status_t EFIAPI efi_main(efi_handle_t handle, + struct efi_system_table *systable) +{ + struct efi_simple_text_output_protocol *con_out = systable->con_out; + + con_out->output_string(con_out, + L"EFI application triggers exception.\n"); + +#if defined(CONFIG_ARM) + /* + * 0xe7f...f. is undefined in ARM mode + * 0xde.. is undefined in Thumb mode + */ + asm volatile (".word 0xe7f7defb\n"); +#elif defined(CONFIG_RISCV) + asm volatile (".word 0xffffffff\n"); +#elif defined(CONFIG_X86) + asm volatile (".word 0xffff\n"); +#endif + con_out->output_string(con_out, L"Exception not triggered.\n"); + return EFI_ABORTED; +} diff --git a/lib/fdtdec.c b/lib/fdtdec.c index ef5e54875c..74525c84e7 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -1535,16 +1535,14 @@ int fdtdec_setup(void) puts("Failed to read control FDT\n"); return -1; } +# elif defined(CONFIG_OF_PRIOR_STAGE) + gd->fdt_blob = (void *)prior_stage_fdt_address; # endif # ifndef CONFIG_SPL_BUILD /* Allow the early environment to override the fdt address */ -# if CONFIG_IS_ENABLED(OF_PRIOR_STAGE) - gd->fdt_blob = (void *)prior_stage_fdt_address; -# else gd->fdt_blob = map_sysmem (env_get_ulong("fdtcontroladdr", 16, (unsigned long)map_to_sysmem(gd->fdt_blob)), 0); -# endif # endif # if CONFIG_IS_ENABLED(MULTI_DTB_FIT) diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 66bf5c990c..b18eab1707 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -35,7 +35,6 @@ CONFIG_APER_1_BASE CONFIG_APER_SIZE CONFIG_APUS_FAST_EXCEPT CONFIG_ARCH_ADPAG101P -CONFIG_ARCH_CPU_INIT CONFIG_ARCH_HAS_ILOG2_U32 CONFIG_ARCH_HAS_ILOG2_U64 CONFIG_ARCH_KIRKWOOD @@ -621,7 +620,6 @@ CONFIG_FSL_SGMII_RISER CONFIG_FSL_SPI_INTERFACE CONFIG_FSL_TBCLK_EXTRA_DIV CONFIG_FSL_TRUST_ARCH_v1 -CONFIG_FSL_USDHC CONFIG_FSL_VIA CONFIG_FSMC_NAND_BASE CONFIG_FSMTDBLK @@ -1210,9 +1208,7 @@ CONFIG_MXC_USB_PORTSC CONFIG_MXS CONFIG_MXS_AUART CONFIG_MXS_AUART_BASE -CONFIG_MXS_GPIO CONFIG_MXS_OCOTP -CONFIG_MX_CYCLIC CONFIG_MY_OPTION CONFIG_NANDFLASH_SIZE CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC @@ -3337,7 +3333,6 @@ CONFIG_SYS_NAND_SELECT_DEVICE CONFIG_SYS_NAND_SIZE CONFIG_SYS_NAND_SPL_KERNEL_OFFS CONFIG_SYS_NAND_SPL_SIZE -CONFIG_SYS_NAND_USE_FLASH_BBT CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_NAND_U_BOOT_RELOC CONFIG_SYS_NAND_U_BOOT_RELOC_SP @@ -3942,7 +3937,6 @@ CONFIG_SYS_SPI_KERNEL_OFFS CONFIG_SYS_SPI_MXC_WAIT CONFIG_SYS_SPI_RTC_DEVID CONFIG_SYS_SPI_ST_ENABLE_WP_PIN -CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_SIZE CONFIG_SYS_SPI_WRITE_TOUT CONFIG_SYS_SPL_ARGS_ADDR diff --git a/test/dm/clk_ccf.c b/test/dm/clk_ccf.c index bbc4b500e8..ae3a4d8a76 100644 --- a/test/dm/clk_ccf.c +++ b/test/dm/clk_ccf.c @@ -64,6 +64,34 @@ static int dm_test_clk_ccf(struct unit_test_state *uts) rate = clk_get_rate(clk); ut_asserteq(rate, 60000000); +#if CONFIG_IS_ENABLED(CLK_CCF) + /* Test clk tree enable/disable */ + ret = clk_get_by_id(SANDBOX_CLK_I2C_ROOT, &clk); + ut_assertok(ret); + ut_asserteq_str("i2c_root", clk->dev->name); + + ret = clk_enable(clk); + ut_assertok(ret); + + ret = sandbox_clk_enable_count(clk); + ut_asserteq(ret, 1); + + ret = clk_get_by_id(SANDBOX_CLK_I2C, &pclk); + ut_assertok(ret); + + ret = sandbox_clk_enable_count(pclk); + ut_asserteq(ret, 1); + + ret = clk_disable(clk); + ut_assertok(ret); + + ret = sandbox_clk_enable_count(clk); + ut_asserteq(ret, 0); + + ret = sandbox_clk_enable_count(pclk); + ut_asserteq(ret, 0); +#endif + return 1; } diff --git a/tools/Makefile b/tools/Makefile index c7afe8a4b3..24581adccd 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -15,7 +15,6 @@ CONFIG_SHA1_CHECK_UB_IMG = y CONFIG_ARCH_SUNXI = y endif -subdir-$(HOST_TOOLS_ALL) += easylogo subdir-$(HOST_TOOLS_ALL) += gdb # Merge all the different vars for envcrc into one diff --git a/tools/easylogo/Makefile b/tools/easylogo/Makefile deleted file mode 100644 index 9278837f58..0000000000 --- a/tools/easylogo/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ - -hostprogs-y := easylogo - -always := $(hostprogs-y) diff --git a/tools/easylogo/easylogo.c b/tools/easylogo/easylogo.c deleted file mode 100644 index ed4bf203dd..0000000000 --- a/tools/easylogo/easylogo.c +++ /dev/null @@ -1,611 +0,0 @@ -/* -** Easylogo TGA->header converter -** ============================== -** (C) 2000 by Paolo Scaffardi (arsenio@tin.it) -** AIRVENT SAM s.p.a - RIMINI(ITALY) -** (C) 2007-2008 Mike Frysinger <vapier@gentoo.org> -** -** This is still under construction! -*/ - -#include <errno.h> -#include <getopt.h> -#include <stdbool.h> -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <unistd.h> -#include <sys/stat.h> - -#pragma pack(1) - -/*#define ENABLE_ASCII_BANNERS */ - -typedef struct { - unsigned char id; - unsigned char ColorMapType; - unsigned char ImageTypeCode; - unsigned short ColorMapOrigin; - unsigned short ColorMapLenght; - unsigned char ColorMapEntrySize; - unsigned short ImageXOrigin; - unsigned short ImageYOrigin; - unsigned short ImageWidth; - unsigned short ImageHeight; - unsigned char ImagePixelSize; - unsigned char ImageDescriptorByte; -} tga_header_t; - -typedef struct { - unsigned char r, g, b; -} rgb_t; - -typedef struct { - unsigned char b, g, r; -} bgr_t; - -typedef struct { - unsigned char Cb, y1, Cr, y2; -} yuyv_t; - -typedef struct { - void *data, *palette; - int width, height, pixels, bpp, pixel_size, size, palette_size, yuyv; -} image_t; - -void *xmalloc (size_t size) -{ - void *ret = malloc (size); - if (!ret) { - fprintf (stderr, "\nerror: malloc(%zu) failed: %s", - size, strerror(errno)); - exit (1); - } - return ret; -} - -void StringUpperCase (char *str) -{ - int count = strlen (str); - char c; - - while (count--) { - c = *str; - if ((c >= 'a') && (c <= 'z')) - *str = 'A' + (c - 'a'); - str++; - } -} - -void StringLowerCase (char *str) -{ - int count = strlen (str); - char c; - - while (count--) { - c = *str; - if ((c >= 'A') && (c <= 'Z')) - *str = 'a' + (c - 'A'); - str++; - } -} -void pixel_rgb_to_yuyv (rgb_t * rgb_pixel, yuyv_t * yuyv_pixel) -{ - unsigned int pR, pG, pB; - - /* Transform (0-255) components to (0-100) */ - pR = rgb_pixel->r * 100 / 255; - pG = rgb_pixel->g * 100 / 255; - pB = rgb_pixel->b * 100 / 255; - - /* Calculate YUV values (0-255) from RGB beetween 0-100 */ - yuyv_pixel->y1 = yuyv_pixel->y2 = 209 * (pR + pG + pB) / 300 + 16; - yuyv_pixel->Cb = pB - (pR / 4) - (pG * 3 / 4) + 128; - yuyv_pixel->Cr = pR - (pG * 3 / 4) - (pB / 4) + 128; - - return; -} - -void printlogo_rgb (rgb_t * data, int w, int h) -{ - int x, y; - - for (y = 0; y < h; y++) { - for (x = 0; x < w; x++, data++) - if ((data->r < - 30) /*&&(data->g == 0)&&(data->b == 0) */ ) - printf (" "); - else - printf ("X"); - printf ("\n"); - } -} - -void printlogo_yuyv (unsigned short *data, int w, int h) -{ - int x, y; - - for (y = 0; y < h; y++) { - for (x = 0; x < w; x++, data++) - if (*data == 0x1080) /* Because of inverted on i386! */ - printf (" "); - else - printf ("X"); - printf ("\n"); - } -} - -static inline unsigned short le16_to_cpu (unsigned short val) -{ - union { - unsigned char pval[2]; - unsigned short val; - } swapped; - - swapped.val = val; - return (swapped.pval[1] << 8) + swapped.pval[0]; -} - -int image_load_tga (image_t * image, char *filename) -{ - FILE *file; - tga_header_t header; - int i; - unsigned char app; - rgb_t *p; - - if ((file = fopen (filename, "rb")) == NULL) - return -1; - - fread (&header, sizeof (header), 1, file); - - /* byte swap: tga is little endian, host is ??? */ - header.ColorMapOrigin = le16_to_cpu (header.ColorMapOrigin); - header.ColorMapLenght = le16_to_cpu (header.ColorMapLenght); - header.ImageXOrigin = le16_to_cpu (header.ImageXOrigin); - header.ImageYOrigin = le16_to_cpu (header.ImageYOrigin); - header.ImageWidth = le16_to_cpu (header.ImageWidth); - header.ImageHeight = le16_to_cpu (header.ImageHeight); - - image->width = header.ImageWidth; - image->height = header.ImageHeight; - - switch (header.ImageTypeCode) { - case 2: /* Uncompressed RGB */ - image->yuyv = 0; - image->palette_size = 0; - image->palette = NULL; - break; - - default: - printf ("Format not supported!\n"); - return -1; - } - - image->bpp = header.ImagePixelSize; - image->pixel_size = ((image->bpp - 1) / 8) + 1; - image->pixels = image->width * image->height; - image->size = image->pixels * image->pixel_size; - image->data = xmalloc (image->size); - - if (image->bpp != 24) { - printf ("Bpp not supported: %d!\n", image->bpp); - return -1; - } - - fread (image->data, image->size, 1, file); - -/* Swapping R and B values */ - - p = image->data; - for (i = 0; i < image->pixels; i++, p++) { - app = p->r; - p->r = p->b; - p->b = app; - } - -/* Swapping image */ - - if (!(header.ImageDescriptorByte & 0x20)) { - unsigned char *temp = xmalloc (image->size); - int linesize = image->pixel_size * image->width; - void *dest = image->data, - *source = temp + image->size - linesize; - - printf ("S"); - if (temp == NULL) { - printf ("Cannot alloc temp buffer!\n"); - return -1; - } - - memcpy (temp, image->data, image->size); - for (i = 0; i < image->height; - i++, dest += linesize, source -= linesize) - memcpy (dest, source, linesize); - - free (temp); - } -#ifdef ENABLE_ASCII_BANNERS - printlogo_rgb (image->data, image->width, image->height); -#endif - - fclose (file); - return 0; -} - -void image_free (image_t * image) -{ - free (image->data); - free (image->palette); -} - -int image_rgb_to_yuyv (image_t * rgb_image, image_t * yuyv_image) -{ - rgb_t *rgb_ptr = (rgb_t *) rgb_image->data; - yuyv_t yuyv; - unsigned short *dest; - int count = 0; - - yuyv_image->pixel_size = 2; - yuyv_image->bpp = 16; - yuyv_image->yuyv = 1; - yuyv_image->width = rgb_image->width; - yuyv_image->height = rgb_image->height; - yuyv_image->pixels = yuyv_image->width * yuyv_image->height; - yuyv_image->size = yuyv_image->pixels * yuyv_image->pixel_size; - dest = (unsigned short *) (yuyv_image->data = - xmalloc (yuyv_image->size)); - yuyv_image->palette = 0; - yuyv_image->palette_size = 0; - - while ((count++) < rgb_image->pixels) { - pixel_rgb_to_yuyv (rgb_ptr++, &yuyv); - - if ((count & 1) == 0) /* Was == 0 */ - memcpy (dest, ((void *) &yuyv) + 2, sizeof (short)); - else - memcpy (dest, (void *) &yuyv, sizeof (short)); - - dest++; - } - -#ifdef ENABLE_ASCII_BANNERS - printlogo_yuyv (yuyv_image->data, yuyv_image->width, - yuyv_image->height); -#endif - return 0; -} - -int image_rgb888_to_rgb565(image_t *rgb888_image, image_t *rgb565_image) -{ - rgb_t *rgb_ptr = (rgb_t *) rgb888_image->data; - unsigned short *dest; - int count = 0; - - rgb565_image->pixel_size = 2; - rgb565_image->bpp = 16; - rgb565_image->yuyv = 0; - rgb565_image->width = rgb888_image->width; - rgb565_image->height = rgb888_image->height; - rgb565_image->pixels = rgb565_image->width * rgb565_image->height; - rgb565_image->size = rgb565_image->pixels * rgb565_image->pixel_size; - dest = (unsigned short *) (rgb565_image->data = - xmalloc(rgb565_image->size)); - rgb565_image->palette = 0; - rgb565_image->palette_size = 0; - - while ((count++) < rgb888_image->pixels) { - - *dest++ = ((rgb_ptr->b & 0xF8) << 8) | - ((rgb_ptr->g & 0xFC) << 3) | - (rgb_ptr->r >> 3); - rgb_ptr++; - } - - return 0; -} - -enum comp_t { - COMP_NONE, - COMP_GZIP, - COMP_LZMA, -}; -static enum comp_t compression = COMP_NONE; -static bool bss_storage = false; - -int image_save_header (image_t * image, char *filename, char *varname) -{ - FILE *file = fopen (filename, "w"); - char app[256], str[256] = "", def_name[64]; - int count = image->size, col = 0; - unsigned char *dataptr = image->data; - - if (file == NULL) - return -1; - - /* Author information */ - fprintf (file, - "/*\n * Generated by EasyLogo, (C) 2000 by Paolo Scaffardi\n *\n"); - fprintf (file, - " * To use this, include it and call: easylogo_plot(screen,&%s, width,x,y)\n *\n", - varname); - fprintf (file, - " * Where:\t'screen'\tis the pointer to the frame buffer\n"); - fprintf (file, " *\t\t'width'\tis the screen width\n"); - fprintf (file, " *\t\t'x'\t\tis the horizontal position\n"); - fprintf (file, " *\t\t'y'\t\tis the vertical position\n */\n\n"); - - /* image compress */ - if (compression != COMP_NONE) { - const char *errstr = NULL; - unsigned char *compressed; - const char *comp_name; - struct stat st; - FILE *compfp; - size_t filename_len = strlen(filename); - char *compfilename = xmalloc(filename_len + 20); - char *compcmd = xmalloc(filename_len + 50); - - sprintf(compfilename, "%s.bin", filename); - switch (compression) { - case COMP_GZIP: - strcpy(compcmd, "gzip"); - comp_name = "GZIP"; - break; - case COMP_LZMA: - strcpy(compcmd, "lzma"); - comp_name = "LZMA"; - break; - default: - errstr = "\nerror: unknown compression method"; - goto done; - } - strcat(compcmd, " > "); - strcat(compcmd, compfilename); - compfp = popen(compcmd, "w"); - if (!compfp) { - errstr = "\nerror: popen() failed"; - goto done; - } - if (fwrite(image->data, image->size, 1, compfp) != 1) { - errstr = "\nerror: writing data to gzip failed"; - goto done; - } - if (pclose(compfp)) { - errstr = "\nerror: gzip process failed"; - goto done; - } - - compfp = fopen(compfilename, "r"); - if (!compfp) { - errstr = "\nerror: open() on gzip data failed"; - goto done; - } - if (stat(compfilename, &st)) { - errstr = "\nerror: stat() on gzip file failed"; - goto done; - } - compressed = xmalloc(st.st_size); - if (fread(compressed, st.st_size, 1, compfp) != 1) { - errstr = "\nerror: reading gzip data failed"; - goto done; - } - fclose(compfp); - - unlink(compfilename); - - dataptr = compressed; - count = st.st_size; - fprintf(file, "#define EASYLOGO_ENABLE_%s %i\n\n", comp_name, count); - if (bss_storage) - fprintf (file, "static unsigned char EASYLOGO_DECOMP_BUFFER[%i];\n\n", image->size); - - done: - free(compfilename); - free(compcmd); - - if (errstr) { - perror (errstr); - return -1; - } - } - - /* Headers */ - fprintf (file, "#include <video_easylogo.h>\n\n"); - /* Macros */ - strcpy (def_name, varname); - StringUpperCase (def_name); - fprintf (file, "#define DEF_%s_WIDTH\t\t%d\n", def_name, - image->width); - fprintf (file, "#define DEF_%s_HEIGHT\t\t%d\n", def_name, - image->height); - fprintf (file, "#define DEF_%s_PIXELS\t\t%d\n", def_name, - image->pixels); - fprintf (file, "#define DEF_%s_BPP\t\t%d\n", def_name, image->bpp); - fprintf (file, "#define DEF_%s_PIXEL_SIZE\t%d\n", def_name, - image->pixel_size); - fprintf (file, "#define DEF_%s_SIZE\t\t%d\n\n", def_name, - image->size); - /* Declaration */ - fprintf (file, "unsigned char DEF_%s_DATA[] = {\n", - def_name); - - /* Data */ - while (count) - switch (col) { - case 0: - sprintf (str, " 0x%02x", *dataptr++); - col++; - count--; - break; - - case 16: - fprintf (file, "%s", str); - if (count > 0) - fprintf (file, ","); - fprintf (file, "\n"); - - col = 0; - break; - - default: - strcpy (app, str); - sprintf(str, "%.*s, 0x%02x", (int)sizeof(str) - 7, app, - *dataptr++); - col++; - count--; - break; - } - - if (col) - fprintf (file, "%s\n", str); - - /* End of declaration */ - fprintf (file, "};\n\n"); - /* Variable */ - fprintf (file, "fastimage_t %s = {\n", varname); - fprintf (file, " DEF_%s_DATA,\n", def_name); - fprintf (file, " DEF_%s_WIDTH,\n", def_name); - fprintf (file, " DEF_%s_HEIGHT,\n", def_name); - fprintf (file, " DEF_%s_BPP,\n", def_name); - fprintf (file, " DEF_%s_PIXEL_SIZE,\n", def_name); - fprintf (file, " DEF_%s_SIZE\n};\n", def_name); - - fclose (file); - - return 0; -} - -#define DEF_FILELEN 256 - -static void usage (int exit_status) -{ - puts ( - "EasyLogo 1.0 (C) 2000 by Paolo Scaffardi\n" - "\n" - "Syntax: easylogo [options] inputfile [outputvar [outputfile]]\n" - "\n" - "Options:\n" - " -r Output RGB888 instead of YUYV\n" - " -s Output RGB565 instead of YUYV\n" - " -g Compress with gzip\n" - " -l Compress with lzma\n" - " -b Preallocate space in bss for decompressing image\n" - " -h Help output\n" - "\n" - "Where: 'inputfile' is the TGA image to load\n" - " 'outputvar' is the variable name to create\n" - " 'outputfile' is the output header file (default is 'inputfile.h')" - ); - exit (exit_status); -} - -int main (int argc, char *argv[]) -{ - int c; - bool use_rgb888 = false; - bool use_rgb565 = false; - char inputfile[DEF_FILELEN], - outputfile[DEF_FILELEN], varname[DEF_FILELEN]; - - image_t rgb888_logo, rgb565_logo, yuyv_logo; - - while ((c = getopt(argc, argv, "hrsglb")) > 0) { - switch (c) { - case 'h': - usage (0); - break; - case 'r': - use_rgb888 = true; - puts("Using 24-bit RGB888 Output Fromat"); - break; - case 's': - use_rgb565 = true; - puts("Using 16-bit RGB565 Output Fromat"); - break; - case 'g': - compression = COMP_GZIP; - puts("Compressing with gzip"); - break; - case 'l': - compression = COMP_LZMA; - puts("Compressing with lzma"); - break; - case 'b': - bss_storage = true; - puts("Preallocating bss space for decompressing image"); - break; - default: - usage (1); - break; - } - } - - c = argc - optind; - if (c > 4 || c < 1) - usage (1); - - strcpy (inputfile, argv[optind]); - - if (c > 1) - strcpy (varname, argv[optind + 1]); - else { - /* transform "input.tga" to just "input" */ - char *dot; - strcpy (varname, inputfile); - dot = strchr (varname, '.'); - if (dot) - *dot = '\0'; - } - - if (c > 2) - strcpy (outputfile, argv[optind + 2]); - else { - /* just append ".h" to input file name */ - strcpy (outputfile, inputfile); - strcat (outputfile, ".h"); - } - - /* Make sure the output is sent as soon as we printf() */ - setbuf(stdout, NULL); - - printf ("Doing '%s' (%s) from '%s'...", - outputfile, varname, inputfile); - - /* Import TGA logo */ - - printf ("L"); - if (image_load_tga(&rgb888_logo, inputfile) < 0) { - printf ("input file not found!\n"); - exit (1); - } - - /* Convert, save, and free the image */ - - if (!use_rgb888 && !use_rgb565) { - printf ("C"); - image_rgb_to_yuyv(&rgb888_logo, &yuyv_logo); - - printf("S"); - image_save_header(&yuyv_logo, outputfile, varname); - image_free(&yuyv_logo); - } else if (use_rgb565) { - printf("C"); - image_rgb888_to_rgb565(&rgb888_logo, &rgb565_logo); - - printf("S"); - image_save_header(&rgb565_logo, outputfile, varname); - image_free(&rgb565_logo); - } else { - printf("S"); - image_save_header(&rgb888_logo, outputfile, varname); - } - - /* Free original image and copy */ - - image_free(&rgb888_logo); - - printf ("\n"); - - return 0; -} diff --git a/tools/easylogo/linux_blackfin.tga b/tools/easylogo/linux_blackfin.tga Binary files differdeleted file mode 100644 index e2bb17b80b..0000000000 --- a/tools/easylogo/linux_blackfin.tga +++ /dev/null diff --git a/tools/easylogo/linux_logo.tga b/tools/easylogo/linux_logo.tga Binary files differdeleted file mode 100644 index ac53def05c..0000000000 --- a/tools/easylogo/linux_logo.tga +++ /dev/null diff --git a/tools/easylogo/runme.sh b/tools/easylogo/runme.sh deleted file mode 100644 index 625ebaae19..0000000000 --- a/tools/easylogo/runme.sh +++ /dev/null @@ -1,4 +0,0 @@ -#!/bin/sh -make -./easylogo linux_logo.tga u_boot_logo video_logo.h -mv video_logo.h ../../include |