diff options
59 files changed, 1529 insertions, 311 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 2df957cf56..3aaeb6a53c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -34,6 +34,8 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra124-jetson-tk1.dtb \ tegra124-nyan-big.dtb \ tegra124-venice2.dtb \ + tegra210-e2220-1170.dtb \ + tegra210-p2371-0000.dtb \ tegra210-p2571.dtb dtb-$(CONFIG_ARCH_UNIPHIER) += \ uniphier-ph1-sld3-ref.dtb \ diff --git a/arch/arm/dts/tegra210-e2220-1170.dts b/arch/arm/dts/tegra210-e2220-1170.dts new file mode 100644 index 0000000000..75efbba106 --- /dev/null +++ b/arch/arm/dts/tegra210-e2220-1170.dts @@ -0,0 +1,58 @@ +/dts-v1/; + +#include "tegra210.dtsi" + +/ { + model = "NVIDIA E2220-1170"; + compatible = "nvidia,e2220-1170", "nvidia,tegra210"; + + chosen { + stdout-path = &uarta; + }; + + aliases { + i2c0 = "/i2c@0,7000d000"; + sdhci0 = "/sdhci@0,700b0600"; + sdhci1 = "/sdhci@0,700b0000"; + usb0 = "/usb@0,7d000000"; + }; + + memory { + reg = <0x0 0x80000000 0x0 0xc0000000>; + }; + + sdhci@0,700b0000 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + }; + + sdhci@0,700b0600 { + status = "okay"; + bus-width = <8>; + }; + + i2c@0,7000d000 { + status = "okay"; + clock-frequency = <400000>; + }; + + usb@0,7d000000 { + status = "okay"; + dr_mode = "peripheral"; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; +}; diff --git a/arch/arm/dts/tegra210-p2371-0000.dts b/arch/arm/dts/tegra210-p2371-0000.dts new file mode 100644 index 0000000000..10172a23ad --- /dev/null +++ b/arch/arm/dts/tegra210-p2371-0000.dts @@ -0,0 +1,59 @@ +/dts-v1/; + +#include "tegra210.dtsi" + +/ { + model = "NVIDIA P2371-0000"; + compatible = "nvidia,p2371-0000", "nvidia,tegra210"; + + chosen { + stdout-path = &uarta; + }; + + aliases { + i2c0 = "/i2c@0,7000d000"; + sdhci0 = "/sdhci@0,700b0600"; + sdhci1 = "/sdhci@0,700b0000"; + usb0 = "/usb@0,7d000000"; + }; + + memory { + reg = <0x0 0x80000000 0x0 0xc0000000>; + }; + + sdhci@0,700b0000 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + }; + + sdhci@0,700b0600 { + status = "okay"; + bus-width = <8>; + }; + + i2c@0,7000d000 { + status = "okay"; + clock-frequency = <400000>; + }; + + usb@0,7d000000 { + status = "okay"; + dr_mode = "otg"; + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; +}; diff --git a/arch/arm/include/asm/arch-tegra/ap.h b/arch/arm/include/asm/arch-tegra/ap.h index 76773b7ec7..8c2586c6f5 100644 --- a/arch/arm/include/asm/arch-tegra/ap.h +++ b/arch/arm/include/asm/arch-tegra/ap.h @@ -64,15 +64,6 @@ int tegra_get_sku_info(void); /* Do any chip-specific cache config */ void config_cache(void); -#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210) -/* Do chip-specific vpr config */ -void config_vpr(void); -#else -static inline void config_vpr(void) -{ -} -#endif - #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) bool tegra_cpu_is_non_secure(void); #endif diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h index f69026002b..ee9436e2e5 100644 --- a/arch/arm/include/asm/arch-tegra/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra/clk_rst.h @@ -249,17 +249,6 @@ struct clk_rst_ctlr { #define PLL_LOCK_SHIFT 27 #define PLL_LOCK_MASK (1U << PLL_LOCK_SHIFT) -#define PLL_DIVP_SHIFT 20 -#define PLL_DIVP_MASK (7U << PLL_DIVP_SHIFT) -/* Special case for T210 PLLU DIVP */ -#define PLLU_DIVP_SHIFT 16 - -#define PLL_DIVN_SHIFT 8 -#define PLL_DIVN_MASK (0x3ffU << PLL_DIVN_SHIFT) - -#define PLL_DIVM_SHIFT 0 -#define PLL_DIVM_MASK (0x1f << PLL_DIVM_SHIFT) - /* CLK_RST_CONTROLLER_PLLx_OUTx_0 */ #define PLL_OUT_RSTN (1 << 0) #define PLL_OUT_CLKEN (1 << 1) @@ -272,24 +261,6 @@ struct clk_rst_ctlr { #define PLL_DCCON_SHIFT 20 #define PLL_DCCON_MASK (1U << PLL_DCCON_SHIFT) -#define PLL_LOCK_ENABLE_SHIFT 18 -#define PLL_LOCK_ENABLE_MASK (1U << PLL_LOCK_ENABLE_SHIFT) - -#define PLL_CPCON_SHIFT 8 -#define PLL_CPCON_MASK (15U << PLL_CPCON_SHIFT) - -#define PLL_LFCON_SHIFT 4 -#define PLL_LFCON_MASK (15U << PLL_LFCON_SHIFT) - -/* CPCON/LFCON replaced by KCP/KVCO in T210 PLLU */ -#define PLLU_KVCO_SHIFT 24 -#define PLLU_KVCO_MASK (3U << PLLU_KVCO_SHIFT) -#define PLLU_KCP_SHIFT 25 -#define PLLU_KCP_MASK (1U << PLLU_KCP_SHIFT) - -#define PLLU_VCO_FREQ_SHIFT 20 -#define PLLU_VCO_FREQ_MASK (1U << PLLU_VCO_FREQ_SHIFT) - #define PLLP_OUT1_OVR (1 << 2) #define PLLP_OUT2_OVR (1 << 18) #define PLLP_OUT3_OVR (1 << 2) @@ -475,4 +446,7 @@ enum { #define PLLDP_SS_CFG_UNDOCUMENTED (1 << 24) #define PLLDP_SS_CFG_DITHER (1 << 28) +/* CLK_RST_PLLD_MISC */ +#define PLLD_CLKENABLE 30 + #endif /* _TEGRA_CLK_RST_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index f9dd3c817d..d570d7f134 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -16,6 +16,8 @@ enum clock_osc_freq { CLOCK_OSC_FREQ_19_2, CLOCK_OSC_FREQ_12_0, CLOCK_OSC_FREQ_26_0, + CLOCK_OSC_FREQ_38_4, + CLOCK_OSC_FREQ_48_0, CLOCK_OSC_FREQ_COUNT, }; @@ -336,6 +338,27 @@ void arch_timer_init(void); void tegra30_set_up_pllp(void); +/* Number of PLL-based clocks (i.e. not OSC or 32KHz) */ +#define CLOCK_ID_PLL_COUNT (CLOCK_ID_COUNT - 2) + +struct clk_pll_info { + u32 m_shift:5; /* DIVM_SHIFT */ + u32 n_shift:5; /* DIVN_SHIFT */ + u32 p_shift:5; /* DIVP_SHIFT */ + u32 kcp_shift:5; /* KCP/cpcon SHIFT */ + u32 kvco_shift:5; /* KVCO/lfcon SHIFT */ + u32 lock_ena:6; /* LOCK_ENABLE/EN_LOCKDET shift */ + u32 rsvd:1; + u32 m_mask:10; /* DIVM_MASK */ + u32 n_mask:12; /* DIVN_MASK */ + u32 p_mask:10; /* DIVP_MASK or VCO_MASK */ + u32 kcp_mask:10; /* KCP/CPCON MASK */ + u32 kvco_mask:10; /* KVCO/LFCON MASK */ + u32 lock_det:6; /* LOCK_DETECT/LOCKED shift */ + u32 rsvd2:6; +}; +extern struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT]; + /** * Enable output clock for external peripherals * diff --git a/arch/arm/include/asm/arch-tegra/gpu.h b/arch/arm/include/asm/arch-tegra/gpu.h new file mode 100644 index 0000000000..52280f40ce --- /dev/null +++ b/arch/arm/include/asm/arch-tegra/gpu.h @@ -0,0 +1,42 @@ +/* + * (C) Copyright 2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_TEGRA_GPU_H +#define __ASM_ARCH_TEGRA_GPU_H + +#if defined(CONFIG_TEGRA_GPU) + +void config_gpu(void); +bool gpu_configured(void); + +#else /* CONFIG_TEGRA_GPU */ + +static inline void config_gpu(void) +{ +} + +static inline bool gpu_configured(void) +{ + return false; +} + +#endif /* CONFIG_TEGRA_GPU */ + +#if defined(CONFIG_OF_LIBFDT) + +int gpu_enable_node(void *blob, const char *gpupath); + +#else /* CONFIG_OF_LIBFDT */ + +static inline int gpu_enable_node(void *blob, const char *gpupath) +{ + return 0; +} + +#endif /* CONFIG_OF_LIBFDT */ + +#endif /* __ASM_ARCH_TEGRA_GPU_H */ diff --git a/arch/arm/include/asm/arch-tegra210/clock-tables.h b/arch/arm/include/asm/arch-tegra210/clock-tables.h index b62e0702a5..175040dae6 100644 --- a/arch/arm/include/asm/arch-tegra210/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra210/clock-tables.h @@ -25,6 +25,7 @@ enum clock_id { CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, CLOCK_ID_EPCI, CLOCK_ID_SFROM32KHZ, + CLOCK_ID_DP, /* These are the base clocks (inputs to the Tegra SoC) */ CLOCK_ID_32KHZ, diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 0db8ee05bd..75924ad848 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -24,9 +24,7 @@ obj-y += pinmux-common.o obj-y += powergate.o obj-y += xusb-padctl.o obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o -#TCW Fix this to use a common config switch (CONFIG_LOCK_VPR?) -obj-$(CONFIG_TEGRA124) += vpr.o -obj-$(CONFIG_TEGRA210) += vpr.o +obj-$(CONFIG_TEGRA_GPU) += gpu.o obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o ifndef CONFIG_SPL_BUILD diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c index e62dda5a6b..b4229f4575 100644 --- a/arch/arm/mach-tegra/ap.c +++ b/arch/arm/mach-tegra/ap.c @@ -226,8 +226,5 @@ void s_init(void) /* enable SMMU */ smmu_enable(); - - /* init vpr */ - config_vpr(); } #endif diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 36bcfb04c0..37953cfda8 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -29,6 +29,7 @@ #include <asm/arch-tegra/sys_proto.h> #include <asm/arch-tegra/uart.h> #include <asm/arch-tegra/warmboot.h> +#include <asm/arch-tegra/gpu.h> #ifdef CONFIG_TEGRA_CLOCK_SCALING #include <asm/arch/emc.h> #endif @@ -60,6 +61,7 @@ __weak void pin_mux_usb(void) {} __weak void pin_mux_spi(void) {} __weak void gpio_early_init_uart(void) {} __weak void pin_mux_display(void) {} +__weak void start_cpu_fan(void) {} #if defined(CONFIG_TEGRA_NAND) __weak void pin_mux_nand(void) @@ -125,6 +127,8 @@ int board_init(void) clock_init(); clock_verify(); + config_gpu(); + #ifdef CONFIG_TEGRA_SPI pin_mux_spi(); #endif @@ -230,6 +234,8 @@ int board_late_init(void) setenv("cpu_ns_mode", ""); } #endif + start_cpu_fan(); + return 0; } @@ -287,11 +293,20 @@ void pad_init_mmc(struct mmc_host *host) * 32-bits of the physical address space. Cap the maximum usable RAM area * at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit * boundary that most devices can address. + * + * Additionally, ARM64 devices typically run a secure monitor in EL3 and + * U-Boot in EL2, and set up some secure RAM carve-outs to contain the EL3 + * code and data. These carve-outs are located at the top of 32-bit address + * space. Restrict U-Boot's RAM usage to well below the location of those + * carve-outs. Ideally, we would the secure monitor would inform U-Boot of + * exactly which RAM it could use at run-time. However, I'm not sure how to + * do that at present (and even if such a mechanism does exist, it would + * likely not be generic across all forms of secure monitor). */ ulong board_get_usable_ram_top(ulong total_size) { - if (gd->ram_top > 0x100000000) - return 0x100000000; + if (gd->ram_top > 0xe0000000) + return 0xe0000000; return gd->ram_top; } diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 5d968d8d33..3b2b4ffd2a 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -44,6 +44,8 @@ static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = { 19200000, 12000000, 26000000, + 38400000, + 48000000, }; /* return 1 if a peripheral ID is in range */ @@ -99,6 +101,7 @@ int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, u32 *divp, u32 *cpcon, u32 *lfcon) { struct clk_pll *pll = get_pll(clkid); + struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid]; u32 data; assert(clkid != CLOCK_ID_USB); @@ -107,17 +110,14 @@ int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB) return -1; data = readl(&pll->pll_base); - *divm = (data & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT; - *divn = (data & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT; - *divp = (data & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT; + *divm = (data >> pllinfo->m_shift) & pllinfo->m_mask; + *divn = (data >> pllinfo->n_shift) & pllinfo->n_mask; + *divp = (data >> pllinfo->p_shift) & pllinfo->p_mask; data = readl(&pll->pll_misc); - *cpcon = (data & PLL_CPCON_MASK) >> PLL_CPCON_SHIFT; - *lfcon = (data & PLL_LFCON_MASK) >> PLL_LFCON_SHIFT; -#if defined(CONFIG_TEGRA210) - /* T210 PLLU uses KCP/KVCO instead of CPCON/LFCON */ - *cpcon = (data & PLLU_KCP_MASK) >> PLLU_KCP_SHIFT; - *lfcon = (data & PLLU_KVCO_MASK) >> PLLU_KVCO_SHIFT; -#endif + /* NOTE: On T210, cpcon/lfcon no longer exist, moved to KCP/KVCO */ + *cpcon = (data >> pllinfo->kcp_shift) & pllinfo->kcp_mask; + *lfcon = (data >> pllinfo->kvco_shift) & pllinfo->kvco_mask; + return 0; } @@ -125,41 +125,25 @@ unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn, u32 divp, u32 cpcon, u32 lfcon) { struct clk_pll *pll = NULL; + struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid]; u32 misc_data, data; if (clkid < (enum clock_id)TEGRA_CLK_PLLS) pll = get_pll(clkid); /* - * We cheat by treating all PLL (except PLLU) in the same fashion. - * This works only because: - * - same fields are always mapped at same offsets, except DCCON - * - DCCON is always 0, doesn't conflict - * - M,N, P of PLLP values are ignored for PLLP - * NOTE: Above is no longer true with T210 - TBD: FIX THIS + * pllinfo has the m/n/p and kcp/kvco mask and shift + * values for all of the PLLs used in U-Boot, with any + * SoC differences accounted for. */ - misc_data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT); - -#if defined(CONFIG_TEGRA210) - /* T210 PLLU uses KCP/KVCO instead of cpcon/lfcon */ - if (clkid == CLOCK_ID_USB) { - /* preserve EN_LOCKDET, set by default */ - misc_data = readl(&pll->pll_misc); - misc_data |= (cpcon << PLLU_KCP_SHIFT) | - (lfcon << PLLU_KVCO_SHIFT); - } -#endif - data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) | - (0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT); - - if (clkid == CLOCK_ID_USB) -#if defined(CONFIG_TEGRA210) - data |= divp << PLLU_DIVP_SHIFT; -#else - data |= divp << PLLU_VCO_FREQ_SHIFT; -#endif - else - data |= divp << PLL_DIVP_SHIFT; + misc_data = readl(&pll->pll_misc); /* preserve EN_LOCKDET, etc. */ + misc_data &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift) | (cpcon << pllinfo->kcp_shift); + misc_data &= ~(pllinfo->kvco_mask << pllinfo->kvco_shift) | (lfcon << pllinfo->kvco_shift); + + data = (divm << pllinfo->m_shift) | (divn << pllinfo->n_shift); + data |= divp << pllinfo->p_shift; + data |= (1 << PLL_ENABLE_SHIFT); /* BYPASS s/b 0 already */ + if (pll) { writel(misc_data, &pll->pll_misc); writel(data, &pll->pll_base); @@ -471,10 +455,9 @@ void reset_cmplx_set_enable(int cpu, int which, int reset) unsigned clock_get_rate(enum clock_id clkid) { struct clk_pll *pll; - u32 base; - u32 divm; - u64 parent_rate; - u64 rate; + u32 base, divm; + u64 parent_rate, rate; + struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid]; parent_rate = osc_freq[clock_get_osc_freq()]; if (clkid == CLOCK_ID_OSC) @@ -485,13 +468,13 @@ unsigned clock_get_rate(enum clock_id clkid) return 0; base = readl(&pll->pll_base); - /* Oh for bf_unpack()... */ - rate = parent_rate * ((base & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT); - divm = (base & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT; - if (clkid == CLOCK_ID_USB) - divm <<= (base & PLLU_VCO_FREQ_MASK) >> PLLU_VCO_FREQ_SHIFT; - else - divm <<= (base & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT; + rate = parent_rate * ((base >> pllinfo->n_shift) & pllinfo->n_mask); + divm = (base >> pllinfo->m_shift) & pllinfo->m_mask; + /* + * PLLU uses p_mask/p_shift for VCO on all but T210, + * T210 uses normal DIVP. Handled in pllinfo table. + */ + divm <<= (base >> pllinfo->p_shift) & pllinfo->p_mask; do_div(rate, divm); return rate; } @@ -515,23 +498,23 @@ unsigned clock_get_rate(enum clock_id clkid) */ int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon) { - u32 base_reg; - u32 misc_reg; + u32 base_reg, misc_reg; struct clk_pll *pll; + struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid]; pll = get_pll(clkid); base_reg = readl(&pll->pll_base); /* Set BYPASS, m, n and p to PLL_BASE */ - base_reg &= ~PLL_DIVM_MASK; - base_reg |= m << PLL_DIVM_SHIFT; + base_reg &= ~(pllinfo->m_mask << pllinfo->m_shift); + base_reg |= m << pllinfo->m_shift; - base_reg &= ~PLL_DIVN_MASK; - base_reg |= n << PLL_DIVN_SHIFT; + base_reg &= ~(pllinfo->n_mask << pllinfo->n_shift); + base_reg |= n << pllinfo->n_shift; - base_reg &= ~PLL_DIVP_MASK; - base_reg |= p << PLL_DIVP_SHIFT; + base_reg &= ~(pllinfo->p_mask << pllinfo->p_shift); + base_reg |= p << pllinfo->p_shift; if (clkid == CLOCK_ID_PERIPH) { /* @@ -550,17 +533,10 @@ int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon) base_reg |= PLL_BYPASS_MASK; writel(base_reg, &pll->pll_base); - /* Set cpcon to PLL_MISC */ + /* Set cpcon (KCP) to PLL_MISC */ misc_reg = readl(&pll->pll_misc); -#if !defined(CONFIG_TEGRA210) - misc_reg &= ~PLL_CPCON_MASK; - misc_reg |= cpcon << PLL_CPCON_SHIFT; -#else - /* T210 uses KCP instead, use the most common bit shift (PLLA/U/D2) */ - misc_reg &= ~PLLU_KCP_MASK; - misc_reg |= cpcon << PLLU_KCP_SHIFT; -#endif - + misc_reg &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift); + misc_reg |= cpcon << pllinfo->kcp_shift; writel(misc_reg, &pll->pll_misc); /* Enable PLL */ @@ -620,17 +596,20 @@ int clock_verify(void) void clock_init(void) { + pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL); pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY); pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH); - pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL); + pll_rate[CLOCK_ID_USB] = clock_get_rate(CLOCK_ID_USB); pll_rate[CLOCK_ID_DISPLAY] = clock_get_rate(CLOCK_ID_DISPLAY); - pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC); - pll_rate[CLOCK_ID_SFROM32KHZ] = 32768; pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU); + pll_rate[CLOCK_ID_SFROM32KHZ] = 32768; + pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC); + debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]); + debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]); debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]); debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]); - debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]); + debug("PLLU = %d\n", pll_rate[CLOCK_ID_USB]); debug("PLLD = %d\n", pll_rate[CLOCK_ID_DISPLAY]); debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]); } diff --git a/arch/arm/mach-tegra/cpu.c b/arch/arm/mach-tegra/cpu.c index f7d45e8f65..ba04a56be7 100644 --- a/arch/arm/mach-tegra/cpu.c +++ b/arch/arm/mach-tegra/cpu.c @@ -67,6 +67,8 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */ { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */ + { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */ + { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */ }, /* * T25: 1.2 GHz @@ -83,6 +85,8 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */ { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */ + { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */ + { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */ }, /* * T30: 600 MHz @@ -99,6 +103,8 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { { .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ { .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */ { .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */ + { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */ + { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */ }, /* * T114: 700 MHz @@ -114,6 +120,8 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */ { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */ { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */ + { .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */ + { .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */ }, /* @@ -130,6 +138,8 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */ { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */ { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */ + { .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */ + { .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */ }, /* @@ -146,6 +156,8 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz = 700.8 MHz*/ { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz = 696 MHz*/ { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz = 702 MHz*/ + { .n = 36, .m = 1, .p = 1 }, /* OSC: 38.4 MHz = 691.2 MHz */ + { .n = 58, .m = 2, .p = 1 }, /* OSC: 48.0 MHz = 696 MHz */ }, }; @@ -169,6 +181,7 @@ static inline void pllx_set_iddq(void) int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, u32 divp, u32 cpcon) { + struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU]; int chip = tegra_get_chip(); u32 reg; debug("%s entry\n", __func__); @@ -182,17 +195,21 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, pllx_set_iddq(); /* Set BYPASS, m, n and p to PLLX_BASE */ - reg = PLL_BYPASS_MASK | (divm << PLL_DIVM_SHIFT); - reg |= ((divn << PLL_DIVN_SHIFT) | (divp << PLL_DIVP_SHIFT)); + reg = PLL_BYPASS_MASK | (divm << pllinfo->m_shift); + reg |= (divn << pllinfo->n_shift) | (divp << pllinfo->p_shift); writel(reg, &pll->pll_base); /* Set cpcon to PLLX_MISC */ if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30) - reg = (cpcon << PLL_CPCON_SHIFT); + reg = (cpcon << pllinfo->kcp_shift); else reg = 0; - /* Set dccon to PLLX_MISC if freq > 600MHz */ + /* + * TODO(twarren@nvidia.com) Check which SoCs use DCCON + * and add to pllinfo table if needed! + */ + /* Set dccon to PLLX_MISC if freq > 600MHz */ if (divn > 600) reg |= (1 << PLL_DCCON_SHIFT); writel(reg, &pll->pll_misc); @@ -203,9 +220,10 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, writel(reg, &pll->pll_base); debug("%s: base = 0x%08X\n", __func__, reg); - /* Set lock_enable to PLLX_MISC */ + /* Set lock_enable to PLLX_MISC if lock_ena is valid (i.e. 0-31) */ reg = readl(&pll->pll_misc); - reg |= PLL_LOCK_ENABLE_MASK; + if (pllinfo->lock_ena < 32) + reg |= (1 << pllinfo->lock_ena); writel(reg, &pll->pll_misc); debug("%s: misc = 0x%08X\n", __func__, reg); diff --git a/arch/arm/mach-tegra/vpr.c b/arch/arm/mach-tegra/gpu.c index f695811c9b..4ea046d3e5 100644 --- a/arch/arm/mach-tegra/vpr.c +++ b/arch/arm/mach-tegra/gpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -21,8 +21,11 @@ #include <asm/arch/tegra.h> #include <asm/arch/mc.h> -/* Configures VPR. Right now, all we do is turn it off. */ -void config_vpr(void) +#include <fdt_support.h> + +static bool _configured; + +void config_gpu(void) { struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE; @@ -32,4 +35,32 @@ void config_vpr(void) &mc->mc_video_protect_reg_ctrl); /* read back to ensure the write went through */ readl(&mc->mc_video_protect_reg_ctrl); + + debug("configured VPR\n"); + + _configured = true; +} + +bool vpr_configured(void) +{ + return _configured; } + +#if defined(CONFIG_OF_LIBFDT) + +int gpu_enable_node(void *blob, const char *gpupath) +{ + int offset; + + if (vpr_configured()) { + offset = fdt_path_offset(blob, gpupath); + if (offset > 0) { + fdt_status_okay(blob, offset); + debug("enabled GPU node %s\n", gpupath); + } + } + + return 0; +} + +#endif diff --git a/arch/arm/mach-tegra/tegra114/clock.c b/arch/arm/mach-tegra/tegra114/clock.c index d5194e11b5..f1831d385d 100644 --- a/arch/arm/mach-tegra/tegra114/clock.c +++ b/arch/arm/mach-tegra/tegra114/clock.c @@ -1,17 +1,8 @@ /* - * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. + * (C) Copyright 2010-2015 + * NVIDIA Corporation <www.nvidia.com> * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0+ */ /* Tegra114 Clock control functions */ @@ -435,6 +426,36 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { }; /* + * PLL divider shift/mask tables for all PLL IDs. + */ +struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { + /* + * T114: some deviations from T2x/T30. + * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLX, etc.) + * If lock_ena or lock_det are >31, they're not used in that PLL. + */ + + { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F, + .lock_ena = 24, .lock_det = 27, .kcp_shift = 28, .kcp_mask = 3, .kvco_shift = 27, .kvco_mask = 1 }, /* PLLC */ + { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0, + .lock_ena = 0, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */ + { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, + .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLP */ + { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, + .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLA */ + { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01, + .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLU */ + { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, + .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD */ + { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F, + .lock_ena = 18, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */ + { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0, + .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ + { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, + .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */ +}; + +/* * Get the oscillator frequency, from the corresponding hardware configuration * field. Note that T30/T114 support 3 new higher freqs, but we map back * to the old T20 freqs. Support for the higher oscillators is TBD. @@ -603,6 +624,8 @@ void clock_early_init(void) { struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + struct clk_pll_info *pllinfo; + u32 data; tegra30_set_up_pllp(); @@ -639,11 +662,15 @@ void clock_early_init(void) writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); /* PLLC_MISC: Set LOCK_ENABLE */ - writel(0x01000000, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc); + pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; + setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); udelay(2); - /* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1 */ - writel(0x40000C10, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc); + /* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1, and enable lock */ + pllinfo = &tegra_pll_info_table[CLOCK_ID_DISPLAY]; + data = (12 << pllinfo->kcp_shift) | (1 << pllinfo->kvco_shift); + data |= (1 << PLLD_CLKENABLE) | (1 << pllinfo->lock_ena); + writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc); udelay(2); } diff --git a/arch/arm/mach-tegra/tegra114/cpu.c b/arch/arm/mach-tegra/tegra114/cpu.c index 18dc1af1b4..272a2ea281 100644 --- a/arch/arm/mach-tegra/tegra114/cpu.c +++ b/arch/arm/mach-tegra/tegra114/cpu.c @@ -1,17 +1,8 @@ /* - * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. + * (C) Copyright 2010-2014 + * NVIDIA Corporation <www.nvidia.com> * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> @@ -31,7 +22,7 @@ static void enable_cpu_power_rail(void) struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; u32 reg; - debug("enable_cpu_power_rail entry\n"); + debug("%s entry\n", __func__); /* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */ pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SCL_PZ6); @@ -61,14 +52,15 @@ static void enable_cpu_power_rail(void) static void enable_cpu_clocks(void) { struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU]; u32 reg; - debug("enable_cpu_clocks entry\n"); + debug("%s entry\n", __func__); /* Wait for PLL-X to lock */ do { reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); - } while ((reg & PLL_LOCK_MASK) == 0); + } while ((reg & (1 << pllinfo->lock_det)) == 0); /* Wait until all clocks are stable */ udelay(PLL_STABILIZATION_DELAY); @@ -87,7 +79,7 @@ static void remove_cpu_resets(void) struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; u32 reg; - debug("remove_cpu_resets entry\n"); + debug("%s entry\n", __func__); /* Take the slow non-CPU partition out of reset */ reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr); writel((reg | CLR_NONCPURESET), &clkrst->crc_rst_cpulp_cmplx_clr); @@ -111,7 +103,7 @@ static void remove_cpu_resets(void) } /** - * The T114 requires some special clock initialization, including setting up + * Tegra114 requires some special clock initialization, including setting up * the DVC I2C, turning on MSELECT and selecting the G CPU cluster */ void t114_init_clocks(void) @@ -121,7 +113,7 @@ void t114_init_clocks(void) struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; u32 val; - debug("t114_init_clocks entry\n"); + debug("%s entry\n", __func__); /* Set active CPU cluster to G */ clrbits_le32(&flow->cluster_control, 1); @@ -189,7 +181,7 @@ void t114_init_clocks(void) reset_set_enable(PERIPH_ID_MC1, 0); reset_set_enable(PERIPH_ID_DVFS, 0); - debug("t114_init_clocks exit\n"); + debug("%s exit\n", __func__); } static bool is_partition_powered(u32 partid) @@ -238,10 +230,9 @@ static void power_partition(u32 partid) void powerup_cpus(void) { - debug("powerup_cpus entry\n"); - /* We boot to the fast cluster */ - debug("powerup_cpus entry: G cluster\n"); + debug("%s entry: G cluster\n", __func__); + /* Power up the fast cluster rail partition */ power_partition(CRAIL); @@ -256,7 +247,7 @@ void start_cpu(u32 reset_vector) { u32 imme, inst; - debug("start_cpu entry, reset_vector = %x\n", reset_vector); + debug("%s entry, reset_vector = %x\n", __func__, reset_vector); t114_init_clocks(); @@ -302,7 +293,7 @@ void start_cpu(u32 reset_vector) inst |= 0xea000000; writel(inst, 0x4003fffc); - /* Write to orignal location for compatibility */ + /* Write to original location for compatibility */ writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR); /* If the CPU(s) don't already have power, power 'em up */ diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c index b9558484b0..912621863a 100644 --- a/arch/arm/mach-tegra/tegra124/clock.c +++ b/arch/arm/mach-tegra/tegra124/clock.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2013 + * (C) Copyright 2013-2015 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -566,6 +566,36 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { }; /* + * PLL divider shift/mask tables for all PLL IDs. + */ +struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { + /* + * T124: same as T114, some deviations from T2x/T30. + * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLX, etc.) + * If lock_ena or lock_det are >31, they're not used in that PLL. + */ + + { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F, + .lock_ena = 24, .lock_det = 27, .kcp_shift = 28, .kcp_mask = 3, .kvco_shift = 27, .kvco_mask = 1 }, /* PLLC */ + { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0, + .lock_ena = 0, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */ + { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, + .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLP */ + { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, + .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLA */ + { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01, + .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLU */ + { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, + .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD */ + { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F, + .lock_ena = 18, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */ + { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0, + .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ + { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, + .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */ +}; + +/* * Get the oscillator frequency, from the corresponding hardware configuration * field. Note that Tegra30+ support 3 new higher freqs, but we map back * to the old T20 freqs. Support for the higher oscillators is TBD. @@ -772,6 +802,8 @@ void clock_early_init(void) { struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + struct clk_pll_info *pllinfo; + u32 data; tegra30_set_up_pllp(); @@ -808,11 +840,15 @@ void clock_early_init(void) writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); /* PLLC_MISC: Set LOCK_ENABLE */ - writel(0x01000000, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc); + pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; + setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); udelay(2); - /* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1 */ - writel(0x40000C10, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc); + /* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1, and enable lock */ + pllinfo = &tegra_pll_info_table[CLOCK_ID_DISPLAY]; + data = (12 << pllinfo->kcp_shift) | (1 << pllinfo->kvco_shift); + data |= (1 << PLLD_CLKENABLE) | (1 << pllinfo->lock_ena); + writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc); udelay(2); } diff --git a/arch/arm/mach-tegra/tegra124/cpu.c b/arch/arm/mach-tegra/tegra124/cpu.c index 974f203f12..0aca6583ba 100644 --- a/arch/arm/mach-tegra/tegra124/cpu.c +++ b/arch/arm/mach-tegra/tegra124/cpu.c @@ -23,7 +23,7 @@ static void enable_cpu_power_rail(void) { struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; - debug("enable_cpu_power_rail entry\n"); + debug("%s entry\n", __func__); /* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */ pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SCL_PZ6); @@ -45,15 +45,16 @@ static void enable_cpu_power_rail(void) static void enable_cpu_clocks(void) { struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU]; u32 reg; - debug("enable_cpu_clocks entry\n"); + debug("%s entry\n", __func__); /* Wait for PLL-X to lock */ do { reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); debug("%s: PLLX base = 0x%08X\n", __func__, reg); - } while ((reg & PLL_LOCK_MASK) == 0); + } while ((reg & (1 << pllinfo->lock_det)) == 0); debug("%s: PLLX locked, delay for stable clocks\n", __func__); /* Wait until all clocks are stable */ @@ -83,7 +84,7 @@ static void remove_cpu_resets(void) struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; u32 reg; - debug("remove_cpu_resets entry\n"); + debug("%s entry\n", __func__); /* Take the slow and fast partitions out of reset */ reg = CLR_NONCPURESET; @@ -105,7 +106,7 @@ static void remove_cpu_resets(void) } /** - * The Tegra124 requires some special clock initialization, including setting up + * Tegra124 requires some special clock initialization, including setting up * the DVC I2C, turning on MSELECT and selecting the G CPU cluster */ void tegra124_init_clocks(void) @@ -116,7 +117,7 @@ void tegra124_init_clocks(void) (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; u32 val; - debug("tegra124_init_clocks entry\n"); + debug("%s entry\n", __func__); /* Set active CPU cluster to G */ clrbits_le32(&flow->cluster_control, 1); @@ -188,7 +189,7 @@ void tegra124_init_clocks(void) reset_set_enable(PERIPH_ID_MSELECT, 0); reset_set_enable(PERIPH_ID_DVFS, 0); - debug("tegra124_init_clocks exit\n"); + debug("%s exit\n", __func__); } static bool is_partition_powered(u32 partid) @@ -223,31 +224,29 @@ static void power_partition(u32 partid) void powerup_cpus(void) { - debug("powerup_cpus entry\n"); - /* We boot to the fast cluster */ - debug("powerup_cpus entry: G cluster\n"); + debug("%s entry: G cluster\n", __func__); /* Power up the fast cluster rail partition */ - debug("powerup_cpus: CRAIL\n"); + debug("%s: CRAIL\n", __func__); power_partition(CRAIL); /* Power up the fast cluster non-CPU partition */ - debug("powerup_cpus: C0NC\n"); + debug("%s: C0NC\n", __func__); power_partition(C0NC); /* Power up the fast cluster CPU0 partition */ - debug("powerup_cpus: CE0\n"); + debug("%s: CE0\n", __func__); power_partition(CE0); - debug("powerup_cpus: done\n"); + debug("%s: done\n", __func__); } void start_cpu(u32 reset_vector) { struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; - debug("start_cpu entry, reset_vector = %x\n", reset_vector); + debug("%s entry, reset_vector = %x\n", __func__, reset_vector); tegra124_init_clocks(); @@ -261,5 +260,5 @@ void start_cpu(u32 reset_vector) remove_cpu_resets(); writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR); powerup_cpus(); - debug("start_cpu exit, should continue @ reset_vector\n"); + debug("%s exit, should continue @ reset_vector\n", __func__); } diff --git a/arch/arm/mach-tegra/tegra20/clock.c b/arch/arm/mach-tegra/tegra20/clock.c index 7b9e10cd93..dea459b164 100644 --- a/arch/arm/mach-tegra/tegra20/clock.c +++ b/arch/arm/mach-tegra/tegra20/clock.c @@ -1,5 +1,7 @@ /* * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2010-2015 + * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -355,6 +357,36 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { }; /* + * PLL divider shift/mask tables for all PLL IDs. + */ +struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { + /* + * T20 and T25 + * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLX, etc.) + * If lock_ena or lock_det are >31, they're not used in that PLL. + */ + + { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x0F, + .lock_ena = 24, .lock_det = 27, .kcp_shift = 28, .kcp_mask = 3, .kvco_shift = 27, .kvco_mask = 1 }, /* PLLC */ + { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 0, .p_mask = 0, + .lock_ena = 0, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */ + { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, + .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLP */ + { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, + .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLA */ + { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01, + .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLU */ + { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, + .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD */ + { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x0F, + .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */ + { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0, + .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ + { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, + .lock_ena = 18, .lock_det = 0, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS */ +}; + +/* * Get the oscillator frequency, from the corresponding hardware configuration * field. T20 has 4 frequencies that it supports. */ diff --git a/arch/arm/mach-tegra/tegra210/Kconfig b/arch/arm/mach-tegra/tegra210/Kconfig index 147e6a83d7..bd34db7117 100644 --- a/arch/arm/mach-tegra/tegra210/Kconfig +++ b/arch/arm/mach-tegra/tegra210/Kconfig @@ -3,6 +3,21 @@ if TEGRA210 choice prompt "Tegra210 board select" +config TARGET_E2220_1170 + bool "NVIDIA Tegra210 E2220-1170 board" + help + E2220-1170 is a Tegra210 bringup board with onboard SoC, DRAM, + eMMC, SD card slot, HDMI, USB micro-B port, and sockets for various + expansion modules. + +config TARGET_P2371_0000 + bool "NVIDIA Tegra210 P2371-0000 board" + help + P2371-0000 is a P2581 or P2530 CPU board married to a P2595 I/O + board. The combination contains SoC, DRAM, eMMC, SD card slot, + HDMI, USB micro-B port, Ethernet via USB3, USB3 host port, SATA, + a GPIO expansion header, and an analog audio jack. + config TARGET_P2571 bool "NVIDIA Tegra210 P2571 base board" help @@ -13,6 +28,8 @@ endchoice config SYS_SOC default "tegra210" +source "board/nvidia/e2220-1170/Kconfig" +source "board/nvidia/p2371-0000/Kconfig" source "board/nvidia/p2571/Kconfig" endif diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c index 4e7d7932cc..a7b3a949fc 100644 --- a/arch/arm/mach-tegra/tegra210/clock.c +++ b/arch/arm/mach-tegra/tegra210/clock.c @@ -631,6 +631,34 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { }; /* + * PLL divider shift/mask tables for all PLL IDs. + */ +struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { + /* + * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLC, etc.) + * If lock_ena or lock_det are >31, they're not used in that PLL (PLLC, etc.) + */ + { .m_shift = 0, .m_mask = 0xFF, .n_shift = 10, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F, + .lock_ena = 32, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLC */ + { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F, + .lock_ena = 4, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */ + { .m_shift = 0, .m_mask = 0xFF, .n_shift = 10, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F, + .lock_ena = 18, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 3, .kvco_shift = 2, .kvco_mask = 1 }, /* PLLP */ + { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F, + .lock_ena = 28, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLA */ + { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 16, .p_mask = 0x1F, + .lock_ena = 29, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLU */ + { .m_shift = 0, .m_mask = 0xFF, .n_shift = 11, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x07, + .lock_ena = 18, .lock_det = 27, .kcp_shift = 23, .kcp_mask = 3, .kvco_shift = 22, .kvco_mask = 1 }, /* PLLD */ + { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F, + .lock_ena = 18, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLX */ + { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0, + .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ + { .m_shift = 0, .m_mask = 0, .n_shift = 0, .n_mask = 0, .p_shift = 0, .p_mask = 0, + .lock_ena = 0, .lock_det = 0, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLS (gone)*/ +}; + +/* * Get the oscillator frequency, from the corresponding hardware configuration * field. Note that Tegra30+ support 3 new higher freqs, but we map back * to the old T20 freqs. Support for the higher oscillators is TBD. @@ -649,8 +677,8 @@ enum clock_osc_freq clock_get_osc_freq(void) */ if (reg == 5) { debug("OSC_FREQ is 38.4MHz (%d) ...\n", reg); - /* Map it to 19.2MHz for now. 38.4MHz OSC support TBD */ - return 1; + /* Map it to the 5th CLOCK_OSC_ enum, i.e. 4 */ + return 4; } /* @@ -903,6 +931,7 @@ void clock_early_init(void) { struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_DISPLAY]; u32 data; tegra210_setup_pllp(); @@ -930,6 +959,10 @@ void clock_early_init(void) clock_set_rate(CLOCK_ID_CGENERAL, 125, 4, 0, 0); clock_set_rate(CLOCK_ID_DISPLAY, 96, 2, 0, 12); break; + case CLOCK_OSC_FREQ_38_4: + clock_set_rate(CLOCK_ID_CGENERAL, 125, 8, 0, 0); + clock_set_rate(CLOCK_ID_DISPLAY, 96, 4, 0, 0); + break; default: /* * These are not supported. It is too early to print a @@ -953,7 +986,7 @@ void clock_early_init(void) udelay(2); /* PLLD_MISC: Set CLKENABLE and LOCK_DETECT bits */ - data = (1 << PLLD_ENABLE_CLK) | (1 << PLLD_EN_LCKDET); + data = (1 << PLLD_ENABLE_CLK) | (1 << pllinfo->lock_ena); writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc); udelay(2); } diff --git a/arch/arm/mach-tegra/tegra30/clock.c b/arch/arm/mach-tegra/tegra30/clock.c index 0eb0f0ade3..3ce508b0b2 100644 --- a/arch/arm/mach-tegra/tegra30/clock.c +++ b/arch/arm/mach-tegra/tegra30/clock.c @@ -1,17 +1,8 @@ /* - * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. + * (C) Copyright 2010-2015 + * NVIDIA Corporation <www.nvidia.com> * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0+ */ /* Tegra30 Clock control functions */ @@ -415,6 +406,36 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { }; /* + * PLL divider shift/mask tables for all PLL IDs. + */ +struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { + /* + * T30: some deviations from T2x. + * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLX, etc.) + * If lock_ena or lock_det are >31, they're not used in that PLL. + */ + + { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x0F, + .lock_ena = 24, .lock_det = 27, .kcp_shift = 28, .kcp_mask = 3, .kvco_shift = 27, .kvco_mask = 1 }, /* PLLC */ + { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 0, .p_mask = 0, + .lock_ena = 0, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */ + { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, + .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLP */ + { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, + .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLA */ + { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01, + .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLU */ + { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, + .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD */ + { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F, + .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */ + { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0, + .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ + { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, + .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */ +}; + +/* * Get the oscillator frequency, from the corresponding hardware configuration * field. Note that T30 supports 3 new higher freqs, but we map back * to the old T20 freqs. Support for the higher oscillators is TBD. diff --git a/board/nvidia/e2220-1170/Kconfig b/board/nvidia/e2220-1170/Kconfig new file mode 100644 index 0000000000..0a30f49362 --- /dev/null +++ b/board/nvidia/e2220-1170/Kconfig @@ -0,0 +1,12 @@ +if TARGET_E2220_1170 + +config SYS_BOARD + default "e2220-1170" + +config SYS_VENDOR + default "nvidia" + +config SYS_CONFIG_NAME + default "e2220-1170" + +endif diff --git a/board/nvidia/e2220-1170/MAINTAINERS b/board/nvidia/e2220-1170/MAINTAINERS new file mode 100644 index 0000000000..0abb378840 --- /dev/null +++ b/board/nvidia/e2220-1170/MAINTAINERS @@ -0,0 +1,6 @@ +E2220-1170 BOARD +M: Tom Warren <twarren@nvidia.com> +S: Maintained +F: board/nvidia/e2220-1170/ +F: include/configs/e2220-1170.h +F: configs/e2220-1170_defconfig diff --git a/board/nvidia/e2220-1170/Makefile b/board/nvidia/e2220-1170/Makefile new file mode 100644 index 0000000000..c956b1972d --- /dev/null +++ b/board/nvidia/e2220-1170/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2013-2015 +# NVIDIA Corporation <www.nvidia.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += e2220-1170.o diff --git a/board/nvidia/e2220-1170/e2220-1170.c b/board/nvidia/e2220-1170/e2220-1170.c new file mode 100644 index 0000000000..d66a72e520 --- /dev/null +++ b/board/nvidia/e2220-1170/e2220-1170.c @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <asm/arch/gpio.h> +#include <asm/arch/pinmux.h> +#include "../p2571/max77620_init.h" +#include "pinmux-config-e2220-1170.h" + +void pin_mux_mmc(void) +{ + struct udevice *dev; + uchar val; + int ret; + + /* Turn on MAX77620 LDO2 to 3.3V for SD card power */ + debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__); + ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev); + if (ret) { + printf("%s: Cannot find MAX77620 I2C chip\n", __func__); + return; + } + /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ + val = 0xF2; + ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); +} + +/* + * Routine: pinmux_init + * Description: Do individual peripheral pinmux configs + */ +void pinmux_init(void) +{ + pinmux_clear_tristate_input_clamping(); + + gpio_config_table(e2220_1170_gpio_inits, + ARRAY_SIZE(e2220_1170_gpio_inits)); + + pinmux_config_pingrp_table(e2220_1170_pingrps, + ARRAY_SIZE(e2220_1170_pingrps)); + + pinmux_config_drvgrp_table(e2220_1170_drvgrps, + ARRAY_SIZE(e2220_1170_drvgrps)); +} diff --git a/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h b/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h new file mode 100644 index 0000000000..7eb1e6c1b3 --- /dev/null +++ b/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h @@ -0,0 +1,277 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * THIS FILE IS AUTO-GENERATED - DO NOT EDIT! + * + * To generate this file, use the tegra-pinmux-scripts tool available from + * https://github.com/NVIDIA/tegra-pinmux-scripts + * Run "board-to-uboot.py e2220-1170". + */ + +#ifndef _PINMUX_CONFIG_E2220_1170_H_ +#define _PINMUX_CONFIG_E2220_1170_H_ + +#define GPIO_INIT(_gpio, _init) \ + { \ + .gpio = GPIO_P##_gpio, \ + .init = TEGRA_GPIO_INIT_##_init, \ + } + +static const struct tegra_gpio_config e2220_1170_gpio_inits[] = { + /* gpio, init_val */ + GPIO_INIT(A5, IN), + GPIO_INIT(A6, IN), + GPIO_INIT(B4, IN), + GPIO_INIT(E6, IN), + GPIO_INIT(G2, OUT0), + GPIO_INIT(G3, OUT0), + GPIO_INIT(H0, OUT0), + GPIO_INIT(H1, OUT0), + GPIO_INIT(H2, IN), + GPIO_INIT(H3, OUT0), + GPIO_INIT(H4, OUT0), + GPIO_INIT(H5, IN), + GPIO_INIT(H6, OUT0), + GPIO_INIT(H7, OUT0), + GPIO_INIT(I0, OUT0), + GPIO_INIT(I1, IN), + GPIO_INIT(I2, OUT0), + GPIO_INIT(I3, OUT0), + GPIO_INIT(K0, IN), + GPIO_INIT(K1, OUT0), + GPIO_INIT(K2, OUT0), + GPIO_INIT(K3, OUT0), + GPIO_INIT(K4, IN), + GPIO_INIT(K5, OUT0), + GPIO_INIT(K6, IN), + GPIO_INIT(K7, OUT0), + GPIO_INIT(L0, OUT0), + GPIO_INIT(S4, OUT0), + GPIO_INIT(S5, OUT0), + GPIO_INIT(S6, OUT0), + GPIO_INIT(S7, OUT0), + GPIO_INIT(T0, OUT0), + GPIO_INIT(T1, OUT0), + GPIO_INIT(V1, OUT0), + GPIO_INIT(V2, OUT0), + GPIO_INIT(V3, IN), + GPIO_INIT(V5, OUT0), + GPIO_INIT(V6, OUT0), + GPIO_INIT(X0, IN), + GPIO_INIT(X1, IN), + GPIO_INIT(X2, IN), + GPIO_INIT(X3, IN), + GPIO_INIT(X4, IN), + GPIO_INIT(X5, IN), + GPIO_INIT(X6, IN), + GPIO_INIT(X7, IN), + GPIO_INIT(Y0, IN), + GPIO_INIT(Y1, IN), + GPIO_INIT(Z0, IN), + GPIO_INIT(Z4, OUT0), + GPIO_INIT(BB2, OUT0), + GPIO_INIT(BB3, OUT0), + GPIO_INIT(BB4, IN), + GPIO_INIT(CC1, IN), + GPIO_INIT(CC5, OUT0), + GPIO_INIT(CC6, IN), + GPIO_INIT(CC7, OUT0), +}; + +#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .od = PMUX_PIN_OD_##_od, \ + .e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \ + .lock = PMUX_PIN_LOCK_DEFAULT, \ + } + +static const struct pmux_pingrp_config e2220_1170_pingrps[] = { + /* pingrp, mux, pull, tri, e_input, od, e_io_hv */ + PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL), + PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, UP, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(PEX_WAKE_N_PA2, PE, UP, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL), + PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, UP, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PA6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP1_FS_PB0, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP1_DIN_PB1, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP1_DOUT_PB2, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP1_SCLK_PB3, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI2_MOSI_PB4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI2_MISO_PB5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI2_SCK_PB6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI2_CS0_PB7, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI1_MOSI_PC0, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI1_MISO_PC1, SPI1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI1_SCK_PC2, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI1_CS0_PC3, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI1_CS1_PC4, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI4_SCK_PC5, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI4_CS0_PC6, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI4_MOSI_PC7, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI4_MISO_PD0, SPI4, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART3_TX_PD1, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART3_RX_PD2, UARTC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART3_RTS_PD3, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART3_CTS_PD4, UARTC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DMIC1_CLK_PE0, DMIC1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(DMIC1_DAT_PE1, DMIC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DMIC2_CLK_PE2, DMIC2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(DMIC2_DAT_PE3, DMIC2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DMIC3_CLK_PE4, DMIC3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(DMIC3_DAT_PE5, DMIC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PE6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(UART2_TX_PG0, UART, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART2_RX_PG1, UART, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART2_RTS_PG2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART2_CTS_PG3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(WIFI_RST_PH1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PH6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(AP_WAKE_NFC_PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(NFC_INT_PI1, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(GPS_EN_PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(GPS_RST_PI3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(DAP4_FS_PJ4, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP4_DIN_PJ5, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP4_DOUT_PJ6, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP4_SCLK_PJ7, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK0, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PK2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PK3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PK4, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PK6, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PL0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PL1, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(CAM1_MCLK_PS0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM2_MCLK_PS1, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(CAM_RST_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM_AF_EN_PS5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM_FLASH_EN_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM1_PWDN_PS7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM2_PWDN_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM1_STROBE_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART1_RTS_PU2, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART1_CTS_PU3, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(LCD_RST_PV2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(LCD_GPIO1_PV3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(AP_READY_PV5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(TOUCH_CLK_PV7, TOUCH, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(MODEM_WAKE_AP_PX0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(TOUCH_INT_PX1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(MOTION_INT_PX2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(ALS_PROX_INT_PX3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_POWER_ON_PX5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_SLIDE_SW_PY0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(LCD_TE_PY2, DISPLAYA, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(AUD_MCLK_PBB0, AUD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(GPIO_X1_AUD_PBB3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(GPIO_X3_AUD_PBB4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(SPDIF_OUT_PCC2, SPDIF, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPDIF_IN_PCC3, SPDIF, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(USB_VBUS_EN1_PCC5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL), + PINCFG(DP_HPD0_PCC6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PCC7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL), + PINCFG(SPI2_CS1_PDD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_SCK_PEE0, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(QSPI_CS_N_PEE1, QSPI, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO0_PEE2, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO1_PEE3, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO2_PEE4, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO3_PEE5, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CLK_REQ, SYS, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), +}; + +#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ + { \ + .drvgrp = PMUX_DRVGRP_##_drvgrp, \ + .slwf = _slwf, \ + .slwr = _slwr, \ + .drvup = _drvup, \ + .drvdn = _drvdn, \ + .lpmd = PMUX_LPMD_##_lpmd, \ + .schmt = PMUX_SCHMT_##_schmt, \ + .hsm = PMUX_HSM_##_hsm, \ + } + +static const struct pmux_drvgrp_config e2220_1170_drvgrps[] = { +}; + +#endif /* PINMUX_CONFIG_E2220_1170_H */ diff --git a/board/nvidia/jetson-tk1/jetson-tk1.c b/board/nvidia/jetson-tk1/jetson-tk1.c index 52425a8f6d..3c21767ce4 100644 --- a/board/nvidia/jetson-tk1/jetson-tk1.c +++ b/board/nvidia/jetson-tk1/jetson-tk1.c @@ -11,6 +11,7 @@ #include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> +#include <asm/arch-tegra/gpu.h> #include "pinmux-config-jetson-tk1.h" @@ -79,3 +80,10 @@ int board_eth_init(bd_t *bis) return pci_eth_init(bis); } #endif /* PCI */ + +int ft_board_setup(void *blob, bd_t *bd) +{ + gpu_enable_node(blob, "/gpu@0,57000000"); + + return 0; +} diff --git a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h index 863721b2a3..b2b2057e3b 100644 --- a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h +++ b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h @@ -4,6 +4,14 @@ * SPDX-License-Identifier: GPL-2.0+ */ +/* + * THIS FILE IS AUTO-GENERATED - DO NOT EDIT! + * + * To generate this file, use the tegra-pinmux-scripts tool available from + * https://github.com/NVIDIA/tegra-pinmux-scripts + * Run "board-to-uboot.py jetson-tk1". + */ + #ifndef _PINMUX_CONFIG_JETSON_TK1_H_ #define _PINMUX_CONFIG_JETSON_TK1_H_ diff --git a/board/nvidia/nyan-big/pinmux-config-nyan-big.h b/board/nvidia/nyan-big/pinmux-config-nyan-big.h index 9c838ba764..dca0171f26 100644 --- a/board/nvidia/nyan-big/pinmux-config-nyan-big.h +++ b/board/nvidia/nyan-big/pinmux-config-nyan-big.h @@ -4,6 +4,14 @@ * SPDX-License-Identifier: GPL-2.0+ */ +/* + * THIS FILE IS AUTO-GENERATED - DO NOT EDIT! + * + * To generate this file, use the tegra-pinmux-scripts tool available from + * https://github.com/NVIDIA/tegra-pinmux-scripts + * Run "board-to-uboot.py nyan-big". + */ + #ifndef _PINMUX_CONFIG_NYAN_BIG_H_ #define _PINMUX_CONFIG_NYAN_BIG_H_ diff --git a/board/nvidia/p2371-0000/Kconfig b/board/nvidia/p2371-0000/Kconfig new file mode 100644 index 0000000000..f94be12be1 --- /dev/null +++ b/board/nvidia/p2371-0000/Kconfig @@ -0,0 +1,12 @@ +if TARGET_P2371_0000 + +config SYS_BOARD + default "p2371-0000" + +config SYS_VENDOR + default "nvidia" + +config SYS_CONFIG_NAME + default "p2371-0000" + +endif diff --git a/board/nvidia/p2371-0000/MAINTAINERS b/board/nvidia/p2371-0000/MAINTAINERS new file mode 100644 index 0000000000..e6d04bf7c5 --- /dev/null +++ b/board/nvidia/p2371-0000/MAINTAINERS @@ -0,0 +1,6 @@ +P2371-0000 BOARD +M: Tom Warren <twarren@nvidia.com> +S: Maintained +F: board/nvidia/p2371-0000/ +F: include/configs/p2371-0000.h +F: configs/p2371-0000_defconfig diff --git a/board/nvidia/p2371-0000/Makefile b/board/nvidia/p2371-0000/Makefile new file mode 100644 index 0000000000..9f580ae5b2 --- /dev/null +++ b/board/nvidia/p2371-0000/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2013-2015 +# NVIDIA Corporation <www.nvidia.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += p2371-0000.o diff --git a/board/nvidia/p2371-0000/p2371-0000.c b/board/nvidia/p2371-0000/p2371-0000.c new file mode 100644 index 0000000000..9df543a4c9 --- /dev/null +++ b/board/nvidia/p2371-0000/p2371-0000.c @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <asm/arch/gpio.h> +#include <asm/arch/pinmux.h> +#include "../p2571/max77620_init.h" +#include "pinmux-config-p2371-0000.h" + +void pin_mux_mmc(void) +{ + struct udevice *dev; + uchar val; + int ret; + + /* Turn on MAX77620 LDO2 to 3.3V for SD card power */ + debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__); + ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev); + if (ret) { + printf("%s: Cannot find MAX77620 I2C chip\n", __func__); + return; + } + /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ + val = 0xF2; + ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); +} + +/* + * Routine: pinmux_init + * Description: Do individual peripheral pinmux configs + */ +void pinmux_init(void) +{ + pinmux_clear_tristate_input_clamping(); + + gpio_config_table(p2371_0000_gpio_inits, + ARRAY_SIZE(p2371_0000_gpio_inits)); + + pinmux_config_pingrp_table(p2371_0000_pingrps, + ARRAY_SIZE(p2371_0000_pingrps)); + + pinmux_config_drvgrp_table(p2371_0000_drvgrps, + ARRAY_SIZE(p2371_0000_drvgrps)); +} diff --git a/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h b/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h new file mode 100644 index 0000000000..35706b4745 --- /dev/null +++ b/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h @@ -0,0 +1,268 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * THIS FILE IS AUTO-GENERATED - DO NOT EDIT! + * + * To generate this file, use the tegra-pinmux-scripts tool available from + * https://github.com/NVIDIA/tegra-pinmux-scripts + * Run "board-to-uboot.py p2371-0000". + */ + +#ifndef _PINMUX_CONFIG_P2371_0000_H_ +#define _PINMUX_CONFIG_P2371_0000_H_ + +#define GPIO_INIT(_gpio, _init) \ + { \ + .gpio = GPIO_P##_gpio, \ + .init = TEGRA_GPIO_INIT_##_init, \ + } + +static const struct tegra_gpio_config p2371_0000_gpio_inits[] = { + /* gpio, init_val */ + GPIO_INIT(A5, IN), + GPIO_INIT(E4, OUT0), + GPIO_INIT(E6, IN), + GPIO_INIT(G0, IN), + GPIO_INIT(G3, OUT0), + GPIO_INIT(H0, OUT0), + GPIO_INIT(H2, IN), + GPIO_INIT(H3, OUT0), + GPIO_INIT(H4, OUT0), + GPIO_INIT(H5, IN), + GPIO_INIT(H6, OUT0), + GPIO_INIT(H7, OUT0), + GPIO_INIT(I0, OUT0), + GPIO_INIT(I1, IN), + GPIO_INIT(I2, OUT0), + GPIO_INIT(I3, OUT0), + GPIO_INIT(K4, IN), + GPIO_INIT(K5, OUT0), + GPIO_INIT(K6, IN), + GPIO_INIT(K7, OUT0), + GPIO_INIT(L0, OUT0), + GPIO_INIT(S4, OUT0), + GPIO_INIT(S5, OUT0), + GPIO_INIT(S6, OUT0), + GPIO_INIT(S7, OUT0), + GPIO_INIT(T0, OUT0), + GPIO_INIT(T1, OUT0), + GPIO_INIT(V1, OUT0), + GPIO_INIT(V2, OUT0), + GPIO_INIT(V5, OUT0), + GPIO_INIT(V6, OUT0), + GPIO_INIT(V7, OUT1), + GPIO_INIT(X0, IN), + GPIO_INIT(X1, IN), + GPIO_INIT(X2, IN), + GPIO_INIT(X3, IN), + GPIO_INIT(X4, IN), + GPIO_INIT(X5, IN), + GPIO_INIT(X6, IN), + GPIO_INIT(X7, IN), + GPIO_INIT(Y1, IN), + GPIO_INIT(Z0, IN), + GPIO_INIT(Z4, OUT0), + GPIO_INIT(BB2, OUT0), + GPIO_INIT(BB3, OUT0), + GPIO_INIT(CC1, IN), + GPIO_INIT(CC6, IN), + GPIO_INIT(CC7, OUT0), +}; + +#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .od = PMUX_PIN_OD_##_od, \ + .e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \ + .lock = PMUX_PIN_LOCK_DEFAULT, \ + } + +static const struct pmux_pingrp_config p2371_0000_pingrps[] = { + /* pingrp, mux, pull, tri, e_input, od, e_io_hv */ + PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH), + PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(PEX_WAKE_N_PA2, PE, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH), + PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PA6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(DAP1_FS_PB0, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP1_DIN_PB1, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP1_DOUT_PB2, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP1_SCLK_PB3, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI2_MOSI_PB4, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI2_MISO_PB5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI2_SCK_PB6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI2_CS0_PB7, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI1_MOSI_PC0, SPI1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI1_MISO_PC1, SPI1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI1_SCK_PC2, SPI1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI1_CS0_PC3, SPI1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI1_CS1_PC4, SPI1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI4_SCK_PC5, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI4_CS0_PC6, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI4_MOSI_PC7, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI4_MISO_PD0, SPI4, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART3_TX_PD1, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART3_RX_PD2, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART3_RTS_PD3, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART3_CTS_PD4, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DMIC1_CLK_PE0, DMIC1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(DMIC1_DAT_PE1, DMIC1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DMIC2_CLK_PE2, DMIC2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(DMIC2_DAT_PE3, DMIC2, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DMIC3_CLK_PE4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(DMIC3_DAT_PE5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PE6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(UART2_TX_PG0, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART2_RX_PG1, UARTB, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART2_RTS_PG2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART2_CTS_PG3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(WIFI_RST_PH1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PH6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(AP_WAKE_NFC_PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(NFC_INT_PI1, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(GPS_EN_PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(GPS_RST_PI3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(DAP4_FS_PJ4, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP4_DIN_PJ5, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP4_DOUT_PJ6, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP4_SCLK_PJ7, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK0, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK1, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK2, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK3, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK4, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PK6, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PL0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PL1, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(CAM1_MCLK_PS0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM2_MCLK_PS1, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(CAM_RST_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM_AF_EN_PS5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM_FLASH_EN_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM1_PWDN_PS7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM2_PWDN_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM1_STROBE_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART1_RTS_PU2, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART1_CTS_PU3, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(LCD_RST_PV2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(LCD_GPIO1_PV3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(AP_READY_PV5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(TOUCH_CLK_PV7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(MODEM_WAKE_AP_PX0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(TOUCH_INT_PX1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(MOTION_INT_PX2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(ALS_PROX_INT_PX3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_POWER_ON_PX5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_SLIDE_SW_PY0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(LCD_TE_PY2, DISPLAYA, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PZ3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PZ4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(AUD_MCLK_PBB0, AUD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(GPIO_X1_AUD_PBB3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(GPIO_X3_AUD_PBB4, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(SPDIF_OUT_PCC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPDIF_IN_PCC3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(USB_VBUS_EN1_PCC5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL), + PINCFG(DP_HPD0_PCC6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PCC7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL), + PINCFG(SPI2_CS1_PDD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_SCK_PEE0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_CS_N_PEE1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO0_PEE2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO1_PEE3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO2_PEE4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO3_PEE5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CLK_REQ, SYS, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), +}; + +#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ + { \ + .drvgrp = PMUX_DRVGRP_##_drvgrp, \ + .slwf = _slwf, \ + .slwr = _slwr, \ + .drvup = _drvup, \ + .drvdn = _drvdn, \ + .lpmd = PMUX_LPMD_##_lpmd, \ + .schmt = PMUX_SCHMT_##_schmt, \ + .hsm = PMUX_HSM_##_hsm, \ + } + +static const struct pmux_drvgrp_config p2371_0000_drvgrps[] = { +}; + +#endif /* PINMUX_CONFIG_P2371_0000_H */ diff --git a/board/nvidia/p2571/Makefile b/board/nvidia/p2571/Makefile index 223062e9a3..627b7efa2a 100644 --- a/board/nvidia/p2571/Makefile +++ b/board/nvidia/p2571/Makefile @@ -5,5 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += max77620_init.o obj-y += p2571.o diff --git a/board/nvidia/p2571/max77620_init.c b/board/nvidia/p2571/max77620_init.c deleted file mode 100644 index ed8d4dc5d7..0000000000 --- a/board/nvidia/p2571/max77620_init.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2013-2015 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch-tegra/tegra_i2c.h> -#include "max77620_init.h" - -/* MAX77620-PMIC-specific early init code - get CPU rails up, etc */ - -void tegra_i2c_ll_write_addr(uint addr, uint config) -{ - struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; - - writel(addr, ®->cmd_addr0); - writel(config, ®->cnfg); -} - -void tegra_i2c_ll_write_data(uint data, uint config) -{ - struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; - - writel(data, ®->cmd_data1); - writel(config, ®->cnfg); -} - -void pmic_enable_cpu_vdd(void) -{ - uint reg; - debug("%s entry\n", __func__); - - /* Setup/Enable GPIO5 - VDD_CPU_REG_EN */ - debug("%s: Setting GPIO5 to enable CPU regulator\n", __func__); - /* B3=1=logic high,B2=dontcare,B1=0=output,B0=1=push-pull */ - reg = 0x0900 | MAX77620_GPIO5_REG; - tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); - tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); - udelay(10 * 1000); - - /* Setup/Enable GPIO1 - VDD_HDMI_5V0_BST_EN */ - debug("%s: Setting GPIO1 to enable HDMI\n", __func__); - reg = 0x0900 | MAX77620_GPIO1_REG; - tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); - tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); - udelay(10 * 1000); - - /* GPIO 0,1,5,6,7 = GPIO, 2,3,4 = alt mode */ - reg = 0x1C00 | MAX77620_AME_GPIO; - tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); - tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); - udelay(10 * 1000); - - /* Disable SD1 Remote Sense, Set SD1 for LPDDR4 to 1.125v */ - debug("%s: Set SD1 for LPDDR4, disable SD1RS, voltage to 1.125v\n", - __func__); - /* bit1=0, SD1 remote sense disabled */ - reg = 0x0400 | MAX77620_CNFG2SD_REG; - tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); - tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); - udelay(10 * 1000); - - /* SD1 output = 1.125V */ - reg = 0x2A00 | MAX77620_SD1_REG; - tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); - tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); - udelay(10 * 1000); - - debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__); - /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ - reg = 0xF200 | MAX77620_CNFG1_L2_REG; - tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); - tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); - udelay(10 * 1000); - - debug("%s: Set LDO1 for USB3 phy power to 1.05V??\n", __func__); - /* 0xCA for 105v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ - reg = 0xCA00 | MAX77620_CNFG1_L1_REG; - tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); - tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); - udelay(10 * 1000); -} diff --git a/board/nvidia/p2571/max77620_init.h b/board/nvidia/p2571/max77620_init.h index 9d5cce7c6e..92c3719112 100644 --- a/board/nvidia/p2571/max77620_init.h +++ b/board/nvidia/p2571/max77620_init.h @@ -10,7 +10,8 @@ /* MAX77620-PMIC-specific early init regs */ -#define MAX77620_I2C_ADDR 0x78 /* or 0x3C 7-bit */ +#define MAX77620_I2C_ADDR 0x78 +#define MAX77620_I2C_ADDR_7BIT 0x3C #define MAX77620_SD0_REG 0x16 #define MAX77620_SD1_REG 0x17 diff --git a/board/nvidia/p2571/p2571.c b/board/nvidia/p2571/p2571.c index fc710c1750..d33e4d12b2 100644 --- a/board/nvidia/p2571/p2571.c +++ b/board/nvidia/p2571/p2571.c @@ -6,10 +6,34 @@ */ #include <common.h> +#include <i2c.h> #include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> +#include <asm/gpio.h> +#include "max77620_init.h" +#include <asm/arch-tegra/gpu.h> #include "pinmux-config-p2571.h" +void pin_mux_mmc(void) +{ + struct udevice *dev; + uchar val; + int ret; + + /* Turn on MAX77620 LDO2 to 3.3V for SD card power */ + debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__); + ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev); + if (ret) { + printf("%s: Cannot find MAX77620 I2C chip\n", __func__); + return; + } + /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ + val = 0xF2; + ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); +} + /* * Routine: pinmux_init * Description: Do individual peripheral pinmux configs @@ -27,3 +51,20 @@ void pinmux_init(void) pinmux_config_drvgrp_table(p2571_drvgrps, ARRAY_SIZE(p2571_drvgrps)); } + +/* + * Routine: start_cpu_fan + * Description: Enable/start PWM CPU fan on P2571 + */ +void start_cpu_fan(void) +{ + /* GPIO_PE4 is PS_VDD_FAN_ENABLE */ + gpio_request(GPIO_PE4, "FAN_VDD"); + gpio_direction_output(GPIO_PE4, 1); +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + gpu_enable_node(blob, "/gpu@0,57000000"); + return 0; +} diff --git a/board/nvidia/p2571/pinmux-config-p2571.h b/board/nvidia/p2571/pinmux-config-p2571.h index ac414f0da5..d3233016b5 100644 --- a/board/nvidia/p2571/pinmux-config-p2571.h +++ b/board/nvidia/p2571/pinmux-config-p2571.h @@ -4,6 +4,14 @@ * SPDX-License-Identifier: GPL-2.0+ */ +/* + * THIS FILE IS AUTO-GENERATED - DO NOT EDIT! + * + * To generate this file, use the tegra-pinmux-scripts tool available from + * https://github.com/NVIDIA/tegra-pinmux-scripts + * Run "board-to-uboot.py p2571". + */ + #ifndef _PINMUX_CONFIG_P2571_H_ #define _PINMUX_CONFIG_P2571_H_ diff --git a/board/nvidia/venice2/pinmux-config-venice2.h b/board/nvidia/venice2/pinmux-config-venice2.h index bf8e3fd965..fb444b3b1d 100644 --- a/board/nvidia/venice2/pinmux-config-venice2.h +++ b/board/nvidia/venice2/pinmux-config-venice2.h @@ -4,6 +4,14 @@ * SPDX-License-Identifier: GPL-2.0+ */ +/* + * THIS FILE IS AUTO-GENERATED - DO NOT EDIT! + * + * To generate this file, use the tegra-pinmux-scripts tool available from + * https://github.com/NVIDIA/tegra-pinmux-scripts + * Run "board-to-uboot.py venice2". + */ + #ifndef _PINMUX_CONFIG_VENICE2_H_ #define _PINMUX_CONFIG_VENICE2_H_ diff --git a/board/nvidia/venice2/venice2.c b/board/nvidia/venice2/venice2.c index c56ef129d6..3e2b9a7745 100644 --- a/board/nvidia/venice2/venice2.c +++ b/board/nvidia/venice2/venice2.c @@ -8,6 +8,7 @@ #include <common.h> #include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> +#include <asm/arch-tegra/gpu.h> #include "pinmux-config-venice2.h" /* @@ -27,3 +28,10 @@ void pinmux_init(void) pinmux_config_drvgrp_table(venice2_drvgrps, ARRAY_SIZE(venice2_drvgrps)); } + +int ft_board_setup(void *blob, bd_t *bd) +{ + gpu_enable_node(blob, "/gpu@0,57000000"); + + return 0; +} diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig index e7443f8be5..2d80247599 100644 --- a/configs/dalmore_defconfig +++ b/configs/dalmore_defconfig @@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra114-dalmore" # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_SPL_DM=y +CONFIG_TEGRA114_SPI=y CONFIG_SPI_FLASH=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/e2220-1170_defconfig b/configs/e2220-1170_defconfig new file mode 100644 index 0000000000..455e7892b5 --- /dev/null +++ b/configs/e2220-1170_defconfig @@ -0,0 +1,17 @@ +CONFIG_ARM=y +CONFIG_TEGRA=y +CONFIG_TEGRA210=y +CONFIG_TARGET_E2220_1170=y +CONFIG_DEFAULT_DEVICE_TREE="tegra210-e2220-1170" +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +CONFIG_SPL_DM=y +CONFIG_TEGRA114_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig index 7085469bb6..44c7a8ef26 100644 --- a/configs/jetson-tk1_defconfig +++ b/configs/jetson-tk1_defconfig @@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra124-jetson-tk1" # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_SPL_DM=y +CONFIG_TEGRA114_SPI=y CONFIG_SPI_FLASH=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig index 79b74a7ba3..ccf656b289 100644 --- a/configs/nyan-big_defconfig +++ b/configs/nyan-big_defconfig @@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra124-nyan-big" # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_SPL_DM=y +CONFIG_TEGRA114_SPI=y CONFIG_SPI_FLASH=y CONFIG_CMD_CROS_EC=y CONFIG_CROS_EC=y diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig new file mode 100644 index 0000000000..cd7d21fe3a --- /dev/null +++ b/configs/p2371-0000_defconfig @@ -0,0 +1,17 @@ +CONFIG_ARM=y +CONFIG_TEGRA=y +CONFIG_TEGRA210=y +CONFIG_TARGET_P2371_0000=y +CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2371-0000" +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +CONFIG_SPL_DM=y +CONFIG_TEGRA114_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig index 8494bb5b6e..5fd2a54eb1 100644 --- a/configs/p2571_defconfig +++ b/configs/p2571_defconfig @@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2571" # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_SPL_DM=y +CONFIG_TEGRA114_SPI=y CONFIG_SPI_FLASH=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig index 9ccd739977..a4735f6392 100644 --- a/configs/venice2_defconfig +++ b/configs/venice2_defconfig @@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra124-venice2" # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_SPL_DM=y +CONFIG_TEGRA114_SPI=y CONFIG_SPI_FLASH=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c index 0edd557ca8..4a4f5593e9 100644 --- a/drivers/usb/host/ehci-tegra.c +++ b/drivers/usb/host/ehci-tegra.c @@ -131,7 +131,9 @@ static const unsigned T20_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 }, { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 }, { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 }, - { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } + { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }, + { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, + { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 } }; static const unsigned T30_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { @@ -139,7 +141,9 @@ static const unsigned T30_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { { 0x3C0, 0x0D, 0x00, 0xC, 1, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 5 }, { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 7 }, { 0x3C0, 0x0C, 0x00, 0xC, 1, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, - { 0x3C0, 0x1A, 0x00, 0xC, 1, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } + { 0x3C0, 0x1A, 0x00, 0xC, 1, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }, + { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, + { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 } }; static const unsigned T114_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { @@ -147,16 +151,20 @@ static const unsigned T114_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { { 0x3C0, 0x0D, 0x00, 0xC, 2, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 6 }, { 0x0C8, 0x04, 0x00, 0x3, 2, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 8 }, { 0x3C0, 0x0C, 0x00, 0xC, 2, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, - { 0x3C0, 0x1A, 0x00, 0xC, 2, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 0xB } + { 0x3C0, 0x1A, 0x00, 0xC, 2, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 11 }, + { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, + { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 } }; /* NOTE: 13/26MHz settings are N/A for T210, so dupe 12MHz settings for now */ static const unsigned T210_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { /* DivN, DivM, DivP, KCP, KVCO, Delays Debounce, Bias */ - { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 30000, 5 }, + { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 32500, 5 }, { 0x019, 0x01, 0x01, 0x0, 0, 0x03, 0x4B, 0x0C, 0xBB, 48000, 8 }, { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 30000, 5 }, - { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 30000, 5 }, + { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 65000, 5 }, + { 0x019, 0x02, 0x01, 0x0, 0, 0x05, 0x96, 0x18, 0x177, 96000, 15 }, + { 0x028, 0x04, 0x01, 0x0, 0, 0x04, 0x66, 0x09, 0xFE, 120000, 20 } }; /* UTMIP Idle Wait Delay */ diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index 504332d3bc..30aecca220 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -50,8 +50,6 @@ #define MACH_TYPE_DALMORE 4304 /* not yet in mach-types.h */ /* SPI */ -#define CONFIG_TEGRA114_SPI -#define CONFIG_TEGRA114_SPI_CTRLS 6 #define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 24000000 diff --git a/include/configs/e2220-1170.h b/include/configs/e2220-1170.h new file mode 100644 index 0000000000..dff3f2a357 --- /dev/null +++ b/include/configs/e2220-1170.h @@ -0,0 +1,65 @@ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _E2220_1170_H +#define _E2220_1170_H + +#include <linux/sizes.h> + +#include "tegra210-common.h" + +/* High-level configuration options */ +#define V_PROMPT "Tegra210 (E2220-1170) # " +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA E2220-1170" + +/* Board-specific serial config */ +#define CONFIG_TEGRA_ENABLE_UARTA + +/* I2C */ +#define CONFIG_SYS_I2C_TEGRA +#define CONFIG_CMD_I2C + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) + +/* SPI */ +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 24000000 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +/* USB2.0 Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_DHCP + +#include "tegra-common-usb-gadget.h" +#include "tegra-common-post.h" + +#define COUNTER_FREQUENCY 38400000 + +#endif /* _E2220_1170_H */ diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h index 477a37ba0a..def0ab4121 100644 --- a/include/configs/jetson-tk1.h +++ b/include/configs/jetson-tk1.h @@ -40,8 +40,6 @@ #define CONFIG_SYS_MMC_ENV_PART 2 /* SPI */ -#define CONFIG_TEGRA114_SPI /* Compatible w/ Tegra114 SPI */ -#define CONFIG_TEGRA114_SPI_CTRLS 6 #define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 24000000 @@ -81,4 +79,6 @@ #define CONFIG_ARMV7_SECURE_BASE 0xfff00000 #define CONFIG_ARMV7_SECURE_RESERVE_SIZE 0x00100000 +#define CONFIG_OF_BOARD_SETUP + #endif /* __CONFIG_H */ diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h index 38b4a87bff..eac24d39ea 100644 --- a/include/configs/nyan-big.h +++ b/include/configs/nyan-big.h @@ -52,8 +52,6 @@ #define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE /* SPI */ -#define CONFIG_TEGRA114_SPI /* Compatible w/ Tegra114 SPI */ -#define CONFIG_TEGRA114_SPI_CTRLS 6 #define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 24000000 diff --git a/include/configs/p2371-0000.h b/include/configs/p2371-0000.h new file mode 100644 index 0000000000..9d7b650d98 --- /dev/null +++ b/include/configs/p2371-0000.h @@ -0,0 +1,65 @@ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _P2371_0000_H +#define _P2371_0000_H + +#include <linux/sizes.h> + +#include "tegra210-common.h" + +/* High-level configuration options */ +#define V_PROMPT "Tegra210 (P2371-0000) # " +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2371-0000" + +/* Board-specific serial config */ +#define CONFIG_TEGRA_ENABLE_UARTA + +/* I2C */ +#define CONFIG_SYS_I2C_TEGRA +#define CONFIG_CMD_I2C + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) + +/* SPI */ +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 24000000 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +/* USB2.0 Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_DHCP + +#include "tegra-common-usb-gadget.h" +#include "tegra-common-post.h" + +#define COUNTER_FREQUENCY 38400000 + +#endif /* _P2371_0000_H */ diff --git a/include/configs/p2571.h b/include/configs/p2571.h index 77faf5fdbc..356c941a77 100644 --- a/include/configs/p2571.h +++ b/include/configs/p2571.h @@ -10,9 +10,6 @@ #include <linux/sizes.h> -/* enable PMIC */ -#define CONFIG_MAX77620_POWER - #include "tegra210-common.h" /* High-level configuration options */ @@ -22,7 +19,6 @@ /* Board-specific serial config */ #define CONFIG_SERIAL_MULTI #define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE /* I2C */ #define CONFIG_SYS_I2C_TEGRA @@ -41,8 +37,6 @@ #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) /* SPI */ -#define CONFIG_TEGRA114_SPI /* Compatible w/ Tegra114 SPI */ -#define CONFIG_TEGRA114_SPI_CTRLS 6 #define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 24000000 @@ -53,7 +47,7 @@ /* USB2.0 Host support */ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_USB_STORAGE #define CONFIG_CMD_USB @@ -64,12 +58,10 @@ /* General networking support */ #define CONFIG_CMD_DHCP -/* - * TODO(twarren@nvidia.com) - add tegra-common-usb-gadget.h back - * breaks 64-bit build in ci_udc.c - */ +#include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" #define COUNTER_FREQUENCY 38400000 +#define CONFIG_OF_BOARD_SETUP #endif /* _P2571_H */ diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h index af7698d95c..39e74f023f 100644 --- a/include/configs/tegra124-common.h +++ b/include/configs/tegra124-common.h @@ -70,4 +70,7 @@ #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 +/* GPU needs setup */ +#define CONFIG_TEGRA_GPU + #endif /* _TEGRA124_COMMON_H_ */ diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h index 0348d4783b..d95056c002 100644 --- a/include/configs/tegra210-common.h +++ b/include/configs/tegra210-common.h @@ -73,4 +73,7 @@ #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 +/* GPU needs setup */ +#define CONFIG_TEGRA_GPU + #endif /* _TEGRA210_COMMON_H_ */ diff --git a/include/configs/venice2.h b/include/configs/venice2.h index ffb2e8c3d1..8b1189e7c4 100644 --- a/include/configs/venice2.h +++ b/include/configs/venice2.h @@ -37,8 +37,6 @@ #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) /* SPI */ -#define CONFIG_TEGRA114_SPI /* Compatible w/ Tegra114 SPI */ -#define CONFIG_TEGRA114_SPI_CTRLS 6 #define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 24000000 @@ -63,4 +61,6 @@ #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" +#define CONFIG_OF_BOARD_SETUP + #endif /* __CONFIG_H */ |