diff options
173 files changed, 1893 insertions, 17158 deletions
@@ -126,7 +126,7 @@ D: Palmtreo680 board, docg4 nand flash driver N: Dave Ellis E: DGE@sixnetio.com -D: EEPROM Speedup, SXNI855T port +D: EEPROM Speedup N: Daniel Engstr?m E: daniel@omicron.se @@ -12,12 +12,6 @@ config KCONFIG_OBJDIR string option env="KCONFIG_OBJDIR" -config DEFCONFIG_LIST - string - depends on !SPL_BUILD - option defconfig_list - default "configs/sandbox_defconfig" - menu "General setup" config SPL_BUILD @@ -658,7 +658,7 @@ build_target() { MAKE="${MAKE} O=${output_dir}" fi - ${MAKE} distclean >/dev/null + ${MAKE} mrproper >/dev/null echo "Building ${target} board..." ${MAKE} -s ${target}_defconfig >/dev/null @@ -109,10 +109,6 @@ ifeq ("$(origin O)", "command line") KBUILD_OUTPUT := $(O) endif -ifeq ("$(origin W)", "command line") - export KBUILD_ENABLE_EXTRA_GCC_CHECKS := $(W) -endif - # That's our default target when none is given on the command line PHONY := _all _all: @@ -441,12 +437,12 @@ ifeq ($(mixed-targets),1) # We're called with mixed targets (*config and build targets). # Handle them one by one. -PHONY += $(MAKECMDGOALS) build-one-by-one +PHONY += $(MAKECMDGOALS) __build_one_by_one -$(MAKECMDGOALS): build-one-by-one +$(filter-out __build_one_by_one, $(MAKECMDGOALS)): __build_one_by_one @: -build-one-by-one: +__build_one_by_one: $(Q)set -e; \ for i in $(MAKECMDGOALS); do \ $(MAKE) -f $(srctree)/Makefile $$i; \ @@ -462,10 +458,10 @@ KBUILD_DEFCONFIG := sandbox_defconfig export KBUILD_DEFCONFIG KBUILD_KCONFIG config: scripts_basic outputmakefile FORCE - +$(Q)$(PYTHON) $(srctree)/scripts/multiconfig.py $@ + (Q)$(MAKE) $(build)=scripts/kconfig $@ %config: scripts_basic outputmakefile FORCE - +$(Q)$(PYTHON) $(srctree)/scripts/multiconfig.py $@ + +$(Q)$(CONFIG_SHELL) $(srctree)/scripts/multiconfig.sh $@ else # =========================================================================== @@ -569,6 +565,8 @@ endif export CONFIG_SYS_TEXT_BASE +include $(srctree)/scripts/Makefile.extrawarn + # Add user supplied CPPFLAGS, AFLAGS and CFLAGS as the last assignments KBUILD_CPPFLAGS += $(KCPPFLAGS) KBUILD_AFLAGS += $(KAFLAGS) @@ -1006,13 +1004,17 @@ quiet_cmd_u-boot__ ?= LD $@ --start-group $(u-boot-main) --end-group \ $(PLATFORM_LIBS) -Map u-boot.map -u-boot: $(u-boot-init) $(u-boot-main) u-boot.lds - $(call if_changed,u-boot__) -ifeq ($(CONFIG_KALLSYMS),y) +quiet_cmd_smap = GEN common/system_map.o +cmd_smap = \ smap=`$(call SYSTEM_MAP,u-boot) | \ awk '$$2 ~ /[tTwW]/ {printf $$1 $$3 "\\\\000"}'` ; \ $(CC) $(c_flags) -DSYSTEM_MAP="\"$${smap}\"" \ -c $(srctree)/common/system_map.c -o common/system_map.o + +u-boot: $(u-boot-init) $(u-boot-main) u-boot.lds + $(call if_changed,u-boot__) +ifeq ($(CONFIG_KALLSYMS),y) + $(call cmd,smap) $(call cmd,u-boot__) common/system_map.o endif @@ -1287,6 +1289,7 @@ distclean: mrproper -o -name '.*.rej' -o -name '*%' -o -name 'core' \ -o -name '*.pyc' \) \ -type f -print | xargs rm -f + @rm -f boards.cfg backup: F=`basename $(srctree)` ; cd .. ; \ @@ -2037,6 +2037,24 @@ CBFS (Coreboot Filesystem) support 4th and following BOOTP requests: delay 0 ... 8 sec + CONFIG_BOOTP_ID_CACHE_SIZE + + BOOTP packets are uniquely identified using a 32-bit ID. The + server will copy the ID from client requests to responses and + U-Boot will use this to determine if it is the destination of + an incoming response. Some servers will check that addresses + aren't in use before handing them out (usually using an ARP + ping) and therefore take up to a few hundred milliseconds to + respond. Network congestion may also influence the time it + takes for a response to make it back to the client. If that + time is too long, U-Boot will retransmit requests. In order + to allow earlier responses to still be accepted after these + retransmissions, U-Boot's BOOTP client keeps a small cache of + IDs. The CONFIG_BOOTP_ID_CACHE_SIZE controls the size of this + cache. The default is to keep IDs for up to four outstanding + requests. Increasing this will allow U-Boot to accept offers + from a BOOTP client in networks with unusually high latency. + - DHCP Advanced Options: You can fine tune the DHCP functionality by defining CONFIG_BOOTP_* symbols: diff --git a/api/api_net.c b/api/api_net.c index 3f52d71171..7b3805e8fd 100644 --- a/api/api_net.c +++ b/api/api_net.c @@ -25,6 +25,7 @@ DECLARE_GLOBAL_DATA_PTR; #define errf(fmt, args...) do { printf("ERROR @ %s(): ", __func__); printf(fmt, ##args); } while (0) +#ifdef CONFIG_CMD_NET static int dev_valid_net(void *cookie) { @@ -85,3 +86,32 @@ int dev_read_net(void *cookie, void *buf, int len) return eth_receive(buf, len); } + +#else + +int dev_open_net(void *cookie) +{ + return API_ENODEV; +} + +int dev_close_net(void *cookie) +{ + return API_ENODEV; +} + +int dev_enum_net(struct device_info *di) +{ + return 0; +} + +int dev_write_net(void *cookie, void *buf, int len) +{ + return API_ENODEV; +} + +int dev_read_net(void *cookie, void *buf, int len) +{ + return API_ENODEV; +} + +#endif diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e385eda94c..e97f94db25 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -287,9 +287,6 @@ config TARGET_SC_SPS_1 config TARGET_NHK8815 bool "Support nhk8815" -config TARGET_OMAP5912OSK - bool "Support omap5912osk" - config TARGET_EDMINIV2 bool "Support edminiv2" @@ -977,7 +974,6 @@ source "board/ti/beagle/Kconfig" source "board/ti/dra7xx/Kconfig" source "board/ti/evm/Kconfig" source "board/ti/ks2_evm/Kconfig" -source "board/ti/omap5912osk/Kconfig" source "board/ti/omap5_uevm/Kconfig" source "board/ti/panda/Kconfig" source "board/ti/sdp3430/Kconfig" diff --git a/arch/nios2/Kconfig b/arch/nios2/Kconfig index b70364680b..0cba45bdbe 100644 --- a/arch/nios2/Kconfig +++ b/arch/nios2/Kconfig @@ -11,16 +11,8 @@ choice config TARGET_NIOS2_GENERIC bool "Support nios2-generic" -config TARGET_PCI5441 - bool "Support PCI5441" - -config TARGET_PK1C20 - bool "Support PK1C20" - endchoice source "board/altera/nios2-generic/Kconfig" -source "board/psyent/pci5441/Kconfig" -source "board/psyent/pk1c20/Kconfig" endmenu diff --git a/arch/nios2/config.mk b/arch/nios2/config.mk index 82bd887961..9b7c56dc85 100644 --- a/arch/nios2/config.mk +++ b/arch/nios2/config.mk @@ -17,3 +17,5 @@ PLATFORM_CPPFLAGS += -G0 LDFLAGS_FINAL += --gc-sections PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections + +__HAVE_ARCH_GENERIC_BOARD := y diff --git a/arch/nios2/cpu/Makefile b/arch/nios2/cpu/Makefile index bdd983d3f1..3fe7847160 100644 --- a/arch/nios2/cpu/Makefile +++ b/arch/nios2/cpu/Makefile @@ -7,5 +7,5 @@ extra-y = start.o obj-y = exceptions.o -obj-y += cpu.o interrupts.o sysid.o traps.o epcs.o +obj-y += cpu.o interrupts.o sysid.o traps.o obj-y += fdt.o diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c index e0dcbc201f..86f94b76fa 100644 --- a/arch/nios2/cpu/cpu.c +++ b/arch/nios2/cpu/cpu.c @@ -10,11 +10,14 @@ #include <nios2-io.h> #include <asm/cache.h> +DECLARE_GLOBAL_DATA_PTR; + #if defined (CONFIG_SYS_NIOS_SYSID_BASE) extern void display_sysid (void); #endif /* CONFIG_SYS_NIOS_SYSID_BASE */ -int checkcpu (void) +#ifdef CONFIG_DISPLAY_CPUINFO +int print_cpuinfo(void) { printf ("CPU : Nios-II\n"); #if !defined(CONFIG_SYS_NIOS_SYSID_BASE) @@ -24,6 +27,7 @@ int checkcpu (void) #endif return (0); } +#endif /* CONFIG_DISPLAY_CPUINFO */ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { @@ -47,3 +51,11 @@ void dcache_disable(void) { flush_dcache(CONFIG_SYS_DCACHE_SIZE, CONFIG_SYS_DCACHELINE_SIZE); } + +int arch_cpu_init(void) +{ + gd->cpu_clk = CONFIG_SYS_CLK_FREQ; + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} diff --git a/arch/nios2/cpu/epcs.c b/arch/nios2/cpu/epcs.c deleted file mode 100644 index 9758552447..0000000000 --- a/arch/nios2/cpu/epcs.c +++ /dev/null @@ -1,717 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt@psyent.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -#if defined(CONFIG_SYS_NIOS_EPCSBASE) -#include <command.h> -#include <asm/io.h> -#include <nios2-io.h> -#include <nios2-epcs.h> - - -/*-----------------------------------------------------------------------*/ -#define SHORT_HELP\ - "epcs - read/write Cyclone EPCS configuration device.\n" - -#define LONG_HELP\ - "\n"\ - "epcs erase start [end]\n"\ - " - erase sector start or sectors start through end.\n"\ - "epcs info\n"\ - " - display EPCS device information.\n"\ - "epcs protect on | off\n"\ - " - turn device protection on or off.\n"\ - "epcs read addr offset count\n"\ - " - read count bytes from offset to addr.\n"\ - "epcs write addr offset count\n"\ - " - write count bytes to offset from addr.\n"\ - "epcs verify addr offset count\n"\ - " - verify count bytes at offset from addr." - - -/*-----------------------------------------------------------------------*/ -/* Operation codes for serial configuration devices - */ -#define EPCS_WRITE_ENA 0x06 /* Write enable */ -#define EPCS_WRITE_DIS 0x04 /* Write disable */ -#define EPCS_READ_STAT 0x05 /* Read status */ -#define EPCS_READ_BYTES 0x03 /* Read bytes */ -#define EPCS_READ_ID 0xab /* Read silicon id */ -#define EPCS_WRITE_STAT 0x01 /* Write status */ -#define EPCS_WRITE_BYTES 0x02 /* Write bytes */ -#define EPCS_ERASE_BULK 0xc7 /* Erase entire device */ -#define EPCS_ERASE_SECT 0xd8 /* Erase sector */ - -/* Device status register bits - */ -#define EPCS_STATUS_WIP (1<<0) /* Write in progress */ -#define EPCS_STATUS_WEL (1<<1) /* Write enable latch */ - -/* Misc - */ -#define EPCS_TIMEOUT 100 /* 100 msec timeout */ - -static nios_spi_t *epcs = (nios_spi_t *)CONFIG_SYS_NIOS_EPCSBASE; - -/*********************************************************************** - * Device access - ***********************************************************************/ -static int epcs_cs (int assert) -{ - ulong start; - unsigned tmp; - - - if (assert) { - tmp = readl (&epcs->control); - writel (tmp | NIOS_SPI_SSO, &epcs->control); - } else { - /* Let all bits shift out */ - start = get_timer (0); - while ((readl (&epcs->status) & NIOS_SPI_TMT) == 0) - if (get_timer (start) > EPCS_TIMEOUT) - return (-1); - tmp = readl (&epcs->control); - writel (tmp & ~NIOS_SPI_SSO, &epcs->control); - } - return (0); -} - -static int epcs_tx (unsigned char c) -{ - ulong start; - - start = get_timer (0); - while ((readl (&epcs->status) & NIOS_SPI_TRDY) == 0) - if (get_timer (start) > EPCS_TIMEOUT) - return (-1); - writel (c, &epcs->txdata); - return (0); -} - -static int epcs_rx (void) -{ - ulong start; - - start = get_timer (0); - while ((readl (&epcs->status) & NIOS_SPI_RRDY) == 0) - if (get_timer (start) > EPCS_TIMEOUT) - return (-1); - return (readl (&epcs->rxdata)); -} - -static unsigned char bitrev[] = { - 0x00, 0x08, 0x04, 0x0c, 0x02, 0x0a, 0x06, 0x0e, - 0x01, 0x09, 0x05, 0x0d, 0x03, 0x0b, 0x07, 0x0f -}; - -static unsigned char epcs_bitrev (unsigned char c) -{ - unsigned char val; - - val = bitrev[c>>4]; - val |= bitrev[c & 0x0f]<<4; - return (val); -} - -static void epcs_rcv (unsigned char *dst, int len) -{ - while (len--) { - epcs_tx (0); - *dst++ = epcs_rx (); - } -} - -static void epcs_rrcv (unsigned char *dst, int len) -{ - while (len--) { - epcs_tx (0); - *dst++ = epcs_bitrev (epcs_rx ()); - } -} - -static void epcs_snd (unsigned char *src, int len) -{ - while (len--) { - epcs_tx (*src++); - epcs_rx (); - } -} - -static void epcs_rsnd (unsigned char *src, int len) -{ - while (len--) { - epcs_tx (epcs_bitrev (*src++)); - epcs_rx (); - } -} - -static void epcs_wr_enable (void) -{ - epcs_cs (1); - epcs_tx (EPCS_WRITE_ENA); - epcs_rx (); - epcs_cs (0); -} - -static unsigned char epcs_status_rd (void) -{ - unsigned char status; - - epcs_cs (1); - epcs_tx (EPCS_READ_STAT); - epcs_rx (); - epcs_tx (0); - status = epcs_rx (); - epcs_cs (0); - return (status); -} - -static void epcs_status_wr (unsigned char status) -{ - epcs_wr_enable (); - epcs_cs (1); - epcs_tx (EPCS_WRITE_STAT); - epcs_rx (); - epcs_tx (status); - epcs_rx (); - epcs_cs (0); - return; -} - -/*********************************************************************** - * Device information - ***********************************************************************/ - -static struct epcs_devinfo_t devinfo[] = { - { "EPCS1 ", 0x10, 17, 4, 15, 8, 0x0c }, - { "EPCS4 ", 0x12, 19, 8, 16, 8, 0x1c }, - { "EPCS16", 0x14, 21, 32, 16, 8, 0x1c }, - { "EPCS64", 0x16, 23,128, 16, 8, 0x1c }, - { 0, 0, 0, 0, 0, 0 } -}; - -int epcs_reset (void) -{ - /* When booting from an epcs controller, the epcs bootrom - * code may leave the slave select in an asserted state. - * This causes two problems: (1) The initial epcs access - * will fail -- not a big deal, and (2) a software reset - * will cause the bootrom code to hang since it does not - * ensure the select is negated prior to first access -- a - * big deal. Here we just negate chip select and everything - * gets better :-) - */ - epcs_cs (0); /* Negate chip select */ - return (0); -} - -epcs_devinfo_t *epcs_dev_find (void) -{ - unsigned char buf[4]; - unsigned char id; - int i; - struct epcs_devinfo_t *dev = NULL; - - /* Read silicon id requires 3 "dummy bytes" before it's put - * on the wire. - */ - buf[0] = EPCS_READ_ID; - buf[1] = 0; - buf[2] = 0; - buf[3] = 0; - - epcs_cs (1); - epcs_snd (buf,4); - epcs_rcv (buf,1); - if (epcs_cs (0) == -1) - return (NULL); - id = buf[0]; - - /* Find the info struct */ - i = 0; - while (devinfo[i].name) { - if (id == devinfo[i].id) { - dev = &devinfo[i]; - break; - } - i++; - } - - return (dev); -} - -/*********************************************************************** - * Misc Utilities - ***********************************************************************/ -int epcs_cfgsz (void) -{ - int sz = 0; - unsigned char buf[128]; - unsigned char *p; - struct epcs_devinfo_t *dev = epcs_dev_find (); - - if (!dev) - return (-1); - - /* Read in the first 128 bytes of the device */ - buf[0] = EPCS_READ_BYTES; - buf[1] = 0; - buf[2] = 0; - buf[3] = 0; - - epcs_cs (1); - epcs_snd (buf,4); - epcs_rrcv (buf, sizeof(buf)); - epcs_cs (0); - - /* Search for the starting 0x6a which is followed by the - * 4-byte 'register' and 4-byte bit-count. - */ - p = buf; - while (p < buf + sizeof(buf)-8) { - if ( *p == 0x6a ) { - /* Point to bit count and extract */ - p += 5; - sz = *p++; - sz |= *p++ << 8; - sz |= *p++ << 16; - sz |= *p++ << 24; - /* Convert to byte count */ - sz += 7; - sz >>= 3; - } else if (*p == 0xff) { - /* 0xff is ok ... just skip */ - p++; - continue; - } else { - /* Not 0xff or 0x6a ... something's not - * right ... report 'unknown' (sz=0). - */ - break; - } - } - return (sz); -} - -int epcs_erase (unsigned start, unsigned end) -{ - unsigned off, sectsz; - unsigned char buf[4]; - struct epcs_devinfo_t *dev = epcs_dev_find (); - - if (!dev || (start>end)) - return (-1); - - /* Erase the requested sectors. An address is required - * that lies within the requested sector -- we'll just - * use the first address in the sector. - */ - printf ("epcs erasing sector %d ", start); - if (start != end) - printf ("to %d ", end); - sectsz = (1 << dev->sz_sect); - while (start <= end) { - off = start * sectsz; - start++; - - buf[0] = EPCS_ERASE_SECT; - buf[1] = off >> 16; - buf[2] = off >> 8; - buf[3] = off; - - epcs_wr_enable (); - epcs_cs (1); - epcs_snd (buf,4); - epcs_cs (0); - - printf ("."); /* Some user feedback */ - - /* Wait for erase to complete */ - while (epcs_status_rd() & EPCS_STATUS_WIP) - ; - } - printf (" done.\n"); - return (0); -} - -int epcs_read (ulong addr, ulong off, ulong cnt) -{ - unsigned char buf[4]; - struct epcs_devinfo_t *dev = epcs_dev_find (); - - if (!dev) - return (-1); - - buf[0] = EPCS_READ_BYTES; - buf[1] = off >> 16; - buf[2] = off >> 8; - buf[3] = off; - - epcs_cs (1); - epcs_snd (buf,4); - epcs_rrcv ((unsigned char *)addr, cnt); - epcs_cs (0); - - return (0); -} - -int epcs_write (ulong addr, ulong off, ulong cnt) -{ - ulong wrcnt; - unsigned pgsz; - unsigned char buf[4]; - struct epcs_devinfo_t *dev = epcs_dev_find (); - - if (!dev) - return (-1); - - pgsz = (1<<dev->sz_page); - while (cnt) { - if (off % pgsz) - wrcnt = pgsz - (off % pgsz); - else - wrcnt = pgsz; - wrcnt = (wrcnt > cnt) ? cnt : wrcnt; - - buf[0] = EPCS_WRITE_BYTES; - buf[1] = off >> 16; - buf[2] = off >> 8; - buf[3] = off; - - epcs_wr_enable (); - epcs_cs (1); - epcs_snd (buf,4); - epcs_rsnd ((unsigned char *)addr, wrcnt); - epcs_cs (0); - - /* Wait for write to complete */ - while (epcs_status_rd() & EPCS_STATUS_WIP) - ; - - cnt -= wrcnt; - off += wrcnt; - addr += wrcnt; - } - - return (0); -} - -int epcs_verify (ulong addr, ulong off, ulong cnt, ulong *err) -{ - ulong rdcnt; - unsigned char buf[256]; - unsigned char *start,*end; - int i; - - start = end = (unsigned char *)addr; - while (cnt) { - rdcnt = (cnt>sizeof(buf)) ? sizeof(buf) : cnt; - epcs_read ((ulong)buf, off, rdcnt); - for (i=0; i<rdcnt; i++) { - if (*end != buf[i]) { - *err = end - start; - return(-1); - } - end++; - } - cnt -= rdcnt; - off += rdcnt; - } - return (0); -} - -static int epcs_sect_erased (int sect, unsigned *offset, - struct epcs_devinfo_t *dev) -{ - unsigned char buf[128]; - unsigned off, end; - unsigned sectsz; - int i; - - sectsz = (1 << dev->sz_sect); - off = sectsz * sect; - end = off + sectsz; - - while (off < end) { - epcs_read ((ulong)buf, off, sizeof(buf)); - for (i=0; i < sizeof(buf); i++) { - if (buf[i] != 0xff) { - *offset = off + i; - return (0); - } - } - off += sizeof(buf); - } - return (1); -} - - -/*********************************************************************** - * Commands - ***********************************************************************/ -static -void do_epcs_info (struct epcs_devinfo_t *dev, int argc, char * const argv[]) -{ - int i; - unsigned char stat; - unsigned tmp; - int erased; - - /* Basic device info */ - printf ("%s: %d kbytes (%d sectors x %d kbytes," - " %d bytes/page)\n", - dev->name, 1 << (dev->size-10), - dev->num_sects, 1 << (dev->sz_sect-10), - 1 << dev->sz_page ); - - /* Status -- for now protection is all-or-nothing */ - stat = epcs_status_rd(); - printf ("status: 0x%02x (WIP:%d, WEL:%d, PROT:%s)\n", - stat, - (stat & EPCS_STATUS_WIP) ? 1 : 0, - (stat & EPCS_STATUS_WEL) ? 1 : 0, - (stat & dev->prot_mask) ? "on" : "off" ); - - /* Configuration */ - tmp = epcs_cfgsz (); - if (tmp) { - printf ("config: 0x%06x (%d) bytes\n", tmp, tmp ); - } else { - printf ("config: unknown\n" ); - } - - /* Sector info */ - for (i=0; (i < dev->num_sects) && (argc > 1); i++) { - erased = epcs_sect_erased (i, &tmp, dev); - if ((i & 0x03) == 0) printf ("\n"); - printf ("%4d: %07x ", - i, i*(1<<dev->sz_sect) ); - if (erased) - printf ("E "); - else - printf (" "); - } - printf ("\n"); - - return; -} - -static -void do_epcs_erase (struct epcs_devinfo_t *dev, int argc, char * const argv[]) -{ - unsigned start,end; - - if ((argc < 3) || (argc > 4)) { - printf ("USAGE: epcs erase sect [end]\n"); - return; - } - if ((epcs_status_rd() & dev->prot_mask) != 0) { - printf ( "epcs: device protected.\n"); - return; - } - - start = simple_strtoul (argv[2], NULL, 10); - if (argc > 3) - end = simple_strtoul (argv[3], NULL, 10); - else - end = start; - if ((start >= dev->num_sects) || (start > end)) { - printf ("epcs: invalid sector range: [%d:%d]\n", - start, end ); - return; - } - - epcs_erase (start, end); - - return; -} - -static -void do_epcs_protect (struct epcs_devinfo_t *dev, int argc, char * const argv[]) -{ - unsigned char stat; - - /* For now protection is all-or-nothing to keep things - * simple. The protection bits don't map in a linear - * fashion ... and we would rather protect the bottom - * of the device since it contains the config data and - * leave the top unprotected for app use. But unfortunately - * protection works from top-to-bottom so it does - * really help very much from a software app point-of-view. - */ - if (argc < 3) { - printf ("USAGE: epcs protect on | off\n"); - return; - } - if (!dev) - return; - - /* Protection on/off is just a matter of setting/clearing - * all protection bits in the status register. - */ - stat = epcs_status_rd (); - if (strcmp ("on", argv[2]) == 0) { - stat |= dev->prot_mask; - } else if (strcmp ("off", argv[2]) == 0 ) { - stat &= ~dev->prot_mask; - } else { - printf ("epcs: unknown protection: %s\n", argv[2]); - return; - } - epcs_status_wr (stat); - return; -} - -static -void do_epcs_read (struct epcs_devinfo_t *dev, int argc, char * const argv[]) -{ - ulong addr,off,cnt; - ulong sz; - - if (argc < 5) { - printf ("USAGE: epcs read addr offset count\n"); - return; - } - - sz = 1 << dev->size; - addr = simple_strtoul (argv[2], NULL, 16); - off = simple_strtoul (argv[3], NULL, 16); - cnt = simple_strtoul (argv[4], NULL, 16); - if (off > sz) { - printf ("offset is greater than device size" - "... aborting.\n"); - return; - } - if ((off + cnt) > sz) { - printf ("request exceeds device size" - "... truncating.\n"); - cnt = sz - off; - } - printf ("epcs: read %08lx <- %06lx (0x%lx bytes)\n", - addr, off, cnt); - epcs_read (addr, off, cnt); - - return; -} - -static -void do_epcs_write (struct epcs_devinfo_t *dev, int argc, char * const argv[]) -{ - ulong addr,off,cnt; - ulong sz; - ulong err; - - if (argc < 5) { - printf ("USAGE: epcs write addr offset count\n"); - return; - } - if ((epcs_status_rd() & dev->prot_mask) != 0) { - printf ( "epcs: device protected.\n"); - return; - } - - sz = 1 << dev->size; - addr = simple_strtoul (argv[2], NULL, 16); - off = simple_strtoul (argv[3], NULL, 16); - cnt = simple_strtoul (argv[4], NULL, 16); - if (off > sz) { - printf ("offset is greater than device size" - "... aborting.\n"); - return; - } - if ((off + cnt) > sz) { - printf ("request exceeds device size" - "... truncating.\n"); - cnt = sz - off; - } - printf ("epcs: write %08lx -> %06lx (0x%lx bytes)\n", - addr, off, cnt); - epcs_write (addr, off, cnt); - if (epcs_verify (addr, off, cnt, &err) != 0) - printf ("epcs: write error at offset %06lx\n", err); - - return; -} - -static -void do_epcs_verify (struct epcs_devinfo_t *dev, int argc, char * const argv[]) -{ - ulong addr,off,cnt; - ulong sz; - ulong err; - - if (argc < 5) { - printf ("USAGE: epcs verify addr offset count\n"); - return; - } - - sz = 1 << dev->size; - addr = simple_strtoul (argv[2], NULL, 16); - off = simple_strtoul (argv[3], NULL, 16); - cnt = simple_strtoul (argv[4], NULL, 16); - if (off > sz) { - printf ("offset is greater than device size" - "... aborting.\n"); - return; - } - if ((off + cnt) > sz) { - printf ("request exceeds device size" - "... truncating.\n"); - cnt = sz - off; - } - printf ("epcs: verify %08lx -> %06lx (0x%lx bytes)\n", - addr, off, cnt); - if (epcs_verify (addr, off, cnt, &err) != 0) - printf ("epcs: verify error at offset %06lx\n", err); - - return; -} - -/*-----------------------------------------------------------------------*/ -int do_epcs (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int len; - struct epcs_devinfo_t *dev = epcs_dev_find (); - - if (!dev) { - printf ("epcs: device not found.\n"); - return (-1); - } - - if (argc < 2) { - do_epcs_info (dev, argc, argv); - return (0); - } - - len = strlen (argv[1]); - if (strncmp ("info", argv[1], len) == 0) { - do_epcs_info (dev, argc, argv); - } else if (strncmp ("erase", argv[1], len) == 0) { - do_epcs_erase (dev, argc, argv); - } else if (strncmp ("protect", argv[1], len) == 0) { - do_epcs_protect (dev, argc, argv); - } else if (strncmp ("read", argv[1], len) == 0) { - do_epcs_read (dev, argc, argv); - } else if (strncmp ("write", argv[1], len) == 0) { - do_epcs_write (dev, argc, argv); - } else if (strncmp ("verify", argv[1], len) == 0) { - do_epcs_verify (dev, argc, argv); - } else { - printf ("epcs: unknown operation: %s\n", argv[1]); - } - - return (0); -} - -/*-----------------------------------------------------------------------*/ - - -U_BOOT_CMD( epcs, 5, 0, do_epcs, SHORT_HELP, LONG_HELP ); - -#endif /* CONFIG_NIOS_EPCS */ diff --git a/arch/nios2/cpu/start.S b/arch/nios2/cpu/start.S index 7ce0d34d7f..6af9b4e943 100644 --- a/arch/nios2/cpu/start.S +++ b/arch/nios2/cpu/start.S @@ -134,11 +134,12 @@ _reloc: mov fp, sp /* - * Call board_init -- never returns + * Call board_init_f -- never returns */ - movhi r4, %hi(board_init@h) - ori r4, r4, %lo(board_init@h) - callr r4 + mov r4, r0 + movhi r2, %hi(board_init_f@h) + ori r2, r2, %lo(board_init_f@h) + callr r2 /* NEVER RETURNS -- but branch to the _start just * in case ;-) @@ -146,6 +147,31 @@ _reloc: br _start + +/* + * relocate_code -- Nios2 handles the relocation above. But + * the generic board code monkeys with the heap, stack, etc. + * (it makes some assumptions that may not be appropriate + * for Nios). Nevertheless, we capitulate here. + * + * We'll call the board_init_r from here since this isn't + * supposed to return. + * + * void relocate_code (ulong sp, gd_t *global_data, + * ulong reloc_addr) + * __attribute__ ((noreturn)); + */ + .text + .global relocate_code + +relocate_code: + mov sp, r4 /* Set the new sp */ + mov r4, r5 + movhi r8, %hi(board_init_r@h) + ori r8, r8, %lo(board_init_r@h) + callr r8 + ret + /* * dly_clks -- Nios2 (like Nios1) doesn't have a timebase in * the core. For simple delay loops, we do our best by counting diff --git a/arch/nios2/include/asm/config.h b/arch/nios2/include/asm/config.h index cd29734789..476a32bdc6 100644 --- a/arch/nios2/include/asm/config.h +++ b/arch/nios2/include/asm/config.h @@ -7,4 +7,7 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SYS_GENERIC_GLOBAL_DATA + #endif diff --git a/arch/nios2/include/asm/posix_types.h b/arch/nios2/include/asm/posix_types.h index 673364099a..6b6c39bcc0 100644 --- a/arch/nios2/include/asm/posix_types.h +++ b/arch/nios2/include/asm/posix_types.h @@ -16,7 +16,11 @@ typedef int __kernel_pid_t; typedef unsigned short __kernel_ipc_pid_t; typedef unsigned short __kernel_uid_t; typedef unsigned short __kernel_gid_t; +#ifdef __GNUC__ +typedef __SIZE_TYPE__ __kernel_size_t; +#else typedef unsigned long __kernel_size_t; +#endif typedef long __kernel_ssize_t; typedef int __kernel_ptrdiff_t; typedef long __kernel_time_t; diff --git a/arch/nios2/include/asm/u-boot.h b/arch/nios2/include/asm/u-boot.h index 51f6c30ef7..cb02e98a82 100644 --- a/arch/nios2/include/asm/u-boot.h +++ b/arch/nios2/include/asm/u-boot.h @@ -15,15 +15,7 @@ #ifndef __ASM_NIOS2_U_BOOT_H_ #define __ASM_NIOS2_U_BOOT_H_ -typedef struct bd_info { - unsigned long bi_memstart; /* start of DRAM memory */ - phys_size_t bi_memsize; /* size of DRAM memory in bytes */ - unsigned long bi_flashstart; /* start of FLASH memory */ - unsigned long bi_flashsize; /* size of FLASH memory */ - unsigned long bi_flashoffset; /* reserved area for startup monitor */ - unsigned long bi_sramstart; /* start of SRAM memory */ - unsigned long bi_sramsize; /* size of SRAM memory */ -} bd_t; +#include <asm-generic/u-boot.h> /* For image.h:image_check_target_arch() */ #define IH_ARCH_DEFAULT IH_ARCH_NIOS2 diff --git a/arch/nios2/lib/Makefile b/arch/nios2/lib/Makefile index 7cb25c0ee1..079378a905 100644 --- a/arch/nios2/lib/Makefile +++ b/arch/nios2/lib/Makefile @@ -6,7 +6,6 @@ # obj-y += cache.o -obj-y += board.o obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-y += libgcc.o obj-y += time.o diff --git a/arch/nios2/lib/board.c b/arch/nios2/lib/board.c deleted file mode 100644 index f24218ff1c..0000000000 --- a/arch/nios2/lib/board.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - * (C) Copyright 2003, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt@psyent.com> - * - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <stdio_dev.h> -#include <watchdog.h> -#include <malloc.h> -#include <mmc.h> -#include <net.h> -#ifdef CONFIG_STATUS_LED -#include <status_led.h> -#endif -#if defined(CONFIG_SYS_NIOS_EPCSBASE) -#include <nios2-epcs.h> -#endif -#ifdef CONFIG_CMD_NAND -#include <nand.h> /* cannot even include nand.h if it isnt configured */ -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* - * All attempts to come up with a "common" initialization sequence - * that works for all boards and architectures failed: some of the - * requirements are just _too_ different. To get rid of the resulting - * mess of board dependend #ifdef'ed code we now make the whole - * initialization sequence configurable to the user. - * - * The requirements for any new initalization function is simple: it - * receives a pointer to the "global data" structure as it's only - * argument, and returns an integer return code, where 0 means - * "continue" and != 0 means "fatal error, hang the system". - */ - - -typedef int (init_fnc_t) (void); - - -/************************************************************************ - * Initialization sequence * - ***********************************************************************/ - -init_fnc_t *init_sequence[] = { -#if defined(CONFIG_BOARD_EARLY_INIT_F) - board_early_init_f, /* Call board-specific init code early.*/ -#endif -#if defined(CONFIG_SYS_NIOS_EPCSBASE) - epcs_reset, -#endif - - env_init, - serial_init, - console_init_f, - display_options, - checkcpu, - checkboard, - NULL, /* Terminate this list */ -}; - - -/***********************************************************************/ -void board_init(void) -{ - bd_t *bd; - init_fnc_t **init_fnc_ptr; - static gd_t gd_data; - static bd_t bd_data; - - /* Pointer is writable since we allocated a register for it. */ - gd = &gd_data; - /* compiler optimization barrier needed for GCC >= 3.4 */ - __asm__ __volatile__("" : : : "memory"); - - gd->bd = &bd_data; - gd->baudrate = CONFIG_BAUDRATE; - gd->cpu_clk = CONFIG_SYS_CLK_FREQ; - - bd = gd->bd; - bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; -#ifndef CONFIG_SYS_NO_FLASH - bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; -#endif -#if defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE) - bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; - bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; -#endif - - for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { - WATCHDOG_RESET(); - if ((*init_fnc_ptr) () != 0) - hang(); - } - - WATCHDOG_RESET(); - - /* The Malloc area is immediately below the monitor copy in RAM */ - mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN); - -#ifndef CONFIG_SYS_NO_FLASH - WATCHDOG_RESET(); - bd->bi_flashsize = flash_init(); -#endif - -#ifdef CONFIG_CMD_NAND - puts("NAND: "); - nand_init(); -#endif - -#ifdef CONFIG_GENERIC_MMC - puts("MMC: "); - mmc_initialize(bd); -#endif - - WATCHDOG_RESET(); - env_relocate(); - - WATCHDOG_RESET(); - stdio_init(); - jumptable_init(); - console_init_r(); - - WATCHDOG_RESET(); - interrupt_init(); - -#if defined(CONFIG_BOARD_LATE_INIT) - board_late_init(); -#endif - -#if defined(CONFIG_CMD_NET) - puts("Net: "); - eth_initialize(bd); -#endif - - /* main_loop */ - for (;;) { - WATCHDOG_RESET(); - main_loop(); - } -} diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index b237505d3e..5bfab70b7e 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -254,12 +254,36 @@ static void enable_tdm_law(void) void enable_cpc(void) { int i; + int ret; u32 size = 0; - + u32 cpccfg0; + char buffer[HWCONFIG_BUFFER_SIZE]; + char cpc_subarg[16]; + bool have_hwconfig = false; + int cpc_args = 0; cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; + /* Extract hwconfig from environment */ + ret = getenv_f("hwconfig", buffer, sizeof(buffer)); + if (ret > 0) { + /* + * If "en_cpc" is not defined in hwconfig then by default all + * cpcs are enable. If this config is defined then individual + * cpcs which have to be enabled should also be defined. + * e.g en_cpc:cpc1,cpc2; + */ + if (hwconfig_f("en_cpc", buffer)) + have_hwconfig = true; + } + for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { - u32 cpccfg0 = in_be32(&cpc->cpccfg0); + if (have_hwconfig) { + sprintf(cpc_subarg, "cpc%u", i + 1); + cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer); + if (cpc_args == 0) + continue; + } + cpccfg0 = in_be32(&cpc->cpccfg0); size += CPC_CFG0_SZ_K(cpccfg0); #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 3665ec6b6c..3222e26a5a 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -134,6 +134,21 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) printf("Failed to reserve memory for spin table: %s\n", fdt_strerror(off)); } +#ifdef CONFIG_DEEP_SLEEP +#ifdef CONFIG_SPL_MMC_BOOT + off = fdt_add_mem_rsv(blob, CONFIG_SYS_MMC_U_BOOT_START, + CONFIG_SYS_MMC_U_BOOT_SIZE); + if (off < 0) + printf("Failed to reserve memory for SD deep sleep: %s\n", + fdt_strerror(off)); +#elif defined(CONFIG_SPL_SPI_BOOT) + off = fdt_add_mem_rsv(blob, CONFIG_SYS_SPI_FLASH_U_BOOT_START, + CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE); + if (off < 0) + printf("Failed to reserve memory for SPI deep sleep: %s\n", + fdt_strerror(off)); +#endif +#endif } #endif diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig index 35608a68b0..2c39244fa7 100644 --- a/arch/powerpc/cpu/mpc8xx/Kconfig +++ b/arch/powerpc/cpu/mpc8xx/Kconfig @@ -14,12 +14,6 @@ config TARGET_COGENT_MPC8XX config TARGET_ESTEEM192E bool "Support ESTEEM192E" -config TARGET_FLAGADM - bool "Support FLAGADM" - -config TARGET_GEN860T - bool "Support GEN860T" - config TARGET_HERMES bool "Support hermes" @@ -47,15 +41,9 @@ config TARGET_R360MPI config TARGET_RRVISION bool "Support RRvision" -config TARGET_SXNI855T - bool "Support SXNI855T" - config TARGET_SPD823TS bool "Support SPD823TS" -config TARGET_SVM_SC8XX - bool "Support svm_sc8xx" - config TARGET_MHPC bool "Support MHPC" @@ -74,9 +62,6 @@ config TARGET_ELPT860 config TARGET_UC100 bool "Support uc100" -config TARGET_STXXTC - bool "Support stxxtc" - config TARGET_FPS850L bool "Support FPS850L" @@ -139,8 +124,6 @@ source "board/cogent/Kconfig" source "board/eltec/mhpc/Kconfig" source "board/emk/top860/Kconfig" source "board/esteem192e/Kconfig" -source "board/flagadm/Kconfig" -source "board/gen860t/Kconfig" source "board/hermes/Kconfig" source "board/icu862/Kconfig" source "board/ip860/Kconfig" @@ -151,10 +134,7 @@ source "board/lwmon/Kconfig" source "board/manroland/uc100/Kconfig" source "board/netvia/Kconfig" source "board/r360mpi/Kconfig" -source "board/sixnet/Kconfig" source "board/spd8xx/Kconfig" -source "board/stx/stxxtc/Kconfig" -source "board/svm_sc8xx/Kconfig" source "board/tqc/tqm8xx/Kconfig" endmenu diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c index e51fec7260..90c7e61d83 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c @@ -44,11 +44,7 @@ void cpu_init_f (volatile immap_t * immr) #endif /* CONFIG_WATCHDOG */ /* SIUMCR - contains debug pin configuration (11-6) */ -#ifndef CONFIG_SVM_SC8xx immr->im_siu_conf.sc_siumcr |= CONFIG_SYS_SIUMCR; -#else - immr->im_siu_conf.sc_siumcr = CONFIG_SYS_SIUMCR; -#endif /* initialize timebase status and control register (11-26) */ /* unlock TBSCRK */ diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index 02962054f6..6eaab88243 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -366,6 +366,8 @@ void board_init_f(ulong bootflag) memset((void *) gd, 0, sizeof(gd_t)); #endif + gd->flags = bootflag; + for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) if ((*init_fnc_ptr) () != 0) hang(); diff --git a/board/davinci/dm355evm/MAINTAINERS b/board/davinci/dm355evm/MAINTAINERS index b823785896..ef586b3884 100644 --- a/board/davinci/dm355evm/MAINTAINERS +++ b/board/davinci/dm355evm/MAINTAINERS @@ -1,6 +1,6 @@ DM355EVM BOARD M: Sandeep Paulraj <s-paulraj@ti.com> -S: Maintained +S: Orphan (since 2014-08) F: board/davinci/dm355evm/ F: include/configs/davinci_dm355evm.h F: configs/davinci_dm355evm_defconfig diff --git a/board/davinci/dm355leopard/MAINTAINERS b/board/davinci/dm355leopard/MAINTAINERS index f17fea2dd2..2fc1e00d5a 100644 --- a/board/davinci/dm355leopard/MAINTAINERS +++ b/board/davinci/dm355leopard/MAINTAINERS @@ -1,6 +1,6 @@ DM355LEOPARD BOARD M: Sandeep Paulraj <s-paulraj@ti.com> -S: Maintained +S: Orphan (since 2014-08) F: board/davinci/dm355leopard/ F: include/configs/davinci_dm355leopard.h F: configs/davinci_dm355leopard_defconfig diff --git a/board/davinci/dm365evm/MAINTAINERS b/board/davinci/dm365evm/MAINTAINERS index 5adb4e0c1d..0bfe02d0ea 100644 --- a/board/davinci/dm365evm/MAINTAINERS +++ b/board/davinci/dm365evm/MAINTAINERS @@ -1,6 +1,6 @@ DM365EVM BOARD M: Sandeep Paulraj <s-paulraj@ti.com> -S: Maintained +S: Orphan (since 2014-08) F: board/davinci/dm365evm/ F: include/configs/davinci_dm365evm.h F: configs/davinci_dm365evm_defconfig diff --git a/board/davinci/dm6467evm/MAINTAINERS b/board/davinci/dm6467evm/MAINTAINERS index 4030bf325f..bb4053626d 100644 --- a/board/davinci/dm6467evm/MAINTAINERS +++ b/board/davinci/dm6467evm/MAINTAINERS @@ -1,6 +1,6 @@ DM6467EVM BOARD M: Sandeep Paulraj <s-paulraj@ti.com> -S: Maintained +S: Orphan (since 2014-08) F: board/davinci/dm6467evm/ F: include/configs/davinci_dm6467evm.h F: configs/davinci_dm6467evm_defconfig diff --git a/board/flagadm/Kconfig b/board/flagadm/Kconfig deleted file mode 100644 index bc0657e5d0..0000000000 --- a/board/flagadm/Kconfig +++ /dev/null @@ -1,11 +0,0 @@ -if TARGET_FLAGADM - -config SYS_BOARD - string - default "flagadm" - -config SYS_CONFIG_NAME - string - default "FLAGADM" - -endif diff --git a/board/flagadm/MAINTAINERS b/board/flagadm/MAINTAINERS deleted file mode 100644 index 606989c04d..0000000000 --- a/board/flagadm/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -FLAGADM BOARD -M: Kári DavÃðsson <kd@flaga.is> -S: Orphan (since 2014-06) -F: board/flagadm/ -F: include/configs/FLAGADM.h -F: configs/FLAGADM_defconfig diff --git a/board/flagadm/Makefile b/board/flagadm/Makefile deleted file mode 100644 index f2377c8392..0000000000 --- a/board/flagadm/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = flagadm.o flash.o diff --git a/board/flagadm/flagadm.c b/board/flagadm/flagadm.c deleted file mode 100644 index 343cb77409..0000000000 --- a/board/flagadm/flagadm.c +++ /dev/null @@ -1,134 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> - -#define _NOT_USED_ 0xFFFFFFFF - -/*Orginal table, GPL4 disabled*/ -const uint sdram_table[] = -{ - /* single read (offset 0x00 in upm ram) */ - 0x1f07cc04, 0xeeaeec04, 0x11adcc04, 0xefbbac00, - 0x1ff74c47, - /* Precharge */ - 0x1FF74C05, - _NOT_USED_, - _NOT_USED_, - /* burst read (offset 0x08 in upm ram) */ - 0x1f07cc04, 0xeeaeec04, 0x00adcc04, 0x00afcc00, - 0x00afcc00, 0x01afcc00, 0x0fbb8c00, 0x1ff74c47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* single write (offset 0x18 in upm ram) */ - 0x1f27cc04, 0xeeaeac00, 0x01b90c04, 0x1ff74c47, - /* Load moderegister */ - 0x1FF74C34, /*Precharge*/ - 0xEFEA8C34, /*NOP*/ - 0x1FB54C35, /*Load moderegister*/ - _NOT_USED_, - - /* burst write (offset 0x20 in upm ram) */ - 0x1f07cc04, 0xeeaeac00, 0x00ad4c00, 0x00afcc00, - 0x00afcc00, 0x01bb8c04, 0x1ff74c47, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* refresh (offset 0x30 in upm ram) */ - 0x1ff5cc84, 0xffffec04, 0xffffec04, 0xffffec04, - 0xffffec84, 0xffffec07, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* exception (offset 0x3C in upm ram) */ - 0x7fffec07, _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* GPL5 driven every cycle */ -/* the display and the DSP */ -const uint dsp_disp_table[] = -{ - /* single read (offset 0x00 in upm ram) */ - 0xffffc80c, 0xffffc004, 0x0fffc004, 0x0fffd004, - 0x0fffc000, 0x0fffc004, 0x3fffc004, 0xffffcc05, - /* burst read (offset 0x08 in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* single write (offset 0x18 in upm ram) */ - 0xffffcc0c, 0xffffc004, 0x0fffc004, 0x0fffd004, - 0x0fffc000, 0x0fffc004, 0x7fffc004, 0xfffffc05, - /* burst write (offset 0x20 in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* refresh (offset 0x30 in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* exception (offset 0x3C in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -int checkboard (void) -{ - puts ("Board: FlagaDM V3.0\n"); - return 0; -} - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size_b0; - - memctl->memc_or2 = CONFIG_SYS_OR2; - memctl->memc_br2 = CONFIG_SYS_BR2; - - udelay(100); - upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - - memctl->memc_mptpr = MPTPR_PTP_DIV16; - memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_1X; - - /*Do the initialization of the SDRAM*/ - /*Start with the precharge cycle*/ - memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \ - MCR_MLCF(1) | MCR_MAD(0x5)); - - /*Then we need two refresh cycles*/ - memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_2X; - memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \ - MCR_MLCF(2) | MCR_MAD(0x30)); - - /*Mode register programming*/ - memctl->memc_mar = 0x00000088; /*CAS Latency = 2 and burst length = 4*/ - memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \ - MCR_MLCF(1) | MCR_MAD(0x1C)); - - /* That should do it, just enable the periodic refresh in burst of 4*/ - memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_4X; - memctl->memc_mamr |= (MAMR_PTAE | MAMR_GPL_A4DIS); - - size_b0 = 16*1024*1024; - - /* - * No bank 1 or 3 - * invalidate bank - */ - memctl->memc_br1 = 0; - memctl->memc_br3 = 0; - - upmconfig(UPMB, (uint *)dsp_disp_table, sizeof(dsp_disp_table)/sizeof(uint)); - - memctl->memc_mbmr = MBMR_GPL_B4DIS; - - memctl->memc_or4 = CONFIG_SYS_OR4; - memctl->memc_br4 = CONFIG_SYS_BR4; - - return (size_b0); -} diff --git a/board/flagadm/flash.c b/board/flagadm/flash.c deleted file mode 100644 index 46a2c9a266..0000000000 --- a/board/flagadm/flash.c +++ /dev/null @@ -1,687 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> -#include <flash.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -ulong flash_recognize (vu_long *base); -int write_word (flash_info_t *info, ulong dest, ulong data); -void flash_get_geometry (vu_long *base, flash_info_t *info); -void flash_unprotect(flash_info_t *info); -int _flash_real_protect(flash_info_t *info, long idx, int on); - - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - int i; - int rec; - - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - *((vu_short*)CONFIG_SYS_FLASH_BASE) = 0xffff; - - flash_get_geometry ((vu_long*)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-flash_info[0].size & 0xFFFF8000); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | - (memctl->memc_br0 & ~(BR_BA_MSK)); - - rec = flash_recognize((vu_long*)CONFIG_SYS_FLASH_BASE); - - if (rec == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - flash_info[0].size, flash_info[0].size<<20); - } - -#if CONFIG_SYS_FLASH_PROTECTION - /*Unprotect all the flash memory*/ - flash_unprotect(&flash_info[0]); -#endif - - *((vu_short*)CONFIG_SYS_FLASH_BASE) = 0xffff; - - return (flash_info[0].size); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_OFFSET, - CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE-1, - &flash_info[0]); -#endif - return (flash_info[0].size); -} - - -int flash_get_protect_status(flash_info_t * info, long idx) -{ - vu_short * base; - ushort res; - -#ifdef DEBUG - printf("\n Attempting to set protection info with %d sectors\n", info->sector_count); -#endif - - - base = (vu_short*)info->start[idx]; - - *(base) = 0xffff; - - *(base + 0x55) = 0x0098; - res = base[0x2]; - - *(base) = 0xffff; - - if(res != 0) - res = 1; - else - res = 0; - - return res; -} - -void flash_get_geometry (vu_long *base, flash_info_t *info) -{ - int i,j; - ulong ner = 0; - vu_short * sb = (vu_short*)base; - ulong offset = (ulong)base; - - /* Read Device geometry */ - - *sb = 0xffff; - - *sb = 0x0090; - - info->flash_id = ((ulong)base[0x0]); -#ifdef DEBUG - printf("Id is %x\n", (uint)(ulong)info->flash_id); -#endif - - *sb = 0xffff; - - *(sb+0x55) = 0x0098; - - info->size = 1 << (sb[0x27]); /* Read flash size */ - -#ifdef DEBUG - printf("Size is %x\n", (uint)(ulong)info->size); -#endif - - *sb = 0xffff; - - *(sb + 0x55) = 0x0098; - ner = sb[0x2c] ; /*Number of erase regions*/ - -#ifdef DEBUG - printf("Number of erase regions %x\n", (uint)ner); -#endif - - info->sector_count = 0; - - for(i = 0; i < ner; i++) - { - uint s; - uint count; - uint t1,t2,t3,t4; - - *sb = 0xffff; - - *(sb + 0x55) = 0x0098; - - t1 = sb[0x2d + i*4]; - t2 = sb[0x2e + i*4]; - t3 = sb[0x2f + i*4]; - t4 = sb[0x30 + i*4]; - - count = ((t1 & 0x00ff) | (((t2 & 0x00ff) << 8) & 0xff00) )+ 1; /*sector count*/ - s = ((t3 & 0x00ff) | (((t4 & 0x00ff) << 8) & 0xff00)) * 256;; /*Sector size*/ - -#ifdef DEBUG - printf("count and size %x, %x\n", count, s); - printf("sector count for erase region %d is %d\n", i, count); -#endif - for(j = 0; j < count; j++) - { -#ifdef DEBUG - printf("%x, ", (uint)offset); -#endif - info->start[ info->sector_count + j] = offset; - offset += s; - } - info->sector_count += count; - } - - if ((offset - (ulong)base) != info->size) - printf("WARNING reported size %x does not match to calculted size %x.\n" - , (uint)info->size, (uint)(offset - (ulong)base) ); - - /* Next check if there are any sectors protected.*/ - - for(i = 0; i < info->sector_count; i++) - info->protect[i] = flash_get_protect_status(info, i); - - *sb = 0xffff; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return ; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case INTEL_MANUFACT & FLASH_VENDMASK: - printf ("Intel "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case INTEL_ID_28F320C3B & FLASH_TYPEMASK: - printf ("28F320RC3(4 MB)\n"); - break; - case INTEL_ID_28F320J3A: - printf("28F320J3A (4 MB)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 4) == 0) - printf ("\n "); - printf (" %02d %08lX%s", - i, info->start[i], - info->protect[i]!=0 ? " (RO)" : " " - ); - } - printf ("\n"); - return ; -} - -ulong flash_recognize (vu_long *base) -{ - ulong id; - ulong res = FLASH_UNKNOWN; - vu_short * sb = (vu_short*)base; - - *sb = 0xffff; - - *sb = 0x0090; - id = base[0]; - - switch (id & 0x00FF0000) - { - case (MT_MANUFACT & 0x00FF0000): /* MT or => Intel */ - case (INTEL_ALT_MANU & 0x00FF0000): - res = FLASH_MAN_INTEL; - break; - default: - res = FLASH_UNKNOWN; - } - - *sb = 0xffff; - - return res; -} - -/*-----------------------------------------------------------------------*/ -#define INTEL_FLASH_STATUS_BLS 0x02 -#define INTEL_FLASH_STATUS_PSS 0x04 -#define INTEL_FLASH_STATUS_VPPS 0x08 -#define INTEL_FLASH_STATUS_PS 0x10 -#define INTEL_FLASH_STATUS_ES 0x20 -#define INTEL_FLASH_STATUS_ESS 0x40 -#define INTEL_FLASH_STATUS_WSMS 0x80 - -int flash_decode_status_bits(char status) -{ - int err = 0; - - if(!(status & INTEL_FLASH_STATUS_WSMS)) { - printf("Busy\n"); - err = -1; - } - - if(status & INTEL_FLASH_STATUS_ESS) { - printf("Erase suspended\n"); - err = -1; - } - - if(status & INTEL_FLASH_STATUS_ES) { - printf("Error in block erase\n"); - err = -1; - } - - if(status & INTEL_FLASH_STATUS_PS) { - printf("Error in programming\n"); - err = -1; - } - - if(status & INTEL_FLASH_STATUS_VPPS) { - printf("Vpp low, operation aborted\n"); - err = -1; - } - - if(status & INTEL_FLASH_STATUS_PSS) { - printf("Program is suspended\n"); - err = -1; - } - - if(status & INTEL_FLASH_STATUS_BLS) { - printf("Attempting to program/erase a locked sector\n"); - err = -1; - } - - if((status & INTEL_FLASH_STATUS_PS) && - (status & INTEL_FLASH_STATUS_ES) && - (status & INTEL_FLASH_STATUS_ESS)) { - printf("A command sequence error\n"); - return -1; - } - - return err; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_short *addr; - int flag, prot, sect; - ulong start, now; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - char tmp; - - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_short *)(info->start[sect]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Single Block Erase Command */ - *addr = 0x0020; - /* Confirm */ - *addr = 0x00D0; - /* Resume Command, as per errata update */ - *addr = 0x00D0; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - *addr = 0x70; /*Read status register command*/ - tmp = (short)*addr & 0x00FF; /* Read the status */ - while (!(tmp & INTEL_FLASH_STATUS_WSMS)) { - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - *addr = 0x0050; /* Reset the status register */ - *addr = 0xffff; - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - start) > 1000) { /* every second */ - putc ('.'); - } - udelay(100000); /* 100 ms */ - *addr = 0x0070; /*Read status register command*/ - tmp = (short)*addr & 0x00FF; /* Read status */ - start = get_timer(0); - } - if( tmp & INTEL_FLASH_STATUS_ES ) - flash_decode_status_bits(tmp); - - *addr = 0x0050; /* Reset the status register */ - *addr = 0xffff; /* Reset to read mode */ - } - } - - - printf (" done\n"); - return rcode; -} - -void flash_unprotect (flash_info_t *info) -{ - /*We can only unprotect the whole flash at once*/ - /*Therefore we must prevent the _flash_real_protect()*/ - /*from re-protecting sectors, that ware protected before */ - /*we called flash_real_protect();*/ - - int i; - - for(i = 0; i < info->sector_count; i++) - info->protect[i] = 0; - -#ifdef CONFIG_SYS_FLASH_PROTECTION - _flash_real_protect(info, 0, 0); -#endif -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_word (flash_info_t *info, ulong dest, ulong da) -{ - vu_short *addr = (vu_short *)dest; - ulong start; - char csr; - int flag; - int i; - union { - u32 data32; - u16 data16[2]; - } data; - - data.data32 = da; - - /* Check if Flash is (sufficiently) erased */ - if (((*addr & data.data16[0]) != data.data16[0]) || - ((*(addr+1) & data.data16[1]) != data.data16[1])) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - for(i = 0; i < 2; i++) - { - /* Write Command */ - *addr = 0x0010; - - /* Write Data */ - *addr = data.data16[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - flag = 0; - *addr = 0x0070; /*Read statusregister command */ - while (((csr = *addr) & INTEL_FLASH_STATUS_WSMS)!=INTEL_FLASH_STATUS_WSMS) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - flag = 1; - break; - } - *addr = 0x0070; /*Read statusregister command */ - } - if (csr & INTEL_FLASH_STATUS_PSS) { - printf ("CSR indicates write error (%0x) at %08lx\n", - csr, (ulong)addr); - flag = 1; - } - - /* Clear Status Registers Command */ - *addr = 0x0050; - /* Reset to read array mode */ - *addr = 0xffff; - addr++; - } - - return (flag); -} - -int flash_real_protect(flash_info_t *info, long offset, int prot) -{ - int i, idx; - - for(idx = 0; idx < info->sector_count; idx++) - if(info->start[idx] == offset) - break; - - if(idx==info->sector_count) - return -1; - - if(prot == 0) { - /* Unprotect one sector, which means unprotect all flash - * and reprotect the other protected sectors. - */ - _flash_real_protect(info, 0, 0); /* Unprotects the whole flash*/ - info->protect[idx] = 0; - - for(i = 0; i < info->sector_count; i++) - if(info->protect[i]) - _flash_real_protect(info, i, 1); - } - else { - /* We can protect individual sectors */ - _flash_real_protect(info, idx, 1); - } - - for( i = 0; i < info->sector_count; i++) - info->protect[i] = flash_get_protect_status(info, i); - - return 0; -} - -int _flash_real_protect(flash_info_t *info, long idx, int prot) -{ - vu_short *addr; - int flag; - ushort cmd; - ushort tmp; - ulong now, start; - - if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) { - printf ("Can't change protection for unknown flash type %08lx - aborted\n", - info->flash_id); - return -1; - } - - if(prot == 0) { - /*Unlock the sector*/ - cmd = 0x00D0; - } - else { - /*Lock the sector*/ - cmd = 0x0001; - } - - addr = (vu_short *)(info->start[idx]); - - /* If chip is busy, wait for it */ - start = get_timer(0); - *addr = 0x0070; /*Read status register command*/ - tmp = ((ushort)(*addr))&0x00ff; /*Read the status*/ - while(!(tmp & INTEL_FLASH_STATUS_WSMS)) { - /*Write State Machine Busy*/ - /*Wait untill done or timeout.*/ - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = 0x0050; /* Reset the status register */ - *addr = 0xffff; /* Reset the chip */ - printf ("TTimeout\n"); - return 1; - } - *addr = 0x0070; - tmp = ((ushort)(*addr))&0x00ff; /*Read the status*/ - start = get_timer(0); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Unlock block*/ - *addr = 0x0060; - - *addr = cmd; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - *addr = 0x0070; /*Read status register command*/ - tmp = ((ushort)(*addr)) & 0x00FF; /* Read the status */ - while (!(tmp & INTEL_FLASH_STATUS_WSMS)) { - /* Write State Machine Busy */ - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = 0x0050; /* Reset the status register */ - *addr = 0xffff; - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - start) > 1000) { /* every second */ - putc ('.'); - } - udelay(100000); /* 100 ms */ - *addr = 0x70; /*Read status register command*/ - tmp = (short)*addr & 0x00FF; /* Read status */ - start = get_timer(0); - } - if( tmp & INTEL_FLASH_STATUS_PS ) - flash_decode_status_bits(tmp); - - *addr =0x0050; /*Clear status register*/ - - /* reset to read mode */ - *addr = 0xffff; - - return 0; -} diff --git a/board/flagadm/u-boot.lds b/board/flagadm/u-boot.lds deleted file mode 100644 index 7ae91ffb2e..0000000000 --- a/board/flagadm/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2001-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/flagadm/u-boot.lds.debug b/board/flagadm/u-boot.lds.debug deleted file mode 100644 index b0091db0c6..0000000000 --- a/board/flagadm/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 22b57ccaa8..50d77317df 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -34,6 +34,8 @@ ifndef CONFIG_RAMBOOT_PBL obj-$(CONFIG_FSL_FIXED_MMC_LOCATION) += sdhc_boot.o endif +obj-$(CONFIG_FSL_DIU_CH7301) += diu_ch7301.o + obj-$(CONFIG_MPC8541CDS) += cds_pci_ft.o obj-$(CONFIG_MPC8548CDS) += cds_pci_ft.o obj-$(CONFIG_MPC8555CDS) += cds_pci_ft.o diff --git a/board/freescale/common/diu_ch7301.c b/board/freescale/common/diu_ch7301.c new file mode 100644 index 0000000000..82ce870b13 --- /dev/null +++ b/board/freescale/common/diu_ch7301.c @@ -0,0 +1,136 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Authors: Priyanka Jain <Priyanka.Jain@freescale.com> + * Wang Dongsheng <dongsheng.wang@freescale.com> + * + * This file is copied and modified from the original t1040qds/diu.c. + * Encoder can be used in T104x and LSx Platform. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <stdio_dev.h> +#include <i2c.h> + +#define I2C_DVI_INPUT_DATA_FORMAT_REG 0x1F +#define I2C_DVI_PLL_CHARGE_CNTL_REG 0x33 +#define I2C_DVI_PLL_DIVIDER_REG 0x34 +#define I2C_DVI_PLL_SUPPLY_CNTL_REG 0x35 +#define I2C_DVI_PLL_FILTER_REG 0x36 +#define I2C_DVI_TEST_PATTERN_REG 0x48 +#define I2C_DVI_POWER_MGMT_REG 0x49 +#define I2C_DVI_LOCK_STATE_REG 0x4D +#define I2C_DVI_SYNC_POLARITY_REG 0x56 + +/* + * Set VSYNC/HSYNC to active high. This is polarity of sync signals + * from DIU->DVI. The DIU default is active igh, so DVI is set to + * active high. + */ +#define I2C_DVI_INPUT_DATA_FORMAT_VAL 0x98 + +#define I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL 0x06 +#define I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL 0x26 +#define I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL 0xA0 +#define I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL 0x08 +#define I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL 0x16 +#define I2C_DVI_PLL_FILTER_LOW_SPEED_VAL 0x60 + +/* Clear test pattern */ +#define I2C_DVI_TEST_PATTERN_VAL 0x18 +/* Exit Power-down mode */ +#define I2C_DVI_POWER_MGMT_VAL 0xC0 + +/* Monitor polarity is handled via DVI Sync Polarity Register */ +#define I2C_DVI_SYNC_POLARITY_VAL 0x00 + +/* Programming of HDMI Chrontel CH7301 connector */ +int diu_set_dvi_encoder(unsigned int pixclock) +{ + int ret; + u8 temp; + + temp = I2C_DVI_TEST_PATTERN_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1, + &temp, 1); + if (ret) { + puts("I2C: failed to select proper dvi test pattern\n"); + return ret; + } + temp = I2C_DVI_INPUT_DATA_FORMAT_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG, + 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi input data format\n"); + return ret; + } + + /* Set Sync polarity register */ + temp = I2C_DVI_SYNC_POLARITY_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1, + &temp, 1); + if (ret) { + puts("I2C: failed to select dvi syc polarity\n"); + return ret; + } + + /* Set PLL registers based on pixel clock rate*/ + if (pixclock > 65000000) { + temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll charge_cntl\n"); + return ret; + } + temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll divider\n"); + return ret; + } + temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_FILTER_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll filter\n"); + return ret; + } + } else { + temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll charge_cntl\n"); + return ret; + } + temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll divider\n"); + return ret; + } + temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_FILTER_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll filter\n"); + return ret; + } + } + + temp = I2C_DVI_POWER_MGMT_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_POWER_MGMT_REG, 1, + &temp, 1); + if (ret) { + puts("I2C: failed to select dvi power mgmt\n"); + return ret; + } + + udelay(500); + + return 0; +} diff --git a/board/freescale/common/diu_ch7301.h b/board/freescale/common/diu_ch7301.h new file mode 100644 index 0000000000..8b6ead0874 --- /dev/null +++ b/board/freescale/common/diu_ch7301.h @@ -0,0 +1,13 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DIU_HDMI_CH7301__ +#define __DIU_HDMI_CH7301__ + +/* Programming of HDMI Chrontel CH7301 connector */ +int diu_set_dvi_encoder(unsigned int pixclock); + +#endif diff --git a/board/freescale/t1040qds/diu.c b/board/freescale/t1040qds/diu.c index ffd074b0f8..0214224707 100644 --- a/board/freescale/t1040qds/diu.c +++ b/board/freescale/t1040qds/diu.c @@ -13,42 +13,9 @@ #include <video_fb.h> #include <fsl_diu_fb.h> #include "../common/qixis.h" +#include "../common/diu_ch7301.h" #include "t1040qds.h" #include "t1040qds_qixis.h" -#include <i2c.h> - - -#define I2C_DVI_INPUT_DATA_FORMAT_REG 0x1F -#define I2C_DVI_PLL_CHARGE_CNTL_REG 0x33 -#define I2C_DVI_PLL_DIVIDER_REG 0x34 -#define I2C_DVI_PLL_SUPPLY_CNTL_REG 0x35 -#define I2C_DVI_PLL_FILTER_REG 0x36 -#define I2C_DVI_TEST_PATTERN_REG 0x48 -#define I2C_DVI_POWER_MGMT_REG 0x49 -#define I2C_DVI_LOCK_STATE_REG 0x4D -#define I2C_DVI_SYNC_POLARITY_REG 0x56 - -/* - * Set VSYNC/HSYNC to active high. This is polarity of sync signals - * from DIU->DVI. The DIU default is active igh, so DVI is set to - * active high. - */ -#define I2C_DVI_INPUT_DATA_FORMAT_VAL 0x98 - -#define I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL 0x06 -#define I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL 0x26 -#define I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL 0xA0 -#define I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL 0x08 -#define I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL 0x16 -#define I2C_DVI_PLL_FILTER_LOW_SPEED_VAL 0x60 - -/* Clear test pattern */ -#define I2C_DVI_TEST_PATTERN_VAL 0x18 -/* Exit Power-down mode */ -#define I2C_DVI_POWER_MGMT_VAL 0xC0 - -/* Monitor polarity is handled via DVI Sync Polarity Register */ -#define I2C_DVI_SYNC_POLARITY_VAL 0x00 /* * DIU Area Descriptor @@ -69,98 +36,6 @@ #define AD_COMP_1_SHIFT 4 #define AD_COMP_0_SHIFT 0 -/* Programming of HDMI Chrontel CH7301 connector */ -int diu_set_dvi_encoder(unsigned int pixclock) -{ - int ret; - u8 temp; - select_i2c_ch_pca9547(I2C_MUX_CH_DIU); - - temp = I2C_DVI_TEST_PATTERN_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1, - &temp, 1); - if (ret) { - puts("I2C: failed to select proper dvi test pattern\n"); - return ret; - } - temp = I2C_DVI_INPUT_DATA_FORMAT_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG, - 1, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi input data format\n"); - return ret; - } - - /* Set Sync polarity register */ - temp = I2C_DVI_SYNC_POLARITY_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1, - &temp, 1); - if (ret) { - puts("I2C: failed to select dvi syc polarity\n"); - return ret; - } - - /* Set PLL registers based on pixel clock rate*/ - if (pixclock > 65000000) { - temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, - I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi pll charge_cntl\n"); - return ret; - } - temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, - I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi pll divider\n"); - return ret; - } - temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, - I2C_DVI_PLL_FILTER_REG, 1, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi pll filter\n"); - return ret; - } - } else { - temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, - I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi pll charge_cntl\n"); - return ret; - } - temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, - I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi pll divider\n"); - return ret; - } - temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, - I2C_DVI_PLL_FILTER_REG, 1, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi pll filter\n"); - return ret; - } - } - - temp = I2C_DVI_POWER_MGMT_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_POWER_MGMT_REG, 1, - &temp, 1); - if (ret) { - puts("I2C: failed to select dvi power mgmt\n"); - return ret; - } - - udelay(500); - - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); - return 0; -} - void diu_set_pixel_clock(unsigned int pixclock) { unsigned long speed_ccb, temp; @@ -172,12 +47,19 @@ void diu_set_pixel_clock(unsigned int pixclock) pixval = speed_ccb / temp; /* Program HDMI encoder */ + /* Switch channel to DIU */ + select_i2c_ch_pca9547(I2C_MUX_CH_DIU); + + /* Set dispaly encoder */ ret = diu_set_dvi_encoder(temp); if (ret) { puts("Failed to set DVI encoder\n"); return; } + /* Switch channel to default */ + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + /* Program pixel clock */ out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, ((pixval << PXCK_BITS_START) & PXCK_MASK)); diff --git a/board/freescale/t104xrdb/Makefile b/board/freescale/t104xrdb/Makefile index 6cd304cce9..b9ef17f903 100644 --- a/board/freescale/t104xrdb/Makefile +++ b/board/freescale/t104xrdb/Makefile @@ -11,6 +11,7 @@ obj-y += t104xrdb.o obj-y += cpld.o obj-y += eth.o obj-$(CONFIG_PCI) += pci.o +obj-$(CONFIG_FSL_DIU_FB)+= diu.o endif obj-y += ddr.o obj-y += law.o diff --git a/board/freescale/t104xrdb/diu.c b/board/freescale/t104xrdb/diu.c new file mode 100644 index 0000000000..3285bef546 --- /dev/null +++ b/board/freescale/t104xrdb/diu.c @@ -0,0 +1,84 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Author: Priyanka Jain <Priyanka.Jain@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/io.h> +#include <common.h> +#include <command.h> +#include <fsl_diu_fb.h> +#include <linux/ctype.h> +#include <video_fb.h> + +#include "../common/diu_ch7301.h" + +#include "cpld.h" +#include "t104xrdb.h" + +/* + * DIU Area Descriptor + * + * Note that we need to byte-swap the value before it's written to the AD + * register. So even though the registers don't look like they're in the same + * bit positions as they are on the MPC8610, the same value is written to the + * AD register on the MPC8610 and on the P1022. + */ +#define AD_BYTE_F 0x10000000 +#define AD_ALPHA_C_SHIFT 25 +#define AD_BLUE_C_SHIFT 23 +#define AD_GREEN_C_SHIFT 21 +#define AD_RED_C_SHIFT 19 +#define AD_PIXEL_S_SHIFT 16 +#define AD_COMP_3_SHIFT 12 +#define AD_COMP_2_SHIFT 8 +#define AD_COMP_1_SHIFT 4 +#define AD_COMP_0_SHIFT 0 + +void diu_set_pixel_clock(unsigned int pixclock) +{ + unsigned long speed_ccb, temp; + u32 pixval; + int ret; + + speed_ccb = get_bus_freq(0); + temp = 1000000000 / pixclock; + temp *= 1000; + pixval = speed_ccb / temp; + + /* Program HDMI encoder */ + ret = diu_set_dvi_encoder(temp); + if (ret) { + puts("Failed to set DVI encoder\n"); + return; + } + + /* Program pixel clock */ + out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, + ((pixval << PXCK_BITS_START) & PXCK_MASK)); + + /* enable clock*/ + out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK | + ((pixval << PXCK_BITS_START) & PXCK_MASK)); +} + +int platform_diu_init(unsigned int xres, unsigned int yres, const char *port) +{ + u32 pixel_format; + u8 sw; + + /*Configure Display ouput port as HDMI*/ + sw = CPLD_READ(sfp_ctl_status); + CPLD_WRITE(sfp_ctl_status , sw & ~(CPLD_DIU_SEL_DFP)); + + pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) | + (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) | + (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) | + (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) | + (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT)); + + printf("DIU: Switching to monitor DVI @ %ux%u\n", xres, yres); + + return fsl_diu_init(xres, yres, pixel_format, 0); +} diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c index c628c95f2d..3822a37738 100644 --- a/board/freescale/t104xrdb/spl.c +++ b/board/freescale/t104xrdb/spl.c @@ -11,6 +11,7 @@ #include <mmc.h> #include <fsl_esdhc.h> #include <spi_flash.h> +#include <asm/mpc85xx_gpio.h> DECLARE_GLOBAL_DATA_PTR; @@ -55,6 +56,11 @@ void board_init_f(ulong bootflag) /* Update GD pointer */ gd = (gd_t *)(CONFIG_SPL_GD_ADDR); +#ifdef CONFIG_DEEP_SLEEP + /* disable the console if boot from deep sleep */ + if (in_be32(&gur->scrtsr[0]) & (1 << 3)) + gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; +#endif /* compiler optimization barrier needed for GCC >= 3.4 */ __asm__ __volatile__("" : : : "memory"); @@ -120,3 +126,16 @@ void board_init_r(gd_t *gd, ulong dest_addr) nand_boot(); #endif } + +#ifdef CONFIG_DEEP_SLEEP +void board_mem_sleep_setup(void) +{ + void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE; + + /* does not provide HW signals for power management */ + clrbits_8(cpld_base + 0x17, 0x40); + /* Disable MCKE isolation */ + gpio_set_value(2, 0); + udelay(1); +} +#endif diff --git a/doc/README.t4240qds b/board/freescale/t4qds/README index ef8c75f3b2..3962fee7f2 100644 --- a/doc/README.t4240qds +++ b/board/freescale/t4qds/README @@ -79,6 +79,25 @@ Board Features - High-speed serial flash Two Serial port Four I2C ports + XFI + XFI is supported on T4QDS-XFI board which removed slot3 and routed + four Lanes A/B/C/D to a SFP+ cages, which to house fiber cable or + direct attach cable(copper), the copper cable is used to emulate + 10GBASE-KR scenario. + So, for XFI usage, there are two scenarios, one will use fiber cable, + another will use copper cable. An hwconfig env "fsl_10gkr_copper" is + introduced to indicate a XFI port will use copper cable, and U-boot + will fixup the dtb accordingly. + It's used as: fsl_10gkr_copper:<10g_mac_name> + The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm2_10g1, fm2_10g2, they + do not have to be coexist in hwconfig. If a MAC is listed in the env + "fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable + will be used by default. + for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm2_10g1,fm2_10g2" in + hwconfig, then both four XFI ports will use copper cable. + set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two + XFI ports will use copper cable, the other two XFI ports will use fiber + cable. Memory map ---------- diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c index 6210e4618f..9b416b138a 100644 --- a/board/freescale/t4qds/eth.c +++ b/board/freescale/t4qds/eth.c @@ -23,6 +23,7 @@ #include <phy.h> #include <asm/fsl_dtsec.h> #include <asm/fsl_serdes.h> +#include <hwconfig.h> #include "../common/qixis.h" #include "../common/fman.h" @@ -173,6 +174,10 @@ void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, enum fm_port port, int offset) { int interface = fm_info_get_enet_if(port); + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + + prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; if (interface == PHY_INTERFACE_MODE_SGMII || interface == PHY_INTERFACE_MODE_QSGMII) { @@ -262,6 +267,76 @@ void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, default: break; } + } else if (interface == PHY_INTERFACE_MODE_XGMII && + ((prtcl2 == 55) || (prtcl2 == 57))) { + /* + * if the 10G is XFI, check hwconfig to see what is the + * media type, there are two types, fiber or copper, + * fix the dtb accordingly. + */ + int media_type = 0; + struct fixed_link f_link; + char lane_mode[20] = {"10GBASE-KR"}; + char buf[32] = "serdes-2,"; + int off; + + switch (port) { + case FM1_10GEC1: + if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) { + media_type = 1; + fdt_set_phy_handle(blob, prop, pa, + "phy_xfi1"); + sprintf(buf, "%s%s%s", buf, "lane-a,", + (char *)lane_mode); + } + break; + case FM1_10GEC2: + if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) { + media_type = 1; + fdt_set_phy_handle(blob, prop, pa, + "phy_xfi2"); + sprintf(buf, "%s%s%s", buf, "lane-b,", + (char *)lane_mode); + } + break; + case FM2_10GEC1: + if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g1")) { + media_type = 1; + fdt_set_phy_handle(blob, prop, pa, + "phy_xfi3"); + sprintf(buf, "%s%s%s", buf, "lane-d,", + (char *)lane_mode); + } + break; + case FM2_10GEC2: + if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g2")) { + media_type = 1; + fdt_set_phy_handle(blob, prop, pa, + "phy_xfi4"); + sprintf(buf, "%s%s%s", buf, "lane-c,", + (char *)lane_mode); + } + break; + default: + return; + } + + if (!media_type) { + /* fixed-link is used for XFI fiber cable */ + fdt_delprop(blob, offset, "phy-handle"); + f_link.phy_id = port; + f_link.duplex = 1; + f_link.link_speed = 10000; + f_link.pause = 0; + f_link.asym_pause = 0; + fdt_setprop(blob, offset, "fixed-link", &f_link, + sizeof(f_link)); + } else { + /* set property for copper cable */ + off = fdt_node_offset_by_compat_reg(blob, + "fsl,fman-memac-mdio", pa + 0x1000); + fdt_setprop_string(blob, off, "lane-instance", buf); + } } } @@ -295,8 +370,23 @@ void fdt_fixup_board_enet(void *fdt) break; case PHY_INTERFACE_MODE_XGMII: /* check if it's XFI interface for 10g */ - if ((prtcl2 == 56) || (prtcl2 == 57)) { - fdt_status_okay_by_alias(fdt, "emi2_xfislot3"); + if ((prtcl2 == 55) || (prtcl2 == 57)) { + if (i == FM1_10GEC1 && hwconfig_sub( + "fsl_10gkr_copper", "fm1_10g1")) + fdt_status_okay_by_alias( + fdt, "xfi_pcs_mdio1"); + if (i == FM1_10GEC2 && hwconfig_sub( + "fsl_10gkr_copper", "fm1_10g2")) + fdt_status_okay_by_alias( + fdt, "xfi_pcs_mdio2"); + if (i == FM2_10GEC1 && hwconfig_sub( + "fsl_10gkr_copper", "fm2_10g1")) + fdt_status_okay_by_alias( + fdt, "xfi_pcs_mdio3"); + if (i == FM2_10GEC2 && hwconfig_sub( + "fsl_10gkr_copper", "fm2_10g2")) + fdt_status_okay_by_alias( + fdt, "xfi_pcs_mdio4"); break; } switch (i) { @@ -460,7 +550,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]); fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]); fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]); - if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) { + if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) { fm_info_set_phy_address(FM1_DTSEC9, slot_qsgmii_phyaddr[1][3]); fm_info_set_phy_address(FM1_DTSEC10, @@ -475,7 +565,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]); fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]); fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]); - if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) { + if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) { fm_info_set_phy_address(FM1_DTSEC9, slot_qsgmii_phyaddr[1][2]); fm_info_set_phy_address(FM1_DTSEC10, @@ -490,7 +580,7 @@ int board_eth_init(bd_t *bis) case 48: fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]); fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]); - if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) { + if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) { fm_info_set_phy_address(FM1_DTSEC10, slot_qsgmii_phyaddr[1][2]); fm_info_set_phy_address(FM1_DTSEC9, @@ -567,13 +657,18 @@ int board_eth_init(bd_t *bis) idx = i - FM1_10GEC1; switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: - lane = serdes_get_first_lane(FSL_SRDS_1, + if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) { + /* A fake PHY address to make U-boot happy */ + fm_info_set_phy_address(i, i); + } else { + lane = serdes_get_first_lane(FSL_SRDS_1, XAUI_FM1_MAC9 + idx); - if (lane < 0) - break; - slot = lane_to_slot_fsm1[lane]; - if (QIXIS_READ(present2) & (1 << (slot - 1))) - fm_disable_port(i); + if (lane < 0) + break; + slot = lane_to_slot_fsm1[lane]; + if (QIXIS_READ(present2) & (1 << (slot - 1))) + fm_disable_port(i); + } mdio_mux[i] = EMI2; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); break; @@ -666,7 +761,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); break; - case 56: + case 55: case 57: /* XFI in Slot3, SGMII in Slot4 */ fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); @@ -743,13 +838,18 @@ int board_eth_init(bd_t *bis) idx = i - FM2_10GEC1; switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: - lane = serdes_get_first_lane(FSL_SRDS_2, + if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) { + /* A fake PHY address to make U-boot happy */ + fm_info_set_phy_address(i, i); + } else { + lane = serdes_get_first_lane(FSL_SRDS_2, XAUI_FM2_MAC9 + idx); - if (lane < 0) - break; - slot = lane_to_slot_fsm2[lane]; - if (QIXIS_READ(present2) & (1 << (slot - 1))) - fm_disable_port(i); + if (lane < 0) + break; + slot = lane_to_slot_fsm2[lane]; + if (QIXIS_READ(present2) & (1 << (slot - 1))) + fm_disable_port(i); + } mdio_mux[i] = EMI2; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); break; diff --git a/board/gen860t/Kconfig b/board/gen860t/Kconfig deleted file mode 100644 index 438f7cc950..0000000000 --- a/board/gen860t/Kconfig +++ /dev/null @@ -1,11 +0,0 @@ -if TARGET_GEN860T - -config SYS_BOARD - string - default "gen860t" - -config SYS_CONFIG_NAME - string - default "GEN860T" - -endif diff --git a/board/gen860t/MAINTAINERS b/board/gen860t/MAINTAINERS deleted file mode 100644 index c5d3da3653..0000000000 --- a/board/gen860t/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -GEN860T BOARD -M: Keith Outwater <Keith_Outwater@mvis.com> -S: Orphan (since 2014-06) -F: board/gen860t/ -F: include/configs/GEN860T.h -F: configs/GEN860T_defconfig -F: configs/GEN860T_SC_defconfig diff --git a/board/gen860t/Makefile b/board/gen860t/Makefile deleted file mode 100644 index 86ae5e80e1..0000000000 --- a/board/gen860t/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = gen860t.o flash.o beeper.o fpga.o ioport.o diff --git a/board/gen860t/README b/board/gen860t/README deleted file mode 100644 index 3ef8ae196e..0000000000 --- a/board/gen860t/README +++ /dev/null @@ -1,131 +0,0 @@ -This directory contains board specific code for a generic MPC860T based -embedded computer, called 'GEN860T'. The design is generic in the sense that -common, readily available components are used and that the architecture of the -system is relatively straightforward: - - One eight bit wide boot (FLASH) memory - 32 bit main memory using SDRAM - DOC 2000+ - Ethernet PHY - Some I2C peripheral devices: Atmel AT24C256 EEPROM, Maxim DS1337 RTC. - Some other miscellaneous peripherals - -NOTE: There are references to a XIlinx FPGA and Mil-Std 1553 databus in this -port. I guess the computer is not as generic as I first said 8) However, -these extras can be safely ignored. - -Given the GEN860T files, it should be pretty easy to reverse engineer the -hardware configuration, if that's useful to you. Hopefully, this code will -be useful to someone as a basis for a port to a new system or as a head start -on a custom design. If you end up using any of this, I would appreciate -hearing from you, especially if you discover bugs or find ways to improve the -quality of this U-Boot port. - -Here are the salient features of the system: -Clock : 33.3 Mhz oscillator -Processor core frequency : 66.6 Mhz if in 1:2:1 mode; can also run 1:1 -Bus frequency : 33.3 Mhz - -Main memory: - Type : SDRAM - Width : 32 bits - Size : 64 mibibytes - Chip : Two Micron MT48LC16M16A2TG-7E - CS : MPC860T CS1*/UPMA - UPMA CONNECTIONS: - SDRAM A10 : GPLA0* - SDRAM CAS* : GPLA2* - SDRAM WE* : GPLA3* - SDRAM RAS* : GPLA4* - -Boot memory: - Type : FLASH - Width : 8 bits - Size : 16 mibibytes - Chip : One Intel 28F128J3A (StrataFlash) - CS : MPC860T CS0*/GPCM (this is the "boot" chip select) - -EEPROM memory: - Type : Serial I2C EEPROM - Width : 8 bits - Size : 32 kibibytes - Chip : One Atmel AT25C256 - CS : 0x50 (external I2C address pins on device are tied to GND) - -Filesystem memory: - Type : NAND FLASH (Toshiba) - Width : 8 bits (i.e. interface to DOC is 8 bits) - Size : 32 mibibytes - Chip : One DiskOnCHip Millenium Plus (DOC 2000+) - CS : MPC860T CS2*/GPCM - -Network support: - MAC : MPC86OT FEC (Fast Ethernet Controller) - PHY : Intel LXT971A - MII Addr: 0x0 (hardwired on the board) - MII IRQ : - -Console: - RS-232 on SMC1 (Maxim MAX3232 LVCMOS-RS232 level shifter) - -Real Time Clock: - Type : Low power, I2C interface - Chip : Maxim DS1337 - CS : Address 0x68 on I2C bus - - The MPC860T's internal RTC has a defect in Mask rev D that increases - the current drain on the KAPWR line to 10 mA. Since this is an - unreasonable amount of current draw for a RTC, and Motorola does not - plan to fix this in future mask revisions, a serial (I2C) RTC that - works has been included instead. NOTE that the DS1337 can be - configured to output a 32768 Hz clock while the main power is on. - This clock output has been routed to the MPC860T's EXTAL pin to allow - the internal RTC to be used. NOTE also that due to yet another - defect in the rev D mask, the RTC does not operate reliably when the - internal RTC divisor is set to use a 32768 Hz reference. So just use - the I2C RTC. - -Miscellaneous: - Xilinx Virtex FPGA on CS3*/GPCM. - Virtex FPGA slave SelectMap interface on cs4*/UPMB. - Mil-Std 1553 databus interface on CS5*/GPCM. - Audio sounder (beeper) with digital volume control connected to SPKROUT. - -SC variant: - A reduced-feature version of the GEN860T port is also supported: GEN860T_SC. - The 'SC' variant only provides support for the Virtex FPGA, SDRAM main - memory, EEPROM and flash memory. The system clock frequency is reduced - to 24 MHz. - -Issues: - The DOC 2000+ returns 0x40 as its device ID when probed using the method - desxribed in the DOC datasheet. Unfortunately, the U-Boot DOC driver - does not recognize this device. As of this writing, it seems that MTD - does not support the DOC 2000+ either. - -Status: - Everything appears to work except DOC support. As of this writing, - David Woodhouse has stated on the MTD mailing list that he has no - knowledge of the DOC Millineum Plus and therfore there is no support - in MTD for this device. I wish I had known this sooner :( - -The GEN860T board specific files and configuration is based on the work -of others who have contributed to U-Boot. The copyright and license notices -of these authors have been retained wherever their code has been reused. -All new code to support the GEN860T board is: - - (C) Copyright 2001-2003 - Keith Outwater (keith_outwater@mvis.com) - -and the following license applies: - -SPDX-License-Identifier: GPL-2.0+ - -Thanks to Wolfgang Denk for a great software package and to everyone -who contributed to its development. - -Keith Outwater -Sr. Staff Engineer -Microvision, Inc. -<keith_outwater@mvis.com> -<outwater@eskimo.com> diff --git a/board/gen860t/beeper.c b/board/gen860t/beeper.c deleted file mode 100644 index 0bebca98b1..0000000000 --- a/board/gen860t/beeper.c +++ /dev/null @@ -1,183 +0,0 @@ -/* - * (C) Copyright 2002 - * Keith Outwater, keith_outwater@mvis.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> -#include <asm/8xx_immap.h> -#include <linux/ctype.h> - -/* - * Basic beeper support for the GEN860T board. The GEN860T includes - * an audio sounder driven by a Phillips TDA8551 amplifier. The - * TDA8551 features a digital volume control which uses a "trinary" - * input (high/high-Z/low) to set volume. The 860's SPKROUT pin - * drives the amplifier input. - */ - -/* - * Initialize beeper-related hardware. Initialize timer 1 for use with - * the beeper. Use 66 MHz internal clock with prescale of 33 to get - * 1 uS period per count. - * FIXME: we should really compute the prescale based on the reported - * core clock frequency. - */ -void init_beeper (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - immap->im_cpmtimer.cpmt_tgcr &= ~TGCR_RST1 | TGCR_STP1; - immap->im_cpmtimer.cpmt_tmr1 = ((33 << TMR_PS_SHIFT) & TMR_PS_MSK) - | TMR_OM | TMR_FRR | TMR_ICLK_IN_GEN; - immap->im_cpmtimer.cpmt_tcn1 = 0; - immap->im_cpmtimer.cpmt_ter1 = 0xffff; - immap->im_cpmtimer.cpmt_tgcr |= TGCR_RST1; -} - -/* - * Set beeper frequency. Max allowed frequency is 2.5 KHz. This limit - * is mostly arbitrary, but the beeper isn't really much good beyond this - * frequency. - */ -void set_beeper_frequency (uint frequency) -{ -#define FREQ_LIMIT 2500 - - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - /* - * Compute timer ticks given desired frequency. The timer is set up - * to count 0.5 uS per tick and it takes two ticks per cycle (Hz). - */ - if (frequency > FREQ_LIMIT) - frequency = FREQ_LIMIT; - frequency = 1000000 / frequency; - immap->im_cpmtimer.cpmt_trr1 = (ushort) frequency; -} - -/* - * Turn the beeper on - */ -void beeper_on (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - immap->im_cpmtimer.cpmt_tgcr &= ~TGCR_STP1; -} - -/* - * Turn the beeper off - */ -void beeper_off (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - immap->im_cpmtimer.cpmt_tgcr |= TGCR_STP1; -} - -/* - * Increase or decrease the beeper volume. Volume can be set - * from off to full in 64 steps. To increase volume, the output - * pin is actively driven high, then returned to tristate. - * To decrease volume, output a low on the port pin (no need to - * change pin mode to tristate) then output a high to go back to - * tristate. - */ -void set_beeper_volume (int steps) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - int i; - - if (steps >= 0) { - for (i = 0; i < (steps >= 64 ? 64 : steps); i++) { - immap->im_cpm.cp_pbodr &= ~(0x80000000 >> 19); - udelay (1); - immap->im_cpm.cp_pbodr |= (0x80000000 >> 19); - udelay (1); - } - } else { - for (i = 0; i > (steps <= -64 ? -64 : steps); i--) { - immap->im_cpm.cp_pbdat &= ~(0x80000000 >> 19); - udelay (1); - immap->im_cpm.cp_pbdat |= (0x80000000 >> 19); - udelay (1); - } - } -} - -/* - * Check the environment to see if the beeper needs beeping. - * Controlled by a sequence of the form: - * freq/delta volume/on time/off time;... where: - * freq = frequency in Hz (0 - 2500) - * delta volume = volume steps up or down (-64 <= vol <= 64) - * on time = time in mS - * off time = time in mS - * - * Return 1 on success, 0 on failure - */ -int do_beeper (char *sequence) -{ -#define DELIMITER ';' - - int args[4]; - int i; - int val; - char *p = sequence; - char *tp; - - /* - * Parse the control sequence. This is a really simple parser - * without any real error checking. You can probably blow it - * up really easily. - */ - if (*p == '\0' || !isdigit (*p)) { - printf ("%s:%d: null or invalid string (%s)\n", - __FILE__, __LINE__, p); - return 0; - } - - i = 0; - while (*p != '\0') { - while (*p != DELIMITER) { - if (i > 3) - i = 0; - val = (int) simple_strtol (p, &tp, 0); - if (tp == p) { - printf ("%s:%d: no digits or bad format\n", - __FILE__, __LINE__); - return 0; - } else { - args[i] = val; - } - - i++; - if (*tp == DELIMITER) - p = tp; - else - p = ++tp; - } - p++; - - /* - * Well, we got something that has a chance of being correct - */ -#if 0 - for (i = 0; i < 4; i++) { - printf ("%s:%d:arg %d = %d\n", __FILE__, __LINE__, i, - args[i]); - } - printf ("\n"); -#endif - set_beeper_frequency (args[0]); - set_beeper_volume (args[1]); - beeper_on (); - udelay (1000 * args[2]); - beeper_off (); - udelay (1000 * args[3]); - } - return 1; -} diff --git a/board/gen860t/beeper.h b/board/gen860t/beeper.h deleted file mode 100644 index 0734fcab0f..0000000000 --- a/board/gen860t/beeper.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * (C) Copyright 2002 - * Keith Outwater, keith_outwater@mvis.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -void init_beeper(void); -void set_beeper_frequency(uint frequency); -void beeper_on(void); -void beeper_off(void); -void set_beeper_volume(int steps); -int do_beeper(char *sequence); diff --git a/board/gen860t/flash.c b/board/gen860t/flash.c deleted file mode 100644 index ca1ed3d62d..0000000000 --- a/board/gen860t/flash.c +++ /dev/null @@ -1,628 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Keith Outwater, keith_outwater@mvsi.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -/* - * Use buffered writes to flash by default - they are about 32x faster than - * single byte writes. - */ -#ifndef CONFIG_SYS_GEN860T_FLASH_USE_WRITE_BUFFER -#define CONFIG_SYS_GEN860T_FLASH_USE_WRITE_BUFFER -#endif - -/* - * Max time to wait (in mS) for flash device to allocate a write buffer. - */ -#ifndef CONFIG_SYS_FLASH_ALLOC_BUFFER_TOUT -#define CONFIG_SYS_FLASH_ALLOC_BUFFER_TOUT 100 -#endif - -/* - * These functions support a single Intel StrataFlash device (28F128J3A) - * in byte mode only!. The flash routines are very basic and simple - * since there isn't really any remapping necessary. - */ - -/* - * Intel SCS (Scalable Command Set) command definitions - * (taken from 28F128J3A datasheet) - */ -#define SCS_READ_CMD 0xff -#define SCS_READ_ID_CMD 0x90 -#define SCS_QUERY_CMD 0x98 -#define SCS_READ_STATUS_CMD 0x70 -#define SCS_CLEAR_STATUS_CMD 0x50 -#define SCS_WRITE_BUF_CMD 0xe8 -#define SCS_PROGRAM_CMD 0x40 -#define SCS_BLOCK_ERASE_CMD 0x20 -#define SCS_BLOCK_ERASE_RESUME_CMD 0xd0 -#define SCS_PROGRAM_RESUME_CMD 0xd0 -#define SCS_BLOCK_ERASE_SUSPEND_CMD 0xb0 -#define SCS_SET_BLOCK_LOCK_CMD 0x60 -#define SCS_CLR_BLOCK_LOCK_CMD 0x60 - -/* - * SCS status/extended status register bit definitions - */ -#define SCS_SR7 0x80 -#define SCS_XSR7 0x80 - -/*---------------------------------------------------------------------*/ -#if 0 -#define DEBUG_FLASH -#endif - -#ifdef DEBUG_FLASH -#define PRINTF(fmt,args...) printf(fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif -/*---------------------------------------------------------------------*/ - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_char *addr, flash_info_t *info); -static int write_data8 (flash_info_t *info, ulong dest, uchar data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - * Initialize the flash memory. - */ -unsigned long -flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0; - int i; - - for (i= 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* - * The gen860t board only has one FLASH memory device, so the - * FLASH Bank configuration is done statically. - */ - PRINTF("\n## Get flash bank 1 size @ 0x%08x\n", FLASH_BASE0_PRELIM); - size_b0 = flash_get_size((vu_char *)FLASH_BASE0_PRELIM, &flash_info[0]); - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0: " - "ID 0x%lx, Size = 0x%08lx = %ld MB\n", - flash_info[0].flash_id,size_b0, size_b0 << 20); - } - - PRINTF("## Before remap:\n" - " BR0: 0x%08x OR0: 0x%08x\n BR1: 0x%08x OR1: 0x%08x\n", - memctl->memc_br0, memctl->memc_or0, - memctl->memc_br1, memctl->memc_or1); - - /* - * Remap FLASH according to real size - */ - memctl->memc_or0 |= (-size_b0 & 0xFFFF8000); - memctl->memc_br0 |= (CONFIG_SYS_FLASH_BASE & BR_BA_MSK); - - PRINTF("## After remap:\n" - " BR0: 0x%08x OR0: 0x%08x\n", memctl->memc_br0, memctl->memc_or0); - - /* - * Re-do sizing to get full correct info - */ - size_b0 = flash_get_size ((vu_char *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_info[0].size = size_b0; - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* - * Monitor protection is ON by default - */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* - * Environment protection ON by default - */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - PRINTF("## Final Flash bank size: 0x%08lx\n",size_b0); - return (size_b0); -} - - -/*----------------------------------------------------------------------- - * Fill in the FLASH offset table - */ -static void -flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += 1024 * 128; - } - return; - - default: - printf ("Don't know sector offsets for FLASH" - " type 0x%lx\n", info->flash_id); - return; - } -} - - -/*----------------------------------------------------------------------- - * Display FLASH device info - */ -void -flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("Intel "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - printf ("28F128J3A (128Mbit = 128K x 128)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - if (info->size >= (1024 * 1024)) { - i = 20; - } else { - i = 10; - } - printf (" Size: %ld %cB in %d Sectors\n", - info->size >> i, - (i == 20) ? 'M' : 'k', - info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - - -/*----------------------------------------------------------------------- - * Get size and other information for a FLASH device. - * NOTE: The following code cannot be run from FLASH! - */ -static -ulong flash_get_size (vu_char *addr, flash_info_t *info) -{ -#define NO_FLASH 0 - - vu_char value[2]; - - /* - * Try to read the manufacturer ID - */ - addr[0] = SCS_READ_CMD; - addr[0] = SCS_READ_ID_CMD; - value[0] = addr[0]; - value[1] = addr[2]; - addr[0] = SCS_READ_CMD; - - PRINTF("Manuf. ID @ 0x%08lx: 0x%02x\n", (ulong)addr, value[0]); - switch (value[0]) { - case (INTEL_MANUFACT & 0xff): - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (NO_FLASH); - } - - /* - * Read the device ID - */ - PRINTF("Device ID @ 0x%08lx: 0x%02x\n", (ulong)(&addr[2]), value[1]); - switch (value[1]) { - case (INTEL_ID_28F128J3A & 0xff): - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 16 * 1024 * 1024; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - return (NO_FLASH); - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - return (info->size); -} - - -/*----------------------------------------------------------------------- - * Erase the specified sectors in the specified FLASH device - */ -int -flash_erase(flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) { - printf ("Can erase only Intel flash types - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - - /* - * Start erase on unprotected sectors - */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_char *addr = (uchar *)(info->start[sect]); - vu_char status; - - /* - * Disable interrupts which might cause a timeout - */ - flag = disable_interrupts(); - - *addr = SCS_CLEAR_STATUS_CMD; - *addr = SCS_BLOCK_ERASE_CMD; - *addr = SCS_BLOCK_ERASE_RESUME_CMD; - - /* - * Re-enable interrupts if necessary - */ - if (flag) - enable_interrupts(); - - /* - * Wait at least 80us - let's wait 1 ms - */ - udelay (1000); - - while (((status = *addr) & SCS_SR7) != SCS_SR7) { - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = SCS_BLOCK_ERASE_SUSPEND_CMD; - *addr = SCS_READ_CMD; - return 1; - } - - /* - * Show that we're waiting - */ - if ((now - last) > 1000) { /* 1 second */ - putc ('.'); - last = now; - } - } - *addr = SCS_READ_CMD; - } - } - printf (" done\n"); - return 0; -} - - -#ifdef CONFIG_SYS_GEN860T_FLASH_USE_WRITE_BUFFER -/* - * Allocate a flash buffer, fill it with data and write it to the flash. - * 0 - OK - * 1 - Timeout on buffer request - * - * NOTE: After the last call to this function, WSM status needs to be checked! - */ -static int -write_flash_buffer8(flash_info_t *info_p, vu_char *src_p, vu_char *dest_p, - uint count) -{ - vu_char *block_addr_p = NULL; - vu_char *start_addr_p = NULL; - ulong blocksize = info_p->size / (ulong)info_p->sector_count; - - int i; - uint time = get_timer(0); - - PRINTF("%s:%d: src: 0x%p dest: 0x%p count: %d\n", - __FUNCTION__, __LINE__, src_p, dest_p, count); - - /* - * What block are we in? We already know that the source address is - * in the flash address range, but we also can't cross a block boundary. - * We assume that the block does not cross a boundary (we'll check before - * calling this function). - */ - for (i = 0; i < info_p->sector_count; ++i) { - if ( ((ulong)dest_p >= info_p->start[i]) && - ((ulong)dest_p < (info_p->start[i] + blocksize)) ) { - PRINTF("%s:%d: Dest addr 0x%p is in block %d @ 0x%.8lx\n", - __FUNCTION__, __LINE__, dest_p, i, info_p->start[i]); - block_addr_p = (vu_char *)info_p->start[i]; - break; - } - } - - /* - * Request a buffer - */ - *block_addr_p = SCS_WRITE_BUF_CMD; - while ((*block_addr_p & SCS_XSR7) != SCS_XSR7) { - if (get_timer(time) > CONFIG_SYS_FLASH_ALLOC_BUFFER_TOUT) { - PRINTF("%s:%d: Buffer allocation timeout @ 0x%p (waited %d mS)\n", - __FUNCTION__, __LINE__, block_addr_p, - CONFIG_SYS_FLASH_ALLOC_BUFFER_TOUT); - return 1; - } - *block_addr_p = SCS_WRITE_BUF_CMD; - } - - /* - * Fill the buffer with data - */ - start_addr_p = dest_p; - *block_addr_p = count - 1; /* flash device wants count - 1 */ - PRINTF("%s:%d: Fill buffer at block addr 0x%p\n", - __FUNCTION__, __LINE__, block_addr_p); - for (i = 0; i < count; i++) { - *start_addr_p++ = *src_p++; - } - - /* - * Flush buffer to flash - */ - *block_addr_p = SCS_PROGRAM_RESUME_CMD; -#if 1 - time = get_timer(0); - while ((*block_addr_p & SCS_SR7) != SCS_SR7) { - if (get_timer(time) > CONFIG_SYS_FLASH_WRITE_TOUT) { - PRINTF("%s:%d: Write timeout @ 0x%p (waited %d mS)\n", - __FUNCTION__, __LINE__, block_addr_p, CONFIG_SYS_FLASH_WRITE_TOUT); - return 1; - } - } - -#endif - return 0; -} -#endif - - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ -int -write_buff(flash_info_t *info_p, uchar *src_p, ulong addr, ulong count) -{ - int rc = 0; -#ifdef CONFIG_SYS_GEN860T_FLASH_USE_WRITE_BUFFER -#define FLASH_WRITE_BUF_SIZE 0x00000020 /* 32 bytes */ - int i; - uint bufs; - ulong buf_count; - vu_char *sp; - vu_char *dp; -#else - ulong wp; -#endif - - PRINTF("\n%s:%d: src: 0x%.8lx dest: 0x%.8lx size: %d (0x%.8lx)\n", - __FUNCTION__, __LINE__, (ulong)src_p, addr, (uint)count, count); - - if (info_p->flash_id == FLASH_UNKNOWN) { - return 4; - } - -#ifdef CONFIG_SYS_GEN860T_FLASH_USE_WRITE_BUFFER - sp = src_p; - dp = (uchar *)addr; - - /* - * For maximum performance, we want to align the start address to - * the beginning of a write buffer boundary (i.e. A4-A0 of the - * start address = 0). See how many bytes are required to get to a - * write-buffer-aligned address. If that number is non-zero, do - * non buffered writes of the non-aligned data. By doing non-buffered - * writes, we avoid the problem of crossing a block (sector) boundary - * with buffered writes. - */ - buf_count = FLASH_WRITE_BUF_SIZE - (addr & (FLASH_WRITE_BUF_SIZE - 1)); - if (buf_count == FLASH_WRITE_BUF_SIZE) { /* already on a boundary */ - buf_count = 0; - } - if (buf_count > count) { /* not a full buffers worth of data to write */ - buf_count = count; - } - count -= buf_count; - - PRINTF("%s:%d: Write buffer alignment count = %ld\n", - __FUNCTION__, __LINE__, buf_count); - while (buf_count-- >= 1) { - if ((rc = write_data8(info_p, (ulong)dp++, *sp++)) != 0) { - return (rc); - } - } - - PRINTF("%s:%d: count = %ld\n", __FUNCTION__, __LINE__, count); - if (count == 0) { /* all done */ - PRINTF("%s:%d: Less than 1 buffer (%d) worth of bytes\n", - __FUNCTION__, __LINE__, FLASH_WRITE_BUF_SIZE); - return (rc); - } - - /* - * Now that we are write buffer aligned, write full or partial buffers. - * The fact that we are write buffer aligned automatically avoids - * crossing a block address during a write buffer operation. - */ - bufs = count / FLASH_WRITE_BUF_SIZE; - PRINTF("%s:%d: %d (0x%x) buffers to write\n", __FUNCTION__, __LINE__, - bufs, bufs); - while (bufs >= 1) { - rc = write_flash_buffer8(info_p, sp, dp, FLASH_WRITE_BUF_SIZE); - if (rc != 0) { - PRINTF("%s:%d: ** Error writing buf %d\n", - __FUNCTION__, __LINE__, bufs); - return (rc); - } - bufs--; - sp += FLASH_WRITE_BUF_SIZE; - dp += FLASH_WRITE_BUF_SIZE; - } - - /* - * Do the leftovers - */ - i = count % FLASH_WRITE_BUF_SIZE; - PRINTF("%s:%d: %d (0x%x) leftover bytes\n", __FUNCTION__, __LINE__, i, i); - if (i > 0) { - rc = write_flash_buffer8(info_p, sp, dp, i); - } - - sp = (vu_char*)info_p->start[0]; - *sp = SCS_READ_CMD; - return (rc); - -#else - wp = addr; - while (count-- >= 1) { - if((rc = write_data8(info_p, wp++, *src_p++)) != 0) - return (rc); - } - return 0; -#endif -} - - -/*----------------------------------------------------------------------- - * Write a byte to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int -write_data8 (flash_info_t *info, ulong dest, uchar data) -{ - vu_char *addr = (vu_char *)dest; - vu_char status; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = SCS_PROGRAM_CMD; - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - while (((status = *addr) & SCS_SR7) != SCS_SR7) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = SCS_READ_CMD; - return (1); - } - } - *addr = SCS_READ_CMD; - return (0); -} - -/* vim: set ts=4 sw=4 tw=78: */ diff --git a/board/gen860t/fpga.c b/board/gen860t/fpga.c deleted file mode 100644 index dd0ef707d6..0000000000 --- a/board/gen860t/fpga.c +++ /dev/null @@ -1,362 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Virtex2 FPGA configuration support for the GEN860T computer - */ - -#include <common.h> -#include <virtex2.h> -#include <command.h> -#include "fpga.h" - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_FPGA) - -#if 0 -#define GEN860T_FPGA_DEBUG -#endif - -#ifdef GEN860T_FPGA_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - -/* - * Port bit numbers for the Selectmap controls - */ -#define FPGA_INIT_BIT_NUM 22 /* PB22 */ -#define FPGA_RESET_BIT_NUM 11 /* PC11 */ -#define FPGA_DONE_BIT_NUM 16 /* PB16 */ -#define FPGA_PROGRAM_BIT_NUM 7 /* PA7 */ - -/* Note that these are pointers to code that is in Flash. They will be - * relocated at runtime. - */ -xilinx_virtex2_slave_selectmap_fns fpga_fns = { - fpga_pre_config_fn, - fpga_pgm_fn, - fpga_init_fn, - fpga_err_fn, - fpga_done_fn, - fpga_clk_fn, - fpga_cs_fn, - fpga_wr_fn, - fpga_read_data_fn, - fpga_write_data_fn, - fpga_busy_fn, - fpga_abort_fn, - fpga_post_config_fn -}; - -xilinx_desc fpga[CONFIG_FPGA_COUNT] = { - {xilinx_virtex2, - slave_selectmap, - XILINX_XC2V3000_SIZE, - (void *) &fpga_fns, - 0} -}; - -/* - * Display FPGA revision information - */ -void print_fpga_revision (void) -{ - vu_long *rev_p = (vu_long *) 0x60000008; - - printf ("FPGA Revision 0x%.8lx" - " (Date %.2lx/%.2lx/%.2lx, Status \"%.1lx\", Version %.3lu)\n", - *rev_p, - ((*rev_p >> 28) & 0xf), - ((*rev_p >> 20) & 0xff), - ((*rev_p >> 12) & 0xff), - ((*rev_p >> 8) & 0xf), (*rev_p & 0xff)); -} - - -/* - * Perform a simple test of the FPGA to processor interface using the FPGA's - * inverting bus test register. The great thing about doing a read/write - * test on a register that inverts it's contents is that you avoid any - * problems with bus charging. - * Return 0 on failure, 1 on success. - */ -int test_fpga_ibtr (void) -{ - vu_long *ibtr_p = (vu_long *) 0x60000010; - vu_long readback; - vu_long compare; - int i; - int j; - int k; - int pass = 1; - - static const ulong bitpattern[] = { - 0xdeadbeef, /* magic ID pattern for debug */ - 0x00000001, /* single bit */ - 0x00000003, /* two adjacent bits */ - 0x00000007, /* three adjacent bits */ - 0x0000000F, /* four adjacent bits */ - 0x00000005, /* two non-adjacent bits */ - 0x00000015, /* three non-adjacent bits */ - 0x00000055, /* four non-adjacent bits */ - 0xaaaaaaaa, /* alternating 1/0 */ - }; - - for (i = 0; i < 1024; i++) { - for (j = 0; j < 31; j++) { - for (k = 0; - k < sizeof (bitpattern) / sizeof (bitpattern[0]); - k++) { - *ibtr_p = compare = (bitpattern[k] << j); - readback = *ibtr_p; - if (readback != ~compare) { - printf ("%s:%d: FPGA test fail: expected 0x%.8lx" " actual 0x%.8lx\n", __FUNCTION__, __LINE__, ~compare, readback); - pass = 0; - break; - } - } - if (!pass) - break; - } - if (!pass) - break; - } - if (pass) { - printf ("FPGA inverting bus test passed\n"); - print_fpga_revision (); - } else { - printf ("** FPGA inverting bus test failed\n"); - } - return pass; -} - - -/* - * Set the active-low FPGA reset signal. - */ -void fpga_reset (int assert) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - PRINTF ("%s:%d: RESET ", __FUNCTION__, __LINE__); - if (assert) { - immap->im_ioport.iop_pcdat &= ~(0x8000 >> FPGA_RESET_BIT_NUM); - PRINTF ("asserted\n"); - } else { - immap->im_ioport.iop_pcdat |= (0x8000 >> FPGA_RESET_BIT_NUM); - PRINTF ("deasserted\n"); - } -} - - -/* - * Initialize the SelectMap interface. We assume that the mode and the - * initial state of all of the port pins have already been set! - */ -void fpga_selectmap_init (void) -{ - PRINTF ("%s:%d: Initialize SelectMap interface\n", __FUNCTION__, - __LINE__); - fpga_pgm_fn(false, false, 0); /* make sure program pin is inactive */ -} - - -/* - * Initialize the fpga. Return 1 on success, 0 on failure. - */ -int gen860t_init_fpga (void) -{ - int i; - - PRINTF ("%s:%d: Initialize FPGA interface\n", - __FUNCTION__, __LINE__); - fpga_init (); - fpga_selectmap_init (); - - for (i = 0; i < CONFIG_FPGA_COUNT; i++) { - PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i); - fpga_add (fpga_xilinx, &fpga[i]); - } - return 1; -} - - -/* - * Set the FPGA's active-low SelectMap program line to the specified level - */ -int fpga_pgm_fn (int assert, int flush, int cookie) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - PRINTF ("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__); - - if (assert) { - immap->im_ioport.iop_padat &= - ~(0x8000 >> FPGA_PROGRAM_BIT_NUM); - PRINTF ("asserted\n"); - } else { - immap->im_ioport.iop_padat |= - (0x8000 >> FPGA_PROGRAM_BIT_NUM); - PRINTF ("deasserted\n"); - } - return assert; -} - - -/* - * Test the state of the active-low FPGA INIT line. Return 1 on INIT - * asserted (low). - */ -int fpga_init_fn (int cookie) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - PRINTF ("%s:%d: INIT check... ", __FUNCTION__, __LINE__); - if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_INIT_BIT_NUM)) { - PRINTF ("high\n"); - return 0; - } else { - PRINTF ("low\n"); - return 1; - } -} - - -/* - * Test the state of the active-high FPGA DONE pin - */ -int fpga_done_fn (int cookie) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - PRINTF ("%s:%d: DONE check... ", __FUNCTION__, __LINE__); - if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_DONE_BIT_NUM)) { - PRINTF ("high\n"); - return FPGA_SUCCESS; - } else { - PRINTF ("low\n"); - return FPGA_FAIL; - } -} - - -/* - * Read FPGA SelectMap data. - */ -int fpga_read_data_fn (unsigned char *data, int cookie) -{ - vu_char *p = (vu_char *) SELECTMAP_BASE; - - *data = *p; -#if 0 - PRINTF ("%s: Read 0x%x into 0x%p\n", __FUNCTION__, (int) data, data); -#endif - return (int) data; -} - - -/* - * Write data to the FPGA SelectMap port - */ -int fpga_write_data_fn (unsigned char data, int flush, int cookie) -{ - vu_char *p = (vu_char *) SELECTMAP_BASE; - -#if 0 - PRINTF ("%s: Write Data 0x%x\n", __FUNCTION__, (int) data); -#endif - *p = data; - return (int) data; -} - - -/* - * Abort and FPGA operation - */ -int fpga_abort_fn (int cookie) -{ - PRINTF ("%s:%d: FPGA program sequence aborted\n", - __FUNCTION__, __LINE__); - return FPGA_FAIL; -} - - -/* - * FPGA pre-configuration function. Just make sure that - * FPGA reset is asserted to keep the FPGA from starting up after - * configuration. - */ -int fpga_pre_config_fn (int cookie) -{ - PRINTF ("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__); - fpga_reset(true); - return 0; -} - - -/* - * FPGA post configuration function. Blip the FPGA reset line and then see if - * the FPGA appears to be running. - */ -int fpga_post_config_fn (int cookie) -{ - int rc; - - PRINTF ("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__); - fpga_reset(true); - udelay (1000); - fpga_reset(false); - udelay (1000); - - /* - * Use the FPGA,s inverting bus test register to do a simple test of the - * processor interface. - */ - rc = test_fpga_ibtr (); - return rc; -} - - -/* - * Clock, chip select and write signal assert functions and error check - * and busy functions. These are only stubs because the GEN860T selectmap - * interface handles sequencing of control signals automatically (it uses - * a memory-mapped interface to the FPGA SelectMap port). The design of - * the interface guarantees that the SelectMap port cannot be overrun so - * no busy check is needed. A configuration error is signalled by INIT - * going low during configuration, so there is no need for a separate error - * function. - */ -int fpga_clk_fn (int assert_clk, int flush, int cookie) -{ - return assert_clk; -} - -int fpga_cs_fn (int assert_cs, int flush, int cookie) -{ - return assert_cs; -} - -int fpga_wr_fn (int assert_write, int flush, int cookie) -{ - return assert_write; -} - -int fpga_err_fn (int cookie) -{ - return 0; -} - -int fpga_busy_fn (int cookie) -{ - return 0; -} -#endif diff --git a/board/gen860t/fpga.h b/board/gen860t/fpga.h deleted file mode 100644 index 95c15c4f63..0000000000 --- a/board/gen860t/fpga.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Virtex2 FPGA configuration support for the GEN860T computer - */ - -extern int gen860t_init_fpga(void); -extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); -extern int fpga_init_fn(int cookie); -extern int fpga_err_fn(int cookie); -extern int fpga_done_fn(int cookie); -extern int fpga_clk_fn(int assert_clk, int flush, int cookie); -extern int fpga_cs_fn(int assert_cs, int flush, int cookie); -extern int fpga_wr_fn(int assert_write, int flush, int cookie); -extern int fpga_read_data_fn(unsigned char *data, int cookie); -extern int fpga_write_data_fn(unsigned char data, int flush, int cookie); -extern int fpga_busy_fn(int cookie); -extern int fpga_abort_fn(int cookie ); -extern int fpga_pre_config_fn(int cookie ); -extern int fpga_post_config_fn(int cookie ); diff --git a/board/gen860t/gen860t.c b/board/gen860t/gen860t.c deleted file mode 100644 index fe139f4920..0000000000 --- a/board/gen860t/gen860t.c +++ /dev/null @@ -1,278 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Keith Outwater, keith_outwater@mvis.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <virtex2.h> -#include <common.h> -#include <mpc8xx.h> -#include <asm/8xx_immap.h> -#include "beeper.h" -#include "fpga.h" -#include "ioport.h" - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_STATUS_LED -#include <status_led.h> -#endif - -#if defined(CONFIG_CMD_MII) && defined(CONFIG_MII) -#include <net.h> -#endif - -#if 0 -#define GEN860T_DEBUG -#endif - -#ifdef GEN860T_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - -/* - * The following UPM init tables were generated automatically by - * Motorola's MCUINIT program. See the README file for UPM to - * SDRAM pin assignments if you want to type this data into - * MCUINIT in order to reverse engineer the waveforms. - */ - -/* - * UPM initialization tables for MICRON MT48LC16M16A2TG SDRAM devices - * (UPMA) and Virtex FPGA SelectMap interface (UPMB). - * NOTE that unused areas of the table are used to hold NOP, precharge - * and mode register set sequences. - * - */ -#define UPMA_NOP_ADDR 0x5 -#define UPMA_PRECHARGE_ADDR 0x6 -#define UPMA_MRS_ADDR 0x12 - -#define UPM_SINGLE_READ_ADDR 0x00 -#define UPM_BURST_READ_ADDR 0x08 -#define UPM_SINGLE_WRITE_ADDR 0x18 -#define UPM_BURST_WRITE_ADDR 0x20 -#define UPM_REFRESH_ADDR 0x30 - -const uint sdram_upm_table[] = { - /* single read (offset 0x00 in upm ram) */ - 0x0e0fdc04, 0x01adfc04, 0x0fbffc00, 0x1fff5c05, - 0xffffffff, 0x0fffffcd, 0x0fff0fce, 0xefcfffff, - /* burst read (offset 0x08 in upm ram) */ - 0x0f0fdc04, 0x00fdfc04, 0xf0fffc00, 0xf0fffc00, - 0xf1fffc00, 0xfffffc00, 0xfffffc05, 0xffffffff, - 0xffffffff, 0xffffffff, 0x0ffffff4, 0x1f3d5ff4, - 0xfffffff4, 0xfffffff5, 0xffffffff, 0xffffffff, - /* single write (offset 0x18 in upm ram) */ - 0x0f0fdc04, 0x00ad3c00, 0x1fff5c05, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - /* burst write (offset 0x20 in upm ram) */ - 0x0f0fdc00, 0x10fd7c00, 0xf0fffc00, 0xf0fffc00, - 0xf1fffc04, 0xfffffc05, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xfffff7ff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - /* refresh (offset 0x30 in upm ram) */ - 0x1ffddc84, 0xfffffc04, 0xfffffc04, 0xfffffc84, - 0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - /* exception (offset 0x3C in upm ram) */ -}; - -const uint selectmap_upm_table[] = { - /* single read (offset 0x00 in upm ram) */ - 0x88fffc06, 0x00fff404, 0x00fffc04, 0x33fffc00, - 0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff, - /* burst read (offset 0x08 in upm ram) */ - 0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - /* single write (offset 0x18 in upm ram) */ - 0x88fffc04, 0x00fff400, 0x77fffc05, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - /* burst write (offset 0x20 in upm ram) */ - 0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - /* refresh (offset 0x30 in upm ram) */ - 0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - /* exception (offset 0x3C in upm ram) */ - 0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff -}; - -/* - * Check board identity. Always successful (gives information only) - */ -int checkboard (void) -{ - char *s; - char buf[64]; - int i; - - i = getenv_f("board_id", buf, sizeof (buf)); - s = (i > 0) ? buf : NULL; - - if (s) { - printf ("%s ", s); - } else { - printf ("<unknown> "); - } - - i = getenv_f("serial#", buf, sizeof (buf)); - s = (i > 0) ? buf : NULL; - - if (s) { - printf ("S/N %s\n", s); - } else { - printf ("S/N <unknown>\n"); - } - - printf ("CPU at %s MHz, ", strmhz (buf, gd->cpu_clk)); - printf ("local bus at %s MHz\n", strmhz (buf, gd->bus_clk)); - return (0); -} - -/* - * Initialize SDRAM - */ -phys_size_t initdram (int board_type) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - - upmconfig (UPMA, - (uint *) sdram_upm_table, - sizeof (sdram_upm_table) / sizeof (uint) - ); - - /* - * Setup MAMR register - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K; - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - - /* - * Map CS1* to SDRAM bank - */ - memctl->memc_or1 = CONFIG_SYS_OR1; - memctl->memc_br1 = CONFIG_SYS_BR1; - - /* - * Perform SDRAM initialization sequence: - * 1. Apply at least one NOP command - * 2. 100 uS delay (JEDEC standard says 200 uS) - * 3. Issue 4 precharge commands - * 4. Perform two refresh cycles - * 5. Program mode register - * - * Program SDRAM for standard operation, sequential burst, burst length - * of 4, CAS latency of 2. - */ - memctl->memc_mar = 0x00000000; - memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 | - MCR_MLCF (0) | UPMA_NOP_ADDR; - udelay (200); - memctl->memc_mar = 0x00000000; - memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 | - MCR_MLCF (4) | UPMA_PRECHARGE_ADDR; - - memctl->memc_mar = 0x00000000; - memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 | - MCR_MLCF (2) | UPM_REFRESH_ADDR; - - memctl->memc_mar = 0x00000088; - memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 | - MCR_MLCF (1) | UPMA_MRS_ADDR; - - memctl->memc_mar = 0x00000000; - memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 | - MCR_MLCF (0) | UPMA_NOP_ADDR; - /* - * Enable refresh - */ - memctl->memc_mamr |= MAMR_PTAE; - - return (SDRAM_SIZE); -} - -/* - * Disk On Chip (DOC) Millenium initialization. - * The DOC lives in the CS2* space - */ -#if defined(CONFIG_CMD_DOC) -void doc_init (void) -{ - printf ("Probing at 0x%.8x: ", DOC_BASE); - doc_probe (DOC_BASE); -} -#endif - -/* - * Miscellaneous intialization - */ -int misc_init_r (void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - - /* - * Set up UPMB to handle the Virtex FPGA SelectMap interface - */ - upmconfig (UPMB, (uint *) selectmap_upm_table, - sizeof (selectmap_upm_table) / sizeof (uint)); - - memctl->memc_mbmr = 0x0; - - config_mpc8xx_ioports (immr); - -#if defined(CONFIG_CMD_MII) - mii_init (); -#endif - -#if defined(CONFIG_FPGA) - gen860t_init_fpga (); -#endif - return 0; -} - -/* - * Final init hook before entering command loop. - */ -int last_stage_init (void) -{ -#if !defined(CONFIG_SC) - char buf[256]; - int i; - - /* - * Turn the beeper volume all the way down in case this is a warm boot. - */ - set_beeper_volume (-64); - init_beeper (); - - /* - * Read the environment to see what to do with the beeper - */ - i = getenv_f("beeper", buf, sizeof (buf)); - if (i > 0) { - do_beeper (buf); - } -#endif - return 0; -} - -/* - * Stub to make POST code happy. Can't self-poweroff, so just hang. - */ -void board_poweroff (void) -{ - puts ("### Please power off the board ###\n"); - while (1); -} diff --git a/board/gen860t/ioport.c b/board/gen860t/ioport.c deleted file mode 100644 index 7cd209b7ac..0000000000 --- a/board/gen860t/ioport.c +++ /dev/null @@ -1,331 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> -#include <asm/8xx_immap.h> -#include "ioport.h" - -#if 0 -#define IOPORT_DEBUG -#endif - -#ifdef IOPORT_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - -/* - * The ioport configuration table. - */ -const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = { - /* - * Port A configuration - * Pin Signal Type Active Initial state - * PA7 fpgaProgramLowOut Out Low High - * PA1 fpgaCoreVoltageFailLow In Low N/A - */ - { /* conf ppar psor pdir podr pdat pint function */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* No pin */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* No pin */ - /* PA15 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PA14 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PA13 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PA12 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PA11 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PA10 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PA9 */ { 1, 0, 0, 1, 0, 0, 0 }, /* grn bicolor LED 1*/ - /* PA8 */ { 1, 0, 0, 1, 0, 0, 0 }, /* red bicolor LED 1*/ - /* PA7 */ { 1, 0, 0, 1, 0, 1, 0 }, /* fpgaProgramLow */ - /* PA6 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PA5 */ { 1, 0, 0, 1, 0, 0, 0 }, /* grn bicolor LED 0*/ - /* PA4 */ { 1, 0, 0, 1, 0, 0, 0 }, /* red bicolor LED 0*/ - /* PA3 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PA2 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#if !defined(CONFIG_SC) - /* PA1 */ { 1, 0, 0, 0, 0, 0, 0 }, /* fpgaCoreVoltageFail*/ -#else - /* PA1 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#endif - /* PA0 */ { 0, 0, 0, 0, 0, 0, 0 } /* */ - }, - - /* - * Port B configuration - * Pin Signal Type Active Initial state - * PB14 docBusyLowIn In Low X - * PB15 gpio1Sig Out High Low - * PB16 fpgaDoneBi In High X - * PB17 swBitOkLowOut Out Low High - * PB19 speakerVolSig Out/Hi-Z High/Low High (Hi-Z) - * PB22 fpgaInitLowBi In Low X - * PB23 batteryOkSig In High X - * PB31 pulseCatcherClr Out High 0 - */ - { /* conf ppar psor pdir podr pdat pint function */ -#if !defined(CONFIG_SC) - /* PB31 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#else - /* PB31 */ { 1, 0, 0, 1, 0, 0, 0 }, /* pulseCatcherClr */ -#endif - /* PB30 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PB29 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PB28 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PB27 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PB26 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PB25 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PB24 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#if !defined(CONFIG_SC) - /* PB23 */ { 1, 0, 0, 0, 0, 0, 0 }, /* batteryOk */ -#else - /* PB23 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#endif - /* PB22 */ { 1, 0, 0, 0, 0, 0, 0 }, /* fpgaInitLowBi */ - /* PB21 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PB20 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#if !defined(CONFIG_SC) - /* PB19 */ { 1, 0, 0, 1, 1, 1, 0 }, /* speakerVol */ -#else - /* PB19 */ { 0, 0, 0, 1, 1, 1, 0 }, /* */ -#endif - /* PB18 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PB17 */ { 1, 0, 0, 1, 0, 1, 0 }, /* swBitOkLow */ - /* PB16 */ { 1, 0, 0, 0, 0, 0, 0 }, /* fpgaDone */ - /* PB15 */ { 1, 0, 0, 1, 0, 0, 0 }, /* gpio1 */ -#if !defined(CONFIG_SC) - /* PB14 */ { 1, 0, 0, 0, 0, 0, 0 } /* docBusyLow */ -#else - /* PB14 */ { 0, 0, 0, 0, 0, 0, 0 } /* */ -#endif - }, - - /* - * Port C configuration - * Pin Signal Type Active Initial state - * PC4 i2cBus1EnSig Out High High - * PC5 i2cBus2EnSig Out High High - * PC6 gpio0Sig Out High Low - * PC8 i2cBus3EnSig Out High High - * PC10 i2cBus4EnSig Out High High - * PC11 fpgaResetLowOut Out Low High - * PC12 systemBitOkIn In High X - * PC15 selfDreqLow In Low X - */ - { /* conf ppar psor pdir podr pdat pint function */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PC15 */ { 1, 0, 0, 0, 0, 0, 0 }, /* selfDreqLowIn */ - /* PC14 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PC13 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#if !defined(CONFIG_SC) - /* PC12 */ { 1, 0, 0, 0, 0, 0, 0 }, /* systemBitOkIn */ -#else - /* PC12 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#endif - /* PC11 */ { 1, 0, 0, 1, 0, 1, 0 }, /* fpgaResetLowOut */ -#if !defined(CONFIG_SC) - /* PC10 */ { 1, 0, 0, 1, 0, 1, 0 }, /* i2cBus4EnSig */ -#else - /* PC10 */ { 0, 0, 0, 1, 0, 1, 0 }, /* */ -#endif - /* PC9 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#if !defined(CONFIG_SC) - /* PC8 */ { 1, 0, 0, 1, 0, 1, 0 }, /* i2cBus3EnSig */ -#else - /* PC8 */ { 0, 0, 0, 1, 0, 1, 0 }, /* */ -#endif - /* PC7 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PC6 */ { 1, 0, 0, 1, 0, 1, 0 }, /* gpio0 */ -#if !defined(CONFIG_SC) - /* PC5 */ { 1, 0, 0, 1, 0, 1, 0 }, /* i2cBus2EnSig */ - /* PC4 */ { 1, 0, 0, 1, 0, 1, 0 }, /* i2cBus1EnSig */ -#else - /* PC5 */ { 0, 0, 0, 1, 0, 1, 0 }, /* */ - /* PC4 */ { 0, 0, 0, 1, 0, 1, 0 }, /* */ -#endif - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 } /* */ - }, - - /* - * Port D configuration - */ - { /* conf ppar psor pdir podr pdat pint function */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD15 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD14 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD13 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD12 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD11 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD10 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD9 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD8 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD7 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD6 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD5 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD4 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD3 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 } /* */ - } -}; - -/* - * Configure the MPC8XX I/O ports per the ioport configuration table - * (taken from ./arch/powerpc/cpu/mpc8260/cpu_init.c) - */ -void config_mpc8xx_ioports (volatile immap_t * immr) -{ - int portnum; - - for (portnum = 0; portnum < NUM_PORTS; portnum++) { - uint pmsk = 0, ppar = 0, psor = 0, pdir = 0; - uint podr = 0, pdat = 0, pint = 0; - uint msk = 1; - mpc8xx_iop_conf_t *iopc = - (mpc8xx_iop_conf_t *) & iop_conf_tab[portnum][0]; - mpc8xx_iop_conf_t *eiopc = iopc + PORT_BITS; - - /* - * For all ports except port B, ignore the two don't care entries - * in the configuration tables. - */ - if (portnum != 1) { - iopc = (mpc8xx_iop_conf_t *) & - iop_conf_tab[portnum][2]; - } - - /* - * NOTE: index 0 refers to pin 17, index 17 refers to pin 0 - */ - while (iopc < eiopc) { - if (iopc->conf) { - pmsk |= msk; - if (iopc->ppar) - ppar |= msk; - if (iopc->psor) - psor |= msk; - if (iopc->pdir) - pdir |= msk; - if (iopc->podr) - podr |= msk; - if (iopc->pdat) - pdat |= msk; - if (iopc->pint) - pint |= msk; - } - msk <<= 1; - iopc++; - } - - PRINTF ("%s:%d:\n portnum=%d ", __FUNCTION__, __LINE__, - portnum); -#ifdef IOPORT_DEBUG - switch (portnum) { - case 0: - printf ("(A)\n"); - break; - case 1: - printf ("(B)\n"); - break; - case 2: - printf ("(C)\n"); - break; - case 3: - printf ("(D)\n"); - break; - default: - printf ("(?)\n"); - break; - } -#endif - PRINTF (" ppar=0x%.8x pdir=0x%.8x podr=0x%.8x\n" - " pdat=0x%.8x psor=0x%.8x pint=0x%.8x pmsk=0x%.8x\n", - ppar, pdir, podr, pdat, psor, pint, pmsk); - - /* - * Have to handle the ioports on a port-by-port basis since there - * are three different flavors. - */ - if (pmsk != 0) { - uint tpmsk = ~pmsk; - - if (0 == portnum) { /* port A */ - immr->im_ioport.iop_papar &= tpmsk; - immr->im_ioport.iop_padat = - (immr->im_ioport. - iop_padat & tpmsk) | pdat; - immr->im_ioport.iop_padir = - (immr->im_ioport. - iop_padir & tpmsk) | pdir; - immr->im_ioport.iop_paodr = - (immr->im_ioport. - iop_paodr & tpmsk) | podr; - immr->im_ioport.iop_papar |= ppar; - } else if (1 == portnum) { /* port B */ - immr->im_cpm.cp_pbpar &= tpmsk; - immr->im_cpm.cp_pbdat = - (immr->im_cpm. - cp_pbdat & tpmsk) | pdat; - immr->im_cpm.cp_pbdir = - (immr->im_cpm. - cp_pbdir & tpmsk) | pdir; - immr->im_cpm.cp_pbodr = - (immr->im_cpm. - cp_pbodr & tpmsk) | podr; - immr->im_cpm.cp_pbpar |= ppar; - } else if (2 == portnum) { /* port C */ - immr->im_ioport.iop_pcpar &= tpmsk; - immr->im_ioport.iop_pcdat = - (immr->im_ioport. - iop_pcdat & tpmsk) | pdat; - immr->im_ioport.iop_pcdir = - (immr->im_ioport. - iop_pcdir & tpmsk) | pdir; - immr->im_ioport.iop_pcint = - (immr->im_ioport. - iop_pcint & tpmsk) | pint; - immr->im_ioport.iop_pcso = - (immr->im_ioport. - iop_pcso & tpmsk) | psor; - immr->im_ioport.iop_pcpar |= ppar; - } else if (3 == portnum) { /* port D */ - immr->im_ioport.iop_pdpar &= tpmsk; - immr->im_ioport.iop_pddat = - (immr->im_ioport. - iop_pddat & tpmsk) | pdat; - immr->im_ioport.iop_pddir = - (immr->im_ioport. - iop_pddir & tpmsk) | pdir; - immr->im_ioport.iop_pdpar |= ppar; - } - } - } - - PRINTF ("%s:%d: Port A:\n papar=0x%.4x padir=0x%.4x" - " paodr=0x%.4x\n padat=0x%.4x\n", __FUNCTION__, __LINE__, - immr->im_ioport.iop_papar, immr->im_ioport.iop_padir, - immr->im_ioport.iop_paodr, immr->im_ioport.iop_padat); - PRINTF ("%s:%d: Port B:\n pbpar=0x%.8x pbdir=0x%.8x" - " pbodr=0x%.8x\n pbdat=0x%.8x\n", __FUNCTION__, __LINE__, - immr->im_cpm.cp_pbpar, immr->im_cpm.cp_pbdir, - immr->im_cpm.cp_pbodr, immr->im_cpm.cp_pbdat); - PRINTF ("%s:%d: Port C:\n pcpar=0x%.4x pcdir=0x%.4x" - " pcdat=0x%.4x\n pcso=0x%.4x pcint=0x%.4x\n ", - __FUNCTION__, __LINE__, immr->im_ioport.iop_pcpar, - immr->im_ioport.iop_pcdir, immr->im_ioport.iop_pcdat, - immr->im_ioport.iop_pcso, immr->im_ioport.iop_pcint); - PRINTF ("%s:%d: Port D:\n pdpar=0x%.4x pddir=0x%.4x" - " pddat=0x%.4x\n", __FUNCTION__, __LINE__, - immr->im_ioport.iop_pdpar, immr->im_ioport.iop_pddir, - immr->im_ioport.iop_pddat); -} diff --git a/board/gen860t/ioport.h b/board/gen860t/ioport.h deleted file mode 100644 index 4ac2aa4dd8..0000000000 --- a/board/gen860t/ioport.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Keith Outwater, keith_outwater@mvis.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define NUM_PORTS 4 -#define PORT_BITS 18 - -/* - * This structure provides configuration information for one port pin. - * We include all fields needed to initialize any of the ioports. - */ -typedef struct { - unsigned char conf:1; /* If 1, configure this port */ - unsigned char ppar:1; /* Port Pin Assignment Register */ - unsigned char psor:1; /* Port Special Options Register */ - unsigned char pdir:1; /* Port Data Direction Register */ - unsigned char podr:1; /* Port Open Drain Register */ - unsigned char pdat:1; /* Port Data Register */ - unsigned char pint:1; /* Port Interrupt Register */ -} mpc8xx_iop_conf_t; - -extern void config_mpc8xx_ioports(volatile immap_t *immr); diff --git a/board/gen860t/u-boot-flashenv.lds b/board/gen860t/u-boot-flashenv.lds deleted file mode 100644 index 7a4a7637e8..0000000000 --- a/board/gen860t/u-boot-flashenv.lds +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Linker command file for the GEN860T board when the environment is - * stored in flash memory. - * - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* - * Read-only sections, merged into text segment: - */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* - * Read-write section, merged into data segment: - */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - KEEP(*(.got)) - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data: - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - - __bss_end = . ; - PROVIDE (end = .); - - .ppcenv: - { - . = env_offset; - common/env_embedded.o - } -} diff --git a/board/gen860t/u-boot.lds b/board/gen860t/u-boot.lds deleted file mode 100644 index 3371c0a3ee..0000000000 --- a/board/gen860t/u-boot.lds +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Linker command file for the GEN860T board. - * - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* - * Read-only sections, merged into text segment: - */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* - * Read-write section, merged into data segment: - */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c index cd083795b8..4a736137e3 100644 --- a/board/keymile/kmp204x/kmp204x.c +++ b/board/keymile/kmp204x/kmp204x.c @@ -108,8 +108,8 @@ int board_early_init_f(void) /* and enable WD on it */ qrio_wdmask(BFTIC4_RST, true); - /* set the ZL30138's prstcfg to reset at power-up and unit reset only */ - qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_UNIT_RST); + /* set the ZL30138's prstcfg to reset at power-up only */ + qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST); /* and take it out of reset as soon as possible (needed for Hooper) */ qrio_prst(ZL30158_RST, false, false); @@ -158,8 +158,8 @@ int misc_init_f(void) qrio_prstcfg(ETH_FRONT_PHY_RST, PRSTCFG_POWUP_UNIT_CORE_RST); qrio_prst(ETH_FRONT_PHY_RST, false, false); - /* set the ZL30343 prstcfg to reset at power-up and unit reset only */ - qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_UNIT_RST); + /* set the ZL30343 prstcfg to reset at power-up only */ + qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST); /* and enable the WD on it */ qrio_wdmask(ZL30343_RST, true); diff --git a/board/psyent/common/AMDLV065D.c b/board/psyent/common/AMDLV065D.c deleted file mode 100644 index 64cb97029e..0000000000 --- a/board/psyent/common/AMDLV065D.c +++ /dev/null @@ -1,170 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include <common.h> -#include <asm/io.h> - -#define SECTSZ (64 * 1024) -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/*----------------------------------------------------------------------*/ -unsigned long flash_init (void) -{ - int i; - unsigned long addr; - flash_info_t *fli = &flash_info[0]; - - fli->size = CONFIG_SYS_FLASH_SIZE; - fli->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D; - - addr = CONFIG_SYS_FLASH_BASE; - for (i = 0; i < fli->sector_count; ++i) { - fli->start[i] = addr; - addr += SECTSZ; - fli->protect[i] = 1; - } - - return (CONFIG_SYS_FLASH_SIZE); -} -/*--------------------------------------------------------------------*/ -void flash_print_info (flash_info_t * info) -{ - int i, k; - int erased; - unsigned long *addr; - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - - /* Check if whole sector is erased */ - erased = 1; - addr = (unsigned long *) info->start[i]; - for (k = 0; k < SECTSZ/sizeof(unsigned long); k++) { - if ( readl(addr++) != (unsigned long)-1) { - erased = 0; - break; - } - } - - /* Print the info */ - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s%s", - info->start[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " "); - } - printf ("\n"); -} - -/*-------------------------------------------------------------------*/ - - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - unsigned char *addr = (unsigned char *) info->start[0]; - unsigned char *addr2; - int prot, sect; - ulong start; - - /* Some sanity checking */ - if ((s_first < 0) || (s_first > s_last)) { - printf ("- no sectors to erase\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* It's ok to erase multiple sectors provided we don't delay more - * than 50 usec between cmds ... at which point the erase time-out - * occurs. So don't go and put printf() calls in the loop ... it - * won't be very helpful ;-) - */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (unsigned char *) info->start[sect]; - writeb (0xaa, addr); - writeb (0x55, addr); - writeb (0x80, addr); - writeb (0xaa, addr); - writeb (0x55, addr); - writeb (0x30, addr2); - /* Now just wait for 0xff & provide some user - * feedback while we wait. - */ - start = get_timer (0); - while ( readb (addr2) != 0xff) { - udelay (1000 * 1000); - putc ('.'); - if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("timeout\n"); - return 1; - } - } - } - } - printf ("\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - - vu_char *cmd = (vu_char *) info->start[0]; - vu_char *dst = (vu_char *) addr; - unsigned char b; - ulong start; - - while (cnt) { - /* Check for sufficient erase */ - b = *src; - if ((readb (dst) & b) != b) { - printf ("%02x : %02x\n", readb (dst), b); - return (2); - } - - writeb (0xaa, cmd); - writeb (0x55, cmd); - writeb (0xa0, cmd); - writeb (dst, b); - - /* Verify write */ - start = get_timer (0); - while (readb (dst) != b) { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return 1; - } - } - dst++; - src++; - cnt--; - } - - return (0); -} diff --git a/board/psyent/pci5441/Kconfig b/board/psyent/pci5441/Kconfig deleted file mode 100644 index d722f31e2d..0000000000 --- a/board/psyent/pci5441/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_PCI5441 - -config SYS_BOARD - string - default "pci5441" - -config SYS_VENDOR - string - default "psyent" - -config SYS_CONFIG_NAME - string - default "PCI5441" - -endif diff --git a/board/psyent/pci5441/MAINTAINERS b/board/psyent/pci5441/MAINTAINERS deleted file mode 100644 index f1f10e9193..0000000000 --- a/board/psyent/pci5441/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -PCI5441 BOARD -M: Scott McNutt <smcnutt@psyent.com> -S: Maintained -F: board/psyent/pci5441/ -F: include/configs/PCI5441.h -F: configs/PCI5441_defconfig diff --git a/board/psyent/pci5441/Makefile b/board/psyent/pci5441/Makefile deleted file mode 100644 index 364f163e4f..0000000000 --- a/board/psyent/pci5441/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := pci5441.o ../common/AMDLV065D.o diff --git a/board/psyent/pci5441/config.mk b/board/psyent/pci5441/config.mk deleted file mode 100644 index 776fa8ab40..0000000000 --- a/board/psyent/pci5441/config.mk +++ /dev/null @@ -1,14 +0,0 @@ -# -# (C) Copyright 2004, Psyent Corporation <www.psyent.com> -# Scott McNutt <smcnutt@psyent.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0x018e0000 - -PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif diff --git a/board/psyent/pci5441/pci5441.c b/board/psyent/pci5441/pci5441.c deleted file mode 100644 index 6d619e5128..0000000000 --- a/board/psyent/pci5441/pci5441.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt@psyent.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -int board_early_init_f (void) -{ - return 0; -} - -int checkboard (void) -{ - puts ("BOARD : Psyent PCI-5441\n"); - return 0; -} - -phys_size_t initdram (int board_type) -{ - return (0); -} diff --git a/board/psyent/pk1c20/Kconfig b/board/psyent/pk1c20/Kconfig deleted file mode 100644 index 75f6cd1e52..0000000000 --- a/board/psyent/pk1c20/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_PK1C20 - -config SYS_BOARD - string - default "pk1c20" - -config SYS_VENDOR - string - default "psyent" - -config SYS_CONFIG_NAME - string - default "PK1C20" - -endif diff --git a/board/psyent/pk1c20/MAINTAINERS b/board/psyent/pk1c20/MAINTAINERS deleted file mode 100644 index 32b901ab9c..0000000000 --- a/board/psyent/pk1c20/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -PK1C20 BOARD -M: Scott McNutt <smcnutt@psyent.com> -S: Maintained -F: board/psyent/pk1c20/ -F: include/configs/PK1C20.h -F: configs/PK1C20_defconfig diff --git a/board/psyent/pk1c20/Makefile b/board/psyent/pk1c20/Makefile deleted file mode 100644 index 5450f93ac3..0000000000 --- a/board/psyent/pk1c20/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := pk1c20.o led.o ../common/AMDLV065D.o diff --git a/board/psyent/pk1c20/config.mk b/board/psyent/pk1c20/config.mk deleted file mode 100644 index 83cfadc113..0000000000 --- a/board/psyent/pk1c20/config.mk +++ /dev/null @@ -1,14 +0,0 @@ -# -# (C) Copyright 2004, Psyent Corporation <www.psyent.com> -# Scott McNutt <smcnutt@psyent.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0x01fc0000 - -PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif diff --git a/board/psyent/pk1c20/led.c b/board/psyent/pk1c20/led.c deleted file mode 100644 index 580d590f2a..0000000000 --- a/board/psyent/pk1c20/led.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt@psyent.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <nios2-io.h> -#include <status_led.h> - -/* The LED port is configured as output only, so we - * must track the state manually. - */ -static led_id_t val = 0; - -void __led_init (led_id_t mask, int state) -{ - nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; - - if (state == STATUS_LED_ON) - val &= ~mask; - else - val |= mask; - writel (val, &pio->data); -} - -void __led_set (led_id_t mask, int state) -{ - nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; - - if (state == STATUS_LED_ON) - val &= ~mask; - else - val |= mask; - writel (val, &pio->data); -} - -void __led_toggle (led_id_t mask) -{ - nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; - - val ^= mask; - writel (val, &pio->data); -} diff --git a/board/psyent/pk1c20/pk1c20.c b/board/psyent/pk1c20/pk1c20.c deleted file mode 100644 index 0b4c9f8ac1..0000000000 --- a/board/psyent/pk1c20/pk1c20.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt@psyent.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <netdev.h> - -int board_early_init_f (void) -{ - return 0; -} - -int checkboard (void) -{ - puts ("BOARD : Psyent PK-1C20\n"); - return 0; -} - -phys_size_t initdram (int board_type) -{ - return (0); -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif diff --git a/board/samsung/common/Makefile b/board/samsung/common/Makefile index 41d0cc3814..93347ef000 100644 --- a/board/samsung/common/Makefile +++ b/board/samsung/common/Makefile @@ -6,7 +6,7 @@ # obj-$(CONFIG_SOFT_I2C_MULTI_BUS) += multi_i2c.o -obj-$(CONFIG_THOR_FUNCTION) += thor.o +obj-$(CONFIG_USBDOWNLOAD_GADGET) += gadget.o obj-$(CONFIG_MISC_COMMON) += misc.o ifndef CONFIG_SPL_BUILD diff --git a/board/samsung/common/thor.c b/board/samsung/common/gadget.c index 1c7630df08..6a1e57f164 100644 --- a/board/samsung/common/thor.c +++ b/board/samsung/common/gadget.c @@ -13,6 +13,9 @@ int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) if (!strcmp(name, "usb_dnl_thor")) { put_unaligned(CONFIG_G_DNL_THOR_VENDOR_NUM, &dev->idVendor); put_unaligned(CONFIG_G_DNL_THOR_PRODUCT_NUM, &dev->idProduct); + } else if (!strcmp(name, "usb_dnl_ums")) { + put_unaligned(CONFIG_G_DNL_UMS_VENDOR_NUM, &dev->idVendor); + put_unaligned(CONFIG_G_DNL_UMS_PRODUCT_NUM, &dev->idProduct); } else { put_unaligned(CONFIG_G_DNL_VENDOR_NUM, &dev->idVendor); put_unaligned(CONFIG_G_DNL_PRODUCT_NUM, &dev->idProduct); diff --git a/board/sixnet/Kconfig b/board/sixnet/Kconfig deleted file mode 100644 index 2c1b995cde..0000000000 --- a/board/sixnet/Kconfig +++ /dev/null @@ -1,11 +0,0 @@ -if TARGET_SXNI855T - -config SYS_BOARD - string - default "sixnet" - -config SYS_CONFIG_NAME - string - default "SXNI855T" - -endif diff --git a/board/sixnet/MAINTAINERS b/board/sixnet/MAINTAINERS deleted file mode 100644 index eedb409a44..0000000000 --- a/board/sixnet/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -SIXNET BOARD -M: Dave Ellis <DGE@sixnetio.com> -S: Orphan (since 2014-06) -F: board/sixnet/ -F: include/configs/SXNI855T.h -F: configs/SXNI855T_defconfig diff --git a/board/sixnet/Makefile b/board/sixnet/Makefile deleted file mode 100644 index 25a8d69536..0000000000 --- a/board/sixnet/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = sixnet.o flash.o diff --git a/board/sixnet/flash.c b/board/sixnet/flash.c deleted file mode 100644 index 75bc3eb3d3..0000000000 --- a/board/sixnet/flash.c +++ /dev/null @@ -1,774 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> -/* environment.h defines the various CONFIG_ENV_... values in terms - * of whichever ones are given in the configuration file. - */ -#include <environment.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it - * has nothing to do with the flash chip being 8-bit or 16-bit. - */ -#ifdef CONFIG_FLASH_16BIT -typedef unsigned short FLASH_PORT_WIDTH; -typedef volatile unsigned short FLASH_PORT_WIDTHV; -#define FLASH_ID_MASK 0xFFFF -#else -typedef unsigned long FLASH_PORT_WIDTH; -typedef volatile unsigned long FLASH_PORT_WIDTHV; -#define FLASH_ID_MASK 0xFFFFFFFF -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define ORMASK(size) ((-size) & OR_AM_MSK) - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(FPWV *addr, flash_info_t *info); -static void flash_reset(flash_info_t *info); -static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data); -static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); -static void flash_get_offsets(ulong base, flash_info_t *info); -#ifdef CONFIG_SYS_FLASH_PROTECTION -static void flash_sync_real_protect(flash_info_t *info); -#endif - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b; - int i; - - /* Init: no FLASHes known */ - for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - size_b = flash_get_size((FPW *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_info[0].size = size_b; - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx\n",size_b); - } - - /* Remap FLASH according to real size, so only at proper address */ - memctl->memc_or0 = (memctl->memc_or0 & ~OR_AM_MSK) | ORMASK(size_b); - - /* Do this again (was done already in flast_get_size), just - * in case we move it when remap the FLASH. - */ - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#ifdef CONFIG_SYS_FLASH_PROTECTION - /* read the hardware protection status (if any) into the - * protection array in flash_info. - */ - flash_sync_real_protect(&flash_info[0]); -#endif - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_ADDR - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_ADDR_REDUND - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - return (size_b); -} - -/*----------------------------------------------------------------------- - */ -static void flash_reset(flash_info_t *info) -{ - FPWV *base = (FPWV *)(info->start[0]); - - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - *base = (FPW)0x00FF00FF; /* Intel Read Mode */ - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - *base = (FPW)0x00F000F0; /* AMD Read Mode */ -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL - && (info->flash_id & FLASH_BTYPE)) { - int bootsect_size; /* number of bytes/boot sector */ - int sect_size; /* number of bytes/regular sector */ - - bootsect_size = 0x00002000 * (sizeof(FPW)/2); - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set sector offsets for bottom boot block type */ - for (i = 0; i < 8; ++i) { - info->start[i] = base + (i * bootsect_size); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i - 7) * sect_size); - } - } - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD - && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) { - - int sect_size; /* number of bytes/sector */ - - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set up sector start address table (uniform sector type) */ - for( i = 0; i < info->sector_count; i++ ) - info->start[i] = base + (i * sect_size); - } - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD - && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM800T) { - - int sect_size; /* number of bytes/sector */ - - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set up sector start address table (top boot sector type) */ - for (i = 0; i < info->sector_count - 3; i++) - info->start[i] = base + (i * sect_size); - i = info->sector_count - 1; - info->start[i--] = base + (info->size - 0x00004000) * (sizeof(FPW)/2); - info->start[i--] = base + (info->size - 0x00006000) * (sizeof(FPW)/2); - info->start[i--] = base + (info->size - 0x00008000) * (sizeof(FPW)/2); - } -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - uchar *boottype; - uchar *bootletter; - char *fmt; - uchar botbootletter[] = "B"; - uchar topbootletter[] = "T"; - uchar botboottype[] = "bottom boot sector"; - uchar topboottype[] = "top boot sector"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - /* check for top or bottom boot, if it applies */ - if (info->flash_id & FLASH_BTYPE) { - boottype = botboottype; - bootletter = botbootletter; - } - else { - boottype = topboottype; - bootletter = topbootletter; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM800T: - fmt = "29LV800B%s (8 Mbit, %s)\n"; - break; - case FLASH_AM640U: - fmt = "29LV641D (64 Mbit, uniform sectors)\n"; - break; - case FLASH_28F800C3B: - case FLASH_28F800C3T: - fmt = "28F800C3%s (8 Mbit, %s)\n"; - break; - case FLASH_INTEL800B: - case FLASH_INTEL800T: - fmt = "28F800B3%s (8 Mbit, %s)\n"; - break; - case FLASH_28F160C3B: - case FLASH_28F160C3T: - fmt = "28F160C3%s (16 Mbit, %s)\n"; - break; - case FLASH_INTEL160B: - case FLASH_INTEL160T: - fmt = "28F160B3%s (16 Mbit, %s)\n"; - break; - case FLASH_28F320C3B: - case FLASH_28F320C3T: - fmt = "28F320C3%s (32 Mbit, %s)\n"; - break; - case FLASH_INTEL320B: - case FLASH_INTEL320T: - fmt = "28F320B3%s (32 Mbit, %s)\n"; - break; - case FLASH_28F640C3B: - case FLASH_28F640C3T: - fmt = "28F640C3%s (64 Mbit, %s)\n"; - break; - case FLASH_INTEL640B: - case FLASH_INTEL640T: - fmt = "28F640B3%s (64 Mbit, %s)\n"; - break; - default: - fmt = "Unknown Chip Type\n"; - break; - } - - printf (fmt, bootletter, boottype); - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) { - printf ("\n "); - } - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -ulong flash_get_size (FPWV *addr, flash_info_t *info) -{ - /* Write auto select command: read Manufacturer ID */ - - /* Write auto select command sequence and test FLASH answer */ - addr[0x0555] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ - addr[0x02AA] = (FPW)0x00550055; /* for AMD, Intel ignores this */ - addr[0x0555] = (FPW)0x00900090; /* selects Intel or AMD */ - - /* The manufacturer codes are only 1 byte, so just use 1 byte. - * This works for any bus width and any FLASH device width. - */ - switch (addr[0] & 0xff) { - - case (uchar)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case (uchar)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ - if (info->flash_id != FLASH_UNKNOWN) switch (addr[1]) { - - case (FPW)AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000 * (sizeof(FPW)/2); - break; /* => 1 or 2 MiB */ - - case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */ - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - case (FPW)INTEL_ID_28F800C3B: - info->flash_id += FLASH_28F800C3B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof(FPW)/2); - break; /* => 1 or 2 MB */ - - case (FPW)INTEL_ID_28F800B3B: - info->flash_id += FLASH_INTEL800B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof(FPW)/2); - break; /* => 1 or 2 MB */ - - case (FPW)INTEL_ID_28F160C3B: - info->flash_id += FLASH_28F160C3B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof(FPW)/2); - break; /* => 2 or 4 MB */ - - case (FPW)INTEL_ID_28F160B3B: - info->flash_id += FLASH_INTEL160B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof(FPW)/2); - break; /* => 2 or 4 MB */ - - case (FPW)INTEL_ID_28F320C3B: - info->flash_id += FLASH_28F320C3B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; /* => 4 or 8 MB */ - - case (FPW)INTEL_ID_28F320B3B: - info->flash_id += FLASH_INTEL320B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; /* => 4 or 8 MB */ - - case (FPW)INTEL_ID_28F640C3B: - info->flash_id += FLASH_28F640C3B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - case (FPW)INTEL_ID_28F640B3B: - info->flash_id += FLASH_INTEL640B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* => no or unknown flash */ - } - - flash_get_offsets((ulong)addr, info); - - /* Put FLASH back in read mode */ - flash_reset(info); - - return (info->size); -} - -#ifdef CONFIG_SYS_FLASH_PROTECTION -/*----------------------------------------------------------------------- - */ - -static void flash_sync_real_protect(flash_info_t *info) -{ - FPWV *addr = (FPWV *)(info->start[0]); - FPWV *sect; - int i; - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F800C3B: - case FLASH_28F800C3T: - case FLASH_28F160C3B: - case FLASH_28F160C3T: - case FLASH_28F320C3B: - case FLASH_28F320C3T: - case FLASH_28F640C3B: - case FLASH_28F640C3T: - /* check for protected sectors */ - *addr = (FPW)0x00900090; - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02. - * D0 = 1 for each device if protected. - * If at least one device is protected the sector is marked - * protected, but mixed protected and unprotected devices - * within a sector should never happen. - */ - sect = (FPWV *)(info->start[i]); - info->protect[i] = (sect[2] & (FPW)(0x00010001)) ? 1 : 0; - } - - /* Put FLASH back in read mode */ - flash_reset(info); - break; - - case FLASH_AM640U: - case FLASH_AM800T: - default: - /* no hardware protect that we support */ - break; - } -} -#endif - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - FPWV *addr; - int flag, prot, sect; - int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_INTEL800B: - case FLASH_INTEL160B: - case FLASH_INTEL320B: - case FLASH_INTEL640B: - case FLASH_28F800C3B: - case FLASH_28F160C3B: - case FLASH_28F320C3B: - case FLASH_28F640C3B: - case FLASH_AM640U: - case FLASH_AM800T: - break; - case FLASH_UNKNOWN: - default: - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer(0); - last = start; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last && rcode == 0; sect++) { - - if (info->protect[sect] != 0) /* protected, skip it */ - continue; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr = (FPWV *)(info->start[sect]); - if (intel) { - *addr = (FPW)0x00500050; /* clear status register */ - *addr = (FPW)0x00200020; /* erase setup */ - *addr = (FPW)0x00D000D0; /* erase confirm */ - } - else { - /* must be AMD style if not Intel */ - FPWV *base; /* first address in bank */ - - base = (FPWV *)(info->start[0]); - base[0x0555] = (FPW)0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW)0x00550055; /* unlock */ - base[0x0555] = (FPW)0x00800080; /* erase mode */ - base[0x0555] = (FPW)0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW)0x00550055; /* unlock */ - *addr = (FPW)0x00300030; /* erase sector */ - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 50us for AMD, 80us for Intel. - * Let's wait 1 ms. - */ - udelay (1000); - - while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - - if (intel) { - /* suspend erase */ - *addr = (FPW)0x00B000B0; - } - - flash_reset(info); /* reset to read mode */ - rcode = 1; /* failed */ - break; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - flash_reset(info); /* reset to read mode */ - } - - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ - int bytes; /* number of bytes to program in current word */ - int left; /* number of bytes left to program */ - int i, res; - - for (left = cnt, res = 0; - left > 0 && res == 0; - addr += sizeof(data), left -= sizeof(data) - bytes) { - - bytes = addr & (sizeof(data) - 1); - addr &= ~(sizeof(data) - 1); - - /* combine source and destination data so can program - * an entire word of 16 or 32 bits - */ - for (i = 0; i < sizeof(data); i++) { - data <<= 8; - if (i < bytes || i - bytes >= left ) - data += *((uchar *)addr + i); - else - data += *src++; - } - - /* write one word to the flash */ - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - res = write_word_amd(info, (FPWV *)addr, data); - break; - case FLASH_MAN_INTEL: - res = write_word_intel(info, (FPWV *)addr, data); - break; - default: - /* unknown flash type, error! */ - printf ("missing or unknown FLASH type\n"); - res = 1; /* not really a timeout, but gives error */ - break; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - FPWV *base; /* first address in flash bank */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - - base = (FPWV *)(info->start[0]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - base[0x0555] = (FPW)0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW)0x00550055; /* unlock */ - base[0x0555] = (FPW)0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - /* data polling for D7 */ - while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00F000F0; /* reset bank */ - res = 1; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for Intel FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *dest = (FPW)0x00500050; /* clear status register */ - *dest = (FPW)0x00FF00FF; /* make sure in read mode */ - *dest = (FPW)0x00400040; /* program setup */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00B000B0; /* Suspend program */ - res = 1; - } - } - - if (res == 0 && (*dest & (FPW)0x00100010)) - res = 1; /* write failed, time out error is close enough */ - - *dest = (FPW)0x00500050; /* clear status register */ - *dest = (FPW)0x00FF00FF; /* make sure in read mode */ - - return (res); -} - -#ifdef CONFIG_SYS_FLASH_PROTECTION -/*----------------------------------------------------------------------- - */ -int flash_real_protect (flash_info_t * info, long sector, int prot) -{ - int rcode = 0; /* assume success */ - FPWV *addr; /* address of sector */ - FPW value; - - addr = (FPWV *) (info->start[sector]); - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F800C3B: - case FLASH_28F800C3T: - case FLASH_28F160C3B: - case FLASH_28F160C3T: - case FLASH_28F320C3B: - case FLASH_28F320C3T: - case FLASH_28F640C3B: - case FLASH_28F640C3T: - flash_reset (info); /* make sure in read mode */ - *addr = (FPW) 0x00600060L; /* lock command setup */ - if (prot) - *addr = (FPW) 0x00010001L; /* lock sector */ - else - *addr = (FPW) 0x00D000D0L; /* unlock sector */ - flash_reset (info); /* reset to read mode */ - - /* now see if it really is locked/unlocked as requested */ - *addr = (FPW) 0x00900090; - /* read sector protection at sector address, (A7 .. A0) = 0x02. - * D0 = 1 for each device if protected. - * If at least one device is protected the sector is marked - * protected, but return failure. Mixed protected and - * unprotected devices within a sector should never happen. - */ - value = addr[2] & (FPW) 0x00010001; - if (value == 0) - info->protect[sector] = 0; - else if (value == (FPW) 0x00010001) - info->protect[sector] = 1; - else { - /* error, mixed protected and unprotected */ - rcode = 1; - info->protect[sector] = 1; - } - if (info->protect[sector] != prot) - rcode = 1; /* failed to protect/unprotect as requested */ - - /* reload all protection bits from hardware for now */ - flash_sync_real_protect (info); - break; - - case FLASH_AM640U: - case FLASH_AM800T: - default: - /* no hardware protect that we support */ - info->protect[sector] = prot; - break; - } - - return rcode; -} -#endif diff --git a/board/sixnet/fpgadata.c b/board/sixnet/fpgadata.c deleted file mode 100644 index 2d3a7b3358..0000000000 --- a/board/sixnet/fpgadata.c +++ /dev/null @@ -1,1719 +0,0 @@ - 0xff, 0x87, 0xff, 0x88, 0x7f, 0xff, 0xf9, 0xff, - 0xff, 0xf5, 0xff, 0x8f, 0xff, 0xf0, 0x8f, 0xf9, - 0xff, 0xef, 0xff, 0xff, 0xff, - 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0x9f, 0xff, 0xf4, 0xb7, 0xfd, 0xff, 0xfe, 0x8f, - 0xbf, 0x71, 0x1f, 0xff, 0x7f, - 0xff, 0xfd, 0x87, 0x87, 0xf0, 0x70, 0x1f, 0xf7, - 0xbf, 0xff, 0xff, 0xff, 0x8f, 0x0f, 0x71, 0x81, - 0xbf, 0x3e, 0x7f, 0x7f, 0xff, - 0xff, 0xff, 0xff, 0xff, 0x8f, 0xff, 0x7f, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xf1, 0xff, 0xff, 0xff, 0xff, - 0xbf, 0xff, 0x07, 0xff, 0xf0, 0xff, 0xff, 0xff, - 0xfe, 0xff, 0xff, 0xf7, 0x8d, 0x7f, 0xf1, 0xff, - 0xff, 0x9f, 0x6f, 0xf1, 0xff, - 0xbf, 0x71, 0x87, 0xfe, 0xf0, 0x8f, 0x8f, 0xf0, - 0xfb, 0xcb, 0xff, 0xf0, 0x8f, 0x7f, 0xf1, 0x8f, - 0x1e, 0xe1, 0x7e, 0x91, 0x7f, - 0xbf, 0x1a, 0xff, 0x71, 0xff, 0x9f, 0x8f, 0xf6, - 0xf8, 0xdf, 0xf7, 0xf4, 0xff, 0xff, 0xff, 0x8f, - 0x1f, 0xf0, 0x7f, 0x97, 0xff, - 0xbf, 0x97, 0xff, 0xfb, 0xbf, 0xdf, 0xff, 0xf7, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xaf, 0xdf, - 0xf9, 0xff, 0xff, 0xff, 0xff, - 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xdf, 0xff, 0xf1, 0xff, - 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0xff, 0xff, 0xff, 0x8f, 0x7f, - 0xbf, 0xff, 0xf8, 0xf7, 0xff, 0xa7, 0xff, 0xf0, - 0xff, 0xff, 0x8f, 0xfe, 0xf0, 0xff, 0xff, 0x8f, - 0x7f, 0xf1, 0xff, 0xff, 0xcf, - 0xff, 0xff, 0xf7, 0x9f, 0xf7, 0xf3, 0xff, 0xff, - 0xff, 0xff, 0x7f, 0xff, 0xff, 0xbf, 0x7f, 0xf9, - 0xff, 0xfe, 0xff, 0xff, 0xdf, - 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0x7f, - 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xbf, 0xbf, - 0xff, 0xff, 0xff, 0xaf, 0xff, 0xf0, 0xff, 0xff, - 0x9f, 0xfe, 0xf1, 0xff, 0xff, 0xcf, 0x7f, 0xf1, - 0xff, 0xff, 0xdf, 0xff, 0xf1, - 0xbf, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0x8f, 0xff, 0xf0, 0xbf, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0x6f, - 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0x7f, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xbf, - 0xff, 0xf8, 0xff, 0xff, 0xdf, 0xff, 0xff, 0xff, - 0xff, 0x8f, 0xff, 0xf1, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xcf, 0xff, - 0xff, 0xd8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0x8f, 0xef, 0xe0, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0x8f, 0x3f, - 0xff, 0xdf, 0xf7, 0xff, 0x0f, 0xfe, 0xf0, 0xff, - 0xff, 0xff, 0xff, 0xef, 0xff, 0xdf, 0x8e, 0x7f, - 0xf1, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xbf, 0xbf, 0xff, 0xff, 0xff, - 0xff, 0xff, 0x8f, 0xff, 0xf1, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xef, 0xff, 0xbf, 0x7f, 0xe1, 0xff, - 0xdf, 0xff, 0x7f, 0xff, 0xbf, - 0xff, 0xa7, 0xff, 0x88, 0xff, 0xf1, 0xfe, 0xff, - 0xff, 0xff, 0xff, 0x1f, 0xff, 0xf0, 0xcf, 0xb1, - 0xff, 0xef, 0xff, 0x7f, 0xff, diff --git a/board/sixnet/sixnet.c b/board/sixnet/sixnet.c deleted file mode 100644 index 06b2083558..0000000000 --- a/board/sixnet/sixnet.c +++ /dev/null @@ -1,578 +0,0 @@ -/* - * (C) Copyright 2001, 2002 - * Dave Ellis, SIXNET, dge@sixnetio.com. - * Based on code by: - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * and other contributors to U-Boot. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <config.h> -#include <jffs2/jffs2.h> -#include <mpc8xx.h> -#include <net.h> /* for eth_init() */ -#include <rtc.h> -#include "sixnet.h" -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include <status_led.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#define ORMASK(size) ((-size) & OR_AM_MSK) - -static long ram_size(ulong *, long); - -/* ------------------------------------------------------------------------- */ - -#ifdef CONFIG_SHOW_BOOT_PROGRESS -void show_boot_progress (int status) -{ -#if defined(CONFIG_STATUS_LED) -# if defined(STATUS_LED_BOOT) - if (status == BOOTSTAGE_ID_RUN_OS) { - /* ready to transfer to kernel, make sure LED is proper state */ - status_led_set(STATUS_LED_BOOT, CONFIG_BOOT_LED_STATE); - } -# endif /* STATUS_LED_BOOT */ -#endif /* CONFIG_STATUS_LED */ -} -#endif - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - * returns 0 if recognized, -1 if unknown - */ - -int checkboard (void) -{ - puts ("Board: SIXNET SXNI855T\n"); - return 0; -} - -/* ------------------------------------------------------------------------- */ - -#if defined(CONFIG_CMD_PCMCIA) -#error "SXNI855T has no PCMCIA port" -#endif - -/* ------------------------------------------------------------------------- */ - -#define _not_used_ 0xffffffff - -/* UPMB table for dual UART. */ - -/* this table is for 50MHz operation, it should work at all lower speeds */ -const uint duart_table[] = -{ - /* single read. (offset 0 in upm RAM) */ - 0xfffffc04, 0x0ffffc04, 0x0ff3fc04, 0x0ff3fc04, - 0x0ff3fc00, 0x0ff3fc04, 0xfffffc04, 0xfffffc05, - - /* burst read. (offset 8 in upm RAM) */ - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* single write. (offset 18 in upm RAM) */ - 0xfffffc04, 0x0ffffc04, 0x00fffc04, 0x00fffc04, - 0x00fffc04, 0x00fffc00, 0xfffffc04, 0xfffffc05, - - /* burst write. (offset 20 in upm RAM) */ - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* refresh. (offset 30 in upm RAM) */ - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* exception. (offset 3c in upm RAM) */ - _not_used_, _not_used_, _not_used_, _not_used_, -}; - -/* Load FPGA very early in boot sequence, since it must be - * loaded before the 16C2550 serial channels can be used as - * console channels. - * - * Note: Much of the configuration is not complete. The - * stack is in DPRAM since SDRAM has not been initialized, - * so the stack must be kept small. Global variables - * are still in FLASH, so they cannot be written. - * Only the FLASH, DPRAM, immap and FPGA can be addressed, - * the other chip selects may not have been initialized. - * The clocks have been initialized, so udelay() can be - * used. - */ -#define FPGA_DONE 0x0080 /* PA8, input, high when FPGA load complete */ -#define FPGA_PROGRAM_L 0x0040 /* PA9, output, low to reset, high to start */ -#define FPGA_INIT_L 0x0020 /* PA10, input, low indicates not ready */ -#define fpga (*(volatile unsigned char *)(CONFIG_SYS_FPGA_PROG)) /* FPGA port */ - -int board_postclk_init (void) -{ - - /* the data to load to the XCSxxXL FPGA */ - static const unsigned char fpgadata[] = { -# include "fpgadata.c" - }; - - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; -#define porta (immap->im_ioport.iop_padat) - const unsigned char* pdata; - - /* /INITFPGA and DONEFPGA signals are inputs */ - immap->im_ioport.iop_padir &= ~(FPGA_INIT_L | FPGA_DONE); - - /* Force output pin to begin at 0, /PROGRAM asserted (0) resets FPGA */ - porta &= ~FPGA_PROGRAM_L; - - /* Set FPGA as an output */ - immap->im_ioport.iop_padir |= FPGA_PROGRAM_L; - - /* delay a little to make sure FPGA sees it, really - * only need less than a microsecond. - */ - udelay(10); - - /* unassert /PROGRAM */ - porta |= FPGA_PROGRAM_L; - - /* delay while FPGA does last erase, indicated by - * /INITFPGA going high. This should happen within a - * few milliseconds. - */ - /* ### FIXME - a timeout check would be good, maybe flash - * the status LED to indicate the error? - */ - while ((porta & FPGA_INIT_L) == 0) - ; /* waiting */ - - /* write program data to FPGA at the programming address - * so extra /CS1 strobes at end of configuration don't actually - * write to any registers. - */ - fpga = 0xff; /* first write is ignored */ - fpga = 0xff; /* fill byte */ - fpga = 0xff; /* fill byte */ - fpga = 0x4f; /* preamble code */ - fpga = 0x80; fpga = 0xaf; fpga = 0x9b; /* length (ignored) */ - fpga = 0x4b; /* field check code */ - - pdata = fpgadata; - /* while no error write out each of the 28 byte frames */ - while ((porta & (FPGA_INIT_L | FPGA_DONE)) == FPGA_INIT_L - && pdata < fpgadata + sizeof(fpgadata)) { - - fpga = 0x4f; /* preamble code */ - - /* 21 bytes of data in a frame */ - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); - - fpga = 0x4b; /* field check code */ - fpga = 0xff; /* extended write cycle */ - fpga = 0x4b; /* extended write cycle - * (actually 0x4b from bitgen.exe) - */ - fpga = 0xff; /* extended write cycle */ - fpga = 0xff; /* extended write cycle */ - fpga = 0xff; /* extended write cycle */ - } - - fpga = 0xff; /* startup byte */ - fpga = 0xff; /* startup byte */ - fpga = 0xff; /* startup byte */ - fpga = 0xff; /* startup byte */ - -#if 0 /* ### FIXME */ - /* If didn't load all the data or FPGA_DONE is low the load failed. - * Maybe someday stop here and flash the status LED? The console - * is not configured, so can't print an error message. Can't write - * global variables to set a flag (except gd?). - * For now it must work. - */ -#endif - - /* Now that the FPGA is loaded, set up the Dual UART chip - * selects. Must be done here since it may be used as the console. - */ - upmconfig(UPMB, (uint *)duart_table, sizeof(duart_table)/sizeof(uint)); - - memctl->memc_mbmr = DUART_MBMR; - memctl->memc_or5 = DUART_OR_VALUE; - memctl->memc_br5 = DUART_BR5_VALUE; - memctl->memc_or6 = DUART_OR_VALUE; - memctl->memc_br6 = DUART_BR6_VALUE; - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -/* base address for SRAM, assume 32-bit port, valid */ -#define NVRAM_BR_VALUE (CONFIG_SYS_SRAM_BASE | BR_PS_32 | BR_V) - -/* up to 64MB - will be adjusted for actual size */ -#define NVRAM_OR_PRELIM (ORMASK(CONFIG_SYS_SRAM_SIZE) \ - | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_EHTR) -/* - * Miscellaneous platform dependent initializations after running in RAM. - */ - -int misc_init_r (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - bd_t *bd = gd->bd; - uchar enetaddr[6]; - - memctl->memc_or2 = NVRAM_OR_PRELIM; - memctl->memc_br2 = NVRAM_BR_VALUE; - - /* Is there any SRAM? Is it 16 or 32 bits wide? */ - - /* First look for 32-bit SRAM */ - bd->bi_sramsize = ram_size((ulong*)CONFIG_SYS_SRAM_BASE, CONFIG_SYS_SRAM_SIZE); - - if (bd->bi_sramsize == 0) { - /* no 32-bit SRAM, but there could be 16-bit SRAM since - * it would report size 0 when configured for 32-bit bus. - * Try again with a 16-bit bus. - */ - memctl->memc_br2 |= BR_PS_16; - bd->bi_sramsize = ram_size((ulong*)CONFIG_SYS_SRAM_BASE, CONFIG_SYS_SRAM_SIZE); - } - - if (bd->bi_sramsize == 0) { - memctl->memc_br2 = 0; /* disable select since nothing there */ - } - else { - /* adjust or2 for actual size of SRAM */ - memctl->memc_or2 |= ORMASK(bd->bi_sramsize); - bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; - printf("SRAM: %lu KB\n", bd->bi_sramsize >> 10); - } - - - /* set standard MPC8xx clock so kernel will see the time - * even if it doesn't have a DS1306 clock driver. - * This helps with experimenting with standard kernels. - */ - { - ulong tim; - struct rtc_time tmp; - - rtc_get(&tmp); /* get time from DS1306 RTC */ - - /* convert to seconds since 1970 */ - tim = mktime(tmp.tm_year, tmp.tm_mon, tmp.tm_mday, - tmp.tm_hour, tmp.tm_min, tmp.tm_sec); - - immap->im_sitk.sitk_rtck = KAPWR_KEY; - immap->im_sit.sit_rtc = tim; - } - - /* set up ethernet address for SCC ethernet. If eth1addr - * is present it gets a unique address, otherwise it - * shares the FEC address. - */ - if (!eth_getenv_enetaddr("eth1addr", enetaddr)) { - eth_getenv_enetaddr("ethaddr", enetaddr); - eth_setenv_enetaddr("eth1addr", enetaddr); - } - - return (0); -} - -#if defined(CONFIG_CMD_NAND) -void nand_init(void) -{ - unsigned long totlen = nand_probe(CONFIG_SYS_DFLASH_BASE); - - printf ("%4lu MB\n", totlen >> 20); -} -#endif - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. - * - * The memory size MUST be a power of 2 for this to work. - * - * The only memory modified is 8 bytes at offset 0. This is important - * since for the SRAM this location is reserved for autosizing, so if - * it is modified and the board is reset before ram_size() completes - * no damage is done. Normally even the memory at 0 is preserved. The - * higher SRAM addresses may contain battery backed RAM disk data which - * must never be corrupted. - */ - -static long ram_size(ulong *base, long maxsize) -{ - volatile long *test_addr; - volatile ulong *base_addr = base; - ulong ofs; /* byte offset from base_addr */ - ulong save; /* to make test non-destructive */ - ulong save2; /* to make test non-destructive */ - long ramsize = -1; /* size not determined yet */ - - save = *base_addr; /* save value at 0 so can restore */ - save2 = *(base_addr+1); /* save value at 4 so can restore */ - - /* is any SRAM present? */ - *base_addr = 0x5555aaaa; - - /* It is important to drive the data bus with different data so - * it doesn't remember the value and look like RAM that isn't there. - */ - *(base_addr + 1) = 0xaaaa5555; /* use write to modify data bus */ - - if (*base_addr != 0x5555aaaa) - ramsize = 0; /* no RAM present, or defective */ - else { - *base_addr = 0xaaaa5555; - *(base_addr + 1) = 0x5555aaaa; /* use write to modify data bus */ - if (*base_addr != 0xaaaa5555) - ramsize = 0; /* no RAM present, or defective */ - } - - /* now size it if any is present */ - for (ofs = 4; ofs < maxsize && ramsize < 0; ofs <<= 1) { - test_addr = (long*)((long)base_addr + ofs); /* location to test */ - - *base_addr = ~*test_addr; - if (*base_addr == *test_addr) - ramsize = ofs; /* wrapped back to 0, so this is the size */ - } - - *base_addr = save; /* restore value at 0 */ - *(base_addr+1) = save2; /* restore value at 4 */ - return (ramsize); -} - -/* ------------------------------------------------------------------------- */ -/* sdram table based on the FADS manual */ -/* for chip MB811171622A-100 */ - -/* this table is for 50MHz operation, it should work at all lower speeds */ - -const uint sdram_table[] = -{ - /* single read. (offset 0 in upm RAM) */ - 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00, - 0x1ff77c47, - - /* precharge and Mode Register Set initialization (offset 5). - * This is also entered at offset 6 to do Mode Register Set - * without the precharge. - */ - 0x1ff77c34, 0xefeabc34, 0x1fb57c35, - - /* burst read. (offset 8 in upm RAM) */ - 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, - 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* single write. (offset 18 in upm RAM) */ - /* FADS had 0x1f27fc04, ... - * but most other boards have 0x1f07fc04, which - * sets GPL0 from A11MPC to 0 1/4 clock earlier, - * like the single read. - * This seems better so I am going with the change. - */ - 0x1f07fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* burst write. (offset 20 in upm RAM) */ - 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, - 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* refresh. (offset 30 in upm RAM) */ - 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc84, 0xfffffc07, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* exception. (offset 3c in upm RAM) */ - 0x7ffffc07, _not_used_, _not_used_, _not_used_ }; - -/* ------------------------------------------------------------------------- */ - -#define SDRAM_MAX_SIZE 0x10000000 /* max 256 MB SDRAM */ - -/* precharge and set Mode Register */ -#define SDRAM_MCR_PRE (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \ - MCR_MB_CS3 | /* chip select */ \ - MCR_MLCF(1) | MCR_MAD(5)) /* 1 time at 0x05 */ - -/* set Mode Register, no precharge */ -#define SDRAM_MCR_MRS (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \ - MCR_MB_CS3 | /* chip select */ \ - MCR_MLCF(1) | MCR_MAD(6)) /* 1 time at 0x06 */ - -/* runs refresh loop twice so get 8 refresh cycles */ -#define SDRAM_MCR_REFR (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \ - MCR_MB_CS3 | /* chip select */ \ - MCR_MLCF(2) | MCR_MAD(0x30)) /* twice at 0x30 */ - -/* MAMR values work in either mamr or mbmr */ -#define SDRAM_MAMR_BASE /* refresh at 50MHz */ \ - ((195 << MAMR_PTA_SHIFT) | MAMR_PTAE \ - | MAMR_DSA_1_CYCL /* 1 cycle disable */ \ - | MAMR_RLFA_1X /* Read loop 1 time */ \ - | MAMR_WLFA_1X /* Write loop 1 time */ \ - | MAMR_TLFA_4X) /* Timer loop 4 times */ -/* 8 column SDRAM */ -#define SDRAM_MAMR_8COL (SDRAM_MAMR_BASE \ - | MAMR_AMA_TYPE_0 /* Address MUX 0 */ \ - | MAMR_G0CLA_A11) /* GPL0 A11[MPC] */ - -/* 9 column SDRAM */ -#define SDRAM_MAMR_9COL (SDRAM_MAMR_BASE \ - | MAMR_AMA_TYPE_1 /* Address MUX 1 */ \ - | MAMR_G0CLA_A10) /* GPL0 A10[MPC] */ - -/* base address 0, 32-bit port, SDRAM UPM, valid */ -#define SDRAM_BR_VALUE (BR_PS_32 | BR_MS_UPMA | BR_V) - -/* up to 256MB, SAM, G5LS - will be adjusted for actual size */ -#define SDRAM_OR_PRELIM (ORMASK(SDRAM_MAX_SIZE) | OR_CSNT_SAM | OR_G5LS) - -/* This is the Mode Select Register value for the SDRAM. - * Burst length: 4 - * Burst Type: sequential - * CAS Latency: 2 - * Write Burst Length: burst - */ -#define SDRAM_MODE 0x22 /* CAS latency 2, burst length 4 */ - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram(int board_type) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - uint size_sdram = 0; - uint size_sdram9 = 0; - uint base = 0; /* SDRAM must start at 0 */ - int i; - - upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - - /* Configure the refresh (mostly). This needs to be - * based upon processor clock speed and optimized to provide - * the highest level of performance. - * - * Preliminary prescaler for refresh. - * This value is selected for four cycles in 31.2 us, - * which gives 8192 cycles in 64 milliseconds. - * This may be too fast, but works for any memory. - * It is adjusted to 4096 cycles in 64 milliseconds if - * possible once we know what memory we have. - * - * We have to be careful changing UPM registers after we - * ask it to run these commands. - * - * PTA - periodic timer period for our design is - * 50 MHz x 31.2us - * --------------- = 195 - * 1 x 8 x 1 - * - * 50MHz clock - * 31.2us refresh interval - * SCCR[DFBRG] 0 - * PTP divide by 8 - * 1 chip select - */ - memctl->memc_mptpr = MPTPR_PTP_DIV8; /* 0x0800 */ - memctl->memc_mamr = SDRAM_MAMR_8COL & (~MAMR_PTAE); /* no refresh yet */ - - /* The SDRAM Mode Register value is shifted left 2 bits since - * A30 and A31 don't connect to the SDRAM for 32-bit wide memory. - */ - memctl->memc_mar = SDRAM_MODE << 2; /* MRS code */ - udelay(200); /* SDRAM needs 200uS before set it up */ - - /* Now run the precharge/nop/mrs commands. */ - memctl->memc_mcr = SDRAM_MCR_PRE; - udelay(2); - - /* Run 8 refresh cycles (2 sets of 4) */ - memctl->memc_mcr = SDRAM_MCR_REFR; /* run refresh twice */ - udelay(2); - - /* some brands want Mode Register set after the refresh - * cycles. This shouldn't hurt anything for the brands - * that were happy with the first time we set it. - */ - memctl->memc_mcr = SDRAM_MCR_MRS; - udelay(2); - - memctl->memc_mamr = SDRAM_MAMR_8COL; /* enable refresh */ - memctl->memc_or3 = SDRAM_OR_PRELIM; - memctl->memc_br3 = SDRAM_BR_VALUE + base; - - /* Some brands need at least 10 DRAM accesses to stabilize. - * It wont hurt the brands that don't. - */ - for (i=0; i<10; ++i) { - volatile ulong *addr = (volatile ulong *)base; - ulong val; - - val = *(addr + i); - *(addr + i) = val; - } - - /* Check SDRAM memory Size in 8 column mode. - * For a 9 column memory we will get half the actual size. - */ - size_sdram = ram_size((ulong *)0, SDRAM_MAX_SIZE); - - /* Check SDRAM memory Size in 9 column mode. - * For an 8 column memory we will see at most 4 megabytes. - */ - memctl->memc_mamr = SDRAM_MAMR_9COL; - size_sdram9 = ram_size((ulong *)0, SDRAM_MAX_SIZE); - - if (size_sdram < size_sdram9) /* leave configuration at 9 columns */ - size_sdram = size_sdram9; - else /* go back to 8 columns */ - memctl->memc_mamr = SDRAM_MAMR_8COL; - - /* adjust or3 for actual size of SDRAM - */ - memctl->memc_or3 |= ORMASK(size_sdram); - - /* Adjust refresh rate depending on SDRAM type. - * For types > 128 MBit (32 Mbyte for 2 x16 devices) leave - * it at the current (fast) rate. - * For 16, 64 and 128 MBit half the rate will do. - */ - if (size_sdram <= 32 * 1024 * 1024) - memctl->memc_mptpr = MPTPR_PTP_DIV16; /* 0x0400 */ - - return (size_sdram); -} diff --git a/board/sixnet/sixnet.h b/board/sixnet/sixnet.h deleted file mode 100644 index 046c9de39e..0000000000 --- a/board/sixnet/sixnet.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Memory map: - * - * ff100000 -> ff13ffff : FPGA CS1 - * ff030000 -> ff03ffff : EXPANSION CS7 - * ff020000 -> ff02ffff : DATA FLASH CS4 - * ff018000 -> ff01ffff : UART B CS6/UPMB - * ff010000 -> ff017fff : UART A CS5/UPMB - * ff000000 -> ff00ffff : IMAP internal to the MPC855T - * f8000000 -> fbffffff : FLASH CS0 up to 64MB - * f4000000 -> f7ffffff : NVSRAM CS2 up to 64MB - * 00000000 -> 0fffffff : SDRAM CS3/UPMA up to 256MB - */ diff --git a/board/sixnet/u-boot.lds b/board/sixnet/u-boot.lds deleted file mode 100644 index 7ee2012c41..0000000000 --- a/board/sixnet/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/stx/stxxtc/Kconfig b/board/stx/stxxtc/Kconfig deleted file mode 100644 index c444cff759..0000000000 --- a/board/stx/stxxtc/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_STXXTC - -config SYS_BOARD - string - default "stxxtc" - -config SYS_VENDOR - string - default "stx" - -config SYS_CONFIG_NAME - string - default "stxxtc" - -endif diff --git a/board/stx/stxxtc/MAINTAINERS b/board/stx/stxxtc/MAINTAINERS deleted file mode 100644 index 5ea36b225d..0000000000 --- a/board/stx/stxxtc/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -STXXTC BOARD -M: Dan Malek <dan@embeddedalley.com> -S: Orphan (since 2014-06) -F: board/stx/stxxtc/ -F: include/configs/stxxtc.h -F: configs/stxxtc_defconfig diff --git a/board/stx/stxxtc/Makefile b/board/stx/stxxtc/Makefile deleted file mode 100644 index 6738d4e15d..0000000000 --- a/board/stx/stxxtc/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = stxxtc.o diff --git a/board/stx/stxxtc/README.stxxtc b/board/stx/stxxtc/README.stxxtc deleted file mode 100644 index 7d9d4d3a2e..0000000000 --- a/board/stx/stxxtc/README.stxxtc +++ /dev/null @@ -1,59 +0,0 @@ - - -First, some build notes on the Silicon Turnkey eXpress XTc. - -This board has both 87x/88x procesor options at various -frequencies. The configuration file has some macros for setting -the clock speed, not all have been tested. They all have -a 10MHz input clock. Please do not check in a configuration -file that selects a high speed not available on all processors. -We chose the 66MHz core and bus speed, which should be OK on -all boards. If you have a processor, lucky you! :-) -Just build a new configuration with that speed, check -the macro configuration to ensure it's correct. If the -macro is updated, please check that in, but keep default -processor speed. - -The board is likely to have more than 1Mbyte of NOR boot flash. -It was also configured with a high boot vector (Dan's fault) -so the standard 8xx mapping doesn't work well. We had to move -the addresses around a little bit so one copy would work. The -flash got fragmented, and we are working on a better solution. -There is an "xtc.cfg" floating around for the BDI2000, use -that for programming a new version of U-Boot. You can probably -find it on the Silicon Turnkey eXpress (www.silicontkx.com), -Embedded Alley Solutions (embeddedalley.com), or Denx (denx.de) -servers. - -The board will also have various SDRAM sizes, but the code -should automatically determine the amount of memory. - -There are a couple of different board versions, visually -they use different BGA or surface mount memory parts. However, -they are logically the same board. - -Now, some operational notes. - -The board has the option of sporting two FEC Ethernet ports. -The second port isn't configured to be automatically available -because it would cause U-Boot to generate a board data structure -(the bd_t) with multiple MAC addresses and be incompatible with -standard 8xx kernel builds. You can use/test the second FEC -in U-Boot by assigning an 'eth1addr' and selecting the second -FEC as the port to use. - -Since this is just a development board and not a product, STx -does not assign unique MAC addresses. We just pilfer the -"default" ones used by Wolfgang on some other boards. Please -ensure you assign unique MAC addresses when using these boards. - -The serial port baud rate is 38400, because that's the way -I like it :-) - -Thanks to Pantelis for lots of the work on this board port. - -Have Fun! - - -- Dan - -15 August 2005 diff --git a/board/stx/stxxtc/stxxtc.c b/board/stx/stxxtc/stxxtc.c deleted file mode 100644 index 1996efb664..0000000000 --- a/board/stx/stxxtc/stxxtc.c +++ /dev/null @@ -1,592 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Pantelis Antoniou, Intracom S.A., panto@intracom.gr - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * (C) Copyright 2005 - * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * U-Boot port on STx XTc board - * Mostly copied from Netta - */ - -#include <common.h> -#include <miiphy.h> - -#include "mpc8xx.h" - -#ifdef CONFIG_HW_WATCHDOG -#include <watchdog.h> -#endif - -/****************************************************************/ - -/* some sane bit macros */ -#define _BD(_b) (1U << (31-(_b))) -#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) - -#define _BW(_b) (1U << (15-(_b))) -#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1)) - -#define _BB(_b) (1U << (7-(_b))) -#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1)) - -#define _B(_b) _BD(_b) -#define _BR(_l, _h) _BDR(_l, _h) - -/****************************************************************/ - -/* - * Check Board Identity: - * - * Return 1 always. - */ - -int checkboard(void) -{ - printf ("Silicon Turnkey eXpress XTc\n"); - return (0); -} - -/****************************************************************/ - -#define _NOT_USED_ 0xFFFFFFFF - -/****************************************************************/ - -#define CS_0000 0x00000000 -#define CS_0001 0x10000000 -#define CS_0010 0x20000000 -#define CS_0011 0x30000000 -#define CS_0100 0x40000000 -#define CS_0101 0x50000000 -#define CS_0110 0x60000000 -#define CS_0111 0x70000000 -#define CS_1000 0x80000000 -#define CS_1001 0x90000000 -#define CS_1010 0xA0000000 -#define CS_1011 0xB0000000 -#define CS_1100 0xC0000000 -#define CS_1101 0xD0000000 -#define CS_1110 0xE0000000 -#define CS_1111 0xF0000000 - -#define BS_0000 0x00000000 -#define BS_0001 0x01000000 -#define BS_0010 0x02000000 -#define BS_0011 0x03000000 -#define BS_0100 0x04000000 -#define BS_0101 0x05000000 -#define BS_0110 0x06000000 -#define BS_0111 0x07000000 -#define BS_1000 0x08000000 -#define BS_1001 0x09000000 -#define BS_1010 0x0A000000 -#define BS_1011 0x0B000000 -#define BS_1100 0x0C000000 -#define BS_1101 0x0D000000 -#define BS_1110 0x0E000000 -#define BS_1111 0x0F000000 - -#define GPL0_AAAA 0x00000000 -#define GPL0_AAA0 0x00200000 -#define GPL0_AAA1 0x00300000 -#define GPL0_000A 0x00800000 -#define GPL0_0000 0x00A00000 -#define GPL0_0001 0x00B00000 -#define GPL0_111A 0x00C00000 -#define GPL0_1110 0x00E00000 -#define GPL0_1111 0x00F00000 - -#define GPL1_0000 0x00000000 -#define GPL1_0001 0x00040000 -#define GPL1_1110 0x00080000 -#define GPL1_1111 0x000C0000 - -#define GPL2_0000 0x00000000 -#define GPL2_0001 0x00010000 -#define GPL2_1110 0x00020000 -#define GPL2_1111 0x00030000 - -#define GPL3_0000 0x00000000 -#define GPL3_0001 0x00004000 -#define GPL3_1110 0x00008000 -#define GPL3_1111 0x0000C000 - -#define GPL4_0000 0x00000000 -#define GPL4_0001 0x00001000 -#define GPL4_1110 0x00002000 -#define GPL4_1111 0x00003000 - -#define GPL5_0000 0x00000000 -#define GPL5_0001 0x00000400 -#define GPL5_1110 0x00000800 -#define GPL5_1111 0x00000C00 -#define LOOP 0x00000080 - -#define EXEN 0x00000040 - -#define AMX_COL 0x00000000 -#define AMX_ROW 0x00000020 -#define AMX_MAR 0x00000030 - -#define NA 0x00000008 - -#define UTA 0x00000004 - -#define TODT 0x00000002 - -#define LAST 0x00000001 - -#define A10_AAAA GPL0_AAAA -#define A10_AAA0 GPL0_AAA0 -#define A10_AAA1 GPL0_AAA1 -#define A10_000A GPL0_000A -#define A10_0000 GPL0_0000 -#define A10_0001 GPL0_0001 -#define A10_111A GPL0_111A -#define A10_1110 GPL0_1110 -#define A10_1111 GPL0_1111 - -#define RAS_0000 GPL1_0000 -#define RAS_0001 GPL1_0001 -#define RAS_1110 GPL1_1110 -#define RAS_1111 GPL1_1111 - -#define CAS_0000 GPL2_0000 -#define CAS_0001 GPL2_0001 -#define CAS_1110 GPL2_1110 -#define CAS_1111 GPL2_1111 - -#define WE_0000 GPL3_0000 -#define WE_0001 GPL3_0001 -#define WE_1110 GPL3_1110 -#define WE_1111 GPL3_1111 - -/* #define CAS_LATENCY 3 */ -#define CAS_LATENCY 2 - -const uint sdram_table[0x40] = { - -#if CAS_LATENCY == 3 - /* RSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, - - /* RBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, -#endif - -#if CAS_LATENCY == 2 - /* RSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* RBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ - CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, - _NOT_USED_, - - /* WBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - -#endif - - /* UPT */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* EXC */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST, - _NOT_USED_, - - /* REG */ - CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA, - CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST, -}; - -static const uint nandcs_table[0x40] = { - /* RSS */ - CS_1000 | GPL4_1111 | GPL5_1111 | UTA, - CS_0000 | GPL4_1110 | GPL5_1111 | UTA, - CS_0000 | GPL4_0000 | GPL5_1111 | UTA, - CS_0000 | GPL4_0000 | GPL5_1111 | UTA, - CS_0000 | GPL4_0000 | GPL5_1111, - CS_0000 | GPL4_0001 | GPL5_1111 | UTA, - CS_0000 | GPL4_1111 | GPL5_1111 | UTA, - CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, /* NOP */ - - /* RBS */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_1000 | GPL4_1111 | GPL5_1110 | UTA, - CS_0000 | GPL4_1111 | GPL5_0000 | UTA, - CS_0000 | GPL4_1111 | GPL5_0000 | UTA, - CS_0000 | GPL4_1111 | GPL5_0000 | UTA, - CS_0000 | GPL4_1111 | GPL5_0001 | UTA, - CS_0000 | GPL4_1111 | GPL5_1111 | UTA, - CS_0000 | GPL4_1111 | GPL5_1111, - CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, - - /* WBS */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* UPT */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* EXC */ - CS_0001 | LAST, - _NOT_USED_, - - /* REG */ - CS_1110 , - CS_0001 | LAST, -}; - -/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */ -/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */ -#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU) - -/* 9 */ -#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -void check_ram(unsigned int addr, unsigned int size) -{ - unsigned int i, j, v, vv; - volatile unsigned int *p; - unsigned int pv; - - p = (unsigned int *)addr; - pv = (unsigned int)p; - for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int)) - *p++ = pv; - - p = (unsigned int *)addr; - for (i = 0; i < size / sizeof(unsigned int); i++) { - v = (unsigned int)p; - vv = *p; - if (vv != v) { - printf("%p: read %08x instead of %08x\n", p, vv, v); - hang(); - } - p++; - } - - for (j = 0; j < 5; j++) { - switch (j) { - case 0: v = 0x00000000; break; - case 1: v = 0xffffffff; break; - case 2: v = 0x55555555; break; - case 3: v = 0xaaaaaaaa; break; - default:v = 0xdeadbeef; break; - } - p = (unsigned int *)addr; - for (i = 0; i < size / sizeof(unsigned int); i++) { - *p = v; - vv = *p; - if (vv != v) { - printf("%p: read %08x instead of %08x\n", p, vv, v); - hang(); - } - *p = ~v; - p++; - } - } -} - -#define DO_LOOP do { for (;;) asm volatile ("nop" : : : "memory"); } while(0) - -phys_size_t initdram(int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size; - u32 d1, d2; - - upmconfig(UPMA, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0])); - - /* - * Preliminary prescaler for refresh - */ - memctl->memc_mptpr = MPTPR_PTP_DIV8; - - memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */ - - /* - * Map controller bank 3 to the SDRAM bank at preliminary address. - */ - memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM; - memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM; - - memctl->memc_mamr = CONFIG_SYS_MAMR & ~MAMR_PTAE; /* no refresh yet */ - - udelay(200); - - /* perform SDRAM initialisation sequence */ - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */ - udelay(1); - - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */ - udelay(1); - - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/ - udelay(1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay(10000); - - - d1 = 0xAA55AA55; - *(volatile u32 *)0 = d1; - d2 = *(volatile u32 *)0; - if (d1 != d2) { - printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); - DO_LOOP; - } - - d1 = 0x55AA55AA; - *(volatile u32 *)0 = d1; - d2 = *(volatile u32 *)0; - if (d1 != d2) { - printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); - DO_LOOP; - } - - d1 = 0x12345678; - *(volatile u32 *)0 = d1; - d2 = *(volatile u32 *)0; - if (d1 != d2) { - printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); - DO_LOOP; - } - - size = get_ram_size((long *)0, SDRAM_MAX_SIZE); - - return size; -} - -/* ------------------------------------------------------------------------- */ - -void reset_phys(void) -{ - int phyno; - unsigned short v; - - udelay(10000); - /* reset the damn phys */ - mii_init(); - - for (phyno = 0; phyno < 32; ++phyno) { - miiphy_read("FEC", phyno, MII_PHYSID1, &v); - if (v == 0xFFFF) - continue; - miiphy_write("FEC", phyno, MII_BMCR, BMCR_PDOWN); - udelay(10000); - miiphy_write("FEC", phyno, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); - udelay(10000); - } -} - -/* ------------------------------------------------------------------------- */ - -/* GP = general purpose, SP = special purpose (on chip peripheral) */ - -/* bits that can have a special purpose or can be configured as inputs/outputs */ -#define PA_GP_INMASK _BW(6) -#define PA_GP_OUTMASK (_BW(7)) -#define PA_SP_MASK 0 -#define PA_ODR_VAL 0 -#define PA_GP_OUTVAL (_BW(7)) -#define PA_SP_DIRVAL 0 - -#define PB_GP_INMASK 0 -#define PB_GP_OUTMASK (_B(23)) -#define PB_SP_MASK 0 -#define PB_ODR_VAL 0 -#define PB_GP_OUTVAL (_B(23)) -#define PB_SP_DIRVAL 0 - -#define PC_GP_INMASK 0 -#define PC_GP_OUTMASK (_BW(15)) - -#define PC_SP_MASK 0 -#define PC_SOVAL 0 -#define PC_INTVAL 0 -#define PC_GP_OUTVAL 0 -#define PC_SP_DIRVAL 0 - -#define PE_GP_INMASK 0 -#define PE_GP_OUTMASK 0 -#define PE_GP_OUTVAL 0 - -#define PE_SP_MASK 0 -#define PE_ODR_VAL 0 -#define PE_SP_DIRVAL 0 - -int board_early_init_f(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile iop8xx_t *ioport = &immap->im_ioport; - volatile cpm8xx_t *cpm = &immap->im_cpm; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - (void)ioport; - (void)cpm; -#if 1 - /* NAND chip select */ - upmconfig(UPMB, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0])); - memctl->memc_or2 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS); - memctl->memc_br2 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMB); - memctl->memc_mbmr = 0; /* all clear */ -#endif - - memctl->memc_br5 &= ~BR_V; - memctl->memc_br6 &= ~BR_V; - memctl->memc_br7 &= ~BR_V; - -#if 1 - ioport->iop_padat = PA_GP_OUTVAL; - ioport->iop_paodr = PA_ODR_VAL; - ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL; - ioport->iop_papar = PA_SP_MASK; - - cpm->cp_pbdat = PB_GP_OUTVAL; - cpm->cp_pbodr = PB_ODR_VAL; - cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL; - cpm->cp_pbpar = PB_SP_MASK; - - ioport->iop_pcdat = PC_GP_OUTVAL; - ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL; - ioport->iop_pcso = PC_SOVAL; - ioport->iop_pcint = PC_INTVAL; - ioport->iop_pcpar = PC_SP_MASK; - - cpm->cp_pedat = PE_GP_OUTVAL; - cpm->cp_peodr = PE_ODR_VAL; - cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL; - cpm->cp_pepar = PE_SP_MASK; -#endif - - return 0; -} - -#ifdef CONFIG_HW_WATCHDOG - -void hw_watchdog_reset(void) -{ - /* XXX add here the really funky stuff */ -} - -#endif - -#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) -int overwrite_console(void) -{ - /* printf("overwrite_console called\n"); */ - return 0; -} -#endif - -extern int drv_phone_init(void); -extern int drv_phone_use_me(void); -extern int drv_phone_is_idle(void); - -int misc_init_r(void) -{ - return 0; -} - -int last_stage_init(void) -{ - reset_phys(); - - return 0; -} diff --git a/board/stx/stxxtc/u-boot.lds b/board/stx/stxxtc/u-boot.lds deleted file mode 100644 index 0dff5a4023..0000000000 --- a/board/stx/stxxtc/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/stx/stxxtc/u-boot.lds.debug b/board/stx/stxxtc/u-boot.lds.debug deleted file mode 100644 index a198cf9520..0000000000 --- a/board/stx/stxxtc/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/svm_sc8xx/Kconfig b/board/svm_sc8xx/Kconfig deleted file mode 100644 index 522b1a85d0..0000000000 --- a/board/svm_sc8xx/Kconfig +++ /dev/null @@ -1,11 +0,0 @@ -if TARGET_SVM_SC8XX - -config SYS_BOARD - string - default "svm_sc8xx" - -config SYS_CONFIG_NAME - string - default "svm_sc8xx" - -endif diff --git a/board/svm_sc8xx/MAINTAINERS b/board/svm_sc8xx/MAINTAINERS deleted file mode 100644 index c19bcae2b2..0000000000 --- a/board/svm_sc8xx/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -SVM_SC8XX BOARD -M: John Zhan <zhanz@sinovee.com> -S: Orphan (since 2014-06) -F: board/svm_sc8xx/ -F: include/configs/svm_sc8xx.h -F: configs/svm_sc8xx_defconfig diff --git a/board/svm_sc8xx/Makefile b/board/svm_sc8xx/Makefile deleted file mode 100644 index 4c0b4a33e9..0000000000 --- a/board/svm_sc8xx/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = svm_sc8xx.o flash.o diff --git a/board/svm_sc8xx/flash.c b/board/svm_sc8xx/flash.c deleted file mode 100644 index 8a04de80b3..0000000000 --- a/board/svm_sc8xx/flash.c +++ /dev/null @@ -1,666 +0,0 @@ -/* - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> - -#ifndef CONFIG_ENV_ADDR -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#endif - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/*----------------------------------------------------------------------- - * Functions - */ -static int write_word(flash_info_t *info, ulong dest, ulong data); - -#ifdef CONFIG_BOOT_8B -static int my_in_8(unsigned char *addr); -static void my_out_8(unsigned char *addr, int val); -#endif -#ifdef CONFIG_BOOT_16B -static int my_in_be16(unsigned short *addr); -static void my_out_be16(unsigned short *addr, int val); -#endif -#ifdef CONFIG_BOOT_32B -static unsigned my_in_be32(unsigned *addr); -static void my_out_be32(unsigned *addr, int val); -#endif -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0, size_b1; - int i; - - size_b0 = 0; - size_b1 = 0; - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; - -#ifdef CONFIG_SYS_DOC_BASE -#ifndef CONFIG_FEL8xx_AT - /* 32k bytes */ - memctl->memc_or5 = (0xffff8000 | CONFIG_SYS_OR_TIMING_DOC); - memctl->memc_br5 = CONFIG_SYS_DOC_BASE | 0x401; -#else - /* 32k bytes */ - memctl->memc_or3 = (0xffff8000 | CONFIG_SYS_OR_TIMING_DOC); - memctl->memc_br3 = CONFIG_SYS_DOC_BASE | 0x401; -#endif -#endif -#if defined(CONFIG_BOOT_8B) - size_b0 = 0x80000; /* 512 K */ - - flash_info[0].flash_id = FLASH_MAN_AMD | FLASH_AM040; - flash_info[0].sector_count = 8; - flash_info[0].size = 0x00080000; - - /* set up sector start address table */ - for (i = 0; i < flash_info[0].sector_count; i++) - flash_info[0].start[i] = 0x40000000 + (i * 0x10000); - - /* protect all sectors */ - for (i = 0; i < flash_info[0].sector_count; i++) - flash_info[0].protect[i] = 0x1; - -#elif defined(CONFIG_BOOT_16B) - size_b0 = 0x400000; /* 4MB , assume AMD29LV320B */ - - flash_info[0].flash_id = FLASH_MAN_AMD | FLASH_AM320B; - flash_info[0].sector_count = 67; - flash_info[0].size = 0x00400000; - - /* set up sector start address table */ - flash_info[0].start[0] = 0x40000000; - flash_info[0].start[1] = 0x40000000 + 0x4000; - flash_info[0].start[2] = 0x40000000 + 0x6000; - flash_info[0].start[3] = 0x40000000 + 0x8000; - - for (i = 4; i < flash_info[0].sector_count; i++) { - flash_info[0].start[i] = - 0x40000000 + 0x10000 + ((i - 4) * 0x10000); - } - - /* protect all sectors */ - for (i = 0; i < flash_info[0].sector_count; i++) - flash_info[0].protect[i] = 0x1; -#endif - -#ifdef CONFIG_BOOT_32B - - /* Static FLASH Bank configuration here - FIXME XXX */ - size_b0 = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, - &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 << 20); - } - - size_b1 = flash_get_size((vu_long *) FLASH_BASE1_PRELIM, - &flash_info[1]); - - if (size_b1 > size_b0) { - printf("## ERROR: " - "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1 << 20, size_b0, size_b0 << 20); - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - - return 0; - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | - (-size_b0 & OR_AM_MSK); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | - BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, - &flash_info[0]); - - flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); -#endif - - if (size_b1) { - memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | - (-size_b1 & 0xFFFF8000); - memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + - size_b0) & BR_BA_MSK) | BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + - size_b0), &flash_info[1]); - - flash_get_offsets(CONFIG_SYS_FLASH_BASE + size_b0, - &flash_info[1]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[1]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[1]); -#endif - } else { - memctl->memc_br1 = 0; /* invalidate bank */ - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - -#endif /* CONFIG_BOOT_32B */ - - return size_b0 + size_b1; -} - - -void flash_print_info(flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: - printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: - printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ - -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long *) (info->start[0]); - int flag, prot, sect, l_sect, in_mid, in_did; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) - printf("- missing\n"); - else - printf("- no sectors to erase\n"); - - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) - prot++; - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - -#if defined(CONFIG_BOOT_8B) - my_out_8((unsigned char *)((ulong)addr + 0x555), 0xaa); - my_out_8((unsigned char *)((ulong)addr + 0x2aa), 0x55); - my_out_8((unsigned char *)((ulong)addr + 0x555), 0x90); - - in_mid = my_in_8((unsigned char *)addr); - in_did = my_in_8((unsigned char *)((ulong)addr + 1)); - - printf(" man ID=0x%x, dev ID=0x%x.\n", in_mid, in_did); - - my_out_8((unsigned char *)addr, 0xf0); - udelay(1); - - my_out_8((unsigned char *)((ulong)addr + 0x555), 0xaa); - my_out_8((unsigned char *)((ulong)addr + 0x2aa), 0x55); - my_out_8((unsigned char *)((ulong)addr + 0x555), 0x80); - my_out_8((unsigned char *)((ulong)addr + 0x555), 0xaa); - my_out_8((unsigned char *)((ulong)addr + 0x2aa), 0x55); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long *) (info->start[sect]); - /*addr[0] = 0x00300030; */ - my_out_8((unsigned char *)((ulong)addr), 0x30); - l_sect = sect; - } - } -#elif defined(CONFIG_BOOT_16B) - my_out_be16((unsigned short *)((ulong)addr + (0xaaa)), 0xaa); - my_out_be16((unsigned short *)((ulong)addr + (0x554)), 0x55); - my_out_be16((unsigned short *)((ulong)addr + (0xaaa)), 0x90); - in_mid = my_in_be16((unsigned short *)addr); - in_did = my_in_be16((unsigned short *)((ulong)addr + 2)); - printf(" man ID=0x%x, dev ID=0x%x.\n", in_mid, in_did); - my_out_be16((unsigned short *)addr, 0xf0); - udelay(1); - my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0xaa); - my_out_be16((unsigned short *)((ulong)addr + 0x554), 0x55); - my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0x80); - my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0xaa); - my_out_be16((unsigned short *)((ulong)addr + 0x554), 0x55); - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long *) (info->start[sect]); - my_out_be16((unsigned short *)((ulong)addr), 0x30); - l_sect = sect; - } - } - -#elif defined(CONFIG_BOOT_32B) - my_out_be32((unsigned *)((ulong)addr + 0x1554), 0xaa); - my_out_be32((unsigned *)((ulong)addr + 0xaa8), 0x55); - my_out_be32((unsigned *)((ulong)addr + 0x1554), 0x90); - - in_mid = my_in_be32((unsigned *)addr); - in_did = my_in_be32((unsigned *)((ulong)addr + 4)); - - printf(" man ID=0x%x, dev ID=0x%x.\n", in_mid, in_did); - - my_out_be32((unsigned *) addr, 0xf0); - udelay(1); - - my_out_be32((unsigned *)((ulong)addr + 0x1554), 0xaa); - my_out_be32((unsigned *)((ulong)addr + 0xaa8), 0x55); - my_out_be32((unsigned *)((ulong)addr + 0x1554), 0x80); - my_out_be32((unsigned *)((ulong)addr + 0x1554), 0xaa); - my_out_be32((unsigned *)((ulong)addr + 0xaa8), 0x55); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long *) (info->start[sect]); - my_out_be32((unsigned *)((ulong)addr), 0x00300030); - l_sect = sect; - } - } - -#else -#error CONFIG_BOOT_(size)B missing. -#endif - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer(0); - last = start; - addr = (vu_long *) (info->start[l_sect]); -#if defined(CONFIG_BOOT_8B) - while ((my_in_8((unsigned char *) addr) & 0x80) != 0x80) -#elif defined(CONFIG_BOOT_16B) - while ((my_in_be16((unsigned short *) addr) & 0x0080) != 0x0080) -#elif defined(CONFIG_BOOT_32B) - while ((my_in_be32((unsigned *) addr) & 0x00800080) != 0x00800080) -#else -#error CONFIG_BOOT_(size)B missing. -#endif - { - now = get_timer(start); - if (now > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } -DONE: - /* reset to read mode */ - addr = (volatile unsigned long *) info->start[0]; - -#if defined(CONFIG_BOOT_8B) - my_out_8((unsigned char *) addr, 0xf0); -#elif defined(CONFIG_BOOT_16B) - my_out_be16((unsigned short *) addr, 0x00f0); -#elif defined(CONFIG_BOOT_32B) - my_out_be32((unsigned *) addr, 0x00F000F0); /* reset bank */ -#else -#error CONFIG_BOOT_(size)B missing. -#endif - printf(" done\n"); - return 0; -} - -/* - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - l = addr - wp; - - if (l != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) - data = (data << 8) | (*(uchar *) cp); - - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) - data = (data << 8) | (*(uchar *) cp); - - rc = write_word(info, wp, data); - - if (rc != 0) - return rc; - - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) - data = (data << 8) | *src++; - - rc = write_word(info, wp, data); - - if (rc != 0) - return rc; - - wp += 4; - cnt -= 4; - } - - if (cnt == 0) - return 0; - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) - data = (data << 8) | (*(uchar *) cp); - - return write_word(info, wp, data); -} - -/* - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word(flash_info_t *info, ulong dest, ulong data) -{ - ulong addr = (ulong) (info->start[0]); - ulong start; - int flag; - ulong i; - int data_short[2]; - - /* Check if Flash is (sufficiently) erased */ - if (((ulong)*(ulong *)dest & data) != data) - return 2; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); -#if defined(CONFIG_BOOT_8B) -#ifdef DEBUG - { - int in_mid, in_did; - - my_out_8((unsigned char *) (addr + 0x555), 0xaa); - my_out_8((unsigned char *) (addr + 0x2aa), 0x55); - my_out_8((unsigned char *) (addr + 0x555), 0x90); - - in_mid = my_in_8((unsigned char *) addr); - in_did = my_in_8((unsigned char *) (addr + 1)); - - printf(" man ID=0x%x, dev ID=0x%x.\n", in_mid, in_did); - - my_out_8((unsigned char *) addr, 0xf0); - udelay(1); - } -#endif - { - int data_ch[4]; - - data_ch[0] = (int) ((data >> 24) & 0xff); - data_ch[1] = (int) ((data >> 16) & 0xff); - data_ch[2] = (int) ((data >> 8) & 0xff); - data_ch[3] = (int) (data & 0xff); - - for (i = 0; i < 4; i++) { - my_out_8((unsigned char *) (addr + 0x555), 0xaa); - my_out_8((unsigned char *) (addr + 0x2aa), 0x55); - my_out_8((unsigned char *) (addr + 0x555), 0xa0); - my_out_8((unsigned char *) (dest + i), data_ch[i]); - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - while ((my_in_8((unsigned char *)(dest + i))) != - (data_ch[i])) { - if (get_timer(start) > - CONFIG_SYS_FLASH_WRITE_TOUT) { - return 1; - } - } - } /* for */ - } -#elif defined(CONFIG_BOOT_16B) - data_short[0] = (int) (data >> 16) & 0xffff; - data_short[1] = (int) data & 0xffff; - for (i = 0; i < 2; i++) { - my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0xaa); - my_out_be16((unsigned short *)((ulong)addr + 0x554), 0x55); - my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0xa0); - my_out_be16((unsigned short *)(dest + (i * 2)), - data_short[i]); - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - while ((my_in_be16((unsigned short *)(dest + (i * 2)))) != - (data_short[i])) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) - return 1; - } - } -#elif defined(CONFIG_BOOT_32B) - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) - return 1; - } -#endif - return 0; -} - -#ifdef CONFIG_BOOT_8B -static int my_in_8(unsigned char *addr) -{ - int ret; - __asm__ __volatile__("lbz%U1%X1 %0,%1; eieio":"=r"(ret):"m"(*addr)); - - return ret; -} - -static void my_out_8(unsigned char *addr, int val) -{ - __asm__ __volatile__("stb%U0%X0 %1,%0; eieio":"=m"(*addr):"r"(val)); -} -#endif -#ifdef CONFIG_BOOT_16B -static int my_in_be16(unsigned short *addr) -{ - int ret; - __asm__ __volatile__("lhz%U1%X1 %0,%1; eieio":"=r"(ret):"m"(*addr)); - - return ret; -} - -static void my_out_be16(unsigned short *addr, int val) -{ - __asm__ __volatile__("sth%U0%X0 %1,%0; eieio":"=m"(*addr):"r"(val)); -} -#endif -#ifdef CONFIG_BOOT_32B -static unsigned my_in_be32(unsigned *addr) -{ - unsigned ret; - __asm__ __volatile__("lwz%U1%X1 %0,%1; eieio":"=r"(ret):"m"(*addr)); - - return ret; -} - -static void my_out_be32(unsigned *addr, int val) -{ - __asm__ __volatile__("stw%U0%X0 %1,%0; eieio":"=m"(*addr):"r"(val)); -} -#endif diff --git a/board/svm_sc8xx/svm_sc8xx.c b/board/svm_sc8xx/svm_sc8xx.c deleted file mode 100644 index 5db48506c6..0000000000 --- a/board/svm_sc8xx/svm_sc8xx.c +++ /dev/null @@ -1,144 +0,0 @@ -/* - * (C) Copyright 2000, 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> - -/* ------------------------------------------------------------------------- */ -const uint sdram_table[] = -{ -/*----------------- - UPM A contents: ------------------ */ -/*--------------------------------------------------- - Read Single Beat Cycle. Offset 0 in the RAM array. ----------------------------------------------------- */ -0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00 , -0x1ff77c47, 0x1ff77c35, 0xefeabc34, 0x1fb57c35 , -/*------------------------------------------------ - Read Burst Cycle. Offset 0x8 in the RAM array. ------------------------------------------------- */ -0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, -0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, -0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, -0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, -/*------------------------------------------------------- - Write Single Beat Cycle. Offset 0x18 in the RAM array -------------------------------------------------------- */ -0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47 , -0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff , -/*------------------------------------------------- - Write Burst Cycle. Offset 0x20 in the RAM array -------------------------------------------------- */ -0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, -0xf0affc00, 0xe1bbbc04, 0x1ff77c47, 0xffffffff, -0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff , -0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff , -/*------------------------------------------------------------------------ - Periodic Timer Expired. For DRAM refresh. Offset 0x30 in the RAM array ------------------------------------------------------------------------- */ -0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, -0xfffffc84, 0xfffffc07, 0xffffffff, 0xffffffff, -0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff , -/*----------- -* Exception: -* ----------- */ -0x7ffefc07, 0xffffffff, 0xffffffff, 0xffffffff , -}; - -/* ------------------------------------------------------------------------- */ -/* - * Check Board Identity: - * - * Test ID string (SVM8...) - * - * Return 1 for "SC8xx" type, 0 else. - */ - -int checkboard(void) -{ - char buf[64]; - int i; - int l = getenv_f("serial#", buf, sizeof(buf)); - - if (l < 0 || strncmp(buf, "SVM8", 4)) { - printf("### No HW ID - assuming SVM SC8xx\n"); - return (0); - } - - for (i = 0; i < l; ++i) { - if (buf[i] == ' ') - break; - putc(buf[i]); - } - - putc('\n'); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size_b0 = 0; - - upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; -#if defined (CONFIG_SDRAM_16M) - memctl->memc_mamr = 0x00802114 | CONFIG_SYS_MxMR_PTx; - memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ - udelay(1); - memctl->memc_mcr = 0x80002830; - udelay(1); - memctl->memc_mar = 0x00000088; - udelay(1); - memctl->memc_mcr = 0x80002106; - udelay(1); - memctl->memc_or1 = 0xff000a00; - size_b0 = 0x01000000; -#elif defined (CONFIG_SDRAM_32M) - memctl->memc_mamr = 0x00904114 | CONFIG_SYS_MxMR_PTx; - memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ - udelay(1); - memctl->memc_mcr = 0x80002830; - udelay(1); - memctl->memc_mar = 0x00000088; - udelay(1); - memctl->memc_mcr = 0x80002106; - udelay(1); - memctl->memc_or1 = 0xfe000a00; - size_b0 = 0x02000000; -#elif defined (CONFIG_SDRAM_64M) - memctl->memc_mamr = 0x00a04114 | CONFIG_SYS_MxMR_PTx; - memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ - udelay(1); - memctl->memc_mcr = 0x80002830; - udelay(1); - memctl->memc_mar = 0x00000088; - udelay(1); - memctl->memc_mcr = 0x80002106; - udelay(1); - memctl->memc_or1 = 0xfc000a00; - size_b0 = 0x04000000; -#else -#error SDRAM size configuration missing. -#endif - memctl->memc_br1 = 0x00000081; - udelay(200); - return (size_b0 ); -} - -#if defined(CONFIG_CMD_DOC) -void doc_init (void) -{ - doc_probe (CONFIG_SYS_DOC_BASE); -} -#endif diff --git a/board/svm_sc8xx/u-boot.lds b/board/svm_sc8xx/u-boot.lds deleted file mode 100644 index df564e9395..0000000000 --- a/board/svm_sc8xx/u-boot.lds +++ /dev/null @@ -1,99 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - lib/built-in.o (.text*) - net/built-in.o (.text*) - arch/powerpc/cpu/mpc8xx/built-in.o (.text*) - arch/powerpc/lib/built-in.o (.text*) - board/svm_sc8xx/built-in.o (.text*) - *(.text.*printf) - *(.text.do_mem_*) - *(.text.flash*) - *(.text.run_command) - *(.text.main_loop) - *(.text.srec_decode) - - . = env_offset; - common/env_embedded.o (.ppcenv*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/svm_sc8xx/u-boot.lds.debug b/board/svm_sc8xx/u-boot.lds.debug deleted file mode 100644 index b2c562c33d..0000000000 --- a/board/svm_sc8xx/u-boot.lds.debug +++ /dev/null @@ -1,114 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/ti/omap5912osk/Kconfig b/board/ti/omap5912osk/Kconfig deleted file mode 100644 index 9f7493a35f..0000000000 --- a/board/ti/omap5912osk/Kconfig +++ /dev/null @@ -1,23 +0,0 @@ -if TARGET_OMAP5912OSK - -config SYS_CPU - string - default "arm926ejs" - -config SYS_BOARD - string - default "omap5912osk" - -config SYS_VENDOR - string - default "ti" - -config SYS_SOC - string - default "omap" - -config SYS_CONFIG_NAME - string - default "omap5912osk" - -endif diff --git a/board/ti/omap5912osk/MAINTAINERS b/board/ti/omap5912osk/MAINTAINERS deleted file mode 100644 index 43ffb9b7b9..0000000000 --- a/board/ti/omap5912osk/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -OMAP5912OSK BOARD -M: Rishi Bhattacharya <rishi@ti.com> -S: Maintained -F: board/ti/omap5912osk/ -F: include/configs/omap5912osk.h -F: configs/omap5912osk_defconfig diff --git a/board/ti/omap5912osk/Makefile b/board/ti/omap5912osk/Makefile deleted file mode 100644 index d7c0ebd729..0000000000 --- a/board/ti/omap5912osk/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := omap5912osk.o -obj-y += lowlevel_init.o diff --git a/board/ti/omap5912osk/config.mk b/board/ti/omap5912osk/config.mk deleted file mode 100644 index 5b8d952ba6..0000000000 --- a/board/ti/omap5912osk/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2002-2004 -# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> -# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> -# -# (C) Copyright 2003 -# Texas Instruments, <www.ti.com> -# Kshitij Gupta <Kshitij@ti.com> -# -# (C) Copyright 2004 -# Texas Instruments, <www.ti.com> -# Rishi Bhattacharya <rishi@ti.com> -# -# TI OSK board with OMAP5912 (ARM925EJS) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# OSK has 1 bank of 32 MB SDRAM -# Physical Address: -# 1000'0000 to 1200'0000 -# -# -# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000 -# (mem base + reserved) -# -# When running from RAM use address 1108'0000, otherwise when -# booting from NOR flash link to address 0000'0000. -# - -CONFIG_SYS_TEXT_BASE = 0x00000000 -#CONFIG_SYS_TEXT_BASE = 0x11080000 diff --git a/board/ti/omap5912osk/lowlevel_init.S b/board/ti/omap5912osk/lowlevel_init.S deleted file mode 100644 index e05a1c7b55..0000000000 --- a/board/ti/omap5912osk/lowlevel_init.S +++ /dev/null @@ -1,477 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2003 - * Texas Instruments, <www.ti.com> - * Kshitij Gupta <Kshitij@ti.com> - * - * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004 - * - * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004 - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <version.h> - -#if defined(CONFIG_OMAP1610) -#include <./configs/omap1510.h> -#endif - -.globl lowlevel_init -lowlevel_init: - - /*------------------------------------------------------* - * Ensure i-cache is enabled * - * To configure TC regs without fetching instruction * - *------------------------------------------------------*/ - mrc p15, 0, r0, c1, c0 - orr r0, r0, #0x1000 - mcr p15, 0, r0, c1, c0 - - /*------------------------------------------------------* - *mask all IRQs by setting all bits in the INTMR default* - *------------------------------------------------------*/ - mov r1, #0xffffffff - ldr r0, =REG_IHL1_MIR - str r1, [r0] - ldr r0, =REG_IHL2_MIR - str r1, [r0] - - /*------------------------------------------------------* - * Set up ARM CLM registers (IDLECT1) * - *------------------------------------------------------*/ - ldr r0, REG_ARM_IDLECT1 - ldr r1, VAL_ARM_IDLECT1 - str r1, [r0] - - /*------------------------------------------------------* - * Set up ARM CLM registers (IDLECT2) * - *------------------------------------------------------*/ - ldr r0, REG_ARM_IDLECT2 - ldr r1, VAL_ARM_IDLECT2 - str r1, [r0] - - /*------------------------------------------------------* - * Set up ARM CLM registers (IDLECT3) * - *------------------------------------------------------*/ - ldr r0, REG_ARM_IDLECT3 - ldr r1, VAL_ARM_IDLECT3 - str r1, [r0] - - mov r1, #0x01 /* PER_EN bit */ - ldr r0, REG_ARM_RSTCT2 - strh r1, [r0] /* CLKM; Peripheral reset. */ - - /* Set CLKM to Sync-Scalable */ - mov r1, #0x1000 - ldr r0, REG_ARM_SYSST - - mov r2, #0 -1: cmp r2, #1 - streqh r1, [r0] - add r2, r2, #1 - cmp r2, #0x100 /* wait for any bubbles to finish */ - bne 1b - - ldr r1, VAL_ARM_CKCTL - ldr r0, REG_ARM_CKCTL - strh r1, [r0] - - /* a few nops to let settle */ - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - - /* setup DPLL 1 */ - /* Ramp up the clock to 96Mhz */ - ldr r1, VAL_DPLL1_CTL - ldr r0, REG_DPLL1_CTL - strh r1, [r0] - ands r1, r1, #0x10 /* Check if PLL is enabled. */ - beq lock_end /* Do not look for lock if BYPASS selected */ -2: - ldrh r1, [r0] - ands r1, r1, #0x01 /* Check the LOCK bit.*/ - beq 2b /* loop until bit goes hi. */ -lock_end: - - /*------------------------------------------------------* - * Turn off the watchdog during init... * - *------------------------------------------------------*/ - ldr r0, REG_WATCHDOG - ldr r1, WATCHDOG_VAL1 - str r1, [r0] - ldr r1, WATCHDOG_VAL2 - str r1, [r0] - ldr r0, REG_WSPRDOG - ldr r1, WSPRDOG_VAL1 - str r1, [r0] - ldr r0, REG_WWPSDOG - -watch1Wait: - ldr r1, [r0] - tst r1, #0x10 - bne watch1Wait - - ldr r0, REG_WSPRDOG - ldr r1, WSPRDOG_VAL2 - str r1, [r0] - ldr r0, REG_WWPSDOG -watch2Wait: - ldr r1, [r0] - tst r1, #0x10 - bne watch2Wait - - /* Set memory timings corresponding to the new clock speed */ - ldr r3, VAL_SDRAM_CONFIG_SDF0 - - /* Check execution location to determine current execution location - * and branch to appropriate initialization code. - */ - mov r0, #0x10000000 /* Load physical SDRAM base. */ - mov r1, pc /* Get current execution location. */ - cmp r1, r0 /* Compare. */ - bge skip_sdram /* Skip over EMIF-fast initialization if running from SDRAM. */ - - /* identify the device revision, -- TMX or TMP(TMS) */ - ldr r0, REG_DEVICE_ID - ldr r1, [r0] - - ldr r0, VAL_DEVICE_ID_TMP - mov r1, r1, lsl #15 - mov r1, r1, lsr #16 - cmp r0, r1 - bne skip_TMP_Patch - - /* Enable TMP/TMS device new features */ - mov r0, #1 - ldr r1, REG_TC_EMIFF_DOUBLER - str r0, [r1] - - /* Enable new ac parameters */ - mov r0, #0x0b - ldr r1, REG_SDRAM_CONFIG2 - str r0, [r1] - - ldr r3, VAL_SDRAM_CONFIG_SDF1 - -skip_TMP_Patch: - - /* - * Delay for SDRAM initialization. - */ - mov r0, #0x1800 /* value should be checked */ -3: - subs r0, r0, #0x1 /* Decrement count */ - bne 3b - - /* - * Set SDRAM control values. Disable refresh before MRS command. - */ - - /* mobile ddr operation */ - ldr r0, REG_SDRAM_OPERATION - mov r2, #07 - str r2, [r0] - - /* config register */ - ldr r0, REG_SDRAM_CONFIG - str r3, [r0] - - /* manual command register */ - ldr r0, REG_SDRAM_MANUAL_CMD - - /* issue set cke high */ - mov r1, #CMD_SDRAM_CKE_SET_HIGH - str r1, [r0] - - /* issue nop */ - mov r1, #CMD_SDRAM_NOP - str r1, [r0] - - mov r2, #0x0100 -waitMDDR1: - subs r2, r2, #1 - bne waitMDDR1 /* delay loop */ - - /* issue precharge */ - mov r1, #CMD_SDRAM_PRECHARGE - str r1, [r0] - - /* issue autorefresh x 2 */ - mov r1, #CMD_SDRAM_AUTOREFRESH - str r1, [r0] - str r1, [r0] - - /* mrs register ddr mobile */ - ldr r0, REG_SDRAM_MRS - mov r1, #0x33 - str r1, [r0] - - /* emrs1 low-power register */ - ldr r0, REG_SDRAM_EMRS1 - /* self refresh on all banks */ - mov r1, #0 - str r1, [r0] - - ldr r0, REG_DLL_URD_CONTROL - ldr r1, DLL_URD_CONTROL_VAL - str r1, [r0] - - ldr r0, REG_DLL_LRD_CONTROL - ldr r1, DLL_LRD_CONTROL_VAL - str r1, [r0] - - ldr r0, REG_DLL_WRT_CONTROL - ldr r1, DLL_WRT_CONTROL_VAL - str r1, [r0] - - /* delay loop */ - mov r0, #0x0100 -waitMDDR2: - subs r0, r0, #1 - bne waitMDDR2 - - /* - * Delay for SDRAM initialization. - */ - mov r0, #0x1800 -4: - subs r0, r0, #1 /* Decrement count. */ - bne 4b - b common_tc - -skip_sdram: - ldr r0, REG_SDRAM_CONFIG - str r3, [r0] - -common_tc: - /* slow interface */ - ldr r1, VAL_TC_EMIFS_CS0_CONFIG - ldr r0, REG_TC_EMIFS_CS0_CONFIG - str r1, [r0] /* Chip Select 0 */ - - ldr r1, VAL_TC_EMIFS_CS1_CONFIG - ldr r0, REG_TC_EMIFS_CS1_CONFIG - str r1, [r0] /* Chip Select 1 */ - - ldr r1, VAL_TC_EMIFS_CS3_CONFIG - ldr r0, REG_TC_EMIFS_CS3_CONFIG - str r1, [r0] /* Chip Select 3 */ - - ldr r1, VAL_TC_EMIFS_DWS - ldr r0, REG_TC_EMIFS_DWS - str r1, [r0] /* Enable EMIFS.RDY for CS1 (ether) */ - -#ifdef CONFIG_H2_OMAP1610 - /* inserting additional 2 clock cycle hold time for LAN */ - ldr r0, REG_TC_EMIFS_CS1_ADVANCED - ldr r1, VAL_TC_EMIFS_CS1_ADVANCED - str r1, [r0] -#endif - /* Start MPU Timer 1 */ - ldr r0, REG_MPU_LOAD_TIMER - ldr r1, VAL_MPU_LOAD_TIMER - str r1, [r0] - - ldr r0, REG_MPU_CNTL_TIMER - ldr r1, VAL_MPU_CNTL_TIMER - str r1, [r0] - - /* - * Setup a temporary stack - */ - ldr sp, SRAM_STACK - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - - /* - * Save the old lr(passed in ip) and the current lr to stack - */ - push {ip, lr} - - /* - * go setup pll, mux, memory - */ - bl s_init - pop {ip, pc} - - /* back to arch calling code */ - mov pc, lr - - /* the literal pools origin */ - .ltorg - -REG_DEVICE_ID: /* 32 bits */ - .word 0xfffe2004 -REG_TC_EMIFS_CONFIG: - .word 0xfffecc0c -REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */ - .word 0xfffecc10 -REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */ - .word 0xfffecc14 -REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */ - .word 0xfffecc18 -REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */ - .word 0xfffecc1c -REG_TC_EMIFS_DWS: /* 32 bits */ - .word 0xfffecc40 -#ifdef CONFIG_H2_OMAP1610 -REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */ - .word 0xfffecc54 -#endif - -/* MPU clock/reset/power mode control registers */ -REG_ARM_CKCTL: /* 16 bits */ - .word 0xfffece00 -REG_ARM_IDLECT3: /* 16 bits */ - .word 0xfffece24 -REG_ARM_IDLECT2: /* 16 bits */ - .word 0xfffece08 -REG_ARM_IDLECT1: /* 16 bits */ - .word 0xfffece04 -REG_ARM_RSTCT2: /* 16 bits */ - .word 0xfffece14 -REG_ARM_SYSST: /* 16 bits */ - .word 0xfffece18 - -/* DPLL control registers */ -REG_DPLL1_CTL: /* 16 bits */ - .word 0xfffecf00 - -/* Watch Dog register */ -/* secure watchdog stop */ -REG_WSPRDOG: - .word 0xfffeb048 -/* watchdog write pending */ -REG_WWPSDOG: - .word 0xfffeb034 - -WSPRDOG_VAL1: - .word 0x0000aaaa -WSPRDOG_VAL2: - .word 0x00005555 - -/* SDRAM config is: auto refresh enabled, 16 bit 4 bank, - counter @8192 rows, 10 ns, 8 burst */ -REG_SDRAM_CONFIG: - .word 0xfffecc20 -REG_SDRAM_CONFIG2: - .word 0xfffecc3c -REG_TC_EMIFF_DOUBLER: /* 32 bits */ - .word 0xfffecc60 - -/* Operation register */ -REG_SDRAM_OPERATION: - .word 0xfffecc80 - -/* Manual command register */ -REG_SDRAM_MANUAL_CMD: - .word 0xfffecc84 - -/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */ -REG_SDRAM_MRS: - .word 0xfffecc70 - -/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */ -REG_SDRAM_EMRS1: - .word 0xfffecc78 - -/* WRT DLL register */ -REG_DLL_WRT_CONTROL: - .word 0xfffecc68 -DLL_WRT_CONTROL_VAL: - .word 0x03f00002 /* Phase of 72deg, write offset +31 */ - -/* URD DLL register */ -REG_DLL_URD_CONTROL: - .word 0xfffeccc0 -DLL_URD_CONTROL_VAL: - .word 0x00800002 /* Phase of 72deg, read offset +31 */ - -/* LRD DLL register */ -REG_DLL_LRD_CONTROL: - .word 0xfffecccc -DLL_LRD_CONTROL_VAL: - .word 0x00800002 /* read offset +31 */ - -REG_WATCHDOG: - .word 0xfffec808 -WATCHDOG_VAL1: - .word 0x000000f5 -WATCHDOG_VAL2: - .word 0x000000a0 - -REG_MPU_LOAD_TIMER: - .word 0xfffec504 -REG_MPU_CNTL_TIMER: - .word 0xfffec500 -VAL_MPU_LOAD_TIMER: - .word 0xffffffff -VAL_MPU_CNTL_TIMER: - .word 0xffffffa1 - -/* 96 MHz Samsung Mobile DDR */ -/* Original setting for TMX device */ -VAL_SDRAM_CONFIG_SDF0: - .word 0x0014e6fe - -/* NEW_SYS_FREQ mode (valid only TMP/TMS devices) */ -VAL_SDRAM_CONFIG_SDF1: - .word 0x0114e6fe - -VAL_ARM_CKCTL: - .word 0x2000 /* was: 0x3000, now use CLK_REF for timer input */ -VAL_DPLL1_CTL: - .word 0x2830 - -#ifdef CONFIG_OSK_OMAP5912 -VAL_TC_EMIFS_CS0_CONFIG: - .word 0x002130b0 -VAL_TC_EMIFS_CS1_CONFIG: - .word 0x00001133 -VAL_TC_EMIFS_CS2_CONFIG: - .word 0x000055f0 -VAL_TC_EMIFS_CS3_CONFIG: - .word 0x88013141 -VAL_TC_EMIFS_DWS: /* Enable EMIFS.RDY for CS1 access (ether) */ - .word 0x000000c0 -VAL_DEVICE_ID_TMP: /* TMP/TMS=0xb65f, TMX=0xb58c */ - .word 0xb65f -#endif - -#ifdef CONFIG_H2_OMAP1610 -VAL_TC_EMIFS_CS0_CONFIG: - .word 0x00203331 -VAL_TC_EMIFS_CS1_CONFIG: - .word 0x8180fff3 -VAL_TC_EMIFS_CS2_CONFIG: - .word 0xf800f22a -VAL_TC_EMIFS_CS3_CONFIG: - .word 0x88013141 -VAL_TC_EMIFS_CS1_ADVANCED: - .word 0x00000022 -#endif - -VAL_ARM_IDLECT1: - .word 0x00000400 -VAL_ARM_IDLECT2: - .word 0x00000886 -VAL_ARM_IDLECT3: - .word 0x00000015 - -SRAM_STACK: - .word CONFIG_SYS_INIT_SP_ADDR - -/* command values */ -.equ CMD_SDRAM_NOP, 0x00000000 -.equ CMD_SDRAM_PRECHARGE, 0x00000001 -.equ CMD_SDRAM_AUTOREFRESH, 0x00000002 -.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007 diff --git a/board/ti/omap5912osk/omap5912osk.c b/board/ti/omap5912osk/omap5912osk.c deleted file mode 100644 index 88a7310cec..0000000000 --- a/board/ti/omap5912osk/omap5912osk.c +++ /dev/null @@ -1,307 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> - * - * (C) Copyright 2003 - * Texas Instruments, <www.ti.com> - * Kshitij Gupta <Kshitij@ti.com> - * - * (C) Copyright 2004 - * Texas Instruments, <www.ti.com> - * Rishi Bhattacharya <rishi@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <netdev.h> -#if defined(CONFIG_OMAP1610) -#include <./configs/omap1510.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -void flash__init (void); -void ether__init (void); -void set_muxconf_regs (void); -void peripheral_power_enable (void); - -#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF) - -static inline void delay (unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -/* - * Miscellaneous platform dependent initialisations - */ - -int board_init (void) -{ - gd->bd->bi_arch_number = MACH_TYPE_OMAP_OSK; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x10000100; - - flash__init(); - ether__init(); - - return 0; -} - -void s_init(void) -{ - /* Configure MUX settings */ - set_muxconf_regs (); - peripheral_power_enable (); - -/* this speeds up your boot a quite a bit. However to make it - * work, you need make sure your kernel startup flush bug is fixed. - * ... rkw ... - */ - icache_enable (); -} - -/****************************** - Routine: - Description: -******************************/ -void flash__init (void) -{ -#define EMIFS_GlB_Config_REG 0xfffecc0c - unsigned int regval; - regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG); - /* Turn off write protection for flash devices. */ - regval = regval | 0x0001; - *((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval; -} -/************************************************************* - Routine:ether__init - Description: take the Ethernet controller out of reset and wait - for the EEPROM load to complete. -*************************************************************/ -void ether__init (void) -{ -#define ETH_CONTROL_REG 0x0480000b - int i; - - *((volatile unsigned short *) 0xfffece08) = 0x03FF; - *((volatile unsigned short *) 0xfffb3824) = 0x8000; - *((volatile unsigned short *) 0xfffb3830) = 0x0000; - *((volatile unsigned short *) 0xfffb3834) = 0x0009; - *((volatile unsigned short *) 0xfffb3838) = 0x0009; - *((volatile unsigned short *) 0xfffb3818) = 0x0002; - *((volatile unsigned short *) 0xfffb382C) = 0x0048; - *((volatile unsigned short *) 0xfffb3824) = 0x8603; - udelay (3); - for (i=0;i<2000;i++); - *((volatile unsigned short *) 0xfffb381C) = 0x6610; - udelay (30); - for (i=0;i<10000;i++); - - *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01; - udelay (3); - - -} - -/****************************** - Routine: - Description: -******************************/ -int dram_init(void) -{ - gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - -/****************************************************** - Routine: set_muxconf_regs - Description: Setting up the configuration Mux registers - specific to the hardware -*******************************************************/ -void set_muxconf_regs (void) -{ - volatile unsigned int *MuxConfReg; - /* set each registers to its reset value; */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0); - /* setup for UART1 */ - *MuxConfReg &= ~(0x02000000); /* bit 25 */ - /* setup for UART2 */ - *MuxConfReg &= ~(0x01000000); /* bit 24 */ - /* Disable Uwire CS Hi-Z */ - *MuxConfReg |= 0x08000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_3); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_4); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_5); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_6); - /*setup mux for UART3 */ - *MuxConfReg |= 0x00000001; /* bit3, 1, 0 (mux0 5,5,26) */ - *MuxConfReg &= ~0x0000003e; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_7); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_8); - /* Disable Uwire CS Hi-Z */ - *MuxConfReg |= 0x00001200; /*bit 9 for CS0 12 for CS3 */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_9); - /* Need to turn on bits 21 and 12 in FUNC_MUX_CTRL_9 so the */ - /* hardware will actually use TX and RTS based on bit 25 in */ - /* FUNC_MUX_CTRL_0. I told you this thing was screwy! */ - *MuxConfReg |= 0x00201000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_A); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_B); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_C); - /* setup for UART2 */ - /* Need to turn on bits 27 and 24 in FUNC_MUX_CTRL_C so the */ - /* hardware will actually use TX and RTS based on bit 24 in */ - /* FUNC_MUX_CTRL_0. */ - *MuxConfReg |= 0x09000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_D); - *MuxConfReg |= 0x00000020; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_0); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_1); - *MuxConfReg = 0x00000000; - /* mux setup for SD/MMC driver */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_2); - *MuxConfReg &= 0xFFFE0FFF; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_3); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); - /* bit 13 for MMC2 XOR_CLK */ - *MuxConfReg &= ~(0x00002000); - /* bit 29 for UART 1 */ - *MuxConfReg &= ~(0x00002000); - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0); - /* Configure for USB. Turn on VBUS_CTRL and VBUS_MODE. */ - *MuxConfReg |= 0x000C0000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int)USB_TRANSCEIVER_CTRL); - *MuxConfReg &= ~(0x00000070); - *MuxConfReg &= ~(0x00000008); - *MuxConfReg |= 0x00000003; - *MuxConfReg |= 0x00000180; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); - /* bit 17, software controls VBUS */ - *MuxConfReg &= ~(0x00020000); - /* Enable USB 48 and 12M clocks */ - *MuxConfReg |= 0x00000200; - *MuxConfReg &= ~(0x00000180); - /*2.75V for MMCSDIO1 */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) VOLTAGE_CTRL_0); - *MuxConfReg = 0x00001FE7; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_0); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_1); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_3); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_4); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_4); - *MuxConfReg = 0x00000000; - /* Turn on UART2 48 MHZ clock */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); - *MuxConfReg |= 0x40000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) USB_OTG_CTRL); - /* setup for USB VBus detection OMAP161x */ - *MuxConfReg |= 0x00040000; /* bit 18 */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2); - /* PullUps for SD/MMC driver */ - *MuxConfReg |= ~(0xFFFE0FFF); - MuxConfReg = - (volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0); - *MuxConfReg = COMP_MODE_ENABLE; -} - -/****************************************************** - Routine: peripheral_power_enable - Description: Enable the power for UART1 -*******************************************************/ -void peripheral_power_enable (void) -{ -#define UART1_48MHZ_ENABLE ((unsigned short)0x0200) -#define SW_CLOCK_REQUEST ((volatile unsigned short *)0xFFFE0834) - - *SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE; -} - -/* - * Check Board Identity - */ -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - puts("Board: OSK5912"); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return (0); -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_LAN91C96 - rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); -#endif - return rc; -} -#endif diff --git a/common/board_f.c b/common/board_f.c index d5e7622eeb..11aa55597b 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -270,7 +270,7 @@ static int setup_mon_len(void) gd->mon_len = (ulong)&__bss_end - (ulong)_start; #elif defined(CONFIG_SANDBOX) gd->mon_len = (ulong)&_end - (ulong)_init; -#elif defined(CONFIG_BLACKFIN) +#elif defined(CONFIG_BLACKFIN) || defined(CONFIG_NIOS2) gd->mon_len = CONFIG_SYS_MONITOR_LEN; #else /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */ @@ -945,7 +945,7 @@ static init_fnc_t init_sequence_f[] = { * - board info struct */ setup_dest_addr, -#if defined(CONFIG_BLACKFIN) +#if defined(CONFIG_BLACKFIN) || defined(CONFIG_NIOS2) /* Blackfin u-boot monitor should be on top of the ram */ reserve_uboot, #endif @@ -970,7 +970,7 @@ static init_fnc_t init_sequence_f[] = { !defined(CONFIG_BLACKFIN) reserve_video, #endif -#if !defined(CONFIG_BLACKFIN) +#if !defined(CONFIG_BLACKFIN) && !defined(CONFIG_NIOS2) reserve_uboot, #endif #ifndef CONFIG_SPL_BUILD diff --git a/common/board_r.c b/common/board_r.c index ba9a68dc66..f9647e1358 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -133,7 +133,7 @@ static int initr_reloc_global_data(void) { #ifdef __ARM__ monitor_flash_len = _end - __image_copy_start; -#elif !defined(CONFIG_SANDBOX) +#elif !defined(CONFIG_SANDBOX) && !defined(CONFIG_NIOS2) monitor_flash_len = (ulong)&__init_end - gd->relocaddr; #endif #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) diff --git a/common/bootm.c b/common/bootm.c index 76d811c983..ff81a271a5 100644 --- a/common/bootm.c +++ b/common/bootm.c @@ -725,13 +725,15 @@ static const void *boot_get_kernel(cmd_tbl_t *cmdtp, int flag, int argc, #endif ulong img_addr; const void *buf; -#if defined(CONFIG_FIT) const char *fit_uname_config = NULL; const char *fit_uname_kernel = NULL; +#if defined(CONFIG_FIT) int os_noffset; #endif - img_addr = genimg_get_kernel_addr(argv[0]); + img_addr = genimg_get_kernel_addr_fit(argc < 1 ? NULL : argv[0], + &fit_uname_config, + &fit_uname_kernel); bootstage_mark(BOOTSTAGE_ID_CHECK_MAGIC); @@ -788,10 +790,6 @@ static const void *boot_get_kernel(cmd_tbl_t *cmdtp, int flag, int argc, #endif #if defined(CONFIG_FIT) case IMAGE_FORMAT_FIT: - if (!fit_parse_conf(argv[0], load_addr, &img_addr, - &fit_uname_config)) - fit_parse_subimage(argv[0], load_addr, &img_addr, - &fit_uname_kernel); os_noffset = fit_image_load(images, img_addr, &fit_uname_kernel, &fit_uname_config, IH_ARCH_DEFAULT, IH_TYPE_KERNEL, diff --git a/common/cli_simple.c b/common/cli_simple.c index 353ceeb734..6c65cc686c 100644 --- a/common/cli_simple.c +++ b/common/cli_simple.c @@ -57,7 +57,7 @@ int cli_simple_parse_line(char *line, char *argv[]) return nargs; } -static void process_macros(const char *input, char *output) +void cli_simple_process_macros(const char *input, char *output) { char c, prev; const char *varname_start = NULL; @@ -236,7 +236,7 @@ int cli_simple_run_command(const char *cmd, int flag) debug_parser("token: \"%s\"\n", token); /* find macros in this token and replace them */ - process_macros(token, finaltoken); + cli_simple_process_macros(token, finaltoken); /* Extract arguments */ argc = cli_simple_parse_line(finaltoken, argv); diff --git a/common/cmd_pxe.c b/common/cmd_pxe.c index c816339232..0ab1e0aaa6 100644 --- a/common/cmd_pxe.c +++ b/common/cmd_pxe.c @@ -15,6 +15,7 @@ #include <fs.h> #include "menu.h" +#include "cli.h" #define MAX_TFTP_PATH_LEN 127 @@ -578,8 +579,12 @@ static int label_localboot(struct pxe_label *label) if (!localcmd) return -ENOENT; - if (label->append) - setenv("bootargs", label->append); + if (label->append) { + char bootargs[CONFIG_SYS_CBSIZE]; + + cli_simple_process_macros(label->append, bootargs); + setenv("bootargs", bootargs); + } debug("running: %s\n", localcmd); @@ -607,7 +612,6 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label *label) char initrd_str[22]; char mac_str[29] = ""; char ip_str[68] = ""; - char *bootargs; int bootm_argc = 3; int len = 0; ulong kernel_addr; @@ -654,7 +658,6 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label *label) sprintf(ip_str, " ip=%s:%s:%s:%s", getenv("ipaddr"), getenv("serverip"), getenv("gatewayip"), getenv("netmask")); - len += strlen(ip_str); } #ifdef CONFIG_CMD_NET @@ -664,27 +667,21 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label *label) err = format_mac_pxe(mac_str + 8, sizeof(mac_str) - 8); if (err < 0) mac_str[0] = '\0'; - len += strlen(mac_str); } #endif - if (label->append) - len += strlen(label->append); + if ((label->ipappend & 0x3) || label->append) { + char bootargs[CONFIG_SYS_CBSIZE] = ""; + char finalbootargs[CONFIG_SYS_CBSIZE]; - if (len) { - bootargs = malloc(len + 1); - if (!bootargs) - return 1; - bootargs[0] = '\0'; if (label->append) strcpy(bootargs, label->append); strcat(bootargs, ip_str); strcat(bootargs, mac_str); - setenv("bootargs", bootargs); - printf("append: %s\n", bootargs); - - free(bootargs); + cli_simple_process_macros(bootargs, finalbootargs); + setenv("bootargs", finalbootargs); + printf("append: %s\n", finalbootargs); } bootm_argv[1] = getenv("kernel_addr_r"); diff --git a/common/image.c b/common/image.c index a2999c0fba..d4ccff0095 100644 --- a/common/image.c +++ b/common/image.c @@ -643,22 +643,24 @@ int genimg_get_comp_id(const char *name) #ifndef USE_HOSTCC /** - * genimg_get_kernel_addr - get the real kernel address + * genimg_get_kernel_addr_fit - get the real kernel address and return 2 + * FIT strings * @img_addr: a string might contain real image address + * @fit_uname_config: double pointer to a char, will hold pointer to a + * configuration unit name + * @fit_uname_kernel: double pointer to a char, will hold pointer to a subimage + * name * - * genimg_get_kernel_addr() get the real kernel start address from a string + * genimg_get_kernel_addr_fit get the real kernel start address from a string * which is normally the first argv of bootm/bootz * * returns: * kernel start address */ -ulong genimg_get_kernel_addr(char * const img_addr) +ulong genimg_get_kernel_addr_fit(char * const img_addr, + const char **fit_uname_config, + const char **fit_uname_kernel) { -#if defined(CONFIG_FIT) - const char *fit_uname_config = NULL; - const char *fit_uname_kernel = NULL; -#endif - ulong kernel_addr; /* find out kernel image address */ @@ -668,13 +670,13 @@ ulong genimg_get_kernel_addr(char * const img_addr) load_addr); #if defined(CONFIG_FIT) } else if (fit_parse_conf(img_addr, load_addr, &kernel_addr, - &fit_uname_config)) { + fit_uname_config)) { debug("* kernel: config '%s' from image at 0x%08lx\n", - fit_uname_config, kernel_addr); + *fit_uname_config, kernel_addr); } else if (fit_parse_subimage(img_addr, load_addr, &kernel_addr, - &fit_uname_kernel)) { + fit_uname_kernel)) { debug("* kernel: subimage '%s' from image at 0x%08lx\n", - fit_uname_kernel, kernel_addr); + *fit_uname_kernel, kernel_addr); #endif } else { kernel_addr = simple_strtoul(img_addr, NULL, 16); @@ -686,6 +688,19 @@ ulong genimg_get_kernel_addr(char * const img_addr) } /** + * genimg_get_kernel_addr() is the simple version of + * genimg_get_kernel_addr_fit(). It ignores those return FIT strings + */ +ulong genimg_get_kernel_addr(char * const img_addr) +{ + const char *fit_uname_config = NULL; + const char *fit_uname_kernel = NULL; + + return genimg_get_kernel_addr_fit(img_addr, &fit_uname_config, + &fit_uname_kernel); +} + +/** * genimg_get_format - get image format type * @img_addr: image start address * diff --git a/configs/FLAGADM_defconfig b/configs/FLAGADM_defconfig deleted file mode 100644 index 6113797016..0000000000 --- a/configs/FLAGADM_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_FLAGADM=y diff --git a/configs/GEN860T_SC_defconfig b/configs/GEN860T_SC_defconfig deleted file mode 100644 index ff624db32d..0000000000 --- a/configs/GEN860T_SC_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="SC" -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_GEN860T=y diff --git a/configs/GEN860T_defconfig b/configs/GEN860T_defconfig deleted file mode 100644 index e6726230ce..0000000000 --- a/configs/GEN860T_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_GEN860T=y diff --git a/configs/PCI5441_defconfig b/configs/PCI5441_defconfig deleted file mode 100644 index a4bfdb4eb3..0000000000 --- a/configs/PCI5441_defconfig +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_NIOS2=y -CONFIG_TARGET_PCI5441=y diff --git a/configs/PK1C20_defconfig b/configs/PK1C20_defconfig deleted file mode 100644 index bb2513ae1f..0000000000 --- a/configs/PK1C20_defconfig +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_NIOS2=y -CONFIG_TARGET_PK1C20=y diff --git a/configs/SXNI855T_defconfig b/configs/SXNI855T_defconfig deleted file mode 100644 index a4c900ad34..0000000000 --- a/configs/SXNI855T_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_SXNI855T=y diff --git a/configs/omap5912osk_defconfig b/configs/omap5912osk_defconfig deleted file mode 100644 index 5aeb0976b8..0000000000 --- a/configs/omap5912osk_defconfig +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_OMAP5912OSK=y diff --git a/configs/stxxtc_defconfig b/configs/stxxtc_defconfig deleted file mode 100644 index d0642e4dd9..0000000000 --- a/configs/stxxtc_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_STXXTC=y diff --git a/configs/svm_sc8xx_defconfig b/configs/svm_sc8xx_defconfig deleted file mode 100644 index 9f0d343a82..0000000000 --- a/configs/svm_sc8xx_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_SVM_SC8XX=y diff --git a/doc/README.kconfig b/doc/README.kconfig new file mode 100644 index 0000000000..cd549a8a54 --- /dev/null +++ b/doc/README.kconfig @@ -0,0 +1,219 @@ +Kconfig in U-Boot +================= + +This document describes the configuration infrastructure of U-Boot. + +The conventional configuration was replaced by Kconfig at v2014.10-rc1 release. + + +Language Specification +---------------------- + +Kconfig originates in Linux Kernel. +See the file "Documentation/kbuild/kconfig*.txt" in your Linux Kernel +source directory for a basic specification of Kconfig. + + +Difference from Linux's Kconfig +------------------------------- + +The biggest difference between Linux Kernel and U-Boot in terms of the +configuration is that U-Boot has to configure multiple boot images per board: +Normal, SPL, TPL. +Kconfig functions need to be expanded for U-Boot to handle multiple images. +The files scripts/kconfig/* were imported from Linux Kernel and adjusted +for that purpose. + +See below for how each configuration target works in U-Boot: + +- config, nconfig, menuconfig, xconfig, gconfig + + These targets are used to configure Normal and create (or modify) the + .config file. For SPL configuration, the configutation targets are prefixed + with "spl/", for example "make spl/config", "make spl/menuconfig", etc. + Those targets create or modify the spl/.config file. Likewise, run + "make tpl/config", "make tpl/menuconfig", etc. for TPL. + +- silentoldconfig + + This target updates .config, include/generated/autoconf.h and + include/configs/*. In U-Boot, the same thing is done for SPL, TPL, + if supported by the target board. Depending on whether CONFIG_SPL and + CONFIG_TPL are defined, "make silentoldconfig" iterates three times at most + changing the work directory. + + To sum up, "make silentoldconfig" possibly updates: + - .config, include/generated/autoconf.h, include/config/* + - spl/.config, spl/include/generated/autoconf.h, spl/include/config/* + (in case CONFIG_SPL=y) + - tpl/.config, tpl/include/generated/autoconf.h, tpl/include/config/* + (in case CONFIG_TPL=y) + +- defconfig, <board>_defconfig + + The target "<board>_defconfig" is used to create the .config based on the + file configs/<board>_defconfig. The "defconfig" target is the same + except it checks for a file specified with KBUILD_DEFCONFIG environment. + + Note: + The defconfig files are placed under the "configs" directory, + not "arch/$(ARCH)/configs". This is because "ARCH" is not necessarily + given from the command line for the U-Boot configuration and build. + + The defconfig file format in U-Boot has the special syntax; each line has + "<condition>:" prefix to show which image(s) the line is valid for. + For example, + + CONFIG_FOO=100 + S:CONFIG_FOO=200 + T:CONFIG_FOO=300 + ST:CONFIG_BAR=y + +S:CONFIG_BAZ=y + +T:CONFIG_QUX=y + +ST:CONFIG_QUUX=y + + Here, the "<condition>:" prefix is one of: + None - the line is valid only for Normal image + S: - the line is valid only for SPL image + T: - the line is valid only for TPL image + ST: - the line is valid for SPL and TPL images + +S: - the line is valid for Normal and SPL images + +T: - the line is valid for Normal and TPL images + +ST: - the line is valid for Normal, SPL and SPL images + + So, if neither CONFIG_SPL nor CONFIG_TPL is defined, the defconfig file + has no "<condition>:" part and therefore has the same form as in Linux. + From the example defconfig shown above, three separete configuration sets + are generated and used for creating .config, spl/.config and tpl/.config. + + - Input for the default configuration of Normal + CONFIG_FOO=100 + CONFIG_BAZ=y + CONFIG_QUX=y + CONFIG_QUUX=y + + - Input for the default configuration of SPL + CONFIG_FOO=200 + CONFIG_BAR=y + CONFIG_BAZ=y + CONFIG_QUUX=y + + - Input for the default configuration of TPL + CONFIG_FOO=300 + CONFIG_BAR=y + CONFIG_QUX=y + CONFIG_QUUX=y + +- savedefconfig + + This is the reverse operation of "make defconfig". If neither CONFIG_SPL + nor CONFIG_TPL is defined in the .config file, it works like "savedefconfig" + in Linux Kernel: creates the minimal set of config based on the .config + and saves it into the "defconfig" file. If CONFIG_SPL (and CONFIG_TPL) is + defined, the common lines among .config, spl/.config (and tpl/.config) are + coalesced together with "<condition:>" prefix for each line as shown above. + This file can be used as an input of "defconfig" target. + + +Migration steps to Kconfig +-------------------------- + +Prior to Kconfig, the C preprocessor based board configuration had been used +in U-Boot. + +Although Kconfig was introduced and some configs have been moved to Kconfig, +many of configs are still defined in C header files. It will take a very +long term to move all of them to Kconfig. In the interim, the two different +configuration infrastructures should coexist. +The configuration files are generated by both Kconfig and the old preprocessor +based configuration as follows: + +Configuration files for use in C sources + - include/generated/autoconf.h (generated by Kconfig for Normal) + - spl/include/generated/autoconf.h (generated by Kconfig for SPL) + - tpl/include/generated/autoconf.h (generated by Kconfig for TPL) + - include/configs/<board>.h (exists for all boards) + +Configuration file for use in makefiles + - include/config/auto.conf (generated by Kconfig for Normal) + - spl/include/config/auto.conf (generated by Kconfig for SPL) + - tpl/include/config/auto.conf (generated by Kconfig for TPL) + - include/autoconf.mk (generated by the old config for Normal) + - spl/include/autoconfig.mk (generated by the old config for SPL) + - tpl/include/autoconfig.mk (generated by the old config for TPL) + +When adding a new CONFIG macro, it is highly recommended to add it to Kconfig +rather than to a header file. + + +Conversion from boards.cfg to Kconfig +------------------------------------- + +Prior to Kconfig, boards.cfg was a primary database that contained Arch, CPU, +SoC, etc. of all the supported boards. It was deleted when switching to +Kconfig. Each field of boards.cfg was converted as follows: + + Status -> "S:" entry of MAINTAINERS + Arch -> CONFIG_SYS_ARCH defined by Kconfig + CPU -> CONFIG_SYS_CPU defined by Kconfig + SoC -> CONFIG_SYS_SOC defined by Kconfig + Vendor -> CONFIG_SYS_VENDOR defined by Kconfig + Board -> CONFIG_SYS_BOARD defined by Kconfig + Target -> File name of defconfig (configs/<target>_defconfig) + Options -> CONFIG_SYS_EXTRA_OPTIONS defined by Kconfig + Maintainers -> "M:" entry of MAINTAINERS + + +Tips to add/remove boards +------------------------- + +When adding a new board, the following steps are generally needed: + + [1] Add a header file include/configs/<target>.h + [2] Make sure to define necessary CONFIG_SYS_* in Kconfig: + Define CONFIG_SYS_CPU="cpu" to compile arch/<arch>/cpu/<cpu> + Define CONFIG_SYS_SOC="soc" to compile arch/<arch>/cpu/<cpu>/<soc> + Define CONFIG_SYS_VENDOR="vendor" to compile board/<vendor>/common/* + and board/<vendor>/<board>/* + Define CONFIG_SYS_BOARD="board" to compile board/<board>/* + (or board/<vendor>/<board>/* if CONFIG_SYS_VENDOR is defined) + Define CONFIG_SYS_CONFIG_NAME="target" to include + include/configs/<target>.h + [3] Add a new entry to the board select menu in Kconfig. + The board select menu is located in arch/<arch>/Kconfig or + arch/<arch>/*/Kconfig. + [4] Add a MAINTAINERS file + It is generally placed at board/<board>/MAINTAINERS or + board/<vendor>/<board>/MAINTAINERS + [5] Add configs/<target>_defconfig + +When removing an obsolete board, the following steps are generally needed: + + [1] Remove configs/<target>_defconfig + [2] Remove include/configs/<target>.h if it is not used by any other boards + [3] Remove board/<vendor>/<board>/* or board/<board>/* if it is not used + by any other boards + [4] Update MAINTAINERS if necessary + [5] Remove the unused entry from the board select menu in Kconfig + [6] Add an entry to doc/README.scrapyard + + +TODO +---- + +- The option field of boards.cfg, which was used for the pre-Kconfig + configuration, moved to CONFIG_SYS_EXTRA_OPTIONS verbatim now. + Board maintainers are expected to implement proper Kconfig options + and switch over to them. Eventually CONFIG_SYS_EXTRA_OPTIONS will go away. + CONFIG_SYS_EXTRA_OPTIONS should not be used for new boards. + +- In the pre-Kconfig, a single board had multiple entries in the boards.cfg + file with differences in the option fields. The correspoing defconfig files + were auto-generated when switching to Kconfig. Now we have too many + defconfig files compared with the number of the supported boards. It is + recommended to have only one defconfig per board and allow users to select + the config options. + +- Move the config macros in header files to Kconfig. When we move at least + macros used in makefiles, we can drop include/autoconfig.mk, which makes + the build scripts much simpler. diff --git a/doc/README.scrapyard b/doc/README.scrapyard index b950a4174f..7ef5a225d9 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,12 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +flagadm powerpc mpc8xx - - Kári DavÃðsson <kd@flaga.is> +gen860t powerpc mpc8xx - - Keith Outwater <Keith_Outwater@mvis.com> +sixnet powerpc mpc8xx - - Dave Ellis <DGE@sixnetio.com> +svm_sc8xx powerpc mpc8xx - - John Zhan <zhanz@sinovee.com> +stxxtc powerpc mpc8xx - - Dan Malek <dan@embeddedalley.com> +omap5912osk arm arm926ejs - - Rishi Bhattacharya <rishi@ti.com> p1023rds powerpc mpc85xx d0bc5140 2014-07-22 Roy Zang <tie-fei.zang@freescale.com> spc1920 powerpc mpc8xx 98ad54be 2014-07-07 v37 powerpc mpc8xx b8c1438a 2014-07-07 diff --git a/doc/git-mailrc b/doc/git-mailrc index 70405f2c96..0fba1003c4 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -119,3 +119,5 @@ alias net uboot, jhersh alias spi uboot, jagan alias usb uboot, marex alias video uboot, ag +alias patman uboot, sjg +alias buildman uboot, sjg diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 7cc6b6fc08..84b8ec4a31 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -30,7 +30,6 @@ obj-$(CONFIG_FTGMAC100) += ftgmac100.o obj-$(CONFIG_FTMAC110) += ftmac110.o obj-$(CONFIG_FTMAC100) += ftmac100.o obj-$(CONFIG_GRETH) += greth.o -obj-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o obj-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o @@ -46,7 +45,6 @@ obj-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o obj-$(CONFIG_NETCONSOLE) += netconsole.o obj-$(CONFIG_NS8382X) += ns8382x.o obj-$(CONFIG_PCNET) += pcnet.o -obj-$(CONFIG_PLB2800_ETHER) += plb2800_eth.o obj-$(CONFIG_RTL8139) += rtl8139.o obj-$(CONFIG_RTL8169) += rtl8169.o obj-$(CONFIG_SH_ETHER) += sh_eth.o diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 9d9b259d64..0eba57cf0c 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -41,12 +41,12 @@ tested on both gig copper and gig fiber boards /* NIC specific static variables go here */ -static char tx_pool[128 + 16]; -static char rx_pool[128 + 16]; -static char packet[2096]; +/* Intel i210 needs the DMA descriptor rings aligned to 128b */ +#define E1000_BUFFER_ALIGN 128 -static struct e1000_tx_desc *tx_base; -static struct e1000_rx_desc *rx_base; +DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN); +DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN); +DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN); static int tx_tail; static int rx_tail, rx_last; @@ -92,6 +92,12 @@ static struct pci_device_id e1000_supported[] = { {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX}, + {} }; @@ -340,7 +346,7 @@ int32_t e1000_acquire_eeprom(struct e1000_hw *hw) return -E1000_ERR_SWFW_SYNC; eecd = E1000_READ_REG(hw, EECD); - if (hw->mac_type != e1000_82573 || hw->mac_type != e1000_82574) { + if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) { /* Request EEPROM Access */ if (hw->mac_type > e1000_82544) { eecd |= E1000_EECD_REQ; @@ -391,10 +397,15 @@ int32_t e1000_acquire_eeprom(struct e1000_hw *hw) static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) { struct e1000_eeprom_info *eeprom = &hw->eeprom; - uint32_t eecd = E1000_READ_REG(hw, EECD); + uint32_t eecd; int32_t ret_val = E1000_SUCCESS; uint16_t eeprom_size; + if (hw->mac_type == e1000_igb) + eecd = E1000_READ_REG(hw, I210_EECD); + else + eecd = E1000_READ_REG(hw, EECD); + DEBUGFUNC(); switch (hw->mac_type) { @@ -485,9 +496,10 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) eeprom->page_size = 8; eeprom->address_bits = 8; } - eeprom->use_eerd = true; - eeprom->use_eewr = true; if (e1000_is_onboard_nvm_eeprom(hw) == false) { + eeprom->use_eerd = true; + eeprom->use_eewr = true; + eeprom->type = e1000_eeprom_flash; eeprom->word_size = 2048; @@ -511,6 +523,16 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) eeprom->use_eerd = true; eeprom->use_eewr = false; break; + case e1000_igb: + /* i210 has 4k of iNVM mapped as EEPROM */ + eeprom->type = e1000_eeprom_invm; + eeprom->opcode_bits = 8; + eeprom->delay_usec = 1; + eeprom->page_size = 32; + eeprom->address_bits = 16; + eeprom->use_eerd = true; + eeprom->use_eewr = false; + break; /* ich8lan does not support currently. if needed, please * add corresponding code and functions. @@ -552,7 +574,8 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) break; } - if (eeprom->type == e1000_eeprom_spi) { + if (eeprom->type == e1000_eeprom_spi || + eeprom->type == e1000_eeprom_invm) { /* eeprom_size will be an enum [0..8] that maps * to eeprom sizes 128B to * 32KB (incremented by powers of 2). @@ -596,10 +619,17 @@ e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) int32_t done = E1000_ERR_EEPROM; for (i = 0; i < attempts; i++) { - if (eerd == E1000_EEPROM_POLL_READ) - reg = E1000_READ_REG(hw, EERD); - else - reg = E1000_READ_REG(hw, EEWR); + if (eerd == E1000_EEPROM_POLL_READ) { + if (hw->mac_type == e1000_igb) + reg = E1000_READ_REG(hw, I210_EERD); + else + reg = E1000_READ_REG(hw, EERD); + } else { + if (hw->mac_type == e1000_igb) + reg = E1000_READ_REG(hw, I210_EEWR); + else + reg = E1000_READ_REG(hw, EEWR); + } if (reg & E1000_EEPROM_RW_REG_DONE) { done = E1000_SUCCESS; @@ -632,13 +662,23 @@ e1000_read_eeprom_eerd(struct e1000_hw *hw, eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + E1000_EEPROM_RW_REG_START; - E1000_WRITE_REG(hw, EERD, eerd); + if (hw->mac_type == e1000_igb) + E1000_WRITE_REG(hw, I210_EERD, eerd); + else + E1000_WRITE_REG(hw, EERD, eerd); + error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); if (error) break; - data[i] = (E1000_READ_REG(hw, EERD) >> + + if (hw->mac_type == e1000_igb) { + data[i] = (E1000_READ_REG(hw, I210_EERD) >> + E1000_EEPROM_RW_REG_DATA); + } else { + data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA); + } } @@ -949,6 +989,10 @@ e1000_get_software_semaphore(struct e1000_hw *hw) DEBUGFUNC(); + swsm = E1000_READ_REG(hw, SWSM); + swsm &= ~E1000_SWSM_SMBI; + E1000_WRITE_REG(hw, SWSM, swsm); + if (hw->mac_type != e1000_80003es2lan) return E1000_SUCCESS; @@ -1069,7 +1113,7 @@ e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) return -E1000_ERR_SWFW_SYNC; swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); - if (!(swfw_sync & (fwmask | swmask))) + if ((swfw_sync & swmask) && !(swfw_sync & fwmask)) break; /* firmware currently using resource (fwmask) */ @@ -1118,13 +1162,23 @@ e1000_read_mac_addr(struct eth_device *nic) struct e1000_hw *hw = nic->priv; uint16_t offset; uint16_t eeprom_data; + uint32_t reg_data = 0; int i; DEBUGFUNC(); for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { offset = i >> 1; - if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { + if (hw->mac_type == e1000_igb) { + /* i210 preloads MAC address into RAL/RAH registers */ + if (offset == 0) + reg_data = E1000_READ_REG_ARRAY(hw, RA, 0); + else if (offset == 1) + reg_data >>= 16; + else if (offset == 2) + reg_data = E1000_READ_REG_ARRAY(hw, RA, 1); + eeprom_data = reg_data & 0xffff; + } else if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { DEBUGOUT("EEPROM Read Error\n"); return -E1000_ERR_EEPROM; } @@ -1320,6 +1374,13 @@ e1000_set_mac_type(struct e1000_hw *hw) case E1000_DEV_ID_ICH8_IGP_M: hw->mac_type = e1000_ich8lan; break; + case PCI_DEVICE_ID_INTEL_I210_COPPER: + case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS: + case PCI_DEVICE_ID_INTEL_I210_SERDES: + case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS: + case PCI_DEVICE_ID_INTEL_I210_1000BASEKX: + hw->mac_type = e1000_igb; + break; default: /* Should never have loaded on this device */ return -E1000_ERR_MAC_TYPE; @@ -1339,6 +1400,7 @@ e1000_reset_hw(struct e1000_hw *hw) uint32_t ctrl_ext; uint32_t manc; uint32_t pba = 0; + uint32_t reg; DEBUGFUNC(); @@ -1357,6 +1419,8 @@ e1000_reset_hw(struct e1000_hw *hw) /* Clear interrupt mask to stop board from generating interrupts */ DEBUGOUT("Masking off all interrupts\n"); + if (hw->mac_type == e1000_igb) + E1000_WRITE_REG(hw, I210_IAM, 0); E1000_WRITE_REG(hw, IMC, 0xffffffff); /* Disable the Transmit and Receive units. Then delay to allow @@ -1386,7 +1450,15 @@ e1000_reset_hw(struct e1000_hw *hw) E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); /* Force a reload from the EEPROM if necessary */ - if (hw->mac_type < e1000_82540) { + if (hw->mac_type == e1000_igb) { + mdelay(20); + reg = E1000_READ_REG(hw, STATUS); + if (reg & E1000_STATUS_PF_RST_DONE) + DEBUGOUT("PF OK\n"); + reg = E1000_READ_REG(hw, I210_EECD); + if (reg & E1000_EECD_AUTO_RD) + DEBUGOUT("EEC OK\n"); + } else if (hw->mac_type < e1000_82540) { /* Wait for reset to complete */ udelay(10); ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); @@ -1406,6 +1478,8 @@ e1000_reset_hw(struct e1000_hw *hw) /* Clear interrupt mask to stop board from generating interrupts */ DEBUGOUT("Masking off all interrupts\n"); + if (hw->mac_type == e1000_igb) + E1000_WRITE_REG(hw, I210_IAM, 0); E1000_WRITE_REG(hw, IMC, 0xffffffff); /* Clear any pending interrupt events. */ @@ -1415,7 +1489,8 @@ e1000_reset_hw(struct e1000_hw *hw) if (hw->mac_type == e1000_82542_rev2_0) { pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); } - E1000_WRITE_REG(hw, PBA, pba); + if (hw->mac_type != e1000_igb) + E1000_WRITE_REG(hw, PBA, pba); } /****************************************************************************** @@ -1451,6 +1526,10 @@ e1000_initialize_hardware_bits(struct e1000_hw *hw) reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); + /* IGB is cool */ + if (hw->mac_type == e1000_igb) + return; + switch (hw->mac_type) { case e1000_82571: case e1000_82572: @@ -1641,6 +1720,7 @@ e1000_init_hw(struct eth_device *nic) switch (hw->mac_type) { case e1000_82545_rev_3: case e1000_82546_rev_3: + case e1000_igb: break; default: /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ @@ -1670,6 +1750,8 @@ e1000_init_hw(struct eth_device *nic) /* More time needed for PHY to initialize */ if (hw->mac_type == e1000_ich8lan) mdelay(15); + if (hw->mac_type == e1000_igb) + mdelay(15); /* Call a subroutine to configure the link and setup flow control. */ ret_val = e1000_setup_link(nic); @@ -1684,7 +1766,6 @@ e1000_init_hw(struct eth_device *nic) } /* Set the receive descriptor write back policy */ - if (hw->mac_type >= e1000_82571) { ctrl = E1000_READ_REG(hw, RXDCTL); ctrl = @@ -1731,6 +1812,8 @@ e1000_init_hw(struct eth_device *nic) reg_data = E1000_READ_REG(hw, GCR); reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; E1000_WRITE_REG(hw, GCR, reg_data); + case e1000_igb: + break; } #if 0 @@ -1807,6 +1890,7 @@ e1000_setup_link(struct eth_device *nic) case e1000_ich8lan: case e1000_82573: case e1000_82574: + case e1000_igb: hw->fc = e1000_fc_full; break; default: @@ -2267,6 +2351,8 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) if (hw->mac_type == e1000_ich8lan) { phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); + } else if (hw->mac_type == e1000_igb) { + phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL); } else { ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); @@ -2278,6 +2364,9 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) if (hw->mac_type == e1000_ich8lan) { phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); + } else if (hw->mac_type == e1000_igb) { + phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; + E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl); } else { phy_data &= ~IGP02E1000_PM_D0_LPLU; ret_val = e1000_write_phy_reg(hw, @@ -2286,6 +2375,9 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) return ret_val; } + if (hw->mac_type == e1000_igb) + return E1000_SUCCESS; + /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during * Dx states where the power conservation is most important. During * driver activity we should enable SmartSpeed, so performance is @@ -2320,6 +2412,9 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) if (hw->mac_type == e1000_ich8lan) { phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); + } else if (hw->mac_type == e1000_igb) { + phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; + E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl); } else { phy_data |= IGP02E1000_PM_D0_LPLU; ret_val = e1000_write_phy_reg(hw, @@ -2328,6 +2423,9 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) return ret_val; } + if (hw->mac_type == e1000_igb) + return E1000_SUCCESS; + /* When LPLU is enabled we should disable SmartSpeed */ ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); @@ -2549,8 +2647,10 @@ e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data) if (e1000_is_second_port(hw)) swfw = E1000_SWFW_PHY1_SM; - if (e1000_swfw_sync_acquire(hw, swfw)) + if (e1000_swfw_sync_acquire(hw, swfw)) { + debug("%s[%i]\n", __func__, __LINE__); return -E1000_ERR_SWFW_SYNC; + } /* Write register address */ reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & @@ -2985,7 +3085,8 @@ e1000_setup_copper_link(struct eth_device *nic) ret_val = e1000_copper_link_igp_setup(hw); if (ret_val) return ret_val; - } else if (hw->phy_type == e1000_phy_m88) { + } else if (hw->phy_type == e1000_phy_m88 || + hw->phy_type == e1000_phy_igb) { ret_val = e1000_copper_link_mgp_setup(hw); if (ret_val) return ret_val; @@ -3229,7 +3330,8 @@ e1000_config_mac_to_phy(struct e1000_hw *hw) */ ctrl = E1000_READ_REG(hw, CTRL); ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); - ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); + ctrl &= ~(E1000_CTRL_ILOS); + ctrl |= (E1000_CTRL_SPD_SEL); /* Set up duplex in the Device Control and Transmit Control * registers depending on negotiated values. @@ -4255,11 +4357,16 @@ e1000_get_phy_cfg_done(struct e1000_hw *hw) case e1000_82571: case e1000_82572: + case e1000_igb: while (timeout) { - if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) - break; - else - mdelay(1); + if (hw->mac_type == e1000_igb) { + if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask) + break; + } else { + if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) + break; + } + mdelay(1); timeout--; } if (!timeout) { @@ -4488,6 +4595,7 @@ e1000_phy_reset(struct e1000_hw *hw) case e1000_phy_igp_2: case e1000_phy_igp_3: case e1000_phy_ife: + case e1000_phy_igb: ret_val = e1000_phy_hw_reset(hw); if (ret_val) return ret_val; @@ -4550,6 +4658,9 @@ static int e1000_set_phy_type (struct e1000_hw *hw) case BME1000_E_PHY_ID: hw->phy_type = e1000_phy_bm; break; + case I210_I_PHY_ID: + hw->phy_type = e1000_phy_igb; + break; /* Fall Through */ default: /* Should never have loaded on this device */ @@ -4654,6 +4765,10 @@ e1000_detect_gig_phy(struct e1000_hw *hw) if (hw->phy_id == IFE_C_E_PHY_ID) match = true; break; + case e1000_igb: + if (hw->phy_id == I210_I_PHY_ID) + match = true; + break; default: DEBUGOUT("Invalid MAC type %d\n", hw->mac_type); return -E1000_ERR_CONFIG; @@ -4705,6 +4820,7 @@ e1000_set_media_type(struct e1000_hw *hw) case e1000_ich8lan: case e1000_82573: case e1000_82574: + case e1000_igb: /* The STATUS_TBIMODE bit is reserved or reused * for the this device. */ @@ -4773,6 +4889,7 @@ e1000_sw_init(struct eth_device *nic) hw->fc_send_xon = 1; /* Media type - copper or fiber */ + hw->tbi_compatibility_en = true; e1000_set_media_type(hw); if (hw->mac_type >= e1000_82543) { @@ -4789,7 +4906,6 @@ e1000_sw_init(struct eth_device *nic) hw->media_type = e1000_media_type_fiber; } - hw->tbi_compatibility_en = true; hw->wait_autoneg_complete = true; if (hw->mac_type < e1000_82543) hw->report_tx_early = 0; @@ -4803,12 +4919,25 @@ void fill_rx(struct e1000_hw *hw) { struct e1000_rx_desc *rd; + uint32_t flush_start, flush_end; rx_last = rx_tail; rd = rx_base + rx_tail; rx_tail = (rx_tail + 1) % 8; memset(rd, 0, 16); - rd->buffer_addr = cpu_to_le64((u32) & packet); + rd->buffer_addr = cpu_to_le64((u32)packet); + + /* + * Make sure there are no stale data in WB over this area, which + * might get written into the memory while the e1000 also writes + * into the same memory area. + */ + invalidate_dcache_range((u32)packet, (u32)packet + 4096); + /* Dump the DMA descriptor into RAM. */ + flush_start = ((u32)rd) & ~(ARCH_DMA_MINALIGN - 1); + flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN); + flush_dcache_range(flush_start, flush_end); + E1000_WRITE_REG(hw, RDT, rx_tail); } @@ -4822,17 +4951,10 @@ fill_rx(struct e1000_hw *hw) static void e1000_configure_tx(struct e1000_hw *hw) { - unsigned long ptr; unsigned long tctl; unsigned long tipg, tarc; uint32_t ipgr1, ipgr2; - ptr = (u32) tx_pool; - if (ptr & 0xf) - ptr = (ptr + 0x10) & (~0xf); - - tx_base = (typeof(tx_base)) ptr; - E1000_WRITE_REG(hw, TDBAL, (u32) tx_base); E1000_WRITE_REG(hw, TDBAH, 0); @@ -4901,7 +5023,22 @@ e1000_configure_tx(struct e1000_hw *hw) hw->txd_cmd |= E1000_TXD_CMD_RPS; else hw->txd_cmd |= E1000_TXD_CMD_RS; + + + if (hw->mac_type == e1000_igb) { + E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10); + + uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL); + reg_txdctl |= 1 << 25; + E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); + mdelay(20); + } + + + E1000_WRITE_REG(hw, TCTL, tctl); + + } /** @@ -4941,7 +5078,6 @@ e1000_setup_rctl(struct e1000_hw *hw) static void e1000_configure_rx(struct e1000_hw *hw) { - unsigned long ptr; unsigned long rctl, ctrl_ext; rx_tail = 0; /* make sure receives are disabled while setting up the descriptors */ @@ -4963,10 +5099,6 @@ e1000_configure_rx(struct e1000_hw *hw) E1000_WRITE_FLUSH(hw); } /* Setup the Base and Length of the Rx Descriptor Ring */ - ptr = (u32) rx_pool; - if (ptr & 0xf) - ptr = (ptr + 0x10) & (~0xf); - rx_base = (typeof(rx_base)) ptr; E1000_WRITE_REG(hw, RDBAL, (u32) rx_base); E1000_WRITE_REG(hw, RDBAH, 0); @@ -4977,7 +5109,16 @@ e1000_configure_rx(struct e1000_hw *hw) E1000_WRITE_REG(hw, RDT, 0); /* Enable Receives */ + if (hw->mac_type == e1000_igb) { + + uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL); + reg_rxdctl |= 1 << 25; + E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl); + mdelay(20); + } + E1000_WRITE_REG(hw, RCTL, rctl); + fill_rx(hw); } @@ -4989,12 +5130,25 @@ e1000_poll(struct eth_device *nic) { struct e1000_hw *hw = nic->priv; struct e1000_rx_desc *rd; + uint32_t inval_start, inval_end; + uint32_t len; + /* return true if there's an ethernet packet ready to read */ rd = rx_base + rx_last; + + /* Re-load the descriptor from RAM. */ + inval_start = ((u32)rd) & ~(ARCH_DMA_MINALIGN - 1); + inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN); + invalidate_dcache_range(inval_start, inval_end); + if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD) return 0; /*DEBUGOUT("recv: packet len=%d \n", rd->length); */ - NetReceive((uchar *)packet, le32_to_cpu(rd->length)); + /* Packet received, make sure the data are re-loaded from RAM. */ + len = le32_to_cpu(rd->length); + invalidate_dcache_range((u32)packet, + (u32)packet + roundup(len, ARCH_DMA_MINALIGN)); + NetReceive((uchar *)packet, len); fill_rx(hw); return 1; } @@ -5002,12 +5156,13 @@ e1000_poll(struct eth_device *nic) /************************************************************************** TRANSMIT - Transmit a frame ***************************************************************************/ -static int e1000_transmit(struct eth_device *nic, void *packet, int length) +static int e1000_transmit(struct eth_device *nic, void *txpacket, int length) { - void *nv_packet = (void *)packet; + void *nv_packet = (void *)txpacket; struct e1000_hw *hw = nic->priv; struct e1000_tx_desc *txp; int i = 0; + uint32_t flush_start, flush_end; txp = tx_base + tx_tail; tx_tail = (tx_tail + 1) % 8; @@ -5015,10 +5170,22 @@ static int e1000_transmit(struct eth_device *nic, void *packet, int length) txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet)); txp->lower.data = cpu_to_le32(hw->txd_cmd | length); txp->upper.data = 0; + + /* Dump the packet into RAM so e1000 can pick them. */ + flush_dcache_range((u32)nv_packet, + (u32)nv_packet + roundup(length, ARCH_DMA_MINALIGN)); + /* Dump the descriptor into RAM as well. */ + flush_start = ((u32)txp) & ~(ARCH_DMA_MINALIGN - 1); + flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN); + flush_dcache_range(flush_start, flush_end); + E1000_WRITE_REG(hw, TDT, tx_tail); E1000_WRITE_FLUSH(hw); - while (!(le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)) { + while (1) { + invalidate_dcache_range(flush_start, flush_end); + if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD) + break; if (i++ > TOUT_LOOP) { DEBUGOUT("e1000: tx timeout\n"); return 0; @@ -5113,9 +5280,8 @@ void e1000_get_bus_type(struct e1000_hw *hw) case e1000_82573: case e1000_82574: case e1000_80003es2lan: - hw->bus_type = e1000_bus_type_pci_express; - break; case e1000_ich8lan: + case e1000_igb: hw->bus_type = e1000_bus_type_pci_express; break; default: @@ -5196,6 +5362,7 @@ e1000_initialize(bd_t * bis) hw->autoneg_failed = 0; hw->autoneg = 1; hw->get_link_status = true; + hw->eeprom_semaphore_present = true; hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); hw->mac_type = e1000_undefined; @@ -5219,7 +5386,8 @@ e1000_initialize(bd_t * bis) E1000_ERR(nic, "EEPROM is invalid!\n"); continue; } - if (e1000_validate_eeprom_checksum(hw)) + if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) && + e1000_validate_eeprom_checksum(hw)) continue; #endif e1000_read_mac_addr(nic); diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h index ff87af2ef8..b025ecc4fc 100644 --- a/drivers/net/e1000.h +++ b/drivers/net/e1000.h @@ -100,6 +100,7 @@ typedef enum { e1000_82574, e1000_80003es2lan, e1000_ich8lan, + e1000_igb, e1000_num_macs } e1000_mac_type; @@ -118,6 +119,7 @@ typedef enum { e1000_eeprom_flash, e1000_eeprom_ich8, e1000_eeprom_none, /* No NVM support */ + e1000_eeprom_invm, e1000_num_eeprom_types } e1000_eeprom_type; @@ -212,6 +214,7 @@ typedef enum { e1000_phy_gg82563, e1000_phy_igp_3, e1000_phy_ife, + e1000_phy_igb, e1000_phy_bm, e1000_phy_undefined = 0xFF } e1000_phy_type; @@ -686,7 +689,9 @@ struct e1000_ffvt_entry { #define E1000_CTRL 0x00000 /* Device Control - RW */ #define E1000_STATUS 0x00008 /* Device Status - RO */ #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ +#define E1000_I210_EECD 0x12010 /* EEPROM/Flash Control - RW */ #define E1000_EERD 0x00014 /* EEPROM Read - RW */ +#define E1000_I210_EERD 0x12014 /* EEPROM Read - RW */ #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ #define E1000_MDIC 0x00020 /* MDI Control - RW */ #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ @@ -698,6 +703,7 @@ struct e1000_ffvt_entry { #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ +#define E1000_I210_IAM 0x000E0 /* Interrupt Ack Auto Mask - RW */ #define E1000_RCTL 0x00100 /* RX Control - RW */ #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ #define E1000_TXCW 0x00178 /* TX Configuration Word - RW */ @@ -711,14 +717,17 @@ struct e1000_ffvt_entry { #define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ #define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */ +#define E1000_I210_PHY_CTRL 0x00E14 /* PHY Control Register in CSR */ #define FEXTNVM_SW_CONFIG 0x0001 #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ #define E1000_PBS 0x01008 /* Packet Buffer Size */ #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ +#define E1000_I210_EEMNGCTL 0x12030 /* MNG EEprom Control */ #define E1000_FLASH_UPDATES 1000 #define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */ #define E1000_FLASHT 0x01028 /* FLASH Timer Register */ #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ +#define E1000_I210_EEWR 0x12018 /* EEPROM Write Register - RW */ #define E1000_FLSWCTL 0x01030 /* FLASH control register */ #define E1000_FLSWDATA 0x01034 /* FLASH data register */ #define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */ @@ -1222,6 +1231,7 @@ struct e1000_hw { #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ +#define E1000_STATUS_PF_RST_DONE 0x00200000 /* PCI-X bus speed */ /* Constants used to intrepret the masked PCI-X bus speed. */ #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */ @@ -2438,6 +2448,8 @@ struct e1000_hw { #define BME1000_E_PHY_ID 0x01410CB0 +#define I210_I_PHY_ID 0x01410C00 + /* Miscellaneous PHY bit definitions. */ #define PHY_PREAMBLE 0xFFFFFFFF #define PHY_SOF 0x01 diff --git a/drivers/net/fm/t4240.c b/drivers/net/fm/t4240.c index 1eacb22841..ae5aca4bb4 100644 --- a/drivers/net/fm/t4240.c +++ b/drivers/net/fm/t4240.c @@ -71,6 +71,11 @@ phy_interface_t fman_port_enet_if(enum fm_port port) (is_serdes_configured(XFI_FM1_MAC10)))) return PHY_INTERFACE_MODE_XGMII; + if ((port == FM1_DTSEC9 || port == FM1_DTSEC10) && + ((is_serdes_configured(XFI_FM1_MAC9)) || + (is_serdes_configured(XFI_FM1_MAC10)))) + return PHY_INTERFACE_MODE_XGMII; + if ((port == FM2_10GEC1 || port == FM2_10GEC2) && ((is_serdes_configured(XAUI_FM2_MAC9)) || (is_serdes_configured(XAUI_FM2_MAC10)) || diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index dbf7bf7058..9556536b77 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -15,7 +15,6 @@ obj-$(CONFIG_PHY_ATHEROS) += atheros.o obj-$(CONFIG_PHY_BROADCOM) += broadcom.o obj-$(CONFIG_PHY_DAVICOM) += davicom.o obj-$(CONFIG_PHY_ET1011C) += et1011c.o -obj-$(CONFIG_PHY_ICPLUS) += icplus.o obj-$(CONFIG_PHY_LXT) += lxt.o obj-$(CONFIG_PHY_MARVELL) += marvell.o obj-$(CONFIG_PHY_MICREL) += micrel.o diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c deleted file mode 100644 index 597195580b..0000000000 --- a/drivers/net/phy/icplus.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * ICPlus PHY drivers - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Copyright (c) 2007 Freescale Semiconductor, Inc. - */ -#include <phy.h> - -/* IP101A/G - IP1001 */ -#define IP10XX_SPEC_CTRL_STATUS 16 /* Spec. Control Register */ -#define IP1001_SPEC_CTRL_STATUS_2 20 /* IP1001 Spec. Control Reg 2 */ -#define IP1001_PHASE_SEL_MASK 3 /* IP1001 RX/TXPHASE_SEL */ -#define IP1001_APS_ON 11 /* IP1001 APS Mode bit */ -#define IP101A_G_APS_ON 2 /* IP101A/G APS Mode bit */ -#define IP101A_G_IRQ_CONF_STATUS 0x11 /* Conf Info IRQ & Status Reg */ -#define IP101A_G_IRQ_PIN_USED (1<<15) /* INTR pin used */ -#define IP101A_G_IRQ_DEFAULT IP101A_G_IRQ_PIN_USED - -static int ip1001_config(struct phy_device *phydev) -{ - int c; - - /* Enable Auto Power Saving mode */ - c = phy_read(phydev, MDIO_DEVAD_NONE, IP1001_SPEC_CTRL_STATUS_2); - if (c < 0) - return c; - c |= IP1001_APS_ON; - c = phy_write(phydev, MDIO_DEVAD_NONE, IP1001_SPEC_CTRL_STATUS_2, c); - if (c < 0) - return c; - - /* INTR pin used: speed/link/duplex will cause an interrupt */ - c = phy_write(phydev, MDIO_DEVAD_NONE, IP101A_G_IRQ_CONF_STATUS, - IP101A_G_IRQ_DEFAULT); - if (c < 0) - return c; - - if (phydev->interface == PHY_INTERFACE_MODE_RGMII) { - /* - * Additional delay (2ns) used to adjust RX clock phase - * at RGMII interface - */ - c = phy_read(phydev, MDIO_DEVAD_NONE, IP10XX_SPEC_CTRL_STATUS); - if (c < 0) - return c; - - c |= IP1001_PHASE_SEL_MASK; - c = phy_write(phydev, MDIO_DEVAD_NONE, IP10XX_SPEC_CTRL_STATUS, - c); - if (c < 0) - return c; - } - - return 0; -} - -static int ip1001_startup(struct phy_device *phydev) -{ - genphy_update_link(phydev); - genphy_parse_link(phydev); - - return 0; -} -static struct phy_driver IP1001_driver = { - .name = "ICPlus IP1001", - .uid = 0x02430d90, - .mask = 0x0ffffff0, - .features = PHY_GBIT_FEATURES, - .config = &ip1001_config, - .startup = &ip1001_startup, - .shutdown = &genphy_shutdown, -}; - -int phy_icplus_init(void) -{ - phy_register(&IP1001_driver); - - return 0; -} diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index aac85c4d09..1d6c14f2ad 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -454,9 +454,6 @@ int phy_init(void) #ifdef CONFIG_PHY_ET1011C phy_et1011c_init(); #endif -#ifdef CONFIG_PHY_ICPLUS - phy_icplus_init(); -#endif #ifdef CONFIG_PHY_LXT phy_lxt_init(); #endif diff --git a/drivers/net/plb2800_eth.c b/drivers/net/plb2800_eth.c deleted file mode 100644 index f869514f29..0000000000 --- a/drivers/net/plb2800_eth.c +++ /dev/null @@ -1,373 +0,0 @@ -/* - * PLB2800 internal switch ethernet driver. - * - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <malloc.h> -#include <net.h> -#include <netdev.h> -#include <asm/addrspace.h> - - -#define NUM_RX_DESC PKTBUFSRX -#define TOUT_LOOP 1000000 - -#define LONG_REF(addr) (*((volatile unsigned long*)addr)) - -#define CMAC_CRX_CTRL LONG_REF(0xb800c870) -#define CMAC_CTX_CTRL LONG_REF(0xb800c874) -#define SYS_MAC_ADDR_0 LONG_REF(0xb800c878) -#define SYS_MAC_ADDR_1 LONG_REF(0xb800c87c) -#define MIPS_H_MASK LONG_REF(0xB800C810) - -#define MA_LEARN LONG_REF(0xb8008004) -#define DA_LOOKUP LONG_REF(0xb8008008) - -#define CMAC_CRX_CTRL_PD 0x00000001 -#define CMAC_CRX_CTRL_CG 0x00000002 -#define CMAC_CRX_CTRL_PL_SHIFT 2 -#define CMAC_CRIT 0x0 -#define CMAC_NON_CRIT 0x1 -#define MBOX_STAT_ID_SHF 28 -#define MBOX_STAT_CP 0x80000000 -#define MBOX_STAT_MB 0x00000001 -#define EN_MA_LEARN 0x02000000 -#define EN_DA_LKUP 0x01000000 -#define MA_DEST_SHF 11 -#define DA_DEST_SHF 11 -#define DA_STATE_SHF 19 -#define TSTAMP_MS 0x00000000 -#define SW_H_MBOX4_MASK 0x08000000 -#define SW_H_MBOX3_MASK 0x04000000 -#define SW_H_MBOX2_MASK 0x02000000 -#define SW_H_MBOX1_MASK 0x01000000 - -typedef volatile struct { - unsigned int stat; - unsigned int cmd; - unsigned int cnt; - unsigned int adr; -} mailbox_t; - -#define MBOX_REG(mb) ((mailbox_t*)(0xb800c830+(mb<<4))) - -typedef volatile struct { - unsigned int word0; - unsigned int word1; - unsigned int word2; -} mbhdr_t; - -#define MBOX_MEM(mb) ((void*)(0xb800a000+((3-mb)<<11))) - - -static int plb2800_eth_init(struct eth_device *dev, bd_t * bis); -static int plb2800_eth_send(struct eth_device *dev, void *packet, int length); -static int plb2800_eth_recv(struct eth_device *dev); -static void plb2800_eth_halt(struct eth_device *dev); - -static void plb2800_set_mac_addr(struct eth_device *dev, unsigned char * addr); -static unsigned char * plb2800_get_mac_addr(void); - -static int rx_new; -static int mac_addr_set = 0; - - -int plb2800_eth_initialize(bd_t * bis) -{ - struct eth_device *dev; - ulong temp; - -#ifdef DEBUG - printf("Entered plb2800_eth_initialize()\n"); -#endif - - if (!(dev = (struct eth_device *) malloc (sizeof *dev))) - { - printf("Failed to allocate memory\n"); - return -1; - } - memset(dev, 0, sizeof(*dev)); - - sprintf(dev->name, "PLB2800 Switch"); - dev->init = plb2800_eth_init; - dev->halt = plb2800_eth_halt; - dev->send = plb2800_eth_send; - dev->recv = plb2800_eth_recv; - - eth_register(dev); - - /* bug fix */ - *(ulong *)0xb800e800 = 0x838; - - /* Set MBOX ownership */ - temp = CMAC_CRIT << MBOX_STAT_ID_SHF; - MBOX_REG(0)->stat = temp; - MBOX_REG(1)->stat = temp; - - temp = CMAC_NON_CRIT << MBOX_STAT_ID_SHF; - MBOX_REG(2)->stat = temp; - MBOX_REG(3)->stat = temp; - - plb2800_set_mac_addr(dev, plb2800_get_mac_addr()); - - /* Disable all Mbox interrupt */ - temp = MIPS_H_MASK; - temp &= ~ (SW_H_MBOX1_MASK | SW_H_MBOX2_MASK | SW_H_MBOX3_MASK | SW_H_MBOX4_MASK) ; - MIPS_H_MASK = temp; - -#ifdef DEBUG - printf("Leaving plb2800_eth_initialize()\n"); -#endif - - return 0; -} - -static int plb2800_eth_init(struct eth_device *dev, bd_t * bis) -{ -#ifdef DEBUG - printf("Entering plb2800_eth_init()\n"); -#endif - - plb2800_set_mac_addr(dev, dev->enetaddr); - - rx_new = 0; - -#ifdef DEBUG - printf("Leaving plb2800_eth_init()\n"); -#endif - - return 0; -} - - -static int plb2800_eth_send(struct eth_device *dev, void *packet, int length) -{ - int i; - int res = -1; - u32 temp; - mailbox_t * mb = MBOX_REG(0); - char * mem = MBOX_MEM(0); - -#ifdef DEBUG - printf("Entered plb2800_eth_send()\n"); -#endif - - if (length <= 0) - { - printf ("%s: bad packet size: %d\n", dev->name, length); - goto Done; - } - - if (length < 64) - { - length = 64; - } - - temp = CMAC_CRX_CTRL_CG | ((length + 4) << CMAC_CRX_CTRL_PL_SHIFT); - -#ifdef DEBUG - printf("0 mb->stat = 0x%x\n", mb->stat); -#endif - - for(i = 0; mb->stat & (MBOX_STAT_CP | MBOX_STAT_MB); i++) - { - if (i >= TOUT_LOOP) - { - printf("%s: tx buffer not ready\n", dev->name); - printf("1 mb->stat = 0x%x\n", mb->stat); - goto Done; - } - } - - /* For some strange reason, memcpy doesn't work, here! - */ - do - { - int words = (length >> 2) + 1; - unsigned int* dst = (unsigned int*)(mem); - unsigned int* src = (unsigned int*)(packet); - for (i = 0; i < words; i++) - { - *dst = *src; - dst++; - src++; - }; - } while(0); - - CMAC_CRX_CTRL = temp; - mb->cmd = MBOX_STAT_CP; - -#ifdef DEBUG - printf("2 mb->stat = 0x%x\n", mb->stat); -#endif - - res = length; -Done: - -#ifdef DEBUG - printf("Leaving plb2800_eth_send()\n"); -#endif - - return res; -} - - -static int plb2800_eth_recv(struct eth_device *dev) -{ - int length = 0; - mailbox_t * mbox = MBOX_REG(3); - unsigned char * hdr = MBOX_MEM(3); - unsigned int stat; - -#ifdef DEBUG - printf("Entered plb2800_eth_recv()\n"); -#endif - - for (;;) - { - stat = mbox->stat; - - if (!(stat & MBOX_STAT_CP)) - { - break; - } - - length = ((*(hdr + 6) & 0x3f) << 8) + *(hdr + 7); - memcpy((void *)NetRxPackets[rx_new], hdr + 12, length); - - stat &= ~MBOX_STAT_CP; - mbox->stat = stat; -#ifdef DEBUG - { - int i; - for (i=0;i<length - 4;i++) - { - if (i % 16 == 0) printf("\n%04x: ", i); - printf("%02X ", NetRxPackets[rx_new][i]); - } - printf("\n"); - } -#endif - - if (length) - { -#ifdef DEBUG - printf("Received %d bytes\n", length); -#endif - NetReceive((void*)(NetRxPackets[rx_new]), - length - 4); - } - else - { -#if 1 - printf("Zero length!!!\n"); -#endif - } - - rx_new = (rx_new + 1) % NUM_RX_DESC; - } - -#ifdef DEBUG - printf("Leaving plb2800_eth_recv()\n"); -#endif - - return length; -} - - -static void plb2800_eth_halt(struct eth_device *dev) -{ -#ifdef DEBUG - printf("Entered plb2800_eth_halt()\n"); -#endif - -#ifdef DEBUG - printf("Leaving plb2800_eth_halt()\n"); -#endif -} - -static void plb2800_set_mac_addr(struct eth_device *dev, unsigned char * addr) -{ - char packet[60]; - ulong temp; - int ix; - - if (mac_addr_set || - NULL == addr || memcmp(addr, "\0\0\0\0\0\0", 6) == 0) - { - return; - } - - /* send one packet through CPU port - * in order to learn system MAC address - */ - - /* Set DA_LOOKUP register */ - temp = EN_MA_LEARN | (0 << DA_STATE_SHF) | (63 << DA_DEST_SHF); - DA_LOOKUP = temp; - - /* Set MA_LEARN register */ - temp = 50 << MA_DEST_SHF; /* static entry */ - MA_LEARN = temp; - - /* set destination address */ - for (ix=0;ix<6;ix++) - packet[ix] = 0xff; - - /* set source address = system MAC address */ - for (ix=0;ix<6;ix++) - packet[6+ix] = addr[ix]; - - /* set type field */ - packet[12]=0xaa; - packet[13]=0x55; - - /* set data field */ - for(ix=14;ix<60;ix++) - packet[ix] = 0x00; - -#ifdef DEBUG - for (ix=0;ix<6;ix++) - printf("mac_addr[%d]=%02X\n", ix, (unsigned char)packet[6+ix]); -#endif - - /* set one packet */ - plb2800_eth_send(dev, packet, sizeof(packet)); - - /* delay for a while */ - for(ix=0;ix<65535;ix++) - temp = ~temp; - - /* Set CMAC_CTX_CTRL register */ - temp = TSTAMP_MS; /* no autocast */ - CMAC_CTX_CTRL = temp; - - /* Set DA_LOOKUP register */ - temp = EN_DA_LKUP; - DA_LOOKUP = temp; - - mac_addr_set = 1; -} - -static unsigned char * plb2800_get_mac_addr(void) -{ - static unsigned char addr[6]; - char *tmp, *end; - int i; - - tmp = getenv ("ethaddr"); - if (NULL == tmp) return NULL; - - for (i=0; i<6; i++) { - addr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; - if (tmp) - tmp = (*end) ? end+1 : end; - } - - return addr; -} diff --git a/drivers/pcmcia/tqm8xx_pcmcia.c b/drivers/pcmcia/tqm8xx_pcmcia.c index dda7d37445..8b7447853b 100644 --- a/drivers/pcmcia/tqm8xx_pcmcia.c +++ b/drivers/pcmcia/tqm8xx_pcmcia.c @@ -20,14 +20,12 @@ #endif #if defined(CONFIG_PCMCIA) \ - && (defined(CONFIG_TQM8xxL) || defined(CONFIG_SVM_SC8xx)) + && defined(CONFIG_TQM8xxL) #if defined(CONFIG_VIRTLAB2) #define PCMCIA_BOARD_MSG "Virtlab2" #elif defined(CONFIG_TQM8xxL) #define PCMCIA_BOARD_MSG "TQM8xxL" -#elif defined(CONFIG_SVM_SC8xx) -#define PCMCIA_BOARD_MSG "SC8xx" #endif #if defined(CONFIG_NSCU) @@ -302,4 +300,4 @@ done: return 0; } -#endif /* CONFIG_PCMCIA && (CONFIG_TQM8xxL || CONFIG_SVM_SC8xx) */ +#endif /* CONFIG_PCMCIA && CONFIG_TQM8xxL */ diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index 4eea907d2e..2efd5a4d5b 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -31,7 +31,6 @@ ifdef CONFIG_USB_DEVICE obj-y += core.o obj-y += ep0.o obj-$(CONFIG_DW_UDC) += designware_udc.o -obj-$(CONFIG_OMAP1610) += omap1510_udc.o obj-$(CONFIG_MPC885_FAMILY) += mpc8xx_udc.o obj-$(CONFIG_CPU_PXA27X) += pxa27x_udc.o endif diff --git a/drivers/usb/gadget/omap1510_udc.c b/drivers/usb/gadget/omap1510_udc.c deleted file mode 100644 index 959df8cdcd..0000000000 --- a/drivers/usb/gadget/omap1510_udc.c +++ /dev/null @@ -1,1506 +0,0 @@ -/* - * (C) Copyright 2003 - * Gerry Hamel, geh@ti.com, Texas Instruments - * - * Based on - * linux/drivers/usb/device/bi/omap.c - * TI OMAP1510 USB bus interface driver - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * (C) Copyright 2002 - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <usbdevice.h> -#include <usb/omap1510_udc.h> -#include <usb/udc.h> - -#include "ep0.h" - - -#define UDC_INIT_MDELAY 80 /* Device settle delay */ -#define UDC_MAX_ENDPOINTS 31 /* Number of endpoints on this UDC */ - -/* Some kind of debugging output... */ -#if 1 -#define UDCDBG(str) -#define UDCDBGA(fmt,args...) -#else /* The bugs still exists... */ -#define UDCDBG(str) serial_printf("[%s] %s:%d: " str "\n", __FILE__,__FUNCTION__,__LINE__) -#define UDCDBGA(fmt,args...) serial_printf("[%s] %s:%d: " fmt "\n", __FILE__,__FUNCTION__,__LINE__, ##args) -#endif - -#if 1 -#define UDCREG(name) -#define UDCREGL(name) -#else /* The bugs still exists... */ -#define UDCREG(name) serial_printf("%s():%d: %s[%08x]=%.4x\n",__FUNCTION__,__LINE__, (#name), name, inw(name)) /* For 16-bit regs */ -#define UDCREGL(name) serial_printf("%s():%d: %s[%08x]=%.8x\n",__FUNCTION__,__LINE__, (#name), name, inl(name)) /* For 32-bit regs */ -#endif - - -static struct urb *ep0_urb = NULL; - -static struct usb_device_instance *udc_device; /* Used in interrupt handler */ -static u16 udc_devstat = 0; /* UDC status (DEVSTAT) */ -static u32 udc_interrupts = 0; - -static void udc_stall_ep (unsigned int ep_addr); - - -static struct usb_endpoint_instance *omap1510_find_ep (int ep) -{ - int i; - - for (i = 0; i < udc_device->bus->max_endpoints; i++) { - if (udc_device->bus->endpoint_array[i].endpoint_address == ep) - return &udc_device->bus->endpoint_array[i]; - } - return NULL; -} - -/* ************************************************************************** */ -/* IO - */ - -/* - * omap1510_prepare_endpoint_for_rx - * - * This function implements TRM Figure 14-11. - * - * The endpoint to prepare for transfer is specified as a physical endpoint - * number. For OUT (rx) endpoints 1 through 15, the corresponding endpoint - * configuration register is checked to see if the endpoint is ISO or not. - * If the OUT endpoint is valid and is non-ISO then its FIFO is enabled. - * No action is taken for endpoint 0 or for IN (tx) endpoints 16 through 30. - */ -static void omap1510_prepare_endpoint_for_rx (int ep_addr) -{ - int ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK; - - UDCDBGA ("omap1510_prepare_endpoint %x", ep_addr); - if (((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT)) { - if ((inw (UDC_EP_RX (ep_num)) & - (UDC_EPn_RX_Valid | UDC_EPn_RX_Iso)) == - UDC_EPn_RX_Valid) { - /* rx endpoint is valid, non-ISO, so enable its FIFO */ - outw (UDC_EP_Sel | ep_num, UDC_EP_NUM); - outw (UDC_Set_FIFO_En, UDC_CTRL); - outw (0, UDC_EP_NUM); - } - } -} - -/* omap1510_configure_endpoints - * - * This function implements TRM Figure 14-10. - */ -static void omap1510_configure_endpoints (struct usb_device_instance *device) -{ - int ep; - struct usb_bus_instance *bus; - struct usb_endpoint_instance *endpoint; - unsigned short ep_ptr; - unsigned short ep_size; - unsigned short ep_isoc; - unsigned short ep_doublebuffer; - int ep_addr; - int packet_size; - int buffer_size; - int attributes; - - bus = device->bus; - - /* There is a dedicated 2048 byte buffer for USB packets that may be - * arbitrarily partitioned among the endpoints on 8-byte boundaries. - * The first 8 bytes are reserved for receiving setup packets on - * endpoint 0. - */ - ep_ptr = 8; /* reserve the first 8 bytes for the setup fifo */ - - for (ep = 0; ep < bus->max_endpoints; ep++) { - endpoint = bus->endpoint_array + ep; - ep_addr = endpoint->endpoint_address; - if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { - /* IN endpoint */ - packet_size = endpoint->tx_packetSize; - attributes = endpoint->tx_attributes; - } else { - /* OUT endpoint */ - packet_size = endpoint->rcv_packetSize; - attributes = endpoint->rcv_attributes; - } - - switch (packet_size) { - case 0: - ep_size = 0; - break; - case 8: - ep_size = 0; - break; - case 16: - ep_size = 1; - break; - case 32: - ep_size = 2; - break; - case 64: - ep_size = 3; - break; - case 128: - ep_size = 4; - break; - case 256: - ep_size = 5; - break; - case 512: - ep_size = 6; - break; - default: - UDCDBGA ("ep 0x%02x has bad packet size %d", - ep_addr, packet_size); - packet_size = 0; - ep_size = 0; - break; - } - - switch (attributes & USB_ENDPOINT_XFERTYPE_MASK) { - case USB_ENDPOINT_XFER_CONTROL: - case USB_ENDPOINT_XFER_BULK: - case USB_ENDPOINT_XFER_INT: - default: - /* A non-isochronous endpoint may optionally be - * double-buffered. For now we disable - * double-buffering. - */ - ep_doublebuffer = 0; - ep_isoc = 0; - if (packet_size > 64) - packet_size = 0; - if (!ep || !ep_doublebuffer) - buffer_size = packet_size; - else - buffer_size = packet_size * 2; - break; - case USB_ENDPOINT_XFER_ISOC: - /* Isochronous endpoints are always double- - * buffered, but the double-buffering bit - * in the endpoint configuration register - * becomes the msb of the endpoint size so we - * set the double-buffering flag to zero. - */ - ep_doublebuffer = 0; - ep_isoc = 1; - buffer_size = packet_size * 2; - break; - } - - /* check to see if our packet buffer RAM is exhausted */ - if ((ep_ptr + buffer_size) > 2048) { - UDCDBGA ("out of packet RAM for ep 0x%02x buf size %d", ep_addr, buffer_size); - buffer_size = packet_size = 0; - } - - /* force a default configuration for endpoint 0 since it is - * always enabled - */ - if (!ep && ((packet_size < 8) || (packet_size > 64))) { - buffer_size = packet_size = 64; - ep_size = 3; - } - - if (!ep) { - /* configure endpoint 0 */ - outw ((ep_size << 12) | (ep_ptr >> 3), UDC_EP0); - /*UDCDBGA("ep 0 buffer offset 0x%03x packet size 0x%03x", */ - /* ep_ptr, packet_size); */ - } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { - /* IN endpoint */ - if (packet_size) { - outw ((1 << 15) | (ep_doublebuffer << 14) | - (ep_size << 12) | (ep_isoc << 11) | - (ep_ptr >> 3), - UDC_EP_TX (ep_addr & - USB_ENDPOINT_NUMBER_MASK)); - UDCDBGA ("IN ep %d buffer offset 0x%03x" - " packet size 0x%03x", - ep_addr & USB_ENDPOINT_NUMBER_MASK, - ep_ptr, packet_size); - } else { - outw (0, - UDC_EP_TX (ep_addr & - USB_ENDPOINT_NUMBER_MASK)); - } - } else { - /* OUT endpoint */ - if (packet_size) { - outw ((1 << 15) | (ep_doublebuffer << 14) | - (ep_size << 12) | (ep_isoc << 11) | - (ep_ptr >> 3), - UDC_EP_RX (ep_addr & - USB_ENDPOINT_NUMBER_MASK)); - UDCDBGA ("OUT ep %d buffer offset 0x%03x" - " packet size 0x%03x", - ep_addr & USB_ENDPOINT_NUMBER_MASK, - ep_ptr, packet_size); - } else { - outw (0, - UDC_EP_RX (ep_addr & - USB_ENDPOINT_NUMBER_MASK)); - } - } - ep_ptr += buffer_size; - } -} - -/* omap1510_deconfigure_device - * - * This function balances omap1510_configure_device. - */ -static void omap1510_deconfigure_device (void) -{ - int epnum; - - UDCDBG ("clear Cfg_Lock"); - outw (inw (UDC_SYSCON1) & ~UDC_Cfg_Lock, UDC_SYSCON1); - UDCREG (UDC_SYSCON1); - - /* deconfigure all endpoints */ - for (epnum = 1; epnum <= 15; epnum++) { - outw (0, UDC_EP_RX (epnum)); - outw (0, UDC_EP_TX (epnum)); - } -} - -/* omap1510_configure_device - * - * This function implements TRM Figure 14-9. - */ -static void omap1510_configure_device (struct usb_device_instance *device) -{ - omap1510_configure_endpoints (device); - - - /* Figure 14-9 indicates we should enable interrupts here, but we have - * other routines (udc_all_interrupts, udc_suspended_interrupts) to - * do that. - */ - - UDCDBG ("set Cfg_Lock"); - outw (inw (UDC_SYSCON1) | UDC_Cfg_Lock, UDC_SYSCON1); - UDCREG (UDC_SYSCON1); -} - -/* omap1510_write_noniso_tx_fifo - * - * This function implements TRM Figure 14-30. - * - * If the endpoint has an active tx_urb, then the next packet of data from the - * URB is written to the tx FIFO. The total amount of data in the urb is given - * by urb->actual_length. The maximum amount of data that can be sent in any - * one packet is given by endpoint->tx_packetSize. The number of data bytes - * from this URB that have already been transmitted is given by endpoint->sent. - * endpoint->last is updated by this routine with the number of data bytes - * transmitted in this packet. - * - * In accordance with Figure 14-30, the EP_NUM register must already have been - * written with the value to select the appropriate tx FIFO before this routine - * is called. - */ -static void omap1510_write_noniso_tx_fifo (struct usb_endpoint_instance - *endpoint) -{ - struct urb *urb = endpoint->tx_urb; - - if (urb) { - unsigned int last, i; - - UDCDBGA ("urb->buffer %p, buffer_length %d, actual_length %d", - urb->buffer, urb->buffer_length, urb->actual_length); - if ((last = - MIN (urb->actual_length - endpoint->sent, - endpoint->tx_packetSize))) { - u8 *cp = urb->buffer + endpoint->sent; - - UDCDBGA ("endpoint->sent %d, tx_packetSize %d, last %d", endpoint->sent, endpoint->tx_packetSize, last); - - if (((u32) cp & 1) == 0) { /* word aligned? */ - outsw (UDC_DATA, cp, last >> 1); - } else { /* byte aligned. */ - for (i = 0; i < (last >> 1); i++) { - u16 w = ((u16) cp[2 * i + 1] << 8) | - (u16) cp[2 * i]; - outw (w, UDC_DATA); - } - } - if (last & 1) { - outb (*(cp + last - 1), UDC_DATA); - } - } - endpoint->last = last; - } -} - -/* omap1510_read_noniso_rx_fifo - * - * This function implements TRM Figure 14-28. - * - * If the endpoint has an active rcv_urb, then the next packet of data is read - * from the rcv FIFO and written to rcv_urb->buffer at offset - * rcv_urb->actual_length to append the packet data to the data from any - * previous packets for this transfer. We assume that there is sufficient room - * left in the buffer to hold an entire packet of data. - * - * The return value is the number of bytes read from the FIFO for this packet. - * - * In accordance with Figure 14-28, the EP_NUM register must already have been - * written with the value to select the appropriate rcv FIFO before this routine - * is called. - */ -static int omap1510_read_noniso_rx_fifo (struct usb_endpoint_instance - *endpoint) -{ - struct urb *urb = endpoint->rcv_urb; - int len = 0; - - if (urb) { - len = inw (UDC_RXFSTAT); - - if (len) { - unsigned char *cp = urb->buffer + urb->actual_length; - - insw (UDC_DATA, cp, len >> 1); - if (len & 1) - *(cp + len - 1) = inb (UDC_DATA); - } - } - return len; -} - -/* omap1510_prepare_for_control_write_status - * - * This function implements TRM Figure 14-17. - * - * We have to deal here with non-autodecoded control writes that haven't already - * been dealt with by ep0_recv_setup. The non-autodecoded standard control - * write requests are: set/clear endpoint feature, set configuration, set - * interface, and set descriptor. ep0_recv_setup handles set/clear requests for - * ENDPOINT_HALT by halting the endpoint for a set request and resetting the - * endpoint for a clear request. ep0_recv_setup returns an error for - * SET_DESCRIPTOR requests which causes them to be terminated with a stall by - * the setup handler. A SET_INTERFACE request is handled by ep0_recv_setup by - * generating a DEVICE_SET_INTERFACE event. This leaves only the - * SET_CONFIGURATION event for us to deal with here. - * - */ -static void omap1510_prepare_for_control_write_status (struct urb *urb) -{ - struct usb_device_request *request = &urb->device_request;; - - /* check for a SET_CONFIGURATION request */ - if (request->bRequest == USB_REQ_SET_CONFIGURATION) { - int configuration = le16_to_cpu (request->wValue) & 0xff; - unsigned short devstat = inw (UDC_DEVSTAT); - - if ((devstat & (UDC_ADD | UDC_CFG)) == UDC_ADD) { - /* device is currently in ADDRESSED state */ - if (configuration) { - /* Assume the specified non-zero configuration - * value is valid and switch to the CONFIGURED - * state. - */ - outw (UDC_Dev_Cfg, UDC_SYSCON2); - } - } else if ((devstat & UDC_CFG) == UDC_CFG) { - /* device is currently in CONFIGURED state */ - if (!configuration) { - /* Switch to ADDRESSED state. */ - outw (UDC_Clr_Cfg, UDC_SYSCON2); - } - } - } - - /* select EP0 tx FIFO */ - outw (UDC_EP_Dir | UDC_EP_Sel, UDC_EP_NUM); - /* clear endpoint (no data bytes in status stage) */ - outw (UDC_Clr_EP, UDC_CTRL); - /* enable the EP0 tx FIFO */ - outw (UDC_Set_FIFO_En, UDC_CTRL); - /* deselect the endpoint */ - outw (UDC_EP_Dir, UDC_EP_NUM); -} - -/* udc_state_transition_up - * udc_state_transition_down - * - * Helper functions to implement device state changes. The device states and - * the events that transition between them are: - * - * STATE_ATTACHED - * || /\ - * \/ || - * DEVICE_HUB_CONFIGURED DEVICE_HUB_RESET - * || /\ - * \/ || - * STATE_POWERED - * || /\ - * \/ || - * DEVICE_RESET DEVICE_POWER_INTERRUPTION - * || /\ - * \/ || - * STATE_DEFAULT - * || /\ - * \/ || - * DEVICE_ADDRESS_ASSIGNED DEVICE_RESET - * || /\ - * \/ || - * STATE_ADDRESSED - * || /\ - * \/ || - * DEVICE_CONFIGURED DEVICE_DE_CONFIGURED - * || /\ - * \/ || - * STATE_CONFIGURED - * - * udc_state_transition_up transitions up (in the direction from STATE_ATTACHED - * to STATE_CONFIGURED) from the specified initial state to the specified final - * state, passing through each intermediate state on the way. If the initial - * state is at or above (i.e. nearer to STATE_CONFIGURED) the final state, then - * no state transitions will take place. - * - * udc_state_transition_down transitions down (in the direction from - * STATE_CONFIGURED to STATE_ATTACHED) from the specified initial state to the - * specified final state, passing through each intermediate state on the way. - * If the initial state is at or below (i.e. nearer to STATE_ATTACHED) the final - * state, then no state transitions will take place. - * - * These functions must only be called with interrupts disabled. - */ -static void udc_state_transition_up (usb_device_state_t initial, - usb_device_state_t final) -{ - if (initial < final) { - switch (initial) { - case STATE_ATTACHED: - usbd_device_event_irq (udc_device, - DEVICE_HUB_CONFIGURED, 0); - if (final == STATE_POWERED) - break; - case STATE_POWERED: - usbd_device_event_irq (udc_device, DEVICE_RESET, 0); - if (final == STATE_DEFAULT) - break; - case STATE_DEFAULT: - usbd_device_event_irq (udc_device, - DEVICE_ADDRESS_ASSIGNED, 0); - if (final == STATE_ADDRESSED) - break; - case STATE_ADDRESSED: - usbd_device_event_irq (udc_device, DEVICE_CONFIGURED, - 0); - case STATE_CONFIGURED: - break; - default: - break; - } - } -} - -static void udc_state_transition_down (usb_device_state_t initial, - usb_device_state_t final) -{ - if (initial > final) { - switch (initial) { - case STATE_CONFIGURED: - usbd_device_event_irq (udc_device, DEVICE_DE_CONFIGURED, 0); - if (final == STATE_ADDRESSED) - break; - case STATE_ADDRESSED: - usbd_device_event_irq (udc_device, DEVICE_RESET, 0); - if (final == STATE_DEFAULT) - break; - case STATE_DEFAULT: - usbd_device_event_irq (udc_device, DEVICE_POWER_INTERRUPTION, 0); - if (final == STATE_POWERED) - break; - case STATE_POWERED: - usbd_device_event_irq (udc_device, DEVICE_HUB_RESET, 0); - case STATE_ATTACHED: - break; - default: - break; - } - } -} - -/* Handle all device state changes. - * This function implements TRM Figure 14-21. - */ -static void omap1510_udc_state_changed (void) -{ - u16 bits; - u16 devstat = inw (UDC_DEVSTAT); - - UDCDBGA ("state changed, devstat %x, old %x", devstat, udc_devstat); - - bits = devstat ^ udc_devstat; - if (bits) { - if (bits & UDC_ATT) { - if (devstat & UDC_ATT) { - UDCDBG ("device attached and powered"); - udc_state_transition_up (udc_device->device_state, STATE_POWERED); - } else { - UDCDBG ("device detached or unpowered"); - udc_state_transition_down (udc_device->device_state, STATE_ATTACHED); - } - } - if (bits & UDC_USB_Reset) { - if (devstat & UDC_USB_Reset) { - UDCDBG ("device reset in progess"); - udc_state_transition_down (udc_device->device_state, STATE_POWERED); - } else { - UDCDBG ("device reset completed"); - } - } - if (bits & UDC_DEF) { - if (devstat & UDC_DEF) { - UDCDBG ("device entering default state"); - udc_state_transition_up (udc_device->device_state, STATE_DEFAULT); - } else { - UDCDBG ("device leaving default state"); - udc_state_transition_down (udc_device->device_state, STATE_POWERED); - } - } - if (bits & UDC_SUS) { - if (devstat & UDC_SUS) { - UDCDBG ("entering suspended state"); - usbd_device_event_irq (udc_device, DEVICE_BUS_INACTIVE, 0); - } else { - UDCDBG ("leaving suspended state"); - usbd_device_event_irq (udc_device, DEVICE_BUS_ACTIVITY, 0); - } - } - if (bits & UDC_R_WK_OK) { - UDCDBGA ("remote wakeup %s", (devstat & UDC_R_WK_OK) - ? "enabled" : "disabled"); - } - if (bits & UDC_ADD) { - if (devstat & UDC_ADD) { - UDCDBG ("default -> addressed"); - udc_state_transition_up (udc_device->device_state, STATE_ADDRESSED); - } else { - UDCDBG ("addressed -> default"); - udc_state_transition_down (udc_device->device_state, STATE_DEFAULT); - } - } - if (bits & UDC_CFG) { - if (devstat & UDC_CFG) { - UDCDBG ("device configured"); - /* The ep0_recv_setup function generates the - * DEVICE_CONFIGURED event when a - * USB_REQ_SET_CONFIGURATION setup packet is - * received, so we should already be in the - * state STATE_CONFIGURED. - */ - udc_state_transition_up (udc_device->device_state, STATE_CONFIGURED); - } else { - UDCDBG ("device deconfigured"); - udc_state_transition_down (udc_device->device_state, STATE_ADDRESSED); - } - } - } - - /* Clear interrupt source */ - outw (UDC_DS_Chg, UDC_IRQ_SRC); - - /* Save current DEVSTAT */ - udc_devstat = devstat; -} - -/* Handle SETUP USB interrupt. - * This function implements TRM Figure 14-14. - */ -static void omap1510_udc_setup (struct usb_endpoint_instance *endpoint) -{ - UDCDBG ("-> Entering device setup"); - - do { - const int setup_pktsize = 8; - unsigned char *datap = - (unsigned char *) &ep0_urb->device_request; - - /* Gain access to EP 0 setup FIFO */ - outw (UDC_Setup_Sel, UDC_EP_NUM); - - /* Read control request data */ - insb (UDC_DATA, datap, setup_pktsize); - - UDCDBGA ("EP0 setup read [%x %x %x %x %x %x %x %x]", - *(datap + 0), *(datap + 1), *(datap + 2), - *(datap + 3), *(datap + 4), *(datap + 5), - *(datap + 6), *(datap + 7)); - - /* Reset EP0 setup FIFO */ - outw (0, UDC_EP_NUM); - } while (inw (UDC_IRQ_SRC) & UDC_Setup); - - /* Try to process setup packet */ - if (ep0_recv_setup (ep0_urb)) { - /* Not a setup packet, stall next EP0 transaction */ - udc_stall_ep (0); - UDCDBG ("can't parse setup packet, still waiting for setup"); - return; - } - - /* Check direction */ - if ((ep0_urb->device_request.bmRequestType & USB_REQ_DIRECTION_MASK) - == USB_REQ_HOST2DEVICE) { - UDCDBG ("control write on EP0"); - if (le16_to_cpu (ep0_urb->device_request.wLength)) { - /* We don't support control write data stages. - * The only standard control write request with a data - * stage is SET_DESCRIPTOR, and ep0_recv_setup doesn't - * support that so we just stall those requests. A - * function driver might support a non-standard - * write request with a data stage, but it isn't - * obvious what we would do with the data if we read it - * so we'll just stall it. It seems like the API isn't - * quite right here. - */ -#if 0 - /* Here is what we would do if we did support control - * write data stages. - */ - ep0_urb->actual_length = 0; - outw (0, UDC_EP_NUM); - /* enable the EP0 rx FIFO */ - outw (UDC_Set_FIFO_En, UDC_CTRL); -#else - /* Stall this request */ - UDCDBG ("Stalling unsupported EP0 control write data " - "stage."); - udc_stall_ep (0); -#endif - } else { - omap1510_prepare_for_control_write_status (ep0_urb); - } - } else { - UDCDBG ("control read on EP0"); - /* The ep0_recv_setup function has already placed our response - * packet data in ep0_urb->buffer and the packet length in - * ep0_urb->actual_length. - */ - endpoint->tx_urb = ep0_urb; - endpoint->sent = 0; - /* select the EP0 tx FIFO */ - outw (UDC_EP_Dir | UDC_EP_Sel, UDC_EP_NUM); - /* Write packet data to the FIFO. omap1510_write_noniso_tx_fifo - * will update endpoint->last with the number of bytes written - * to the FIFO. - */ - omap1510_write_noniso_tx_fifo (endpoint); - /* enable the FIFO to start the packet transmission */ - outw (UDC_Set_FIFO_En, UDC_CTRL); - /* deselect the EP0 tx FIFO */ - outw (UDC_EP_Dir, UDC_EP_NUM); - } - - UDCDBG ("<- Leaving device setup"); -} - -/* Handle endpoint 0 RX interrupt - * This routine implements TRM Figure 14-16. - */ -static void omap1510_udc_ep0_rx (struct usb_endpoint_instance *endpoint) -{ - unsigned short status; - - UDCDBG ("RX on EP0"); - /* select EP0 rx FIFO */ - outw (UDC_EP_Sel, UDC_EP_NUM); - - status = inw (UDC_STAT_FLG); - - if (status & UDC_ACK) { - /* Check direction */ - if ((ep0_urb->device_request.bmRequestType - & USB_REQ_DIRECTION_MASK) == USB_REQ_HOST2DEVICE) { - /* This rx interrupt must be for a control write data - * stage packet. - * - * We don't support control write data stages. - * We should never end up here. - */ - - /* clear the EP0 rx FIFO */ - outw (UDC_Clr_EP, UDC_CTRL); - - /* deselect the EP0 rx FIFO */ - outw (0, UDC_EP_NUM); - - UDCDBG ("Stalling unexpected EP0 control write " - "data stage packet"); - udc_stall_ep (0); - } else { - /* This rx interrupt must be for a control read status - * stage packet. - */ - UDCDBG ("ACK on EP0 control read status stage packet"); - /* deselect EP0 rx FIFO */ - outw (0, UDC_EP_NUM); - } - } else if (status & UDC_STALL) { - UDCDBG ("EP0 stall during RX"); - /* deselect EP0 rx FIFO */ - outw (0, UDC_EP_NUM); - } else { - /* deselect EP0 rx FIFO */ - outw (0, UDC_EP_NUM); - } -} - -/* Handle endpoint 0 TX interrupt - * This routine implements TRM Figure 14-18. - */ -static void omap1510_udc_ep0_tx (struct usb_endpoint_instance *endpoint) -{ - unsigned short status; - struct usb_device_request *request = &ep0_urb->device_request; - - UDCDBG ("TX on EP0"); - /* select EP0 TX FIFO */ - outw (UDC_EP_Dir | UDC_EP_Sel, UDC_EP_NUM); - - status = inw (UDC_STAT_FLG); - if (status & UDC_ACK) { - /* Check direction */ - if ((request->bmRequestType & USB_REQ_DIRECTION_MASK) == - USB_REQ_HOST2DEVICE) { - /* This tx interrupt must be for a control write status - * stage packet. - */ - UDCDBG ("ACK on EP0 control write status stage packet"); - /* deselect EP0 TX FIFO */ - outw (UDC_EP_Dir, UDC_EP_NUM); - } else { - /* This tx interrupt must be for a control read data - * stage packet. - */ - int wLength = le16_to_cpu (request->wLength); - - /* Update our count of bytes sent so far in this - * transfer. - */ - endpoint->sent += endpoint->last; - - /* We are finished with this transfer if we have sent - * all of the bytes in our tx urb (urb->actual_length) - * unless we need a zero-length terminating packet. We - * need a zero-length terminating packet if we returned - * fewer bytes than were requested (wLength) by the host, - * and the number of bytes we returned is an exact - * multiple of the packet size endpoint->tx_packetSize. - */ - if ((endpoint->sent == ep0_urb->actual_length) - && ((ep0_urb->actual_length == wLength) - || (endpoint->last != - endpoint->tx_packetSize))) { - /* Done with control read data stage. */ - UDCDBG ("control read data stage complete"); - /* deselect EP0 TX FIFO */ - outw (UDC_EP_Dir, UDC_EP_NUM); - /* select EP0 RX FIFO to prepare for control - * read status stage. - */ - outw (UDC_EP_Sel, UDC_EP_NUM); - /* clear the EP0 RX FIFO */ - outw (UDC_Clr_EP, UDC_CTRL); - /* enable the EP0 RX FIFO */ - outw (UDC_Set_FIFO_En, UDC_CTRL); - /* deselect the EP0 RX FIFO */ - outw (0, UDC_EP_NUM); - } else { - /* We still have another packet of data to send - * in this control read data stage or else we - * need a zero-length terminating packet. - */ - UDCDBG ("ACK control read data stage packet"); - omap1510_write_noniso_tx_fifo (endpoint); - /* enable the EP0 tx FIFO to start transmission */ - outw (UDC_Set_FIFO_En, UDC_CTRL); - /* deselect EP0 TX FIFO */ - outw (UDC_EP_Dir, UDC_EP_NUM); - } - } - } else if (status & UDC_STALL) { - UDCDBG ("EP0 stall during TX"); - /* deselect EP0 TX FIFO */ - outw (UDC_EP_Dir, UDC_EP_NUM); - } else { - /* deselect EP0 TX FIFO */ - outw (UDC_EP_Dir, UDC_EP_NUM); - } -} - -/* Handle RX transaction on non-ISO endpoint. - * This function implements TRM Figure 14-27. - * The ep argument is a physical endpoint number for a non-ISO OUT endpoint - * in the range 1 to 15. - */ -static void omap1510_udc_epn_rx (int ep) -{ - unsigned short status; - - /* Check endpoint status */ - status = inw (UDC_STAT_FLG); - - if (status & UDC_ACK) { - int nbytes; - struct usb_endpoint_instance *endpoint = - omap1510_find_ep (ep); - - nbytes = omap1510_read_noniso_rx_fifo (endpoint); - usbd_rcv_complete (endpoint, nbytes, 0); - - /* enable rx FIFO to prepare for next packet */ - outw (UDC_Set_FIFO_En, UDC_CTRL); - } else if (status & UDC_STALL) { - UDCDBGA ("STALL on RX endpoint %d", ep); - } else if (status & UDC_NAK) { - UDCDBGA ("NAK on RX ep %d", ep); - } else { - serial_printf ("omap-bi: RX on ep %d with status %x", ep, - status); - } -} - -/* Handle TX transaction on non-ISO endpoint. - * This function implements TRM Figure 14-29. - * The ep argument is a physical endpoint number for a non-ISO IN endpoint - * in the range 16 to 30. - */ -static void omap1510_udc_epn_tx (int ep) -{ - unsigned short status; - - /*serial_printf("omap1510_udc_epn_tx( %x )\n",ep); */ - - /* Check endpoint status */ - status = inw (UDC_STAT_FLG); - - if (status & UDC_ACK) { - struct usb_endpoint_instance *endpoint = - omap1510_find_ep (ep); - - /* We need to transmit a terminating zero-length packet now if - * we have sent all of the data in this URB and the transfer - * size was an exact multiple of the packet size. - */ - if (endpoint->tx_urb - && (endpoint->last == endpoint->tx_packetSize) - && (endpoint->tx_urb->actual_length - endpoint->sent - - endpoint->last == 0)) { - /* Prepare to transmit a zero-length packet. */ - endpoint->sent += endpoint->last; - /* write 0 bytes of data to FIFO */ - omap1510_write_noniso_tx_fifo (endpoint); - /* enable tx FIFO to start transmission */ - outw (UDC_Set_FIFO_En, UDC_CTRL); - } else if (endpoint->tx_urb - && endpoint->tx_urb->actual_length) { - /* retire the data that was just sent */ - usbd_tx_complete (endpoint); - /* Check to see if we have more data ready to transmit - * now. - */ - if (endpoint->tx_urb - && endpoint->tx_urb->actual_length) { - /* write data to FIFO */ - omap1510_write_noniso_tx_fifo (endpoint); - /* enable tx FIFO to start transmission */ - outw (UDC_Set_FIFO_En, UDC_CTRL); - } - } - } else if (status & UDC_STALL) { - UDCDBGA ("STALL on TX endpoint %d", ep); - } else if (status & UDC_NAK) { - UDCDBGA ("NAK on TX endpoint %d", ep); - } else { - /*serial_printf("omap-bi: TX on ep %d with status %x\n", ep, status); */ - } -} - - -/* -------------------------------------------------------------------------------- -*/ - -/* Handle general USB interrupts and dispatch according to type. - * This function implements TRM Figure 14-13. - */ -void omap1510_udc_irq (void) -{ - u16 irq_src = inw (UDC_IRQ_SRC); - int valid_irq = 0; - - if (!(irq_src & ~UDC_SOF_Flg)) /* ignore SOF interrupts ) */ - return; - - UDCDBGA ("< IRQ #%d start >- %x", udc_interrupts, irq_src); - /*serial_printf("< IRQ #%d start >- %x\n", udc_interrupts, irq_src); */ - - if (irq_src & UDC_DS_Chg) { - /* Device status changed */ - omap1510_udc_state_changed (); - valid_irq++; - } - if (irq_src & UDC_EP0_RX) { - /* Endpoint 0 receive */ - outw (UDC_EP0_RX, UDC_IRQ_SRC); /* ack interrupt */ - omap1510_udc_ep0_rx (udc_device->bus->endpoint_array + 0); - valid_irq++; - } - if (irq_src & UDC_EP0_TX) { - /* Endpoint 0 transmit */ - outw (UDC_EP0_TX, UDC_IRQ_SRC); /* ack interrupt */ - omap1510_udc_ep0_tx (udc_device->bus->endpoint_array + 0); - valid_irq++; - } - if (irq_src & UDC_Setup) { - /* Device setup */ - omap1510_udc_setup (udc_device->bus->endpoint_array + 0); - valid_irq++; - } - /*if (!valid_irq) */ - /* serial_printf("unknown interrupt, IRQ_SRC %.4x\n", irq_src); */ - UDCDBGA ("< IRQ #%d end >", udc_interrupts); - udc_interrupts++; -} - -/* This function implements TRM Figure 14-26. */ -void omap1510_udc_noniso_irq (void) -{ - unsigned short epnum; - unsigned short irq_src = inw (UDC_IRQ_SRC); - int valid_irq = 0; - - if (!(irq_src & (UDC_EPn_RX | UDC_EPn_TX))) - return; - - UDCDBGA ("non-ISO IRQ, IRQ_SRC %x", inw (UDC_IRQ_SRC)); - - if (irq_src & UDC_EPn_RX) { /* Endpoint N OUT transaction */ - /* Determine the endpoint number for this interrupt */ - epnum = (inw (UDC_EPN_STAT) & 0x0f00) >> 8; - UDCDBGA ("RX on ep %x", epnum); - - /* acknowledge interrupt */ - outw (UDC_EPn_RX, UDC_IRQ_SRC); - - if (epnum) { - /* select the endpoint FIFO */ - outw (UDC_EP_Sel | epnum, UDC_EP_NUM); - - omap1510_udc_epn_rx (epnum); - - /* deselect the endpoint FIFO */ - outw (epnum, UDC_EP_NUM); - } - valid_irq++; - } - if (irq_src & UDC_EPn_TX) { /* Endpoint N IN transaction */ - /* Determine the endpoint number for this interrupt */ - epnum = (inw (UDC_EPN_STAT) & 0x000f) | USB_DIR_IN; - UDCDBGA ("TX on ep %x", epnum); - - /* acknowledge interrupt */ - outw (UDC_EPn_TX, UDC_IRQ_SRC); - - if (epnum) { - /* select the endpoint FIFO */ - outw (UDC_EP_Sel | UDC_EP_Dir | epnum, UDC_EP_NUM); - - omap1510_udc_epn_tx (epnum); - - /* deselect the endpoint FIFO */ - outw (UDC_EP_Dir | epnum, UDC_EP_NUM); - } - valid_irq++; - } - if (!valid_irq) - serial_printf (": unknown non-ISO interrupt, IRQ_SRC %.4x\n", - irq_src); -} - -/* -------------------------------------------------------------------------------- -*/ - - -/* - * Start of public functions. - */ - -/* Called to start packet transmission. */ -int udc_endpoint_write (struct usb_endpoint_instance *endpoint) -{ - unsigned short epnum = - endpoint->endpoint_address & USB_ENDPOINT_NUMBER_MASK; - - UDCDBGA ("Starting transmit on ep %x", epnum); - - if (endpoint->tx_urb) { - /* select the endpoint FIFO */ - outw (UDC_EP_Sel | UDC_EP_Dir | epnum, UDC_EP_NUM); - /* write data to FIFO */ - omap1510_write_noniso_tx_fifo (endpoint); - /* enable tx FIFO to start transmission */ - outw (UDC_Set_FIFO_En, UDC_CTRL); - /* deselect the endpoint FIFO */ - outw (UDC_EP_Dir | epnum, UDC_EP_NUM); - } - - return 0; -} - -/* Start to initialize h/w stuff */ -int udc_init (void) -{ - u16 udc_rev; - uchar value; - ulong gpio; - int i; - - /* Let the device settle down before we start */ - for (i = 0; i < UDC_INIT_MDELAY; i++) udelay(1000); - - udc_device = NULL; - - UDCDBG ("starting"); - - /* Check peripheral reset. Must be 1 to make sure - MPU TIPB peripheral reset is inactive */ - UDCREG (ARM_RSTCT2); - - /* Set and check clock control. - * We might ought to be using the clock control API to do - * this instead of fiddling with the clock registers directly - * here. - */ - outw ((1 << 4) | (1 << 5), CLOCK_CTRL); - UDCREG (CLOCK_CTRL); - - /* Set and check SOFT - * The below line of code has been changed to perform a - * read-modify-write instead of a simple write for - * configuring the SOFT_REQ register. This allows the code - * to be compatible with OMAP5912 and OMAP16xx devices - */ - outw ((1 << 4) | (1 << 3) | 1 | (inw(SOFT_REQ)), SOFT_REQ); - - /* Short delay to wait for DPLL */ - udelay (1000); - - /* Print banner with device revision */ - udc_rev = inw (UDC_REV) & 0xff; - -#ifdef CONFIG_OMAP1610 - printf ("USB: TI OMAP5912 USB function module rev %d.%d\n", - udc_rev >> 4, udc_rev & 0xf); -#endif - - /* The VBUS_MODE bit selects whether VBUS detection is done via - * software (1) or hardware (0). When software detection is - * selected, VBUS_CTRL selects whether USB is not connected (0) - * or connected (1). - */ - outl (inl (FUNC_MUX_CTRL_0) | UDC_VBUS_MODE, FUNC_MUX_CTRL_0); - outl (inl (FUNC_MUX_CTRL_0) & ~UDC_VBUS_CTRL, FUNC_MUX_CTRL_0); - UDCREGL (FUNC_MUX_CTRL_0); - - /* - * At this point, device is ready for configuration... - */ - - UDCDBG ("disable USB interrupts"); - outw (0, UDC_IRQ_EN); - UDCREG (UDC_IRQ_EN); - - UDCDBG ("disable USB DMA"); - outw (0, UDC_DMA_IRQ_EN); - UDCREG (UDC_DMA_IRQ_EN); - - UDCDBG ("initialize SYSCON1"); - outw (UDC_Self_Pwr | UDC_Pullup_En, UDC_SYSCON1); - UDCREG (UDC_SYSCON1); - - return 0; -} - -/* Stall endpoint */ -static void udc_stall_ep (unsigned int ep_addr) -{ - /*int ep_addr = PHYS_EP_TO_EP_ADDR(ep); */ - int ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK; - - UDCDBGA ("stall ep_addr %d", ep_addr); - - /* REVISIT? - * The OMAP TRM section 14.2.4.2 says we must check that the FIFO - * is empty before halting the endpoint. The current implementation - * doesn't check that the FIFO is empty. - */ - - if (!ep_num) { - outw (UDC_Stall_Cmd, UDC_SYSCON2); - } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT) { - if (inw (UDC_EP_RX (ep_num)) & UDC_EPn_RX_Valid) { - /* we have a valid rx endpoint, so halt it */ - outw (UDC_EP_Sel | ep_num, UDC_EP_NUM); - outw (UDC_Set_Halt, UDC_CTRL); - outw (ep_num, UDC_EP_NUM); - } - } else { - if (inw (UDC_EP_TX (ep_num)) & UDC_EPn_TX_Valid) { - /* we have a valid tx endpoint, so halt it */ - outw (UDC_EP_Sel | UDC_EP_Dir | ep_num, UDC_EP_NUM); - outw (UDC_Set_Halt, UDC_CTRL); - outw (ep_num, UDC_EP_NUM); - } - } -} - -/* Reset endpoint */ -#if 0 -static void udc_reset_ep (unsigned int ep_addr) -{ - /*int ep_addr = PHYS_EP_TO_EP_ADDR(ep); */ - int ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK; - - UDCDBGA ("reset ep_addr %d", ep_addr); - - if (!ep_num) { - /* control endpoint 0 can't be reset */ - } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT) { - UDCDBGA ("UDC_EP_RX(%d) = 0x%04x", ep_num, - inw (UDC_EP_RX (ep_num))); - if (inw (UDC_EP_RX (ep_num)) & UDC_EPn_RX_Valid) { - /* we have a valid rx endpoint, so reset it */ - outw (ep_num | UDC_EP_Sel, UDC_EP_NUM); - outw (UDC_Reset_EP, UDC_CTRL); - outw (ep_num, UDC_EP_NUM); - UDCDBGA ("OUT endpoint %d reset", ep_num); - } - } else { - UDCDBGA ("UDC_EP_TX(%d) = 0x%04x", ep_num, - inw (UDC_EP_TX (ep_num))); - /* Resetting of tx endpoints seems to be causing the USB function - * module to fail, which causes problems when the driver is - * uninstalled. We'll skip resetting tx endpoints for now until - * we figure out what the problem is. - */ -#if 0 - if (inw (UDC_EP_TX (ep_num)) & UDC_EPn_TX_Valid) { - /* we have a valid tx endpoint, so reset it */ - outw (ep_num | UDC_EP_Dir | UDC_EP_Sel, UDC_EP_NUM); - outw (UDC_Reset_EP, UDC_CTRL); - outw (ep_num | UDC_EP_Dir, UDC_EP_NUM); - UDCDBGA ("IN endpoint %d reset", ep_num); - } -#endif - } -} -#endif - -/* ************************************************************************** */ - -/** - * udc_check_ep - check logical endpoint - * - * Return physical endpoint number to use for this logical endpoint or zero if not valid. - */ -#if 0 -int udc_check_ep (int logical_endpoint, int packetsize) -{ - if ((logical_endpoint == 0x80) || - ((logical_endpoint & 0x8f) != logical_endpoint)) { - return 0; - } - - switch (packetsize) { - case 8: - case 16: - case 32: - case 64: - case 128: - case 256: - case 512: - break; - default: - return 0; - } - - return EP_ADDR_TO_PHYS_EP (logical_endpoint); -} -#endif - -/* - * udc_setup_ep - setup endpoint - * - * Associate a physical endpoint with endpoint_instance - */ -void udc_setup_ep (struct usb_device_instance *device, - unsigned int ep, struct usb_endpoint_instance *endpoint) -{ - UDCDBGA ("setting up endpoint addr %x", endpoint->endpoint_address); - - /* This routine gets called by bi_modinit for endpoint 0 and from - * bi_config for all of the other endpoints. bi_config gets called - * during the DEVICE_CREATE, DEVICE_CONFIGURED, and - * DEVICE_SET_INTERFACE events. We need to reconfigure the OMAP packet - * RAM after bi_config scans the selected device configuration and - * initializes the endpoint structures, but before this routine enables - * the OUT endpoint FIFOs. Since bi_config calls this routine in a - * loop for endpoints 1 through UDC_MAX_ENDPOINTS, we reconfigure our - * packet RAM here when ep==1. - * I really hate to do this here, but it seems like the API exported - * by the USB bus interface controller driver to the usbd-bi module - * isn't quite right so there is no good place to do this. - */ - if (ep == 1) { - omap1510_deconfigure_device (); - omap1510_configure_device (device); - } - - if (endpoint && (ep < UDC_MAX_ENDPOINTS)) { - int ep_addr = endpoint->endpoint_address; - - if (!ep_addr) { - /* nothing to do for endpoint 0 */ - } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { - /* nothing to do for IN (tx) endpoints */ - } else { /* OUT (rx) endpoint */ - if (endpoint->rcv_packetSize) { - /*struct urb* urb = &(urb_out_array[ep&0xFF]); */ - /*urb->endpoint = endpoint; */ - /*urb->device = device; */ - /*urb->buffer_length = sizeof(urb->buffer); */ - - /*endpoint->rcv_urb = urb; */ - omap1510_prepare_endpoint_for_rx (ep_addr); - } - } - } -} - -/** - * udc_disable_ep - disable endpoint - * @ep: - * - * Disable specified endpoint - */ -#if 0 -void udc_disable_ep (unsigned int ep_addr) -{ - /*int ep_addr = PHYS_EP_TO_EP_ADDR(ep); */ - int ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK; - struct usb_endpoint_instance *endpoint = omap1510_find_ep (ep_addr); /*udc_device->bus->endpoint_array + ep; */ - - UDCDBGA ("disable ep_addr %d", ep_addr); - - if (!ep_num) { - /* nothing to do for endpoint 0 */ ; - } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { - if (endpoint->tx_packetSize) { - /* we have a valid tx endpoint */ - /*usbd_flush_tx(endpoint); */ - endpoint->tx_urb = NULL; - } - } else { - if (endpoint->rcv_packetSize) { - /* we have a valid rx endpoint */ - /*usbd_flush_rcv(endpoint); */ - endpoint->rcv_urb = NULL; - } - } -} -#endif - -/* ************************************************************************** */ - -/** - * udc_connected - is the USB cable connected - * - * Return non-zero if cable is connected. - */ -#if 0 -int udc_connected (void) -{ - return ((inw (UDC_DEVSTAT) & UDC_ATT) == UDC_ATT); -} -#endif - -/* Turn on the USB connection by enabling the pullup resistor */ -void udc_connect (void) -{ - UDCDBG ("connect, enable Pullup"); - outl (0x00000018, FUNC_MUX_CTRL_D); -} - -/* Turn off the USB connection by disabling the pullup resistor */ -void udc_disconnect (void) -{ - UDCDBG ("disconnect, disable Pullup"); - outl (0x00000000, FUNC_MUX_CTRL_D); -} - -/* ************************************************************************** */ - - -/* - * udc_disable_interrupts - disable interrupts - * switch off interrupts - */ -#if 0 -void udc_disable_interrupts (struct usb_device_instance *device) -{ - UDCDBG ("disabling all interrupts"); - outw (0, UDC_IRQ_EN); -} -#endif - -/* ************************************************************************** */ - -/** - * udc_ep0_packetsize - return ep0 packetsize - */ -#if 0 -int udc_ep0_packetsize (void) -{ - return EP0_PACKETSIZE; -} -#endif - -/* Switch on the UDC */ -void udc_enable (struct usb_device_instance *device) -{ - UDCDBGA ("enable device %p, status %d", device, device->status); - - /* initialize driver state variables */ - udc_devstat = 0; - - /* Save the device structure pointer */ - udc_device = device; - - /* Setup ep0 urb */ - if (!ep0_urb) { - ep0_urb = - usbd_alloc_urb (udc_device, - udc_device->bus->endpoint_array); - } else { - serial_printf ("udc_enable: ep0_urb already allocated %p\n", - ep0_urb); - } - - UDCDBG ("Check clock status"); - UDCREG (STATUS_REQ); - - /* The VBUS_MODE bit selects whether VBUS detection is done via - * software (1) or hardware (0). When software detection is - * selected, VBUS_CTRL selects whether USB is not connected (0) - * or connected (1). - */ - outl (inl (FUNC_MUX_CTRL_0) | UDC_VBUS_CTRL | UDC_VBUS_MODE, - FUNC_MUX_CTRL_0); - UDCREGL (FUNC_MUX_CTRL_0); - - omap1510_configure_device (device); -} - -/* Switch off the UDC */ -void udc_disable (void) -{ - UDCDBG ("disable UDC"); - - omap1510_deconfigure_device (); - - /* The VBUS_MODE bit selects whether VBUS detection is done via - * software (1) or hardware (0). When software detection is - * selected, VBUS_CTRL selects whether USB is not connected (0) - * or connected (1). - */ - outl (inl (FUNC_MUX_CTRL_0) | UDC_VBUS_MODE, FUNC_MUX_CTRL_0); - outl (inl (FUNC_MUX_CTRL_0) & ~UDC_VBUS_CTRL, FUNC_MUX_CTRL_0); - UDCREGL (FUNC_MUX_CTRL_0); - - /* Free ep0 URB */ - if (ep0_urb) { - /*usbd_dealloc_urb(ep0_urb); */ - ep0_urb = NULL; - } - - /* Reset device pointer. - * We ought to do this here to balance the initialization of udc_device - * in udc_enable, but some of our other exported functions get called - * by the bus interface driver after udc_disable, so we have to hang on - * to the device pointer to avoid a null pointer dereference. */ - /* udc_device = NULL; */ -} - -/** - * udc_startup - allow udc code to do any additional startup - */ -void udc_startup_events (struct usb_device_instance *device) -{ - /* The DEVICE_INIT event puts the USB device in the state STATE_INIT. */ - usbd_device_event_irq (device, DEVICE_INIT, 0); - - /* The DEVICE_CREATE event puts the USB device in the state - * STATE_ATTACHED. - */ - usbd_device_event_irq (device, DEVICE_CREATE, 0); - - /* Some USB controller driver implementations signal - * DEVICE_HUB_CONFIGURED and DEVICE_RESET events here. - * DEVICE_HUB_CONFIGURED causes a transition to the state STATE_POWERED, - * and DEVICE_RESET causes a transition to the state STATE_DEFAULT. - * The OMAP USB client controller has the capability to detect when the - * USB cable is connected to a powered USB bus via the ATT bit in the - * DEVSTAT register, so we will defer the DEVICE_HUB_CONFIGURED and - * DEVICE_RESET events until later. - */ - - udc_enable (device); -} - -/** - * udc_irq - do pseudo interrupts - */ -void udc_irq(void) -{ - /* Loop while we have interrupts. - * If we don't do this, the input chain - * polling delay is likely to miss - * host requests. - */ - while (inw (UDC_IRQ_SRC) & ~UDC_SOF_Flg) { - /* Handle any new IRQs */ - omap1510_udc_irq (); - omap1510_udc_noniso_irq (); - } -} - -/* Flow control */ -void udc_set_nak(int epid) -{ - /* TODO: implement this functionality in omap1510 */ -} - -void udc_unset_nak (int epid) -{ - /* TODO: implement this functionality in omap1510 */ -} diff --git a/include/cli.h b/include/cli.h index 699426252c..6da7a4afdb 100644 --- a/include/cli.h +++ b/include/cli.h @@ -31,6 +31,14 @@ void cli_simple_loop(void); int cli_simple_run_command(const char *cmd, int flag); /** + * cli_simple_process_macros() - Expand $() and ${} format env. variables + * + * @param input Input string possible containing $() / ${} vars + * @param output Output string with $() / ${} vars expanded + */ +void cli_simple_process_macros(const char *input, char *output); + +/** * cli_simple_run_command_list() - Execute a list of command * * The commands should be separated by ; or \n and will be executed diff --git a/include/common.h b/include/common.h index 1d6cb48ff0..c7e51ca41c 100644 --- a/include/common.h +++ b/include/common.h @@ -32,10 +32,7 @@ typedef volatile unsigned char vu_char; defined(CONFIG_MPC866) || \ defined(CONFIG_MPC866P) # define CONFIG_MPC866_FAMILY 1 -#elif defined(CONFIG_MPC870) \ - || defined(CONFIG_MPC875) \ - || defined(CONFIG_MPC880) \ - || defined(CONFIG_MPC885) +#elif defined(CONFIG_MPC885) # define CONFIG_MPC885_FAMILY 1 #endif #if defined(CONFIG_MPC860) \ diff --git a/include/commproc.h b/include/commproc.h index 52ac4caf5a..82a1a985b2 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -456,27 +456,6 @@ typedef struct scc_enet { #define SICR_ENET_CLKRT ((uint)0x00002c00) #endif /* CONFIG_BSEIP */ -/*** BSEIP **********************************************************/ - -#ifdef CONFIG_FLAGADM -/* Enet configuration for the FLAGADM */ -/* Enet on SCC2 */ - -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) -#define PA_ENET_TXD ((ushort)0x0008) -#define PA_ENET_TCLK ((ushort)0x0100) -#define PA_ENET_RCLK ((ushort)0x0400) -#define PB_ENET_TENA ((uint)0x00002000) -#define PC_ENET_CLSN ((ushort)0x0040) -#define PC_ENET_RENA ((ushort)0x0080) - -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00003400) -#endif /* CONFIG_FLAGADM */ - /*** ELPT860 *********************************************************/ #ifdef CONFIG_ELPT860 @@ -556,27 +535,6 @@ typedef struct scc_enet { #define SICR_ENET_CLKRT ((uint)0x00002600) #endif /* CONFIG_FPS850L, CONFIG_FPS860L */ -/*** GEN860T **********************************************************/ -#if defined(CONFIG_GEN860T) -#undef SCC_ENET -#define FEC_ENET - -#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ -#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ -#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ -#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ -#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ -#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ -#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ -#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ -#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ -#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ -#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ -#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ -#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ -#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3-15 */ -#endif /* CONFIG_GEN860T */ - /*** HERMES-PRO ******************************************************/ /* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */ @@ -779,57 +737,6 @@ typedef struct scc_enet { /*** NETVIA *******************************************************/ -/* SinoVee Microsystems SC8xx series FEL8xx-AT,SC823,SC850,SC855T,SC860T */ -#if ( defined CONFIG_SVM_SC8xx ) -# ifndef CONFIG_FEC_ENET - -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 - - /* Bits in parallel I/O port registers that have to be set/cleared - * * * * to configure the pins for SCC2 use. - * * * */ -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0400) /* PA 5 */ -#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ - -#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ - -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to - * * * * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. - * * * */ -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00003700) - -# else /* Use FEC for Fast Ethernet */ - -#undef SCC_ENET -#define FEC_ENET - -#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ -#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ -#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ -#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ -#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ -#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ -#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ -#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ -#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ -#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ -#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ -#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ -#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ - -#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ - -# endif /* CONFIG_FEC_ENET */ -#endif /* CONFIG_SVM_SC8xx */ - - #if defined(CONFIG_NETVIA) /* Bits in parallel I/O port registers that have to be set/cleared * to configure the pins for SCC2 use. @@ -916,16 +823,6 @@ typedef struct scc_enet { #define SICR_ENET_CLKRT ((uint)0x00002E00) #endif /* CONFIG_SPD823TS */ -/*** SXNI855T ******************************************************/ - -#if defined(CONFIG_SXNI855T) - -#ifdef CONFIG_FEC_ENET -#define FEC_ENET /* use FEC for Ethernet */ -#endif /* CONFIG_FEC_ETHERNET */ - -#endif /* CONFIG_SXNI855T */ - /*** MVS1, TQM823L/M, TQM850L/M, TQM885D, R360MPI **********/ #if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \ diff --git a/include/configs/FLAGADM.h b/include/configs/FLAGADM.h deleted file mode 100644 index d93223fa40..0000000000 --- a/include/configs/FLAGADM.h +++ /dev/null @@ -1,296 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_FLAGADM 1 /* ...on a FLAGA DM */ -#define CONFIG_8xx_GCLK_FREQ 48000000 /*48MHz*/ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#undef CONFIG_8xx_CONS_SMC1 /* Console is on SMC1 */ -#define CONFIG_8xx_CONS_SMC2 1 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ - -#undef CONFIG_CLOCKS_IN_MHZ - -#if 0 -#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp" -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs root=/dev/ram ip=off panic=1;" \ - "bootm 40040000 400e0000" -#else -#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp panic=1" -#define CONFIG_BOOTCOMMAND "bootp 0x400000; bootm 0x400000" -#endif /* 0|1*/ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -/*#define CONFIG_WATCHDOG*/ /* watchdog enabled */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ - -#define CONFIG_CMD_BDI -#define CONFIG_CMD_IMI -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_NET - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "EEG> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x40040000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -/* This is a litlebit wasteful, but one sector is 128kb and we have to - * assigne a whole sector for the environment, so that we can safely - * erase and write it without disturbing the boot sector - */ -#define CONFIG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif -#define CONFIG_SYS_DELAYED_ICACHE 1 /* enable ICache not before - * running in RAM. - */ - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#ifdef CONFIG_WATCHDOG -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_PRE_SIUMCR (SIUMCR_DBGC11 | SIUMCR_MPRE | \ - SIUMCR_MLRC01 | SIUMCR_GB5E) -#define CONFIG_SYS_SIUMCR (CONFIG_SYS_PRE_SIUMCR | SIUMCR_DLK) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit miltiplier of 0x00b i.e. operation clock is - * 4MHz * (0x00b+1) = 4MHz * 12 = 48MHz - */ -#define CONFIG_SYS_PLPRCR (0x00b00000 | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR ( SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -#define CONFIG_SYS_DER 0 - -/* - * In the Flaga DM we have: - * Flash on BR0/OR0/CS0a at 0x40000000 - * Display on BR1/OR1/CS1 at 0x20000000 - * SDRAM on BR2/OR2/CS2 at 0x00000000 - * Free BR3/OR3/CS3 - * DSP1 on BR4/OR4/CS4 at 0x80000000 - * DSP2 on BR5/OR5/CS5 at 0xa0000000 - * - * For now we just configure the Flash and the SDRAM and leave the others - * untouched. -*/ - -#define CONFIG_SYS_FLASH_PROTECTION 0 - -#define FLASH_BASE0 0x40000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_OR_AM 0xff000000 /* OR addr mask */ -#define CONFIG_SYS_OR_ATM 0x00006000 - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | \ - OR_SCY_3_CLK | OR_TRLX | OR_EHTR ) - -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_OR_AM | CONFIG_SYS_OR_ATM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0 & BR_BA_MSK) | BR_PS_16 | BR_V ) - -/* - * BR2 and OR2 (SDRAM) - * - */ -#define SDRAM_BASE2 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM ( 0x00000800 ) - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2 & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#define CONFIG_SYS_BR2 CONFIG_SYS_BR2_PRELIM -#define CONFIG_SYS_OR2 CONFIG_SYS_OR2_PRELIM - -/* - * MAMR settings for SDRAM - */ -#define CONFIG_SYS_MAMR_48_SDR (CONFIG_SYS_MAMR_PTA | MAMR_WLFA_1X | MAMR_RLFA_1X \ - | MAMR_G0CLA_A11) - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 0x0F000000 - -/* - * BR4 and OR4 (DSP1) - * - * We do not wan't preliminary setup of the DSP, anyway we need the - * UPMB setup correctly before we can access the DSP. - * -*/ -#define DSP_BASE 0x80000000 - -#define CONFIG_SYS_OR4 ( OR_AM_MSK | OR_CSNT_SAM | OR_BI | OR_G5LS) -#define CONFIG_SYS_BR4 ( (DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_UPMB | BR_V ) - -#endif /* __CONFIG_H */ diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h deleted file mode 100644 index fd6c9763d8..0000000000 --- a/include/configs/GEN860T.h +++ /dev/null @@ -1,712 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Keith Outwater, keith_outwater@mvis.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config_GEN860T.h - board specific configuration options - */ - -#ifndef __CONFIG_GEN860T_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_MPC860 -#define CONFIG_GEN860T - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -/* - * Identify the board - */ -#if !defined(CONFIG_SC) -#define CONFIG_IDENT_STRING " B2" -#else -#define CONFIG_IDENT_STRING " SC" -#endif - -/* - * Don't depend on the RTC clock to determine clock frequency - - * the 860's internal rtc uses a 32.768 KHz clock which is - * generated by the DS1337 - and the DS1337 clock can be turned off. - */ -#if !defined(CONFIG_SC) -#define CONFIG_8xx_GCLK_FREQ 66600000 -#else -#define CONFIG_8xx_GCLK_FREQ 48000000 -#endif - -/* - * The RS-232 console port is on SMC1 - */ -#define CONFIG_8xx_CONS_SMC1 -#define CONFIG_BAUDRATE 38400 - -/* - * Print console information - */ -#undef CONFIG_SYS_CONSOLE_INFO_QUIET - -/* - * Set the autoboot delay in seconds. A delay of -1 disables autoboot - */ -#define CONFIG_BOOTDELAY 5 - -/* - * Pass the clock frequency to the Linux kernel in units of MHz - */ -#define CONFIG_CLOCKS_IN_MHZ - -#define CONFIG_PREBOOT \ - "echo;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -/* - * Turn off echo for serial download by default. Allow baud rate to be changed - * for downloads - */ -#undef CONFIG_LOADS_ECHO -#define CONFIG_SYS_LOADS_BAUD_CHANGE - -/* - * Turn off the watchdog timer - */ -#undef CONFIG_WATCHDOG - -/* - * Do not reboot if a panic occurs - */ -#define CONFIG_PANIC_HANG - -/* - * Enable the status LED - */ -#define CONFIG_STATUS_LED - -/* - * Reset address. We pick an address such that when an instruction - * is executed at that address, a machine check exception occurs - */ -#define CONFIG_SYS_RESET_ADDRESS ((ulong) -1) - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * The GEN860T network interface uses the on-chip 10/100 FEC with - * an Intel LXT971A PHY connected to the 860T's MII. The PHY's - * MII address is hardwired on the board to zero. - */ -#define CONFIG_FEC_ENET -#define CONFIG_SYS_DISCOVER_PHY -#define CONFIG_MII -#define CONFIG_MII_INIT 1 -#define CONFIG_PHY_ADDR 0 - -/* - * Set default IP stuff just to get bootstrap entries into the - * environment so that we can source the full default environment. - */ -#define CONFIG_ETHADDR 9a:52:63:15:85:25 -#define CONFIG_SERVERIP 10.0.4.201 -#define CONFIG_IPADDR 10.0.4.111 - -/* - * This board has a 32 kibibyte EEPROM (Atmel AT24C256) connected to - * the MPC860T I2C interface. - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10 mS w/ 20% margin */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* need 16 bit address */ -#define CONFIG_ENV_EEPROM_SIZE (32 * 1024) - -/* - * Enable I2C and select the hardware/software driver - */ -#define CONFIG_HARD_I2C 1 /* CPM based I2C */ -#undef CONFIG_SYS_I2C_SOFT /* Bit-banged I2C */ - -#ifdef CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 /* clock speed in Hz */ -#define CONFIG_SYS_I2C_SLAVE 0xFE /* I2C slave address */ -#endif - -#ifdef CONFIG_SYS_I2C_SOFT -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if (bit) \ - immr->im_cpm.cp_pbdat |= PB_SDA; \ - else \ - immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if (bit) \ - immr->im_cpm.cp_pbdat |= PB_SCL; \ - else \ - immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#endif - -/* - * Allow environment overwrites by anyone - */ -#define CONFIG_ENV_OVERWRITE - -#if !defined(CONFIG_SC) -/* - * The MPC860's internal RTC is horribly broken in rev D masks. Three - * internal MPC860T circuit nodes were inadvertently left floating; this - * causes KAPWR current in power down mode to be three orders of magnitude - * higher than specified in the datasheet (from 10 uA to 10 mA). No - * reasonable battery can keep that kind RTC running during powerdown for any - * length of time, so we use an external RTC on the I2C bus instead. - */ -#define CONFIG_RTC_DS1337 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -#else -/* - * No external RTC on SC variant, so we're stuck with the internal one. - */ -#define CONFIG_RTC_MPC8xx -#endif - -/* - * Power On Self Test support - */ -#define CONFIG_POST ( CONFIG_SYS_POST_CACHE | \ - CONFIG_SYS_POST_MEMORY | \ - CONFIG_SYS_POST_CPU | \ - CONFIG_SYS_POST_UART | \ - CONFIG_SYS_POST_SPR ) - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_DATE -#define CONFIG_CMD_FPGA -#define CONFIG_CMD_FPGA_LOADMK -#define CONFIG_CMD_MII -#define CONFIG_CMD_BEDBUG - -#ifdef CONFIG_POST -#define CONFIG_CMD_DIAG -#endif - -/* - * There is no IDE/PCMCIA hardware support on the board. - */ -#undef CONFIG_IDE_PCMCIA -#undef CONFIG_IDE_LED -#undef CONFIG_IDE_RESET - -/* - * Enable the call to misc_init_r() for miscellaneous platform - * dependent initialization. - */ -#define CONFIG_MISC_INIT_R - -/* - * Enable call to last_stage_init() so we can twiddle some LEDS :) - */ -#define CONFIG_LAST_STAGE_INIT - -/* - * Virtex2 FPGA configuration support - */ -#define CONFIG_FPGA_COUNT 1 -#define CONFIG_FPGA -#define CONFIG_FPGA_XILINX -#define CONFIG_FPGA_VIRTEX2 -#define CONFIG_SYS_FPGA_PROG_FEEDBACK - -/* - * Verbose help from command monitor. - */ -#define CONFIG_SYS_LONGHELP -#if !defined(CONFIG_SC) -#define CONFIG_SYS_PROMPT "B2> " -#else -#define CONFIG_SYS_PROMPT "SC> " -#endif - - -/* - * Use the "hush" command parser - */ -#define CONFIG_SYS_HUSH_PARSER - -/* - * Set buffer size for console I/O - */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 -#else -#define CONFIG_SYS_CBSIZE 256 -#endif - -/* - * Print buffer size - */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - -/* - * Maximum number of arguments that a command can accept - */ -#define CONFIG_SYS_MAXARGS 16 - -/* - * Boot argument buffer size - */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * Default memory test range - */ -#define CONFIG_SYS_MEMTEST_START 0x0100000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (128 * 1024)) - -/* - * Select the more full-featured memory test - */ -#define CONFIG_SYS_ALT_MEMTEST - -/* - * Default load address - */ -#define CONFIG_SYS_LOAD_ADDR 0x01000000 - -/* - * Device memory map (after SDRAM remap to 0x0): - * - * CS Device Base Addr Size - * ---------------------------------------------------- - * CS0* Flash 0x40000000 64 M - * CS1* SDRAM 0x00000000 16 M - * CS2* Disk-On-Chip 0x50000000 32 K - * CS3* FPGA 0x60000000 64 M - * CS4* SelectMap 0x70000000 32 K - * CS5* Mil-Std 1553 I/F 0x80000000 32 K - * CS6* Unused - * CS7* Unused - * IMMR 860T Registers 0xfff00000 - */ - -/* - * Base addresses and block sizes - */ -#define CONFIG_SYS_IMMR 0xFF000000 - -#define SDRAM_BASE 0x00000000 -#define SDRAM_SIZE (64 * 1024 * 1024) - -#define FLASH_BASE 0x40000000 -#define FLASH_SIZE (16 * 1024 * 1024) - -#define DOC_BASE 0x50000000 -#define DOC_SIZE (32 * 1024) - -#define FPGA_BASE 0x60000000 -#define FPGA_SIZE (64 * 1024 * 1024) - -#define SELECTMAP_BASE 0x70000000 -#define SELECTMAP_SIZE (32 * 1024) - -#define M1553_BASE 0x80000000 -#define M1553_SIZE (64 * 1024) - -/* - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_INIT_DATA_SIZE 64 /* # bytes reserved for initial data*/ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE SDRAM_BASE - -/* - * FLASH organization - */ -#define CONFIG_SYS_FLASH_BASE FLASH_BASE -#define CONFIG_SYS_FLASH_SIZE FLASH_SIZE -#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024) -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 128 - -/* - * The timeout values are for an entire chip and are in milliseconds. - * Yes I know that the write timeout is huge. Accroding to the - * datasheet a single byte takes 630 uS (round to 1 ms) max at worst - * case VCC and temp after 100K programming cycles. It works out - * to 280 minutes (might as well be forever). - */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (CONFIG_SYS_MAX_FLASH_SECT * 5000) -#define CONFIG_SYS_FLASH_WRITE_TOUT (CONFIG_SYS_MAX_FLASH_SECT * 128 * 1024 * 1) - -/* - * Allow direct writes to FLASH from tftp transfers (** dangerous **) - */ -#define CONFIG_SYS_DIRECT_FLASH_TFTP - -/* - * Reserve memory for U-Boot. - */ -#define CONFIG_SYS_MAX_UBOOT_SECTS 4 -#define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_MAX_UBOOT_SECTS * CONFIG_SYS_FLASH_SECT_SIZE) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE - -/* - * Select environment placement. NOTE that u-boot.lds must - * be edited if this is changed! - */ -#undef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_IS_IN_EEPROM - -#if defined(CONFIG_ENV_IS_IN_EEPROM) -#define CONFIG_ENV_SIZE (2 * 1024) -#define CONFIG_ENV_OFFSET (CONFIG_ENV_EEPROM_SIZE - (8 * 1024)) -#else -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SIZE - -/* - * This ultimately gets passed right into the linker script, so we have to - * use a number :( - */ -#define CONFIG_ENV_OFFSET 0x060000 -#endif - -/* - * Reserve memory for malloc() - */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) - -/* - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of above value */ -#endif - -/*------------------------------------------------------------------------ - * SYPCR - System Protection Control UM 11-9 - * ----------------------------------------------------------------------- - * SYPCR can only be written once after reset! - * - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR ( SYPCR_SWTC | \ - SYPCR_BMT | \ - SYPCR_BME | \ - SYPCR_SWF | \ - SYPCR_SWE | \ - SYPCR_SWRI | \ - SYPCR_SWP \ - ) -#else -#define CONFIG_SYS_SYPCR ( SYPCR_SWTC | \ - SYPCR_BMT | \ - SYPCR_BME | \ - SYPCR_SWF | \ - SYPCR_SWP \ - ) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration UM 11-6 - *----------------------------------------------------------------------- - * Set debug pin mux, enable SPKROUT and GPLB5*. - */ -#define CONFIG_SYS_SIUMCR ( SIUMCR_DBGC11 | \ - SIUMCR_DBPC11 | \ - SIUMCR_MLRC11 | \ - SIUMCR_GB5E \ - ) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control UM 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freeze enabled - */ -#define CONFIG_SYS_TBSCR ( TBSCR_REFA | \ - TBSCR_REFB | \ - TBSCR_TBF \ - ) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register UM 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC ( RTCSC_SEC | \ - RTCSC_ALR | \ - RTCSC_RTF | \ - RTCSC_RTE \ - ) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control UM 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR ( PISCR_PS | \ - PISCR_PITF \ - ) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register UM 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit. Set MF for 1:2:1 mode. - */ -#define CONFIG_SYS_PLPRCR ( ((0x1 << PLPRCR_MF_SHIFT) & PLPRCR_MF_MSK) | \ - PLPRCR_SPLSS | \ - PLPRCR_TEXPS | \ - PLPRCR_TMIST \ - ) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register UM 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 - -#if !defined(CONFIG_SC) -#define CONFIG_SYS_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \ - SCCR_COM00 | /* full strength CLKOUT */ \ - SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \ - SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \ - SCCR_DFNL000 | \ - SCCR_DFNH000 \ - ) -#else -#define CONFIG_SYS_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \ - SCCR_COM00 | /* full strength CLKOUT */ \ - SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \ - SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \ - SCCR_DFNL000 | \ - SCCR_DFNH000 | \ - SCCR_RTDIV | \ - SCCR_RTSEL \ - ) -#endif - -/*----------------------------------------------------------------------- - * DER - Debug Enable Register UM 37-46 - *----------------------------------------------------------------------- - * Mask all events that can cause entry into debug mode - */ -#define CONFIG_SYS_DER 0 - -/* - * Initialize Memory Controller: - * - * BR0 and OR0 (FLASH memory) - */ -#define FLASH_BASE0_PRELIM FLASH_BASE - -/* - * Flash address mask - */ -#define CONFIG_SYS_PRELIM_OR_AM 0xfe000000 - -/* - * FLASH timing: - * 33 Mhz bus with ACS = 11, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 - */ -#define CONFIG_SYS_OR_TIMING_FLASH ( OR_CSNT_SAM | \ - OR_ACS_DIV2 | \ - OR_BI | \ - OR_SCY_2_CLK | \ - OR_TRLX | \ - OR_EHTR \ - ) - -#define CONFIG_SYS_OR0_PRELIM ( CONFIG_SYS_PRELIM_OR_AM | \ - CONFIG_SYS_OR_TIMING_FLASH \ - ) - -#define CONFIG_SYS_BR0_PRELIM ( (FLASH_BASE0_PRELIM & BR_BA_MSK) | \ - BR_MS_GPCM | \ - BR_PS_8 | \ - BR_V \ - ) - -/* - * SDRAM configuration - */ -#define CONFIG_SYS_OR1_AM 0xfc000000 -#define CONFIG_SYS_OR1 ( (CONFIG_SYS_OR1_AM & OR_AM_MSK) | \ - OR_CSNT_SAM \ - ) - -#define CONFIG_SYS_BR1 ( (SDRAM_BASE & BR_BA_MSK) | \ - BR_MS_UPMA | \ - BR_PS_32 | \ - BR_V \ - ) - -/* - * Refresh rate 7.8 us (= 64 ms / 8K = 31.2 uS quad bursts) for one bank - * of 256 MBit SDRAM - */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 - -/* - * Periodic timer for refresh @ 33 MHz system clock - */ -#define CONFIG_SYS_MAMR_PTA 64 - -/* - * MAMR settings for SDRAM - */ -#define CONFIG_SYS_MAMR_8COL ( (CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | \ - MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | \ - MAMR_DSA_1_CYCL | \ - MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | \ - MAMR_WLFA_1X | \ - MAMR_TLFA_4X \ - ) - -/* - * CS2* configuration for Disk On Chip: - * 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1, - * no burst. - */ -#define CONFIG_SYS_OR2_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ - OR_CSNT_SAM | \ - OR_ACS_DIV2 | \ - OR_BI | \ - OR_SCY_2_CLK | \ - OR_TRLX | \ - OR_EHTR \ - ) - -#define CONFIG_SYS_BR2_PRELIM ( (DOC_BASE & BR_BA_MSK) | \ - BR_PS_8 | \ - BR_MS_GPCM | \ - BR_V \ - ) - -/* - * CS3* configuration for FPGA: - * 33 MHz bus with SCY=15, no burst. - * The FPGA uses TA and TEA to terminate bus cycles, but we - * clear SETA and set the cycle length to a large number so that - * the cycle will still complete even if there is a configuration - * error that prevents TA from asserting on FPGA accesss. - */ -#define CONFIG_SYS_OR3_PRELIM ( (0xfc000000 & OR_AM_MSK) | \ - OR_SCY_15_CLK | \ - OR_BI \ - ) - -#define CONFIG_SYS_BR3_PRELIM ( (FPGA_BASE & BR_BA_MSK) | \ - BR_PS_32 | \ - BR_MS_GPCM | \ - BR_V \ - ) -/* - * CS4* configuration for FPGA SelectMap configuration interface. - * 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge - * of GCLK1_50 - */ -#define CONFIG_SYS_OR4_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ - OR_G5LS | \ - OR_BI \ - ) - -#define CONFIG_SYS_BR4_PRELIM ( (SELECTMAP_BASE & BR_BA_MSK) | \ - BR_PS_8 | \ - BR_MS_UPMB | \ - BR_V \ - ) - -/* - * CS5* configuration for Mil-Std 1553 databus interface. - * 33 MHz bus, GPCM, no burst. - * The 1553 interface uses TA and TEA to terminate bus cycles, - * but we clear SETA and set the cycle length to a large number so that - * the cycle will still complete even if there is a configuration - * error that prevents TA from asserting on FPGA accesss. - */ -#define CONFIG_SYS_OR5_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ - OR_SCY_15_CLK | \ - OR_EHTR | \ - OR_TRLX | \ - OR_CSNT_SAM | \ - OR_BI \ - ) - -#define CONFIG_SYS_BR5_PRELIM ( (M1553_BASE & BR_BA_MSK) | \ - BR_PS_16 | \ - BR_MS_GPCM | \ - BR_V \ - ) - -/* - * FEC interrupt assignment - */ -#define FEC_INTERRUPT SIU_LEVEL1 - -/* - * Sanity checks - */ -#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) -#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured -#endif - -#endif /* __CONFIG_GEN860T_H */ diff --git a/include/configs/PCI5441.h b/include/configs/PCI5441.h deleted file mode 100644 index 7ae25d7b66..0000000000 --- a/include/configs/PCI5441.h +++ /dev/null @@ -1,150 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt@psyent.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*------------------------------------------------------------------------ - * BOARD/CPU - *----------------------------------------------------------------------*/ -#define CONFIG_PCI5441 1 /* PCI-5441 board */ -#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */ - -#define CONFIG_SYS_RESET_ADDR 0x00000000 /* Hard-reset address */ -#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/ -#define CONFIG_SYS_NIOS_SYSID_BASE 0x00920828 /* System id address */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ - -/*------------------------------------------------------------------------ - * CACHE -- the following will support II/s and II/f. The II/s does not - * have dcache, so the cache instructions will behave as NOPs. - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_ICACHE_SIZE 4096 /* 4 KByte total */ -#define CONFIG_SYS_ICACHELINE_SIZE 32 /* 32 bytes/line */ -#define CONFIG_SYS_DCACHE_SIZE 2048 /* 2 KByte (II/f) */ -#define CONFIG_SYS_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */ - -/*------------------------------------------------------------------------ - * MEMORY BASE ADDRESSES - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_FLASH_BASE 0x00000000 /* FLASH base addr */ -#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */ -#define CONFIG_SYS_SDRAM_BASE 0x01000000 /* SDRAM base addr */ -#define CONFIG_SYS_SDRAM_SIZE 0x01000000 /* 16 MByte */ - -/*------------------------------------------------------------------------ - * MEMORY ORGANIZATION - * -Monitor at top. - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MONITOR_LEN (128 * 1024) /* Reserve 128k */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET - -/*------------------------------------------------------------------------ - * FLASH (AM29LV065D) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size */ - -/*------------------------------------------------------------------------ - * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above - * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the - * reset address, no? This will keep the environment in user region - * of flash. NOTE: the monitor length must be multiple of sector size - * (which is common practice). - *----------------------------------------------------------------------*/ -#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */ -#define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ -#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_RESET_ADDR + CONFIG_SYS_MONITOR_LEN) - -/*------------------------------------------------------------------------ - * CONSOLE - *----------------------------------------------------------------------*/ -#define CONFIG_ALTERA_UART 1 /* Use altera uart */ -#if defined(CONFIG_ALTERA_JTAG_UART) -#define CONFIG_SYS_NIOS_CONSOLE 0x00920820 /* JTAG UART base addr */ -#else -#define CONFIG_SYS_NIOS_CONSOLE 0x009208a0 /* UART base addr */ -#endif - -#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ -#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ -#define CONFIG_SYS_BAUDRATE_TABLE {115200} /* It's fixed ;-) */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ - -/*------------------------------------------------------------------------ - * DEBUG - *----------------------------------------------------------------------*/ -#undef CONFIG_ROM_STUBS /* Stubs not in ROM */ - -/*------------------------------------------------------------------------ - * TIMEBASE -- - * - * The high res timer defaults to 1 msec. Since it includes the period - * registers, the interrupt frequency can be reduced using TMRCNT. - * If the default period is acceptable, TMRCNT can be left undefined. - * TMRMS represents the desired mecs per tick (msecs per interrupt). - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LOW_RES_TIMER -#define CONFIG_SYS_NIOS_TMRBASE 0x00920860 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/ -#define CONFIG_SYS_NIOS_TMRCNT \ - (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_BDI -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_IMI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_MISC -#define CONFIG_CMD_RUN -#define CONFIG_CMD_SAVES - - -/*------------------------------------------------------------------------ - * MISC - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LONGHELP /* Provide extended help*/ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */ -#define CONFIG_SYS_MAXARGS 16 /* Max command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg buf size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* Default load address */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* Start addr for test */ -#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_INIT_SP - 0x00020000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/PK1C20.h b/include/configs/PK1C20.h deleted file mode 100644 index e7d08647fc..0000000000 --- a/include/configs/PK1C20.h +++ /dev/null @@ -1,225 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt@psyent.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*------------------------------------------------------------------------ - * BOARD/CPU - *----------------------------------------------------------------------*/ -#define CONFIG_PK1C20 1 /* PK1C20 board */ -#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */ - -#define CONFIG_SYS_RESET_ADDR 0x00000000 /* Hard-reset address */ -#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/ -#define CONFIG_SYS_NIOS_SYSID_BASE 0x021208b8 /* System id address */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ - -/*------------------------------------------------------------------------ - * CACHE -- the following will support II/s and II/f. The II/s does not - * have dcache, so the cache instructions will behave as NOPs. - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_ICACHE_SIZE 4096 /* 4 KByte total */ -#define CONFIG_SYS_ICACHELINE_SIZE 32 /* 32 bytes/line */ -#define CONFIG_SYS_DCACHE_SIZE 2048 /* 2 KByte (II/f) */ -#define CONFIG_SYS_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */ - -/*------------------------------------------------------------------------ - * MEMORY BASE ADDRESSES - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_FLASH_BASE 0x00000000 /* FLASH base addr */ -#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */ -#define CONFIG_SYS_SDRAM_BASE 0x01000000 /* SDRAM base addr */ -#define CONFIG_SYS_SDRAM_SIZE 0x01000000 /* 16 MByte */ -#define CONFIG_SYS_SRAM_BASE 0x02000000 /* SRAM base addr */ -#define CONFIG_SYS_SRAM_SIZE 0x00100000 /* 1 MB (only 1M mapped)*/ - -/*------------------------------------------------------------------------ - * MEMORY ORGANIZATION - * -Monitor at top. - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 128k */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET - -/*------------------------------------------------------------------------ - * FLASH (AM29LV065D) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size */ - -/*------------------------------------------------------------------------ - * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above - * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the - * reset address, no? This will keep the environment in user region - * of flash. NOTE: the monitor length must be multiple of sector size - * (which is common practice). - *----------------------------------------------------------------------*/ -#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */ -#define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ -#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_RESET_ADDR + CONFIG_SYS_MONITOR_LEN) - -/*------------------------------------------------------------------------ - * CONSOLE - *----------------------------------------------------------------------*/ -#define CONFIG_ALTERA_UART 1 /* Use altera uart */ -#if defined(CONFIG_ALTERA_JTAG_UART) -#define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ -#else -#define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */ -#endif - -#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ -#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ -#define CONFIG_SYS_BAUDRATE_TABLE {115200} /* It's fixed ;-) */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ - -/*------------------------------------------------------------------------ - * EPCS Device -- wne CONFIG_SYS_NIOS_EPCSBASE is defined code/commands for - * epcs device access is enabled. The base address is the epcs - * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK. - * The register base is currently at offset 0x600 from the memory base. - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_NIOS_EPCSBASE 0x02100200 /* EPCS register base */ - -/*------------------------------------------------------------------------ - * DEBUG - *----------------------------------------------------------------------*/ -#undef CONFIG_ROM_STUBS /* Stubs not in ROM */ - -/*------------------------------------------------------------------------ - * TIMEBASE -- - * - * The high res timer defaults to 1 msec. Since it includes the period - * registers, the interrupt frequency can be reduced using TMRCNT. - * If the default period is acceptable, TMRCNT can be left undefined. - * TMRMS represents the desired mecs per tick (msecs per interrupt). - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LOW_RES_TIMER -#define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period */ -#define CONFIG_SYS_NIOS_TMRCNT \ - (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) - -/*------------------------------------------------------------------------ - * STATUS LED -- Provides a simple blinking led. For Nios2 each board - * must implement its own led routines -- leds are, after all, - * board-specific, no? - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */ -#define CONFIG_STATUS_LED /* Enable status driver */ -#define CONFIG_BOARD_SPECIFIC_LED - -#define STATUS_LED_BIT 1 /* Bit-0 on PIO */ -#define STATUS_LED_STATE 1 /* Blinking */ -#define STATUS_LED_PERIOD (500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec */ - -/*------------------------------------------------------------------------ - * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ... - * and really doesn't need any additional clutter. So I choose the lazy - * way out to avoid changes there -- define the base address to ensure - * cache bypass so there's no need to monkey with inx/outx macros. - *----------------------------------------------------------------------*/ -#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */ -#define CONFIG_SMC91111 /* Using SMC91c111 */ -#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ -#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */ - -#define CONFIG_ETHADDR 08:00:3e:26:0a:5b -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.2.21 -#define CONFIG_SERVERIP 192.168.2.16 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ - -#define CONFIG_CMD_BDI -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_IMI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_MISC -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_RUN -#define CONFIG_CMD_SAVES - - -/*------------------------------------------------------------------------ - * COMPACT FLASH - *----------------------------------------------------------------------*/ -#if defined(CONFIG_CMD_IDE) -#define CONFIG_IDE_PREINIT /* Implement id_preinit */ -#define CONFIG_SYS_IDE_MAXBUS 1 /* 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_BASE_ADDR 0x00900800 /* ATA base addr */ -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 /* IDE0 offset */ -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0040 /* Data IO offset */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0040 /* Register offset */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 /* Alternate reg offset */ -#define CONFIG_SYS_ATA_STRIDE 4 /* Width betwix addrs */ -#define CONFIG_DOS_PARTITION - -/* Board-specific cf regs */ -#define CONFIG_SYS_CF_PRESENT 0x00900880 /* CF Present PIO base */ -#define CONFIG_SYS_CF_POWER 0x00900890 /* CF Power FET PIO base*/ -#define CONFIG_SYS_CF_ATASEL 0x009008a0 /* CF ATASEL PIO base */ - -#endif - -/*------------------------------------------------------------------------ - * JFFS2 - *----------------------------------------------------------------------*/ -#if defined(CONFIG_CMD_JFFS2) -#define CONFIG_SYS_JFFS_CUSTOM_PART /* board defined part */ -#endif - -/*------------------------------------------------------------------------ - * MISC - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LONGHELP /* Provide extended help*/ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */ -#define CONFIG_SYS_MAXARGS 16 /* Max command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg buf size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* Default load address */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* Start addr for test */ -#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_INIT_SP - 0x00020000 - -#define CONFIG_SYS_HUSH_PARSER - -#endif /* __CONFIG_H */ diff --git a/include/configs/SXNI855T.h b/include/configs/SXNI855T.h deleted file mode 100644 index 38940194fb..0000000000 --- a/include/configs/SXNI855T.h +++ /dev/null @@ -1,378 +0,0 @@ -/* - * U-Boot configuration for SIXNET SXNI855T CPU board. - * This board is based (loosely) on the Motorola FADS board, so this - * file is based (loosely) on config_FADS860T.h, see it for additional - * credits. - * - * Copyright (c) 2000-2002 Dave Ellis, SIXNET, dge@sixnetio.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Memory map: - * - * ff100000 -> ff13ffff : FPGA CS1 - * ff030000 -> ff03ffff : EXPANSION CS7 - * ff020000 -> ff02ffff : DATA FLASH CS4 - * ff018000 -> ff01ffff : UART B CS6/UPMB - * ff010000 -> ff017fff : UART A CS5/UPMB - * ff000000 -> ff00ffff : IMAP internal to the MPC855T - * f8000000 -> fbffffff : FLASH CS0 up to 64MB - * f4000000 -> f7ffffff : NVSRAM CS2 up to 64MB - * 00000000 -> 0fffffff : SDRAM CS3/UPMA up to 256MB - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#include <mpc8xx_irq.h> - -#define CONFIG_SXNI855T 1 /* SIXNET IPm 855T CPU module */ - -/* The 855T is just a stripped 860T and needs code for 860, so for now - * at least define 860, 860T and 855T - */ -#define CONFIG_MPC860 1 -#define CONFIG_MPC860T 1 -#define CONFIG_MPC855T 1 - -#define CONFIG_SYS_TEXT_BASE 0xF8000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_SCC1 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ - -#define MPC8XX_FACT 10 /* 50 MHz is 5 MHz in times 10 */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_HAS_ETH1 - -/*----------------------------------------------------------------------- - * Definitions for status LED - */ -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -# define STATUS_LED_PAR im_ioport.iop_papar -# define STATUS_LED_DIR im_ioport.iop_padir -# define STATUS_LED_ODR im_ioport.iop_paodr -# define STATUS_LED_DAT im_ioport.iop_padat - -# define STATUS_LED_BIT 0x8000 /* LED 0 is on PA.0 */ -# define STATUS_LED_PERIOD ((CONFIG_SYS_HZ / 2) / 5) /* blink at 5 Hz */ -# define STATUS_LED_STATE STATUS_LED_BLINKING - -# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ - -# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ - -#ifdef DEV /* development (debug) settings */ -#define CONFIG_BOOT_LED_STATE STATUS_LED_OFF -#else /* production settings */ -#define CONFIG_BOOT_LED_STATE STATUS_LED_ON -#endif - -#define CONFIG_SHOW_BOOT_PROGRESS 1 - -#define CONFIG_BOOTCOMMAND "bootm f8040000 f8100000" /* autoboot command */ -#define CONFIG_BOOTARGS "root=/dev/ram ip=off" - -#define CONFIG_MISC_INIT_R /* have misc_init_r() function */ -#define CONFIG_BOARD_POSTCLK_INIT /* have board_postclk_init() function */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_RTC_DS1306 /* Dallas 1306 real time clock */ - -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Atmel 24C64 */ -# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ - -#define CONFIG_FEC_ENET 1 /* use FEC ethernet */ -#define CONFIG_MII 1 - -#define CONFIG_SYS_DISCOVER_PHY - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_DATE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save a little memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 -#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SRAM_BASE 0xF4000000 -#define CONFIG_SYS_SRAM_SIZE 0x04000000 /* autosize up to 64Mbyte */ - -#define CONFIG_SYS_FLASH_BASE 0xF8000000 -#define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ - -#define CONFIG_SYS_DFLASH_BASE 0xff020000 /* DiskOnChip or NAND FLASH */ -#define CONFIG_SYS_DFLASH_SIZE 0x00010000 - -#define CONFIG_SYS_FPGA_BASE 0xFF100000 /* Xilinx FPGA */ -#define CONFIG_SYS_FPGA_PROG 0xFF130000 /* Programming address */ -#define CONFIG_SYS_FPGA_SIZE 0x00040000 /* 256KiB usable */ - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -/* Intel 28F640 has 135, 127 64K sectors in 8MB, + 8 more for 8K boot blocks. - * AMD 29LV641 has 128 64K sectors in 8MB - */ -#define CONFIG_SYS_MAX_FLASH_SECT 135 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * set the PLL, the low-power modes and the reset control (15-29) - */ -#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00) - - /*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the - * entire address space, we have to set the memory controller - * differently. Normally, you write the option register - * first, and then enable the chip select by writing the - * base register. For CS0, you must write the base register - * first, followed by the option register. - */ - -/* - * Init Memory Controller: - * - ********************************************************** - * BR0 and OR0 (FLASH) - */ - -#define CONFIG_SYS_PRELIM_OR0_AM 0xFC000000 /* OR addr mask */ - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR0_AM | CONFIG_SYS_OR_TIMING_FLASH) - -#define CONFIG_FLASH_16BIT -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V ) -#define CONFIG_SYS_FLASH_PROTECTION /* need to lock/unlock sectors in hardware */ - -/********************************************************** - * BR1 and OR1 (FPGA) - * These preliminary values are also the final values. - */ -#define CONFIG_SYS_OR_TIMING_FPGA \ - (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_4_CLK | OR_EHTR | OR_TRLX) -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_FPGA_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) -#define CONFIG_SYS_OR1_PRELIM (((-CONFIG_SYS_FPGA_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_FPGA) - -/********************************************************** - * BR4 and OR4 (data flash) - * These preliminary values are also the final values. - */ -#define CONFIG_SYS_OR_TIMING_DFLASH \ - (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK | OR_EHTR | OR_TRLX) -#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_DFLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) -#define CONFIG_SYS_OR4_PRELIM (((-CONFIG_SYS_DFLASH_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_DFLASH) - -/********************************************************** - * BR5/6 and OR5/6 (Dual UART) - */ -#define CONFIG_SYS_DUART_SIZE 0x8000 /* 32K window, only uses 8 bytes */ -#define CONFIG_SYS_DUARTA_BASE 0xff010000 -#define CONFIG_SYS_DUARTB_BASE 0xff018000 - -#define DUART_MBMR 0 -#define DUART_OR_VALUE (ORMASK(CONFIG_SYS_DUART_SIZE) | OR_G5LS| OR_BI) -#define DUART_BR_VALUE (BR_MS_UPMB | BR_PS_8 | BR_V) -#define DUART_BR5_VALUE ((CONFIG_SYS_DUARTA_BASE & BR_BA_MSK ) | DUART_BR_VALUE) -#define DUART_BR6_VALUE ((CONFIG_SYS_DUARTB_BASE & BR_BA_MSK ) | DUART_BR_VALUE) - -#define CONFIG_RESET_ON_PANIC /* reset if system panic() */ - -#define CONFIG_ENV_IS_IN_FLASH -#ifdef CONFIG_ENV_IS_IN_FLASH - /* environment is in FLASH */ - #define CONFIG_ENV_ADDR 0xF8040000 /* AM29LV641 or AM29LV800BT */ - #define CONFIG_ENV_ADDR_REDUND 0xF8050000 /* AM29LV641 or AM29LV800BT */ - #define CONFIG_ENV_SECT_SIZE 0x00010000 - #define CONFIG_ENV_SIZE 0x00002000 -#else - /* environment is in EEPROM */ - #define CONFIG_ENV_IS_IN_EEPROM 1 - #define CONFIG_ENV_OFFSET 0 /* at beginning of EEPROM */ - #define CONFIG_ENV_SIZE 1024 /* Use only a part of it*/ -#endif - -#if 1 -#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ -#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay -#define CONFIG_AUTOBOOT_DELAY_STR "delayabit" -#define CONFIG_AUTOBOOT_STOP_STR " " /* easy to stop for now */ -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index ebee89a9a1..a781ba327a 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -416,6 +416,7 @@ unsigned long get_board_ddr_clk(void); /* Video */ #define CONFIG_FSL_DIU_FB #ifdef CONFIG_FSL_DIU_FB +#define CONFIG_FSL_DIU_CH7301 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) #define CONFIG_VIDEO #define CONFIG_CMD_BMP diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index c4bf0d68f4..0ee0ff242d 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -32,7 +32,7 @@ #define CONFIG_SPL_I2C_SUPPORT #define CONFIG_SPL_DRIVERS_MISC_SUPPORT #define CONFIG_FSL_LAW /* Use common FSL init code */ -#define CONFIG_SYS_TEXT_BASE 0x00201000 +#define CONFIG_SYS_TEXT_BASE 0x30001000 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 #define CONFIG_SPL_PAD_TO 0x40000 #define CONFIG_SPL_MAX_SIZE 0x28000 @@ -48,21 +48,21 @@ #ifdef CONFIG_NAND #define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" #define CONFIG_SPL_NAND_BOOT #endif #ifdef CONFIG_SPIFLASH -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC #define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_FLASH_MINIMAL #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" #ifndef CONFIG_SPL_BUILD @@ -72,12 +72,12 @@ #endif #ifdef CONFIG_SDCARD -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SPL_MMC_MINIMAL #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) +#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) +#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" #ifndef CONFIG_SPL_BUILD @@ -268,6 +268,9 @@ #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ #define CPLD_LBMAP_RESET 0xFF #define CPLD_LBMAP_SHIFT 0x03 +#ifdef CONFIG_T1042RDB_PI +#define CPLD_DIU_SEL_DFP 0x80 +#endif #define CONFIG_SYS_CPLD_BASE 0xffdf0000 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) @@ -429,6 +432,24 @@ #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#ifdef CONFIG_T1042RDB_PI +/* Video */ +#define CONFIG_FSL_DIU_FB + +#ifdef CONFIG_FSL_DIU_FB +#define CONFIG_FSL_DIU_CH7301 +#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) +#define CONFIG_VIDEO +#define CONFIG_CMD_BMP +#define CONFIG_CFB_CONSOLE +#define CONFIG_CFB_CONSOLE_ANSI +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#endif +#endif + /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT #define CONFIG_OF_BOARD_SETUP @@ -461,6 +482,10 @@ #endif #ifdef CONFIG_T1042RDB_PI +/* LDI/DVI Encoder for display */ +#define CONFIG_SYS_I2C_LDI_ADDR 0x38 +#define CONFIG_SYS_I2C_DVI_ADDR 0x75 + /* * RTC configuration */ @@ -772,11 +797,18 @@ #define RAMDISKFILE "t1040rdb_pi/ramdisk.uboot" #endif +#ifdef CONFIG_FSL_DIU_FB +#define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" +#else +#define DIU_ENVIRONMENT +#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ "netdev=eth0\0" \ + "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ "tftpflash=tftpboot $loadaddr $uboot && " \ diff --git a/include/configs/exynos4-dt.h b/include/configs/exynos4-dt.h index 44e6ab4ef3..7dac1a3717 100644 --- a/include/configs/exynos4-dt.h +++ b/include/configs/exynos4-dt.h @@ -105,6 +105,8 @@ #define CONFIG_G_DNL_PRODUCT_NUM 0x6601 #define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM #define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D +#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 +#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 #define CONFIG_G_DNL_MANUFACTURER "Samsung" /* Miscellaneous configurable options */ diff --git a/include/configs/km/km-powerpc.h b/include/configs/km/km-powerpc.h index 763c5bad82..eb85a74919 100644 --- a/include/configs/km/km-powerpc.h +++ b/include/configs/km/km-powerpc.h @@ -59,8 +59,9 @@ #define CONFIG_KM_PHRAM 0x100000 /* resereved pram area at the end of memroy [hex] */ #define CONFIG_KM_RESERVED_PRAM 0x0 -/* enable protected RAM */ -#define CONFIG_PRAM 0 +/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable + * is not valid yet, which is the case for when u-boot copies itself to RAM */ +#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10) #define CONFIG_KM_CRAMFS_ADDR 0x800000 #define CONFIG_KM_KERNEL_ADDR 0x400000 /* 3968Kbytes */ diff --git a/include/configs/nios2-generic.h b/include/configs/nios2-generic.h index 1578b010b9..51b1d00d99 100644 --- a/include/configs/nios2-generic.h +++ b/include/configs/nios2-generic.h @@ -15,6 +15,8 @@ #include "../board/altera/nios2-generic/custom_fpga.h" /* fpga parameters */ #define CONFIG_BOARD_NAME "nios2-generic" /* custom board name */ #define CONFIG_BOARD_EARLY_INIT_F /* enable early board-spec. init */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_NIOS_SYSID_BASE CONFIG_SYS_SYSID_BASE /* diff --git a/include/configs/omap1510.h b/include/configs/omap1510.h deleted file mode 100644 index 5482722561..0000000000 --- a/include/configs/omap1510.h +++ /dev/null @@ -1,756 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * OMAP hardware map - * - * Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com) - * Author: RidgeRun, Inc. - * Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <linux/sizes.h> - -/* - There are 2 sets of general I/O --> - 1. GPIO (shared between ARM & DSP, configured by ARM) - 2. MPUIO which can be used only by the ARM. - - Base address FFFB:5000 is where the ARM accesses the MPUIO control registers - (see 7.2.2 of the TRM for MPUIO reg definitions). - - Base address E101:5000 is reserved for ARM access of the same MPUIO control - regs, but via the DSP I/O map. This address is unavailable on 1510. - - Base address FFFC:E000 is where the ARM accesses the GPIO config registers - directly via its own peripheral bus. - - Base address E101:E000 is where the ARM can access the same GPIO config - registers, but the access takes place through the ARM port interface (called - API or MPUI) via the DSP's peripheral bus (DSP I/O space). - - Therefore, the ARM should setup the GPIO regs thru the FFFC:E000 addresses - instead of the E101:E000 addresses. The DSP has only read access of the pin - control register, so this may explain the inability to write to E101:E018. - Try accessing pin control reg at FFFC:E018. - */ -#define OMAP1510_GPIO_BASE 0xfffce000 -#define OMAP1510_GPIO_START OMAP1510_GPIO_BASE -#define OMAP1510_GPIO_SIZE SZ_4K - -#define OMAP1510_MCBSP1_BASE 0xE1011000 -#define OMAP1510_MCBSP1_SIZE SZ_4K -#define OMAP1510_MCBSP1_START 0xE1011000 - -#define OMAP1510_MCBSP2_BASE 0xFFFB1000 - -#define OMAP1510_MCBSP3_BASE 0xE1017000 -#define OMAP1510_MCBSP3_SIZE SZ_4K -#define OMAP1510_MCBSP3_START 0xE1017000 - -/* - * Where's the flush address (for flushing D and I cache?) - */ -#define FLUSH_BASE 0xdf000000 -#define FLUSH_BASE_PHYS 0x00000000 - -#ifndef __ASSEMBLER__ - -#define PCIO_BASE 0 - -/* - * RAM definitions - */ -#define MAPTOPHYS(a) ((unsigned long)(a) - PAGE_OFFSET) -#define KERNTOPHYS(a) ((unsigned long)(&a)) -#define KERNEL_BASE (0x10008000) -#endif - -/* macro to get at IO space when running virtually */ -#define IO_ADDRESS(x) ((x)) - -/* ---------------------------------------------------------------------------- - * OMAP1510 system registers - * ---------------------------------------------------------------------------- - */ - -#define OMAP1510_UART1_BASE 0xfffb0000 /* "BLUETOOTH-UART" */ -#define OMAP1510_UART2_BASE 0xfffb0800 /* "MODEM-UART" */ -#define OMAP1510_RTC_BASE 0xfffb4800 /* RTC */ -#define OMAP1510_UART3_BASE 0xfffb9800 /* Shared MPU/DSP UART */ -#define OMAP1510_COM_MCBSP2_BASE 0xffff1000 /* Com McBSP2 */ -#define OMAP1510_AUDIO_MCBSP_BASE 0xffff1800 /* Audio McBSP2 */ -#define OMAP1510_ARMIO_BASE 0xfffb5000 /* keyboard/gpio */ - -/* - * OMAP1510 UART3 Registers - */ - -#define OMAP_MPU_UART3_BASE 0xFFFB9800 /* UART3 through MPU bus */ - -/* UART3 Registers Maping through MPU bus */ - -#define UART3_RHR (OMAP_MPU_UART3_BASE + 0) -#define UART3_THR (OMAP_MPU_UART3_BASE + 0) -#define UART3_DLL (OMAP_MPU_UART3_BASE + 0) -#define UART3_IER (OMAP_MPU_UART3_BASE + 4) -#define UART3_DLH (OMAP_MPU_UART3_BASE + 4) -#define UART3_IIR (OMAP_MPU_UART3_BASE + 8) -#define UART3_FCR (OMAP_MPU_UART3_BASE + 8) -#define UART3_EFR (OMAP_MPU_UART3_BASE + 8) -#define UART3_LCR (OMAP_MPU_UART3_BASE + 0x0C) -#define UART3_MCR (OMAP_MPU_UART3_BASE + 0x10) -#define UART3_XON1_ADDR1 (OMAP_MPU_UART3_BASE + 0x10) -#define UART3_XON2_ADDR2 (OMAP_MPU_UART3_BASE + 0x14) -#define UART3_LSR (OMAP_MPU_UART3_BASE + 0x14) -#define UART3_TCR (OMAP_MPU_UART3_BASE + 0x18) -#define UART3_MSR (OMAP_MPU_UART3_BASE + 0x18) -#define UART3_XOFF1 (OMAP_MPU_UART3_BASE + 0x18) -#define UART3_XOFF2 (OMAP_MPU_UART3_BASE + 0x1C) -#define UART3_SPR (OMAP_MPU_UART3_BASE + 0x1C) -#define UART3_TLR (OMAP_MPU_UART3_BASE + 0x1C) -#define UART3_MDR1 (OMAP_MPU_UART3_BASE + 0x20) -#define UART3_MDR2 (OMAP_MPU_UART3_BASE + 0x24) -#define UART3_SFLSR (OMAP_MPU_UART3_BASE + 0x28) -#define UART3_TXFLL (OMAP_MPU_UART3_BASE + 0x28) -#define UART3_RESUME (OMAP_MPU_UART3_BASE + 0x2C) -#define UART3_TXFLH (OMAP_MPU_UART3_BASE + 0x2C) -#define UART3_SFREGL (OMAP_MPU_UART3_BASE + 0x30) -#define UART3_RXFLL (OMAP_MPU_UART3_BASE + 0x30) -#define UART3_SFREGH (OMAP_MPU_UART3_BASE + 0x34) -#define UART3_RXFLH (OMAP_MPU_UART3_BASE + 0x34) -#define UART3_BLR (OMAP_MPU_UART3_BASE + 0x38) -#define UART3_ACREG (OMAP_MPU_UART3_BASE + 0x3C) -#define UART3_DIV16 (OMAP_MPU_UART3_BASE + 0x3C) -#define UART3_SCR (OMAP_MPU_UART3_BASE + 0x40) -#define UART3_SSR (OMAP_MPU_UART3_BASE + 0x44) -#define UART3_EBLR (OMAP_MPU_UART3_BASE + 0x48) -#define UART3_OSC_12M_SEL (OMAP_MPU_UART3_BASE + 0x4C) -#define UART3_MVR (OMAP_MPU_UART3_BASE + 0x50) - -/* - * Configuration Registers - */ -#define FUNC_MUX_CTRL_0 0xfffe1000 -#define FUNC_MUX_CTRL_1 0xfffe1004 -#define FUNC_MUX_CTRL_2 0xfffe1008 -#define COMP_MODE_CTRL_0 0xfffe100c -#define FUNC_MUX_CTRL_3 0xfffe1010 -#define FUNC_MUX_CTRL_4 0xfffe1014 -#define FUNC_MUX_CTRL_5 0xfffe1018 -#define FUNC_MUX_CTRL_6 0xfffe101C -#define FUNC_MUX_CTRL_7 0xfffe1020 -#define FUNC_MUX_CTRL_8 0xfffe1024 -#define FUNC_MUX_CTRL_9 0xfffe1028 -#define FUNC_MUX_CTRL_A 0xfffe102C -#define FUNC_MUX_CTRL_B 0xfffe1030 -#define FUNC_MUX_CTRL_C 0xfffe1034 -#define FUNC_MUX_CTRL_D 0xfffe1038 -#define PULL_DWN_CTRL_0 0xfffe1040 -#define PULL_DWN_CTRL_1 0xfffe1044 -#define PULL_DWN_CTRL_2 0xfffe1048 -#define PULL_DWN_CTRL_3 0xfffe104c -#define GATE_INH_CTRL_0 0xfffe1050 -#define VOLTAGE_CTRL_0 0xfffe1060 -#define TEST_DBG_CTRL_0 0xfffe1070 - -#define MOD_CONF_CTRL_0 0xfffe1080 - -#ifdef CONFIG_OMAP1610 /* 1610 Configuration Register */ - -#define USB_OTG_CTRL 0xFFFB040C -#define USB_TRANSCEIVER_CTRL 0xFFFE1064 -#define PULL_DWN_CTRL_4 0xFFFE10AC -#define PU_PD_SEL_0 0xFFFE10B4 -#define PU_PD_SEL_1 0xFFFE10B8 -#define PU_PD_SEL_2 0xFFFE10BC -#define PU_PD_SEL_3 0xFFFE10C0 -#define PU_PD_SEL_4 0xFFFE10C4 - -#endif -/* - * Traffic Controller Memory Interface Registers - */ -#define TCMIF_BASE 0xfffecc00 -#define IMIF_PRIO (TCMIF_BASE + 0x00) -#define EMIFS_PRIO_REG (TCMIF_BASE + 0x04) -#define EMIFF_PRIO_REG (TCMIF_BASE + 0x08) -#define EMIFS_CONFIG_REG (TCMIF_BASE + 0x0c) -#define EMIFS_CS0_CONFIG (TCMIF_BASE + 0x10) -#define EMIFS_CS1_CONFIG (TCMIF_BASE + 0x14) -#define EMIFS_CS2_CONFIG (TCMIF_BASE + 0x18) -#define EMIFS_CS3_CONFIG (TCMIF_BASE + 0x1c) -#define EMIFF_SDRAM_CONFIG (TCMIF_BASE + 0x20) -#define EMIFF_MRS (TCMIF_BASE + 0x24) -#define TC_TIMEOUT1 (TCMIF_BASE + 0x28) -#define TC_TIMEOUT2 (TCMIF_BASE + 0x2c) -#define TC_TIMEOUT3 (TCMIF_BASE + 0x30) -#define TC_ENDIANISM (TCMIF_BASE + 0x34) -#define EMIFF_SDRAM_CONFIG_2 (TCMIF_BASE + 0x3c) -#define EMIF_CFG_DYNAMIC_WS (TCMIF_BASE + 0x40) - -/* - * LCD Panel - */ -#define TI925_LCD_BASE 0xFFFEC000 -#define TI925_LCD_CONTROL (TI925_LCD_BASE) -#define TI925_LCD_TIMING0 (TI925_LCD_BASE+0x4) -#define TI925_LCD_TIMING1 (TI925_LCD_BASE+0x8) -#define TI925_LCD_TIMING2 (TI925_LCD_BASE+0xc) -#define TI925_LCD_STATUS (TI925_LCD_BASE+0x10) -#define TI925_LCD_SUBPANEL (TI925_LCD_BASE+0x14) - -#define OMAP_LCD_CONTROL TI925_LCD_CONTROL - -/* I2C Registers */ - -#define I2C_BASE 0xfffb3800 - -#define I2C_REV (I2C_BASE + 0x00) -#define I2C_IE (I2C_BASE + 0x04) -#define I2C_STAT (I2C_BASE + 0x08) -#define I2C_IV (I2C_BASE + 0x0c) -#define I2C_BUF (I2C_BASE + 0x14) -#define I2C_CNT (I2C_BASE + 0x18) -#define I2C_DATA (I2C_BASE + 0x1c) -#define I2C_CON (I2C_BASE + 0x24) -#define I2C_OA (I2C_BASE + 0x28) -#define I2C_SA (I2C_BASE + 0x2c) -#define I2C_PSC (I2C_BASE + 0x30) -#define I2C_SCLL (I2C_BASE + 0x34) -#define I2C_SCLH (I2C_BASE + 0x38) -#define I2C_SYSTEST (I2C_BASE + 0x3c) - -/* I2C masks */ - -/* I2C Interrupt Enable Register (I2C_IE): */ - -#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ -#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ -#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ -#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ - -/* I2C Status Register (I2C_STAT): */ - -#define I2C_STAT_SBD (1 << 15) /* Single byte data */ -#define I2C_STAT_BB (1 << 12) /* Bus busy */ -#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ -#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ -#define I2C_STAT_AAS (1 << 9) /* Address as slave */ -#define I2C_STAT_AD0 (1 << 8) /* Address zero */ -#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ -#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ -#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ -#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ - -/* I2C Interrupt Vector Register (I2C_IV): */ - -/* I2C Interrupt Code Register (I2C_INTCODE): */ - -#define I2C_INTCODE_MASK 7 -#define I2C_INTCODE_NONE 0 -#define I2C_INTCODE_AL 1 /* Arbitration lost */ -#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ -#define I2C_INTCODE_ARDY 3 /* Register access ready */ -#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ -#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ - -/* I2C Buffer Configuration Register (I2C_BUF): */ - -#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */ -#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */ - -/* I2C Configuration Register (I2C_CON): */ - -#define I2C_CON_EN (1 << 15) /* I2C module enable */ -#define I2C_CON_BE (1 << 14) /* Big endian mode */ -#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ -#define I2C_CON_MST (1 << 10) /* Master/slave mode */ -#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */ -#define I2C_CON_XA (1 << 8) /* Expand address */ -#define I2C_CON_RM (1 << 2) /* Repeat mode (master mode only) */ -#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ -#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ - -/* I2C System Test Register (I2C_SYSTEST): */ - -#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ -#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode (on breakpoint) */ -#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ -#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ -#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */ -#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */ -#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */ -#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */ - -/* - * MMC/SD Host Controller Registers - */ - -#define OMAP_MMC_CMD 0xFFFB7800 /* MMC Command */ -#define OMAP_MMC_ARGL 0xFFFB7804 /* MMC argument low */ -#define OMAP_MMC_ARGH 0xFFFB7808 /* MMC argument high */ -#define OMAP_MMC_CON 0xFFFB780C /* MMC system configuration */ -#define OMAP_MMC_STAT 0xFFFB7810 /* MMC status */ -#define OMAP_MMC_IE 0xFFFB7814 /* MMC system interrupt enable */ -#define OMAP_MMC_CTO 0xFFFB7818 /* MMC command time-out */ -#define OMAP_MMC_DTO 0xFFFB781C /* MMC data time-out */ -#define OMAP_MMC_DATA 0xFFFB7820 /* MMC TX/RX FIFO data */ -#define OMAP_MMC_BLEN 0xFFFB7824 /* MMC block length */ -#define OMAP_MMC_NBLK 0xFFFB7828 /* MMC number of blocks */ -#define OMAP_MMC_BUF 0xFFFB782C /* MMC buffer configuration */ -#define OMAP_MMC_SPI 0xFFFB7830 /* MMC serial port interface */ -#define OMAP_MMC_SDIO 0xFFFB7834 /* MMC SDIO mode configuration */ -#define OMAP_MMC_SYST 0xFFFB7838 /* MMC system test */ -#define OMAP_MMC_REV 0xFFFB783C /* MMC module version */ -#define OMAP_MMC_RSP0 0xFFFB7840 /* MMC command response 0 */ -#define OMAP_MMC_RSP1 0xFFFB7844 /* MMC command response 1 */ -#define OMAP_MMC_RSP2 0xFFFB7848 /* MMC command response 2 */ -#define OMAP_MMC_RSP3 0xFFFB784C /* MMC command response 3 */ -#define OMAP_MMC_RSP4 0xFFFB7850 /* MMC command response 4 */ -#define OMAP_MMC_RSP5 0xFFFB7854 /* MMC command response 5 */ -#define OMAP_MMC_RSP6 0xFFFB7858 /* MMC command response 6 */ -#define OMAP_MMC_RSP7 0xFFFB785C /* MMC command response 4 */ - -/* MMC masks */ - -#define OMAP_MMC_END_OF_CMD (1 << 0) /* End of command phase */ -#define OMAP_MMC_CARD_BUSY (1 << 2) /* Card enter busy state */ -#define OMAP_MMC_BLOCK_RS (1 << 3) /* Block received/sent */ -#define OMAP_MMC_EOF_BUSY (1 << 4) /* Card exit busy state */ -#define OMAP_MMC_DATA_TIMEOUT (1 << 5) /* Data response time-out */ -#define OMAP_MMC_DATA_CRC (1 << 6) /* Date CRC error */ -#define OMAP_MMC_CMD_TIMEOUT (1 << 7) /* Command response time-out */ -#define OMAP_MMC_CMD_CRC (1 << 8) /* Command CRC error */ -#define OMAP_MMC_A_FULL (1 << 10) /* Buffer almost full */ -#define OMAP_MMC_A_EMPTY (1 << 11) /* Buffer almost empty */ -#define OMAP_MMC_OCR_BUSY (1 << 12) /* OCR busy */ -#define OMAP_MMC_CARD_IRQ (1 << 13) /* Card IRQ received */ -#define OMAP_MMC_CARD_ERR (1 << 14) /* Card status error in response */ - -/* 2.9.2 MPUI Interface Registers FFFE:C900 */ - -#define MPUI_CTRL_REG (volatile __u32 *)(0xfffec900) -#define MPUI_DEBUG_ADDR (volatile __u32 *)(0xfffec904) -#define MPUI_DEBUG_DATA (volatile __u32 *)(0xfffec908) -#define MPUI_DEBUG_FLAG (volatile __u16 *)(0xfffec90c) -#define MPUI_STATUS_REG (volatile __u16 *)(0xfffec910) -#define MPUI_DSP_STATUS_REG (volatile __u16 *)(0xfffec914) -#define MPUI_DSP_BOOT_CONFIG (volatile __u16 *)(0xfffec918) -#define MPUI_DSP_API_CONFIG (volatile __u16 *)(0xfffec91c) - -/* 2.9.6 Traffic Controller Memory Interface Registers: */ -#define OMAP_IMIF_PRIO_REG 0xfffecc00 -#define OMAP_EMIFS_PRIO_REG 0xfffecc04 -#define OMAP_EMIFF_PRIO_REG 0xfffecc08 -#define OMAP_EMIFS_CONFIG_REG 0xfffecc0c -#define OMAP_EMIFS_CS0_CONFIG 0xfffecc10 -#define OMAP_EMIFS_CS1_CONFIG 0xfffecc14 -#define OMAP_EMIFS_CS2_CONFIG 0xfffecc18 -#define OMAP_EMIFS_CS3_CONFIG 0xfffecc1c -#define OMAP_EMIFF_SDRAM_CONFIG 0xfffecc20 -#define OMAP_EMIFF_MRS 0xfffecc24 -#define OMAP_TIMEOUT1 0xfffecc28 -#define OMAP_TIMEOUT2 0xfffecc2c -#define OMAP_TIMEOUT3 0xfffecc30 -#define OMAP_ENDIANISM 0xfffecc34 - -/* 2.9.10 EMIF Slow Interface Configuration Register (EMIFS_CONFIG_REG): */ -#define OMAP_EMIFS_CONFIG_FR (1 << 4) -#define OMAP_EMIFS_CONFIG_PDE (1 << 3) -#define OMAP_EMIFS_CONFIG_PWD_EN (1 << 2) -#define OMAP_EMIFS_CONFIG_BM (1 << 1) -#define OMAP_EMIFS_CONFIG_WP (1 << 0) - -/* - * Memory chunk set aside for the Framebuffer in SRAM - */ -#define SRAM_FRAMEBUFFER_MEMORY OMAP1510_SRAM_BASE - - -/* - * DMA - */ - -#define OMAP1510_DMA_BASE 0xFFFED800 -#define OMAP_DMA_BASE OMAP1510_DMA_BASE - -/* Global Register selection */ -#define NO_GLOBAL_DMA_ACCESS 0 - -/* Channel select field - * NOTE: all other channels are linear, chan0 is 0, chan1 is 1, etc... - */ -#define LCD_CHANNEL 0xc - -/* Register Select Field (LCD) */ -#define DMA_LCD_CTRL 0 -#define DMA_LCD_TOP_F1_L 1 -#define DMA_LCD_TOP_F1_U 2 -#define DMA_LCD_BOT_F1_L 3 -#define DMA_LCD_BOT_F1_U 4 - -#define LCD_FRAME_MODE (1<<0) -#define LCD_FRAME_IT_IE (1<<1) -#define LCD_BUS_ERROR_IT_IE (1<<2) -#define LCD_FRAME_1_IT_COND (1<<3) -#define LCD_FRAME_2_IT_COND (1<<4) -#define LCD_BUS_ERROR_IT_COND (1<<5) -#define LCD_SOURCE_IMIF (1<<6) - -/* - * Real-Time Clock - */ - -#define RTC_SECONDS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x00) -#define RTC_MINUTES (volatile __u8 *)(OMAP1510_RTC_BASE + 0x04) -#define RTC_HOURS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x08) -#define RTC_DAYS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x0C) -#define RTC_MONTHS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x10) -#define RTC_YEARS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x14) -#define RTC_CTRL (volatile __u8 *)(OMAP1510_RTC_BASE + 0x40) - - -/* --------------------------------------------------------------------------- - * OMAP1510 Interrupt Handlers - * --------------------------------------------------------------------------- - * - */ -#define OMAP_IH1_BASE 0xfffecb00 -#define OMAP_IH2_BASE 0xfffe0000 -#define OMAP1510_ITR 0x0 -#define OMAP1510_MASK 0x4 - -#define INTERRUPT_HANDLER_BASE OMAP_IH1_BASE -#define INTERRUPT_INPUT_REGISTER OMAP1510_ITR -#define INTERRUPT_MASK_REGISTER OMAP1510_MASK - - -/* --------------------------------------------------------------------------- - * OMAP1510 TIMERS - * --------------------------------------------------------------------------- - * - */ - -#define OMAP1510_32kHz_TIMER_BASE 0xfffb9000 - -/* 32k Timer Registers */ -#define TIMER32k_CR 0x08 -#define TIMER32k_TVR 0x00 -#define TIMER32k_TCR 0x04 - -/* 32k Timer Control Register definition */ -#define TIMER32k_TSS (1<<0) -#define TIMER32k_TRB (1<<1) -#define TIMER32k_INT (1<<2) -#define TIMER32k_ARL (1<<3) - -/* MPU Timer base addresses */ -#define OMAP1510_MPUTIMER_BASE 0xfffec500 -#define OMAP1510_MPUTIMER_OFF 0x00000100 - -#define OMAP1510_TIMER1_BASE 0xfffec500 -#define OMAP1510_TIMER2_BASE 0xfffec600 -#define OMAP1510_TIMER3_BASE 0xfffec700 - -/* MPU Timer Registers */ -#define CNTL_TIMER 0 -#define LOAD_TIM 4 -#define READ_TIM 8 - -/* CNTL_TIMER register bits */ -#define MPUTIM_FREE (1<<6) -#define MPUTIM_CLOCK_ENABLE (1<<5) -#define MPUTIM_PTV_MASK (0x7<<MPUTIM_PTV_BIT) -#define MPUTIM_PTV_BIT 2 -#define MPUTIM_AR (1<<1) -#define MPUTIM_ST (1<<0) - -/* --------------------------------------------------------------------------- - * OMAP1510 GPIO (SHARED) - * --------------------------------------------------------------------------- - * - */ -#define GPIO_DATA_INPUT_REG (OMAP1510_GPIO_BASE + 0x0) -#define GPIO_DATA_OUTPUT_REG (OMAP1510_GPIO_BASE + 0x4) -#define GPIO_DIR_CONTROL_REG (OMAP1510_GPIO_BASE + 0x8) -#define GPIO_INT_CONTROL_REG (OMAP1510_GPIO_BASE + 0xc) -#define GPIO_INT_MASK_REG (OMAP1510_GPIO_BASE + 0x10) -#define GPIO_INT_STATUS_REG (OMAP1510_GPIO_BASE + 0x14) -#define GPIO_PIN_CONTROL_REG (OMAP1510_GPIO_BASE + 0x18) - - -/* --------------------------- - * OMAP1510 MPUIO (ARM only) - *---------------------------- - */ -#define OMAP1510_MPUIO_BASE 0xFFFB5000 -#define MPUIO_DATA_INPUT_REG (OMAP1510_MPUIO_BASE + 0x0) -#define MPUIO_DATA_OUTPUT_REG (OMAP1510_MPUIO_BASE + 0x4) -#define MPUIO_DIR_CONTROL_REG (OMAP1510_MPUIO_BASE + 0x8) - -/* --------------------------------------------------------------------------- - * OMAP1510 TIPB (only) - * --------------------------------------------------------------------------- - * - */ -#define TIPB_PUBLIC_CNTL_BASE 0xfffed300 -#define MPU_PUBLIC_TIPB_CNTL_REG (TIPB_PUBLIC_CNTL_BASE + 0x8) -#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00 -#define MPU_PRIVATE_TIPB_CNTL_REG (TIPB_PRIVATE_CNTL_BASE + 0x8) - -/* - * --------------------------------------------------------------------------- - * OMAP1510 Camera Interface - * --------------------------------------------------------------------------- - */ -#define CAMERA_BASE (IO_BASE + 0x6800) -#define CAM_CTRLCLOCK_REG (CAMERA_BASE + 0x00) -#define CAM_IT_STATUS_REG (CAMERA_BASE + 0x04) -#define CAM_MODE_REG (CAMERA_BASE + 0x08) -#define CAM_STATUS_REG (CAMERA_BASE + 0x0C) -#define CAM_CAMDATA_REG (CAMERA_BASE + 0x10) -#define CAM_GPIO_REG (CAMERA_BASE + 0x14) -#define CAM_PEAK_CTR_REG (CAMERA_BASE + 0x18) - -#if 0 -#ifndef __ASSEMBLY__ -typedef struct { - __u32 ctrlclock; - __u32 it_status; - __u32 mode; - __u32 status; - __u32 camdata; - __u32 gpio; - __u32 peak_counter; -} camera_regs_t; -#endif -#endif - -/* CTRLCLOCK bit shifts */ -#define FOSCMOD_BIT 0 -#define FOSCMOD_MASK (0x7 << FOSCMOD_BIT) -#define FOSCMOD_12MHz 0x0 -#define FOSCMOD_6MHz 0x2 -#define FOSCMOD_9_6MHz 0x4 -#define FOSCMOD_24MHz 0x5 -#define FOSCMOD_8MHz 0x6 -#define POLCLK (1<<3) -#define CAMEXCLK_EN (1<<4) -#define MCLK_EN (1<<5) -#define DPLL_EN (1<<6) -#define LCLK_EN (1<<7) - -/* IT_STATUS bit shifts */ -#define V_UP (1<<0) -#define V_DOWN (1<<1) -#define H_UP (1<<2) -#define H_DOWN (1<<3) -#define FIFO_FULL (1<<4) -#define DATA_XFER (1<<5) - -/* MODE bit shifts */ -#define CAMOSC (1<<0) -#define IMGSIZE_BIT 1 -#define IMGSIZE_MASK (0x3 << IMGSIZE_BIT) -#define IMGSIZE_CIF (0x0 << IMGSIZE_BIT) /* 352x288 */ -#define IMGSIZE_QCIF (0x1 << IMGSIZE_BIT) /* 176x144 */ -#define IMGSIZE_VGA (0x2 << IMGSIZE_BIT) /* 640x480 */ -#define IMGSIZE_QVGA (0x3 << IMGSIZE_BIT) /* 320x240 */ -#define ORDERCAMD (1<<3) -#define EN_V_UP (1<<4) -#define EN_V_DOWN (1<<5) -#define EN_H_UP (1<<6) -#define EN_H_DOWN (1<<7) -#define EN_DMA (1<<8) -#define THRESHOLD (1<<9) -#define THRESHOLD_BIT 9 -#define THRESHOLD_MASK (0x7f<<9) -#define EN_NIRQ (1<<16) -#define EN_FIFO_FULL (1<<17) -#define RAZ_FIFO (1<<18) - -/* STATUS bit shifts */ -#define VSTATUS (1<<0) -#define HSTATUS (1<<1) - -/* GPIO bit shifts */ -#define CAM_RST (1<<0) - - -/********************* - * Watchdog timer. - *********************/ -#define WDTIM_BASE 0xfffec800 -#define WDTIM_CONTROL (WDTIM_BASE+0x00) -#define WDTIM_LOAD (WDTIM_BASE+0x04) -#define WDTIM_READ (WDTIM_BASE+0x04) -#define WDTIM_MODE (WDTIM_BASE+0x08) - -/* Values to write to mode register to disable the watchdog function. */ -#define DISABLE_SEQ1 0xF5 -#define DISABLE_SEQ2 0xA0 - -/* WDTIM_CONTROL bit definitions. */ -#define WDTIM_CONTROL_ST BIT7 - - -/* --------------------------------------------------------------------------- - * Differentiating processor versions for those who care. - * --------------------------------------------------------------------------- - * - */ -#define OMAP1509 0 -#define OMAP1510 1 - -#define OMAP1510_ID_CODE_REG 0xfffed404 - -#ifndef __ASSEMBLY__ -int cpu_type(void); -#endif - -/*****************************************************************************/ - -#define CLKGEN_RESET_BASE (0xfffece00) -#define ARM_CKCTL (volatile __u16 *)(CLKGEN_RESET_BASE + 0x0) -#define ARM_IDLECT1 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x4) -#define ARM_IDLECT2 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x8) -#define ARM_EWUPCT (volatile __u16 *)(CLKGEN_RESET_BASE + 0xC) -#define ARM_RSTCT1 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x10) -#define ARM_RSTCT2 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x14) -#define ARM_SYSST (volatile __u16 *)(CLKGEN_RESET_BASE + 0x18) - - -#define CK_CLKIN 12 /* MHz */ -#define CK_RATEF 1 -#define CK_IDLEF 2 -#define CK_ENABLEF 4 -#define CK_SELECTF 8 -#ifndef __ASSEMBLER__ -#define CK_DPLL1 ((volatile __u16 *)0xfffecf00) -#else -#define CK_DPLL1 (0xfffecf00) -#endif -#define SETARM_IDLE_SHIFT - -/* ARM_CKCTL bit shifts */ -#define PERDIV 0 -#define LCDDIV 2 -#define ARMDIV 4 -#define DSPDIV 6 -#define TCDIV 8 -#define DSPMMUDIV 10 -#define ARM_TIMXO 12 -#define EN_DSPCK 13 -#define ARM_INTHCK_SEL 14 /* REVISIT -- where is this used? */ - -#define ARM_CKCTL_RSRVD_BIT15 (1 << 15) -#define ARM_CKCTL_ARM_INTHCK_SEL (1 << 14) -#define ARM_CKCTL_EN_DSPCK (1 << 13) -#define ARM_CKCTL_ARM_TIMXO (1 << 12) -#define ARM_CKCTL_DSPMMU_DIV1 (1 << 11) -#define ARM_CKCTL_DSPMMU_DIV2 (1 << 10) -#define ARM_CKCTL_TCDIV1 (1 << 9) -#define ARM_CKCTL_TCDIV2 (1 << 8) -#define ARM_CKCTL_DSPDIV1 (1 << 7) -#define ARM_CKCTL_DSPDIV0 (1 << 6) -#define ARM_CKCTL_ARMDIV1 (1 << 5) -#define ARM_CKCTL_ARMDIV0 (1 << 4) -#define ARM_CKCTL_LCDDIV1 (1 << 3) -#define ARM_CKCTL_LCDDIV0 (1 << 2) -#define ARM_CKCTL_PERDIV1 (1 << 1) -#define ARM_CKCTL_PERDIV0 (1 << 0) - -/* ARM_IDLECT1 bit shifts */ -#define IDLWDT_ARM 0 -#define IDLXORP_ARM 1 -#define IDLPER_ARM 2 -#define IDLLCD_ARM 3 -#define IDLLB_ARM 4 -#define IDLHSAB_ARM 5 -#define IDLIF_ARM 6 -#define IDLDPLL_ARM 7 -#define IDLAPI_ARM 8 -#define IDLTIM_ARM 9 -#define SETARM_IDLE 11 - -/* ARM_IDLECT2 bit shifts */ -#define EN_WDTCK 0 -#define EN_XORPCK 1 -#define EN_PERCK 2 -#define EN_LCDCK 3 -#define EN_LBCK 4 -#define EN_HSABCK 5 -#define EN_APICK 6 -#define EN_TIMCK 7 -#define DMACK_REQ 8 -#define EN_GPIOCK 9 -#define EN_LBFREECK 10 - -#define ARM_RSTCT1_SW_RST (1 << 3) -#define ARM_RSTCT1_DSP_RST (1 << 2) -#define ARM_RSTCT1_DSP_EN (1 << 1) -#define ARM_RSTCT1_ARM_RST (1 << 0) - -/* ARM_RSTCT2 bit shifts */ -#define EN_PER 0 - -#define ARM_SYSST_RSRVD_BIT15 (1 << 15) -#define ARM_SYSST_RSRVD_BIT14 (1 << 14) -#define ARM_SYSST_CLOCK_SELECT2 (1 << 13) -#define ARM_SYSST_CLOCK_SELECT1 (1 << 12) -#define ARM_SYSST_CLOCK_SELECT0 (1 << 11) -#define ARM_SYSST_RSRVD_BIT10 (1 << 10) -#define ARM_SYSST_RSRVD_BIT9 (1 << 9) -#define ARM_SYSST_RSRVD_BIT8 (1 << 8) -#define ARM_SYSST_RSRVD_BIT7 (1 << 7) -#define ARM_SYSST_IDLE_DSP (1 << 6) -#define ARM_SYSST_POR (1 << 5) -#define ARM_SYSST_EXT_RST (1 << 4) -#define ARM_SYSST_ARM_MCRST (1 << 3) -#define ARM_SYSST_ARM_WDRST (1 << 2) -#define ARM_SYSST_GLOB_SWRST (1 << 1) -#define ARM_SYSST_DSP_WDRST (1 << 0) - -/* Table 15-23. DPLL Control Registers: */ -#define DPLL_CTL_REG (volatile __u16 *)(0xfffecf00) - -/* Table 15-24. Control Register (CTL_REG): */ - -#define DPLL_CTL_REG_IOB (1 << 13) -#define DPLL_CTL_REG_PLL_MULT Fld(5,0) - -/*****************************************************************************/ - -/* OMAP INTERRUPT REGISTERS */ -#define IRQ_ITR 0x00 -#define IRQ_MIR 0x04 -#define IRQ_SIR_IRQ 0x10 -#define IRQ_SIR_FIQ 0x14 -#define IRQ_CONTROL_REG 0x18 -#define IRQ_ISR 0x9c -#define IRQ_ILR0 0x1c - -#define REG_IHL1_MIR (OMAP_IH1_BASE+IRQ_MIR) -#define REG_IHL2_MIR (OMAP_IH2_BASE+IRQ_MIR) - -/* INTERRUPT LEVEL REGISTER BITS */ -#define ILR_PRIORITY_MASK (0x3c) -#define ILR_PRIORITY_SHIFT (2) -#define ILR_LEVEL_TRIGGER (1<<1) -#define ILR_FIQ (1<<0) - -#define IRQ_LEVEL_INT 1 -#define IRQ_EDGE_INT 0 - -/* Macros to access registers */ -#define outb(v,p) *(volatile u8 *) (p) = v -#define outw(v,p) *(volatile u16 *) (p) = v -#define outl(v,p) *(volatile u32 *) (p) = v - -#define inb(p) *(volatile u8 *) (p) -#define inw(p) *(volatile u16 *) (p) -#define inl(p) *(volatile u32 *) (p) diff --git a/include/configs/omap5912osk.h b/include/configs/omap5912osk.h deleted file mode 100644 index 376dfdb14c..0000000000 --- a/include/configs/omap5912osk.h +++ /dev/null @@ -1,174 +0,0 @@ -/* - * (C) Copyright 2003 - * Texas Instruments. - * Kshitij Gupta <kshitij@ti.com> - * Configuation settings for the TI OMAP Innovator board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP1610 1 /* 5912 is same as 1610 */ -#define CONFIG_OSK_OMAP5912 1 /* a OSK Board */ - -#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */ -#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */ - -/* input clock of PLL */ -/* the OMAP5912 OSK has 12MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 12000000 - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 /* Required for ramdisk support */ - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * Hardware drivers - */ -/* -*/ -#define CONFIG_LAN91C96 -#define CONFIG_LAN91C96_BASE 0x04800300 -#define CONFIG_LAN91C96_EXT_PHY - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */ -#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart - on helen */ - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP5912 OSK */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DHCP - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH - - -#include <configs/omap1510.h> - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd \ - root=/dev/nfs rw nfsroot=157.87.82.48:\ - /home/mwd/myfs/target ip=dhcp" -#define CONFIG_NETMASK 255.255.254.0 /* talk on MY local net */ -#define CONFIG_IPADDR 156.117.97.156 /* static IP I currently own */ -#define CONFIG_SERVERIP 156.117.97.139 /* current IP of my dev pc */ -#define CONFIG_BOOTFILE "uImage" /* file to load */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "OMAP5912 OSK # " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */ - -/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by - * DPLL1. This time is further subdivided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */ -#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x01000000 /* Flash Bank #2 */ - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ - -#define PHYS_SRAM 0x20000000 - -/*----------------------------------------------------------------------- - * FLASH driver setup - */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ - -#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */ -#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -/* addr of environment */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) - -#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_OFFSET 0x40000 /* environment starts here */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR PHYS_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE (250 * 1024) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h deleted file mode 100644 index 4e3b7277f4..0000000000 --- a/include/configs/stxxtc.h +++ /dev/null @@ -1,485 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com - * U-Boot port on STx XTc 8xx board - * Mostly copied from Panto's NETTA2 board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC875 1 /* This is a MPC875 CPU */ -#define CONFIG_STXXTC 1 /* ...on a STx XTc board */ - -#define CONFIG_SYS_TEXT_BASE 0x40F00000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115.2kbps */ - -#define CONFIG_XIN 10000000 /* 10 MHz input xtal */ - -/* Select one of few clock rates defined later in this file. -*/ -/* #define MPC8XX_HZ 50000000 */ -#define MPC8XX_HZ 66666666 - -#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_SOURCE -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ -#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_NISDOMAIN - - -#undef CONFIG_MAC_PARTITION -#undef CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define FEC_ENET 1 /* eth.c needs it that way... */ -#undef CONFIG_SYS_DISCOVER_PHY -#define CONFIG_MII 1 -#define CONFIG_MII_INIT 1 -#undef CONFIG_RMII - -#define CONFIG_ETHER_ON_FEC1 1 -#define CONFIG_FEC1_PHY 1 /* phy address of FEC */ -#undef CONFIG_FEC1_PHY_NORXERR - -#define CONFIG_ETHER_ON_FEC2 1 -#define CONFIG_FEC2_PHY 3 -#undef CONFIG_FEC2_PHY_NORXERR - -#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_MII -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PING - - -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_MISC_INIT_R - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "xtc> " /* Monitor Command Prompt */ - -#define CONFIG_SYS_HUSH_PARSER 1 - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#if defined(DEBUG) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif - -/* yes this is weird, I know :) */ -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE | 0x00F00000) -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -#define CONFIG_SYS_RESET_ADDRESS 0x80000000 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE 0x10000 - -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000) -#define CONFIG_ENV_OFFSET 0 -#define CONFIG_ENV_SIZE 0x4000 - -#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x00010000) -#define CONFIG_ENV_OFFSET_REDUND 0 -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ - -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x2000000 } - -#define CONFIG_SYS_FLASH_PROTECTION - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC | SIUMCR_GB5E) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - */ - -#if CONFIG_XIN == 10000000 - -#if MPC8XX_HZ == 50000000 -#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (1 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 66666666 -#define CONFIG_SYS_PLPRCR ((1 << PLPRCR_MFN_SHIFT) | (2 << PLPRCR_MFD_SHIFT) | \ - (1 << PLPRCR_S_SHIFT) | (13 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#else -#error unsupported CPU freq for XIN = 10MHz -#endif -#else -#error unsupported freq for XIN (must be 10MHz) -#endif - - -/* - *----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - * - * Note: When TBS == 0 the timebase is independent of current cpu clock. - */ - -#define SCCR_MASK SCCR_EBDF11 -#if MPC8XX_HZ > 66666666 -#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00 | SCCR_EBDF01) -#else -#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) -#endif - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/*#define CONFIG_SYS_DER 0x2002000F*/ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x42000000 /* FLASH bank #1 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ - -#define FLASH_BANK_MAX_SIZE 0x01000000 /* max size per chip */ - -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 -#define CONFIG_SYS_PRELIM_OR_AM (0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) - -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) - -#define CONFIG_SYS_OR1_PRELIM ((0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) - -/* - * BR4 and OR4 (SDRAM) - * - */ -#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) - -#define CONFIG_SYS_OR4_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM) -#define CONFIG_SYS_BR4_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V) - -/* - * Memory Periodic Timer Prescaler - */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_MAMR_PTA 234 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */ - -/****************************************************************/ - -#define NAND_SIZE 0x00010000 /* 64K */ -#define NAND_BASE 0xF1000000 - -/*****************************************************************************/ - -#define CONFIG_SYS_DIRECT_FLASH_TFTP - -/*****************************************************************************/ - -/* Status Leds are on the MODCK pins, which become the PCMCIA PGCRB, - * CxOE and CxRESET. We use the CxOE. - */ -#define STATUS_LED_BIT 0x00000080 /* bit 24 */ - -#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) -#define STATUS_LED_STATE STATUS_LED_BLINKING - -#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ -#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ - -#ifndef __ASSEMBLY__ - -/* LEDs */ - -/* led_id_t is unsigned int mask */ -typedef unsigned int led_id_t; - -#define __led_toggle(_msk) \ - do { \ - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb ^= (_msk); \ - } while(0) - -#define __led_set(_msk, _st) \ - do { \ - if ((_st)) \ - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb |= (_msk); \ - else \ - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb &= ~(_msk); \ - } while(0) - -#define __led_init(msk, st) __led_set(msk, st) - -#endif - -/******************************************************************************/ - -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 -#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1 -#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1 - -/******************************************************************************/ - -/* use board specific hardware */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_HW_WATCHDOG - -/*****************************************************************************/ - -#define CONFIG_AUTO_COMPLETE 1 -#define CONFIG_CRC32_VERIFY 1 -#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1 - -/*****************************************************************************/ - -/* pass open firmware flattened device tree */ -#define CONFIG_OF_LIBFDT 1 - -#define OF_TBCLK (MPC8XX_HZ / 16) - -#endif /* __CONFIG_H */ diff --git a/include/configs/svm_sc8xx.h b/include/configs/svm_sc8xx.h deleted file mode 100644 index b4aa948565..0000000000 --- a/include/configs/svm_sc8xx.h +++ /dev/null @@ -1,450 +0,0 @@ -/* - * (C) Copyright 2000, 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific, - * for SinoVee Microsystems SC8xx series SBC - * http://www.fel.com.cn (Chinese) - * http://www.sinovee.com (English) - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -/* Custom configuration */ -/* SC823,SC850,SC860SAR, FEL8xx-AT(823/850/860) */ -/* SC85T,SC860T, FEL8xx-AT(855T/860T) */ -/*#define CONFIG_FEL8xx_AT */ -/*#define CONFIG_LCD */ -/*#define CONFIG_MPC8XX_LCD*/ -/* if core > 50MHz , un-comment CONFIG_BUS_DIV2 */ -/* #define CONFIG_50MHz */ -/* #define CONFIG_66MHz */ -/* #define CONFIG_75MHz */ -#define CONFIG_80MHz -/*#define CONFIG_100MHz */ -/* #define CONFIG_BUS_DIV2 1 */ -/* for BOOT device port size */ -/* #define CONFIG_BOOT_8B */ -#define CONFIG_BOOT_16B -/* #define CONFIG_BOOT_32B */ -/* #define CONFIG_CAN_DRIVER */ -/* #define DEBUG */ -#define CONFIG_FEC_ENET - -/* #define CONFIG_SDRAM_16M */ -#define CONFIG_SDRAM_32M -/* #define CONFIG_SDRAM_64M */ -#define CONFIG_SYS_RESET_ADDRESS 0xffffffff -/* - * High Level Configuration Options - * (easy to change) - */ - -/* #define CONFIG_MPC823 1 */ -/* #define CONFIG_MPC850 1 */ -#define CONFIG_MPC855 1 -/* #define CONFIG_MPC860 1 */ -/* #define CONFIG_MPC860T 1 */ - -#undef CONFIG_WATCHDOG /* watchdog */ - -#define CONFIG_SVM_SC8xx 1 /* ...on SVM SC8xx series */ - -#ifdef CONFIG_LCD /* with LCD controller ? */ -/* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */ -#endif - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 19200 /* console baudrate = 115kbps */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;echo Welcome to U-Boot SVM port;echo;echo Type \"? or help\" to get on-line help;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 0x210000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/sinovee/ppc8xx-linux-2.0/target\0" \ - "bootfile=pImage-sc855t\0" \ - "kernel_addr=48000000\0" \ - "ramdisk_addr=48100000\0" \ - "" -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "tftpboot 0x210000 pImage-sc855t;bootm 0x210000" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - - -#ifdef CONFIG_LCD -# undef CONFIG_STATUS_LED /* disturbs display */ -#else -# define CONFIG_STATUS_LED 1 /* Status LED enabled */ -#endif /* CONFIG_LCD */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DATE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#ifdef CONFIG_SYS_HUSH_PARSER -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 - -#ifdef CONFIG_BOOT_8B -#define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ -#elif defined (CONFIG_BOOT_16B) -#define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ -#elif defined (CONFIG_BOOT_32B) -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ -#endif - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x46454C38 /* 'SVM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -/*#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -*/ -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR 0xffffff88 -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -/*#define CONFIG_SYS_SIUMCR 0x00610c00 */ -#define CONFIG_SYS_SIUMCR 0x00000000 -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR 0x0001 - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC 0x00c3 - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR 0x0000 - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#if defined (CONFIG_100MHz) -#define CONFIG_SYS_PLPRCR 0x06301000 -#define CONFIG_8xx_GCLK_FREQ 100000000 -#elif defined (CONFIG_80MHz) -#define CONFIG_SYS_PLPRCR 0x04f01000 -#define CONFIG_8xx_GCLK_FREQ 80000000 -#elif defined(CONFIG_75MHz) -#define CONFIG_SYS_PLPRCR 0x04a00100 -#define CONFIG_8xx_GCLK_FREQ 75000000 -#elif defined(CONFIG_66MHz) -#define CONFIG_SYS_PLPRCR 0x04101000 -#define CONFIG_8xx_GCLK_FREQ 66000000 -#elif defined(CONFIG_50MHz) -#define CONFIG_SYS_PLPRCR 0x03101000 -#define CONFIG_8xx_GCLK_FREQ 50000000 -#endif - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#ifdef CONFIG_BUS_DIV2 -#define CONFIG_SYS_SCCR 0x02020000 | SCCR_RTSEL -#else /* up to 50 MHz we use a 1:1 clock */ -#define CONFIG_SYS_SCCR 0x02000000 | SCCR_RTSEL -#endif - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */ -#define CONFIG_IDE_8xx_DIRECT 1 /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_BASE_ADDR 0xFE100010 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -/*#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0C00 */ -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O - */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0200 /* Offset for normal register accesses - */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0210 /* Offset for alternate registers - */ -#define CONFIG_ATAPI -#define CONFIG_SYS_PIO_MODE 0 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/*#define CONFIG_SYS_DER 0x2002000F*/ -#define CONFIG_SYS_DER 0x0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#if defined(CONFIG_100MHz) -#define CONFIG_SYS_OR_TIMING_FLASH 0x000002f4 -#define CONFIG_SYS_OR_TIMING_DOC 0x000002f4 -#define CONFIG_SYS_MxMR_PTx 0x61000000 -#define CONFIG_SYS_MPTPR 0x400 - -#elif defined(CONFIG_80MHz) -#define CONFIG_SYS_OR_TIMING_FLASH 0x00000ff4 -#define CONFIG_SYS_OR_TIMING_DOC 0x000001f4 -#define CONFIG_SYS_MxMR_PTx 0x4e000000 -#define CONFIG_SYS_MPTPR 0x400 - -#elif defined(CONFIG_75MHz) -#define CONFIG_SYS_OR_TIMING_FLASH 0x000008f4 -#define CONFIG_SYS_OR_TIMING_DOC 0x000002f4 -#define CONFIG_SYS_MxMR_PTx 0x49000000 -#define CONFIG_SYS_MPTPR 0x400 - -#elif defined(CONFIG_66MHz) -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) -/*#define CONFIG_SYS_OR_TIMING_FLASH 0x000001f4 */ -#define CONFIG_SYS_OR_TIMING_DOC 0x000003f4 -#define CONFIG_SYS_MxMR_PTx 0x40000000 -#define CONFIG_SYS_MPTPR 0x400 - -#else /* 50 MHz */ -#define CONFIG_SYS_OR_TIMING_FLASH 0x00000ff4 -#define CONFIG_SYS_OR_TIMING_DOC 0x000001f4 -#define CONFIG_SYS_MxMR_PTx 0x30000000 -#define CONFIG_SYS_MPTPR 0x400 -#endif /*CONFIG_??MHz */ - - -#if defined (CONFIG_BOOT_8B) /* 512K X 8 ,29F040 , 2MB space */ -#define CONFIG_SYS_OR0_PRELIM (0xffe00000 | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8) -#elif defined (CONFIG_BOOT_16B) /* 29lv160 X 16 , 4MB space */ -#define CONFIG_SYS_OR0_PRELIM (0xffc00000 | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16) -#elif defined( CONFIG_BOOT_32B ) /* 29lv160 X 2 X 32, 4/8/16MB , 64MB space */ -#define CONFIG_SYS_OR0_PRELIM (0xfc000000 | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) -#else -#error Boot device port size missing. -#endif - -/* - * Disk-On-Chip configuration - */ - -#define CONFIG_SYS_DOC_SHORT_TIMEOUT -#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ - -#define CONFIG_SYS_DOC_SUPPORT_2000 -#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM -#define CONFIG_SYS_DOC_BASE 0x80000000 - -#endif /* __CONFIG_H */ diff --git a/include/image.h b/include/image.h index ca2fe862ce..69f86ad49e 100644 --- a/include/image.h +++ b/include/image.h @@ -424,6 +424,9 @@ enum fit_load_op { #define IMAGE_FORMAT_FIT 0x02 /* new, libfdt based format */ #define IMAGE_FORMAT_ANDROID 0x03 /* Android boot image */ +ulong genimg_get_kernel_addr_fit(char * const img_addr, + const char **fit_uname_config, + const char **fit_uname_kernel); ulong genimg_get_kernel_addr(char * const img_addr); int genimg_get_format(const void *img_addr); int genimg_has_config(bootm_headers_t *images); diff --git a/include/netdev.h b/include/netdev.h index e45dd7abec..260c8d01b6 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -69,7 +69,6 @@ int ne2k_register(void); int npe_initialize(bd_t *bis); int ns8382x_initialize(bd_t *bis); int pcnet_initialize(bd_t *bis); -int plb2800_eth_initialize(bd_t *bis); int ppc_4xx_eth_initialize (bd_t *bis); int rtl8139_initialize(bd_t *bis); int rtl8169_initialize(bd_t *bis); diff --git a/include/nios2-epcs.h b/include/nios2-epcs.h deleted file mode 100644 index 8c8f2385ee..0000000000 --- a/include/nios2-epcs.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt@psyent.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************* - * Altera Nios-II EPCS Controller Core interfaces - ************************************************************************/ - -#ifndef __NIOS2_EPCS_H__ -#define __NIOS2_EPCS_H__ - -typedef struct epcs_devinfo_t { - const char *name; /* Device name */ - unsigned char id; /* Device silicon id */ - unsigned char size; /* Total size log2(bytes)*/ - unsigned char num_sects; /* Number of sectors */ - unsigned char sz_sect; /* Sector size log2(bytes) */ - unsigned char sz_page; /* Page size log2(bytes) */ - unsigned char prot_mask; /* Protection mask */ -}epcs_devinfo_t; - -/* Resets the epcs controller -- to prevent (potential) soft-reset - * problems when booting from the epcs controller - */ -extern int epcs_reset (void); - -/* Returns the devinfo struct if EPCS device is found; - * NULL otherwise. - */ -extern epcs_devinfo_t *epcs_dev_find (void); - -/* Returns the number of bytes used by config data. - * Negative on error. - */ -extern int epcs_cfgsz (void); - -/* Erase sectors 'start' to 'end' - return zero on success - */ -extern int epcs_erase (unsigned start, unsigned end); - -/* Read 'cnt' bytes from device offset 'off' into buf at 'addr' - * Zero return on success - */ -extern int epcs_read (ulong addr, ulong off, ulong cnt); - -/* Write 'cnt' bytes to device offset 'off' from buf at 'addr'. - * Zero return on success - */ -extern int epcs_write (ulong addr, ulong off, ulong cnt); - -/* Verify 'cnt' bytes at device offset 'off' comparing with buf - * at 'addr'. On failure, write first invalid offset to *err. - * Zero return on success - */ -extern int epcs_verify (ulong addr, ulong off, ulong cnt, ulong *err); - -#endif /* __NIOS2_EPCS_H__ */ diff --git a/include/pci_ids.h b/include/pci_ids.h index 6bab677449..f220c3aa5c 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -2546,6 +2546,13 @@ #define PCI_DEVICE_ID_INTEL_82441 0x1237 #define PCI_DEVICE_ID_INTEL_82380FB 0x124b #define PCI_DEVICE_ID_INTEL_82439 0x1250 +#define PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED 0x1531 +#define PCI_DEVICE_ID_INTEL_I210_COPPER 0x1533 +#define PCI_DEVICE_ID_INTEL_I210_SERDES 0x1536 +#define PCI_DEVICE_ID_INTEL_I210_1000BASEKX 0x1537 +#define PCI_DEVICE_ID_INTEL_I210_EXTPHY 0x1538 +#define PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS 0x157b +#define PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS 0x157c #define PCI_DEVICE_ID_INTEL_80960_RP 0x1960 #define PCI_DEVICE_ID_INTEL_82840_HB 0x1a21 #define PCI_DEVICE_ID_INTEL_82845_HB 0x1a30 diff --git a/include/pcmcia.h b/include/pcmcia.h index 8aec2541b8..4b667f49ce 100644 --- a/include/pcmcia.h +++ b/include/pcmcia.h @@ -21,7 +21,7 @@ #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) -#if defined(CONFIG_TQM8xxL) || defined(CONFIG_SVM_SC8xx) +#if defined(CONFIG_TQM8xxL) # define CONFIG_PCMCIA_SLOT_B /* The TQM8xxL use SLOT_B */ #elif defined(CONFIG_SPD823TS) /* The SPD8xx use SLOT_B */ # define CONFIG_PCMCIA_SLOT_B diff --git a/include/sparse_format.h b/include/sparse_format.h new file mode 100644 index 0000000000..af67581cde --- /dev/null +++ b/include/sparse_format.h @@ -0,0 +1,49 @@ +/* + * This is from the Android Project, + * Repository: https://android.googlesource.com/platform/system/core + * File: libsparse/sparse_format.h + * Commit: 28fa5bc347390480fe190294c6c385b6a9f0d68b + * Copyright (C) 2010 The Android Open Source Project + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _LIBSPARSE_SPARSE_FORMAT_H_ +#define _LIBSPARSE_SPARSE_FORMAT_H_ +#include "sparse_defs.h" + +typedef struct sparse_header { + __le32 magic; /* 0xed26ff3a */ + __le16 major_version; /* (0x1) - reject images with higher major versions */ + __le16 minor_version; /* (0x0) - allow images with higer minor versions */ + __le16 file_hdr_sz; /* 28 bytes for first revision of the file format */ + __le16 chunk_hdr_sz; /* 12 bytes for first revision of the file format */ + __le32 blk_sz; /* block size in bytes, must be a multiple of 4 (4096) */ + __le32 total_blks; /* total blocks in the non-sparse output image */ + __le32 total_chunks; /* total chunks in the sparse input image */ + __le32 image_checksum; /* CRC32 checksum of the original data, counting "don't care" */ + /* as 0. Standard 802.3 polynomial, use a Public Domain */ + /* table implementation */ +} sparse_header_t; + +#define SPARSE_HEADER_MAGIC 0xed26ff3a + +#define CHUNK_TYPE_RAW 0xCAC1 +#define CHUNK_TYPE_FILL 0xCAC2 +#define CHUNK_TYPE_DONT_CARE 0xCAC3 +#define CHUNK_TYPE_CRC32 0xCAC4 + +typedef struct chunk_header { + __le16 chunk_type; /* 0xCAC1 -> raw; 0xCAC2 -> fill; 0xCAC3 -> don't care */ + __le16 reserved1; + __le32 chunk_sz; /* in blocks in output image */ + __le32 total_sz; /* in bytes of chunk input file including chunk header and data */ +} chunk_header_t; + +/* Following a Raw or Fill or CRC32 chunk is data. + * For a Raw chunk, it's the data in chunk_sz * blk_sz. + * For a Fill chunk, it's 4 bytes of the fill data. + * For a CRC32 chunk, it's 4 bytes of CRC32 + */ + +#endif diff --git a/include/status_led.h b/include/status_led.h index b8aaaf78fc..c1d2242b9d 100644 --- a/include/status_led.h +++ b/include/status_led.h @@ -56,30 +56,6 @@ void status_led_set (int led, int state); # define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ -/***** GEN860T *********************************************************/ -#elif defined(CONFIG_GEN860T) - -# define STATUS_LED_PAR im_ioport.iop_papar -# define STATUS_LED_DIR im_ioport.iop_padir -# define STATUS_LED_ODR im_ioport.iop_paodr -# define STATUS_LED_DAT im_ioport.iop_padat - -# define STATUS_LED_BIT 0x0800 /* Red LED 0 is on PA.4 */ -# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4) -# define STATUS_LED_STATE STATUS_LED_OFF -# define STATUS_LED_BIT1 0x0400 /* Grn LED 1 is on PA.5 */ -# define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 8) -# define STATUS_LED_STATE1 STATUS_LED_BLINKING -# define STATUS_LED_BIT2 0x0080 /* Red LED 2 is on PA.8 */ -# define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 4) -# define STATUS_LED_STATE2 STATUS_LED_OFF -# define STATUS_LED_BIT3 0x0040 /* Grn LED 3 is on PA.9 */ -# define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 4) -# define STATUS_LED_STATE3 STATUS_LED_OFF - -# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ -# define STATUS_LED_BOOT 1 /* Boot status on LED 1 */ - /***** IVMS8 **********************************************************/ #elif defined(CONFIG_IVMS8) @@ -217,24 +193,6 @@ void status_led_set (int led, int state); # define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ -#elif defined(CONFIG_SVM_SC8xx) -# define STATUS_LED_PAR im_cpm.cp_pbpar -# define STATUS_LED_DIR im_cpm.cp_pbdir -# define STATUS_LED_ODR im_cpm.cp_pbodr -# define STATUS_LED_DAT im_cpm.cp_pbdat - -# define STATUS_LED_BIT 0x00000001 -# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) -# define STATUS_LED_STATE STATUS_LED_BLINKING - -# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ - -# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ - -/***** STx XTc ********************************************************/ -#elif defined(CONFIG_STXXTC) -/* XXX empty just to avoid the error */ -/************************************************************************/ #elif defined(CONFIG_V38B) # define STATUS_LED_BIT 0x0010 /* Timer7 GPIO */ diff --git a/net/bootp.c b/net/bootp.c index a4f6db570c..d4c86cf179 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -47,7 +47,12 @@ #define CONFIG_DHCP_MIN_EXT_LEN 64 #endif -ulong BootpID; +#ifndef CONFIG_BOOTP_ID_CACHE_SIZE +#define CONFIG_BOOTP_ID_CACHE_SIZE 4 +#endif + +ulong bootp_ids[CONFIG_BOOTP_ID_CACHE_SIZE]; +unsigned int bootp_num_ids; int BootpTry; ulong bootp_start; ulong bootp_timeout; @@ -77,6 +82,30 @@ static char *dhcpmsg2str(int type) #endif #endif +static void bootp_add_id(ulong id) +{ + if (bootp_num_ids >= ARRAY_SIZE(bootp_ids)) { + size_t size = sizeof(bootp_ids) - sizeof(id); + + memmove(bootp_ids, &bootp_ids[1], size); + bootp_ids[bootp_num_ids - 1] = id; + } else { + bootp_ids[bootp_num_ids] = id; + bootp_num_ids++; + } +} + +static bool bootp_match_id(ulong id) +{ + unsigned int i; + + for (i = 0; i < bootp_num_ids; i++) + if (bootp_ids[i] == id) + return true; + + return false; +} + static int BootpCheckPkt(uchar *pkt, unsigned dest, unsigned src, unsigned len) { struct Bootp_t *bp = (struct Bootp_t *) pkt; @@ -96,7 +125,7 @@ static int BootpCheckPkt(uchar *pkt, unsigned dest, unsigned src, unsigned len) retval = -4; else if (bp->bp_hlen != HWL_ETHER) retval = -5; - else if (NetReadLong((ulong *)&bp->bp_id) != BootpID) + else if (!bootp_match_id(NetReadLong((ulong *)&bp->bp_id))) retval = -6; debug("Filtering pkt = %d\n", retval); @@ -351,8 +380,8 @@ BootpTimeout(void) #endif } else { bootp_timeout *= 2; - if (bootp_timeout > 1000) - bootp_timeout = 1000; + if (bootp_timeout > 2000) + bootp_timeout = 2000; NetSetTimeout(bootp_timeout, BootpTimeout); BootpRequest(); } @@ -616,9 +645,10 @@ static int BootpExtended(u8 *e) void BootpReset(void) { + bootp_num_ids = 0; BootpTry = 0; bootp_start = get_timer(0); - bootp_timeout = 10; + bootp_timeout = 250; } void @@ -631,6 +661,7 @@ BootpRequest(void) #ifdef CONFIG_BOOTP_RANDOM_DELAY ulong rand_ms; #endif + ulong BootpID; bootstage_mark_name(BOOTSTAGE_ID_BOOTP_START, "bootp_start"); #if defined(CONFIG_CMD_DHCP) @@ -699,7 +730,8 @@ BootpRequest(void) | ((ulong)NetOurEther[4] << 8) | (ulong)NetOurEther[5]; BootpID += get_timer(0); - BootpID = htonl(BootpID); + BootpID = htonl(BootpID); + bootp_add_id(BootpID); NetCopyLong(&bp->bp_id, &BootpID); /* @@ -960,8 +992,8 @@ DhcpHandler(uchar *pkt, unsigned dest, IPaddr_t sip, unsigned src, /* Store net params from reply */ BootpCopyNetParams(bp); dhcp_state = BOUND; - printf("DHCP client bound to address %pI4\n", - &NetOurIP); + printf("DHCP client bound to address %pI4 (%lu ms)\n", + &NetOurIP, get_timer(bootp_start)); bootstage_mark_name(BOOTSTAGE_ID_BOOTP_STOP, "bootp_stop"); diff --git a/scripts/Lindent b/scripts/Lindent new file mode 100755 index 0000000000..9c4b3e2b70 --- /dev/null +++ b/scripts/Lindent @@ -0,0 +1,18 @@ +#!/bin/sh +PARAM="-npro -kr -i8 -ts8 -sob -l80 -ss -ncs -cp1" +RES=`indent --version` +V1=`echo $RES | cut -d' ' -f3 | cut -d'.' -f1` +V2=`echo $RES | cut -d' ' -f3 | cut -d'.' -f2` +V3=`echo $RES | cut -d' ' -f3 | cut -d'.' -f3` +if [ $V1 -gt 2 ]; then + PARAM="$PARAM -il0" +elif [ $V1 -eq 2 ]; then + if [ $V2 -gt 2 ]; then + PARAM="$PARAM -il0"; + elif [ $V2 -eq 2 ]; then + if [ $V3 -ge 10 ]; then + PARAM="$PARAM -il0" + fi + fi +fi +indent $PARAM "$@" diff --git a/scripts/Makefile.build b/scripts/Makefile.build index baeaabe310..6742ddd0b8 100644 --- a/scripts/Makefile.build +++ b/scripts/Makefile.build @@ -66,67 +66,6 @@ ifeq ($(KBUILD_NOPEDANTIC),) endif endif -# -# make W=... settings -# -# W=1 - warnings that may be relevant and does not occur too often -# W=2 - warnings that occur quite often but may still be relevant -# W=3 - the more obscure warnings, can most likely be ignored -# -# $(call cc-option, -W...) handles gcc -W.. options which -# are not supported by all versions of the compiler -ifdef KBUILD_ENABLE_EXTRA_GCC_CHECKS -warning- := $(empty) - -warning-1 := -Wextra -Wunused -Wno-unused-parameter -warning-1 += -Wmissing-declarations -warning-1 += -Wmissing-format-attribute -warning-1 += $(call cc-option, -Wmissing-prototypes) -warning-1 += -Wold-style-definition -warning-1 += $(call cc-option, -Wmissing-include-dirs) -warning-1 += $(call cc-option, -Wunused-but-set-variable) -warning-1 += $(call cc-disable-warning, missing-field-initializers) - -# Clang -warning-1 += $(call cc-disable-warning, initializer-overrides) -warning-1 += $(call cc-disable-warning, unused-value) -warning-1 += $(call cc-disable-warning, format) -warning-1 += $(call cc-disable-warning, unknown-warning-option) -warning-1 += $(call cc-disable-warning, sign-compare) -warning-1 += $(call cc-disable-warning, format-zero-length) -warning-1 += $(call cc-disable-warning, uninitialized) -warning-1 += $(call cc-option, -fcatch-undefined-behavior) - -warning-2 := -Waggregate-return -warning-2 += -Wcast-align -warning-2 += -Wdisabled-optimization -warning-2 += -Wnested-externs -warning-2 += -Wshadow -warning-2 += $(call cc-option, -Wlogical-op) -warning-2 += $(call cc-option, -Wmissing-field-initializers) - -warning-3 := -Wbad-function-cast -warning-3 += -Wcast-qual -warning-3 += -Wconversion -warning-3 += -Wpacked -warning-3 += -Wpadded -warning-3 += -Wpointer-arith -warning-3 += -Wredundant-decls -warning-3 += -Wswitch-default -warning-3 += $(call cc-option, -Wpacked-bitfield-compat) -warning-3 += $(call cc-option, -Wvla) - -warning := $(warning-$(findstring 1, $(KBUILD_ENABLE_EXTRA_GCC_CHECKS))) -warning += $(warning-$(findstring 2, $(KBUILD_ENABLE_EXTRA_GCC_CHECKS))) -warning += $(warning-$(findstring 3, $(KBUILD_ENABLE_EXTRA_GCC_CHECKS))) - -ifeq ("$(strip $(warning))","") - $(error W=$(KBUILD_ENABLE_EXTRA_GCC_CHECKS) is unknown) -endif - -KBUILD_CFLAGS += $(warning) -endif - include scripts/Makefile.lib ifdef host-progs diff --git a/scripts/Makefile.extrawarn b/scripts/Makefile.extrawarn new file mode 100644 index 0000000000..65643506c7 --- /dev/null +++ b/scripts/Makefile.extrawarn @@ -0,0 +1,67 @@ +# ========================================================================== +# +# make W=... settings +# +# W=1 - warnings that may be relevant and does not occur too often +# W=2 - warnings that occur quite often but may still be relevant +# W=3 - the more obscure warnings, can most likely be ignored +# +# $(call cc-option, -W...) handles gcc -W.. options which +# are not supported by all versions of the compiler +# ========================================================================== + +ifeq ("$(origin W)", "command line") + export KBUILD_ENABLE_EXTRA_GCC_CHECKS := $(W) +endif + +ifdef KBUILD_ENABLE_EXTRA_GCC_CHECKS +warning- := $(empty) + +warning-1 := -Wextra -Wunused -Wno-unused-parameter +warning-1 += -Wmissing-declarations +warning-1 += -Wmissing-format-attribute +warning-1 += $(call cc-option, -Wmissing-prototypes) +warning-1 += -Wold-style-definition +warning-1 += $(call cc-option, -Wmissing-include-dirs) +warning-1 += $(call cc-option, -Wunused-but-set-variable) +warning-1 += $(call cc-disable-warning, missing-field-initializers) + +# Clang +warning-1 += $(call cc-disable-warning, initializer-overrides) +warning-1 += $(call cc-disable-warning, unused-value) +warning-1 += $(call cc-disable-warning, format) +warning-1 += $(call cc-disable-warning, unknown-warning-option) +warning-1 += $(call cc-disable-warning, sign-compare) +warning-1 += $(call cc-disable-warning, format-zero-length) +warning-1 += $(call cc-disable-warning, uninitialized) +warning-1 += $(call cc-option, -fcatch-undefined-behavior) + +warning-2 := -Waggregate-return +warning-2 += -Wcast-align +warning-2 += -Wdisabled-optimization +warning-2 += -Wnested-externs +warning-2 += -Wshadow +warning-2 += $(call cc-option, -Wlogical-op) +warning-2 += $(call cc-option, -Wmissing-field-initializers) + +warning-3 := -Wbad-function-cast +warning-3 += -Wcast-qual +warning-3 += -Wconversion +warning-3 += -Wpacked +warning-3 += -Wpadded +warning-3 += -Wpointer-arith +warning-3 += -Wredundant-decls +warning-3 += -Wswitch-default +warning-3 += $(call cc-option, -Wpacked-bitfield-compat) +warning-3 += $(call cc-option, -Wvla) + +warning := $(warning-$(findstring 1, $(KBUILD_ENABLE_EXTRA_GCC_CHECKS))) +warning += $(warning-$(findstring 2, $(KBUILD_ENABLE_EXTRA_GCC_CHECKS))) +warning += $(warning-$(findstring 3, $(KBUILD_ENABLE_EXTRA_GCC_CHECKS))) + +ifeq ("$(strip $(warning))","") + $(error W=$(KBUILD_ENABLE_EXTRA_GCC_CHECKS) is unknown) +endif + +KBUILD_CFLAGS += $(warning) +endif diff --git a/scripts/mailmapper b/scripts/mailmapper index dd1ddf6a71..922ada6f5f 100755 --- a/scripts/mailmapper +++ b/scripts/mailmapper @@ -59,8 +59,7 @@ MIN_COMMITS = 50 try: toplevel = subprocess.check_output(['git', 'rev-parse', '--show-toplevel']) except subprocess.CalledProcessError: - print >> sys.stderr, 'Please run in a git repository.' - sys.exit(1) + sys.exit('Please run in a git repository.') # strip '\n' toplevel = toplevel.rstrip() diff --git a/scripts/mkmakefile b/scripts/mkmakefile index 0cc0442607..84af27bf0f 100644 --- a/scripts/mkmakefile +++ b/scripts/mkmakefile @@ -42,18 +42,11 @@ MAKEARGS += O=\$(if \$(patsubst /%,,\$(makedir)),\$(CURDIR)/)\$(patsubst %/,%,\$ MAKEFLAGS += --no-print-directory -.PHONY: all \$(MAKECMDGOALS) +.PHONY: __sub-make \$(MAKECMDGOALS) -all := \$(filter-out all Makefile,\$(MAKECMDGOALS)) +__sub-make: + \$(Q)\$(MAKE) \$(MAKEARGS) \$(MAKECMDGOALS) -all: - \$(Q)\$(MAKE) \$(MAKEARGS) \$(all) - -Makefile:; - -\$(all): all - @: - -%/: all +\$(filter-out __sub-make, \$(MAKECMDGOALS)): __sub-make @: EOF diff --git a/scripts/multiconfig.py b/scripts/multiconfig.py deleted file mode 100755 index 749abcb7a5..0000000000 --- a/scripts/multiconfig.py +++ /dev/null @@ -1,410 +0,0 @@ -#!/usr/bin/env python -# -# Copyright (C) 2014, Masahiro Yamada <yamada.m@jp.panasonic.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -""" -A wrapper script to adjust Kconfig for U-Boot - -The biggest difference between Linux Kernel and U-Boot in terms of the -board configuration is that U-Boot has to configure multiple boot images -per board: Normal, SPL, TPL. -We need to expand the functions of Kconfig to handle multiple boot -images. - -Instead of touching various parts under the scripts/kconfig/ directory, -pushing necessary adjustments into this single script would be better -for code maintainance. All the make targets related to the configuration -(make %config) should be invoked via this script. - -Let's see what is different from the original Kconfig. - -- config, menuconfig, etc. - -The commands 'make config', 'make menuconfig', etc. are used to create -or modify the .config file, which stores configs for Normal boot image. - -The location of the one for SPL, TPL image is spl/.config, tpl/.config, -respectively. Use 'make spl/config', 'make spl/menuconfig', etc. -to create or modify the spl/.config file, which contains configs -for SPL image. -Do likewise for the tpl/.config file. -The generic syntax for SPL, TPL configuration is -'make <target_image>/<config_command>'. - -- silentoldconfig - -The command 'make silentoldconfig' updates .config, if necessary, and -additionally updates include/generated/autoconf.h and files under -include/configs/ directory. In U-Boot, it should do the same things for -SPL, TPL images for boards supporting them. -Depending on whether CONFIG_SPL, CONFIG_TPL is defined or not, -'make silentoldconfig' iterates three times at most changing the target -directory. - -To sum up, 'make silentoldconfig' possibly updates - - .config, include/generated/autoconf.h, include/config/* - - spl/.config, spl/include/generated/autoconf.h, spl/include/config/* - (in case CONFIG_SPL=y) - - tpl/.config, tpl/include/generated/autoconf.h, tpl/include/config/* - (in case CONFIG_TPL=y) - -- defconfig, <board>_defconfig - -The command 'make <board>_defconfig' creates a new .config based on the -file configs/<board>_defconfig. The command 'make defconfig' is the same -but the difference is it uses the file specified with KBUILD_DEFCONFIG -environment. - -We need to create .config, spl/.config, tpl/.config for boards where SPL -and TPL images are supported. One possible solution for that is to have -multiple defconfig files per board, but it would produce duplication -among the defconfigs. -The approach chosen here is to expand the feature and support -conditional definition in defconfig, that is, each line in defconfig -files has the form of: -<condition>:<macro definition> - -The '<condition>:' prefix specifies which image the line is valid for. -The '<condition>:' is one of: - None - the line is valid only for Normal image - S: - the line is valid only for SPL image - T: - the line is valid only for TPL image - ST: - the line is valid for SPL and TPL images - +S: - the line is valid for Normal and SPL images - +T: - the line is valid for Normal and TPL images - +ST: - the line is valid for Normal, SPL and SPL images - -So, if neither CONFIG_SPL nor CONFIG_TPL is defined, the defconfig file -has no '<condition>:' part and therefore has the same form of that of -Linux Kernel. - -In U-Boot, for example, a defconfig file can be written like this: - - CONFIG_FOO=100 - S:CONFIG_FOO=200 - T:CONFIG_FOO=300 - ST:CONFIG_BAR=y - +S:CONFIG_BAZ=y - +T:CONFIG_QUX=y - +ST:CONFIG_QUUX=y - -The defconfig above is parsed by this script and internally divided into -three temporary defconfig files. - - - Temporary defconfig for Normal image - CONFIG_FOO=100 - CONFIG_BAZ=y - CONFIG_QUX=y - CONFIG_QUUX=y - - - Temporary defconfig for SPL image - CONFIG_FOO=200 - CONFIG_BAR=y - CONFIG_BAZ=y - CONFIG_QUUX=y - - - Temporary defconfig for TPL image - CONFIG_FOO=300 - CONFIG_BAR=y - CONFIG_QUX=y - CONFIG_QUUX=y - -They are passed to scripts/kconfig/conf, each is used for generating -.config, spl/.config, tpl/.config, respectively. - -- savedefconfig - -This is the reverse operation of 'make defconfig'. -If neither CONFIG_SPL nor CONFIG_TPL is defined in the .config file, -it works as 'make savedefconfig' in Linux Kernel: create the minimal set -of config based on the .config and save it into 'defconfig' file. - -If CONFIG_SPL or CONFIG_TPL is defined, the common lines among .config, -spl/.config, tpl/.config are coalesced together and output to the file -'defconfig' in the form like: - - CONFIG_FOO=100 - S:CONFIG_FOO=200 - T:CONFIG_FOO=300 - ST:CONFIG_BAR=y - +S:CONFIG_BAZ=y - +T:CONFIG_QUX=y - +ST:CONFIG_QUUX=y - -This can be used as an input of 'make <board>_defconfig' command. -""" - -import errno -import os -import re -import subprocess -import sys - -# Constant variables -SUB_IMAGES = ('spl', 'tpl') -IMAGES = ('',) + SUB_IMAGES -SYMBOL_MAP = {'': '+', 'spl': 'S', 'tpl': 'T'} -PATTERN_SYMBOL = re.compile(r'(\+?)(S?)(T?):(.*)') - -# Environment variables (should be defined in the top Makefile) -# .get('key', 'default_value') method is useful for standalone testing. -MAKE = os.environ.get('MAKE', 'make') -srctree = os.environ.get('srctree', '.') -KCONFIG_CONFIG = os.environ.get('KCONFIG_CONFIG', '.config') - -# Useful shorthand -build = '%s -f %s/scripts/Makefile.build obj=scripts/kconfig %%s' % (MAKE, srctree) -autoconf = '%s -f %s/scripts/Makefile.autoconf obj=%%s %%s' % (MAKE, srctree) - -### helper functions ### -def mkdirs(*dirs): - """Make directories ignoring 'File exists' error.""" - for d in dirs: - try: - os.makedirs(d) - except OSError as exception: - # Ignore 'File exists' error - if exception.errno != errno.EEXIST: - raise - -def rmfiles(*files): - """Remove files ignoring 'No such file or directory' error.""" - for f in files: - try: - os.remove(f) - except OSError as exception: - # Ignore 'No such file or directory' error - if exception.errno != errno.ENOENT: - raise - -def rmdirs(*dirs): - """Remove directories ignoring 'No such file or directory' - and 'Directory not empty' error. - """ - for d in dirs: - try: - os.rmdir(d) - except OSError as exception: - # Ignore 'No such file or directory' - # and 'Directory not empty' error - if exception.errno != errno.ENOENT and \ - exception.errno != errno.ENOTEMPTY: - raise - -def error(msg): - """Output the given argument to stderr and exit with return code 1.""" - print >> sys.stderr, msg - sys.exit(1) - -def run_command(command, callback_on_error=None): - """Run the given command in a sub-shell (and exit if it fails). - - Arguments: - command: A string of the command - callback_on_error: Callback handler invoked just before exit - when the command fails (Default=None) - """ - retcode = subprocess.call(command, shell=True) - if retcode: - if callback_on_error: - callback_on_error() - error("'%s' Failed" % command) - -def run_make_config(cmd, objdir, callback_on_error=None): - """Run the make command in a sub-shell (and exit if it fails). - - Arguments: - cmd: Make target such as 'config', 'menuconfig', 'defconfig', etc. - objdir: Target directory where the make command is run. - Typically '', 'spl', 'tpl' for Normal, SPL, TPL image, - respectively. - callback_on_error: Callback handler invoked just before exit - when the command fails (Default=None) - """ - # Linux expects defconfig files in arch/$(SRCARCH)/configs/ directory, - # but U-Boot puts them in configs/ directory. - # Give SRCARCH=.. to fake scripts/kconfig/Makefile. - options = 'SRCARCH=.. KCONFIG_OBJDIR=%s' % objdir - if objdir: - options += ' KCONFIG_CONFIG=%s/%s' % (objdir, KCONFIG_CONFIG) - mkdirs(objdir) - run_command(build % cmd + ' ' + options, callback_on_error) - -def get_enabled_subimages(ignore_error=False): - """Parse .config file to detect if CONFIG_SPL, CONFIG_TPL is enabled - and return a tuple of enabled subimages. - - Arguments: - ignore_error: Specify the behavior when '.config' is not found; - Raise an exception if this flag is False. - Return a null tuple if this flag is True. - - Returns: - A tuple of enabled subimages as follows: - () if neither CONFIG_SPL nor CONFIG_TPL is defined - ('spl',) if CONFIG_SPL is defined but CONFIG_TPL is not - ('spl', 'tpl') if both CONFIG_SPL and CONFIG_TPL are defined - """ - enabled = () - match_patterns = [ (img, 'CONFIG_' + img.upper() + '=y\n') - for img in SUB_IMAGES ] - try: - f = open(KCONFIG_CONFIG) - except IOError as exception: - if not ignore_error or exception.errno != errno.ENOENT: - raise - return enabled - with f: - for line in f: - for img, pattern in match_patterns: - if line == pattern: - enabled += (img,) - return enabled - -def do_silentoldconfig(cmd): - """Run 'make silentoldconfig' for all the enabled images. - - Arguments: - cmd: should always be a string 'silentoldconfig' - """ - run_make_config(cmd, '') - subimages = get_enabled_subimages() - for obj in subimages: - mkdirs(os.path.join(obj, 'include', 'config'), - os.path.join(obj, 'include', 'generated')) - run_make_config(cmd, obj) - remove_auto_conf = lambda : rmfiles('include/config/auto.conf') - # If the following part failed, include/config/auto.conf should be deleted - # so 'make silentoldconfig' will be re-run on the next build. - run_command(autoconf % - ('include', 'include/autoconf.mk include/autoconf.mk.dep'), - remove_auto_conf) - # include/config.h has been updated after 'make silentoldconfig'. - # We need to touch include/config/auto.conf so it gets newer - # than include/config.h. - # Otherwise, 'make silentoldconfig' would be invoked twice. - os.utime('include/config/auto.conf', None) - for obj in subimages: - run_command(autoconf % (obj + '/include', - obj + '/include/autoconf.mk'), - remove_auto_conf) - -def do_tmp_defconfig(output_lines, img): - """Helper function for do_board_defconfig(). - - Write the defconfig contents into a file '.tmp_defconfig' and - invoke 'make .tmp_defconfig'. - - Arguments: - output_lines: A sequence of defconfig lines of each image - img: Target image. Typically '', 'spl', 'tpl' for - Normal, SPL, TPL images, respectively. - """ - TMP_DEFCONFIG = '.tmp_defconfig' - TMP_DIRS = ('arch', 'configs') - defconfig_path = os.path.join('configs', TMP_DEFCONFIG) - mkdirs(*TMP_DIRS) - with open(defconfig_path, 'w') as f: - f.write(''.join(output_lines[img])) - cleanup = lambda: (rmfiles(defconfig_path), rmdirs(*TMP_DIRS)) - run_make_config(TMP_DEFCONFIG, img, cleanup) - cleanup() - -def do_board_defconfig(cmd): - """Run 'make <board>_defconfig'. - - Arguments: - cmd: should be a string '<board>_defconfig' - """ - defconfig_path = os.path.join(srctree, 'configs', cmd) - output_lines = dict([ (img, []) for img in IMAGES ]) - with open(defconfig_path) as f: - for line in f: - m = PATTERN_SYMBOL.match(line) - if m: - for idx, img in enumerate(IMAGES): - if m.group(idx + 1): - output_lines[img].append(m.group(4) + '\n') - continue - output_lines[''].append(line) - do_tmp_defconfig(output_lines, '') - for img in get_enabled_subimages(): - do_tmp_defconfig(output_lines, img) - -def do_defconfig(cmd): - """Run 'make defconfig'. - - Arguments: - cmd: should always be a string 'defconfig' - """ - KBUILD_DEFCONFIG = os.environ['KBUILD_DEFCONFIG'] - print "*** Default configuration is based on '%s'" % KBUILD_DEFCONFIG - do_board_defconfig(KBUILD_DEFCONFIG) - -def do_savedefconfig(cmd): - """Run 'make savedefconfig'. - - Arguments: - cmd: should always be a string 'savedefconfig' - """ - DEFCONFIG = 'defconfig' - # Continue even if '.config' does not exist - subimages = get_enabled_subimages(True) - run_make_config(cmd, '') - output_lines = [] - prefix = {} - with open(DEFCONFIG) as f: - for line in f: - output_lines.append(line) - prefix[line] = '+' - for img in subimages: - run_make_config(cmd, img) - unmatched_lines = [] - with open(DEFCONFIG) as f: - for line in f: - if line in output_lines: - index = output_lines.index(line) - output_lines[index:index] = unmatched_lines - unmatched_lines = [] - prefix[line] += SYMBOL_MAP[img] - else: - ummatched_lines.append(line) - prefix[line] = SYMBOL_MAP[img] - with open(DEFCONFIG, 'w') as f: - for line in output_lines: - if prefix[line] == '+': - f.write(line) - else: - f.write(prefix[line] + ':' + line) - -def do_others(cmd): - """Run the make command other than 'silentoldconfig', 'defconfig', - '<board>_defconfig' and 'savedefconfig'. - - Arguments: - cmd: Make target in the form of '<target_image>/<config_command>' - The field '<target_image>/' is typically empty, 'spl/', 'tpl/' - for Normal, SPL, TPL images, respectively. - The field '<config_command>' is make target such as 'config', - 'menuconfig', etc. - """ - objdir, _, cmd = cmd.rpartition('/') - run_make_config(cmd, objdir) - -cmd_list = {'silentoldconfig': do_silentoldconfig, - 'defconfig': do_defconfig, - 'savedefconfig': do_savedefconfig} - -def main(): - cmd = sys.argv[1] - if cmd.endswith('_defconfig'): - do_board_defconfig(cmd) - else: - func = cmd_list.get(cmd, do_others) - func(cmd) - -if __name__ == '__main__': - main() diff --git a/scripts/multiconfig.sh b/scripts/multiconfig.sh new file mode 100644 index 0000000000..56cf0c2a5d --- /dev/null +++ b/scripts/multiconfig.sh @@ -0,0 +1,260 @@ +#!/bin/sh +# +# A wrapper script to adjust Kconfig for U-Boot +# +# Instead of touching various parts under the scripts/kconfig/ directory, +# pushing necessary adjustments into this single script would be better +# for code maintainance. All the make targets related to the configuration +# (make %config) should be invoked via this script. +# See doc/README.kconfig for further information of Kconfig. +# +# Copyright (C) 2014, Masahiro Yamada <yamada.m@jp.panasonic.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +set -e + +# Set "DEBUG" enavironment variable to show debug messages +debug () { + if [ $DEBUG ]; then + echo "$@" + fi +} + +# Useful shorthands +build () { + debug $progname: $MAKE -f $srctree/scripts/Makefile.build obj="$@" + $MAKE -f $srctree/scripts/Makefile.build obj="$@" +} + +autoconf () { + debug $progname: $MAKE -f $srctree/scripts/Makefile.autoconf obj="$@" + $MAKE -f $srctree/scripts/Makefile.autoconf obj="$@" +} + +# Make a configuration target +# Usage: +# run_make_config <target> <objdir> +# <target>: Make target such as "config", "menuconfig", "defconfig", etc. +# <objdir>: Target directory where the make command is run. +# Typically "", "spl", "tpl" for Normal, SPL, TPL, respectively. +run_make_config () { + target=$1 + objdir=$2 + + # Linux expects defconfig files in arch/$(SRCARCH)/configs/ directory, + # but U-Boot has them in configs/ directory. + # Give SRCARCH=.. to fake scripts/kconfig/Makefile. + options="SRCARCH=.. KCONFIG_OBJDIR=$objdir" + if [ "$objdir" ]; then + options="$options KCONFIG_CONFIG=$objdir/$KCONFIG_CONFIG" + mkdir -p $objdir + fi + + build scripts/kconfig $options $target +} + +# Parse .config file to detect if CONFIG_SPL, CONFIG_TPL is enabled +# and returns: +# "" if neither CONFIG_SPL nor CONFIG_TPL is defined +# "spl" if CONFIG_SPL is defined but CONFIG_TPL is not +# "spl tpl" if both CONFIG_SPL and CONFIG_TPL are defined +get_enabled_subimages() { + if [ ! -r "$KCONFIG_CONFIG" ]; then + # This should never happen + echo "$progname: $KCONFIG_CONFIG not found" >&2 + exit 1 + fi + + # CONFIG_SPL=y -> spl + # CONFIG_TPL=y -> tpl + sed -n -e 's/^CONFIG_\(SPL\|TPL\)=y$/\1/p' $KCONFIG_CONFIG | \ + tr '[A-Z]' '[a-z]' +} + +do_silentoldconfig () { + run_make_config silentoldconfig + subimages=$(get_enabled_subimages) + + for obj in $subimages + do + mkdir -p $obj/include/config $obj/include/generated + run_make_config silentoldconfig $obj + done + + # If the following part fails, include/config/auto.conf should be + # deleted so "make silentoldconfig" will be re-run on the next build. + autoconf include include/autoconf.mk include/autoconf.mk.dep || { + rm -f include/config/auto.conf + exit 1 + } + + # include/config.h has been updated after "make silentoldconfig". + # We need to touch include/config/auto.conf so it gets newer + # than include/config.h. + # Otherwise, 'make silentoldconfig' would be invoked twice. + touch include/config/auto.conf + + for obj in $subimages + do + autoconf $obj/include $obj/include/autoconf.mk || { + rm -f include/config/auto.conf + exit 1 + } + done +} + +cleanup_after_defconfig () { + rm -f configs/.tmp_defconfig + # ignore 'Directory not empty' error + # without using non-POSIX option '--ignore-fail-on-non-empty' + rmdir arch configs 2>/dev/null || true +} + +# Usage: +# do_board_defconfig <board>_defconfig +do_board_defconfig () { + defconfig_path=$srctree/configs/$1 + tmp_defconfig_path=configs/.tmp_defconfig + + mkdir -p arch configs + # defconfig for Normal: + # pick lines without prefixes and lines starting '+' prefix + # and rip the prefixes off. + sed -n -e '/^[+A-Z]*:/!p' -e 's/^+[A-Z]*://p' $defconfig_path \ + > configs/.tmp_defconfig + + run_make_config .tmp_defconfig || { + cleanup_after_defconfig + exit 1 + } + + for img in $(get_enabled_subimages) + do + symbol=$(echo $img | cut -c 1 | tr '[a-z]' '[A-Z]') + # defconfig for SPL, TPL: + # pick lines with 'S', 'T' prefix and rip the prefixes off + sed -n -e 's/^[+A-Z]*'$symbol'[A-Z]*://p' $defconfig_path \ + > configs/.tmp_defconfig + run_make_config .tmp_defconfig $img || { + cleanup_after_defconfig + exit 1 + } + done + + cleanup_after_defconfig +} + +do_defconfig () { + if [ "$KBUILD_DEFCONFIG" ]; then + do_board_defconfig $KBUILD_DEFCONFIG + echo "*** Default configuration is based on '$KBUILD_DEFCONFIG'" + else + run_make_config defconfig + fi +} + +do_savedefconfig () { + if [ -r "$KCONFIG_CONFIG" ]; then + subimages=$(get_enabled_subimages) + else + subimages= + fi + + run_make_config savedefconfig + + output_lines= + + # -r option is necessay because some string-type configs may include + # backslashes as an escape character + while read -r line + do + output_lines="$output_lines $line" + done < defconfig + + for img in $subimages + do + run_make_config savedefconfig $img + + symbol=$(echo $img | cut -c 1 | tr '[a-z]' '[A-Z]') + unmatched= + + while read -r line + do + tmp= + match= + + # coalesce common lines together + for i in $output_lines + do + case "$i" in + "[+A-Z]*:$line") + tmp="$tmp $unmatched" + i=$(echo "$i" | \ + sed -e "s/^\([^:]\)*/\1$symbol/") + tmp="$tmp $i" + match=1 + ;; + "$line") + tmp="$tmp $unmatched" + tmp="$tmp +$symbol:$i" + match=1 + ;; + *) + tmp="$tmp $i" + ;; + esac + done + + if [ "$match" ]; then + output_lines="$tmp" + unmatched= + else + unmatched="$unmatched $symbol:$line" + fi + done < defconfig + done + + rm -f defconfig + for line in $output_lines + do + echo $line >> defconfig + done +} + +# Usage: +# do_others <objdir>/<target> +# The field "<objdir>/" is typically empy, "spl/", "tpl/" for Normal, SPL, TPL, +# respectively. +# The field "<target>" is a configuration target such as "config", +# "menuconfig", etc. +do_others () { + target=${1##*/} + + if [ "$target" = "$1" ]; then + objdir= + else + objdir=${1%/*} + fi + + run_make_config $target $objdir +} + +progname=$(basename $0) +target=$1 + +case $target in +*_defconfig) + do_board_defconfig $target;; +*_config) + do_board_defconfig ${target%_config}_defconfig;; +silentoldconfig) + do_silentoldconfig;; +defconfig) + do_defconfig;; +savedefconfig) + do_savedefconfig;; +*) + do_others $target;; +esac diff --git a/scripts/objdiff b/scripts/objdiff index b3e4f10bfc..62e51dae21 100755 --- a/scripts/objdiff +++ b/scripts/objdiff @@ -25,25 +25,47 @@ # # Note: 'make mrproper' will also remove .tmp_objdiff -GIT_DIR="`git rev-parse --git-dir`" +SRCTREE=$(cd $(git rev-parse --show-toplevel 2>/dev/null); pwd) -if [ -d "$GIT_DIR" ]; then - TMPD="${GIT_DIR%git}tmp_objdiff" - - [ -d "$TMPD" ] || mkdir "$TMPD" -else - echo "ERROR: git directory not found." +if [ -z "$SRCTREE" ]; then + echo >&2 "ERROR: Not a git repository." exit 1 fi +TMPD=$SRCTREE/.tmp_objdiff + usage() { - echo "Usage: $0 <command> <args>" - echo " record <list of object files>" - echo " diff <commitA> <commitB>" - echo " clean all | <commit>" + echo >&2 "Usage: $0 <command> <args>" + echo >&2 " record <list of object files or directories>" + echo >&2 " diff <commitA> <commitB>" + echo >&2 " clean all | <commit>" exit 1 } +get_output_dir() { + dir=${1%/*} + + if [ "$dir" = "$1" ]; then + dir=. + fi + + dir=$(cd $dir; pwd) + + echo $TMPD/$CMT${dir#$SRCTREE} +} + +do_objdump() { + dir=$(get_output_dir $1) + base=${1##*/} + dis=$dir/${base%.o}.dis + + [ ! -d "$dir" ] && mkdir -p $dir + + # remove addresses for a cleaner diff + # http://dummdida.tumblr.com/post/60924060451/binary-diff-between-libc-from-scientificlinux-and + $OBJDUMP -D $1 | sed "s/^[[:space:]]\+[0-9a-f]\+//" > $dis +} + dorecord() { [ $# -eq 0 ] && usage @@ -52,20 +74,16 @@ dorecord() { CMT="`git rev-parse --short HEAD`" OBJDUMP="${CROSS_COMPILE}objdump" - OBJDIFFD="$TMPD/$CMT" - - [ ! -d "$OBJDIFFD" ] && mkdir -p "$OBJDIFFD" - for f in $FILES; do - dn="${f%/*}" - bn="${f##*/}" - - [ ! -d "$OBJDIFFD/$dn" ] && mkdir -p "$OBJDIFFD/$dn" - - # remove addresses for a more clear diff - # http://dummdida.tumblr.com/post/60924060451/binary-diff-between-libc-from-scientificlinux-and - $OBJDUMP -D "$f" | sed "s/^[[:space:]]\+[0-9a-f]\+//" \ - >"$OBJDIFFD/$dn/$bn" + for d in $FILES; do + if [ -d "$d" ]; then + for f in $(find $d -name '*.o') + do + do_objdump $f + done + else + do_objdump $d + fi done } @@ -90,12 +108,12 @@ dodiff() { DSTD="$TMPD/$DST" if [ ! -d "$SRCD" ]; then - echo "ERROR: $SRCD doesn't exist" + echo >&2 "ERROR: $SRCD doesn't exist" exit 1 fi if [ ! -d "$DSTD" ]; then - echo "ERROR: $DSTD doesn't exist" + echo >&2 "ERROR: $DSTD doesn't exist" exit 1 fi @@ -114,7 +132,7 @@ doclean() { if [ -d "$TMPD/$CMT" ]; then rm -rf $TMPD/$CMT else - echo "$CMT not found" + echo >&2 "$CMT not found" fi fi } @@ -135,7 +153,7 @@ case "$1" in doclean $* ;; *) - echo "Unrecognized command '$1'" + echo >&2 "Unrecognized command '$1'" exit 1 ;; esac diff --git a/test/dfu/dfu_gadget_test.sh b/test/dfu/dfu_gadget_test.sh index 4133155ae9..2f5b7db58d 100755 --- a/test/dfu/dfu_gadget_test.sh +++ b/test/dfu/dfu_gadget_test.sh @@ -1,5 +1,15 @@ #! /bin/bash +# Copyright (C) 2014 Samsung Electronics +# Lukasz Majewski <l.majewski@samsung.com> +# +# Script fixes, enhancements and testing: +# Stephen Warren <swarren@nvidia.com> +# +# DFU operation test script +# +# SPDX-License-Identifier: GPL-2.0+ + set -e # any command return if not equal to zero clear diff --git a/test/dfu/dfu_gadget_test_init.sh b/test/dfu/dfu_gadget_test_init.sh index 2163a685a5..640628eecb 100755 --- a/test/dfu/dfu_gadget_test_init.sh +++ b/test/dfu/dfu_gadget_test_init.sh @@ -1,5 +1,15 @@ #! /bin/bash +# Copyright (C) 2014 Samsung Electronics +# Lukasz Majewski <l.majewski@samsung.com> +# +# Script fixes, enhancements and testing: +# Stephen Warren <swarren@nvidia.com> +# +# Script for test files generation +# +# SPDX-License-Identifier: GPL-2.0+ + set -e # any command return if not equal to zero clear @@ -9,7 +19,11 @@ COLOUR_DEFAULT="\33[0m" LOG_DIR="./log" -TEST_FILES_SIZES="63 64 65 127 128 129 4095 4096 4097 959 960 961 1048575 1048576 8M" +if [ $# -eq 0 ]; then + TEST_FILES_SIZES="63 64 65 127 128 129 4095 4096 4097 959 960 961 1048575 1048576 8M" +else + TEST_FILES_SIZES=$@ +fi printf "Init script for generating data necessary for DFU test script" diff --git a/test/ums/README b/test/ums/README new file mode 100644 index 0000000000..c80fbfefbf --- /dev/null +++ b/test/ums/README @@ -0,0 +1,30 @@ +UMS test script. + +ums_gadget_test.sh +================== + +Example usage: +1. On the target: + create UMS exportable partitions (with e.g. gpt write), or specify a + partition number (PART_NUM) as "-" to use the entire device + ums 0 mmc 0 +2. On the host: + sudo test/ums/ums_gadget_test.sh VID PID PART_NUM [-f FILE_SYSTEM] [test_file] + e.g. sudo test/ums/ums_gadget_test.sh 0525 a4a5 6 -f vfat ./dat_14M.img + +... where: + VID - UMS device USB Vendor ID + PID - UMS device USB Product ID + PART_NUM - is the partition number on which UMS operates or "-" to use the + whole device + +Information about available partitions on the target one can read with using +the 'mmc part' or 'part list' commands. + +The partition num (PART_NUM) can be specified as '-' for using the whole device. + +The [-f FILE_SYSTEM] optional switch allows for formatting target partition to +FILE_SYSTEM. + +The last, optional [test_file] parameter is for specifying the exact test file +to use. diff --git a/test/ums/ums_gadget_test.sh b/test/ums/ums_gadget_test.sh new file mode 100755 index 0000000000..56d4616376 --- /dev/null +++ b/test/ums/ums_gadget_test.sh @@ -0,0 +1,175 @@ +#! /bin/bash + +# Copyright (C) 2014 Samsung Electronics +# Lukasz Majewski <l.majewski@samsung.com> +# +# UMS operation test script +# +# SPDX-License-Identifier: GPL-2.0+ + +clear + +COLOUR_RED="\33[31m" +COLOUR_GREEN="\33[32m" +COLOUR_DEFAULT="\33[0m" + +DIR=./ +SUFFIX=img +RCV_DIR=rcv/ +LOG_FILE=./log/log-`date +%d-%m-%Y_%H-%M-%S` + +cd `dirname $0` +../dfu/dfu_gadget_test_init.sh 33M 97M + +cleanup () { + rm -rf $RCV_DIR $MNT_DIR +} + +control_c() +# run if user hits control-c +{ + echo -en "\n*** CTRL+C ***\n" + umount $MNT_DIR + cleanup + exit 0 +} + +# trap keyboard interrupt (control-c) +trap control_c SIGINT + +die () { + printf " $COLOUR_RED FAILED $COLOUR_DEFAULT \n" + cleanup + exit 1 +} + +calculate_md5sum () { + MD5SUM=`md5sum $1` + MD5SUM=`echo $MD5SUM | cut -d ' ' -f1` + echo "md5sum:"$MD5SUM +} + +ums_test_file () { + printf "$COLOUR_GREEN========================================================================================= $COLOUR_DEFAULT\n" + printf "File:$COLOUR_GREEN %s $COLOUR_DEFAULT\n" $1 + + mount /dev/$MEM_DEV $MNT_DIR + if [ -f $MNT_DIR/dat_* ]; then + rm $MNT_DIR/dat_* + fi + + cp ./$1 $MNT_DIR + umount $MNT_DIR + + + echo -n "TX: " + calculate_md5sum $1 + + MD5_TX=$MD5SUM + sleep 1 + N_FILE=$DIR$RCV_DIR${1:2}"_rcv" + + mount /dev/$MEM_DEV $MNT_DIR + cp $MNT_DIR/$1 $N_FILE || die $? + rm $MNT_DIR/$1 + umount $MNT_DIR + + echo -n "RX: " + calculate_md5sum $N_FILE + MD5_RX=$MD5SUM + + if [ "$MD5_TX" == "$MD5_RX" ]; then + printf " $COLOUR_GREEN -------> OK $COLOUR_DEFAULT \n" + else + printf " $COLOUR_RED -------> FAILED $COLOUR_DEFAULT \n" + cleanup + exit 1 + fi +} + +printf "$COLOUR_GREEN========================================================================================= $COLOUR_DEFAULT\n" +echo "U-boot UMS test program" + +if [ $EUID -ne 0 ]; then + echo "You must be root to do this." 1>&2 + exit 100 +fi + +if [ $# -lt 3 ]; then + echo "Wrong number of arguments" + echo "Example:" + echo "sudo ./ums_gadget_test.sh VID PID PART_NUM [-f ext4] [test_file]" + die +fi + +MNT_DIR="/mnt/tmp-ums-test" + +VID=$1; shift +PID=$1; shift +PART_NUM=$1; shift + +if [ "$1" == "-f" ]; then + shift + FS_TO_FORMAT=$1; shift +fi + +TEST_FILE=$1 + +for f in `find /sys -type f -name idProduct`; do + d=`dirname ${f}` + if [ `cat ${d}/idVendor` != "${VID}" ]; then + continue + fi + if [ `cat ${d}/idProduct` != "${PID}" ]; then + continue + fi + USB_DEV=${d} + break +done + +if [ -z "${USB_DEV}" ]; then + echo "Connect target" + echo "e.g. ums 0 mmc 0" + exit 1 +fi + +MEM_DEV=`find $USB_DEV -type d -name "sd[a-z]" | awk -F/ '{print $(NF)}' -` + +mkdir -p $RCV_DIR +if [ ! -d $MNT_DIR ]; then + mkdir -p $MNT_DIR +fi + +if [ "$PART_NUM" == "-" ]; then + PART_NUM="" +fi +MEM_DEV=$MEM_DEV$PART_NUM + +if [ -n "$FS_TO_FORMAT" ]; then + echo -n "Formatting partition /dev/$MEM_DEV to $FS_TO_FORMAT" + mkfs -t $FS_TO_FORMAT /dev/$MEM_DEV > /dev/null 2>&1 + if [ $? -eq 0 ]; then + printf " $COLOUR_GREEN DONE $COLOUR_DEFAULT \n" + else + die + fi +fi + +printf "Mount: /dev/$MEM_DEV \n" + +if [ -n "$TEST_FILE" ]; then + if [ ! -e $TEST_FILE ]; then + echo "No file: $TEST_FILE" + die + fi + ums_test_file $TEST_FILE +else + for file in $DIR*.$SUFFIX + do + ums_test_file $file + done +fi + +cleanup + +exit 0 diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py index d5b8454c08..a555bd81fc 100644 --- a/tools/buildman/builder.py +++ b/tools/buildman/builder.py @@ -308,7 +308,7 @@ class Builder: Args: commit: Commit object that is being built brd: Board object that is being built - stage: Stage that we are at (distclean, config, build) + stage: Stage that we are at (mrproper, config, build) cwd: Directory where make should be run args: Arguments to pass to make kwargs: Arguments to pass to command.RunPipe() diff --git a/tools/buildman/builderthread.py b/tools/buildman/builderthread.py index 32297e20e8..8214662e36 100644 --- a/tools/buildman/builderthread.py +++ b/tools/buildman/builderthread.py @@ -91,7 +91,7 @@ class BuilderThread(threading.Thread): commit: Commit object that is being built brd: Board object that is being built stage: Stage of the build. Valid stages are: - distclean - can be called to clean source + mrproper - can be called to clean source config - called to configure for a board build - the main make invocation - it does the build args: A list of arguments to pass to 'make' @@ -200,8 +200,8 @@ class BuilderThread(threading.Thread): # If we need to reconfigure, do that now if do_config: - result = self.Make(commit, brd, 'distclean', cwd, - 'distclean', *args, env=env) + result = self.Make(commit, brd, 'mrproper', cwd, + 'mrproper', *args, env=env) result = self.Make(commit, brd, 'config', cwd, *(args + config_args), env=env) config_out = result.combined diff --git a/tools/buildman/buildman.py b/tools/buildman/buildman.py index 6ca8dc65b5..e18859b3d7 100755 --- a/tools/buildman/buildman.py +++ b/tools/buildman/buildman.py @@ -118,7 +118,7 @@ parser.add_option('-u', '--show_unknown', action='store_true', parser.add_option('-v', '--verbose', action='store_true', default=False, help='Show build results while the build progresses') -parser.usage = """buildman -b <branch> [options] +parser.usage += """ Build U-Boot for all commits in a branch. Use -n to do a dry run""" diff --git a/tools/buildman/control.py b/tools/buildman/control.py index 98a07a29e7..d98e50ac1f 100644 --- a/tools/buildman/control.py +++ b/tools/buildman/control.py @@ -110,15 +110,13 @@ def DoBuildman(options, args): if count is None: str = ("Branch '%s' not found or has no upstream" % options.branch) - print col.Color(col.RED, str) - sys.exit(1) + sys.exit(col.Color(col.RED, str)) count += 1 # Build upstream commit also if not count: str = ("No commits found to process in branch '%s': " "set branch's upstream or use -c flag" % options.branch) - print col.Color(col.RED, str) - sys.exit(1) + sys.exit(col.Color(col.RED, str)) # Work out what subset of the boards we are building board_file = os.path.join(options.git, 'boards.cfg') @@ -127,16 +125,14 @@ def DoBuildman(options, args): status = subprocess.call([os.path.join(options.git, 'tools/genboardscfg.py')]) if status != 0: - print >> sys.stderr, "Failed to generate boards.cfg" - sys.exit(1) + sys.exit("Failed to generate boards.cfg") boards = board.Boards() boards.ReadBoards(os.path.join(options.git, 'boards.cfg')) why_selected = boards.SelectBoards(args) selected = boards.GetSelected() if not len(selected): - print col.Color(col.RED, 'No matching boards found') - sys.exit(1) + sys.exit(col.Color(col.RED, 'No matching boards found')) # Read the metadata from the commits. First look at the upstream commit, # then the ones in the branch. We would like to do something like @@ -182,8 +178,7 @@ def DoBuildman(options, args): gnu_make = command.Output(os.path.join(options.git, 'scripts/show-gnu-make')).rstrip() if not gnu_make: - print >> sys.stderr, 'GNU Make not found' - sys.exit(1) + sys.exit('GNU Make not found') # Create a new builder with the selected options if options.branch: diff --git a/tools/genboardscfg.py b/tools/genboardscfg.py index 734d90b5e5..e92e4f8880 100755 --- a/tools/genboardscfg.py +++ b/tools/genboardscfg.py @@ -36,7 +36,7 @@ COMMENT_BLOCK = '''# # List of boards # Automatically generated by %s: don't edit # -# Status, Arch, CPU(:SPLCPU), SoC, Vendor, Board, Target, Options, Maintainers +# Status, Arch, CPU, SoC, Vendor, Board, Target, Options, Maintainers ''' % __file__ @@ -58,8 +58,6 @@ def get_terminal_columns(): try: ret = fcntl.ioctl(sys.stdout.fileno(), termios.TIOCGWINSZ, arg) except IOError as exception: - if exception.errno != errno.ENOTTY: - raise # If 'Inappropriate ioctl for device' error occurs, # stdout is probably redirected. Return 0. return 0 @@ -77,16 +75,14 @@ def check_top_directory(): """Exit if we are not at the top of source directory.""" for f in ('README', 'Licenses'): if not os.path.exists(f): - print >> sys.stderr, 'Please run at the top of source directory.' - sys.exit(1) + sys.exit('Please run at the top of source directory.') def get_make_cmd(): """Get the command name of GNU Make.""" process = subprocess.Popen([SHOW_GNU_MAKE], stdout=subprocess.PIPE) ret = process.communicate() if process.returncode: - print >> sys.stderr, 'GNU Make not found' - sys.exit(1) + sys.exit('GNU Make not found') return ret[0].rstrip() ### classes ### @@ -209,16 +205,12 @@ class DotConfigParser: # sanity check of '.config' file for field in self.must_fields: if not field in fields: - print >> sys.stderr, 'Error: %s is not defined in %s' % \ - (field, defconfig) - sys.exit(1) + sys.exit('Error: %s is not defined in %s' % (field, defconfig)) - # fix-up for aarch64 and tegra + # fix-up for aarch64 if fields['arch'] == 'arm' and 'cpu' in fields: if fields['cpu'] == 'armv8': fields['arch'] = 'aarch64' - if 'soc' in fields and re.match('tegra[0-9]*$', fields['soc']): - fields['cpu'] += ':arm720t' target, match, rear = defconfig.partition('_defconfig') assert match and not rear, \ @@ -408,7 +400,7 @@ def __gen_boards_cfg(jobs): jobs: The number of jobs to run simultaneously Note: - The incomplete boards.cfg is left over when an error (including + The incomplete boards.cfg is left over when an error (including the termination by the keyboard interrupt) occurs on the halfway. """ check_top_directory() @@ -455,8 +447,7 @@ def __gen_boards_cfg(jobs): # wait until the reformat tool finishes reformat_process.communicate() if reformat_process.returncode != 0: - print >> sys.stderr, '"%s" failed' % REFORMAT_CMD[0] - sys.exit(1) + sys.exit('"%s" failed' % REFORMAT_CMD[0]) def gen_boards_cfg(jobs): """Generate boards.cfg file. @@ -489,8 +480,7 @@ def main(): try: jobs = int(options.jobs) except ValueError: - print >> sys.stderr, 'Option -j (--jobs) takes a number' - sys.exit(1) + sys.exit('Option -j (--jobs) takes a number') else: try: jobs = int(subprocess.Popen(['getconf', '_NPROCESSORS_ONLN'], diff --git a/tools/patman/checkpatch.py b/tools/patman/checkpatch.py index 0d4e935244..34a3bd22b0 100644 --- a/tools/patman/checkpatch.py +++ b/tools/patman/checkpatch.py @@ -34,9 +34,8 @@ def FindCheckPatch(): return fname path = os.path.dirname(path) - print >> sys.stderr, ('Cannot find checkpatch.pl - please put it in your ' + - '~/bin directory or use --no-check') - sys.exit(1) + sys.exit('Cannot find checkpatch.pl - please put it in your ' + + '~/bin directory or use --no-check') def CheckPatch(fname, verbose=False): """Run checkpatch.pl on a file. diff --git a/tools/patman/patman.py b/tools/patman/patman.py index c60aa5a1c4..ca34cb9fd8 100755 --- a/tools/patman/patman.py +++ b/tools/patman/patman.py @@ -58,7 +58,7 @@ parser.add_option('--no-check', action='store_false', dest='check_patch', parser.add_option('--no-tags', action='store_false', dest='process_tags', default=True, help="Don't process subject tags as aliaes") -parser.usage = """patman [options] +parser.usage += """ Create patches from commits in a branch, check them and email them as specified by tags you place in the commits. Use -n to do a dry run first.""" @@ -122,8 +122,7 @@ else: col = terminal.Color() if not options.count: str = 'No commits found to process - please use -c flag' - print col.Color(col.RED, str) - sys.exit(1) + sys.exit(col.Color(col.RED, str)) # Read the metadata from the commits if options.count: |