Merge with /home/wd/git/u-boot/master

103 files changed, 7353 insertions, 366 deletions

diff --git a/include/405_mal.h b/include/405_mal.h
index 0598586953..2a421848b4 100644
--- a/include/405_mal.h
+++ b/include/405_mal.h
@@ -92,7 +92,7 @@
 #define MAL_ESR_PBEI	  0x00000001
       /* ^^			 ^^   */
       /* Mal IER		      */
-#ifdef CONFIG_440SPE
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define MAL_IER_PT	  0x00000080
 #define MAL_IER_PRE	  0x00000040
 #define MAL_IER_PWE	  0x00000020
diff --git a/include/440_i2c.h b/include/440_i2c.h
index 9c90a9e3c4..0c2bf36273 100644
--- a/include/440_i2c.h
+++ b/include/440_i2c.h
@@ -1,7 +1,8 @@
 #ifndef _440_i2c_h_
 #define _440_i2c_h_
 
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define    I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000700)
 #else
 #define    I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000400)
diff --git a/include/_exports.h b/include/_exports.h
index 61dcaaf331..2b8ec3d3f9 100644
--- a/include/_exports.h
+++ b/include/_exports.h
@@ -12,6 +12,9 @@ EXPORT_FUNC(udelay)
 EXPORT_FUNC(get_timer)
 EXPORT_FUNC(vprintf)
 EXPORT_FUNC(do_reset)
+EXPORT_FUNC(getenv)
+EXPORT_FUNC(setenv)
+EXPORT_FUNC(simple_strtoul)
 #if (CONFIG_COMMANDS & CFG_CMD_I2C)
 EXPORT_FUNC(i2c_write)
 EXPORT_FUNC(i2c_read)
diff --git a/include/ahci.h b/include/ahci.h
new file mode 100644
index 0000000000..80701e298c
--- /dev/null
+++ b/include/ahci.h
@@ -0,0 +1,190 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+ * Author: Jason Jin<Jason.jin@freescale.com>
+ *         Zhang Wei<wei.zhang@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#ifndef _AHCI_H_
+#define _AHCI_H_
+
+#define AHCI_PCI_BAR		0x24
+#define AHCI_MAX_SG		56 /* hardware max is 64K */
+#define AHCI_CMD_SLOT_SZ	32
+#define AHCI_RX_FIS_SZ		256
+#define AHCI_CMD_TBL_HDR	0x80
+#define AHCI_CMD_TBL_CDB	0x40
+#define AHCI_CMD_TBL_SZ		AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16)
+#define AHCI_PORT_PRIV_DMA_SZ	AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ	\
+				+ AHCI_RX_FIS_SZ
+#define AHCI_CMD_ATAPI		(1 << 5)
+#define AHCI_CMD_WRITE		(1 << 6)
+#define AHCI_CMD_PREFETCH	(1 << 7)
+#define AHCI_CMD_RESET		(1 << 8)
+#define AHCI_CMD_CLR_BUSY	(1 << 10)
+
+#define RX_FIS_D2H_REG		0x40	/* offset of D2H Register FIS data */
+
+/* Global controller registers */
+#define HOST_CAP		0x00 /* host capabilities */
+#define HOST_CTL		0x04 /* global host control */
+#define HOST_IRQ_STAT		0x08 /* interrupt status */
+#define HOST_PORTS_IMPL		0x0c /* bitmap of implemented ports */
+#define HOST_VERSION		0x10 /* AHCI spec. version compliancy */
+
+/* HOST_CTL bits */
+#define HOST_RESET		(1 << 0)  /* reset controller; self-clear */
+#define HOST_IRQ_EN		(1 << 1)  /* global IRQ enable */
+#define HOST_AHCI_EN		(1 << 31) /* AHCI enabled */
+
+/* Registers for each SATA port */
+#define PORT_LST_ADDR		0x00 /* command list DMA addr */
+#define PORT_LST_ADDR_HI	0x04 /* command list DMA addr hi */
+#define PORT_FIS_ADDR		0x08 /* FIS rx buf addr */
+#define PORT_FIS_ADDR_HI	0x0c /* FIS rx buf addr hi */
+#define PORT_IRQ_STAT		0x10 /* interrupt status */
+#define PORT_IRQ_MASK		0x14 /* interrupt enable/disable mask */
+#define PORT_CMD		0x18 /* port command */
+#define PORT_TFDATA		0x20 /* taskfile data */
+#define PORT_SIG		0x24 /* device TF signature */
+#define PORT_CMD_ISSUE		0x38 /* command issue */
+#define PORT_SCR		0x28 /* SATA phy register block */
+#define PORT_SCR_STAT		0x28 /* SATA phy register: SStatus */
+#define PORT_SCR_CTL		0x2c /* SATA phy register: SControl */
+#define PORT_SCR_ERR		0x30 /* SATA phy register: SError */
+#define PORT_SCR_ACT		0x34 /* SATA phy register: SActive */
+
+/* PORT_IRQ_{STAT,MASK} bits */
+#define PORT_IRQ_COLD_PRES	(1 << 31) /* cold presence detect */
+#define PORT_IRQ_TF_ERR		(1 << 30) /* task file error */
+#define PORT_IRQ_HBUS_ERR	(1 << 29) /* host bus fatal error */
+#define PORT_IRQ_HBUS_DATA_ERR	(1 << 28) /* host bus data error */
+#define PORT_IRQ_IF_ERR		(1 << 27) /* interface fatal error */
+#define PORT_IRQ_IF_NONFATAL	(1 << 26) /* interface non-fatal error */
+#define PORT_IRQ_OVERFLOW	(1 << 24) /* xfer exhausted available S/G */
+#define PORT_IRQ_BAD_PMP	(1 << 23) /* incorrect port multiplier */
+
+#define PORT_IRQ_PHYRDY		(1 << 22) /* PhyRdy changed */
+#define PORT_IRQ_DEV_ILCK	(1 << 7) /* device interlock */
+#define PORT_IRQ_CONNECT	(1 << 6) /* port connect change status */
+#define PORT_IRQ_SG_DONE	(1 << 5) /* descriptor processed */
+#define PORT_IRQ_UNK_FIS	(1 << 4) /* unknown FIS rx'd */
+#define PORT_IRQ_SDB_FIS	(1 << 3) /* Set Device Bits FIS rx'd */
+#define PORT_IRQ_DMAS_FIS	(1 << 2) /* DMA Setup FIS rx'd */
+#define PORT_IRQ_PIOS_FIS	(1 << 1) /* PIO Setup FIS rx'd */
+#define PORT_IRQ_D2H_REG_FIS	(1 << 0) /* D2H Register FIS rx'd */
+
+#define PORT_IRQ_FATAL		PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_ERR 	\
+				| PORT_IRQ_HBUS_DATA_ERR | PORT_IRQ_IF_ERR
+
+#define DEF_PORT_IRQ		PORT_IRQ_FATAL | PORT_IRQ_PHYRDY 	\
+				| PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE 	\
+				| PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS 	\
+				| PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS	\
+				| PORT_IRQ_D2H_REG_FIS
+
+/* PORT_CMD bits */
+#define PORT_CMD_ATAPI		(1 << 24) /* Device is ATAPI */
+#define PORT_CMD_LIST_ON	(1 << 15) /* cmd list DMA engine running */
+#define PORT_CMD_FIS_ON		(1 << 14) /* FIS DMA engine running */
+#define PORT_CMD_FIS_RX		(1 << 4) /* Enable FIS receive DMA engine */
+#define PORT_CMD_CLO		(1 << 3) /* Command list override */
+#define PORT_CMD_POWER_ON	(1 << 2) /* Power up device */
+#define PORT_CMD_SPIN_UP	(1 << 1) /* Spin up device */
+#define PORT_CMD_START		(1 << 0) /* Enable port DMA engine */
+
+#define PORT_CMD_ICC_ACTIVE	(0x1 << 28) /* Put i/f in active state */
+#define PORT_CMD_ICC_PARTIAL	(0x2 << 28) /* Put i/f in partial state */
+#define PORT_CMD_ICC_SLUMBER	(0x6 << 28) /* Put i/f in slumber state */
+
+#define AHCI_MAX_PORTS		32
+
+/* SETFEATURES stuff */
+#define SETFEATURES_XFER	0x03
+#define XFER_UDMA_7		0x47
+#define XFER_UDMA_6		0x46
+#define XFER_UDMA_5		0x45
+#define XFER_UDMA_4		0x44
+#define XFER_UDMA_3		0x43
+#define XFER_UDMA_2		0x42
+#define XFER_UDMA_1		0x41
+#define XFER_UDMA_0		0x40
+#define XFER_MW_DMA_2		0x22
+#define XFER_MW_DMA_1		0x21
+#define XFER_MW_DMA_0		0x20
+#define XFER_SW_DMA_2		0x12
+#define XFER_SW_DMA_1		0x11
+#define XFER_SW_DMA_0		0x10
+#define XFER_PIO_4		0x0C
+#define XFER_PIO_3		0x0B
+#define XFER_PIO_2		0x0A
+#define XFER_PIO_1		0x09
+#define XFER_PIO_0		0x08
+#define XFER_PIO_SLOW		0x00
+
+#define ATA_FLAG_SATA		(1 << 3)
+#define ATA_FLAG_NO_LEGACY	(1 << 4) /* no legacy mode check */
+#define ATA_FLAG_MMIO		(1 << 6) /* use MMIO, not PIO */
+#define ATA_FLAG_SATA_RESET	(1 << 7) /* (obsolete) use COMRESET */
+#define ATA_FLAG_PIO_DMA	(1 << 8) /* PIO cmds via DMA */
+#define ATA_FLAG_NO_ATAPI	(1 << 11) /* No ATAPI support */
+
+struct ahci_cmd_hdr {
+	u32	opts;
+	u32	status;
+	u32	tbl_addr;
+	u32	tbl_addr_hi;
+	u32	reserved[4];
+};
+
+struct ahci_sg {
+	u32	addr;
+	u32	addr_hi;
+	u32	reserved;
+	u32	flags_size;
+};
+
+struct ahci_ioports {
+	u32	cmd_addr;
+	u32	scr_addr;
+	u32	port_mmio;
+	struct ahci_cmd_hdr	*cmd_slot;
+	struct ahci_sg		*cmd_tbl_sg;
+	u32	cmd_tbl;
+	u32	rx_fis;
+};
+
+struct ahci_probe_ent {
+	pci_dev_t 	dev;
+	struct ahci_ioports	port[AHCI_MAX_PORTS];
+	u32	n_ports;
+	u32	hard_port_no;
+	u32	host_flags;
+	u32	host_set_flags;
+	u32	mmio_base;
+	u32     pio_mask;
+	u32	udma_mask;
+	u32	flags;
+	u32	cap;	/* cache of HOST_CAP register */
+	u32	port_map; /* cache of HOST_PORTS_IMPL reg */
+	u32	link_port_map; /*linkup port map*/
+};
+
+#endif
diff --git a/include/arm925t.h b/include/arm925t.h
index ab343eaace..3d767b35c0 100644
--- a/include/arm925t.h
+++ b/include/arm925t.h
@@ -6,10 +6,6 @@
 #ifndef __ARM925T_H__
 #define __ARM925T_H__
 
-void gpioreserve(ushort mask);
-void gpiosetdir(ushort mask, ushort in);
-void gpiosetout(ushort mask, ushort out);
-void gpioinit(void);
 void archflashwp(void *archdata, int wp);
 
 #endif /*__ARM925T_H__*/
diff --git a/include/asm-avr32/addrspace.h b/include/asm-avr32/addrspace.h
new file mode 100644
index 0000000000..b2ba1ee2fe
--- /dev/null
+++ b/include/asm-avr32/addrspace.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_ADDRSPACE_H
+#define __ASM_AVR32_ADDRSPACE_H
+
+/* Memory segments when segmentation is enabled */
+#define P0SEG		0x00000000
+#define P1SEG		0x80000000
+#define P2SEG		0xa0000000
+#define P3SEG		0xc0000000
+#define P4SEG		0xe0000000
+
+/* Returns the privileged segment base of a given address */
+#define PXSEG(a)	(((unsigned long)(a)) & 0xe0000000)
+
+/* Returns the physical address of a PnSEG (n=1,2) address */
+#define PHYSADDR(a)	(((unsigned long)(a)) & 0x1fffffff)
+
+/*
+ * Map an address to a certain privileged segment
+ */
+#define P1SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG))
+#define P2SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG))
+#define P3SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG))
+#define P4SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG))
+
+#endif /* __ASM_AVR32_ADDRSPACE_H */
diff --git a/include/asm-avr32/arch-at32ap7000/hmatrix2.h b/include/asm-avr32/arch-at32ap7000/hmatrix2.h
new file mode 100644
index 0000000000..e6df4b7fe3
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap7000/hmatrix2.h
@@ -0,0 +1,232 @@
+/*
+ * Register definition for the High-speed Bus Matrix
+ */
+#ifndef __ASM_AVR32_HMATRIX2_H__
+#define __ASM_AVR32_HMATRIX2_H__
+
+/* HMATRIX2 register offsets */
+#define HMATRIX2_MCFG0				0x0000
+#define HMATRIX2_MCFG1				0x0004
+#define HMATRIX2_MCFG2				0x0008
+#define HMATRIX2_MCFG3				0x000c
+#define HMATRIX2_MCFG4				0x0010
+#define HMATRIX2_MCFG5				0x0014
+#define HMATRIX2_MCFG6				0x0018
+#define HMATRIX2_MCFG7				0x001c
+#define HMATRIX2_MCFG8				0x0020
+#define HMATRIX2_MCFG9				0x0024
+#define HMATRIX2_MCFG10				0x0028
+#define HMATRIX2_MCFG11				0x002c
+#define HMATRIX2_MCFG12				0x0030
+#define HMATRIX2_MCFG13				0x0034
+#define HMATRIX2_MCFG14				0x0038
+#define HMATRIX2_MCFG15				0x003c
+#define HMATRIX2_SCFG0				0x0040
+#define HMATRIX2_SCFG1				0x0044
+#define HMATRIX2_SCFG2				0x0048
+#define HMATRIX2_SCFG3				0x004c
+#define HMATRIX2_SCFG4				0x0050
+#define HMATRIX2_SCFG5				0x0054
+#define HMATRIX2_SCFG6				0x0058
+#define HMATRIX2_SCFG7				0x005c
+#define HMATRIX2_SCFG8				0x0060
+#define HMATRIX2_SCFG9				0x0064
+#define HMATRIX2_SCFG10				0x0068
+#define HMATRIX2_SCFG11				0x006c
+#define HMATRIX2_SCFG12				0x0070
+#define HMATRIX2_SCFG13				0x0074
+#define HMATRIX2_SCFG14				0x0078
+#define HMATRIX2_SCFG15				0x007c
+#define HMATRIX2_PRAS0				0x0080
+#define HMATRIX2_PRBS0				0x0084
+#define HMATRIX2_PRAS1				0x0088
+#define HMATRIX2_PRBS1				0x008c
+#define HMATRIX2_PRAS2				0x0090
+#define HMATRIX2_PRBS2				0x0094
+#define HMATRIX2_PRAS3				0x0098
+#define HMATRIX2_PRBS3				0x009c
+#define HMATRIX2_PRAS4				0x00a0
+#define HMATRIX2_PRBS4				0x00a4
+#define HMATRIX2_PRAS5				0x00a8
+#define HMATRIX2_PRBS5				0x00ac
+#define HMATRIX2_PRAS6				0x00b0
+#define HMATRIX2_PRBS6				0x00b4
+#define HMATRIX2_PRAS7				0x00b8
+#define HMATRIX2_PRBS7				0x00bc
+#define HMATRIX2_PRAS8				0x00c0
+#define HMATRIX2_PRBS8				0x00c4
+#define HMATRIX2_PRAS9				0x00c8
+#define HMATRIX2_PRBS9				0x00cc
+#define HMATRIX2_PRAS10				0x00d0
+#define HMATRIX2_PRBS10				0x00d4
+#define HMATRIX2_PRAS11				0x00d8
+#define HMATRIX2_PRBS11				0x00dc
+#define HMATRIX2_PRAS12				0x00e0
+#define HMATRIX2_PRBS12				0x00e4
+#define HMATRIX2_PRAS13				0x00e8
+#define HMATRIX2_PRBS13				0x00ec
+#define HMATRIX2_PRAS14				0x00f0
+#define HMATRIX2_PRBS14				0x00f4
+#define HMATRIX2_PRAS15				0x00f8
+#define HMATRIX2_PRBS15				0x00fc
+#define HMATRIX2_MRCR				0x0100
+#define HMATRIX2_SFR0				0x0110
+#define HMATRIX2_SFR1				0x0114
+#define HMATRIX2_SFR2				0x0118
+#define HMATRIX2_SFR3				0x011c
+#define HMATRIX2_SFR4				0x0120
+#define HMATRIX2_SFR5				0x0124
+#define HMATRIX2_SFR6				0x0128
+#define HMATRIX2_SFR7				0x012c
+#define HMATRIX2_SFR8				0x0130
+#define HMATRIX2_SFR9				0x0134
+#define HMATRIX2_SFR10				0x0138
+#define HMATRIX2_SFR11				0x013c
+#define HMATRIX2_SFR12				0x0140
+#define HMATRIX2_SFR13				0x0144
+#define HMATRIX2_SFR14				0x0148
+#define HMATRIX2_SFR15				0x014c
+#define HMATRIX2_VERSION			0x01fc
+
+/* Bitfields in MCFG0 */
+#define HMATRIX2_ULBT_OFFSET			0
+#define HMATRIX2_ULBT_SIZE			3
+
+/* Bitfields in SCFG0 */
+#define HMATRIX2_SLOT_CYCLE_OFFSET		0
+#define HMATRIX2_SLOT_CYCLE_SIZE		8
+#define HMATRIX2_DEFMSTR_TYPE_OFFSET		16
+#define HMATRIX2_DEFMSTR_TYPE_SIZE		2
+#define HMATRIX2_FIXED_DEFMSTR_OFFSET		18
+#define HMATRIX2_FIXED_DEFMSTR_SIZE		4
+#define HMATRIX2_ARBT_OFFSET			24
+#define HMATRIX2_ARBT_SIZE			2
+
+/* Bitfields in PRAS0 */
+#define HMATRIX2_M0PR_OFFSET			0
+#define HMATRIX2_M0PR_SIZE			4
+#define HMATRIX2_M1PR_OFFSET			4
+#define HMATRIX2_M1PR_SIZE			4
+#define HMATRIX2_M2PR_OFFSET			8
+#define HMATRIX2_M2PR_SIZE			4
+#define HMATRIX2_M3PR_OFFSET			12
+#define HMATRIX2_M3PR_SIZE			4
+#define HMATRIX2_M4PR_OFFSET			16
+#define HMATRIX2_M4PR_SIZE			4
+#define HMATRIX2_M5PR_OFFSET			20
+#define HMATRIX2_M5PR_SIZE			4
+#define HMATRIX2_M6PR_OFFSET			24
+#define HMATRIX2_M6PR_SIZE			4
+#define HMATRIX2_M7PR_OFFSET			28
+#define HMATRIX2_M7PR_SIZE			4
+
+/* Bitfields in PRBS0 */
+#define HMATRIX2_M8PR_OFFSET			0
+#define HMATRIX2_M8PR_SIZE			4
+#define HMATRIX2_M9PR_OFFSET			4
+#define HMATRIX2_M9PR_SIZE			4
+#define HMATRIX2_M10PR_OFFSET			8
+#define HMATRIX2_M10PR_SIZE			4
+#define HMATRIX2_M11PR_OFFSET			12
+#define HMATRIX2_M11PR_SIZE			4
+#define HMATRIX2_M12PR_OFFSET			16
+#define HMATRIX2_M12PR_SIZE			4
+#define HMATRIX2_M13PR_OFFSET			20
+#define HMATRIX2_M13PR_SIZE			4
+#define HMATRIX2_M14PR_OFFSET			24
+#define HMATRIX2_M14PR_SIZE			4
+#define HMATRIX2_M15PR_OFFSET			28
+#define HMATRIX2_M15PR_SIZE			4
+
+/* Bitfields in MRCR */
+#define HMATRIX2_RBC0_OFFSET			0
+#define HMATRIX2_RBC0_SIZE			1
+#define HMATRIX2_RBC1_OFFSET			1
+#define HMATRIX2_RBC1_SIZE			1
+#define HMATRIX2_RBC2_OFFSET			2
+#define HMATRIX2_RBC2_SIZE			1
+#define HMATRIX2_RBC3_OFFSET			3
+#define HMATRIX2_RBC3_SIZE			1
+#define HMATRIX2_RBC4_OFFSET			4
+#define HMATRIX2_RBC4_SIZE			1
+#define HMATRIX2_RBC5_OFFSET			5
+#define HMATRIX2_RBC5_SIZE			1
+#define HMATRIX2_RBC6_OFFSET			6
+#define HMATRIX2_RBC6_SIZE			1
+#define HMATRIX2_RBC7_OFFSET			7
+#define HMATRIX2_RBC7_SIZE			1
+#define HMATRIX2_RBC8_OFFSET			8
+#define HMATRIX2_RBC8_SIZE			1
+#define HMATRIX2_RBC9_OFFSET			9
+#define HMATRIX2_RBC9_SIZE			1
+#define HMATRIX2_RBC10_OFFSET			10
+#define HMATRIX2_RBC10_SIZE			1
+#define HMATRIX2_RBC11_OFFSET			11
+#define HMATRIX2_RBC11_SIZE			1
+#define HMATRIX2_RBC12_OFFSET			12
+#define HMATRIX2_RBC12_SIZE			1
+#define HMATRIX2_RBC13_OFFSET			13
+#define HMATRIX2_RBC13_SIZE			1
+#define HMATRIX2_RBC14_OFFSET			14
+#define HMATRIX2_RBC14_SIZE			1
+#define HMATRIX2_RBC15_OFFSET			15
+#define HMATRIX2_RBC15_SIZE			1
+
+/* Bitfields in SFR0 */
+#define HMATRIX2_SFR_OFFSET			0
+#define HMATRIX2_SFR_SIZE			32
+
+/* Bitfields in SFR4 */
+#define HMATRIX2_CS1A_OFFSET			1
+#define HMATRIX2_CS1A_SIZE			1
+#define HMATRIX2_CS3A_OFFSET			3
+#define HMATRIX2_CS3A_SIZE			1
+#define HMATRIX2_CS4A_OFFSET			4
+#define HMATRIX2_CS4A_SIZE			1
+#define HMATRIX2_CS5A_OFFSET			5
+#define HMATRIX2_CS5A_SIZE			1
+#define HMATRIX2_DBPUC_OFFSET			8
+#define HMATRIX2_DBPUC_SIZE			1
+
+/* Bitfields in VERSION */
+#define HMATRIX2_VERSION_OFFSET			0
+#define HMATRIX2_VERSION_SIZE			12
+#define HMATRIX2_MFN_OFFSET			16
+#define HMATRIX2_MFN_SIZE			3
+
+/* Constants for ULBT */
+#define HMATRIX2_ULBT_INFINITE			0
+#define HMATRIX2_ULBT_SINGLE			1
+#define HMATRIX2_ULBT_FOUR_BEAT			2
+#define HMATRIX2_ULBT_SIXTEEN_BEAT		4
+
+/* Constants for DEFMSTR_TYPE */
+#define HMATRIX2_DEFMSTR_TYPE_NO_DEFAULT	0
+#define HMATRIX2_DEFMSTR_TYPE_LAST_DEFAULT	1
+#define HMATRIX2_DEFMSTR_TYPE_FIXED_DEFAULT	2
+
+/* Constants for ARBT */
+#define HMATRIX2_ARBT_ROUND_ROBIN		0
+#define HMATRIX2_ARBT_FIXED_PRIORITY		1
+
+/* Bit manipulation macros */
+#define HMATRIX2_BIT(name)					\
+	(1 << HMATRIX2_##name##_OFFSET)
+#define HMATRIX2_BF(name,value)					\
+	(((value) & ((1 << HMATRIX2_##name##_SIZE) - 1))	\
+	 << HMATRIX2_##name##_OFFSET)
+#define HMATRIX2_BFEXT(name,value)				\
+	(((value) >> HMATRIX2_##name##_OFFSET)			\
+	 & ((1 << HMATRIX2_##name##_SIZE) - 1))
+#define HMATRIX2_BFINS(name,value,old)				\
+	(((old) & ~(((1 << HMATRIX2_##name##_SIZE) - 1)		\
+		    << HMATRIX2_##name##_OFFSET))		\
+	 | HMATRIX2_BF(name,value))
+
+/* Register access macros */
+#define hmatrix2_readl(port,reg)				\
+	readl((port)->regs + HMATRIX2_##reg)
+#define hmatrix2_writel(port,reg,value)				\
+	writel((value), (port)->regs + HMATRIX2_##reg)
+
+#endif /* __ASM_AVR32_HMATRIX2_H__ */
diff --git a/include/asm-avr32/arch-at32ap7000/memory-map.h b/include/asm-avr32/arch-at32ap7000/memory-map.h
new file mode 100644
index 0000000000..8ffe851c89
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap7000/memory-map.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_PART_MEMORY_MAP_H__
+#define __ASM_AVR32_PART_MEMORY_MAP_H__
+
+#define AUDIOC_BASE                             0xFFF02800
+#define DAC_BASE                                0xFFF02000
+#define DMAC_BASE                               0xFF200000
+#define ECC_BASE                                0xFFF03C00
+#define HISI_BASE                               0xFFF02C00
+#define HMATRIX_BASE                            0xFFF00800
+#define HSDRAMC_BASE                            0xFFF03800
+#define HSMC_BASE                               0xFFF03400
+#define LCDC_BASE                               0xFF000000
+#define MACB0_BASE                              0xFFF01800
+#define MACB1_BASE                              0xFFF01C00
+#define MMCI_BASE                               0xFFF02400
+#define PIOA_BASE                               0xFFE02800
+#define PIOB_BASE                               0xFFE02C00
+#define PIOC_BASE                               0xFFE03000
+#define PIOD_BASE                               0xFFE03400
+#define PIOE_BASE                               0xFFE03800
+#define PSIF_BASE                               0xFFE03C00
+#define PWM_BASE                                0xFFF01400
+#define SM_BASE                                 0xFFF00000
+#define INTC_BASE				0XFFF00400
+#define SPI0_BASE                               0xFFE00000
+#define SPI1_BASE                               0xFFE00400
+#define SSC0_BASE                               0xFFE01C00
+#define SSC1_BASE                               0xFFE02000
+#define SSC2_BASE                               0xFFE02400
+#define TIMER0_BASE                             0xFFF00C00
+#define TIMER1_BASE                             0xFFF01000
+#define TWI_BASE                                0xFFE00800
+#define USART0_BASE                             0xFFE00C00
+#define USART1_BASE                             0xFFE01000
+#define USART2_BASE                             0xFFE01400
+#define USART3_BASE                             0xFFE01800
+#define USB_FIFO                                0xFF300000
+#define USB_BASE                                0xFFF03000
+
+#endif /* __ASM_AVR32_PART_MEMORY_MAP_H__ */
diff --git a/include/asm-avr32/arch-at32ap7000/platform.h b/include/asm-avr32/arch-at32ap7000/platform.h
new file mode 100644
index 0000000000..759050116a
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap7000/platform.h
@@ -0,0 +1,146 @@
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _ASM_AVR32_ARCH_PM_H
+#define _ASM_AVR32_ARCH_PM_H
+
+#include <config.h>
+
+enum clock_domain_id {
+	CLOCK_CPU,
+	CLOCK_HSB,
+	CLOCK_PBA,
+	CLOCK_PBB,
+	NR_CLOCK_DOMAINS,
+};
+
+enum resource_type {
+	RESOURCE_GPIO,
+	RESOURCE_CLOCK,
+};
+
+enum gpio_func {
+	GPIO_FUNC_GPIO,
+	GPIO_FUNC_A,
+	GPIO_FUNC_B,
+};
+
+enum device_id {
+	DEVICE_HEBI,
+	DEVICE_PBA_BRIDGE,
+	DEVICE_PBB_BRIDGE,
+	DEVICE_HRAMC,
+	/* GPIO controllers must be kept together */
+	DEVICE_PIOA,
+	DEVICE_PIOB,
+	DEVICE_PIOC,
+	DEVICE_PIOD,
+	DEVICE_PIOE,
+	DEVICE_SM,
+	DEVICE_INTC,
+	DEVICE_HMATRIX,
+#if defined(CFG_HPDC)
+	DEVICE_HPDC,
+#endif
+#if defined(CFG_MACB0)
+	DEVICE_MACB0,
+#endif
+#if defined(CFG_MACB1)
+	DEVICE_MACB1,
+#endif
+#if defined(CFG_LCDC)
+	DEVICE_LCDC,
+#endif
+#if defined(CFG_USART0)
+	DEVICE_USART0,
+#endif
+#if defined(CFG_USART1)
+	DEVICE_USART1,
+#endif
+#if defined(CFG_USART2)
+	DEVICE_USART2,
+#endif
+#if defined(CFG_USART3)
+	DEVICE_USART3,
+#endif
+#if defined(CFG_MMCI)
+	DEVICE_MMCI,
+#endif
+#if defined(CFG_DMAC)
+	DEVICE_DMAC,
+#endif
+	NR_DEVICES,
+	NO_DEVICE = -1,
+};
+
+struct resource {
+	enum resource_type type;
+	union {
+		struct {
+			unsigned long base;
+		} iomem;
+		struct {
+			unsigned char nr_pins;
+			enum device_id gpio_dev;
+			enum gpio_func func;
+			unsigned short start;
+		} gpio;
+		struct {
+			enum clock_domain_id id;
+			unsigned char index;
+		} clock;
+	} u;
+};
+
+struct device {
+	void *regs;
+	unsigned int nr_resources;
+	const struct resource *resource;
+};
+
+struct clock_domain {
+	unsigned short reg;
+	enum clock_domain_id id;
+	enum device_id bridge;
+};
+
+extern const struct device chip_device[NR_DEVICES];
+extern const struct clock_domain chip_clock[NR_CLOCK_DOMAINS];
+
+/**
+ * Set up PIO, clock management and I/O memory for a device.
+ */
+const struct device *get_device(enum device_id devid);
+void put_device(const struct device *dev);
+
+int gpio_set_func(enum device_id gpio_devid, unsigned int start,
+		  unsigned int nr_pins, enum gpio_func func);
+void gpio_free(enum device_id gpio_devid, unsigned int start,
+	       unsigned int nr_pins);
+
+void pm_init(void);
+int pm_enable_clock(enum clock_domain_id id, unsigned int index);
+void pm_disable_clock(enum clock_domain_id id, unsigned int index);
+unsigned long pm_get_clock_freq(enum clock_domain_id domain);
+
+void cpu_enable_sdram(void);
+
+#endif /* _ASM_AVR32_ARCH_PM_H */
diff --git a/include/asm-avr32/bitops.h b/include/asm-avr32/bitops.h
new file mode 100644
index 0000000000..f15fd4647e
--- /dev/null
+++ b/include/asm-avr32/bitops.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_BITOPS_H
+#define __ASM_AVR32_BITOPS_H
+
+#endif /* __ASM_AVR32_BITOPS_H */
diff --git a/include/asm-avr32/byteorder.h b/include/asm-avr32/byteorder.h
new file mode 100644
index 0000000000..2fe867e978
--- /dev/null
+++ b/include/asm-avr32/byteorder.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_BYTEORDER_H
+#define __ASM_AVR32_BYTEORDER_H
+
+#include <asm/types.h>
+
+#define __arch__swab32(x) __builtin_bswap_32(x)
+#define __arch__swab16(x) __builtin_bswap_16(x)
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+# define __BYTEORDER_HAS_U64__
+# define __SWAB_64_THRU_32__
+#endif
+
+#include <linux/byteorder/big_endian.h>
+
+#endif /* __ASM_AVR32_BYTEORDER_H */
diff --git a/include/asm-avr32/cacheflush.h b/include/asm-avr32/cacheflush.h
new file mode 100644
index 0000000000..929f68e1a0
--- /dev/null
+++ b/include/asm-avr32/cacheflush.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_CACHEFLUSH_H
+#define __ASM_AVR32_CACHEFLUSH_H
+
+/*
+ * Invalidate any cacheline containing virtual address vaddr without
+ * writing anything back to memory.
+ *
+ * Note that this function may corrupt unrelated data structures when
+ * applied on buffers that are not cacheline aligned in both ends.
+ */
+static inline void dcache_invalidate_line(volatile void *vaddr)
+{
+	asm volatile("cache %0[0], 0x0b" : : "r"(vaddr) : "memory");
+}
+
+/*
+ * Make sure any cacheline containing virtual address vaddr is written
+ * to memory.
+ */
+static inline void dcache_clean_line(volatile void *vaddr)
+{
+	asm volatile("cache %0[0], 0x0c" : : "r"(vaddr) : "memory");
+}
+
+/*
+ * Make sure any cacheline containing virtual address vaddr is written
+ * to memory and then invalidate it.
+ */
+static inline void dcache_flush_line(volatile void *vaddr)
+{
+	asm volatile("cache %0[0], 0x0d" : : "r"(vaddr) : "memory");
+}
+
+/*
+ * Invalidate any instruction cacheline containing virtual address
+ * vaddr.
+ */
+static inline void icache_invalidate_line(volatile void *vaddr)
+{
+	asm volatile("cache %0[0], 0x01" : : "r"(vaddr) : "memory");
+}
+
+/*
+ * Applies the above functions on all lines that are touched by the
+ * specified virtual address range.
+ */
+void dcache_invalidate_range(volatile void *start, size_t len);
+void dcache_clean_range(volatile void *start, size_t len);
+void dcache_flush_range(volatile void *start, size_t len);
+void icache_invalidate_range(volatile void *start, size_t len);
+
+static inline void dcache_flush_unlocked(void)
+{
+	asm volatile("cache %0[5], 0x08" : : "r"(0) : "memory");
+}
+
+/*
+ * Make sure any pending writes are completed before continuing.
+ */
+#define sync_write_buffer() asm volatile("sync 0" : : : "memory")
+
+#endif /* __ASM_AVR32_CACHEFLUSH_H */
diff --git a/include/asm-avr32/div64.h b/include/asm-avr32/div64.h
new file mode 100644
index 0000000000..2e0ba8389e
--- /dev/null
+++ b/include/asm-avr32/div64.h
@@ -0,0 +1,39 @@
+#ifndef _ASM_GENERIC_DIV64_H
+#define _ASM_GENERIC_DIV64_H
+/*
+ * Copyright (C) 2003 Bernardo Innocenti <bernie@develer.com>
+ * Based on former asm-ppc/div64.h and asm-m68knommu/div64.h
+ *
+ * The semantics of do_div() are:
+ *
+ * uint32_t do_div(uint64_t *n, uint32_t base)
+ * {
+ * 	uint32_t remainder = *n % base;
+ * 	*n = *n / base;
+ * 	return remainder;
+ * }
+ *
+ * NOTE: macro parameter n is evaluated multiple times,
+ *       beware of side effects!
+ */
+
+#include <linux/types.h>
+
+extern uint32_t __div64_32(uint64_t *dividend, uint32_t divisor);
+
+/* The unnecessary pointer compare is there
+ * to check for type safety (n must be 64bit)
+ */
+# define do_div(n,base) ({				\
+	uint32_t __base = (base);			\
+	uint32_t __rem;					\
+	(void)(((typeof((n)) *)0) == ((uint64_t *)0));	\
+	if (((n) >> 32) == 0) {			\
+		__rem = (uint32_t)(n) % __base;		\
+		(n) = (uint32_t)(n) / __base;		\
+	} else 						\
+		__rem = __div64_32(&(n), __base);	\
+	__rem;						\
+ })
+
+#endif /* _ASM_GENERIC_DIV64_H */
diff --git a/include/asm-avr32/dma-mapping.h b/include/asm-avr32/dma-mapping.h
new file mode 100644
index 0000000000..3b46fa3e62
--- /dev/null
+++ b/include/asm-avr32/dma-mapping.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_DMA_MAPPING_H
+#define __ASM_AVR32_DMA_MAPPING_H
+
+#include <asm/io.h>
+#include <asm/cacheflush.h>
+
+enum dma_data_direction {
+	DMA_BIDIRECTIONAL	= 0,
+	DMA_TO_DEVICE		= 1,
+	DMA_FROM_DEVICE		= 2,
+};
+extern void *dma_alloc_coherent(size_t len, unsigned long *handle);
+
+static inline unsigned long dma_map_single(volatile void *vaddr, size_t len,
+					   enum dma_data_direction dir)
+{
+	extern void __bad_dma_data_direction(void);
+
+	switch (dir) {
+	case DMA_BIDIRECTIONAL:
+		dcache_flush_range(vaddr, len);
+		break;
+	case DMA_TO_DEVICE:
+		dcache_clean_range(vaddr, len);
+		break;
+	case DMA_FROM_DEVICE:
+		dcache_invalidate_range(vaddr, len);
+		break;
+	default:
+		/* This will cause a linker error */
+		__bad_dma_data_direction();
+	}
+
+	return virt_to_phys(vaddr);
+}
+
+static inline void dma_unmap_single(volatile void *vaddr, size_t len,
+				    unsigned long paddr)
+{
+
+}
+
+#endif /* __ASM_AVR32_DMA_MAPPING_H */
diff --git a/include/asm-avr32/errno.h b/include/asm-avr32/errno.h
new file mode 100644
index 0000000000..ea3506ff38
--- /dev/null
+++ b/include/asm-avr32/errno.h
@@ -0,0 +1,132 @@
+#ifndef _ASM_AVR32_ERRNO_H
+#define _ASM_AVR32_ERRNO_H
+
+#define	EPERM		 1	/* Operation not permitted */
+#define	ENOENT		 2	/* No such file or directory */
+#define	ESRCH		 3	/* No such process */
+#define	EINTR		 4	/* Interrupted system call */
+#define	EIO		 5	/* I/O error */
+#define	ENXIO		 6	/* No such device or address */
+#define	E2BIG		 7	/* Argument list too long */
+#define	ENOEXEC		 8	/* Exec format error */
+#define	EBADF		 9	/* Bad file number */
+#define	ECHILD		10	/* No child processes */
+#define	EAGAIN		11	/* Try again */
+#define	ENOMEM		12	/* Out of memory */
+#define	EACCES		13	/* Permission denied */
+#define	EFAULT		14	/* Bad address */
+#define	ENOTBLK		15	/* Block device required */
+#define	EBUSY		16	/* Device or resource busy */
+#define	EEXIST		17	/* File exists */
+#define	EXDEV		18	/* Cross-device link */
+#define	ENODEV		19	/* No such device */
+#define	ENOTDIR		20	/* Not a directory */
+#define	EISDIR		21	/* Is a directory */
+#define	EINVAL		22	/* Invalid argument */
+#define	ENFILE		23	/* File table overflow */
+#define	EMFILE		24	/* Too many open files */
+#define	ENOTTY		25	/* Not a typewriter */
+#define	ETXTBSY		26	/* Text file busy */
+#define	EFBIG		27	/* File too large */
+#define	ENOSPC		28	/* No space left on device */
+#define	ESPIPE		29	/* Illegal seek */
+#define	EROFS		30	/* Read-only file system */
+#define	EMLINK		31	/* Too many links */
+#define	EPIPE		32	/* Broken pipe */
+#define	EDOM		33	/* Math argument out of domain of func */
+#define	ERANGE		34	/* Math result not representable */
+#define	EDEADLK		35	/* Resource deadlock would occur */
+#define	ENAMETOOLONG	36	/* File name too long */
+#define	ENOLCK		37	/* No record locks available */
+#define	ENOSYS		38	/* Function not implemented */
+#define	ENOTEMPTY	39	/* Directory not empty */
+#define	ELOOP		40	/* Too many symbolic links encountered */
+#define	EWOULDBLOCK	EAGAIN	/* Operation would block */
+#define	ENOMSG		42	/* No message of desired type */
+#define	EIDRM		43	/* Identifier removed */
+#define	ECHRNG		44	/* Channel number out of range */
+#define	EL2NSYNC	45	/* Level 2 not synchronized */
+#define	EL3HLT		46	/* Level 3 halted */
+#define	EL3RST		47	/* Level 3 reset */
+#define	ELNRNG		48	/* Link number out of range */
+#define	EUNATCH		49	/* Protocol driver not attached */
+#define	ENOCSI		50	/* No CSI structure available */
+#define	EL2HLT		51	/* Level 2 halted */
+#define	EBADE		52	/* Invalid exchange */
+#define	EBADR		53	/* Invalid request descriptor */
+#define	EXFULL		54	/* Exchange full */
+#define	ENOANO		55	/* No anode */
+#define	EBADRQC		56	/* Invalid request code */
+#define	EBADSLT		57	/* Invalid slot */
+
+#define	EDEADLOCK	EDEADLK
+
+#define	EBFONT		59	/* Bad font file format */
+#define	ENOSTR		60	/* Device not a stream */
+#define	ENODATA		61	/* No data available */
+#define	ETIME		62	/* Timer expired */
+#define	ENOSR		63	/* Out of streams resources */
+#define	ENONET		64	/* Machine is not on the network */
+#define	ENOPKG		65	/* Package not installed */
+#define	EREMOTE		66	/* Object is remote */
+#define	ENOLINK		67	/* Link has been severed */
+#define	EADV		68	/* Advertise error */
+#define	ESRMNT		69	/* Srmount error */
+#define	ECOMM		70	/* Communication error on send */
+#define	EPROTO		71	/* Protocol error */
+#define	EMULTIHOP	72	/* Multihop attempted */
+#define	EDOTDOT		73	/* RFS specific error */
+#define	EBADMSG		74	/* Not a data message */
+#define	EOVERFLOW	75	/* Value too large for defined data type */
+#define	ENOTUNIQ	76	/* Name not unique on network */
+#define	EBADFD		77	/* File descriptor in bad state */
+#define	EREMCHG		78	/* Remote address changed */
+#define	ELIBACC		79	/* Can not access a needed shared library */
+#define	ELIBBAD		80	/* Accessing a corrupted shared library */
+#define	ELIBSCN		81	/* .lib section in a.out corrupted */
+#define	ELIBMAX		82	/* Attempting to link in too many shared libraries */
+#define	ELIBEXEC	83	/* Cannot exec a shared library directly */
+#define	EILSEQ		84	/* Illegal byte sequence */
+#define	ERESTART	85	/* Interrupted system call should be restarted */
+#define	ESTRPIPE	86	/* Streams pipe error */
+#define	EUSERS		87	/* Too many users */
+#define	ENOTSOCK	88	/* Socket operation on non-socket */
+#define	EDESTADDRREQ	89	/* Destination address required */
+#define	EMSGSIZE	90	/* Message too long */
+#define	EPROTOTYPE	91	/* Protocol wrong type for socket */
+#define	ENOPROTOOPT	92	/* Protocol not available */
+#define	EPROTONOSUPPORT	93	/* Protocol not supported */
+#define	ESOCKTNOSUPPORT	94	/* Socket type not supported */
+#define	EOPNOTSUPP	95	/* Operation not supported on transport endpoint */
+#define	EPFNOSUPPORT	96	/* Protocol family not supported */
+#define	EAFNOSUPPORT	97	/* Address family not supported by protocol */
+#define	EADDRINUSE	98	/* Address already in use */
+#define	EADDRNOTAVAIL	99	/* Cannot assign requested address */
+#define	ENETDOWN	100	/* Network is down */
+#define	ENETUNREACH	101	/* Network is unreachable */
+#define	ENETRESET	102	/* Network dropped connection because of reset */
+#define	ECONNABORTED	103	/* Software caused connection abort */
+#define	ECONNRESET	104	/* Connection reset by peer */
+#define	ENOBUFS		105	/* No buffer space available */
+#define	EISCONN		106	/* Transport endpoint is already connected */
+#define	ENOTCONN	107	/* Transport endpoint is not connected */
+#define	ESHUTDOWN	108	/* Cannot send after transport endpoint shutdown */
+#define	ETOOMANYREFS	109	/* Too many references: cannot splice */
+#define	ETIMEDOUT	110	/* Connection timed out */
+#define	ECONNREFUSED	111	/* Connection refused */
+#define	EHOSTDOWN	112	/* Host is down */
+#define	EHOSTUNREACH	113	/* No route to host */
+#define	EALREADY	114	/* Operation already in progress */
+#define	EINPROGRESS	115	/* Operation now in progress */
+#define	ESTALE		116	/* Stale NFS file handle */
+#define	EUCLEAN		117	/* Structure needs cleaning */
+#define	ENOTNAM		118	/* Not a XENIX named type file */
+#define	ENAVAIL		119	/* No XENIX semaphores available */
+#define	EISNAM		120	/* Is a named type file */
+#define	EREMOTEIO	121	/* Remote I/O error */
+#define	EDQUOT		122	/* Quota exceeded */
+
+#define	ENOMEDIUM	123	/* No medium found */
+#define	EMEDIUMTYPE	124	/* Wrong medium type */
+
+#endif /* _ASM_AVR32_ERRNO_H */
diff --git a/include/asm-avr32/global_data.h b/include/asm-avr32/global_data.h
new file mode 100644
index 0000000000..01d836c639
--- /dev/null
+++ b/include/asm-avr32/global_data.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_GLOBAL_DATA_H__
+#define __ASM_GLOBAL_DATA_H__
+
+/*
+ * The following data structure is placed in some memory wich is
+ * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
+ * some locked parts of the data cache) to allow for a minimum set of
+ * global variables during system initialization (until we have set
+ * up the memory controller so that we can use RAM).
+ *
+ * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t)
+ */
+
+typedef	struct	global_data {
+	bd_t		*bd;
+	unsigned long	flags;
+	const struct device	*console_uart;
+	const struct device	*sm;
+	unsigned long	baudrate;
+	unsigned long	sdram_size;
+	unsigned long	have_console;	/* serial_init() was called */
+	unsigned long	reloc_off;	/* Relocation Offset */
+	unsigned long	env_addr;	/* Address of env struct */
+	unsigned long	env_valid;	/* Checksum of env valid? */
+	unsigned long	cpu_hz;		/* cpu core clock frequency */
+	void		**jt;		/* jump table */
+} gd_t;
+
+/*
+ * Global Data Flags
+ */
+#define GD_FLG_RELOC	0x00001		/* Code was relocated to RAM	 */
+#define GD_FLG_DEVINIT	0x00002		/* Devices have been initialized */
+#define GD_FLG_SILENT	0x00004		/* Silent mode			 */
+
+#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm("r5")
+
+#endif /* __ASM_GLOBAL_DATA_H__ */
diff --git a/include/asm-avr32/initcalls.h b/include/asm-avr32/initcalls.h
new file mode 100644
index 0000000000..7ba25cde53
--- /dev/null
+++ b/include/asm-avr32/initcalls.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2005, 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_INITCALLS_H__
+#define __ASM_AVR32_INITCALLS_H__
+
+#include <config.h>
+
+extern int cpu_init(void);
+extern int timer_init(void);
+extern void board_init_memories(void);
+extern void board_init_pio(void);
+extern void board_init_info(void);
+
+#endif /* __ASM_AVR32_INITCALLS_H__ */
diff --git a/include/asm-avr32/io.h b/include/asm-avr32/io.h
new file mode 100644
index 0000000000..e86c456ae1
--- /dev/null
+++ b/include/asm-avr32/io.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_IO_H
+#define __ASM_AVR32_IO_H
+
+#ifdef __KERNEL__
+
+/*
+ * Generic IO read/write.  These perform native-endian accesses.  Note
+ * that some architectures will want to re-define __raw_{read,write}w.
+ */
+extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
+extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
+extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
+
+extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
+extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
+extern void __raw_readsl(unsigned int addr, void *data, int longlen);
+
+#define __raw_writeb(v,a)       (*(volatile unsigned char  *)(a) = (v))
+#define __raw_writew(v,a)       (*(volatile unsigned short *)(a) = (v))
+#define __raw_writel(v,a)       (*(volatile unsigned int   *)(a) = (v))
+
+#define __raw_readb(a)          (*(volatile unsigned char  *)(a))
+#define __raw_readw(a)          (*(volatile unsigned short *)(a))
+#define __raw_readl(a)          (*(volatile unsigned int   *)(a))
+
+/* As long as I/O is only performed in P4 (or possibly P3), we're safe */
+#define writeb(v,a)		__raw_writeb(v,a)
+#define writew(v,a)		__raw_writew(v,a)
+#define writel(v,a)		__raw_writel(v,a)
+
+#define readb(a)		__raw_readb(a)
+#define readw(a)		__raw_readw(a)
+#define readl(a)		__raw_readl(a)
+
+/*
+ * Bad read/write accesses...
+ */
+extern void __readwrite_bug(const char *fn);
+
+#define IO_SPACE_LIMIT	0xffffffff
+
+/*
+ * All I/O is memory mapped, so these macros doesn't make very much sense
+ */
+#define outb(v,p)		__raw_writeb(v, p)
+#define outw(v,p)		__raw_writew(cpu_to_le16(v),p)
+#define outl(v,p)		__raw_writel(cpu_to_le32(v),p)
+
+#define inb(p)	({ unsigned int __v = __raw_readb(p); __v; })
+#define inw(p)	({ unsigned int __v = __le16_to_cpu(__raw_readw(p)); __v; })
+#define inl(p)	({ unsigned int __v = __le32_to_cpu(__raw_readl(p)); __v; })
+
+#include <asm/addrspace.h>
+
+/* virt_to_phys will only work when address is in P1 or P2 */
+static __inline__ unsigned long virt_to_phys(volatile void *address)
+{
+	return PHYSADDR(address);
+}
+
+static __inline__ void * phys_to_virt(unsigned long address)
+{
+	return (void *)P1SEGADDR(address);
+}
+
+#define cached(addr) ((void *)P1SEGADDR(addr))
+#define uncached(addr) ((void *)P2SEGADDR(addr))
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_AVR32_IO_H */
diff --git a/include/asm-avr32/posix_types.h b/include/asm-avr32/posix_types.h
new file mode 100644
index 0000000000..edf1bc14d2
--- /dev/null
+++ b/include/asm-avr32/posix_types.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_POSIX_TYPES_H
+#define __ASM_AVR32_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned long	__kernel_dev_t;
+typedef unsigned long	__kernel_ino_t;
+typedef unsigned short	__kernel_mode_t;
+typedef unsigned short	__kernel_nlink_t;
+typedef long		__kernel_off_t;
+typedef int		__kernel_pid_t;
+typedef unsigned short	__kernel_ipc_pid_t;
+typedef unsigned int	__kernel_uid_t;
+typedef unsigned int	__kernel_gid_t;
+typedef unsigned long	__kernel_size_t;
+typedef int		__kernel_ssize_t;
+typedef int		__kernel_ptrdiff_t;
+typedef long		__kernel_time_t;
+typedef long		__kernel_suseconds_t;
+typedef long		__kernel_clock_t;
+typedef int		__kernel_timer_t;
+typedef int		__kernel_clockid_t;
+typedef int		__kernel_daddr_t;
+typedef char *		__kernel_caddr_t;
+typedef unsigned short	__kernel_uid16_t;
+typedef unsigned short	__kernel_gid16_t;
+typedef unsigned int	__kernel_uid32_t;
+typedef unsigned int	__kernel_gid32_t;
+
+typedef unsigned short	__kernel_old_uid_t;
+typedef unsigned short	__kernel_old_gid_t;
+typedef unsigned short	__kernel_old_dev_t;
+
+#ifdef __GNUC__
+typedef long long	__kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+	int	val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+	int	__val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__)
+
+#undef  __FD_SET
+static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+	unsigned long __tmp = __fd / __NFDBITS;
+	unsigned long __rem = __fd % __NFDBITS;
+	__fdsetp->fds_bits[__tmp] |= (1UL<<__rem);
+}
+
+#undef  __FD_CLR
+static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+	unsigned long __tmp = __fd / __NFDBITS;
+	unsigned long __rem = __fd % __NFDBITS;
+	__fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem);
+}
+
+
+#undef  __FD_ISSET
+static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p)
+{
+	unsigned long __tmp = __fd / __NFDBITS;
+	unsigned long __rem = __fd % __NFDBITS;
+	return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0;
+}
+
+/*
+ * This will unroll the loop for the normal constant case (8 ints,
+ * for a 256-bit fd_set)
+ */
+#undef  __FD_ZERO
+static __inline__ void __FD_ZERO(__kernel_fd_set *__p)
+{
+	unsigned long *__tmp = __p->fds_bits;
+	int __i;
+
+	if (__builtin_constant_p(__FDSET_LONGS)) {
+		switch (__FDSET_LONGS) {
+		case 16:
+			__tmp[ 0] = 0; __tmp[ 1] = 0;
+			__tmp[ 2] = 0; __tmp[ 3] = 0;
+			__tmp[ 4] = 0; __tmp[ 5] = 0;
+			__tmp[ 6] = 0; __tmp[ 7] = 0;
+			__tmp[ 8] = 0; __tmp[ 9] = 0;
+			__tmp[10] = 0; __tmp[11] = 0;
+			__tmp[12] = 0; __tmp[13] = 0;
+			__tmp[14] = 0; __tmp[15] = 0;
+			return;
+
+		case 8:
+			__tmp[ 0] = 0; __tmp[ 1] = 0;
+			__tmp[ 2] = 0; __tmp[ 3] = 0;
+			__tmp[ 4] = 0; __tmp[ 5] = 0;
+			__tmp[ 6] = 0; __tmp[ 7] = 0;
+			return;
+
+		case 4:
+			__tmp[ 0] = 0; __tmp[ 1] = 0;
+			__tmp[ 2] = 0; __tmp[ 3] = 0;
+			return;
+		}
+	}
+	__i = __FDSET_LONGS;
+	while (__i) {
+		__i--;
+		*__tmp = 0;
+		__tmp++;
+	}
+}
+
+#endif /* defined(__KERNEL__) */
+
+#endif /* __ASM_AVR32_POSIX_TYPES_H */
diff --git a/include/asm-avr32/processor.h b/include/asm-avr32/processor.h
new file mode 100644
index 0000000000..cc59dfad56
--- /dev/null
+++ b/include/asm-avr32/processor.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_PROCESSOR_H
+#define __ASM_AVR32_PROCESSOR_H
+
+#ifndef __ASSEMBLY__
+
+#define current_text_addr() ({ void *pc; __asm__("mov %0,pc" : "=r"(pc)); pc; })
+
+struct avr32_cpuinfo {
+	unsigned long loops_per_jiffy;
+};
+
+extern struct avr32_cpuinfo boot_cpu_data;
+
+#ifdef CONFIG_SMP
+extern struct avr32_cpuinfo cpu_data[];
+#define current_cpu_data cpu_data[smp_processor_id()]
+#else
+#define cpu_data (&boot_cpu_data)
+#define current_cpu_data boot_cpu_data
+#endif
+
+/* TODO: Make configurable (2GB will serve as a reasonable default) */
+#define TASK_SIZE	0x80000000
+
+/* This decides where the kernel will search for a free chunk of vm
+ * space during mmap's
+ */
+#define TASK_UNMAPPED_BASE	(TASK_SIZE / 3)
+
+#define cpu_relax()		barrier()
+#define cpu_sync_pipeline()	asm volatile("sub pc, -2" : : : "memory")
+
+/* This struct contains the CPU context as stored by switch_to() */
+struct thread_struct {
+	unsigned long pc;
+	unsigned long ksp;	/* Kernel stack pointer */
+	unsigned long r7;
+	unsigned long r6;
+	unsigned long r5;
+	unsigned long r4;
+	unsigned long r3;
+	unsigned long r2;
+	unsigned long r1;
+	unsigned long r0;
+};
+
+#define INIT_THREAD {						\
+	.ksp = sizeof(init_stack) + (long)&init_stack,		\
+}
+
+/*
+ * Do necessary setup to start up a newly executed thread.
+ */
+#define start_thread(regs, new_pc, new_sp)	 \
+	set_fs(USER_DS);			 \
+	regs->sr = 0;		/* User mode. */ \
+	regs->gr[REG_PC] = new_pc;		 \
+	regs->gr[REG_SP] = new_sp
+
+struct task_struct;
+
+/* Free all resources held by a thread */
+extern void release_thread(struct task_struct *);
+
+/* Create a kernel thread without removing it from tasklists */
+extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
+
+/* Prepare to copy thread state - unlazy all lazy status */
+#define prepare_to_copy(tsk) do { } while(0)
+
+/* Return saved PC of a blocked thread */
+#define thread_saved_pc(tsk)    (tsk->thread.pc)
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_AVR32_PROCESSOR_H */
diff --git a/include/asm-avr32/ptrace.h b/include/asm-avr32/ptrace.h
new file mode 100644
index 0000000000..c770ba02c3
--- /dev/null
+++ b/include/asm-avr32/ptrace.h
@@ -0,0 +1,148 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_PTRACE_H
+#define __ASM_AVR32_PTRACE_H
+
+/*
+ * Status Register bits
+ */
+#define SR_H		0x40000000
+#define SR_R		0x20000000
+#define SR_J		0x10000000
+#define SR_DM		0x08000000
+#define SR_D		0x04000000
+#define MODE_NMI	0x01c00000
+#define MODE_EXCEPTION	0x01800000
+#define MODE_INT3	0x01400000
+#define MODE_INT2	0x01000000
+#define MODE_INT1	0x00c00000
+#define MODE_INT0	0x00800000
+#define MODE_SUPERVISOR	0x00400000
+#define MODE_USER	0x00000000
+#define MODE_MASK	0x01c00000
+#define SR_EM		0x00200000
+#define SR_I3M		0x00100000
+#define SR_I2M		0x00080000
+#define SR_I1M		0x00040000
+#define SR_I0M		0x00020000
+#define SR_GM		0x00010000
+
+#define MODE_SHIFT	22
+#define SR_EM_BIT	21
+#define SR_I3M_BIT	20
+#define SR_I2M_BIT	19
+#define SR_I1M_BIT	18
+#define SR_I0M_BIT	17
+#define SR_GM_BIT	16
+
+/* The user-visible part */
+#define SR_Q		0x00000010
+#define SR_V		0x00000008
+#define SR_N		0x00000004
+#define SR_Z		0x00000002
+#define SR_C		0x00000001
+
+/*
+ * The order is defined by the stdsp instruction. r0 is stored first, so it
+ * gets the highest address.
+ *
+ * Registers 0-12 are general-purpose registers (r12 is normally used for
+ * the function return value).
+ * Register 13 is the stack pointer
+ * Register 14 is the link register
+ * Register 15 is the program counter
+ */
+#define FRAME_SIZE_FULL 72
+#define REG_R12_ORIG	68
+#define REG_R0		64
+#define REG_R1		60
+#define REG_R2		56
+#define REG_R3		52
+#define REG_R4		48
+#define REG_R5		44
+#define REG_R6		40
+#define REG_R7		36
+#define REG_R8		32
+#define REG_R9		28
+#define REG_R10		34
+#define REG_R11		20
+#define REG_R12		16
+#define REG_SP		12
+#define REG_LR		 8
+
+#define FRAME_SIZE_MIN	 8
+#define REG_PC		 4
+#define REG_SR		 0
+
+#ifndef __ASSEMBLY__
+struct pt_regs {
+	/* These are always saved */
+	unsigned long sr;
+	unsigned long pc;
+
+	/* These are sometimes saved */
+	unsigned long lr;
+	unsigned long sp;
+	unsigned long r12;
+	unsigned long r11;
+	unsigned long r10;
+	unsigned long r9;
+	unsigned long r8;
+	unsigned long r7;
+	unsigned long r6;
+	unsigned long r5;
+	unsigned long r4;
+	unsigned long r3;
+	unsigned long r2;
+	unsigned long r1;
+	unsigned long r0;
+
+	/* Only saved on system call */
+	unsigned long r12_orig;
+};
+
+#ifdef __KERNEL__
+# define user_mode(regs) (((regs)->sr & MODE_MASK) == MODE_USER)
+# define instruction_pointer(regs) ((regs)->pc)
+extern void show_regs (struct pt_regs *);
+
+static __inline__ int valid_user_regs(struct pt_regs *regs)
+{
+	/*
+	 * Some of the Java bits might be acceptable if/when we
+	 * implement some support for that stuff...
+	 */
+	if ((regs->sr & 0xffff0000) == 0)
+		return 1;
+
+	/*
+	 * Force status register flags to be sane and report this
+	 * illegal behaviour...
+	 */
+	regs->sr &= 0x0000ffff;
+	return 0;
+}
+#endif
+
+#endif /* ! __ASSEMBLY__ */
+
+#endif /* __ASM_AVR32_PTRACE_H */
diff --git a/include/asm-avr32/sdram.h b/include/asm-avr32/sdram.h
new file mode 100644
index 0000000000..5057eefa8a
--- /dev/null
+++ b/include/asm-avr32/sdram.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_SDRAM_H
+#define __ASM_AVR32_SDRAM_H
+
+struct sdram_info {
+	unsigned long phys_addr;
+	unsigned int row_bits, col_bits, bank_bits;
+	unsigned int cas, twr, trc, trp, trcd, tras, txsr;
+};
+
+extern unsigned long sdram_init(const struct sdram_info *info);
+
+#endif /* __ASM_AVR32_SDRAM_H */
diff --git a/include/asm-avr32/sections.h b/include/asm-avr32/sections.h
new file mode 100644
index 0000000000..75373abde7
--- /dev/null
+++ b/include/asm-avr32/sections.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_SECTIONS_H
+#define __ASM_AVR32_SECTIONS_H
+
+/* References to section boundaries */
+
+extern char _text[], _etext[];
+extern char __flashprog_start[], __flashprog_end[];
+extern char _data[], __data_lma[], _edata[], __edata_lma[];
+extern char __got_start[], __got_lma[], __got_end[];
+extern char _end[];
+
+/*
+ * Everything in .flashprog will be locked in the icache so it doesn't
+ * get disturbed when executing flash commands.
+ */
+#define __flashprog __attribute__((section(".flashprog"), __noinline__))
+
+#endif /* __ASM_AVR32_SECTIONS_H */
diff --git a/include/asm-avr32/setup.h b/include/asm-avr32/setup.h
new file mode 100644
index 0000000000..e6ef8d6b50
--- /dev/null
+++ b/include/asm-avr32/setup.h
@@ -0,0 +1,142 @@
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * Based on linux/include/asm-arm/setup.h
+ *   Copyright (C) 1997-1999 Russel King
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_SETUP_H__
+#define __ASM_AVR32_SETUP_H__
+
+#define COMMAND_LINE_SIZE 256
+
+/* Magic number indicating that a tag table is present */
+#define ATAG_MAGIC	0xa2a25441
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Generic memory range, used by several tags.
+ *
+ *   addr is always physical.
+ *   size is measured in bytes.
+ *   next is for use by the OS, e.g. for grouping regions into
+ *	  linked lists.
+ */
+struct tag_mem_range {
+	u32			addr;
+	u32			size;
+	struct tag_mem_range *	next;
+};
+
+/* The list ends with an ATAG_NONE node. */
+#define ATAG_NONE	0x00000000
+
+struct tag_header {
+	u32 size;
+	u32 tag;
+};
+
+/* The list must start with an ATAG_CORE node */
+#define ATAG_CORE	0x54410001
+
+struct tag_core {
+	u32 flags;
+	u32 pagesize;
+	u32 rootdev;
+};
+
+/* it is allowed to have multiple ATAG_MEM nodes */
+#define ATAG_MEM	0x54410002
+/* ATAG_MEM uses tag_mem_range */
+
+/* command line: \0 terminated string */
+#define ATAG_CMDLINE	0x54410003
+
+struct tag_cmdline {
+	char	cmdline[1];	/* this is the minimum size */
+};
+
+/* Ramdisk image (may be compressed) */
+#define ATAG_RDIMG	0x54410004
+/* ATAG_RDIMG uses tag_mem_range */
+
+/* Information about various clocks present in the system */
+#define ATAG_CLOCK	0x54410005
+
+struct tag_clock {
+	u32	clock_id;	/* Which clock are we talking about? */
+	u32	clock_flags;	/* Special features */
+	u64	clock_hz;	/* Clock speed in Hz */
+};
+
+/* The clock types we know about */
+#define ACLOCK_BOOTCPU	0	/* The CPU we're booting from */
+#define ACLOCK_HSB	1	/* Deprecated */
+
+/* Memory reserved for the system (e.g. the bootloader) */
+#define ATAG_RSVD_MEM	0x54410006
+/* ATAG_RSVD_MEM uses tag_mem_range */
+
+/* Ethernet information */
+
+#define ATAG_ETHERNET	0x54410007
+
+struct tag_ethernet {
+	u8	mac_index;
+	u8	mii_phy_addr;
+	u8	hw_address[6];
+};
+
+#define AETH_INVALID_PHY	0xff
+
+struct tag {
+	struct tag_header hdr;
+	union {
+		struct tag_core core;
+		struct tag_mem_range mem_range;
+		struct tag_cmdline cmdline;
+		struct tag_clock clock;
+		struct tag_ethernet ethernet;
+	} u;
+};
+
+struct tagtable {
+	u32	tag;
+	int	(*parse)(struct tag *);
+};
+
+#define __tag __attribute_used__ __attribute__((__section__(".taglist")))
+#define __tagtable(tag, fn)						\
+	static struct tagtable __tagtable_##fn __tag = { tag, fn }
+
+#define tag_member_present(tag,member)					\
+	((unsigned long)(&((struct tag *)0L)->member + 1)		\
+	 <= (tag)->hdr.size * 4)
+
+#define tag_next(t)	((struct tag *)((u32 *)(t) + (t)->hdr.size))
+#define tag_size(type)	((sizeof(struct tag_header) + sizeof(struct type)) >> 2)
+
+#define for_each_tag(t,base)						\
+	for (t = base; t->hdr.size; t = tag_next(t))
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __ASM_AVR32_SETUP_H__ */
diff --git a/include/asm-avr32/string.h b/include/asm-avr32/string.h
new file mode 100644
index 0000000000..8b05d1a031
--- /dev/null
+++ b/include/asm-avr32/string.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_STRING_H
+#define __ASM_AVR32_STRING_H
+
+#define __HAVE_ARCH_MEMSET
+extern void *memset(void *s, int c, size_t n);
+
+#endif /* __ASM_AVR32_STRING_H */
diff --git a/include/asm-avr32/sysreg.h b/include/asm-avr32/sysreg.h
new file mode 100644
index 0000000000..72ad49e5e2
--- /dev/null
+++ b/include/asm-avr32/sysreg.h
@@ -0,0 +1,279 @@
+/*
+ * System registers for AVR32
+ */
+#ifndef __ASM_AVR32_SYSREG_H__
+#define __ASM_AVR32_SYSREG_H__
+
+/* system register offsets */
+#define SYSREG_SR			0x0000
+#define SYSREG_EVBA			0x0004
+#define SYSREG_ACBA			0x0008
+#define SYSREG_CPUCR			0x000c
+#define SYSREG_ECR			0x0010
+#define SYSREG_RSR_SUP			0x0014
+#define SYSREG_RSR_INT0			0x0018
+#define SYSREG_RSR_INT1			0x001c
+#define SYSREG_RSR_INT2			0x0020
+#define SYSREG_RSR_INT3			0x0024
+#define SYSREG_RSR_EX			0x0028
+#define SYSREG_RSR_NMI			0x002c
+#define SYSREG_RSR_DBG			0x0030
+#define SYSREG_RAR_SUP			0x0034
+#define SYSREG_RAR_INT0			0x0038
+#define SYSREG_RAR_INT1			0x003c
+#define SYSREG_RAR_INT2			0x0040
+#define SYSREG_RAR_INT3			0x0044
+#define SYSREG_RAR_EX			0x0048
+#define SYSREG_RAR_NMI			0x004c
+#define SYSREG_RAR_DBG			0x0050
+#define SYSREG_JECR			0x0054
+#define SYSREG_JOSP			0x0058
+#define SYSREG_JAVA_LV0			0x005c
+#define SYSREG_JAVA_LV1			0x0060
+#define SYSREG_JAVA_LV2			0x0064
+#define SYSREG_JAVA_LV3			0x0068
+#define SYSREG_JAVA_LV4			0x006c
+#define SYSREG_JAVA_LV5			0x0070
+#define SYSREG_JAVA_LV6			0x0074
+#define SYSREG_JAVA_LV7			0x0078
+#define SYSREG_JTBA			0x007c
+#define SYSREG_JBCR			0x0080
+#define SYSREG_CONFIG0			0x0100
+#define SYSREG_CONFIG1			0x0104
+#define SYSREG_COUNT			0x0108
+#define SYSREG_COMPARE			0x010c
+#define SYSREG_TLBEHI			0x0110
+#define SYSREG_TLBELO			0x0114
+#define SYSREG_PTBR			0x0118
+#define SYSREG_TLBEAR			0x011c
+#define SYSREG_MMUCR			0x0120
+#define SYSREG_TLBARLO			0x0124
+#define SYSREG_TLBARHI			0x0128
+#define SYSREG_PCCNT			0x012c
+#define SYSREG_PCNT0			0x0130
+#define SYSREG_PCNT1			0x0134
+#define SYSREG_PCCR			0x0138
+#define SYSREG_BEAR			0x013c
+#define SYSREG_SABAL			0x0300
+#define SYSREG_SABAH			0x0304
+#define SYSREG_SABD			0x0308
+
+/* Bitfields in SR */
+#define SYSREG_SR_C_OFFSET		0
+#define SYSREG_SR_C_SIZE		1
+#define SYSREG_Z_OFFSET			1
+#define SYSREG_Z_SIZE			1
+#define SYSREG_SR_N_OFFSET		2
+#define SYSREG_SR_N_SIZE		1
+#define SYSREG_SR_V_OFFSET		3
+#define SYSREG_SR_V_SIZE		1
+#define SYSREG_Q_OFFSET			4
+#define SYSREG_Q_SIZE			1
+#define SYSREG_L_OFFSET			5
+#define SYSREG_L_SIZE			1
+#define SYSREG_T_OFFSET			14
+#define SYSREG_T_SIZE			1
+#define SYSREG_SR_R_OFFSET		15
+#define SYSREG_SR_R_SIZE		1
+#define SYSREG_GM_OFFSET		16
+#define SYSREG_GM_SIZE			1
+#define SYSREG_I0M_OFFSET		17
+#define SYSREG_I0M_SIZE			1
+#define SYSREG_I1M_OFFSET		18
+#define SYSREG_I1M_SIZE			1
+#define SYSREG_I2M_OFFSET		19
+#define SYSREG_I2M_SIZE			1
+#define SYSREG_I3M_OFFSET		20
+#define SYSREG_I3M_SIZE			1
+#define SYSREG_EM_OFFSET		21
+#define SYSREG_EM_SIZE			1
+#define SYSREG_M0_OFFSET		22
+#define SYSREG_M0_SIZE			1
+#define SYSREG_M1_OFFSET		23
+#define SYSREG_M1_SIZE			1
+#define SYSREG_M2_OFFSET		24
+#define SYSREG_M2_SIZE			1
+#define SYSREG_SR_D_OFFSET		26
+#define SYSREG_SR_D_SIZE		1
+#define SYSREG_DM_OFFSET		27
+#define SYSREG_DM_SIZE			1
+#define SYSREG_SR_J_OFFSET		28
+#define SYSREG_SR_J_SIZE		1
+#define SYSREG_H_OFFSET			29
+#define SYSREG_H_SIZE			1
+
+/* Bitfields in CPUCR */
+#define SYSREG_BI_OFFSET		0
+#define SYSREG_BI_SIZE			1
+#define SYSREG_BE_OFFSET		1
+#define SYSREG_BE_SIZE			1
+#define SYSREG_FE_OFFSET		2
+#define SYSREG_FE_SIZE			1
+#define SYSREG_RE_OFFSET		3
+#define SYSREG_RE_SIZE			1
+#define SYSREG_IBE_OFFSET		4
+#define SYSREG_IBE_SIZE			1
+#define SYSREG_IEE_OFFSET		5
+#define SYSREG_IEE_SIZE			1
+
+/* Bitfields in ECR */
+#define SYSREG_ECR_OFFSET		0
+#define SYSREG_ECR_SIZE			32
+
+/* Bitfields in CONFIG0 */
+#define SYSREG_CONFIG0_R_OFFSET		0
+#define SYSREG_CONFIG0_R_SIZE		1
+#define SYSREG_CONFIG0_D_OFFSET		1
+#define SYSREG_CONFIG0_D_SIZE		1
+#define SYSREG_CONFIG0_S_OFFSET		2
+#define SYSREG_CONFIG0_S_SIZE		1
+#define SYSREG_O_OFFSET			3
+#define SYSREG_O_SIZE			1
+#define SYSREG_P_OFFSET			4
+#define SYSREG_P_SIZE			1
+#define SYSREG_CONFIG0_J_OFFSET		5
+#define SYSREG_CONFIG0_J_SIZE		1
+#define SYSREG_F_OFFSET			6
+#define SYSREG_F_SIZE			1
+#define SYSREG_MMUT_OFFSET		7
+#define SYSREG_MMUT_SIZE		3
+#define SYSREG_AR_OFFSET		10
+#define SYSREG_AR_SIZE			3
+#define SYSREG_AT_OFFSET		13
+#define SYSREG_AT_SIZE			3
+#define SYSREG_PROCESSORREVISION_OFFSET	16
+#define SYSREG_PROCESSORREVISION_SIZE	8
+#define SYSREG_PROCESSORID_OFFSET	24
+#define SYSREG_PROCESSORID_SIZE		8
+
+/* Bitfields in CONFIG1 */
+#define SYSREG_DASS_OFFSET		0
+#define SYSREG_DASS_SIZE		3
+#define SYSREG_DLSZ_OFFSET		3
+#define SYSREG_DLSZ_SIZE		3
+#define SYSREG_DSET_OFFSET		6
+#define SYSREG_DSET_SIZE		4
+#define SYSREG_IASS_OFFSET		10
+#define SYSREG_IASS_SIZE		3
+#define SYSREG_ILSZ_OFFSET		13
+#define SYSREG_ILSZ_SIZE		3
+#define SYSREG_ISET_OFFSET		16
+#define SYSREG_ISET_SIZE		4
+#define SYSREG_DMMUSZ_OFFSET		20
+#define SYSREG_DMMUSZ_SIZE		6
+#define SYSREG_IMMUSZ_OFFSET		26
+#define SYSREG_IMMUSZ_SIZE		6
+
+/* Bitfields in TLBEHI */
+#define SYSREG_ASID_OFFSET		0
+#define SYSREG_ASID_SIZE		8
+#define SYSREG_TLBEHI_I_OFFSET		8
+#define SYSREG_TLBEHI_I_SIZE		1
+#define SYSREG_TLBEHI_V_OFFSET		9
+#define SYSREG_TLBEHI_V_SIZE		1
+#define SYSREG_VPN_OFFSET		10
+#define SYSREG_VPN_SIZE			22
+
+/* Bitfields in TLBELO */
+#define SYSREG_W_OFFSET			0
+#define SYSREG_W_SIZE			1
+#define SYSREG_TLBELO_D_OFFSET		1
+#define SYSREG_TLBELO_D_SIZE		1
+#define SYSREG_SZ_OFFSET		2
+#define SYSREG_SZ_SIZE			2
+#define SYSREG_AP_OFFSET		4
+#define SYSREG_AP_SIZE			3
+#define SYSREG_B_OFFSET			7
+#define SYSREG_B_SIZE			1
+#define SYSREG_G_OFFSET			8
+#define SYSREG_G_SIZE			1
+#define SYSREG_TLBELO_C_OFFSET		9
+#define SYSREG_TLBELO_C_SIZE		1
+#define SYSREG_PFN_OFFSET		10
+#define SYSREG_PFN_SIZE			22
+
+/* Bitfields in MMUCR */
+#define SYSREG_E_OFFSET			0
+#define SYSREG_E_SIZE			1
+#define SYSREG_M_OFFSET			1
+#define SYSREG_M_SIZE			1
+#define SYSREG_MMUCR_I_OFFSET		2
+#define SYSREG_MMUCR_I_SIZE		1
+#define SYSREG_MMUCR_N_OFFSET		3
+#define SYSREG_MMUCR_N_SIZE		1
+#define SYSREG_MMUCR_S_OFFSET		4
+#define SYSREG_MMUCR_S_SIZE		1
+#define SYSREG_DLA_OFFSET		8
+#define SYSREG_DLA_SIZE			6
+#define SYSREG_DRP_OFFSET		14
+#define SYSREG_DRP_SIZE			6
+#define SYSREG_ILA_OFFSET		20
+#define SYSREG_ILA_SIZE			6
+#define SYSREG_IRP_OFFSET		26
+#define SYSREG_IRP_SIZE			6
+
+/* Bitfields in PCCR */
+#define SYSREG_PCCR_R_OFFSET		1
+#define SYSREG_PCCR_R_SIZE		1
+#define SYSREG_PCCR_C_OFFSET		2
+#define SYSREG_PCCR_C_SIZE		1
+#define SYSREG_PCCR_S_OFFSET		3
+#define SYSREG_PCCR_S_SIZE		1
+#define SYSREG_IEC_OFFSET		4
+#define SYSREG_IEC_SIZE			1
+#define SYSREG_IE0_OFFSET		5
+#define SYSREG_IE0_SIZE			1
+#define SYSREG_IE1_OFFSET		6
+#define SYSREG_IE1_SIZE			1
+#define SYSREG_FC_OFFSET		8
+#define SYSREG_FC_SIZE			1
+#define SYSREG_F0_OFFSET		9
+#define SYSREG_F0_SIZE			1
+#define SYSREG_F1_OFFSET		10
+#define SYSREG_F1_SIZE			1
+#define SYSREG_CONF0_OFFSET		12
+#define SYSREG_CONF0_SIZE		6
+#define SYSREG_CONF1_OFFSET		18
+#define SYSREG_CONF1_SIZE		6
+
+/* Constants for ECR */
+#define ECR_UNRECOVERABLE		0
+#define ECR_TLB_MULTIPLE		1
+#define ECR_BUS_ERROR_WRITE		2
+#define ECR_BUS_ERROR_READ		3
+#define ECR_NMI				4
+#define ECR_ADDR_ALIGN_X		5
+#define ECR_PROTECTION_X		6
+#define ECR_DEBUG			7
+#define ECR_ILLEGAL_OPCODE		8
+#define ECR_UNIMPL_INSTRUCTION		9
+#define ECR_PRIVILEGE_VIOLATION		10
+#define ECR_FPE				11
+#define ECR_COPROC_ABSENT		12
+#define ECR_ADDR_ALIGN_R		13
+#define ECR_ADDR_ALIGN_W		14
+#define ECR_PROTECTION_R		15
+#define ECR_PROTECTION_W		16
+#define ECR_DTLB_MODIFIED		17
+#define ECR_TLB_MISS_X			20
+#define ECR_TLB_MISS_R			24
+#define ECR_TLB_MISS_W			28
+
+/* Bit manipulation macros */
+#define SYSREG_BIT(name)		(1 << SYSREG_##name##_OFFSET)
+#define SYSREG_BF(name,value)				\
+	(((value) & ((1 << SYSREG_##name##_SIZE) - 1))	\
+	 << SYSREG_##name##_OFFSET)
+#define SYSREG_BFEXT(name,value)			\
+	(((value) >> SYSREG_##name##_OFFSET)		\
+	 & ((1 << SYSREG_##name##_SIZE) - 1))
+#define SYSREG_BFINS(name,value,old)			\
+	(((old) & ~(((1 << SYSREG_##name##_SIZE) - 1)	\
+		    << SYSREG_##name##_OFFSET))		\
+	 | SYSREG_BF(name,value))
+
+/* Register access macros */
+#define sysreg_read(reg)		__builtin_mfsr(SYSREG_##reg)
+#define sysreg_write(reg, value)	__builtin_mtsr(SYSREG_##reg, value)
+
+#endif /* __ASM_AVR32_SYSREG_H__ */
diff --git a/include/asm-avr32/types.h b/include/asm-avr32/types.h
new file mode 100644
index 0000000000..e6c65d9179
--- /dev/null
+++ b/include/asm-avr32/types.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_TYPES_H
+#define __ASM_AVR32_TYPES_H
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+#define BITS_PER_LONG 32
+
+#ifndef __ASSEMBLY__
+
+typedef __signed__ char s8;
+typedef unsigned char u8;
+
+typedef __signed__ short s16;
+typedef unsigned short u16;
+
+typedef __signed__ int s32;
+typedef unsigned int u32;
+
+typedef __signed__ long long s64;
+typedef unsigned long long u64;
+
+/* Dma addresses are 32-bits wide.  */
+
+typedef u32 dma_addr_t;
+
+#ifdef CONFIG_LBD
+typedef u64 sector_t;
+#define HAVE_SECTOR_T
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+
+#endif /* __ASM_AVR32_TYPES_H */
diff --git a/include/asm-avr32/u-boot.h b/include/asm-avr32/u-boot.h
new file mode 100644
index 0000000000..71dfcaf284
--- /dev/null
+++ b/include/asm-avr32/u-boot.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_U_BOOT_H__
+#define __ASM_U_BOOT_H__ 1
+
+typedef struct bd_info {
+	unsigned long		bi_baudrate;
+	unsigned long		bi_ip_addr;
+	unsigned char		bi_enetaddr[6];
+	unsigned char		bi_phy_id[4];
+	struct environment_s	*bi_env;
+	unsigned long		bi_board_number;
+	void			*bi_boot_params;
+	struct {
+		unsigned long	start;
+		unsigned long	size;
+	}			bi_dram[CONFIG_NR_DRAM_BANKS];
+	unsigned long		bi_flashstart;
+	unsigned long		bi_flashsize;
+	unsigned long		bi_flashoffset;
+} bd_t;
+
+#define bi_memstart bi_dram[0].start
+#define bi_memsize bi_dram[0].size
+
+/**
+ *  container_of - cast a member of a structure out to the containing structure
+ *
+ *    @ptr:        the pointer to the member.
+ *    @type:       the type of the container struct this is embedded in.
+ *    @member:     the name of the member within the struct.
+ */
+#define container_of(ptr, type, member) ({                      \
+	const typeof( ((type *)0)->member ) *__mptr = (ptr);    \
+	(type *)( (char *)__mptr - offsetof(type,member) );})
+
+#endif /* __ASM_U_BOOT_H__ */
diff --git a/include/asm-ppc/fsl_i2c.h b/include/asm-ppc/fsl_i2c.h
new file mode 100644
index 0000000000..76b1c4309b
--- /dev/null
+++ b/include/asm-ppc/fsl_i2c.h
@@ -0,0 +1,90 @@
+/*
+ * Freescale I2C Controller
+ *
+ * Copyright 2006 Freescale Semiconductor, Inc.
+ *
+ * Based on earlier versions by Gleb Natapov <gnatapov@mrv.com>,
+ * Xianghua Xiao <x.xiao@motorola.com>, Eran Liberty (liberty@freescale.com),
+ * and Jeff Brown.
+ * Some bits are taken from linux driver writen by adrian@humboldt.co.uk.
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_FSL_I2C_H_
+#define _ASM_FSL_I2C_H_
+
+#include <asm/types.h>
+
+typedef struct fsl_i2c {
+
+	u8 adr;		/* I2C slave address */
+	u8 res0[3];
+#define I2C_ADR		0xFE
+#define I2C_ADR_SHIFT	1
+#define I2C_ADR_RES	~(I2C_ADR)
+
+	u8 fdr;		/* I2C frequency divider register */
+	u8 res1[3];
+#define IC2_FDR		0x3F
+#define IC2_FDR_SHIFT	0
+#define IC2_FDR_RES	~(IC2_FDR)
+
+	u8 cr;		/* I2C control redister	*/
+	u8 res2[3];
+#define I2C_CR_MEN	0x80
+#define I2C_CR_MIEN	0x40
+#define I2C_CR_MSTA	0x20
+#define I2C_CR_MTX	0x10
+#define I2C_CR_TXAK	0x08
+#define I2C_CR_RSTA	0x04
+#define I2C_CR_BCST	0x01
+
+	u8 sr;		/* I2C status register */
+	u8 res3[3];
+#define I2C_SR_MCF	0x80
+#define I2C_SR_MAAS	0x40
+#define I2C_SR_MBB	0x20
+#define I2C_SR_MAL	0x10
+#define I2C_SR_BCSTM	0x08
+#define I2C_SR_SRW	0x04
+#define I2C_SR_MIF	0x02
+#define I2C_SR_RXAK	0x01
+
+	u8 dr;		/* I2C data register */
+	u8 res4[3];
+#define I2C_DR		0xFF
+#define I2C_DR_SHIFT	0
+#define I2C_DR_RES	~(I2C_DR)
+
+	u8 dfsrr;	/* I2C digital filter sampling rate register */
+	u8 res5[3];
+#define I2C_DFSRR	0x3F
+#define I2C_DFSRR_SHIFT	0
+#define I2C_DFSRR_RES	~(I2C_DR)
+
+	/* Fill out the reserved block */
+	u8 res6[0xE8];
+} fsl_i2c_t;
+
+
+#define I2C_READ  1
+#define I2C_WRITE 0
+
+#endif	/* _ASM_I2C_H_ */
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 2f10e9591d..5377c2eb5b 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -9,6 +9,9 @@
 #ifndef __IMMAP_85xx__
 #define __IMMAP_85xx__
 
+#include <asm/types.h>
+#include <asm/fsl_i2c.h>
+
 /*
  * Local-Access Registers and ECM Registers(0x0000-0x2000)
  */
@@ -129,37 +132,8 @@ typedef struct ccsr_ddr {
  * I2C Registers(0x3000-0x4000)
  */
 typedef struct ccsr_i2c {
-	u_char	i2cadr;		/* 0x3000 - I2C Address Register */
-#define MPC85xx_I2CADR_MASK	0xFE
-	char	res1[3];
-	u_char	i2cfdr;		/* 0x3004 - I2C Frequency Divider Register */
-#define MPC85xx_I2CFDR_MASK	0x3F
-	char	res2[3];
-	u_char	i2ccr;		/* 0x3008 - I2C Control Register */
-#define MPC85xx_I2CCR_MEN	0x80
-#define MPC85xx_I2CCR_MIEN	0x40
-#define MPC85xx_I2CCR_MSTA      0x20
-#define MPC85xx_I2CCR_MTX       0x10
-#define MPC85xx_I2CCR_TXAK      0x08
-#define MPC85xx_I2CCR_RSTA      0x04
-#define MPC85xx_I2CCR_BCST      0x01
-	char	res3[3];
-	u_char	i2csr;		/* 0x300c - I2C Status Register */
-#define MPC85xx_I2CSR_MCF	0x80
-#define MPC85xx_I2CSR_MAAS      0x40
-#define MPC85xx_I2CSR_MBB       0x20
-#define MPC85xx_I2CSR_MAL       0x10
-#define MPC85xx_I2CSR_BCSTM     0x08
-#define MPC85xx_I2CSR_SRW       0x04
-#define MPC85xx_I2CSR_MIF       0x02
-#define MPC85xx_I2CSR_RXAK      0x01
-	char	res4[3];
-	u_char	i2cdr;		/* 0x3010 - I2C Data Register */
-#define MPC85xx_I2CDR_DATA	0xFF
-	char	res5[3];
-	u_char	i2cdfsrr;	/* 0x3014 - I2C Digital Filtering Sampling Rate Register */
-#define MPC85xx_I2CDFSRR	0x3F
-	char	res6[4075];
+	struct fsl_i2c	i2c[1];
+	u8	res[4096 - 1 * sizeof(struct fsl_i2c)];
 } ccsr_i2c_t;
 
 #if defined(CONFIG_MPC8540) \
@@ -246,7 +220,6 @@ typedef struct ccsr_lbc {
 
 /*
  * PCI Registers(0x8000-0x9000)
- * Omitting Reserved(0x9000-0x2_0000)
  */
 typedef struct ccsr_pcix {
 	uint	cfg_addr;	/* 0x8000 - PCIX Configuration Address Register */
@@ -309,9 +282,27 @@ typedef struct ccsr_pcix {
 	uint	peextaddrcr;	/* 0x8e14 - PCIX  Error Extended Address Capture Register */
 	uint	pedlcr;		/* 0x8e18 - PCIX Error Data Low Capture Register */
 	uint	pedhcr;		/* 0x8e1c - PCIX Error Error Data High Capture Register */
-	char	res11[94688];
+	uint	gas_timr;	/* 0x8e20 - PCIX Gasket Timer Register */
+	char	res11[476];
 } ccsr_pcix_t;
 
+#define PCIX_COMMAND	0x62
+#define POWAR_EN	0x80000000
+#define POWAR_IO_READ	0x00080000
+#define POWAR_MEM_READ	0x00040000
+#define POWAR_IO_WRITE	0x00008000
+#define POWAR_MEM_WRITE	0x00004000
+#define POWAR_MEM_512M	0x0000001c
+#define POWAR_IO_1M	0x00000013
+
+#define PIWAR_EN	0x80000000
+#define PIWAR_PF	0x20000000
+#define PIWAR_LOCAL	0x00f00000
+#define PIWAR_READ_SNOOP	0x00050000
+#define PIWAR_WRITE_SNOOP	0x00005000
+#define PIWAR_MEM_2G		0x0000001e
+
+
 /*
  * L2 Cache Registers(0x2_0000-0x2_1000)
  */
@@ -1572,6 +1563,8 @@ typedef struct ccsr_gur {
 	char	res15[61651];
 } ccsr_gur_t;
 
+#define PORDEVSR_PCI	(0x00800000)	/* PCI Mode */
+
 typedef struct immap {
 	ccsr_local_ecm_t	im_local_ecm;
 	ccsr_ddr_t		im_ddr;
@@ -1579,6 +1572,8 @@ typedef struct immap {
 	ccsr_duart_t		im_duart;
 	ccsr_lbc_t		im_lbc;
 	ccsr_pcix_t		im_pcix;
+	ccsr_pcix_t		im_pcix2;
+	char			reserved[90112];
 	ccsr_l2cache_t		im_l2cache;
 	ccsr_dma_t		im_dma;
 	ccsr_tsec_t		im_tsec1;
diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h
new file mode 100644
index 0000000000..a5552c48ee
--- /dev/null
+++ b/include/asm-ppc/immap_86xx.h
@@ -0,0 +1,1323 @@
+/*
+ * MPC86xx Internal Memory Map
+ *
+ * Copyright(c) 2004 Freescale Semiconductor
+ * Jeff Brown (Jeffrey@freescale.com)
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ */
+
+#ifndef __IMMAP_86xx__
+#define __IMMAP_86xx__
+
+#include <asm/types.h>
+#include <asm/fsl_i2c.h>
+
+/* Local-Access Registers and MCM Registers(0x0000-0x2000) */
+typedef struct ccsr_local_mcm {
+	uint	ccsrbar;	/* 0x0 - Control Configuration Status Registers Base Address Register */
+	char	res1[4];
+	uint	altcbar;	/* 0x8 - Alternate Configuration Base Address Register */
+	char	res2[4];
+	uint	altcar;		/* 0x10 - Alternate Configuration Attribute Register */
+	char	res3[12];
+	uint	bptr;		/* 0x20 - Boot Page Translation Register */
+	char	res4[3044];
+	uint	lawbar0;	/* 0xc08 - Local Access Window 0 Base Address Register */
+	char	res5[4];
+	uint	lawar0;		/* 0xc10 - Local Access Window 0 Attributes Register */
+	char	res6[20];
+	uint	lawbar1;	/* 0xc28 - Local Access Window 1 Base Address Register */
+	char	res7[4];
+	uint	lawar1;		/* 0xc30 - Local Access Window 1 Attributes Register */
+	char	res8[20];
+	uint	lawbar2;	/* 0xc48 - Local Access Window 2 Base Address Register */
+	char	res9[4];
+	uint	lawar2;		/* 0xc50 - Local Access Window 2 Attributes Register */
+	char	res10[20];
+	uint	lawbar3;	/* 0xc68 - Local Access Window 3 Base Address Register */
+	char	res11[4];
+	uint	lawar3;		/* 0xc70 - Local Access Window 3 Attributes Register */
+	char	res12[20];
+	uint	lawbar4;	/* 0xc88 - Local Access Window 4 Base Address Register */
+	char	res13[4];
+	uint	lawar4;		/* 0xc90 - Local Access Window 4 Attributes Register */
+	char	res14[20];
+	uint	lawbar5;	/* 0xca8 - Local Access Window 5 Base Address Register */
+	char	res15[4];
+	uint	lawar5;		/* 0xcb0 - Local Access Window 5 Attributes Register */
+	char	res16[20];
+	uint	lawbar6;	/* 0xcc8 - Local Access Window 6 Base Address Register */
+	char	res17[4];
+	uint	lawar6;		/* 0xcd0 - Local Access Window 6 Attributes Register */
+	char	res18[20];
+	uint	lawbar7;	/* 0xce8 - Local Access Window 7 Base Address Register */
+	char	res19[4];
+	uint	lawar7;		/* 0xcf0 - Local Access Window 7 Attributes Register */
+	char	res20[20];
+	uint	lawbar8;	/* 0xd08 - Local Access Window 8 Base Address Register */
+	char	res21[4];
+	uint	lawar8;		/* 0xd10 - Local Access Window 8 Attributes Register */
+	char	res22[20];
+	uint	lawbar9;	/* 0xd28 - Local Access Window 9 Base Address Register */
+	char	res23[4];
+	uint	lawar9;		/* 0xd30 - Local Access Window 9 Attributes Register */
+	char	res24[716];
+	uint	abcr;		/* 0x1000 - MCM CCB Address Configuration Register */
+	char	res25[4];
+	uint    dbcr;           /* 0x1008 - MCM MPX data bus Configuration Register */
+	char	res26[4];
+	uint	pcr;		/* 0x1010 - MCM CCB Port Configuration Register */
+	char	res27[44];
+	uint	hpmr0;		/* 0x1040 - MCM HPM Threshold Count Register 0 */
+	uint	hpmr1;		/* 0x1044 - MCM HPM Threshold Count Register 1 */
+	uint	hpmr2;		/* 0x1048 - MCM HPM Threshold Count Register 2 */
+	uint	hpmr3;		/* 0x104c - MCM HPM Threshold Count Register 3 */
+	char	res28[16];
+	uint	hpmr4;		/* 0x1060 - MCM HPM Threshold Count Register 4 */
+	uint	hpmr5;		/* 0x1064 - MCM HPM Threshold Count Register 5 */
+	uint	hpmccr;		/* 0x1068 - MCM HPM Cycle Count Register */
+	char	res29[3476];
+	uint	edr;		/* 0x1e00 - MCM Error Detect Register */
+	char	res30[4];
+	uint	eer;		/* 0x1e08 - MCM Error Enable Register */
+	uint	eatr;		/* 0x1e0c - MCM Error Attributes Capture Register */
+	uint	eladr;		/* 0x1e10 - MCM Error Low Address Capture Register */
+	uint	ehadr;		/* 0x1e14 - MCM Error High Address Capture Register */
+	char	res31[488];
+} ccsr_local_mcm_t;
+
+/* DDR memory controller registers(0x2000-0x3000) and (0x6000-0x7000) */
+
+typedef struct ccsr_ddr {
+	uint	cs0_bnds;		/* 0x2000 - DDR Chip Select 0 Memory Bounds */
+	char	res1[4];
+	uint	cs1_bnds;		/* 0x2008 - DDR Chip Select 1 Memory Bounds */
+	char	res2[4];
+	uint	cs2_bnds;		/* 0x2010 - DDR Chip Select 2 Memory Bounds */
+	char	res3[4];
+	uint	cs3_bnds;		/* 0x2018 - DDR Chip Select 3 Memory Bounds */
+	char	res4[4];
+	uint	cs4_bnds;		/* 0x2020 - DDR Chip Select 4 Memory Bounds */
+	char	res5[4];
+	uint	cs5_bnds;		/* 0x2028 - DDR Chip Select 5 Memory Bounds */
+	char	res6[84];
+	uint	cs0_config;		/* 0x2080 - DDR Chip Select Configuration */
+	uint	cs1_config;		/* 0x2084 - DDR Chip Select Configuration */
+	uint	cs2_config;		/* 0x2088 - DDR Chip Select Configuration */
+	uint	cs3_config;		/* 0x208c - DDR Chip Select Configuration */
+	uint	cs4_config;		/* 0x2090 - DDR Chip Select Configuration */
+	uint	cs5_config;		/* 0x2094 - DDR Chip Select Configuration */
+	char	res7[104];
+	uint    ext_refrec;             /* 0x2100 - DDR SDRAM extended refresh recovery */
+	uint	timing_cfg_0;		/* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
+	uint	timing_cfg_1;		/* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
+	uint	timing_cfg_2;		/* 0x210c - DDR SDRAM Timing Configuration Register 2 */
+	uint	sdram_cfg_1;		/* 0x2110 - DDR SDRAM Control Configuration 1 */
+	uint    sdram_cfg_2;            /* 0x2114 - DDR SDRAM Control Configuration 2 */
+	uint	sdram_mode_1;		/* 0x2118 - DDR SDRAM Mode Configuration 1 */
+	uint    sdram_mode_2;		/* 0x211c - DDR SDRAM Mode Configuration 2 */
+	uint    sdram_mode_cntl;        /* 0x2120 - DDR SDRAM Mode Control */
+	uint	sdram_interval;		/* 0x2124 - DDR SDRAM Interval Configuration */
+	uint    sdram_data_init; 	/* 0x2128 - DDR SDRAM Data Initialization */
+	char	res8[4];
+	uint	sdram_clk_cntl;		/* 0x2130 - DDR SDRAM Clock Control */
+	char    res9[12];
+	uint    sdram_ocd_cntl;		/* 0x2140 - DDR SDRAM OCD Control */
+	uint    sdram_ocd_status;	/* 0x2144 - DDR SDRAM OCD Status */
+	uint    init_addr;		/* 0x2148 - DDR training initialzation address */
+	uint    init_addr_ext;		/* 0x214C - DDR training initialzation extended address */
+	char    res10[2728];
+	uint    ip_rev1;		/* 0x2BF8 - DDR IP Block Revision 1 */
+	uint    ip_rev2;		/* 0x2BFC - DDR IP Block Revision 2 */
+	char	res11[512];
+	uint	data_err_inject_hi;	/* 0x2e00 - DDR Memory Data Path Error Injection Mask High */
+	uint	data_err_inject_lo;	/* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */
+	uint	ecc_err_inject;		/* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */
+	char	res12[20];
+	uint	capture_data_hi;	/* 0x2e20 - DDR Memory Data Path Read Capture High */
+	uint	capture_data_lo;	/* 0x2e24 - DDR Memory Data Path Read Capture Low */
+	uint	capture_ecc;		/* 0x2e28 - DDR Memory Data Path Read Capture ECC */
+	char	res13[20];
+	uint	err_detect;		/* 0x2e40 - DDR Memory Error Detect */
+	uint	err_disable;		/* 0x2e44 - DDR Memory Error Disable */
+	uint	err_int_en;		/* 0x2e48 - DDR Memory Error Interrupt Enable */
+	uint	capture_attributes;	/* 0x2e4c - DDR Memory Error Attributes Capture */
+	uint	capture_address;	/* 0x2e50 - DDR Memory Error Address Capture */
+	uint	capture_ext_address;	/* 0x2e54 - DDR Memory Error Extended Address Capture */
+	uint	err_sbe;		/* 0x2e58 - DDR Memory Single-Bit ECC Error Management */
+	char	res14[164];
+	uint	debug_1;		/* 0x2f00 */
+	uint	debug_2;
+	uint	debug_3;
+	uint	debug_4;
+	uint	debug_5;
+	char	res15[236];
+} ccsr_ddr_t;
+
+
+/* Daul I2C Registers(0x3000-0x4000) */
+typedef struct ccsr_i2c {
+	struct fsl_i2c	i2c[2];
+	u8	res[4096 - 2 * sizeof(struct fsl_i2c)];
+} ccsr_i2c_t;
+
+/* DUART Registers(0x4000-0x5000) */
+typedef struct ccsr_duart {
+	char	res1[1280];
+	u_char	urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */
+	u_char	uier1_udmb1;	/* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */
+	u_char	uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */
+	u_char	ulcr1;		/* 0x4503 - UART1 Line Control Register */
+	u_char	umcr1;		/* 0x4504 - UART1 Modem Control Register */
+	u_char	ulsr1;		/* 0x4505 - UART1 Line Status Register */
+	u_char	umsr1;		/* 0x4506 - UART1 Modem Status Register */
+	u_char	uscr1;		/* 0x4507 - UART1 Scratch Register */
+	char	res2[8];
+	u_char	udsr1;		/* 0x4510 - UART1 DMA Status Register */
+	char	res3[239];
+	u_char	urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */
+	u_char	uier2_udmb2;	/* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */
+	u_char	uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */
+	u_char	ulcr2;		/* 0x4603 - UART2 Line Control Register */
+	u_char	umcr2;		/* 0x4604 - UART2 Modem Control Register */
+	u_char	ulsr2;		/* 0x4605 - UART2 Line Status Register */
+	u_char	umsr2;		/* 0x4606 - UART2 Modem Status Register */
+	u_char	uscr2;		/* 0x4607 - UART2 Scratch Register */
+	char	res4[8];
+	u_char	udsr2;		/* 0x4610 - UART2 DMA Status Register */
+	char	res5[2543];
+} ccsr_duart_t;
+
+
+/* Local Bus Controller Registers(0x5000-0x6000) */
+typedef struct ccsr_lbc {
+	uint	br0;		/* 0x5000 - LBC Base Register 0 */
+	uint	or0;		/* 0x5004 - LBC Options Register 0 */
+	uint	br1;		/* 0x5008 - LBC Base Register 1 */
+	uint	or1;		/* 0x500c - LBC Options Register 1 */
+	uint	br2;		/* 0x5010 - LBC Base Register 2 */
+	uint	or2;		/* 0x5014 - LBC Options Register 2 */
+	uint	br3;		/* 0x5018 - LBC Base Register 3 */
+	uint	or3;		/* 0x501c - LBC Options Register 3 */
+	uint	br4;		/* 0x5020 - LBC Base Register 4 */
+	uint	or4;		/* 0x5024 - LBC Options Register 4 */
+	uint	br5;		/* 0x5028 - LBC Base Register 5 */
+	uint	or5;		/* 0x502c - LBC Options Register 5 */
+	uint	br6;		/* 0x5030 - LBC Base Register 6 */
+	uint	or6;		/* 0x5034 - LBC Options Register 6 */
+	uint	br7;		/* 0x5038 - LBC Base Register 7 */
+	uint	or7;		/* 0x503c - LBC Options Register 7 */
+	char	res1[40];
+	uint	mar;		/* 0x5068 - LBC UPM Address Register */
+	char	res2[4];
+	uint	mamr;		/* 0x5070 - LBC UPMA Mode Register */
+	uint	mbmr;		/* 0x5074 - LBC UPMB Mode Register */
+	uint	mcmr;		/* 0x5078 - LBC UPMC Mode Register */
+	char	res3[8];
+	uint	mrtpr;		/* 0x5084 - LBC Memory Refresh Timer Prescaler Register */
+	uint	mdr;		/* 0x5088 - LBC UPM Data Register */
+	char	res4[8];
+	uint	lsdmr;		/* 0x5094 - LBC SDRAM Mode Register */
+	char	res5[8];
+	uint	lurt;		/* 0x50a0 - LBC UPM Refresh Timer */
+	uint	lsrt;		/* 0x50a4 - LBC SDRAM Refresh Timer */
+	char	res6[8];
+	uint	ltesr;		/* 0x50b0 - LBC Transfer Error Status Register */
+	uint	ltedr;		/* 0x50b4 - LBC Transfer Error Disable Register */
+	uint	lteir;		/* 0x50b8 - LBC Transfer Error Interrupt Register */
+	uint	lteatr;		/* 0x50bc - LBC Transfer Error Attributes Register */
+	uint	ltear;		/* 0x50c0 - LBC Transfer Error Address Register */
+	char	res7[12];
+	uint	lbcr;		/* 0x50d0 - LBC Configuration Register */
+	uint	lcrr;		/* 0x50d4 - LBC Clock Ratio Register */
+	char	res8[3880];
+} ccsr_lbc_t;
+
+/* PCI Express Registers(0x8000-0x9000) and (0x9000-0xA000) */
+typedef struct ccsr_pex {
+	uint	cfg_addr;	/* 0x8000 - PEX Configuration Address Register */
+	uint	cfg_data;	/* 0x8004 - PEX Configuration Data Register */
+	char	res1[4];
+	uint	out_comp_to;	/* 0x800C - PEX Outbound Completion Timeout Register */
+	char	res2[16];
+	uint	pme_msg_det;	/* 0x8020 - PEX PME & message detect register */
+	uint    pme_msg_int_en;	/* 0x8024 - PEX PME & message interrupt enable register */
+	uint    pme_msg_dis;	/* 0x8028 - PEX PME & message disable register */
+	uint    pm_command;	/* 0x802c - PEX PM Command register */
+	char	res3[3016];
+	uint    block_rev1;	/* 0x8bf8 - PEX Block Revision register 1 */
+	uint    block_rev2;	/* 0x8bfc - PEX Block Revision register 2 */
+	uint	potar0;	        /* 0x8c00 - PEX Outbound Transaction Address Register 0 */
+	uint	potear0;	/* 0x8c04 - PEX Outbound Translation Extended Address Register 0 */
+	char	res4[8];
+	uint	powar0;	        /* 0x8c10 - PEX Outbound Window Attributes Register 0 */
+	char	res5[12];
+	uint	potar1;	        /* 0x8c20 - PEX Outbound Transaction Address Register 1 */
+	uint	potear1;	/* 0x8c24 - PEX Outbound Translation Extended Address Register 1 */
+	uint	powbar1;	/* 0x8c28 - PEX Outbound Window Base Address Register 1 */
+	char	res6[4];
+	uint	powar1;	        /* 0x8c30 - PEX Outbound Window Attributes Register 1 */
+	char	res7[12];
+	uint	potar2;	        /* 0x8c40 - PEX Outbound Transaction Address Register 2 */
+	uint	potear2;	/* 0x8c44 - PEX Outbound Translation Extended Address Register 2 */
+	uint	powbar2;	/* 0x8c48 - PEX Outbound Window Base Address Register 2 */
+	char	res8[4];
+	uint	powar2;	        /* 0x8c50 - PEX Outbound Window Attributes Register 2 */
+	char	res9[12];
+	uint	potar3;	        /* 0x8c60 - PEX Outbound Transaction Address Register 3 */
+	uint	potear3;	/* 0x8c64 - PEX Outbound Translation Extended Address Register 3 */
+	uint	powbar3;	/* 0x8c68 - PEX Outbound Window Base Address Register 3 */
+	char	res10[4];
+	uint	powar3;	        /* 0x8c70 - PEX Outbound Window Attributes Register 3 */
+	char	res11[12];
+	uint	potar4;	        /* 0x8c80 - PEX Outbound Transaction Address Register 4 */
+	uint	potear4;	/* 0x8c84 - PEX Outbound Translation Extended Address Register 4 */
+	uint	powbar4;	/* 0x8c88 - PEX Outbound Window Base Address Register 4 */
+	char	res12[4];
+	uint	powar4;	        /* 0x8c90 - PEX Outbound Window Attributes Register 4 */
+	char	res13[12];
+	char	res14[256];
+	uint	pitar3;	        /* 0x8da0 - PEX Inbound Translation Address Register 3  */
+	char	res15[4];
+	uint	piwbar3;	/* 0x8da8 - PEX Inbound Window Base Address Register 3 */
+	uint	piwbear3;	/* 0x8dac - PEX Inbound Window Base Extended Address Register 3 */
+	uint	piwar3;	        /* 0x8db0 - PEX Inbound Window Attributes Register 3 */
+	char	res16[12];
+	uint	pitar2;	        /* 0x8dc0 - PEX Inbound Translation Address Register 2  */
+	char	res17[4];
+	uint	piwbar2;	/* 0x8dc8 - PEX Inbound Window Base Address Register 2 */
+	uint	piwbear2;	/* 0x8dcc - PEX Inbound Window Base Extended Address Register 2 */
+	uint	piwar2;	        /* 0x8dd0 - PEX Inbound Window Attributes Register 2 */
+	char	res18[12];
+	uint	pitar1;	        /* 0x8de0 - PEX Inbound Translation Address Register 1  */
+	char	res19[4];
+	uint	piwbar1;	/* 0x8de8 - PEX Inbound Window Base Address Register 1 */
+	uint	piwbear1;
+	uint	piwar1;	        /* 0x8df0 - PEX Inbound Window Attributes Register 1 */
+	char	res20[12];
+	uint	pedr;		/* 0x8e00 - PEX Error Detect Register */
+	char    res21[4];
+	uint	peer;		/* 0x8e08 - PEX Error Interrupt Enable Register */
+	char    res22[4];
+	uint	pecdr;		/* 0x8e10 - PEX Error Disable Register */
+	char    res23[12];
+	uint	peer_stat;	/* 0x8e20 - PEX Error Capture Status Register */
+	char    res24[4];
+	uint	perr_cap0;	/* 0x8e28 - PEX Error Capture Register 0 */
+	uint	perr_cap1;	/* 0x8e2c - PEX Error Capture Register 1 */
+	uint	perr_cap2;	/* 0x8e30 - PEX Error Capture Register 2 */
+	uint	perr_cap3;	/* 0x8e34 - PEX Error Capture Register 3 */
+	char	res25[452];
+	char    res26[4];
+} ccsr_pex_t;
+
+/* Hyper Transport Register Block (0xA000-0xB000) */
+typedef struct ccsr_ht {
+	uint    hcfg_addr;      /* 0xa000 - HT Configuration Address register */
+	uint    hcfg_data;      /* 0xa004 - HT Configuration Data register */
+	char	res1[3064];
+	uint    howtar0;        /* 0xac00 - HT Outbound Window 0 Translation register */
+	char	res2[12];
+	uint    howar0;         /* 0xac10 - HT Outbound Window 0 Attributes register */
+	char	res3[12];
+	uint    howtar1;        /* 0xac20 - HT Outbound Window 1 Translation register */
+	char	res4[4];
+	uint    howbar1;        /* 0xac28 - HT Outbound Window 1 Base Address register */
+	char	res5[4];
+	uint    howar1;         /* 0xac30 - HT Outbound Window 1 Attributes register */
+	char	res6[12];
+	uint    howtar2;        /* 0xac40 - HT Outbound Window 2 Translation register */
+	char	res7[4];
+	uint    howbar2;        /* 0xac48 - HT Outbound Window 2 Base Address register */
+	char	res8[4];
+	uint    howar2;         /* 0xac50 - HT Outbound Window 2 Attributes register */
+	char	res9[12];
+	uint    howtar3;        /* 0xac60 - HT Outbound Window 3 Translation register */
+	char	res10[4];
+	uint    howbar3;        /* 0xac68 - HT Outbound Window 3 Base Address register */
+	char	res11[4];
+	uint    howar3;         /* 0xac70 - HT Outbound Window 3 Attributes  register */
+	char	res12[12];
+	uint    howtar4;        /* 0xac80 - HT Outbound Window 4 Translation register */
+	char	res13[4];
+	uint    howbar4;        /* 0xac88 - HT Outbound Window 4 Base Address register */
+	char	res14[4];
+	uint    howar4;         /* 0xac90 - HT Outbound Window 4 Attributes register */
+	char	res15[236];
+	uint    hiwtar4;        /* 0xad80 - HT Inbound Window 4 Translation register */
+	char	res16[4];
+	uint    hiwbar4;        /* 0xad88 - HT Inbound Window 4 Base Address register */
+	char	res17[4];
+	uint    hiwar4;         /* 0xad90 - HT Inbound Window 4 Attributes register */
+	char	res18[12];
+	uint    hiwtar3;        /* 0xada0 - HT Inbound Window 3 Translation register */
+	char	res19[4];
+	uint    hiwbar3;        /* 0xada8 - HT Inbound Window 3 Base Address register */
+	char	res20[4];
+	uint    hiwar3;         /* 0xadb0 - HT Inbound Window 3 Attributes register */
+	char	res21[12];
+	uint    hiwtar2;        /* 0xadc0 - HT Inbound Window 2 Translation register */
+	char	res22[4];
+	uint    hiwbar2;        /* 0xadc8 - HT Inbound Window 2 Base Address register */
+	char	res23[4];
+	uint    hiwar2;         /* 0xadd0 - HT Inbound Window 2 Attributes register */
+	char	res24[12];
+	uint    hiwtar1;        /* 0xade0 - HT Inbound Window 1 Translation register */
+	char	res25[4];
+	uint    hiwbar1;        /* 0xade8 - HT Inbound Window 1 Base Address register */
+	char	res26[4];
+	uint    hiwar1;         /* 0xadf0 - HT Inbound Window 1 Attributes register */
+	char	res27[12];
+	uint    hedr;           /* 0xae00 - HT Error Detect register */
+	char	res28[4];
+	uint    heier;          /* 0xae08 - HT Error Interrupt Enable register */
+	char	res29[4];
+	uint    hecdr;          /* 0xae10 - HT Error Capture Disbale register */
+	char	res30[12];
+	uint    hecsr;          /* 0xae20 - HT Error Capture Status register */
+	char	res31[4];
+	uint    hec0;           /* 0xae28 - HT Error Capture 0 register */
+	uint    hec1;           /* 0xae2c - HT Error Capture 1 register */
+	uint    hec2;           /* 0xae30 - HT Error Capture 2 register */
+	char    res32[460];
+} ccsr_ht_t;
+
+/* DMA Registers(0x2_1000-0x2_2000) */
+typedef struct ccsr_dma {
+	char	res1[256];
+	uint	mr0;		/* 0x21100 - DMA 0 Mode Register */
+	uint	sr0;		/* 0x21104 - DMA 0 Status Register */
+	char	res2[4];
+	uint	clndar0;	/* 0x2110c - DMA 0 Current Link Descriptor Address Register */
+	uint	satr0;		/* 0x21110 - DMA 0 Source Attributes Register */
+	uint	sar0;		/* 0x21114 - DMA 0 Source Address Register */
+	uint	datr0;		/* 0x21118 - DMA 0 Destination Attributes Register */
+	uint	dar0;		/* 0x2111c - DMA 0 Destination Address Register */
+	uint	bcr0;		/* 0x21120 - DMA 0 Byte Count Register */
+	char	res3[4];
+	uint	nlndar0;	/* 0x21128 - DMA 0 Next Link Descriptor Address Register */
+	char	res4[8];
+	uint	clabdar0;	/* 0x21134 - DMA 0 Current List - Alternate Base Descriptor Address Register */
+	char	res5[4];
+	uint	nlsdar0;	/* 0x2113c - DMA 0 Next List Descriptor Address Register */
+	uint	ssr0;		/* 0x21140 - DMA 0 Source Stride Register */
+	uint	dsr0;		/* 0x21144 - DMA 0 Destination Stride Register */
+	char	res6[56];
+	uint	mr1;		/* 0x21180 - DMA 1 Mode Register */
+	uint	sr1;		/* 0x21184 - DMA 1 Status Register */
+	char	res7[4];
+	uint	clndar1;	/* 0x2118c - DMA 1 Current Link Descriptor Address Register */
+	uint	satr1;		/* 0x21190 - DMA 1 Source Attributes Register */
+	uint	sar1;		/* 0x21194 - DMA 1 Source Address Register */
+	uint	datr1;		/* 0x21198 - DMA 1 Destination Attributes Register */
+	uint	dar1;		/* 0x2119c - DMA 1 Destination Address Register */
+	uint	bcr1;		/* 0x211a0 - DMA 1 Byte Count Register */
+	char	res8[4];
+	uint	nlndar1;	/* 0x211a8 - DMA 1 Next Link Descriptor Address Register */
+	char	res9[8];
+	uint	clabdar1;	/* 0x211b4 - DMA 1 Current List - Alternate Base Descriptor Address Register */
+	char	res10[4];
+	uint	nlsdar1;	/* 0x211bc - DMA 1 Next List Descriptor Address Register */
+	uint	ssr1;		/* 0x211c0 - DMA 1 Source Stride Register */
+	uint	dsr1;		/* 0x211c4 - DMA 1 Destination Stride Register */
+	char	res11[56];
+	uint	mr2;		/* 0x21200 - DMA 2 Mode Register */
+	uint	sr2;		/* 0x21204 - DMA 2 Status Register */
+	char	res12[4];
+	uint	clndar2;	/* 0x2120c - DMA 2 Current Link Descriptor Address Register */
+	uint	satr2;		/* 0x21210 - DMA 2 Source Attributes Register */
+	uint	sar2;		/* 0x21214 - DMA 2 Source Address Register */
+	uint	datr2;		/* 0x21218 - DMA 2 Destination Attributes Register */
+	uint	dar2;		/* 0x2121c - DMA 2 Destination Address Register */
+	uint	bcr2;		/* 0x21220 - DMA 2 Byte Count Register */
+	char	res13[4];
+	uint	nlndar2;	/* 0x21228 - DMA 2 Next Link Descriptor Address Register */
+	char	res14[8];
+	uint	clabdar2;	/* 0x21234 - DMA 2 Current List - Alternate Base Descriptor Address Register */
+	char	res15[4];
+	uint	nlsdar2;	/* 0x2123c - DMA 2 Next List Descriptor Address Register */
+	uint	ssr2;		/* 0x21240 - DMA 2 Source Stride Register */
+	uint	dsr2;		/* 0x21244 - DMA 2 Destination Stride Register */
+	char	res16[56];
+	uint	mr3;		/* 0x21280 - DMA 3 Mode Register */
+	uint	sr3;		/* 0x21284 - DMA 3 Status Register */
+	char	res17[4];
+	uint	clndar3;	/* 0x2128c - DMA 3 Current Link Descriptor Address Register */
+	uint	satr3;		/* 0x21290 - DMA 3 Source Attributes Register */
+	uint	sar3;		/* 0x21294 - DMA 3 Source Address Register */
+	uint	datr3;		/* 0x21298 - DMA 3 Destination Attributes Register */
+	uint	dar3;		/* 0x2129c - DMA 3 Destination Address Register */
+	uint	bcr3;		/* 0x212a0 - DMA 3 Byte Count Register */
+	char	res18[4];
+	uint	nlndar3;	/* 0x212a8 - DMA 3 Next Link Descriptor Address Register */
+	char	res19[8];
+	uint	clabdar3;	/* 0x212b4 - DMA 3 Current List - Alternate Base Descriptor Address Register */
+	char	res20[4];
+	uint	nlsdar3;	/* 0x212bc - DMA 3 Next List Descriptor Address Register */
+	uint	ssr3;		/* 0x212c0 - DMA 3 Source Stride Register */
+	uint	dsr3;		/* 0x212c4 - DMA 3 Destination Stride Register */
+	char	res21[56];
+	uint	dgsr;		/* 0x21300 - DMA General Status Register */
+	char	res22[3324];
+} ccsr_dma_t;
+
+/* tsec1-4: 24000-28000 */
+typedef struct ccsr_tsec {
+	uint    id; 		/* 0x24000 - Controller ID Register */
+	char	res1[12];
+	uint	ievent;		/* 0x24010 - Interrupt Event Register */
+	uint	imask;		/* 0x24014 - Interrupt Mask Register */
+	uint	edis;		/* 0x24018 - Error Disabled Register */
+	char	res2[4];
+	uint	ecntrl;		/* 0x24020 - Ethernet Control Register */
+	char    res2_1[4];
+	uint	ptv;		/* 0x24028 - Pause Time Value Register */
+	uint	dmactrl;	/* 0x2402c - DMA Control Register */
+	uint	tbipa;		/* 0x24030 - TBI PHY Address Register */
+	char	res3[88];
+	uint	fifo_tx_thr;	/* 0x2408c - FIFO transmit threshold register */
+	char	res4[8];
+	uint	fifo_tx_starve;	/* 0x24098 - FIFO transmit starve register */
+	uint	fifo_tx_starve_shutoff;/* 0x2409c - FIFO transmit starve shutoff register */
+	char    res4_1[4];
+	uint    fifo_rx_pause;  /* 0x240a4 - FIFO receive pause threshold register */
+	uint    fifo_rx_alarm;  /* 0x240a8 - FIFO receive alarm threshold register */
+	char	res5[84];
+	uint	tctrl;		/* 0x24100 - Transmit Control Register */
+	uint	tstat;		/* 0x24104 - Transmit Status Register */
+	uint    dfvlan;		/* 0x24108 - Default VLAN control word */
+	char    res6[4];
+	uint    txic;		/* 0x24110 - Transmit interrupt coalescing Register */
+	uint    tqueue;         /* 0x24114 - Transmit Queue Control Register */
+	char	res7[40];
+	uint    tr03wt;         /* 0x24140 - TxBD Rings 0-3 round-robin weightings */
+	uint    tw47wt;         /* 0x24144 - TxBD Rings 4-7 round-robin weightings */
+	char    res8[52];
+	uint	tbdbph;	        /* 0x2417c - Transmit Data Buffer Pointer High Register */
+	char    res9[4];
+	uint    tbptr0;         /* 0x24184 - Transmit Buffer Descriptor Pointer for Ring 0 */
+	char    res10[4];
+	uint    tbptr1;         /* 0x2418C - Transmit Buffer Descriptor Pointer for Ring 1 */
+	char    res11[4];
+	uint    tbptr2;         /* 0x24194 - Transmit Buffer Descriptor Pointer for Ring 2 */
+	char    res12[4];
+	uint    tbptr3;         /* 0x2419C - Transmit Buffer Descriptor Pointer for Ring 3 */
+	char    res13[4];
+	uint    tbptr4;         /* 0x241A4 - Transmit Buffer Descriptor Pointer for Ring 4 */
+	char    res14[4];
+	uint    tbptr5;         /* 0x241AC - Transmit Buffer Descriptor Pointer for Ring 5 */
+	char    res15[4];
+	uint    tbptr6;         /* 0x241B4 - Transmit Buffer Descriptor Pointer for Ring 6 */
+	char    res16[4];
+	uint    tbptr7;         /* 0x241BC - Transmit Buffer Descriptor Pointer for Ring 7 */
+	char    res17[64];
+	uint	tbaseh;		/* 0x24200 - Transmit Descriptor Base Address High Register */
+	uint	tbase0;		/* 0x24204 - Transmit Descriptor Base Address Register of Ring 0 */
+	char    res18[4];
+	uint    tbase1;         /* 0x2420C - Transmit Descriptor base address of Ring 1 */
+	char    res19[4];
+	uint    tbase2;         /* 0x24214 - Transmit Descriptor base address of Ring 2 */
+	char    res20[4];
+	uint    tbase3;         /* 0x2421C - Transmit Descriptor base address of Ring 3 */
+	char    res21[4];
+	uint    tbase4;         /* 0x24224 - Transmit Descriptor base address of Ring 4 */
+	char    res22[4];
+	uint    tbase5;         /* 0x2422C - Transmit Descriptor base address of Ring 5 */
+	char    res23[4];
+	uint    tbase6;         /* 0x24234 - Transmit Descriptor base address of Ring 6 */
+	char    res24[4];
+	uint    tbase7;         /* 0x2423C - Transmit Descriptor base address of Ring 7 */
+	char    res25[192];
+	uint	rctrl;		/* 0x24300 - Receive Control Register */
+	uint	rstat;		/* 0x24304 - Receive Status Register */
+	char	res26[8];
+	uint    rxic;           /* 0x24310 - Receive Interrupt Coalecing Register */
+	uint    rqueue;         /* 0x24314 - Receive queue control register */
+	char	res27[24];
+	uint    rbifx;		/* 0x24330 - Receive bit field extract control Register */
+	uint    rqfar;		/* 0x24334 - Receive queue filing table address Register */
+	uint    rqfcr;		/* 0x24338 - Receive queue filing table control Register */
+	uint    rqfpr;      	/* 0x2433c - Receive queue filing table property Register */
+	uint	mrblr;		/* 0x24340 - Maximum Receive Buffer Length Register */
+	char	res28[56];
+	uint    rbdbph;		/* 0x2437C - Receive Data Buffer Pointer High */
+	char    res29[4];
+	uint	rbptr0;		/* 0x24384 - Receive Buffer Descriptor Pointer for Ring 0 */
+	char    res30[4];
+	uint	rbptr1;		/* 0x2438C - Receive Buffer Descriptor Pointer for Ring 1 */
+	char    res31[4];
+	uint	rbptr2;		/* 0x24394 - Receive Buffer Descriptor Pointer for Ring 2 */
+	char    res32[4];
+	uint	rbptr3;		/* 0x2439C - Receive Buffer Descriptor Pointer for Ring 3 */
+	char    res33[4];
+	uint	rbptr4;		/* 0x243A4 - Receive Buffer Descriptor Pointer for Ring 4 */
+	char    res34[4];
+	uint	rbptr5;		/* 0x243AC - Receive Buffer Descriptor Pointer for Ring 5 */
+	char    res35[4];
+	uint	rbptr6;		/* 0x243B4 - Receive Buffer Descriptor Pointer for Ring 6 */
+	char    res36[4];
+	uint	rbptr7;		/* 0x243BC - Receive Buffer Descriptor Pointer for Ring 7 */
+	char    res37[64];
+	uint	rbaseh;		/* 0x24400 - Receive Descriptor Base Address High 0 */
+	uint	rbase0;		/* 0x24404 - Receive Descriptor Base Address of Ring 0 */
+	char    res38[4];
+	uint	rbase1;		/* 0x2440C - Receive Descriptor Base Address of Ring 1 */
+	char    res39[4];
+	uint	rbase2;		/* 0x24414 - Receive Descriptor Base Address of Ring 2 */
+	char    res40[4];
+	uint	rbase3;		/* 0x2441C - Receive Descriptor Base Address of Ring 3 */
+	char    res41[4];
+	uint	rbase4;		/* 0x24424 - Receive Descriptor Base Address of Ring 4 */
+	char    res42[4];
+	uint	rbase5;		/* 0x2442C - Receive Descriptor Base Address of Ring 5 */
+	char    res43[4];
+	uint	rbase6;		/* 0x24434 - Receive Descriptor Base Address of Ring 6 */
+	char    res44[4];
+	uint	rbase7;		/* 0x2443C - Receive Descriptor Base Address of Ring 7 */
+	char    res45[192];
+	uint	maccfg1;	/* 0x24500 - MAC Configuration 1 Register */
+	uint	maccfg2;	/* 0x24504 - MAC Configuration 2 Register */
+	uint	ipgifg;		/* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */
+	uint	hafdup;		/* 0x2450c - Half Duplex Register */
+	uint	maxfrm;		/* 0x24510 - Maximum Frame Length Register */
+	char	res46[12];
+	uint	miimcfg;	/* 0x24520 - MII Management Configuration Register */
+	uint	miimcom;	/* 0x24524 - MII Management Command Register */
+	uint	miimadd;	/* 0x24528 - MII Management Address Register */
+	uint	miimcon;	/* 0x2452c - MII Management Control Register */
+	uint	miimstat;	/* 0x24530 - MII Management Status Register */
+	uint	miimind;	/* 0x24534 - MII Management Indicator Register */
+	uint    ifctrl;		/* 0x24538 - Interface Contrl Register */
+	uint	ifstat;		/* 0x2453c - Interface Status Register */
+	uint	macstnaddr1;	/* 0x24540 - Station Address Part 1 Register */
+	uint	macstnaddr2;	/* 0x24544 - Station Address Part 2 Register */
+	uint    mac01addr1;     /* 0x24548 - MAC exact match address 1, part 1 */
+	uint    mac01addr2;     /* 0x2454C - MAC exact match address 1, part 2 */
+	uint    mac02addr1;     /* 0x24550 - MAC exact match address 2, part 1 */
+	uint    mac02addr2;     /* 0x24554 - MAC exact match address 2, part 2 */
+	uint    mac03addr1;     /* 0x24558 - MAC exact match address 3, part 1 */
+	uint    mac03addr2;     /* 0x2455C - MAC exact match address 3, part 2 */
+	uint    mac04addr1;     /* 0x24560 - MAC exact match address 4, part 1 */
+	uint    mac04addr2;     /* 0x24564 - MAC exact match address 4, part 2 */
+	uint    mac05addr1;     /* 0x24568 - MAC exact match address 5, part 1 */
+	uint    mac05addr2;     /* 0x2456C - MAC exact match address 5, part 2 */
+	uint    mac06addr1;     /* 0x24570 - MAC exact match address 6, part 1 */
+	uint    mac06addr2;     /* 0x24574 - MAC exact match address 6, part 2 */
+	uint    mac07addr1;     /* 0x24578 - MAC exact match address 7, part 1 */
+	uint    mac07addr2;     /* 0x2457C - MAC exact match address 7, part 2 */
+	uint    mac08addr1;     /* 0x24580 - MAC exact match address 8, part 1 */
+	uint    mac08addr2;     /* 0x24584 - MAC exact match address 8, part 2 */
+	uint    mac09addr1;     /* 0x24588 - MAC exact match address 9, part 1 */
+	uint    mac09addr2;     /* 0x2458C - MAC exact match address 9, part 2 */
+	uint    mac10addr1;     /* 0x24590 - MAC exact match address 10, part 1 */
+	uint    mac10addr2;     /* 0x24594 - MAC exact match address 10, part 2 */
+	uint    mac11addr1;     /* 0x24598 - MAC exact match address 11, part 1 */
+	uint    mac11addr2;     /* 0x2459C - MAC exact match address 11, part 2 */
+	uint    mac12addr1;     /* 0x245A0 - MAC exact match address 12, part 1 */
+	uint    mac12addr2;     /* 0x245A4 - MAC exact match address 12, part 2 */
+	uint    mac13addr1;     /* 0x245A8 - MAC exact match address 13, part 1 */
+	uint    mac13addr2;     /* 0x245AC - MAC exact match address 13, part 2 */
+	uint    mac14addr1;     /* 0x245B0 - MAC exact match address 14, part 1 */
+	uint    mac14addr2;     /* 0x245B4 - MAC exact match address 14, part 2 */
+	uint    mac15addr1;     /* 0x245B8 - MAC exact match address 15, part 1 */
+	uint    mac15addr2;     /* 0x245BC - MAC exact match address 15, part 2 */
+	char	res48[192];
+	uint	tr64;		/* 0x24680 - Transmit and Receive 64-byte Frame Counter */
+	uint	tr127;		/* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */
+	uint	tr255;		/* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */
+	uint	tr511;		/* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */
+	uint	tr1k;		/* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */
+	uint	trmax;		/* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */
+	uint	trmgv;		/* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
+	uint	rbyt;		/* 0x2469c - Receive Byte Counter */
+	uint	rpkt;		/* 0x246a0 - Receive Packet Counter */
+	uint	rfcs;		/* 0x246a4 - Receive FCS Error Counter */
+	uint	rmca;		/* 0x246a8 - Receive Multicast Packet Counter */
+	uint	rbca;		/* 0x246ac - Receive Broadcast Packet Counter */
+	uint	rxcf;		/* 0x246b0 - Receive Control Frame Packet Counter */
+	uint	rxpf;		/* 0x246b4 - Receive Pause Frame Packet Counter */
+	uint	rxuo;		/* 0x246b8 - Receive Unknown OP Code Counter */
+	uint	raln;		/* 0x246bc - Receive Alignment Error Counter */
+	uint	rflr;		/* 0x246c0 - Receive Frame Length Error Counter */
+	uint	rcde;		/* 0x246c4 - Receive Code Error Counter */
+	uint	rcse;		/* 0x246c8 - Receive Carrier Sense Error Counter */
+	uint	rund;		/* 0x246cc - Receive Undersize Packet Counter */
+	uint	rovr;		/* 0x246d0 - Receive Oversize Packet Counter */
+	uint	rfrg;		/* 0x246d4 - Receive Fragments Counter */
+	uint	rjbr;		/* 0x246d8 - Receive Jabber Counter */
+	uint	rdrp;		/* 0x246dc - Receive Drop Counter */
+	uint	tbyt;		/* 0x246e0 - Transmit Byte Counter Counter */
+	uint	tpkt;		/* 0x246e4 - Transmit Packet Counter */
+	uint	tmca;		/* 0x246e8 - Transmit Multicast Packet Counter */
+	uint	tbca;		/* 0x246ec - Transmit Broadcast Packet Counter */
+	uint	txpf;		/* 0x246f0 - Transmit Pause Control Frame Counter */
+	uint	tdfr;		/* 0x246f4 - Transmit Deferral Packet Counter */
+	uint	tedf;		/* 0x246f8 - Transmit Excessive Deferral Packet Counter */
+	uint	tscl;		/* 0x246fc - Transmit Single Collision Packet Counter */
+	uint	tmcl;		/* 0x24700 - Transmit Multiple Collision Packet Counter */
+	uint	tlcl;		/* 0x24704 - Transmit Late Collision Packet Counter */
+	uint	txcl;		/* 0x24708 - Transmit Excessive Collision Packet Counter */
+	uint	tncl;		/* 0x2470c - Transmit Total Collision Counter */
+	char	res49[4];
+	uint	tdrp;		/* 0x24714 - Transmit Drop Frame Counter */
+	uint	tjbr;		/* 0x24718 - Transmit Jabber Frame Counter */
+	uint	tfcs;		/* 0x2471c - Transmit FCS Error Counter */
+	uint	txcf;		/* 0x24720 - Transmit Control Frame Counter */
+	uint	tovr;		/* 0x24724 - Transmit Oversize Frame Counter */
+	uint	tund;		/* 0x24728 - Transmit Undersize Frame Counter */
+	uint	tfrg;		/* 0x2472c - Transmit Fragments Frame Counter */
+	uint	car1;		/* 0x24730 - Carry Register One */
+	uint	car2;		/* 0x24734 - Carry Register Two */
+	uint	cam1;		/* 0x24738 - Carry Mask Register One */
+	uint	cam2;		/* 0x2473c - Carry Mask Register Two */
+	uint    rrej;	        /* 0x24740 - Receive filer rejected packet counter */
+	char	res50[188];
+	uint	iaddr0;		/* 0x24800 - Indivdual address register 0 */
+	uint	iaddr1;		/* 0x24804 - Indivdual address register 1 */
+	uint	iaddr2;		/* 0x24808 - Indivdual address register 2 */
+	uint	iaddr3;		/* 0x2480c - Indivdual address register 3 */
+	uint	iaddr4;		/* 0x24810 - Indivdual address register 4 */
+	uint	iaddr5;		/* 0x24814 - Indivdual address register 5 */
+	uint	iaddr6;		/* 0x24818 - Indivdual address register 6 */
+	uint	iaddr7;		/* 0x2481c - Indivdual address register 7 */
+	char	res51[96];
+	uint	gaddr0;		/* 0x24880 - Global address register 0 */
+	uint	gaddr1;		/* 0x24884 - Global address register 1 */
+	uint	gaddr2;		/* 0x24888 - Global address register 2 */
+	uint	gaddr3;		/* 0x2488c - Global address register 3 */
+	uint	gaddr4;		/* 0x24890 - Global address register 4 */
+	uint	gaddr5;		/* 0x24894 - Global address register 5 */
+	uint	gaddr6;		/* 0x24898 - Global address register 6 */
+	uint	gaddr7;		/* 0x2489c - Global address register 7 */
+	char	res52[352];
+	uint    fifocfg;        /* 0x24A00 - FIFO interface configuration register */
+	char    res53[500];
+	uint    attr;           /* 0x24BF8 - DMA Attribute register */
+	uint    attreli;        /* 0x24BFC - DMA Attribute extract length and index register */
+	char    res54[1024];
+} ccsr_tsec_t;
+
+/* PIC Registers(0x4_0000-0x6_1000) */
+
+typedef struct ccsr_pic {
+	char	res1[64];
+	uint	ipidr0;		/* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */
+	char	res2[12];
+	uint	ipidr1;		/* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */
+	char	res3[12];
+	uint	ipidr2;		/* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */
+	char	res4[12];
+	uint	ipidr3;		/* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */
+	char	res5[12];
+	uint	ctpr;		/* 0x40080 - Current Task Priority Register */
+	char	res6[12];
+	uint	whoami;		/* 0x40090 - Who Am I Register */
+	char	res7[12];
+	uint	iack;		/* 0x400a0 - Interrupt Acknowledge Register */
+	char	res8[12];
+	uint	eoi;		/* 0x400b0 - End Of Interrupt Register */
+	char	res9[3916];
+	uint	frr;		/* 0x41000 - Feature Reporting Register */
+	char	res10[28];
+	uint	gcr;		/* 0x41020 - Global Configuration Register */
+	char	res11[92];
+	uint	vir;		/* 0x41080 - Vendor Identification Register */
+	char	res12[12];
+	uint	pir;		/* 0x41090 - Processor Initialization Register */
+	char	res13[12];
+	uint	ipivpr0;	/* 0x410a0 - IPI Vector/Priority Register 0 */
+	char	res14[12];
+	uint	ipivpr1;	/* 0x410b0 - IPI Vector/Priority Register 1 */
+	char	res15[12];
+	uint	ipivpr2;	/* 0x410c0 - IPI Vector/Priority Register 2 */
+	char	res16[12];
+	uint	ipivpr3;	/* 0x410d0 - IPI Vector/Priority Register 3 */
+	char	res17[12];
+	uint	svr;		/* 0x410e0 - Spurious Vector Register */
+	char	res18[12];
+	uint	tfrr;		/* 0x410f0 - Timer Frequency Reporting Register */
+	char	res19[12];
+	uint	gtccr0;		/* 0x41100 - Global Timer Current Count Register 0 */
+	char	res20[12];
+	uint	gtbcr0;		/* 0x41110 - Global Timer Base Count Register 0 */
+	char	res21[12];
+	uint	gtvpr0;		/* 0x41120 - Global Timer Vector/Priority Register 0 */
+	char	res22[12];
+	uint	gtdr0;		/* 0x41130 - Global Timer Destination Register 0 */
+	char	res23[12];
+	uint	gtccr1;		/* 0x41140 - Global Timer Current Count Register 1 */
+	char	res24[12];
+	uint	gtbcr1;		/* 0x41150 - Global Timer Base Count Register 1 */
+	char	res25[12];
+	uint	gtvpr1;		/* 0x41160 - Global Timer Vector/Priority Register 1 */
+	char	res26[12];
+	uint	gtdr1;		/* 0x41170 - Global Timer Destination Register 1 */
+	char	res27[12];
+	uint	gtccr2;		/* 0x41180 - Global Timer Current Count Register 2 */
+	char	res28[12];
+	uint	gtbcr2;		/* 0x41190 - Global Timer Base Count Register 2 */
+	char	res29[12];
+	uint	gtvpr2;		/* 0x411a0 - Global Timer Vector/Priority Register 2 */
+	char	res30[12];
+	uint	gtdr2;		/* 0x411b0 - Global Timer Destination Register 2 */
+	char	res31[12];
+	uint	gtccr3;		/* 0x411c0 - Global Timer Current Count Register 3 */
+	char	res32[12];
+	uint	gtbcr3;		/* 0x411d0 - Global Timer Base Count Register 3 */
+	char	res33[12];
+	uint	gtvpr3;		/* 0x411e0 - Global Timer Vector/Priority Register 3 */
+	char	res34[12];
+	uint	gtdr3;		/* 0x411f0 - Global Timer Destination Register 3 */
+	char	res35[268];
+	uint	tcr;		/* 0x41300 - Timer Control Register */
+	char	res36[12];
+	uint	irqsr0;		/* 0x41310 - IRQ_OUT Summary Register 0 */
+	char	res37[12];
+	uint	irqsr1;		/* 0x41320 - IRQ_OUT Summary Register 1 */
+	char	res38[12];
+	uint	cisr0;		/* 0x41330 - Critical Interrupt Summary Register 0 */
+	char	res39[12];
+	uint	cisr1;		/* 0x41340 - Critical Interrupt Summary Register 1 */
+	char	res40[12];
+	uint	pm0mr0;		/* 0x41350 - Performance monitor 0 mask register 0  */
+	char	res41[12];
+	uint	pm0mr1;		/* 0x41360 - Performance monitor 0 mask register 1  */
+	char	res42[12];
+	uint	pm1mr0;		/* 0x41370 - Performance monitor 1 mask register 0  */
+	char	res43[12];
+	uint	pm1mr1;		/* 0x41380 - Performance monitor 1 mask register 1  */
+	char	res44[12];
+	uint	pm2mr0;		/* 0x41390 - Performance monitor 2 mask register 0  */
+	char	res45[12];
+	uint	pm2mr1;		/* 0x413A0 - Performance monitor 2 mask register 1  */
+	char	res46[12];
+	uint	pm3mr0;		/* 0x413B0 - Performance monitor 3 mask register 0  */
+	char	res47[12];
+	uint	pm3mr1;		/* 0x413C0 - Performance monitor 3 mask register 1  */
+	char	res48[60];
+	uint	msgr0;		/* 0x41400 - Message Register 0 */
+	char	res49[12];
+	uint	msgr1;		/* 0x41410 - Message Register 1 */
+	char	res50[12];
+	uint	msgr2;		/* 0x41420 - Message Register 2 */
+	char	res51[12];
+	uint	msgr3;		/* 0x41430 - Message Register 3 */
+	char	res52[204];
+	uint	mer;		/* 0x41500 - Message Enable Register */
+	char	res53[12];
+	uint	msr;		/* 0x41510 - Message Status Register */
+	char	res54[60140];
+	uint	eivpr0;		/* 0x50000 - External Interrupt Vector/Priority Register 0 */
+	char	res55[12];
+	uint	eidr0;		/* 0x50010 - External Interrupt Destination Register 0 */
+	char	res56[12];
+	uint	eivpr1;		/* 0x50020 - External Interrupt Vector/Priority Register 1 */
+	char	res57[12];
+	uint	eidr1;		/* 0x50030 - External Interrupt Destination Register 1 */
+	char	res58[12];
+	uint	eivpr2;		/* 0x50040 - External Interrupt Vector/Priority Register 2 */
+	char	res59[12];
+	uint	eidr2;		/* 0x50050 - External Interrupt Destination Register 2 */
+	char	res60[12];
+	uint	eivpr3;		/* 0x50060 - External Interrupt Vector/Priority Register 3 */
+	char	res61[12];
+	uint	eidr3;		/* 0x50070 - External Interrupt Destination Register 3 */
+	char	res62[12];
+	uint	eivpr4;		/* 0x50080 - External Interrupt Vector/Priority Register 4 */
+	char	res63[12];
+	uint	eidr4;		/* 0x50090 - External Interrupt Destination Register 4 */
+	char	res64[12];
+	uint	eivpr5;		/* 0x500a0 - External Interrupt Vector/Priority Register 5 */
+	char	res65[12];
+	uint	eidr5;		/* 0x500b0 - External Interrupt Destination Register 5 */
+	char	res66[12];
+	uint	eivpr6;		/* 0x500c0 - External Interrupt Vector/Priority Register 6 */
+	char	res67[12];
+	uint	eidr6;		/* 0x500d0 - External Interrupt Destination Register 6 */
+	char	res68[12];
+	uint	eivpr7;		/* 0x500e0 - External Interrupt Vector/Priority Register 7 */
+	char	res69[12];
+	uint	eidr7;		/* 0x500f0 - External Interrupt Destination Register 7 */
+	char	res70[12];
+	uint	eivpr8;		/* 0x50100 - External Interrupt Vector/Priority Register 8 */
+	char	res71[12];
+	uint	eidr8;		/* 0x50110 - External Interrupt Destination Register 8 */
+	char	res72[12];
+	uint	eivpr9;		/* 0x50120 - External Interrupt Vector/Priority Register 9 */
+	char	res73[12];
+	uint	eidr9;		/* 0x50130 - External Interrupt Destination Register 9 */
+	char	res74[12];
+	uint	eivpr10;	/* 0x50140 - External Interrupt Vector/Priority Register 10 */
+	char	res75[12];
+	uint	eidr10;		/* 0x50150 - External Interrupt Destination Register 10 */
+	char	res76[12];
+	uint	eivpr11;	/* 0x50160 - External Interrupt Vector/Priority Register 11 */
+	char	res77[12];
+	uint	eidr11;		/* 0x50170 - External Interrupt Destination Register 11 */
+	char	res78[140];
+	uint	iivpr0;		/* 0x50200 - Internal Interrupt Vector/Priority Register 0 */
+	char	res79[12];
+	uint	iidr0;		/* 0x50210 - Internal Interrupt Destination Register 0 */
+	char	res80[12];
+	uint	iivpr1;		/* 0x50220 - Internal Interrupt Vector/Priority Register 1 */
+	char	res81[12];
+	uint	iidr1;		/* 0x50230 - Internal Interrupt Destination Register 1 */
+	char	res82[12];
+	uint	iivpr2;		/* 0x50240 - Internal Interrupt Vector/Priority Register 2 */
+	char	res83[12];
+	uint	iidr2;		/* 0x50250 - Internal Interrupt Destination Register 2 */
+	char	res84[12];
+	uint	iivpr3;		/* 0x50260 - Internal Interrupt Vector/Priority Register 3 */
+	char	res85[12];
+	uint	iidr3;		/* 0x50270 - Internal Interrupt Destination Register 3 */
+	char	res86[12];
+	uint	iivpr4;		/* 0x50280 - Internal Interrupt Vector/Priority Register 4 */
+	char	res87[12];
+	uint	iidr4;		/* 0x50290 - Internal Interrupt Destination Register 4 */
+	char	res88[12];
+	uint	iivpr5;		/* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */
+	char	res89[12];
+	uint	iidr5;		/* 0x502b0 - Internal Interrupt Destination Register 5 */
+	char	res90[12];
+	uint	iivpr6;		/* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */
+	char	res91[12];
+	uint	iidr6;		/* 0x502d0 - Internal Interrupt Destination Register 6 */
+	char	res92[12];
+	uint	iivpr7;		/* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */
+	char	res93[12];
+	uint	iidr7;		/* 0x502f0 - Internal Interrupt Destination Register 7 */
+	char	res94[12];
+	uint	iivpr8;		/* 0x50300 - Internal Interrupt Vector/Priority Register 8 */
+	char	res95[12];
+	uint	iidr8;		/* 0x50310 - Internal Interrupt Destination Register 8 */
+	char	res96[12];
+	uint	iivpr9;		/* 0x50320 - Internal Interrupt Vector/Priority Register 9 */
+	char	res97[12];
+	uint	iidr9;		/* 0x50330 - Internal Interrupt Destination Register 9 */
+	char	res98[12];
+	uint	iivpr10;	/* 0x50340 - Internal Interrupt Vector/Priority Register 10 */
+	char	res99[12];
+	uint	iidr10;		/* 0x50350 - Internal Interrupt Destination Register 10 */
+	char	res100[12];
+	uint	iivpr11;	/* 0x50360 - Internal Interrupt Vector/Priority Register 11 */
+	char	res101[12];
+	uint	iidr11;		/* 0x50370 - Internal Interrupt Destination Register 11 */
+	char	res102[12];
+	uint	iivpr12;	/* 0x50380 - Internal Interrupt Vector/Priority Register 12 */
+	char	res103[12];
+	uint	iidr12;		/* 0x50390 - Internal Interrupt Destination Register 12 */
+	char	res104[12];
+	uint	iivpr13;	/* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */
+	char	res105[12];
+	uint	iidr13;		/* 0x503b0 - Internal Interrupt Destination Register 13 */
+	char	res106[12];
+	uint	iivpr14;	/* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */
+	char	res107[12];
+	uint	iidr14;		/* 0x503d0 - Internal Interrupt Destination Register 14 */
+	char	res108[12];
+	uint	iivpr15;	/* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */
+	char	res109[12];
+	uint	iidr15;		/* 0x503f0 - Internal Interrupt Destination Register 15 */
+	char	res110[12];
+	uint	iivpr16;	/* 0x50400 - Internal Interrupt Vector/Priority Register 16 */
+	char	res111[12];
+	uint	iidr16;		/* 0x50410 - Internal Interrupt Destination Register 16 */
+	char	res112[12];
+	uint	iivpr17;	/* 0x50420 - Internal Interrupt Vector/Priority Register 17 */
+	char	res113[12];
+	uint	iidr17;		/* 0x50430 - Internal Interrupt Destination Register 17 */
+	char	res114[12];
+	uint	iivpr18;	/* 0x50440 - Internal Interrupt Vector/Priority Register 18 */
+	char	res115[12];
+	uint	iidr18;		/* 0x50450 - Internal Interrupt Destination Register 18 */
+	char	res116[12];
+	uint	iivpr19;	/* 0x50460 - Internal Interrupt Vector/Priority Register 19 */
+	char	res117[12];
+	uint	iidr19;		/* 0x50470 - Internal Interrupt Destination Register 19 */
+	char	res118[12];
+	uint	iivpr20;	/* 0x50480 - Internal Interrupt Vector/Priority Register 20 */
+	char	res119[12];
+	uint	iidr20;		/* 0x50490 - Internal Interrupt Destination Register 20 */
+	char	res120[12];
+	uint	iivpr21;	/* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */
+	char	res121[12];
+	uint	iidr21;		/* 0x504b0 - Internal Interrupt Destination Register 21 */
+	char	res122[12];
+	uint	iivpr22;	/* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */
+	char	res123[12];
+	uint	iidr22;		/* 0x504d0 - Internal Interrupt Destination Register 22 */
+	char	res124[12];
+	uint	iivpr23;	/* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */
+	char	res125[12];
+	uint	iidr23;		/* 0x504f0 - Internal Interrupt Destination Register 23 */
+	char	res126[12];
+	uint	iivpr24;	/* 0x50500 - Internal Interrupt Vector/Priority Register 24 */
+	char	res127[12];
+	uint	iidr24;		/* 0x50510 - Internal Interrupt Destination Register 24 */
+	char	res128[12];
+	uint	iivpr25;	/* 0x50520 - Internal Interrupt Vector/Priority Register 25 */
+	char	res129[12];
+	uint	iidr25;		/* 0x50530 - Internal Interrupt Destination Register 25 */
+	char	res130[12];
+	uint	iivpr26;	/* 0x50540 - Internal Interrupt Vector/Priority Register 26 */
+	char	res131[12];
+	uint	iidr26;		/* 0x50550 - Internal Interrupt Destination Register 26 */
+	char	res132[12];
+	uint	iivpr27;	/* 0x50560 - Internal Interrupt Vector/Priority Register 27 */
+	char	res133[12];
+	uint	iidr27;		/* 0x50570 - Internal Interrupt Destination Register 27 */
+	char	res134[12];
+	uint	iivpr28;	/* 0x50580 - Internal Interrupt Vector/Priority Register 28 */
+	char	res135[12];
+	uint	iidr28;		/* 0x50590 - Internal Interrupt Destination Register 28 */
+	char	res136[12];
+	uint	iivpr29;	/* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */
+	char	res137[12];
+	uint	iidr29;		/* 0x505b0 - Internal Interrupt Destination Register 29 */
+	char	res138[12];
+	uint	iivpr30;	/* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */
+	char	res139[12];
+	uint	iidr30;		/* 0x505d0 - Internal Interrupt Destination Register 30 */
+	char	res140[12];
+	uint	iivpr31;	/* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */
+	char	res141[12];
+	uint	iidr31;		/* 0x505f0 - Internal Interrupt Destination Register 31 */
+	char	res142[4108];
+	uint	mivpr0;		/* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */
+	char	res143[12];
+	uint	midr0;		/* 0x51610 - Messaging Interrupt Destination Register 0 */
+	char	res144[12];
+	uint	mivpr1;		/* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */
+	char	res145[12];
+	uint	midr1;		/* 0x51630 - Messaging Interrupt Destination Register 1 */
+	char	res146[12];
+	uint	mivpr2;		/* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */
+	char	res147[12];
+	uint	midr2;		/* 0x51650 - Messaging Interrupt Destination Register 2 */
+	char	res148[12];
+	uint	mivpr3;		/* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */
+	char	res149[12];
+	uint	midr3;		/* 0x51670 - Messaging Interrupt Destination Register 3 */
+	char	res150[59852];
+	uint	ipi0dr0;	/* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */
+	char	res151[12];
+	uint	ipi0dr1;	/* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */
+	char	res152[12];
+	uint	ipi0dr2;	/* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */
+	char	res153[12];
+	uint	ipi0dr3;	/* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */
+	char	res154[12];
+	uint	ctpr0;		/* 0x60080 - Current Task Priority Register for Processor 0 */
+	char	res155[12];
+	uint	whoami0;	/* 0x60090 - Who Am I Register for Processor 0 */
+	char	res156[12];
+	uint	iack0;		/* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */
+	char	res157[12];
+	uint	eoi0;		/* 0x600b0 - End Of Interrupt Register for Processor 0 */
+	char	res158[3916];
+} ccsr_pic_t;
+
+/* RapidIO Registers(0xc_0000-0xe_0000) */
+
+typedef struct ccsr_rio {
+	uint	didcar;		/* 0xc0000 - Device Identity Capability Register */
+	uint	dicar;		/* 0xc0004 - Device Information Capability Register */
+	uint	aidcar;		/* 0xc0008 - Assembly Identity Capability Register */
+	uint	aicar;		/* 0xc000c - Assembly Information Capability Register */
+	uint	pefcar;		/* 0xc0010 - Processing Element Features Capability Register */
+	uint	spicar;		/* 0xc0014 - Switch Port Information Capability Register */
+	uint	socar;		/* 0xc0018 - Source Operations Capability Register */
+	uint	docar;		/* 0xc001c - Destination Operations Capability Register */
+	char	res1[32];
+	uint	msr;		/* 0xc0040 - Mailbox Command And Status Register */
+	uint	pwdcsr;		/* 0xc0044 - Port-Write and Doorbell Command And Status Register */
+	char	res2[4];
+	uint	pellccsr;	/* 0xc004c - Processing Element Logic Layer Control Command and Status Register */
+	char	res3[12];
+	uint	lcsbacsr;	/* 0xc005c - Local Configuration Space Base Address Command and Status Register */
+	uint	bdidcsr;	/* 0xc0060 - Base Device ID Command and Status Register */
+	char	res4[4];
+	uint	hbdidlcsr;	/* 0xc0068 - Host Base Device ID Lock Command and Status Register */
+	uint	ctcsr;		/* 0xc006c - Component Tag Command and Status Register */
+	char	res5[144];
+	uint	pmbh0csr;	/* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */
+	char	res6[28];
+	uint	pltoccsr;	/* 0xc0120 - Port Link Time-out Control Command and Status Register */
+	uint	prtoccsr;	/* 0xc0124 - Port Response Time-out Control Command and Status Register */
+	char	res7[20];
+	uint	pgccsr;		/* 0xc013c - Port General Command and Status Register */
+	uint	plmreqcsr;	/* 0xc0140 - Port Link Maintenance Request Command and Status Register */
+	uint	plmrespcsr;	/* 0xc0144 - Port Link Maintenance Response Command and Status Register */
+	uint	plascsr;	/* 0xc0148 - Port Local Ackid Status Command and Status Register */
+	char	res8[12];
+	uint	pescsr;		/* 0xc0158 - Port Error and Status Command and Status Register */
+	uint	pccsr;		/* 0xc015c - Port Control Command and Status Register */
+	char	res9[1184];
+	uint	erbh;		/* 0xc0600 - Error Reporting Block Header Register */
+	char	res10[4];
+	uint	ltledcsr;	/* 0xc0608 - Logical/Transport layer error detect status register */
+	uint	ltleecsr;	/* 0xc060c - Logical/Transport layer error enable register */
+	char	res11[4];
+	uint	ltlaccsr;	/* 0xc0614 - Logical/Transport layer addresss capture register */
+	uint	ltldidccsr;	/* 0xc0618 - Logical/Transport layer device ID capture register */
+	uint	ltlcccsr;	/* 0xc061c - Logical/Transport layer control capture register */
+	char	res12[32];
+	uint	edcsr;	        /* 0xc0640 - Port 0 error detect status register */
+	uint	erecsr;	        /* 0xc0644 - Port 0 error rate enable status register */
+	uint	ecacsr;	        /* 0xc0648 - Port 0 error capture attributes register */
+	uint	pcseccsr0;	/* 0xc064c - Port 0 packet/control symbol error capture register 0 */
+	uint	peccsr1;	/* 0xc0650 - Port 0 error capture command and status register 1 */
+	uint	peccsr2;	/* 0xc0654 - Port 0 error capture command and status register 2 */
+	uint	peccsr3;	/* 0xc0658 - Port 0 error capture command and status register 3 */
+	char	res13[12];
+	uint	ercsr;	        /* 0xc0668 - Port 0 error rate command and status register */
+	uint	ertcsr;	        /* 0xc066C - Port 0 error rate threshold status register*/
+	char	res14[63892];
+	uint	llcr;		/* 0xd0004 - Logical Layer Configuration Register */
+	char	res15[12];
+	uint	epwisr;		/* 0xd0010 - Error / Port-Write Interrupt Status Register */
+	char	res16[12];
+	uint	lretcr;		/* 0xd0020 - Logical Retry Error Threshold Configuration Register */
+	char	res17[92];
+	uint	pretcr;		/* 0xd0080 - Physical Retry Erorr Threshold Configuration Register */
+	char	res18[124];
+	uint	adidcsr;	/* 0xd0100 - Port 0 Alt. Device ID Command and Status Register */
+	char	res19[28];
+	uint	ptaacr;	        /* 0xd0120 - Port 0 Pass-Through/Accept-All Configuration Register */
+	char	res20[12];
+	uint	iecsr;	        /* 0xd0130 - Port 0 Implementation Error Status Register */
+	char	res21[12];
+	uint	pcr;		/* 0xd0140 - Port 0 Phsyical Configuration RegisterRegister */
+	char	res22[20];
+	uint	slcsr;	        /* 0xd0158 - Port 0 Serial Link Command and Status Register */
+	char	res23[4];
+	uint	sleir;	        /* 0xd0160 - Port 0 Serial Link Error Injection Register */
+	char	res24[2716];
+	uint	rowtar0;	/* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */
+	uint	rowtear0;	/* 0xd0c04 - RapidIO Outbound Window Translation Ext. Address Register 0 */
+	char	res25[8];
+	uint	rowar0;		/* 0xd0c10 - RapidIO Outbound Attributes Register 0 */
+	char	res26[12];
+	uint	rowtar1;	/* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */
+	uint	rowtear1;	/* 0xd0c24 - RapidIO Outbound Window Translation Ext. Address Register 1 */
+	uint	rowbar1;	/* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */
+	char	res27[4];
+	uint	rowar1;		/* 0xd0c30 - RapidIO Outbound Attributes Register 1 */
+	uint	rows1r1;	/* 0xd0c34 - RapidIO Outbound Window Segment 1 Register 1 */
+	uint	rows2r1;	/* 0xd0c38 - RapidIO Outbound Window Segment 2 Register 1 */
+	uint	rows3r1;	/* 0xd0c3c - RapidIO Outbound Window Segment 3 Register 1 */
+	uint	rowtar2;	/* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */
+	uint	rowtear2;	/* 0xd0c44 - RapidIO Outbound Window Translation Ext. Address Register 2 */
+	uint	rowbar2;	/* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */
+	char	res28[4];
+	uint	rowar2;		/* 0xd0c50 - RapidIO Outbound Attributes Register 2 */
+	uint	rows1r2;	/* 0xd0c54 - RapidIO Outbound Window Segment 1 Register 2 */
+	uint	rows2r2;	/* 0xd0c58 - RapidIO Outbound Window Segment 2 Register 2 */
+	uint	rows3r2;	/* 0xd0c5c - RapidIO Outbound Window Segment 3 Register 2 */
+	uint	rowtar3;	/* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */
+	uint	rowtear3;	/* 0xd0c64 - RapidIO Outbound Window Translation Ext. Address Register 3 */
+	uint	rowbar3;	/* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */
+	char	res29[4];
+	uint	rowar3;		/* 0xd0c70 - RapidIO Outbound Attributes Register 3 */
+	uint	rows1r3;	/* 0xd0c74 - RapidIO Outbound Window Segment 1 Register 3 */
+	uint	rows2r3;	/* 0xd0c78 - RapidIO Outbound Window Segment 2 Register 3 */
+	uint	rows3r3;	/* 0xd0c7c - RapidIO Outbound Window Segment 3 Register 3 */
+	uint	rowtar4;	/* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */
+	uint	rowtear4;	/* 0xd0c84 - RapidIO Outbound Window Translation Ext. Address Register 4 */
+	uint	rowbar4;	/* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */
+	char	res30[4];
+	uint	rowar4;		/* 0xd0c90 - RapidIO Outbound Attributes Register 4 */
+	uint	rows1r4;	/* 0xd0c94 - RapidIO Outbound Window Segment 1 Register 4 */
+	uint	rows2r4;	/* 0xd0c98 - RapidIO Outbound Window Segment 2 Register 4 */
+	uint	rows3r4;	/* 0xd0c9c - RapidIO Outbound Window Segment 3 Register 4 */
+	uint	rowtar5;	/* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */
+	uint	rowtear5;	/* 0xd0ca4 - RapidIO Outbound Window Translation Ext. Address Register 5 */
+	uint	rowbar5;	/* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */
+	char	res31[4];
+	uint	rowar5;		/* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */
+	uint	rows1r5;	/* 0xd0cb4 - RapidIO Outbound Window Segment 1 Register 5 */
+	uint	rows2r5;	/* 0xd0cb8 - RapidIO Outbound Window Segment 2 Register 5 */
+	uint	rows3r5;	/* 0xd0cbc - RapidIO Outbound Window Segment 3 Register 5 */
+	uint	rowtar6;	/* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */
+	uint	rowtear6;	/* 0xd0cc4 - RapidIO Outbound Window Translation Ext. Address Register 6 */
+	uint	rowbar6;	/* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */
+	char	res32[4];
+	uint	rowar6;		/* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */
+	uint	rows1r6;	/* 0xd0cd4 - RapidIO Outbound Window Segment 1 Register 6 */
+	uint	rows2r6;	/* 0xd0cd8 - RapidIO Outbound Window Segment 2 Register 6 */
+	uint	rows3r6;	/* 0xd0cdc - RapidIO Outbound Window Segment 3 Register 6 */
+	uint	rowtar7;	/* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */
+	uint	rowtear7;	/* 0xd0ce4 - RapidIO Outbound Window Translation Ext. Address Register 7 */
+	uint	rowbar7;	/* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */
+	char	res33[4];
+	uint	rowar7;		/* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */
+	uint	rows1r7;	/* 0xd0cf4 - RapidIO Outbound Window Segment 1 Register 7 */
+	uint	rows2r7;	/* 0xd0cf8 - RapidIO Outbound Window Segment 2 Register 7 */
+	uint	rows3r7;	/* 0xd0cfc - RapidIO Outbound Window Segment 3 Register 7 */
+	uint	rowtar8;	/* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */
+	uint	rowtear8;	/* 0xd0d04 - RapidIO Outbound Window Translation Ext. Address Register 8 */
+	uint	rowbar8;	/* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */
+	char	res34[4];
+	uint	rowar8;		/* 0xd0d10 - RapidIO Outbound Attributes Register 8 */
+	uint	rows1r8;	/* 0xd0d14 - RapidIO Outbound Window Segment 1 Register 8 */
+	uint	rows2r8;	/* 0xd0d18 - RapidIO Outbound Window Segment 2 Register 8 */
+	uint	rows3r8;	/* 0xd0d1c - RapidIO Outbound Window Segment 3 Register 8 */
+	char	res35[64];
+	uint	riwtar4;	/* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */
+	uint	riwbar4;	/* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */
+	char	res36[4];
+	uint	riwar4;		/* 0xd0d70 - RapidIO Inbound Attributes Register 4 */
+	char	res37[12];
+	uint	riwtar3;	/* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */
+	char	res38[4];
+	uint	riwbar3;	/* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */
+	char	res39[4];
+	uint	riwar3;		/* 0xd0d90 - RapidIO Inbound Attributes Register 3 */
+	char	res40[12];
+	uint	riwtar2;	/* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */
+	char	res41[4];
+	uint	riwbar2;	/* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */
+	char	res42[4];
+	uint	riwar2;		/* 0xd0db0 - RapidIO Inbound Attributes Register 2 */
+	char	res43[12];
+	uint	riwtar1;	/* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */
+	char	res44[4];
+	uint	riwbar1;	/* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */
+	char	res45[4];
+	uint	riwar1;		/* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */
+	char	res46[12];
+	uint	riwtar0;	/* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */
+	char	res47[12];
+	uint	riwar0;		/* 0xd0df0 - RapidIO Inbound Attributes Register 0 */
+	char	res48[12];
+	uint	pnfedr;		/* 0xd0e00 - Port Notification/Fatal Error Detect Register */
+	uint	pnfedir;	/* 0xd0e04 - Port Notification/Fatal Error Detect Register */
+	uint	pnfeier;	/* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */
+	uint	pecr;		/* 0xd0e0c - Port Error Control Register */
+	uint	pepcsr0;	/* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */
+	uint	pepr1;		/* 0xd0e14 - Port Error Packet Register 1 */
+	uint	pepr2;		/* 0xd0e18 - Port Error Packet Register 2 */
+	char	res49[4];
+	uint	predr;		/* 0xd0e20 - Port Recoverable Error Detect Register */
+	char	res50[4];
+	uint	pertr;		/* 0xd0e28 - Port Error Recovery Threshold Register */
+	uint	prtr;		/* 0xd0e2c - Port Retry Threshold Register */
+	char	res51[8656];
+	uint	omr;		/* 0xd3000 - Outbound Mode Register */
+	uint	osr;		/* 0xd3004 - Outbound Status Register */
+	uint	eodqtpar;	/* 0xd3008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */
+	uint	odqtpar;	/* 0xd300c - Outbound Descriptor Queue Tail Pointer Address Register */
+	uint	eosar;		/* 0xd3010 - Extended Outbound Unit Source Address Register */
+	uint	osar;		/* 0xd3014 - Outbound Unit Source Address Register */
+	uint	odpr;		/* 0xd3018 - Outbound Destination Port Register */
+	uint	odatr;		/* 0xd301c - Outbound Destination Attributes Register */
+	uint	odcr;		/* 0xd3020 - Outbound Doubleword Count Register */
+	uint	eodqhpar;	/* 0xd3024 - Extended Outbound Descriptor Queue Head Pointer Address Register */
+	uint	odqhpar;	/* 0xd3028 - Outbound Descriptor Queue Head Pointer Address Register */
+	uint	oretr;	        /* 0xd302C - Outbound Retry Error Threshold Register */
+	uint	omgr;	        /* 0xd3030 - Outbound Multicast Group Register */
+	uint	omlr;	        /* 0xd3034 - Outbound Multicast List Register */
+	char	res52[40];
+	uint	imr;		/* 0xd3060 - Outbound Mode Register */
+	uint	isr;		/* 0xd3064 - Inbound Status Register */
+	uint	eidqtpar;	/* 0xd3068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */
+	uint	idqtpar;	/* 0xd306c - Inbound Descriptor Queue Tail Pointer Address Register */
+	uint	eifqhpar;	/* 0xd3070 - Extended Inbound Frame Queue Head Pointer Address Register */
+	uint	ifqhpar;	/* 0xd3074 - Inbound Frame Queue Head Pointer Address Register */
+	uint	imirir;	        /* 0xd3078 - Inbound Maximum Interrutp Report Interval Register */
+	char	res53[900];
+	uint	oddmr;		/* 0xd3400 - Outbound Doorbell Mode Register */
+	uint	oddsr;		/* 0xd3404 - Outbound Doorbell Status Register */
+	char	res54[16];
+	uint	oddpr;		/* 0xd3418 - Outbound Doorbell Destination Port Register */
+	uint	oddatr;		/* 0xd341C - Outbound Doorbell Destination Attributes Register */
+	char	res55[12];
+	uint	oddretr;	/* 0xd342C - Outbound Doorbell Retry Threshold Configuration Register */
+	char	res56[48];
+	uint	idmr;		/* 0xd3460 - Inbound Doorbell Mode Register */
+	uint	idsr;		/* 0xd3464 - Inbound Doorbell Status Register */
+	uint	iedqtpar;	/* 0xd3468 - Extended Inbound Doorbell Queue Tail Pointer Address Register */
+	uint	iqtpar;	        /* 0xd346c - Inbound Doorbell Queue Tail Pointer Address Register */
+	uint	iedqhpar;	/* 0xd3470 - Extended Inbound Doorbell Queue Head Pointer Address Register */
+	uint	idqhpar;	/* 0xd3474 - Inbound Doorbell Queue Head Pointer Address Register */
+	uint	idmirir;	/* 0xd3478 - Inbound Doorbell Max Interrupt Report Interval Register */
+	char	res57[100];
+	uint	pwmr;		/* 0xd34e0 - Port-Write Mode Register */
+	uint	pwsr;		/* 0xd34e4 - Port-Write Status Register */
+	uint	epwqbar;	/* 0xd34e8 - Extended Port-Write Queue Base Address Register */
+	uint	pwqbar;		/* 0xd34ec - Port-Write Queue Base Address Register */
+	char	res58[51984];
+} ccsr_rio_t;
+
+/* Global Utilities Register Block(0xe_0000-0xf_ffff) */
+typedef struct ccsr_gur {
+	uint	porpllsr;	/* 0xe0000 - POR PLL ratio status register */
+	uint	porbmsr;	/* 0xe0004 - POR boot mode status register */
+#define MPC86xx_PORBMSR_HA      0x00060000
+	uint	porimpscr;	/* 0xe0008 - POR I/O impedance status and control register */
+	uint	pordevsr;	/* 0xe000c - POR I/O device status regsiter */
+#define MPC86xx_PORDEVSR_IO_SEL 0x000F0000
+	uint	pordbgmsr;	/* 0xe0010 - POR debug mode status register */
+	char	res1[12];
+	uint	gpporcr;	/* 0xe0020 - General-purpose POR configuration register */
+	char	res2[12];
+	uint	gpiocr;		/* 0xe0030 - GPIO control register */
+	char	res3[12];
+	uint	gpoutdr;	/* 0xe0040 - General-purpose output data register */
+	char	res4[12];
+	uint	gpindr;		/* 0xe0050 - General-purpose input data register */
+	char	res5[12];
+	uint	pmuxcr;		/* 0xe0060 - Alternate function signal multiplex control */
+	char	res6[12];
+	uint	devdisr;	/* 0xe0070 - Device disable control */
+#define MPC86xx_DEVDISR_PCIEX1  0x80000000
+#define MPC86xx_DEVDISR_PCIEX2  0x40000000
+	char	res7[12];
+	uint	powmgtcsr;	/* 0xe0080 - Power management status and control register */
+	char	res8[12];
+	uint	mcpsumr;	/* 0xe0090 - Machine check summary register */
+	char	res9[12];
+	uint	pvr;		/* 0xe00a0 - Processor version register */
+	uint	svr;		/* 0xe00a4 - System version register */
+	char	res10[3416];
+	uint	clkocr;		/* 0xe0e00 - Clock out select register */
+	char	res11[12];
+	uint	ddrdllcr;	/* 0xe0e10 - DDR DLL control register */
+	char	res12[12];
+	uint	lbcdllcr;	/* 0xe0e20 - LBC DLL control register */
+	int	res13[57];
+	uint    lynxdcr1;        /* 0xe0f08 - Lynx debug control register 1*/
+	int     res14[6];
+	uint    ddrioovcr;      /* 0xe0f24 - DDR IO Overdrive Control register */
+	char	res15[61656];
+} ccsr_gur_t;
+
+typedef struct immap {
+	ccsr_local_mcm_t	im_local_mcm;
+	ccsr_ddr_t		im_ddr1;
+	ccsr_i2c_t		im_i2c;
+	ccsr_duart_t		im_duart;
+	ccsr_lbc_t		im_lbc;
+	ccsr_ddr_t		im_ddr2;
+	char                    res1[4096];
+	ccsr_pex_t		im_pex1;
+	ccsr_pex_t		im_pex2;
+	ccsr_ht_t               im_ht;
+	char                    res2[90112];
+	ccsr_dma_t		im_dma;
+	char                    res3[8192];
+	ccsr_tsec_t		im_tsec1;
+	ccsr_tsec_t		im_tsec2;
+	ccsr_tsec_t             im_tsec3;
+	ccsr_tsec_t             im_tsec4;
+	char                    res4[98304];
+	ccsr_pic_t		im_pic;
+	char                    res5[389120];
+	ccsr_rio_t		im_rio;
+	ccsr_gur_t		im_gur;
+} immap_t;
+
+extern immap_t  *immr;
+
+#endif /*__IMMAP_86xx__*/
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index baaf6f7976..914f28b461 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -117,8 +117,8 @@ typedef struct _P601_BAT {
  */
 
 typedef struct _pte {
-   	unsigned long page_num:20;
-   	unsigned long flags:12;		/* Page flags (some unused bits) */
+	unsigned long page_num:20;
+	unsigned long flags:12;		/* Page flags (some unused bits) */
 } pte;
 
 #define PD_SHIFT (10+12)		/* Page directory */
@@ -434,9 +434,14 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
 #define BOOKE_PAGESZ_1GB        10
 #define BOOKE_PAGESZ_4GB        11
 
+#if defined(CONFIG_MPC86xx)
+#define LAWBAR_BASE_ADDR	0x00FFFFFF
+#define LAWAR_TRGT_IF		0x01F00000
+#else
 #define LAWBAR_BASE_ADDR	0x000FFFFF
-#define LAWAR_EN		0x80000000
 #define LAWAR_TRGT_IF		0x00F00000
+#endif
+#define LAWAR_EN		0x80000000
 #define LAWAR_SIZE		0x0000003F
 
 #define LAWAR_TRGT_IF_PCI	0x00000000
@@ -445,8 +450,11 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
 #define LAWAR_TRGT_IF_PCI2	0x00100000
 #define LAWAR_TRGT_IF_LBC	0x00400000
 #define LAWAR_TRGT_IF_CCSR	0x00800000
+#define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000
 #define LAWAR_TRGT_IF_RIO	0x00c00000
 #define LAWAR_TRGT_IF_DDR	0x00f00000
+#define LAWAR_TRGT_IF_DDR1	0x00f00000
+#define LAWAR_TRGT_IF_DDR2	0x01600000
 
 #define LAWAR_SIZE_BASE		0xa
 #define LAWAR_SIZE_4K		(LAWAR_SIZE_BASE+1)
@@ -469,6 +477,10 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
 #define LAWAR_SIZE_512M		(LAWAR_SIZE_BASE+18)
 #define LAWAR_SIZE_1G		(LAWAR_SIZE_BASE+19)
 #define LAWAR_SIZE_2G		(LAWAR_SIZE_BASE+20)
+#define LAWAR_SIZE_4G		(LAWAR_SIZE_BASE+21)
+#define LAWAR_SIZE_8G		(LAWAR_SIZE_BASE+22)
+#define LAWAR_SIZE_16G		(LAWAR_SIZE_BASE+23)
+#define LAWAR_SIZE_32G		(LAWAR_SIZE_BASE+24)
 
 #ifdef CONFIG_440SPE
 /*----------------------------------------------------------------------------+
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 44b23f1eb4..388dea430c 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -264,6 +264,7 @@
 #define SPRN_ICTC	0x3FB	/* Instruction Cache Throttling Control Reg */
 #define SPRN_IMISS	0x3D4	/* Instruction TLB Miss Register */
 #define SPRN_IMMR	0x27E  	/* Internal Memory Map Register */
+#define SPRN_LDSTCR	0x3F8   /* Load/Store Control Register */
 #define SPRN_L2CR	0x3F9	/* Level 2 Cache Control Regsiter */
 #define SPRN_LR		0x008	/* Link Register */
 #define SPRN_MBAR       0x137   /* System memory base address */
@@ -443,6 +444,11 @@
 #define SPRN_MCSR	0x23c	/* Machine Check Syndrome register */
 #define ESR_ST          0x00800000      /* Store Operation */
 
+#if defined(CONFIG_MPC86xx)
+#define SPRN_MSSCRO	0x3f6
+#endif
+
+
 /* Short-hand versions for a number of the above SPRNs */
 
 #define CTR	SPRN_CTR	/* Counter Register */
@@ -501,10 +507,14 @@
 #define ICMP	SPRN_ICMP	/* Instruction TLB Compare Register */
 #define IMISS	SPRN_IMISS	/* Instruction TLB Miss Register */
 #define IMMR	SPRN_IMMR      	/* PPC 860/821 Internal Memory Map Register */
+#define LDSTCR	SPRN_LDSTCR     /* Load/Store Control Register */
 #define L2CR	SPRN_L2CR    	/* PPC 750 L2 control register */
 #define LR	SPRN_LR
 #define MBAR    SPRN_MBAR       /* System memory base address */
-#if defined(CONFIG_E500)
+#if defined(CONFIG_MPC86xx)
+#define MSSCR0	SPRN_MSSCRO
+#endif
+#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
 #define PIR	SPRN_PIR
 #endif
 #define SVR	SPRN_SVR	/* System-On-Chip Version Register */
@@ -538,7 +548,7 @@
 #define CSRR0	SPRN_CSRR0
 #define CSRR1	SPRN_CSRR1
 #define IVPR	SPRN_IVPR
-#define USPRG0	SPRN_USPRG0
+#define USPRG0	SPRN_USPRG
 #define SPRG4R	SPRN_SPRG4R
 #define SPRG5R	SPRN_SPRG5R
 #define SPRG6R	SPRN_SPRG6R
@@ -728,6 +738,10 @@
 #define PVR_440EP_RC	0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
 #define PVR_440GR_RA	0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
 #define PVR_440GR_RB	0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
+#define PVR_440EPX1_RA  0x216218D0 /* 440EPX rev A with Security / Kasumi */
+#define PVR_440EPX2_RA  0x216218D4 /* 440EPX rev A without Security / Kasumi */
+#define PVR_440GRX1_RA  0x216218D8 /* 440GRX rev A with Security / Kasumi */
+#define PVR_440GRX2_RA  0x216218DC /* 440GRX rev A without Security / Kasumi */
 #define PVR_440GX_RA	0x51B21850
 #define PVR_440GX_RB	0x51B21851
 #define PVR_440GX_RC	0x51B21892
@@ -759,6 +773,8 @@
 #define PVR_85xx_REV1	(PVR_85xx | 0x0010)
 #define PVR_85xx_REV2	(PVR_85xx | 0x0020)
 
+#define PVR_86xx	0x80040000
+#define PVR_86xx_REV1	(PVR_86xx | 0x0010)
 
 /*
  * For the 8xx processors, all of them report the same PVR family for
@@ -794,6 +810,8 @@
 #define SVR_VER(svr)	(((svr) >>  16) & 0xFFFF)	/* Version field */
 #define SVR_REV(svr)	(((svr) >>   0) & 0xFFFF)	/* Revison field */
 
+#define SVR_SUBVER(svr)	(((svr) >>  8) & 0xFF)	/* Process/MFG sub-version */
+
 #define SVR_FAM(svr)	(((svr) >> 20) & 0xFFF)	/* Family field */
 #define SVR_MEM(svr)	(((svr) >> 16) & 0xF)	/* Member field */
 
@@ -811,6 +829,7 @@
 #define SVR_8541	0x807A
 #define SVR_8548	0x8031
 #define SVR_8548_E	0x8039
+#define SVR_8641	0x8090
 
 
 /* I am just adding a single entry for 8260 boards.  I think we may be
diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h
index f7aa55f334..30b44e3d22 100644
--- a/include/asm-ppc/u-boot.h
+++ b/include/asm-ppc/u-boot.h
@@ -45,7 +45,7 @@ typedef struct bd_info {
 	unsigned long	bi_sramstart;	/* start of SRAM memory */
 	unsigned long	bi_sramsize;	/* size	 of SRAM memory */
 #if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \
-	|| defined(CONFIG_E500)
+	|| defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
 	unsigned long	bi_immr_base;	/* base of IMMR register */
 #endif
 #if defined(CONFIG_MPC5xxx)
@@ -108,7 +108,8 @@ typedef struct bd_info {
 #endif
 
 #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined (CONFIG_440GX) || \
-    defined(CONFIG_440EP) || defined(CONFIG_440GR)
+    defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	unsigned int	bi_opbfreq;		/* OPB clock in Hz */
 	int		bi_iic_fast[2];		/* Use fast i2c mode */
 #endif
diff --git a/include/common.h b/include/common.h
index e4637ad356..ac78d1c001 100644
--- a/include/common.h
+++ b/include/common.h
@@ -79,6 +79,10 @@ typedef volatile unsigned char	vu_char;
 #endif
 #include <asm/immap_8260.h>
 #endif
+#ifdef CONFIG_MPC86xx
+#include <mpc86xx.h>
+#include <asm/immap_86xx.h>
+#endif
 #ifdef CONFIG_MPC85xx
 #include <mpc85xx.h>
 #include <asm/immap_85xx.h>
@@ -109,6 +113,12 @@ typedef volatile unsigned char	vu_char;
 #define debugX(level,fmt,args...)
 #endif	/* DEBUG */
 
+#define BUG() do { \
+	printf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \
+	panic("BUG!"); \
+} while (0)
+#define BUG_ON(condition) do { if (unlikely((condition)!=0)) BUG(); } while(0)
+
 typedef void (interrupt_handler_t)(void *);
 
 #include <asm/u-boot.h> /* boot information for Linux kernel */
@@ -194,6 +204,9 @@ int	checkdram     (void);
 char *	strmhz(char *buf, long hz);
 int	last_stage_init(void);
 extern ulong monitor_flash_len;
+#ifdef CFG_ID_EEPROM
+int mac_read_from_eeprom(void);
+#endif
 
 /* common/flash.c */
 void flash_perror (int);
@@ -245,6 +258,9 @@ void	pciinfo	      (int, int);
 	void	pci_master_init	     (struct pci_controller *);
 #   endif
     int	    is_pci_host		(struct pci_controller *);
+#if defined(CONFIG_440SPE)
+   void pcie_setup_hoses(void);
+#endif
 #endif
 
 int	misc_init_f   (void);
@@ -254,7 +270,7 @@ int	misc_init_r   (void);
 void	jumptable_init(void);
 
 /* common/memsize.c */
-int	get_ram_size  (volatile long *, long);
+long	get_ram_size  (volatile long *, long);
 
 /* $(BOARD)/$(BOARD).c */
 void	reset_phy     (void);
@@ -304,7 +320,8 @@ void	board_ether_init (void);
 
 #if defined(CONFIG_RPXCLASSIC)	|| defined(CONFIG_MBX) || \
     defined(CONFIG_IAD210)	|| defined(CONFIG_XPEDITE1K) || \
-    defined(CONFIG_METROBOX)    || defined(CONFIG_KAREF)
+    defined(CONFIG_METROBOX)    || defined(CONFIG_KAREF) || \
+    defined(CONFIG_V38B)
 void	board_get_enetaddr (uchar *addr);
 #endif
 
@@ -367,6 +384,7 @@ void	trap_init     (ulong);
     defined (CONFIG_74xx)	|| \
     defined (CONFIG_MPC8220)	|| \
     defined (CONFIG_MPC85xx)	|| \
+    defined (CONFIG_MPC86xx)	|| \
     defined (CONFIG_MPC83XX)
 unsigned char	in8(unsigned int);
 void		out8(unsigned int, unsigned char);
@@ -455,6 +473,10 @@ ulong	get_bus_freq  (ulong);
 typedef MPC85xx_SYS_INFO sys_info_t;
 void	get_sys_info  ( sys_info_t * );
 #endif
+#if defined(CONFIG_MPC86xx)
+typedef MPC86xx_SYS_INFO sys_info_t;
+void   get_sys_info  ( sys_info_t * );
+#endif
 
 #if defined(CONFIG_4xx) || defined(CONFIG_IOP480)
 #  if defined(CONFIG_440)
@@ -462,6 +484,7 @@ void	get_sys_info  ( sys_info_t * );
 #	if defined(CONFIG_440SPE)
 	 unsigned long determine_sysper(void);
 	 unsigned long determine_pci_clock_per(void);
+	 int ppc440spe_revB(void);
 #	endif
 #  else
     typedef PPC405_SYS_INFO sys_info_t;
@@ -473,7 +496,7 @@ void	get_sys_info  ( sys_info_t * );
 #if defined(CONFIG_8xx) || defined(CONFIG_8260)
 void	cpu_init_f    (volatile immap_t *immr);
 #endif
-#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2)
+#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2) ||defined(CONFIG_MPC86xx)
 void	cpu_init_f    (void);
 #endif
 
@@ -599,7 +622,7 @@ void	show_boot_progress (int status);
 #endif
 
 #ifdef CONFIG_INIT_CRITICAL
-#error CONFIG_INIT_CRITICAL is depracted!
+#error CONFIG_INIT_CRITICAL is deprecated!
 #error Read section CONFIG_SKIP_LOWLEVEL_INIT in README.
 #endif
 
diff --git a/include/configs/CPCI440.h b/include/configs/CPCI440.h
index a5bc773e17..90d3a8d8fa 100644
--- a/include/configs/CPCI440.h
+++ b/include/configs/CPCI440.h
@@ -31,7 +31,8 @@
 /*-----------------------------------------------------------------------
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
-#define CONFIG_EBONY		1	    /* Board is ebony		*/
+#define CONFIG_CPCI440		1	    /* Board is ebony		*/
+#define CONFIG_440GP		1	    /* Specifc GP support	*/
 #define CONFIG_4xx		1	    /* ... PPC4xx family	*/
 #define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
 #undef	CFG_DRAM_TEST			    /* Disable-takes long time! */
diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h
index 244e45a750..bc23fc0278 100644
--- a/include/configs/CPCI750.h
+++ b/include/configs/CPCI750.h
@@ -74,7 +74,7 @@
 
 #define CFG_PROMPT_HUSH_PS2	"> "
 
-#define CFG_AUTO_COMPLETE 1
+#define CONFIG_AUTO_COMPLETE 1
 
 /* Define which ETH port will be used for connecting the network */
 #define CFG_ETH_PORT		ETH_0
diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h
index 7a1dada2db..ce969ecdd1 100644
--- a/include/configs/CPU87.h
+++ b/include/configs/CPU87.h
@@ -527,7 +527,7 @@
 			 PSDMR_LDOTOPRE_1C		|\
 			 PSDMR_WRC_1C			|\
 			 PSDMR_CL_2)
-			 
+
 /*
  * Init Memory Controller:
  *
diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h
index 7bbceb01bd..2ad6f06985 100644
--- a/include/configs/KAREF.h
+++ b/include/configs/KAREF.h
@@ -200,7 +200,6 @@
 
 /* Include auto complete with tabs */
 #define CONFIG_AUTO_COMPLETE 1
-#define CFG_AUTO_COMPLETE    1
 #define CFG_ALT_MEMTEST	     1	     /* use real memory test	 */
 
 
diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h
index b96557148a..465a4ecb8b 100644
--- a/include/configs/METROBOX.h
+++ b/include/configs/METROBOX.h
@@ -268,7 +268,7 @@
 
 /* Include auto complete with tabs */
 #define CONFIG_AUTO_COMPLETE 1
-#define CFG_AUTO_COMPLETE    1
+#define CONFIG_AUTO_COMPLETE 1
 #define CFG_ALT_MEMTEST	     1	     /* use real memory test	 */
 
 
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 131c832242..74a84f4e86 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -68,6 +68,10 @@
  * The board, however, can run at 66MHz.  In any event, this value
  * must match the settings of some switches.  Details can be found
  * in the README.mpc85xxads.
+ *
+ * XXX -- Can't we run at 66 MHz, anyway?  PCI should drop to
+ * 33MHz to accommodate, based on a PCI pin.
+ * Note that PCI-X won't work at 33MHz.
  */
 
 #ifndef CONFIG_SYS_CLK_FREQ
@@ -293,12 +297,31 @@
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
-/* I2C */
-#define  CONFIG_HARD_I2C		/* I2C with hardware support*/
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE	8192
+
+#define OF_CPU			"PowerPC,8540@0"
+#define OF_SOC			"soc8540@e0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 8)
+#define OF_STDOUT_PATH		"/soc8540@e0000000/serial@4500"
+
+#define CFG_64BIT_VSPRINTF	1
+#define CFG_64BIT_STRTOUL	1
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CFG_I2C_SLAVE		0x7F
 #define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+#define CFG_I2C_OFFSET		0x3000
 
 /* RapidIO MMU */
 #define CFG_RIO_MEM_BASE	0xc0000000	/* base address */
@@ -312,9 +335,10 @@
 #define CFG_PCI1_MEM_BASE	0x80000000
 #define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
 #define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI1_IO_BASE	0xe2000000
-#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */
+
+#define CFG_PCI1_IO_BASE	0x0
+#define CFG_PCI1_IO_PHYS	0xe2000000
+#define CFG_PCI1_IO_SIZE	0x100000	/* 1M */
 
 #if defined(CONFIG_PCI)
 
@@ -497,8 +521,10 @@
 #define	CONFIG_EXTRA_ENV_SETTINGS				        \
    "netdev=eth0\0"                                                      \
    "consoledev=ttyS0\0"                                                 \
-   "ramdiskaddr=400000\0"						\
-   "ramdiskfile=your.ramdisk.u-boot\0"
+   "ramdiskaddr=600000\0"						\
+   "ramdiskfile=your.ramdisk.u-boot\0"					\
+   "fdtaddr=400000\0"							\
+   "fdtfile=your.fdt.dtb\0"
 
 #define CONFIG_NFSBOOTCOMMAND	                                        \
    "setenv bootargs root=/dev/nfs rw "                                  \
@@ -506,13 +532,15 @@
       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
       "console=$consoledev,$baudrate $othbootargs;"                     \
    "tftp $loadaddr $bootfile;"                                          \
-   "bootm $loadaddr"
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr - $fdtaddr"
 
 #define CONFIG_RAMBOOTCOMMAND \
    "setenv bootargs root=/dev/ram rw "                                  \
       "console=$consoledev,$baudrate $othbootargs;"                     \
    "tftp $ramdiskaddr $ramdiskfile;"                                    \
    "tftp $loadaddr $bootfile;"                                          \
+   "tftp $fdtaddr $fdtfile;"						\
    "bootm $loadaddr $ramdiskaddr"
 
 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h
index 1af923103f..418a3a38e6 100644
--- a/include/configs/MPC8540EVAL.h
+++ b/include/configs/MPC8540EVAL.h
@@ -179,12 +179,16 @@
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
-/* I2C */
-#define  CONFIG_HARD_I2C		/* I2C with hardware support*/
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
 #define CFG_I2C_SLAVE		0x7F
 #define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+#define CFG_I2C_OFFSET		0x3000
 
 /* General PCI */
 #define CFG_PCI_MEM_BASE	0x80000000
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index c96b98b54d..db389cfe67 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -308,13 +308,29 @@ extern unsigned long get_clock_freq(void);
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
-/* I2C */
-#define CONFIG_HARD_I2C			/* I2C with hardware support */
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE	8192
+
+#define OF_CPU			"PowerPC,8541@0"
+#define OF_SOC			"soc8541@e0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 8)
+#define OF_STDOUT_PATH		"/soc8541@e0000000/serial@4600"
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CFG_I2C_EEPROM_ADDR	0x57
 #define CFG_I2C_SLAVE		0x7F
 #define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+#define CFG_I2C_OFFSET		0x3000
 
 /*
  * General PCI
@@ -323,32 +339,27 @@ extern unsigned long get_clock_freq(void);
 #define CFG_PCI1_MEM_BASE	0x80000000
 #define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
 #define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI1_IO_BASE	0xe2000000
-#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */
+#define CFG_PCI1_IO_BASE	0x00000000
+#define CFG_PCI1_IO_PHYS	0xe2000000
+#define CFG_PCI1_IO_SIZE	0x100000	/* 1M */
 
 #define CFG_PCI2_MEM_BASE	0xa0000000
 #define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
 #define CFG_PCI2_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI2_IO_BASE	0xe3000000
-#define CFG_PCI2_IO_PHYS	CFG_PCI2_IO_BASE
-#define CFG_PCI2_IO_SIZE	0x1000000	/* 16M */
+#define CFG_PCI2_IO_BASE	0x00000000
+#define CFG_PCI2_IO_PHYS	0xe2100000
+#define CFG_PCI2_IO_SIZE	0x100000	/* 1M */
 
 
 #if defined(CONFIG_PCI)
 
+#define CONFIG_MPC85XX_PCI2
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
 
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
 
-#if !defined(CONFIG_PCI_PNP)
-    #define PCI_ENET0_IOADDR      0xe0000000
-    #define PCI_ENET0_MEMADDR     0xe0000000
-    #define PCI_IDSEL_NUMBER      0x0c 	/*slot0->3(IDSEL)=12->15*/
-#endif
-
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 
@@ -482,8 +493,10 @@ extern unsigned long get_clock_freq(void);
 #define	CONFIG_EXTRA_ENV_SETTINGS				        \
    "netdev=eth0\0"                                                      \
    "consoledev=ttyS1\0"                                                 \
-   "ramdiskaddr=400000\0"                                               \
-   "ramdiskfile=your.ramdisk.u-boot\0"
+   "ramdiskaddr=600000\0"                                               \
+   "ramdiskfile=your.ramdisk.u-boot\0"					\
+   "fdtaddr=400000\0"							\
+   "fdtfile=your.fdt.dtb\0"
 
 #define CONFIG_NFSBOOTCOMMAND	                                        \
    "setenv bootargs root=/dev/nfs rw "                                  \
@@ -491,7 +504,8 @@ extern unsigned long get_clock_freq(void);
       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
       "console=$consoledev,$baudrate $othbootargs;"                     \
    "tftp $loadaddr $bootfile;"                                          \
-   "bootm $loadaddr"
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr - $fdtaddr"
 
 #define CONFIG_RAMBOOTCOMMAND \
    "setenv bootargs root=/dev/ram rw "                                  \
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 4ca8bc35db..7c4849fadf 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -314,13 +314,29 @@ extern unsigned long get_clock_freq(void);
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
-/* I2C */
-#define CONFIG_HARD_I2C			/* I2C with hardware support */
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE	8192
+
+#define OF_CPU			"PowerPC,8548@0"
+#define OF_SOC			"soc8548@e0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 8)
+#define OF_STDOUT_PATH		"/soc8548@e0000000/serial@4600"
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CFG_I2C_EEPROM_ADDR	0x57
 #define CFG_I2C_SLAVE		0x7F
 #define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+#define CFG_I2C_OFFSET		0x3000
 
 /*
  * General PCI
@@ -329,32 +345,27 @@ extern unsigned long get_clock_freq(void);
 #define CFG_PCI1_MEM_BASE	0x80000000
 #define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
 #define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI1_IO_BASE	0xe2000000
-#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */
+#define CFG_PCI1_IO_BASE	0x00000000
+#define CFG_PCI1_IO_PHYS	0xe2000000
+#define CFG_PCI1_IO_SIZE	0x00100000	/* 1M */
 
 #define CFG_PCI2_MEM_BASE	0xa0000000
 #define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
 #define CFG_PCI2_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI2_IO_BASE	0xe3000000
-#define CFG_PCI2_IO_PHYS	CFG_PCI2_IO_BASE
-#define CFG_PCI2_IO_SIZE	0x1000000	/* 16M */
+#define CFG_PCI2_IO_BASE	0x00000000
+#define CFG_PCI2_IO_PHYS	0xe2100000
+#define CFG_PCI2_IO_SIZE	0x00100000	/* 1M */
 
 
 #if defined(CONFIG_PCI)
 
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+#define CONFIG_85XX_PCI2
 
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
 
-#if !defined(CONFIG_PCI_PNP)
-    #define PCI_ENET0_IOADDR      0xe0000000
-    #define PCI_ENET0_MEMADDR     0xe0000000
-    #define PCI_IDSEL_NUMBER      0x0c 	/*slot0->3(IDSEL)=12->15*/
-#endif
-
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 
@@ -374,7 +385,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_MPC85XX_TSEC2_NAME	"eTSEC1"
 #define CONFIG_MPC85XX_TSEC3	1
 #define CONFIG_MPC85XX_TSEC3_NAME	"eTSEC2"
-#define CONFIG_MPC85XX_TSEC4	1
+#undef CONFIG_MPC85XX_TSEC4
 #define CONFIG_MPC85XX_TSEC4_NAME	"eTSEC3"
 #undef CONFIG_MPC85XX_FEC
 
@@ -382,13 +393,11 @@ extern unsigned long get_clock_freq(void);
 #define TSEC2_PHY_ADDR		1
 #define TSEC3_PHY_ADDR		2
 #define TSEC4_PHY_ADDR		3
-#define FEC_PHY_ADDR		3
 
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
 #define TSEC3_PHYIDX		0
 #define TSEC4_PHYIDX		0
-#define FEC_PHYIDX		0
 
 /* Options are: eTSEC[0-3] */
 #define CONFIG_ETHPRIME		"eTSEC0"
@@ -476,6 +485,8 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
 #define CONFIG_HAS_ETH2
 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
+#define CONFIG_HAS_ETH3
+#define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
 #endif
 
 #define CONFIG_IPADDR    192.168.1.253
@@ -498,8 +509,11 @@ extern unsigned long get_clock_freq(void);
 #define	CONFIG_EXTRA_ENV_SETTINGS				        \
    "netdev=eth0\0"                                                      \
    "consoledev=ttyS1\0"                                                 \
-   "ramdiskaddr=400000\0"                                               \
-   "ramdiskfile=your.ramdisk.u-boot\0"
+   "ramdiskaddr=600000\0"                                               \
+   "ramdiskfile=your.ramdisk.u-boot\0"					\
+   "fdtaddr=400000\0"							\
+   "fdtfile=your.fdt.dtb\0"
+
 
 #define CONFIG_NFSBOOTCOMMAND	                                        \
    "setenv bootargs root=/dev/nfs rw "                                  \
@@ -507,7 +521,9 @@ extern unsigned long get_clock_freq(void);
       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
       "console=$consoledev,$baudrate $othbootargs;"                     \
    "tftp $loadaddr $bootfile;"                                          \
-   "bootm $loadaddr"
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr - $fdtaddr"
+
 
 #define CONFIG_RAMBOOTCOMMAND \
    "setenv bootargs root=/dev/ram rw "                                  \
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index a44e3ec845..4c8b4e73f3 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -308,13 +308,29 @@ extern unsigned long get_clock_freq(void);
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
-/* I2C */
-#define CONFIG_HARD_I2C			/* I2C with hardware support */
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE	8192
+
+#define OF_CPU			"PowerPC,8555@0"
+#define OF_SOC			"soc8555@e0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 8)
+#define OF_STDOUT_PATH		"/soc8555@e0000000/serial@4600"
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CFG_I2C_EEPROM_ADDR	0x57
 #define CFG_I2C_SLAVE		0x7F
 #define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+#define CFG_I2C_OFFSET		0x3000
 
 /*
  * General PCI
@@ -323,33 +339,28 @@ extern unsigned long get_clock_freq(void);
 #define CFG_PCI1_MEM_BASE	0x80000000
 #define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
 #define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI1_IO_BASE	0xe2000000
-#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */
+#define CFG_PCI1_IO_BASE	0x00000000
+#define CFG_PCI1_IO_PHYS	0xe2000000
+#define CFG_PCI1_IO_SIZE	0x00100000	/* 1M */
 
 #define CFG_PCI2_MEM_BASE	0xa0000000
 #define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
 #define CFG_PCI2_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI2_IO_BASE	0xe3000000
-#define CFG_PCI2_IO_PHYS	CFG_PCI2_IO_BASE
-#define CFG_PCI2_IO_SIZE	0x1000000	/* 16M */
+#define CFG_PCI2_IO_BASE	0x00000000
+#define CFG_PCI2_IO_PHYS	0xe2100000
+#define CFG_PCI2_IO_SIZE	0x00100000	/* 1M */
 
 
 #if defined(CONFIG_PCI)
 
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+#define CONFIG_MPC85XX_PCI2
 
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
 
-#if !defined(CONFIG_PCI_PNP)
-    #define PCI_ENET0_IOADDR      0xe0000000
-    #define PCI_ENET0_MEMADDR     0xe0000000
-    #define PCI_IDSEL_NUMBER      0x0c 	/*slot0->3(IDSEL)=12->15*/
-#endif
-
-#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 
 #endif	/* CONFIG_PCI */
@@ -482,8 +493,10 @@ extern unsigned long get_clock_freq(void);
 #define	CONFIG_EXTRA_ENV_SETTINGS				        \
    "netdev=eth0\0"                                                      \
    "consoledev=ttyS1\0"                                                 \
-   "ramdiskaddr=400000\0"                                               \
-   "ramdiskfile=your.ramdisk.u-boot\0"
+   "ramdiskaddr=600000\0"                                               \
+   "ramdiskfile=your.ramdisk.u-boot\0"					\
+   "fdtaddr=400000\0"							\
+   "fdtfile=your.fdt.dtb\0"
 
 #define CONFIG_NFSBOOTCOMMAND	                                        \
    "setenv bootargs root=/dev/nfs rw "                                  \
@@ -491,7 +504,8 @@ extern unsigned long get_clock_freq(void);
       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
       "console=$consoledev,$baudrate $othbootargs;"                     \
    "tftp $loadaddr $bootfile;"                                          \
-   "bootm $loadaddr"
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr - $fdtaddr"
 
 #define CONFIG_RAMBOOTCOMMAND \
    "setenv bootargs root=/dev/ram rw "                                  \
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 2d5031b77d..835bf5cb64 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -290,12 +290,28 @@
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
-/* I2C */
-#define  CONFIG_HARD_I2C		/* I2C with hardware support*/
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE	8192
+
+#define OF_CPU			"PowerPC,8560@0"
+#define OF_SOC			"soc8560@e0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 8)
+#define OF_STDOUT_PATH		"/soc8560@e0000000/serial@4500"
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CFG_I2C_SLAVE		0x7F
 #define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+#define CFG_I2C_OFFSET		0x3000
 
 /* RapidIO MMU */
 #define CFG_RIO_MEM_BASE	0xc0000000	/* base address */
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
new file mode 100644
index 0000000000..246ac7f316
--- /dev/null
+++ b/include/configs/MPC8641HPCN.h
@@ -0,0 +1,634 @@
+/*
+ * Copyright 2006 Freescale Semiconductor.
+ *
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * MPC8641HPCN board configuration file
+ *
+ * Make sure you change the MAC address and other network params first,
+ * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_MPC86xx		1	/* MPC86xx */
+#define CONFIG_MPC8641		1	/* MPC8641 specific */
+#define CONFIG_MPC8641HPCN	1	/* MPC8641HPCN board specific */
+#define CONFIG_NUM_CPUS         2       /* Number of CPUs in the system */
+#define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
+#undef DEBUG
+
+#ifdef RUN_DIAG
+#define CFG_DIAG_ADDR        0xff800000
+#endif
+
+#define CFG_RESET_ADDRESS    0xfff00100
+
+/*#undef CONFIG_PCI*/
+#define CONFIG_PCI
+
+#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#undef CONFIG_DDR_DLL			/* possible DLL fix needed */
+#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
+#define CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+#define CONFIG_NUM_DDR_CONTROLLERS     2
+/* #define CONFIG_DDR_INTERLEAVE               1 */
+#define CACHE_LINE_INTERLEAVING		0x20000000
+#define PAGE_INTERLEAVING		0x21000000
+#define BANK_INTERLEAVING		0x22000000
+#define SUPER_BANK_INTERLEAVING		0x23000000
+
+
+#define CONFIG_ALTIVEC          1
+
+/*
+ * L2CR setup -- make sure this is right for your board!
+ */
+#define CFG_L2
+#define L2_INIT		0
+#define L2_ENABLE	(L2CR_L2E)
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
+
+#undef	CFG_DRAM_TEST			/* memory test, takes time */
+#define CFG_MEMTEST_START	0x00200000	/* memtest region */
+#define CFG_MEMTEST_END		0x00400000
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
+#define CFG_CCSRBAR		0xf8000000	/* relocated CCSRBAR */
+#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define MPC86xx_DDR_SDRAM_CLK_CNTL
+
+#if defined(CONFIG_SPD_EEPROM)
+    /*
+     * Determine DDR configuration from I2C interface.
+     */
+    #define SPD_EEPROM_ADDRESS1		0x51		/* DDR DIMM */
+    #define SPD_EEPROM_ADDRESS2		0x52		/* DDR DIMM */
+    #define SPD_EEPROM_ADDRESS3		0x53		/* DDR DIMM */
+    #define SPD_EEPROM_ADDRESS4		0x54		/* DDR DIMM */
+
+#else
+    /*
+     * Manually set up DDR1 parameters
+     */
+
+    #define CFG_SDRAM_SIZE	256		/* DDR is 256MB */
+
+    #define CFG_DDR_CS0_BNDS	0x0000000F
+    #define CFG_DDR_CS0_CONFIG	0x80010102      /* Enable, no interleaving */
+    #define CFG_DDR_EXT_REFRESH 0x00000000
+    #define CFG_DDR_TIMING_0    0x00260802
+    #define CFG_DDR_TIMING_1	0x39357322
+    #define CFG_DDR_TIMING_2	0x14904cc8
+    #define CFG_DDR_MODE_1	0x00480432
+    #define CFG_DDR_MODE_2	0x00000000
+    #define CFG_DDR_INTERVAL	0x06090100
+    #define CFG_DDR_DATA_INIT   0xdeadbeef
+    #define CFG_DDR_CLK_CTRL    0x03800000
+    #define CFG_DDR_OCD_CTRL    0x00000000
+    #define CFG_DDR_OCD_STATUS  0x00000000
+    #define CFG_DDR_CONTROL	0xe3008000	/* Type = DDR2 */
+    #define CFG_DDR_CONTROL2	0x04400000
+
+    /* Not used in fixed_sdram function */
+
+    #define CFG_DDR_MODE	0x00000022
+    #define CFG_DDR_CS1_BNDS	0x00000000
+    #define CFG_DDR_CS2_BNDS	0x00000FFF	/* Not done */
+    #define CFG_DDR_CS3_BNDS	0x00000FFF	/* Not done */
+    #define CFG_DDR_CS4_BNDS	0x00000FFF	/* Not done */
+    #define CFG_DDR_CS5_BNDS	0x00000FFF	/* Not done */
+#endif
+
+#define CFG_ID_EEPROM	1
+#define ID_EEPROM_ADDR 0x57
+
+/*
+ * In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000.
+ * There is an 8MB flash.  In effect, the addresses from fe000000 to fe7fffff
+ * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff.
+ * However, when u-boot comes up, the flash_init needs hard start addresses
+ * to build its info table.  For user convenience, the flash addresses is
+ * fe800000 and ff800000.  That way, u-boot knows where the flash is
+ * and the user can download u-boot code from promjet to fef00000, a
+ * more intuitive location than fe700000.
+ *
+ * Note that, on switching the boot location, fef00000 becomes fff00000.
+ */
+#define CFG_FLASH_BASE          0xfe800000     /* start of FLASH 32M */
+#define CFG_FLASH_BASE2		0xff800000
+
+#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2}
+
+#define CFG_BR0_PRELIM		0xff001001	/* port size 16bit */
+#define CFG_OR0_PRELIM		0xff006ff7	/* 16MB Boot Flash area*/
+
+#define CFG_BR1_PRELIM		0xfe001001	/* port size 16bit */
+#define CFG_OR1_PRELIM		0xff006ff7	/* 16MB Alternate Boot Flash area*/
+
+#define CFG_BR2_PRELIM		0xf8201001	/* port size 16bit */
+#define CFG_OR2_PRELIM		0xfff06ff7	/* 1MB Compact Flash area*/
+
+#define CFG_BR3_PRELIM		0xf8100801	/* port size 8bit */
+#define CFG_OR3_PRELIM		0xfff06ff7	/* 1MB PIXIS area*/
+
+
+#define PIXIS_BASE	0xf8100000      /* PIXIS registers */
+#define PIXIS_ID		0x0	/* Board ID at offset 0 */
+#define PIXIS_VER		0x1	/* Board version at offset 1 */
+#define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
+#define PIXIS_RST		0x4	/* PIXIS Reset Control register */
+#define PIXIS_AUX		0x6	/* PIXIS Auxiliary register; Scratch register */
+#define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
+#define PIXIS_VCTL		0x10	/* VELA Control Register */
+#define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
+#define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
+#define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
+#define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
+#define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
+#define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
+#define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
+
+#define CFG_MAX_FLASH_BANKS	2		/* number of banks */
+#define CFG_MAX_FLASH_SECT	128		/* sectors per device */
+
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
+
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_FLASH_EMPTY_INFO
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef  CFG_RAMBOOT
+#endif
+
+#if defined(CFG_RAMBOOT)
+#undef CFG_FLASH_CFI_DRIVER
+#undef CONFIG_SPD_EEPROM
+#define CFG_SDRAM_SIZE	256
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK	1
+#ifndef CFG_INIT_RAM_LOCK
+#define CFG_INIT_RAM_ADDR	0x0fd00000	/* Initial RAM address */
+#else
+#define CFG_INIT_RAM_ADDR	0xf8400000	/* Initial RAM address */
+#endif
+#define CFG_INIT_RAM_END    	0x4000	    	/* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE  	128		/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN	    	(256 * 1024)    /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN	    	(128 * 1024)    /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX     1
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE    1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef  CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/*
+ * Pass open firmware flat tree to kernel
+ */
+#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE	8192
+
+#define OF_CPU		"PowerPC,8641@0"
+#define OF_SOC		"soc8641@f8000000"
+#define OF_TBCLK	(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH	"/soc8641@f8000000/serial@4500"
+
+#define CFG_64BIT_VSPRINTF	1
+#define CFG_64BIT_STRTOUL	1
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+#define CFG_I2C_OFFSET		0x3100
+
+/*
+ * RapidIO MMU
+ */
+#define CFG_RIO_MEM_BASE	0xc0000000	/* base address */
+#define CFG_RIO_MEM_PHYS	CFG_RIO_MEM_BASE
+#define CFG_RIO_MEM_SIZE	0x20000000	/* 128M */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE	0x80000000
+#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCI1_IO_BASE	0xe2000000
+#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
+#define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */
+
+/* PCI view of System Memory */
+#define CFG_PCI_MEMORY_BUS      0x00000000
+#define CFG_PCI_MEMORY_PHYS     0x00000000
+#define CFG_PCI_MEMORY_SIZE     0x80000000
+
+/* For RTL8139 */
+#define KSEG1ADDR(x)		({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
+#define _IO_BASE                0x00000000
+
+#define CFG_PCI2_MEM_BASE	0xa0000000
+#define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
+#define CFG_PCI2_MEM_SIZE	0x10000000	/* 256M */
+#define CFG_PCI2_IO_BASE	0xe3000000
+#define CFG_PCI2_IO_PHYS	CFG_PCI2_IO_BASE
+#define CFG_PCI2_IO_SIZE	0x1000000	/* 16M */
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
+
+#undef CFG_SCSI_SCAN_BUS_REVERSE
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+
+#define CONFIG_RTL8139
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+    #define PCI_ENET0_IOADDR	0xe0000000
+    #define PCI_ENET0_MEMADDR	0xe0000000
+    #define PCI_IDSEL_NUMBER	0x0c 	/* slot0->3(IDSEL)=12->15 */
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SCSI_AHCI
+
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_SATA_ULI5288
+#define CFG_SCSI_MAX_SCSI_ID	4
+#define CFG_SCSI_MAX_LUN	1
+#define CFG_SCSI_MAX_DEVICE 	(CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
+#define CFG_SCSI_MAXDEVICE	CFG_SCSI_MAX_DEVICE
+#endif
+
+#endif	/* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 	1
+#endif
+
+#define CONFIG_MII		1	/* MII PHY management */
+
+#define CONFIG_MPC86XX_TSEC1    1
+#define CONFIG_MPC86XX_TSEC1_NAME       "eTSEC1"
+#define CONFIG_MPC86XX_TSEC2    1
+#define CONFIG_MPC86XX_TSEC2_NAME       "eTSEC2"
+#define CONFIG_MPC86XX_TSEC3    1
+#define CONFIG_MPC86XX_TSEC3_NAME       "eTSEC3"
+#define CONFIG_MPC86XX_TSEC4    1
+#define CONFIG_MPC86XX_TSEC4_NAME       "eTSEC4"
+
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define TSEC3_PHY_ADDR		2
+#define TSEC4_PHY_ADDR		3
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC3_PHYIDX		0
+#define TSEC4_PHYIDX		0
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * BAT0         2G     Cacheable, non-guarded
+ * 0x0000_0000  2G     DDR
+ */
+#define CFG_DBAT0L      (BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_DBAT0U      (BATU_BL_2G | BATU_VS | BATU_VP)
+#define CFG_IBAT0L      (BATL_PP_RW | BATL_MEMCOHERENCE )
+#define CFG_IBAT0U      CFG_DBAT0U
+
+/*
+ * BAT1         1G     Cache-inhibited, guarded
+ * 0x8000_0000  512M   PCI-Express 1 Memory
+ * 0xa000_0000  512M   PCI-Express 2 Memory
+ *	Changed it for operating from 0xd0000000
+ */
+#define CFG_DBAT1L      ( CFG_PCI1_MEM_BASE | BATL_PP_RW \
+			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT1U      (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT1L      (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT1U      CFG_DBAT1U
+
+/*
+ * BAT2         512M   Cache-inhibited, guarded
+ * 0xc000_0000  512M   RapidIO Memory
+ */
+#define CFG_DBAT2L      (CFG_RIO_MEM_BASE | BATL_PP_RW \
+			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT2U      (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
+#define CFG_IBAT2L      (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U      CFG_DBAT2U
+
+/*
+ * BAT3         4M     Cache-inhibited, guarded
+ * 0xf800_0000  4M     CCSR
+ */
+#define CFG_DBAT3L      ( CFG_CCSRBAR | BATL_PP_RW \
+			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT3U      (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CFG_IBAT3L      (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U      CFG_DBAT3U
+
+/*
+ * BAT4         32M    Cache-inhibited, guarded
+ * 0xe200_0000  16M    PCI-Express 1 I/O
+ * 0xe300_0000  16M    PCI-Express 2 I/0
+ *    Note that this is at 0xe0000000
+ */
+#define CFG_DBAT4L      ( CFG_PCI1_IO_BASE | BATL_PP_RW \
+			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT4U      (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_IBAT4L      (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT4U      CFG_DBAT4U
+
+/*
+ * BAT5         128K   Cacheable, non-guarded
+ * 0xe401_0000  128K   Init RAM for stack in the CPU DCache (no backing memory)
+ */
+#define CFG_DBAT5L      (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_DBAT5U      (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CFG_IBAT5L      CFG_DBAT5L
+#define CFG_IBAT5U      CFG_DBAT5U
+
+/*
+ * BAT6         32M    Cache-inhibited, guarded
+ * 0xfe00_0000  32M    FLASH
+ */
+#define CFG_DBAT6L      ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
+			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT6U      ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_IBAT6L      ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_IBAT6U      CFG_DBAT6U
+
+#define CFG_DBAT7L 0x00000000
+#define CFG_DBAT7U 0x00000000
+#define CFG_IBAT7L 0x00000000
+#define CFG_IBAT7U 0x00000000
+
+/*
+ * Environment
+ */
+#ifndef CFG_RAMBOOT
+    #define CFG_ENV_IS_IN_FLASH	1
+    #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+    #define CFG_ENV_SECT_SIZE		0x40000	/* 256K(one sector) for env */
+    #define CFG_ENV_SIZE		0x2000
+#else
+    #define CFG_NO_FLASH		1	/* Flash is not usable now */
+    #define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+    #define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+    #define CFG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+#if defined(CFG_RAMBOOT)
+  #if defined(CONFIG_PCI)
+    #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
+				 | CFG_CMD_PING		\
+				 | CFG_CMD_PCI		\
+				 | CFG_CMD_I2C		\
+				 | CFG_CMD_SCSI		\
+				 | CFG_CMD_EXT2)	\
+				&			\
+				 ~(CFG_CMD_ENV		\
+				  | CFG_CMD_IMLS	\
+				  | CFG_CMD_FLASH	\
+				  | CFG_CMD_LOADS))
+  #else
+    #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
+				 | CFG_CMD_PING		\
+				 | CFG_CMD_I2C		\
+				 | CFG_CMD_SCSI		\
+				 | CGF_CMD_EXT2)	\
+				&			\
+				 ~(CFG_CMD_ENV		\
+				 | CFG_CMD_IMLS		\
+				 | CFG_CMD_FLASH	\
+				 | CFG_CMD_LOADS))
+  #endif
+#else
+  #if defined(CONFIG_PCI)
+    #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL		\
+				| CFG_CMD_PCI		\
+				| CFG_CMD_PING		\
+				| CFG_CMD_I2C		\
+				| CFG_CMD_SCSI		\
+				| CFG_CMD_EXT2)
+  #else
+    #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL		\
+				| CFG_CMD_PING		\
+				| CFG_CMD_I2C)
+  #endif
+#endif
+
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	*/
+#define CFG_LOAD_ADDR	0x2000000	/* default load address */
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+    #define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+    #define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE		32768
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR   00:E0:0C:00:00:01
+#define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
+#define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
+#define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
+#endif
+
+#define CONFIG_HAS_ETH1		1
+#define CONFIG_HAS_ETH2		1
+#define CONFIG_HAS_ETH3		1
+
+#define CONFIG_IPADDR		192.168.1.100
+
+#define CONFIG_HOSTNAME		unknown
+#define CONFIG_ROOTPATH		/opt/nfsroot
+#define CONFIG_BOOTFILE		uImage
+
+#define CONFIG_SERVERIP		192.168.1.1
+#define CONFIG_GATEWAYIP	192.168.1.1
+#define CONFIG_NETMASK		255.255.255.0
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				        \
+   "netdev=eth0\0"                                                      \
+   "consoledev=ttyS0\0"                                                 \
+   "ramdiskaddr=2000000\0"						\
+   "ramdiskfile=your.ramdisk.u-boot\0"                                  \
+   "dtbaddr=400000\0"						\
+   "dtbfile=mpc8641_hpcn.dtb\0"                                  \
+   "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
+   "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
+   "maxcpus=2"
+
+
+#define CONFIG_NFSBOOTCOMMAND	                                        \
+   "setenv bootargs root=/dev/nfs rw "                                  \
+      "nfsroot=$serverip:$rootpath "                                    \
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $loadaddr $bootfile;"                                          \
+   "tftp $dtbaddr $dtbfile;"                                          \
+   "bootm $loadaddr - $dtbaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+   "setenv bootargs root=/dev/ram rw "                                  \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $ramdiskaddr $ramdiskfile;"                                    \
+   "tftp $loadaddr $bootfile;"                                          \
+   "tftp $dtbaddr $dtbfile;"                                          \
+   "bootm $loadaddr $ramdiskaddr $dtbaddr"
+
+#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/PM854.h b/include/configs/PM854.h
index da01186771..4fb54402b1 100644
--- a/include/configs/PM854.h
+++ b/include/configs/PM854.h
@@ -193,12 +193,16 @@
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
-/* I2C */
-#define	 CONFIG_HARD_I2C		/* I2C with hardware support*/
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CFG_I2C_SLAVE		0x7F
 #define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
+#define CFG_I2C_OFFSET		0x3000
 
 /*
  * EEPROM configuration
diff --git a/include/configs/PM856.h b/include/configs/PM856.h
index 4d834878ee..87ab934873 100644
--- a/include/configs/PM856.h
+++ b/include/configs/PM856.h
@@ -190,12 +190,16 @@
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
-/* I2C */
-#define  CONFIG_HARD_I2C		/* I2C with hardware support*/
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CFG_I2C_SLAVE		0x7F
 #define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+#define CFG_I2C_OFFSET		0x3000
 
 /*
  * EEPROM configuration
diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h
index 0451b20819..f8e3397a3f 100644
--- a/include/configs/SBC8540.h
+++ b/include/configs/SBC8540.h
@@ -214,12 +214,16 @@
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
-/* I2C */
-#define	 CONFIG_HARD_I2C		/* I2C with hardware support*/
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
 #define CFG_I2C_SLAVE		0x7F
 #define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
+#define CFG_I2C_OFFSET		0x3000
 
 #define CFG_PCI_MEM_BASE	0xC0000000
 #define CFG_PCI_MEM_PHYS	0xC0000000
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index be83b67672..08674ca49f 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -37,7 +37,8 @@
 #define CONFIG_TQM5200		1	/* ... on TQM5200 module		*/
 #undef CONFIG_TQM5200_REV100		/*  define for revision 100 modules	*/
 
-#ifndef CONFIG_CAM5200			/* On a Cameron board or ...		*/
+/* On a Cameron or on a FO300 board or ...				*/
+#if !defined(CONFIG_CAM5200) && !defined(CONFIG_FO300)
 #define CONFIG_STK52XX		1	/* ... on a STK52XX board		*/
 #endif
 
@@ -58,6 +59,20 @@
 #define CONFIG_BAUDRATE		115200	/* ... at 115200 bps			*/
 #define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
+#ifdef CONFIG_FO300
+#define CFG_DEVICE_NULLDEV		1	/* enable null device */
+#define CONFIG_SILENT_CONSOLE		1	/* enable silent startup */
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* used to detect S1 switch position */
+#define CONFIG_USB_BIN_FIXUP		1	/* for a buggy USB device */
+#if 0
+#define FO300_SILENT_CONSOLE_WHEN_S1_CLOSED	1	/* silent console on PSC1 when S1 */
+							/* switch is closed */
+#endif
+
+#undef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED		/* silent console on PSC1 when S1 */
+							/* switch is open */
+#endif	/* CONFIG_FO300 */
+
 #ifdef CONFIG_STK52XX
 #define CONFIG_PS2KBD			/* AT-PS/2 Keyboard		*/
 #define CONFIG_PS2MULT			/* .. on PS/2 Multiplexer	*/
@@ -105,12 +120,18 @@
 #define CONFIG_VIDEO_SM501_32BPP
 #define CONFIG_CFB_CONSOLE
 #define CONFIG_VIDEO_LOGO
-#define CONFIG_VGA_AS_SINGLE_DEVICE
+
+#ifndef CONFIG_FO300
 #define CONFIG_CONSOLE_EXTRA_INFO
+#else
+#define CONFIG_VIDEO_BMP_LOGO
+#endif
+
+#define CONFIG_VGA_AS_SINGLE_DEVICE
 #define CONFIG_VIDEO_SW_CURSOR
 #define CONFIG_SPLASH_SCREEN
 #define CFG_CONSOLE_IS_IN_ENV
-#endif
+#endif /* #ifndef CONFIG_TQM5200S */
 
 #ifdef CONFIG_VIDEO
 #define ADD_BMP_CMD		CFG_CMD_BMP
@@ -124,7 +145,7 @@
 #define CONFIG_ISO_PARTITION
 
 /* USB */
-#ifdef CONFIG_STK52XX
+#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
 #define CONFIG_USB_OHCI
 #define ADD_USB_CMD		CFG_CMD_USB | CFG_CMD_FAT
 #define CONFIG_USB_STORAGE
@@ -148,7 +169,7 @@
 #endif
 
 /* IDE */
-#if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX)
+#if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX) || defined(CONFIG_FO300)
 #define ADD_IDE_CMD		(CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2)
 #else
 #define ADD_IDE_CMD		0
@@ -196,37 +217,19 @@
 
 #undef	CONFIG_BOOTARGS
 
-#ifdef CONFIG_STK52XX
-# if defined(CONFIG_TQM5200_B)
-#  if defined(CFG_LOWBOOT)
-#   define ENV_UPDT							\
-	"update=protect off FC000000 FC07FFFF;"				\
-		"erase FC000000 FC07FFFF;"				\
-		"cp.b 200000 FC000000 ${filesize};"			\
-		"protect on FC000000 FC07FFFF\0"
-#  else	/* highboot */
-#   define ENV_UPDT							\
-	"update=protect off FFF00000 FFF7FFFF;"				\
-		"erase FFF00000 FFF7FFFF;"				\
+#if defined(CONFIG_TQM5200_B) && !defined(CFG_LOWBOOT)
+# define ENV_UPDT							\
+	"update=protect off FFF00000 +${filesize};"			\
+		"erase FFF00000 +${filesize};"				\
 		"cp.b 200000 FFF00000 ${filesize};"			\
-		"protect on FFF00000 FFF7FFFF\0"
-#  endif /* CFG_LOWBOOT */
-# else	/* !CONFIG_TQM5200_B */
-#  define ENV_UPDT							\
-	"update=protect off FC000000 FC05FFFF;"				\
-		"erase FC000000 FC05FFFF;"				\
-		"cp.b 200000 FC000000 ${filesize};"			\
-		"protect on FC000000 FC05FFFF\0"
-# endif /* CONFIG_TQM5200_B */
-#elif defined (CONFIG_CAM5200)
+		"protect on FFF00000 +${filesize}\0"
+#else	/* default lowboot configuration */
 #   define ENV_UPDT							\
-	"update=protect off FC000000 FC03FFFF;"				\
-		"erase FC000000 FC03FFFF;"				\
+	"update=protect off FC000000 +${filesize};"			\
+		"erase FC000000 +${filesize};"				\
 		"cp.b 200000 FC000000 ${filesize};"			\
-		"protect on FC000000 FC03FFFF\0"
-#else
-# error "Unknown Carrier Board"
-#endif	/* CONFIG_STK52XX */
+		"protect on FC000000 +${filesize}\0"
+#endif
 
 #define CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\
@@ -258,7 +261,7 @@
  */
 #define CFG_IPBSPEED_133		/* define for 133MHz speed */
 
-#if defined(CFG_IPBSPEED_133)
+#if defined(CFG_IPBSPEED_133) && !defined(CONFIG_CAM5200)
 /*
  * PCI Bus clocking configuration
  *
@@ -322,13 +325,29 @@
  */
 #define CFG_FLASH_BASE		0xFC000000
 
+#ifndef CONFIG_CAM5200
 /* use CFI flash driver */
 #define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CFG_FLASH_CFI_DRIVER	1	/* Use the common driver */
 #define CFG_FLASH_BANKS_LIST	{ CFG_BOOTCS_START }
+#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
+					   (= chip selects) */
+#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
+#else /* CONFIG_CAM5200 */
+#define CFG_MAX_FLASH_BANKS	2	/* max num of flash banks
+					   (= chip selects) */
+#define CFG_FLASH_WORD_SIZE	unsigned int /* main flash device with */
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_ADDR0		0x555
+#define CFG_FLASH_ADDR1		0x2AA
+#define CFG_FLASH_2ND_16BIT_DEV	1	/* NIOS flash is a 16bit device */
+#define CFG_MAX_FLASH_SECT	128
+#endif /* ifndef CONFIG_CAM5200 */
+
 #define CFG_FLASH_EMPTY_INFO
 #define CFG_FLASH_SIZE		0x04000000 /* 64 MByte */
-#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
 #define CFG_FLASH_USE_BUFFER_WRITE	1
 
 #if defined (CONFIG_CAM5200)
@@ -339,9 +358,6 @@
 # define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00060000)
 #endif
 
-#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
-					   (= chip selects) */
-
 /* Dynamic MTD partition support */
 #define CONFIG_JFFS2_CMDLINE
 #define MTDIDS_DEFAULT		"nor0=TQM5200-0"
@@ -374,8 +390,13 @@
 #elif defined (CONFIG_CAM5200)
 #   define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:768k(firmware),"	\
 						"1792k(kernel),"	\
-						"3584k(small-fs),"	\
+						"5632k(rootfs),"	\
+						"24m(home)"
+#elif defined (CONFIG_FO300)
+#   define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:640k(firmware),"	\
+						"1408k(kernel),"	\
 						"2m(initrd),"		\
+						"4m(small-fs),"		\
 						"8m(misc),"		\
 						"16m(big-fs)"
 #else
@@ -387,7 +408,7 @@
  */
 #define CFG_ENV_IS_IN_FLASH	1
 #define CFG_ENV_SIZE		0x4000	/* 16 k - keep small for fast booting */
-#if defined(CONFIG_TQM5200_B)
+#if defined(CONFIG_TQM5200_B) || defined (CONFIG_CAM5200)
 #define CFG_ENV_SECT_SIZE	0x40000
 #else
 #define CFG_ENV_SECT_SIZE	0x20000
@@ -445,28 +466,43 @@
 /*
  * GPIO configuration
  *
- * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
- *	Bit 0 (mask: 0x80000000): 1
+ * use CS1: Bit 0 (mask: 0x80000000):
+ *	   1 -> Pin gpio_wkup_6 as second SDRAM chip select (mem_cs1).
  * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
- *	00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
- *	01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
- *	      Use for REV200 STK52XX boards. Do not use with REV100 modules
- *	      (because, there I2C1 is used as I2C bus)
- * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
- * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
- *	000 -> All PSC2 pins are GIOPs
- *	001 -> CAN1/2 on PSC2 pins
- *	       Use for REV100 STK52xx boards
- * use PSC6:
- *   on STK52xx:
- *	use as UART. Pins PSC6_0 to PSC6_3 are used.
- *	Bits 9:11 (mask: 0x00700000):
- *	   101 -> PSC6 : Extended POST test is not available
- *   on MINI-FAP and TQM5200_IB:
- *	use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
- *	   000 -> PSC6 could not be used as UART, CODEC or IrDA
- *   GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
- *   tests.
+ *	  00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
+ *		SPI on PSC3 according to PSC3 setting. Use for CAM5200.
+ *	  01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
+ *		Use for REV200 STK52XX boards and FO300 boards. Do not use
+ *		with REV100 modules (because, there I2C1 is used as I2C bus).
+ * use ATA: Bits 6-7 (mask 0x03000000):
+ *	  00 -> No ATA chip selects, csb_4/5 used as normal chip selects.
+ *		Use for CAM5200 board.
+ *	  01 -> ATA cs0/1 on csb_4/5. Use for the remaining boards.
+ * use PSC6: Bits 9-11 (mask 0x00700000):
+ *	 000 -> use PSC6_0 to PSC6_3 as GPIO, PSC6 could not be used as
+ *		UART, CODEC or IrDA.
+ *		GPIO on PSC6_3 is used in post_hotkeys_pressed() to
+ *		enable extended POST tests.
+ *		Use for MINI-FAP and TQM5200_IB boards.
+ *	 101 -> use PSC6 as UART. Pins PSC6_0 to PSC6_3 are used.
+ *		Extended POST test is not available.
+ *		Use for STK52xx, FO300 and CAM5200 boards.
+ * use PCI_DIS: Bit 16 (mask 0x00008000):
+ *	   1 -> disable PCI controller (on CAM5200 board).
+ * use USB: Bits 18-19 (mask 0x00003000):
+ *	  10 -> two UARTs (on FO300 and CAM5200).
+ * use PSC3: Bits 20-23 (mask: 0x00000f00):
+ *	0000 -> All PSC3 pins are GPIOs.
+ *	1100 -> UART/SPI (on FO300 board).
+ *	0100 -> UART (on CAM5200 board).
+ * use PSC2: Bits 25:27 (mask: 0x00000030):
+ *	 000 -> All PSC2 pins are GPIOs.
+ *	 100 -> UART (on CAM5200 board).
+ *	 001 -> CAN1/2 on PSC2 pins.
+ *	        Use for REV100 STK52xx boards
+ *	 01x -> Use AC97 (on FO300 board).
+ * use PSC1: Bits 29-31 (mask: 0x00000007):
+ *	 100 -> UART (on all boards).
  */
 #if defined (CONFIG_MINIFAP)
 # define CFG_GPS_PORT_CONFIG	0x91000004
@@ -480,6 +516,10 @@
 #   define CFG_GPS_PORT_CONFIG	0x91500004
 #  endif
 # endif
+#elif defined (CONFIG_FO300)
+# define CFG_GPS_PORT_CONFIG	0x91502c24
+#elif defined (CONFIG_CAM5200)
+# define CFG_GPS_PORT_CONFIG	0x8050A444
 #else  /* TMQ5200 Inbetriebnahme-Board */
 # define CFG_GPS_PORT_CONFIG	0x81000004
 #endif
@@ -502,6 +542,7 @@
 #define CFG_LONGHELP			/* undef to save memory	    */
 #define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
 
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
 #define	CFG_PROMPT_HUSH_PS2	"> "
 
@@ -574,6 +615,16 @@
 #define CFG_CS_BURST		0x00000000
 #define CFG_CS_DEADCYCLE	0x33333311	/* 1 dead cycle for flash and SM501 */
 
+#if defined(CONFIG_CAM5200)
+#define CFG_CS4_START		0xB0000000
+#define CFG_CS4_SIZE		0x00010000
+#define CFG_CS4_CFG		0x01019C10
+
+#define CFG_CS5_START		0xD0000000
+#define CFG_CS5_SIZE		0x01208000
+#define CFG_CS5_CFG		0x1414BF10
+#endif
+
 #define CFG_RESET_ADDRESS	0xff000000
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h
index b1c70f88c2..247f705fb6 100644
--- a/include/configs/TQM823L.h
+++ b/include/configs/TQM823L.h
@@ -123,9 +123,8 @@
 #define	CFG_LONGHELP			/* undef to save memory		*/
 #define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
-#if 0
-#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
-#endif
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
 #ifdef	CFG_HUSH_PARSER
 #define	CFG_PROMPT_HUSH_PS2	"> "
 #endif
diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h
index 9f958f5477..1461b5f203 100644
--- a/include/configs/TQM823M.h
+++ b/include/configs/TQM823M.h
@@ -112,9 +112,8 @@
 #define	CFG_LONGHELP			/* undef to save memory		*/
 #define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
-#if 0
-#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
-#endif
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
 #ifdef	CFG_HUSH_PARSER
 #define	CFG_PROMPT_HUSH_PS2	"> "
 #endif
diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h
index 49c3872630..ffd5c0b95c 100644
--- a/include/configs/TQM8260.h
+++ b/include/configs/TQM8260.h
@@ -237,6 +237,13 @@
  */
 #define	CFG_LONGHELP			/* undef to save memory		*/
 #define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index cec7e3ece4..4bbee97db5 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -353,6 +353,12 @@ extern int tqm834x_num_flash_banks;
 #define CFG_LOAD_ADDR		0x2000000	/* default load address */
 #define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
 
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 	#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
@@ -422,9 +428,9 @@ extern int tqm834x_num_flash_banks;
 #define CFG_SICRL	SICRL_LDP_A
 
 /* i-cache and d-cache disabled */
-#define CFG_HID0_INIT		0x000000000
-#define CFG_HID0_FINAL		CFG_HID0_INIT
-#define CFG_HID2		0x000000000
+#define CFG_HID0_INIT	0x000000000
+#define CFG_HID0_FINAL	CFG_HID0_INIT
+#define CFG_HID2	HID2_HBE
 
 /* DDR 0 - 512M */
 #define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
@@ -437,12 +443,21 @@ extern int tqm834x_num_flash_banks;
 #define CFG_IBAT2U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 
 /* PCI */
-#define CFG_IBAT3L	(CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#ifdef CONFIG_PCI
+#define CFG_IBAT3L	(CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 #define CFG_IBAT3U	(CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_IBAT4L	(CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT4L	(CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
 #define CFG_IBAT4U	(CFG_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 #define CFG_IBAT5L	(CFG_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CFG_IBAT5U	(CFG_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP)
+#else
+#define CFG_IBAT3L	(0)
+#define CFG_IBAT3U	(0)
+#define CFG_IBAT4L	(0)
+#define CFG_IBAT4U	(0)
+#define CFG_IBAT5L	(0)
+#define CFG_IBAT5U	(0)
+#endif
 
 /* IMMRBAR */
 #define CFG_IBAT6L	(CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h
index 16b2ce3f05..90ecbadb2e 100644
--- a/include/configs/TQM850L.h
+++ b/include/configs/TQM850L.h
@@ -104,9 +104,8 @@
 #define	CFG_LONGHELP			/* undef to save memory		*/
 #define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
-#if 0
-#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
-#endif
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
 #ifdef	CFG_HUSH_PARSER
 #define	CFG_PROMPT_HUSH_PS2	"> "
 #endif
diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h
index bbc69608b2..b3f8f8d835 100644
--- a/include/configs/TQM850M.h
+++ b/include/configs/TQM850M.h
@@ -102,9 +102,8 @@
 #define	CFG_LONGHELP			/* undef to save memory		*/
 #define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
-#if 0
-#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
-#endif
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
 #ifdef	CFG_HUSH_PARSER
 #define	CFG_PROMPT_HUSH_PS2	"> "
 #endif
diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h
index 198db1954d..49aaeea44d 100644
--- a/include/configs/TQM855L.h
+++ b/include/configs/TQM855L.h
@@ -107,9 +107,8 @@
 #define	CFG_LONGHELP			/* undef to save memory		*/
 #define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
-#if 0
-#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
-#endif
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
 #ifdef	CFG_HUSH_PARSER
 #define	CFG_PROMPT_HUSH_PS2	"> "
 #endif
diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h
index e25a7a204f..50df49e93c 100644
--- a/include/configs/TQM855M.h
+++ b/include/configs/TQM855M.h
@@ -141,9 +141,8 @@
 #define	CFG_LONGHELP			/* undef to save memory		*/
 #define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
-#if 0
-#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
-#endif
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
 #ifdef	CFG_HUSH_PARSER
 #define	CFG_PROMPT_HUSH_PS2	"> "
 #endif
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index 780f27433e..f45f3a2f5a 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -186,18 +186,23 @@
 #define CFG_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-/* Use the HUSH parser */
-#define CFG_HUSH_PARSER
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
 #ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define	CFG_PROMPT_HUSH_PS2	"> "
 #endif
 
-/* I2C */
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
 #define CONFIG_HARD_I2C			/* I2C with hardware support	*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
 #define CFG_I2C_SLAVE		0x7F
 #define CFG_I2C_NOPROBES	{0x48}	/* Don't probe these addrs	*/
+#define CFG_I2C_OFFSET		0x3000
 
 /* I2C RTC */
 #define CONFIG_RTC_DS1337		/* Use ds1337 rtc via i2c	*/
@@ -424,7 +429,7 @@
 #define CONFIG_BOOTDELAY 5		/* -1 disables auto-boot	*/
 
 #define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 	"echo"
 
 #undef	CONFIG_BOOTARGS		/* the boot command will set bootargs	*/
@@ -449,7 +454,7 @@
 		"run nfsargs addip addcons;bootm\0"			\
 	"rootpath=/opt/eldk/ppc_85xx\0"					\
 	"kernel_addr=FE000000\0"					\
-	"ramdisk_addr=FE100000\0"					\
+	"ramdisk_addr=FE180000\0"					\
 	"load=tftp 100000 /tftpboot/$hostname/u-boot.bin\0"		\
 	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
 		"cp.b 100000 fffc0000 40000;"			        \
diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h
index 4a1a4325dc..9be5db1e42 100644
--- a/include/configs/TQM860L.h
+++ b/include/configs/TQM860L.h
@@ -110,9 +110,8 @@
 #define	CFG_LONGHELP			/* undef to save memory		*/
 #define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
-#if 0
-#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
-#endif
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
 #ifdef	CFG_HUSH_PARSER
 #define	CFG_PROMPT_HUSH_PS2	"> "
 #endif
diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h
index 4b754ba9cb..37f6c985d3 100644
--- a/include/configs/TQM860M.h
+++ b/include/configs/TQM860M.h
@@ -108,9 +108,8 @@
 #define	CFG_LONGHELP			/* undef to save memory		*/
 #define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
-#if 0
-#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
-#endif
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
 #ifdef	CFG_HUSH_PARSER
 #define	CFG_PROMPT_HUSH_PS2	"> "
 #endif
diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h
index 1dc9f74d5e..f03690a7b2 100644
--- a/include/configs/TQM862L.h
+++ b/include/configs/TQM862L.h
@@ -110,9 +110,8 @@
 #define	CFG_LONGHELP			/* undef to save memory		*/
 #define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
-#if 0
-#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
-#endif
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
 #ifdef	CFG_HUSH_PARSER
 #define	CFG_PROMPT_HUSH_PS2	"> "
 #endif
diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h
index 3df060c619..495934045f 100644
--- a/include/configs/TQM862M.h
+++ b/include/configs/TQM862M.h
@@ -110,9 +110,8 @@
 #define	CFG_LONGHELP			/* undef to save memory		*/
 #define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
-#if 0
-#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
-#endif
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
 #ifdef	CFG_HUSH_PARSER
 #define	CFG_PROMPT_HUSH_PS2	"> "
 #endif
diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h
index 8f9c2c9cbb..148490b586 100644
--- a/include/configs/TQM866M.h
+++ b/include/configs/TQM866M.h
@@ -151,11 +151,10 @@
 #define CFG_LONGHELP			/* undef to save memory		*/
 #define CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
-#if 0
-#define CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
-#endif
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
 #ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define	CFG_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h
index ede4e3b9b3..d470ade847 100644
--- a/include/configs/TQM885D.h
+++ b/include/configs/TQM885D.h
@@ -160,11 +160,10 @@
 #define CFG_LONGHELP			/* undef to save memory		*/
 #define CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
-#if 0
-#define CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
-#endif
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
 #ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define	CFG_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h
new file mode 100644
index 0000000000..458ebabeb9
--- /dev/null
+++ b/include/configs/atstk1002.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * Configuration settings for the ATSTK1002 CPU daughterboard
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_AVR32			1
+#define CONFIG_AT32AP			1
+#define CONFIG_AT32AP7000		1
+#define CONFIG_ATSTK1002		1
+#define CONFIG_ATSTK1000		1
+
+#define CONFIG_ATSTK1000_EXT_FLASH	1
+
+/*
+ * Timer clock frequency. We're using the CPU-internal COUNT register
+ * for this, so this is equivalent to the CPU core clock frequency
+ */
+#define CFG_HZ				1000
+
+/*
+ * Set up the PLL to run at 199.5 MHz, the CPU to run at 1/2 the PLL
+ * frequency and the peripherals to run at 1/4 the PLL frequency.
+ */
+#define CONFIG_PLL			1
+#define CFG_POWER_MANAGER		1
+#define CFG_OSC0_HZ			20000000
+#define CFG_PLL0_DIV			1
+#define CFG_PLL0_MUL			7
+#define CFG_PLL0_SUPPRESS_CYCLES	16
+#define CFG_CLKDIV_CPU			0
+#define CFG_CLKDIV_HSB			1
+#define CFG_CLKDIV_PBA			2
+#define CFG_CLKDIV_PBB			1
+
+/*
+ * The PLLOPT register controls the PLL like this:
+ *   icp = PLLOPT<2>
+ *   ivco = PLLOPT<1:0>
+ *
+ * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
+ */
+#define CFG_PLL0_OPT			0x04
+
+#define CFG_USART1			1
+
+#define CFG_CONSOLE_UART_DEV		DEVICE_USART1
+
+/* User serviceable stuff */
+#define CONFIG_CMDLINE_TAG		1
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+#define CONFIG_STACKSIZE		(2048)
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_BOOTARGS							\
+	"console=ttyUS0 root=/dev/mtdblock1 fbmem=600k"
+
+#define CONFIG_COMMANDS			(CFG_CMD_BDI			\
+					 | CFG_CMD_LOADS		\
+					 | CFG_CMD_LOADB		\
+					 /* | CFG_CMD_IMI */		\
+					 /* | CFG_CMD_CACHE */		\
+					 | CFG_CMD_FLASH		\
+					 | CFG_CMD_MEMORY		\
+					 /* | CFG_CMD_NET */		\
+					 | CFG_CMD_ENV			\
+					 /* | CFG_CMD_IRQ */		\
+					 | CFG_CMD_BOOTD		\
+					 | CFG_CMD_CONSOLE		\
+					 /* | CFG_CMD_EEPROM */		\
+					 | CFG_CMD_ASKENV		\
+					 | CFG_CMD_RUN			\
+					 | CFG_CMD_ECHO			\
+					 /* | CFG_CMD_I2C */		\
+					 | CFG_CMD_REGINFO		\
+					 /* | CFG_CMD_DATE */		\
+					 /* | CFG_CMD_DHCP */		\
+					 /* | CFG_CMD_AUTOSCRIPT */	\
+					 /* | CFG_CMD_MII */		\
+					 | CFG_CMD_MISC			\
+					 /* | CFG_CMD_SDRAM */		\
+					 /* | CFG_CMD_DIAG */		\
+					 /* | CFG_CMD_HWFLOW */		\
+					 /* | CFG_CMD_SAVES */		\
+					 /* | CFG_CMD_SPI */		\
+					 /* | CFG_CMD_PING */		\
+					 /* | CFG_CMD_MMC */		\
+					 /* | CFG_CMD_FAT */		\
+					 /* | CFG_CMD_IMLS */		\
+					 /* | CFG_CMD_ITEST */		\
+					 /* | CFG_CMD_EXT2 */		\
+		)
+
+#include <cmd_confdefs.h>
+
+#define CONFIG_ATMEL_USART		1
+#define CONFIG_PIO2			1
+#define CFG_NR_PIOS			5
+#define CFG_HSDRAMC			1
+
+#define CFG_DCACHE_LINESZ		32
+#define CFG_ICACHE_LINESZ		32
+
+#define CONFIG_NR_DRAM_BANKS		1
+
+/* External flash on STK1000 */
+#if 0
+#define CFG_FLASH_CFI			1
+#define CFG_FLASH_CFI_DRIVER		1
+#endif
+
+#define CFG_FLASH_BASE			0x00000000
+#define CFG_FLASH_SIZE			0x800000
+#define CFG_MAX_FLASH_BANKS		1
+#define CFG_MAX_FLASH_SECT		135
+
+#define CFG_MONITOR_BASE		CFG_FLASH_BASE
+
+#define CFG_INTRAM_BASE			0x24000000
+#define CFG_INTRAM_SIZE			0x8000
+
+#define CFG_SDRAM_BASE			0x10000000
+
+#define CFG_ENV_IS_IN_FLASH		1
+#define CFG_ENV_SIZE			65536
+#define CFG_ENV_ADDR			(CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE)
+
+#define CFG_INIT_SP_ADDR		(CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
+
+#define CFG_MALLOC_LEN			(256*1024)
+#define CFG_MALLOC_END							\
+	({								\
+		DECLARE_GLOBAL_DATA_PTR;				\
+		CFG_SDRAM_BASE + gd->sdram_size;			\
+	})
+#define CFG_MALLOC_START		(CFG_MALLOC_END - CFG_MALLOC_LEN)
+
+#define CFG_DMA_ALLOC_LEN		(16384)
+#define CFG_DMA_ALLOC_END		(CFG_MALLOC_START)
+#define CFG_DMA_ALLOC_START		(CFG_DMA_ALLOC_END - CFG_DMA_ALLOC_LEN)
+/* Allow 2MB for the kernel run-time image */
+#define CFG_LOAD_ADDR			(CFG_SDRAM_BASE + 0x00200000)
+#define CFG_BOOTPARAMS_LEN		(16 * 1024)
+
+/* Other configuration settings that shouldn't have to change all that often */
+#define CFG_PROMPT			"Uboot> "
+#define CFG_CBSIZE			256
+#define CFG_MAXARGS			8
+#define CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_LONGHELP			1
+
+#define CFG_MEMTEST_START						\
+	({ DECLARE_GLOBAL_DATA_PTR; gd->bd->bi_dram[0].start; })
+#define CFG_MEMTEST_END							\
+	({								\
+		DECLARE_GLOBAL_DATA_PTR;				\
+		gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;	\
+	})
+#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h
index 2c1c31927c..4961011b5c 100644
--- a/include/configs/bamboo.h
+++ b/include/configs/bamboo.h
@@ -73,6 +73,7 @@
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in SDRAM)
  *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
 #define CFG_INIT_RAM_ADDR	0x70000000		/* DCache       */
 #define CFG_INIT_RAM_END	(4 << 10)
 #define CFG_GBL_DATA_SIZE	256		    	/* num bytes initial data	*/
@@ -310,11 +311,11 @@
 
 #define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
 				CFG_CMD_ASKENV	| \
-				CFG_CMD_EEPROM	| \
 				CFG_CMD_DATE	| \
 				CFG_CMD_DHCP	| \
 				CFG_CMD_DIAG	| \
 				CFG_CMD_ELF	| \
+				CFG_CMD_EEPROM	| \
 				CFG_CMD_I2C	| \
 				CFG_CMD_IRQ	| \
 				CFG_CMD_MII	| \
@@ -358,13 +359,11 @@
 
 #define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */
 
-#define CONFIG_CMDLINE_EDITING
-
-#ifdef CONFIG_CMDLINE_EDITING
-#undef CONFIG_AUTO_COMPLETE
-#else
-#define CONFIG_AUTO_COMPLETE
-#endif
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h
index 4a79835d6a..a66cdc3956 100644
--- a/include/configs/bubinga.h
+++ b/include/configs/bubinga.h
@@ -200,8 +200,9 @@
 
 #define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
diff --git a/include/configs/ebony.h b/include/configs/ebony.h
index a26af6952e..d8882ea31c 100644
--- a/include/configs/ebony.h
+++ b/include/configs/ebony.h
@@ -143,7 +143,13 @@
 #undef	CONFIG_SOFT_I2C			    /* I2C bit-banged		*/
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
 #define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES    {0x69}  /* Don't probe these addrs */
+
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
 
 #define CONFIG_PREBOOT	"echo;"	\
 	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
@@ -205,6 +211,7 @@
 				CFG_CMD_DHCP	| \
 				CFG_CMD_DIAG	| \
 				CFG_CMD_ELF	| \
+				CFG_CMD_EEPROM	| \
 				CFG_CMD_I2C	| \
 				CFG_CMD_IRQ	| \
 				CFG_CMD_MII	| \
@@ -243,8 +250,9 @@
 
 #define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
 
-#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h
new file mode 100644
index 0000000000..a77ccef63b
--- /dev/null
+++ b/include/configs/ep82xxm.h
@@ -0,0 +1,395 @@
+/*
+ * Copyright (C) 2006 Embedded Planet, LLC.
+ *
+ * U-Boot configuration for Embedded Planet EP82xxM boards.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MPC8260
+#define CPU_ID_STR		"MPC8270"
+
+#define CONFIG_EP82XXM	/* Embedded Planet EP82xxM H 1.0 board */
+			/* 256MB SDRAM / 64MB FLASH */
+
+#undef DEBUG
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f */
+
+/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Select serial console configuration
+ *
+ * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ */
+#define	CONFIG_CONS_ON_SMC		/* Console is on SMC         */
+#undef  CONFIG_CONS_ON_SCC		/* It's not on SCC           */
+#undef	CONFIG_CONS_NONE		/* It's not on external UART */
+#define CONFIG_CONS_INDEX	1	/* SMC1 is used for console  */
+
+#define CFG_BCSR		0xFA000000
+
+/*
+ * Select ethernet configuration
+ *
+ * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
+ * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
+ * SCC, 1-3 for FCC)
+ *
+ * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
+ * must be defined elsewhere (as for the console), or CFG_CMD_NET must
+ * be removed from CONFIG_COMMANDS to remove support for networking.
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* Ethernet is not on SCC */
+#define CONFIG_ETHER_ON_FCC		/* Ethernet is on FCC     */
+#undef	CONFIG_ETHER_NONE		/* No external Ethernet   */
+
+#define CONFIG_NET_MULTI
+
+#define CONFIG_ETHER_ON_FCC2
+#define CONFIG_ETHER_ON_FCC3
+
+#define CFG_CMXFCR_MASK3	(CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
+#define CFG_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK16)
+#define CFG_CMXFCR_MASK2	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+#define CFG_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+
+#define CFG_CPMFCR_RAMTYPE	0
+#define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+
+#define CONFIG_MII			/* MII PHY management        */
+#define CONFIG_BITBANGMII		/* Bit-banged MDIO interface */
+
+/*
+ * GPIO pins used for bit-banged MII communications
+ */
+#define MDIO_PORT		0	/* Not used - implemented in BCSR */
+#define MDIO_ACTIVE		(*(vu_char *)(CFG_BCSR + 8) &= 0xFB)
+#define MDIO_TRISTATE		(*(vu_char *)(CFG_BCSR + 8) |= 0x04)
+#define MDIO_READ		(*(vu_char *)(CFG_BCSR + 8) & 1)
+
+#define MDIO(bit)		if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x01; \
+				else	*(vu_char *)(CFG_BCSR + 8) &= 0xFE
+
+#define MDC(bit)		if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x02; \
+				else	*(vu_char *)(CFG_BCSR + 8) &= 0xFD
+
+#define MIIDELAY		udelay(1)
+
+
+#ifndef CONFIG_8260_CLKIN
+#define CONFIG_8260_CLKIN	66000000 /* in Hz */
+#endif
+
+#define CONFIG_BAUDRATE		115200
+
+#define CFG_VXWORKS_MAC_PTR 0x4300 /* Pass Ethernet MAC to VxWorks */
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL   \
+				| CFG_CMD_DHCP    \
+				| CFG_CMD_ECHO    \
+				| CFG_CMD_I2C     \
+				| CFG_CMD_IMMAP   \
+				| CFG_CMD_MII     \
+				| CFG_CMD_PING    \
+				| CFG_CMD_DATE    \
+				| CFG_CMD_DTT	  \
+				| CFG_CMD_EEPROM  \
+				| CFG_CMD_PCI	  \
+				| CFG_CMD_DIAG	  \
+				)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_ETHADDR		00:10:EC:00:88:65
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR		00:10:EC:80:88:65
+#define CONFIG_IPADDR		10.0.0.245
+#define CONFIG_HOSTNAME		EP82xxM
+#define CONFIG_SERVERIP		10.0.0.26
+#define CONFIG_GATEWAYIP	10.0.0.1
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+#define CFG_ENV_IN_OWN_SECT	1
+#define CONFIG_AUTO_COMPLETE	1
+#define	CONFIG_EXTRA_ENV_SETTINGS	"ethprime=FCC3 ETHERNET"
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
+#define CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
+#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
+#define CONFIG_KGDB_INDEX	1	/* which serial channel for kgdb */
+#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
+#endif
+
+#define CONFIG_BZIP2	/* include support for bzip2 compressed images */
+#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#define CFG_LONGHELP			/* undef to save memory	    */
+#define CFG_PROMPT		"ep82xxm=> "	/* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size  */
+#define CFG_MAXARGS		16		/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size  */
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+/*
+ * Define here the location of the environment variables (FLASH or EEPROM).
+ * Note: DENX encourages to use redundant environment in FLASH.
+ */
+#if 1
+#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+#else
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_BASE		0xFC000000
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks	*/
+#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector in flinfo */
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE	0x20000
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+/* EEPROM Configuration */
+#define CFG_EEPROM_SIZE	0x1000
+#define CFG_I2C_EEPROM_ADDR	0x54
+#define CFG_I2C_EEPROM_ADDR_LEN	1
+#define CFG_EEPROM_PAGE_WRITE_BITS	3
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+#ifdef CFG_ENV_IS_IN_EEPROM
+#define CFG_ENV_SIZE		0x200	    /* Size of Environment vars */
+#define CFG_ENV_OFFSET		0x0
+#endif /* CFG_ENV_IS_IN_EEPROM */
+
+/* RTC Configuration */
+#define CONFIG_RTC_M41T11	1 	/* uses a M41T81 */
+#define CFG_I2C_RTC_ADDR	0x68
+#define CONFIG_M41T11_BASE_YEAR	1900
+
+/* I2C SYSMON (LM75) */
+#define CONFIG_DTT_LM75		1
+#define CONFIG_DTT_SENSORS	{0}
+#define CFG_DTT_MAX_TEMP	70
+#define CFG_DTT_LOW_TEMP	-30
+#define	CFG_DTT_HYSTERESIS	3
+
+/*-----------------------------------------------------------------------
+ * NVRAM Configuration
+ *-----------------------------------------------------------------------
+ */
+#define CFG_NVRAM_BASE_ADDR	0xFA080000
+#define CFG_NVRAM_SIZE		(128*1024)-16
+
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play   */
+#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
+#define CONFIG_PCI_BOOTDELAY	0
+
+/* PCI Memory map (if different from default map */
+#define CFG_PCI_SLV_MEM_LOCAL	CFG_SDRAM_BASE		/* Local base */
+#define CFG_PCI_SLV_MEM_BUS		0x00000000	/* PCI base */
+#define CFG_PICMR0_MASK_ATTRIB	(PICMR_MASK_512MB | PICMR_ENABLE | \
+				 PICMR_PREFETCH_EN)
+
+/*
+ * These are the windows that allow the CPU to access PCI address space.
+ * All three PCI master windows, which allow the CPU to access PCI
+ * prefetch, non prefetch, and IO space (see below), must all fit within
+ * these windows.
+ */
+
+/*
+ * Master window that allows the CPU to access PCI Memory (prefetch).
+ * This window will be setup with the second set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CFG_PCI_MSTR_MEM_LOCAL	0x80000000          /* Local base */
+#define CFG_PCI_MSTR_MEM_BUS	0x80000000          /* PCI base   */
+#define	CFG_CPU_PCI_MEM_START	PCI_MSTR_MEM_LOCAL
+#define CFG_PCI_MSTR_MEM_SIZE	0x20000000          /* 512MB */
+#define CFG_POCMR0_MASK_ATTRIB	(POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
+
+/*
+ * Master window that allows the CPU to access PCI Memory (non-prefetch).
+ * This window will be setup with the second set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CFG_PCI_MSTR_MEMIO_LOCAL    0xA0000000          /* Local base */
+#define CFG_PCI_MSTR_MEMIO_BUS      0xA0000000          /* PCI base   */
+#define CFG_CPU_PCI_MEMIO_START     PCI_MSTR_MEMIO_LOCAL
+#define CFG_PCI_MSTR_MEMIO_SIZE     0x20000000          /* 512MB */
+#define CFG_POCMR1_MASK_ATTRIB      (POCMR_MASK_512MB | POCMR_ENABLE)
+
+/*
+ * Master window that allows the CPU to access PCI IO space.
+ * This window will be setup with the first set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CFG_PCI_MSTR_IO_LOCAL       0xF6000000          /* Local base */
+#define CFG_PCI_MSTR_IO_BUS         0x00000000          /* PCI base   */
+#define CFG_CPU_PCI_IO_START        PCI_MSTR_IO_LOCAL
+#define CFG_PCI_MSTR_IO_SIZE        0x02000000          /* 64MB */
+#define CFG_POCMR2_MASK_ATTRIB      (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
+
+
+/* PCIBR0 - for PCI IO*/
+#define CFG_PCI_MSTR0_LOCAL		CFG_PCI_MSTR_IO_LOCAL		/* Local base */
+#define CFG_PCIMSK0_MASK		~(CFG_PCI_MSTR_IO_SIZE - 1U)	/* Size of window */
+/* PCIBR1 - prefetch and non-prefetch regions joined together */
+#define CFG_PCI_MSTR1_LOCAL		CFG_PCI_MSTR_MEM_LOCAL
+#define CFG_PCIMSK1_MASK		~(CFG_PCI_MSTR_MEM_SIZE + CFG_PCI_MSTR_MEMIO_SIZE - 1U)
+
+
+#define	CFG_DIRECT_FLASH_TFTP
+
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+#define CFG_JFFS2_FIRST_BANK	0
+#define CFG_JFFS2_NUM_BANKS	CFG_MAX_FLASH_BANKS
+#define CFG_JFFS2_FIRST_SECTOR  0
+#define CFG_JFFS2_LAST_SECTOR   62
+#define CFG_JFFS2_SORT_FRAGMENTS
+#define CFG_JFFS_CUSTOM_PART
+#endif /* CFG_CMD_JFFS2 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_I2C)
+#define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
+#define CFG_I2C_SPEED		100000	/* I2C speed			*/
+#define CFG_I2C_SLAVE		0x7F	/* I2C slave address		*/
+#endif /* CFG_CMD_I2C */
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#endif
+
+#define CFG_MONITOR_LEN		(512 << 10)	/* Reserve 256KB for Monitor */
+
+#define CFG_DEFAULT_IMMR	0x00010000
+#define CFG_IMMR		0xF0000000
+
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+
+/* Hard reset configuration word */
+#define CFG_HRCW_MASTER		0 /*0x1C800641*/  /* Not used - provided by CPLD */
+/* No slaves */
+#define CFG_HRCW_SLAVE1 	0
+#define CFG_HRCW_SLAVE2 	0
+#define CFG_HRCW_SLAVE3 	0
+#define CFG_HRCW_SLAVE4 	0
+#define CFG_HRCW_SLAVE5 	0
+#define CFG_HRCW_SLAVE6 	0
+#define CFG_HRCW_SLAVE7 	0
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM		0x02	/* Software reboot                  */
+
+#define CFG_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+#define CFG_HID0_INIT		0
+#define CFG_HID0_FINAL		0
+
+#define CFG_HID2		0
+
+#define CFG_SIUMCR		0x02610000
+#define CFG_SYPCR		0xFFFF0689
+#define CFG_BCR			0x8080E000
+#define CFG_SCCR		0x00000001
+
+#define CFG_RMR			0
+#define CFG_TMCNTSC		0x000000C3
+#define CFG_PISCR		0x00000083
+#define CFG_RCCR		0
+
+#define CFG_MPTPR		0x0A00
+#define CFG_PSDMR		0xC432246E
+#define CFG_PSRT		0x32
+
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_SDRAM_BR		(CFG_SDRAM_BASE | 0x00000041)
+#define CFG_SDRAM_OR		0xF0002900
+
+#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | 0x00001801)
+#define CFG_OR0_PRELIM		0xFC000882
+#define CFG_BR4_PRELIM		(CFG_BCSR | 0x00001001)
+#define CFG_OR4_PRELIM		0xFFF00050
+
+#define CFG_RESET_ADDRESS	0xFFF00100
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/luan.h b/include/configs/luan.h
index 0335a00985..0350e91f0f 100644
--- a/include/configs/luan.h
+++ b/include/configs/luan.h
@@ -145,6 +145,13 @@
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
 #define CFG_I2C_SLAVE		0x7F
 
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
 #define CONFIG_PREBOOT	"echo;"	\
 	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
 	"echo"
@@ -215,6 +222,7 @@
 				CFG_CMD_DHCP		|	\
 				CFG_CMD_DIAG		|	\
 				CFG_CMD_ELF		|	\
+				CFG_CMD_EEPROM		|	\
 				CFG_CMD_I2C		|	\
 				CFG_CMD_IRQ		|	\
 				CFG_CMD_MII		|	\
@@ -253,6 +261,12 @@
 
 #define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */
 
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h
index ce33b85c96..0c935bfcea 100644
--- a/include/configs/mcc200.h
+++ b/include/configs/mcc200.h
@@ -37,12 +37,12 @@
 
 #define CONFIG_MISC_INIT_R
 
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH 	*/
-#define BOOTFLAG_WARM		0x02	/* Software reboot	     		*/
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs 			*/
+#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value 	*/
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
 #endif
 
 /*
@@ -51,16 +51,36 @@
  *  To select console on the one of 8 external UARTs,
  * define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART,
  * or as 5, 6, 7, or 8 for the second Quad UART.
+ * COM11, COM12, COM13, COM14 are located on the second Quad UART.
  *
  *  CONFIG_PSC_CONSOLE must be undefined in this case.
  */
-/* #define CONFIG_QUART_CONSOLE	1	*/ /* console is on UART1 of QUART1	*/
+#if !defined(CONFIG_PRS200)
+/* MCC200 configuration: */
+#ifdef CONFIG_CONSOLE_COM12
+#define CONFIG_QUART_CONSOLE	6	/* console is on UARTF of QUART2	*/
+#else
+#define CONFIG_QUART_CONSOLE	8	/* console is on UARTH of QUART2	*/
+#endif
+#else
+/* PRS200 configuration: */
+#undef CONFIG_QUART_CONSOLE
+#endif /* CONFIG_PRS200 */
 /*
  *  To select console on PSC1, define CONFIG_PSC_CONSOLE as 1
  * and undefine CONFIG_QUART_CONSOLE.
  */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1			*/
-#if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE)
+#if !defined(CONFIG_PRS200)
+/* MCC200 configuration: */
+#define CONFIG_SERIAL_MULTI	1
+#define CONFIG_PSC_CONSOLE	1	/* PSC1 may be COM */
+#define CONFIG_PSC_CONSOLE2	2	/* PSC2 is PSoC */
+#else
+/* PRS200 configuration: */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1		*/
+#endif
+#if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE) && \
+	!defined(CONFIG_SERIAL_MULTI)
 #error "Select only one console device!"
 #endif
 #define CONFIG_BAUDRATE		115200
@@ -72,7 +92,7 @@
 
 /* USB */
 #define CONFIG_USB_OHCI
-#define ADD_USB_CMD             CFG_CMD_USB | CFG_CMD_FAT
+#define ADD_USB_CMD		CFG_CMD_USB | CFG_CMD_FAT
 #define CONFIG_USB_STORAGE
 
 /*
@@ -98,33 +118,46 @@
 
 #undef	CONFIG_BOOTARGS
 
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
+#define XMK_STR(x)		#x
+#define MK_STR(x)		XMK_STR(x)
+
+#ifdef CONFIG_PRS200
+# define CFG__BOARDNAME		"prs200"
+# define CFG__LINUX_CONSOLE	"ttyS0"
+#else
+# define CFG__BOARDNAME		"mcc200"
+# define CFG__LINUX_CONSOLE	"ttyEU7"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\
-	"hostname=mcc200\0"						\
+	"hostname=" CFG__BOARDNAME "\0"					\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=${serverip}:${rootpath}\0"			\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
 	"addip=setenv bootargs ${bootargs} "				\
 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
 		":${hostname}:${netdev}:off panic=1\0"			\
-	"flash_nfs=run nfsargs addip;"					\
+	"addcons=setenv bootargs ${bootargs} "				\
+		"console=${console},${baudrate}\0"			\
+	"flash_nfs=run nfsargs addip addcons;"				\
 		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip;"					\
+	"flash_self=run ramargs addip addcons;"				\
 		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"net_nfs=tftp 200000 ${bootfile};"				\
+		"run nfsargs addip addcons;bootm\0"			\
+	"console=" CFG__LINUX_CONSOLE "\0"				\
 	"rootpath=/opt/eldk/ppc_6xx\0"					\
-	"bootfile=/tftpboot/mcc200/uImage\0"				\
-	"baudrate=115200\0"						\
-	"load=tftp 200000 /tftpboot/mcc200/u-boot.bin\0"		\
-	"update=protect off FFF00000 +${filesize};"			\
-		"era FFF00000 +${filesize};"				\
-		"cp.b 200000 FFF00000 ${filesize}\0"		        \
-	"serverip=192.168.1.1\0"					\
-	"ipaddr=192.168.133.144\0"					\
-	"netmask=255.255.0.0\0"						\
+	"bootfile=/tftpboot/" CFG__BOARDNAME "/uImage\0"		\
+	"load=tftp 200000 /tftpboot/" CFG__BOARDNAME "/u-boot.bin\0"	\
+	"text_base=" MK_STR(TEXT_BASE) "\0"				\
+	"update=protect off ${text_base} +${filesize};"			\
+		"era ${text_base} +${filesize};"			\
+		"cp.b 200000 ${text_base} ${filesize}\0"		\
 	"unlock=yes\0"							\
-	"ethaddr=00:02:44:7D:73:3B\0"					\
 	""
+#undef MK_STR
+#undef XMK_STR
 
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
@@ -134,7 +167,7 @@
 /*
  * IPB Bus clocking configuration.
  */
-#define CFG_IPBSPEED_133   		/* define for 133MHz speed */
+#define CFG_IPBSPEED_133		/* define for 133MHz speed */
 
 /*
  * I2C configuration
@@ -150,9 +183,9 @@
  * TEXT base always at 0xFFF00000
  * ENV_ADDR always at  0xFFF40000
  * FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!)
- *               0xFE000000 for 32 MB
- *               0xFF000000 for 16 MB
- *               0xFF800000 for  8 MB
+ *		 0xFE000000 for 32 MB
+ *		 0xFF000000 for 16 MB
+ *		 0xFF800000 for  8 MB
  */
 #define CFG_FLASH_BASE		0xfc000000
 #define CFG_FLASH_SIZE		0x04000000
@@ -174,9 +207,9 @@
 #define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 #define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
 
-#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+#define CFG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars	*/
 
-#define CFG_ENV_SECT_SIZE	0x40000 	/* size of one complete sector	*/
+#define CFG_ENV_SECT_SIZE	0x40000	/* size of one complete sector	*/
 #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 #define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
 
@@ -206,7 +239,7 @@
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_BASE    TEXT_BASE
+#define CFG_MONITOR_BASE	TEXT_BASE
 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 #   define CFG_RAMBOOT		1
 #endif
@@ -226,27 +259,45 @@
 #define CONFIG_PHY_ADDR		1
 
 /*
+ * LCD Splash Screen
+ */
+#if !defined(CONFIG_PRS200)
+#define CONFIG_LCD		1
+#endif
+
+#if defined(CONFIG_LCD)
+#define CONFIG_SPLASH_SCREEN	1
+#define CFG_CONSOLE_IS_IN_ENV	1
+#define LCD_BPP			LCD_MONOCHROME
+#endif
+
+/*
  * GPIO configuration
  */
 /* 0x10000004 = 32MB SDRAM */
 /* 0x90000004 = 64MB SDRAM */
+#if defined(CONFIG_LCD)
+/* set PSC2 in UART mode */
+#define CFG_GPS_PORT_CONFIG	0x00000044
+#else
 #define CFG_GPS_PORT_CONFIG	0x00000004
+#endif
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size	*/
 #define CFG_MAXARGS		16		/* max number of command args	*/
 #define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
 
 #define CFG_LOAD_ADDR		0x100000	/* default load address */
@@ -309,7 +360,7 @@
  * One of four SC16C554 UARTs is selected with
  * A3-A4 (DA5-DA6) lines.
  */
-#if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5)
+#if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) && !defined(CONFIG_PRS200)
 #define CFG_NS16550_COM1	(CFG_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5)
 #elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9)
 #define CFG_NS16550_COM1	(CFG_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5)
diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h
index a13d6a870a..89e9164e03 100644
--- a/include/configs/ocotea.h
+++ b/include/configs/ocotea.h
@@ -158,7 +158,13 @@
 #undef	CONFIG_SOFT_I2C			    /* I2C bit-banged		*/
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
 #define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES    {0x69}  /* Don't probe these addrs */
+
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
 
 #define CONFIG_PREBOOT	"echo;"	\
 	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
@@ -219,6 +225,9 @@
 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
 #define CONFIG_PHY_RESET        1       /* reset phy upon startup         */
 #define CONFIG_PHY_RESET_DELAY	1000
+#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
 
 #define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
 				CFG_CMD_ASKENV	| \
@@ -226,6 +235,7 @@
 				CFG_CMD_DHCP	| \
 				CFG_CMD_DIAG	| \
 				CFG_CMD_ELF	| \
+				CFG_CMD_EEPROM	| \
 				CFG_CMD_I2C	| \
 				CFG_CMD_IRQ	| \
 				CFG_CMD_MII	| \
@@ -264,15 +274,12 @@
 
 #define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
-#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
-
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h
index 50c1c4fd4c..23bdfc8dfb 100644
--- a/include/configs/pcs440ep.h
+++ b/include/configs/pcs440ep.h
@@ -63,6 +63,7 @@
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in SDRAM)
  *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
 #define CFG_INIT_RAM_ADDR	0x70000000		/* DCache       */
 #define CFG_INIT_RAM_END	(8 << 10)
 #define CFG_GBL_DATA_SIZE	256			/* num bytes initial data*/
diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h
index 5a434dc767..6e4fdb2498 100644
--- a/include/configs/sbc8560.h
+++ b/include/configs/sbc8560.h
@@ -197,12 +197,16 @@
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
-/* I2C */
-#define	 CONFIG_HARD_I2C		/* I2C with hardware support*/
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
 #define CFG_I2C_SLAVE		0x7F
 #define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
+#define CFG_I2C_OFFSET		0x3000
 
 #define CFG_PCI_MEM_BASE	0xC0000000
 #define CFG_PCI_MEM_PHYS	0xC0000000
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
new file mode 100644
index 0000000000..1a460cde06
--- /dev/null
+++ b/include/configs/sequoia.h
@@ -0,0 +1,430 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2006
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * sequoia.h - configuration for Sequoia board (PowerPC440EPx)
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+/* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */
+#ifndef CONFIG_RAINIER
+#define CONFIG_SEQUOIA		1		/* Board is Sequoia	*/
+#define CONFIG_440EPX		1		/* Specific PPC440EPx	*/
+#else
+#define CONFIG_440GRX		1		/* Specific PPC440GRx	*/
+#endif
+#define CONFIG_4xx		1		/* ... PPC4xx family	*/
+#define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R	1		/* Call misc_init_r	*/
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN		(384 * 1024)	/* Reserve 384 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+
+#define CFG_BOOT_BASE_ADDR	0xf0000000
+#define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
+#define CFG_FLASH_BASE		0xfc000000	/* start of FLASH	*/
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_NAND_ADDR		0xd0000000      /* NAND Flash		*/
+#define CFG_OCM_BASE		0xe0010000      /* ocm			*/
+#define CFG_PCI_BASE		0xe0000000      /* Internal PCI regs	*/
+#define CFG_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
+#define CFG_PCI_MEMBASE1	CFG_PCI_MEMBASE  + 0x10000000
+#define CFG_PCI_MEMBASE2	CFG_PCI_MEMBASE1 + 0x10000000
+#define CFG_PCI_MEMBASE3	CFG_PCI_MEMBASE2 + 0x10000000
+
+/* Don't change either of these */
+#define CFG_PERIPHERAL_BASE	0xef600000	/* internal peripherals	*/
+
+#define CFG_USB2D0_BASE		0xe0000100
+#define CFG_USB_DEVICE		0xe0000000
+#define CFG_USB_HOST		0xe0000400
+#define CFG_BCSR_BASE		0xc0000000
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer
+ *----------------------------------------------------------------------*/
+/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache	*/
+#define CFG_INIT_RAM_OCM	1		/* OCM as init ram	*/
+#define CFG_INIT_RAM_ADDR	CFG_OCM_BASE	/* OCM			*/
+
+#define CFG_INIT_RAM_END	(4 << 10)
+#define CFG_GBL_DATA_SIZE	256		/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CFG_EXT_SERIAL_CLOCK	11059200	/* ext. 11.059MHz clk	*/
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SERIAL_MULTI     1
+/* define this if you want console on UART1 */
+#undef CONFIG_UART1_CONSOLE
+
+#define CFG_BAUDRATE_TABLE						\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+#else
+#define CFG_ENV_IS_IN_NAND	1	/* use NAND for environment vars	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
+#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
+
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CFG_FLASH_PROTECTION	1	/* use hardware flash protection	*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE	0x20000 	/* size of one complete sector	*/
+#define CFG_ENV_ADDR		((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
+#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+#endif
+
+/*
+ * IPL (Initial Program Loader, integrated inside CPU)
+ * Will load first 4k from NAND (SPL) into cache and execute it from there.
+ *
+ * SPL (Secondary Program Loader)
+ * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
+ * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
+ * controller and the NAND controller so that the special U-Boot image can be
+ * loaded from NAND to SDRAM.
+ *
+ * NUB (NAND U-Boot)
+ * This NAND U-Boot (NUB) is a special U-Boot version which can be started
+ * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
+ *
+ * On 440EPx the SPL is copied to SDRAM before the NAND controller is
+ * set up. While still running from cache, I experienced problems accessing
+ * the NAND controller.	sr - 2006-08-25
+ */
+#define CFG_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location			*/
+#define CFG_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size			*/
+#define CFG_NAND_BOOT_SPL_DST	(CFG_OCM_BASE + (12 << 10)) /* Copy SPL here	*/
+#define CFG_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr	*/
+#define CFG_NAND_U_BOOT_START	CFG_NAND_U_BOOT_DST /* Start NUB from this addr	*/
+#define CFG_NAND_BOOT_SPL_DELTA	(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
+
+/*
+ * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
+ */
+#define CFG_NAND_U_BOOT_OFFS	(16 << 10)	/* Offset to RAM U-Boot image	*/
+#define CFG_NAND_U_BOOT_SIZE	(384 << 10)	/* Size of RAM U-Boot image	*/
+
+/*
+ * Now the NAND chip has to be defined (no autodetection used!)
+ */
+#define CFG_NAND_PAGE_SIZE	(512)		/* NAND chip page size		*/
+#define CFG_NAND_BLOCK_SIZE	(16 << 10)	/* NAND chip block size		*/
+#define CFG_NAND_PAGE_COUNT	(32)		/* NAND chip page count		*/
+#define CFG_NAND_BAD_BLOCK_POS	(5)		/* Location of bad block marker	*/
+#undef CFG_NAND_4_ADDR_CYCLE			/* No fourth addr used (<=32MB)	*/
+
+#ifdef CFG_ENV_IS_IN_NAND
+/*
+ * For NAND booting the environment is embedded in the U-Boot image. Please take
+ * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
+ */
+#define CFG_ENV_SIZE		CFG_NAND_BLOCK_SIZE
+#define CFG_ENV_OFFSET		(CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
+#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET + CFG_ENV_SIZE)
+#endif
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CFG_MBYTES_SDRAM        (256)    /* 256MB			*/
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C		1		/* I2C with hardware support	*/
+#undef	CONFIG_SOFT_I2C				/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
+#define CONFIG_DTT_LM75		1		/* ON Semi's LM75	*/
+#define CONFIG_DTT_AD7414	1		/* use AD7414		*/
+#define CONFIG_DTT_SENSORS	{0}		/* Sensor addresses	*/
+#define CFG_DTT_MAX_TEMP	70
+#define CFG_DTT_LOW_TEMP	-30
+#define CFG_DTT_HYSTERESIS	3
+
+#define CONFIG_PREBOOT	"echo;"						\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=sequoia\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
+	        "bootm\0"						\
+	"rootpath=/opt/eldk/ppc_4xxFP\0"					\
+	"bootfile=/tftpboot/sequoia/uImage\0"				\
+	"kernel_addr=FC000000\0"					\
+	"ramdisk_addr=FC180000\0"					\
+	"load=tftp 100000 /tftpboot/sequoia/u-boot.bin\0"		\
+	"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;"	\
+		"cp.b 100000 FFFA0000 60000\0"			        \
+	"upd=run load;run update\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_M88E1111_PHY	1
+#define	CONFIG_IBM_EMAC4_V4	1
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address, See schematics	*/
+
+#define CONFIG_PHY_RESET        1	/* reset phy upon startup         */
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+
+#define CONFIG_HAS_ETH0
+#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NET_MULTI	1
+#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
+#define CONFIG_PHY1_ADDR	1
+
+/* USB */
+#ifdef CONFIG_440EPX
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+/* Comment this out to enable USB 1.1 device */
+#define USB_2_0_DEVICE
+
+#define CMD_USB			CFG_CMD_USB
+#else
+#define CMD_USB			0	/* no USB on 440GRx		*/
+#endif /* CONFIG_440EPX */
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#define CONFIG_COMMANDS       (CONFIG_CMD_DFL	|	\
+			       CFG_CMD_ASKENV	|	\
+			       CFG_CMD_DHCP	|	\
+			       CFG_CMD_DTT	|	\
+			       CFG_CMD_DIAG	|	\
+			       CFG_CMD_EEPROM	|	\
+			       CFG_CMD_ELF	|	\
+			       CFG_CMD_FAT	|	\
+			       CFG_CMD_I2C	|	\
+			       CFG_CMD_IRQ	|	\
+			       CFG_CMD_MII	|	\
+			       CFG_CMD_NAND	|	\
+			       CFG_CMD_NET	|	\
+			       CFG_CMD_NFS	|	\
+			       CFG_CMD_PCI	|	\
+			       CFG_CMD_PING	|	\
+			       CFG_CMD_REGINFO	|	\
+			       CFG_CMD_SDRAM	|	\
+			       CMD_USB)
+
+#define CONFIG_SUPPORT_VFAT
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	        16	/* max number of command args	*/
+#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000 /* memtest works on		*/
+#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000  /* default load address	*/
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *----------------------------------------------------------------------*/
+/* General PCI */
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup  */
+#define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT		/* enable board pci_pre_init()	*/
+#define CFG_PCI_TARGET_INIT
+#define CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC				*/
+#define CFG_PCI_SUBSYS_ID       0xcafe	/* Whatever			*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH		CFG_FLASH_BASE
+#define CFG_NAND		0xD0000000
+#define CFG_CPLD		0xC0000000
+
+/*
+ * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
+ */
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#define CFG_NAND_CS		3		/* NAND chip connected to CSx	*/
+/* Memory Bank 0 (NOR-FLASH) initialization					*/
+#define CFG_EBC_PB0AP		0x03017300
+#define CFG_EBC_PB0CR		(CFG_FLASH | 0xda000)
+
+/* Memory Bank 3 (NAND-FLASH) initialization					*/
+#define CFG_EBC_PB3AP		0x018003c0
+#define CFG_EBC_PB3CR		(CFG_NAND | 0x1c000)
+#else
+#define CFG_NAND_CS		0		/* NAND chip connected to CSx	*/
+/* Memory Bank 3 (NOR-FLASH) initialization					*/
+#define CFG_EBC_PB3AP		0x03017300
+#define CFG_EBC_PB3CR		(CFG_FLASH | 0xda000)
+
+/* Memory Bank 0 (NAND-FLASH) initialization					*/
+#define CFG_EBC_PB0AP		0x018003c0
+#define CFG_EBC_PB0CR		(CFG_NAND | 0x1c000)
+#endif
+
+/* Memory Bank 2 (CPLD) initialization						*/
+#define CFG_EBC_PB2AP		0x24814580
+#define CFG_EBC_PB2CR		(CFG_CPLD | 0x38000)
+
+/*-----------------------------------------------------------------------
+ * NAND FLASH
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_NAND_DEVICE	1
+#define NAND_MAX_CHIPS		1
+#define CFG_NAND_BASE		(CFG_NAND_ADDR + CFG_NAND_CS)
+#define CFG_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ *----------------------------------------------------------------------*/
+#define CFG_DCACHE_SIZE		(32<<10)  /* For AMCC 440 CPUs			*/
+#define CFG_CACHELINE_SIZE	32	      /* ...			            */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	      /* log base 2 of the above value	*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	    /* which serial port to use */
+#endif
+#endif	/* __CONFIG_H */
diff --git a/include/configs/sorcery.h b/include/configs/sorcery.h
index 3d907f888c..4937638820 100644
--- a/include/configs/sorcery.h
+++ b/include/configs/sorcery.h
@@ -261,6 +261,7 @@
 #define CONFIG_MPC8220_FEC	1
 #define CONFIG_FEC_10MBIT	1 /* Workaround for FEC 100Mbit problem */
 #define CONFIG_PHY_ADDR		0x1F
+#define CONFIG_MII		1
 
 /*
  * Miscellaneous configurable options
diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h
index e218597db0..625cf20144 100644
--- a/include/configs/stxgp3.h
+++ b/include/configs/stxgp3.h
@@ -172,8 +172,11 @@
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
-/* I2C */
-#define  CONFIG_HARD_I2C    		/* I2C with hardware support*/
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
 #define CFG_I2C_SLAVE		0x7F
@@ -183,6 +186,7 @@
 /* I did the 'if 0' so we could keep the syntax above if ever needed. */
 #undef CFG_I2C_NOPROBES
 #endif
+#define CFG_I2C_OFFSET		0x3000
 
 /* RapdIO Map configuration, mapped 1:1.
 */
diff --git a/include/configs/v38b.h b/include/configs/v38b.h
new file mode 100644
index 0000000000..554a7a41b8
--- /dev/null
+++ b/include/configs/v38b.h
@@ -0,0 +1,343 @@
+/*
+ * (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering,
+ * wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc., 59
+ * Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MPC5xxx			1	/* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200			1	/* This is an MPC5200 CPU */
+#define CONFIG_V38B			1	/* ...on V38B board */
+#define CFG_MPC5XXX_CLKIN	33000000	/* ...running at 33.000000MHz */
+
+#define CONFIG_RTC_PCF8563		1	/* has PCF8563 RTC */
+#define CONFIG_MPC5200_DDR		1	/* has DDR SDRAM */
+
+#undef CONFIG_HW_WATCHDOG			/* don't use watchdog */
+
+#define CONFIG_NETCONSOLE		1
+
+#define CONFIG_BOARD_EARLY_INIT_R	1	/* do board-specific init */
+
+#define CFG_XLB_PIPELINING		1	/* gives better performance */
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM		0x02	/* Software reboot */
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * DDR
+ */
+#define SDRAM_DDR		1	/* is DDR */
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE		0x018D0000
+#define SDRAM_EMODE		0x40090000
+#define SDRAM_CONTROL		0x704f0f00
+#define SDRAM_CONFIG1		0x73722930
+#define SDRAM_CONFIG2		0x47770000
+#define SDRAM_TAPDELAY		0x10000000
+
+/*
+ * PCI - no suport
+ */
+#undef CONFIG_PCI
+
+/*
+ * Partitions
+ */
+#define CONFIG_MAC_PARTITION	1
+#define CONFIG_DOS_PARTITION	1
+
+/*
+ * USB
+ */
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_CLOCK	0x0001BBBB
+#define CONFIG_USB_CONFIG	0x00001000
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL	| \
+				 CFG_CMD_FAT	| \
+				 CFG_CMD_I2C	| \
+				 CFG_CMD_IDE	| \
+				 CFG_CMD_PING	| \
+				 CFG_CMD_DHCP	| \
+				 CFG_CMD_DIAG	| \
+				 CFG_CMD_IRQ	| \
+				 CFG_CMD_JFFS2	| \
+				 CFG_CMD_MII	| \
+				 CFG_CMD_SDRAMi	| \
+				 CFG_CMD_DATE	| \
+				 CFG_CMD_USB	| \
+				 CFG_CMD_FAT)
+
+#define CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Boot low with 16 MB Flash
+ */
+#define CFG_LOWBOOT		1
+#define CFG_LOWBOOT16		1
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"bootcmd=run net_nfs\0"						\
+	"bootdelay=3\0"							\
+	"baudrate=115200\0"						\
+	"preboot=echo;echo Type \"run flash_nfs\" to mount root "	\
+		"filesystem over NFS; echo\0"				\
+	"netdev=eth0\0"							\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs $(bootargs) "				\
+		"ip=$(ipaddr):$(serverip):$(gatewayip):"		\
+		"$(netmask):$(hostname):$(netdev):off panic=1\0"	\
+	"flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0"		\
+	"flash_self=run ramargs addip;bootm $(kernel_addr) "		\
+		"$(ramdisk_addr)\0"					\
+	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=$(serverip):$(rootpath)\0"			\
+	"hostname=v38b\0"						\
+	"ethact=FEC ETHERNET\0"						\
+	"rootpath=/opt/eldk-3.1.1/ppc_6xx\0"				\
+	"update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; "	\
+		"cp.b 200000 ff000000 $(filesize);"			\
+		"prot on ff000000 ff03ffff\0"				\
+	"load=tftp 200000 $(u-boot)\0"					\
+	"netmask=255.255.0.0\0"						\
+	"ipaddr=192.168.160.18\0"					\
+	"serverip=192.168.1.1\0"					\
+	"ethaddr=00:e0:ee:00:05:2e\0"					\
+	"bootfile=/tftpboot/v38b/uImage\0"				\
+	"u-boot=/tftpboot/v38b/u-boot.bin\0"				\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run net_nfs"
+
+#if defined(CONFIG_MPC5200)
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CFG_IPBSPEED_133			/* define for 133MHz speed */
+#endif
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+#define CFG_I2C_SPEED		100000	/* 100 kHz */
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CFG_I2C_EEPROM_ADDR_LEN		1
+#define CFG_EEPROM_PAGE_WRITE_BITS	3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70
+
+/*
+ * RTC configuration
+ */
+#define CFG_I2C_RTC_ADDR		0x51
+
+/*
+ * Flash configuration - use CFI driver
+ */
+#define CFG_FLASH_CFI		1		/* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER	1		/* Use the common driver */
+#define CFG_FLASH_CFI_AMD_RESET	1
+#define CFG_FLASH_BASE		0xFF000000
+#define CFG_MAX_FLASH_BANKS	1		/* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+#define CFG_FLASH_SIZE		0x01000000	/* 16 MiB */
+#define CFG_MAX_FLASH_SECT	256		/* max num of sects on one chip */
+#define CFG_FLASH_USE_BUFFER_WRITE	1	/* flash write speed-up */
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00040000)
+#define CFG_ENV_SIZE		0x10000
+#define CFG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_OVERWRITE	1
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR		0xF0000000
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_DEFAULT_MBAR	0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT		1
+#endif
+
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256kB for Monitor */
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128kB for malloc() */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Linux initial memory map */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_PHY_ADDR		0x00
+#define CONFIG_MII		1
+
+/*
+ * GPIO configuration
+ */
+#define CFG_GPS_PORT_CONFIG	0x90001404
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM */
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+/*
+ * Various low-level settings
+ */
+#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL		HID0_ICE
+
+#define CFG_BOOTCS_START	CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
+#define CFG_BOOTCS_CFG		0x00047801
+#define CFG_CS0_START		CFG_FLASH_BASE
+#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+
+#define CFG_CS_BURST		0x00000000
+#define CFG_CS_DEADCYCLE	0x33333333
+
+#define CFG_RESET_ADDRESS	0xff000000
+
+/*
+ * IDE/ATA (supports IDE harddisk)
+ */
+#undef CONFIG_IDE_8xx_PCCARD		/* Don't use IDE with PC Card Adapter */
+#undef CONFIG_IDE_8xx_DIRECT		/* Direct IDE not supported */
+#undef CONFIG_IDE_LED			/* LED for ide not supported */
+
+#define CONFIG_IDE_RESET		/* reset for ide supported */
+#define CONFIG_IDE_PREINIT
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus */
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus */
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+
+#define CFG_ATA_DATA_OFFSET	(0x0060)	/* data I/O offset */
+
+#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)	/* normal register accesses offset */
+
+#define CFG_ATA_ALT_OFFSET	(0x005C)	/* alternate registers offset */
+
+#define CFG_ATA_STRIDE		4		/* Interval between registers */
+
+/*
+ * Status LED
+ */
+#define  CONFIG_STATUS_LED		/* Status LED enabled */
+#define  CONFIG_BOARD_SPECIFIC_LED	/* version has board specific leds */
+
+#define CFG_LED_BASE	MPC5XXX_GPT7_ENABLE	/* Timer 7 GPIO */
+#ifndef __ASSEMBLY__
+typedef unsigned int led_id_t;
+
+#define __led_toggle(_msk) \
+	do { \
+		*((volatile long *) (CFG_LED_BASE)) ^= (_msk); \
+	} while(0)
+
+#define __led_set(_msk, _st) \
+	do { \
+		if ((_st)) \
+			*((volatile long *) (CFG_LED_BASE)) &= ~(_msk); \
+		else \
+			*((volatile long *) (CFG_LED_BASE)) |= (_msk); \
+	} while(0)
+
+#define __led_init(_msk, st) \
+	do { \
+		*((volatile long *) (CFG_LED_BASE)) |= 0x34; \
+	} while(0)
+#endif /* __ASSEMBLY__ */
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/walnut.h b/include/configs/walnut.h
index 1171ee5ae5..28abd6e153 100644
--- a/include/configs/walnut.h
+++ b/include/configs/walnut.h
@@ -90,6 +90,11 @@
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		1	/* PHY address			*/
 
+#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
+#define CONFIG_NET_MULTI		/* needed for NetConsole	*/
+
 #define CONFIG_RTC_DS174x	1	/* use DS1743 RTC in Walnut	*/
 
 #define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
@@ -97,6 +102,7 @@
 				CFG_CMD_DATE	| \
 				CFG_CMD_DHCP	| \
 				CFG_CMD_DIAG	| \
+				CFG_CMD_EEPROM	| \
 				CFG_CMD_ELF	| \
 				CFG_CMD_I2C	| \
 				CFG_CMD_IRQ	| \
@@ -156,16 +162,12 @@
 
 #define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
 
-#define CONFIG_AUTO_COMPLETE	1	/* add autocompletion support	*/
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_LOOPW		1	/* enable loopw command		*/
+#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
-#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
-
-#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
-#define CONFIG_NET_MULTI		/* needed for NetConsole	*/
-
 /*-----------------------------------------------------------------------
  * I2C stuff
  *-----------------------------------------------------------------------
@@ -175,6 +177,13 @@
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
 #define CFG_I2C_SLAVE		0x7F
 
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
diff --git a/include/configs/yellowstone.h b/include/configs/yellowstone.h
index 7d555665ec..ba27f37f6e 100644
--- a/include/configs/yellowstone.h
+++ b/include/configs/yellowstone.h
@@ -65,6 +65,7 @@
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in SDRAM)
  *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
 #define CFG_INIT_RAM_ADDR	0x70000000		/* DCache       */
 #define CFG_INIT_RAM_END	(8 << 10)
 #define CFG_GBL_DATA_SIZE	256			/* num bytes initial data*/
@@ -109,6 +110,8 @@
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+
 #define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #ifdef CFG_ENV_IS_IN_FLASH
@@ -229,6 +232,7 @@
 				CFG_CMD_DHCP	| \
 				CFG_CMD_DIAG	| \
 				CFG_CMD_ELF	| \
+				CFG_CMD_EEPROM	| \
 				CFG_CMD_I2C	| \
 				CFG_CMD_IRQ	| \
 				CFG_CMD_MII	| \
@@ -265,6 +269,12 @@
 
 #define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */
 
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h
index a81cf34f11..3d7b4a2f4b 100644
--- a/include/configs/yosemite.h
+++ b/include/configs/yosemite.h
@@ -65,6 +65,7 @@
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in SDRAM)
  *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
 #define CFG_INIT_RAM_ADDR	0x70000000		/* DCache       */
 #define CFG_INIT_RAM_END	(8 << 10)
 #define CFG_GBL_DATA_SIZE	256			/* num bytes initial data*/
@@ -231,6 +232,7 @@
 				CFG_CMD_DHCP	| \
 				CFG_CMD_DIAG	| \
 				CFG_CMD_ELF	| \
+				CFG_CMD_EEPROM	| \
 				CFG_CMD_I2C	| \
 				CFG_CMD_IRQ	| \
 				CFG_CMD_MII	| \
@@ -272,6 +274,12 @@
 
 #define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */
 
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
diff --git a/include/configs/yucca.h b/include/configs/yucca.h
index 0e58e7e102..a6532b5e85 100644
--- a/include/configs/yucca.h
+++ b/include/configs/yucca.h
@@ -31,9 +31,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define DEBUG
-#undef DEBUG
-
 /*-----------------------------------------------------------------------
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
@@ -63,17 +60,20 @@
 #define CFG_PERIPHERAL_BASE	0xa0000000	/* internal peripherals	*/
 #define CFG_ISRAM_BASE		0x90000000	/* internal SRAM	*/
 
-#define CFG_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
-#define CFG_PCI_MEMBASE1	0x90000000	/* mapped pci memory	*/
-#define CFG_PCI_MEMBASE2	0xa0000000	/* mapped pci memory	*/
-#define CFG_PCI_MEMBASE3	0xb0000000	/* mapped pci memory	*/
-
+#define CFG_PCI_MEMBASE		0x80000000	/* mapped PCI memory	*/
 #define CFG_PCI_BASE		0xd0000000	/* internal PCI regs	*/
-#define CFG_PCI_TARGBASE	0x80000000	/*PCIaddr mapped to CFG_PCI_MEMBASE*/
+#define CFG_PCI_TARGBASE	CFG_PCI_MEMBASE
+
+#define CFG_PCIE_MEMBASE	0xb0000000	/* mapped PCIe memory	*/
+#define CFG_PCIE_MEMSIZE	0x01000000
+#define CFG_PCIE_BASE		0xe0000000	/* PCIe UTL regs */
 
-/* #define CFG_PCI_BASE_IO	0xB8000000 */	/* internal PCI I-O	*/
-/* #define CFG_PCI_BASE_REGS	0xBEC00000 */	/* internal PCI regs	*/
-/* #define CFG_PCI_BASE_CYCLE	0xBED00000 */	/* internal PCI regs	*/
+#define CFG_PCIE0_CFGBASE	0xc0000000
+#define CFG_PCIE0_XCFGBASE	0xc0000400
+#define CFG_PCIE1_CFGBASE	0xc0001000
+#define CFG_PCIE1_XCFGBASE	0xc0001400
+#define CFG_PCIE2_CFGBASE	0xc0002000
+#define CFG_PCIE2_XCFGBASE	0xc0002400
 
 /* System RAM mapped to PCI space */
 #define CONFIG_PCI_SYS_MEM_BUS	CFG_SDRAM_BASE
@@ -220,6 +220,9 @@
 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
 #define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
 
+#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
+#define CONFIG_NET_MULTI		/* needed for NetConsole	*/
+
 #undef CONFIG_WATCHDOG			/* watchdog disabled		*/
 
 /*
@@ -245,6 +248,12 @@
 
 #define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
 
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
@@ -292,6 +301,7 @@
  */
 /* Support for Intel 82557/82559/82559ER chips. */
 #define CONFIG_EEPRO100
+
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
@@ -506,8 +516,8 @@
 #define FPGA_REG1C_PE1_WAKE		0x0040
 #define FPGA_REG1C_PE2_WAKE		0x0020
 #define FPGA_REG1C_PE0_PERST		0x0010
-#define FPGA_REG1C_PE1_PERST		0x0080
-#define FPGA_REG1C_PE2_PERST		0x0040
+#define FPGA_REG1C_PE1_PERST		0x0008
+#define FPGA_REG1C_PE2_PERST		0x0004
 
 /*----------------------------------------------------------------------------+
 | Defines
diff --git a/include/environment.h b/include/environment.h
index 422f800897..26b07120da 100644
--- a/include/environment.h
+++ b/include/environment.h
@@ -79,6 +79,10 @@
 # ifdef CFG_ENV_OFFSET_REDUND
 #  define CFG_REDUNDAND_ENVIRONMENT
 # endif
+# if defined(CONFIG_NAND_U_BOOT)
+/* Use embedded environment in NAND boot versions */
+#  define ENV_IS_EMBEDDED	1
+# endif
 #endif /* CFG_ENV_IS_IN_NAND */
 
 
diff --git a/include/exports.h b/include/exports.h
index 0eaf66e183..8f7f61703c 100644
--- a/include/exports.h
+++ b/include/exports.h
@@ -20,6 +20,9 @@ void udelay(unsigned long);
 unsigned long get_timer(unsigned long);
 void vprintf(const char *, va_list);
 void do_reset (void);
+unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base);
+char *getenv (char *name);
+void setenv (char *varname, char *varvalue);
 #if (CONFIG_COMMANDS & CFG_CMD_I2C)
 int i2c_write (uchar, uint, int , uchar* , int);
 int i2c_read (uchar, uint, int , uchar* , int);
@@ -37,7 +40,7 @@ enum {
 	XF_MAX
 };
 
-#define XF_VERSION	2
+#define XF_VERSION	3
 
 #if defined(CONFIG_I386)
 extern gd_t *global_data;
diff --git a/include/fat.h b/include/fat.h
index 0645458f17..92638d535e 100644
--- a/include/fat.h
+++ b/include/fat.h
@@ -175,15 +175,19 @@ typedef struct dir_slot {
 	__u8    name11_12[4];	/* Last 2 characters in name */
 } dir_slot;
 
-/* Private filesystem parameters */
+/* Private filesystem parameters
+ *
+ * Note: FAT buffer has to be 32 bit aligned
+ * (see FAT32 accesses)
+ */
 typedef struct {
+	__u8	fatbuf[FATBUFSIZE]; /* Current FAT buffer */
 	int	fatsize;	/* Size of FAT in bits */
 	__u16	fatlength;	/* Length of FAT in sectors */
 	__u16	fat_sect;	/* Starting sector of the FAT */
 	__u16	rootdir_sect;	/* Start sector of root directory */
 	__u16	clust_size;	/* Size of clusters in sectors */
 	short	data_begin;	/* The sector of the first cluster, can be negative */
-	__u8	fatbuf[FATBUFSIZE]; /* Current FAT buffer */
 	int	fatbufnum;	/* Used by get_fatent, init to -1 */
 } fsdata;
 
diff --git a/include/flash.h b/include/flash.h
index 84b48a9f2e..9c57cbc427 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -43,9 +43,14 @@ typedef struct {
 	ulong	write_tout;		/* maximum write timeout		*/
 	ulong	buffer_write_tout;	/* maximum buffer write timeout		*/
 	ushort	vendor;			/* the primary vendor id		*/
-	ushort	cmd_reset;		/* Vendor specific reset command	*/
+	ushort	cmd_reset;		/* vendor specific reset command	*/
 	ushort	interface;		/* used for x8/x16 adjustments		*/
 	ushort	legacy_unlock;		/* support Intel legacy (un)locking	*/
+	uchar	manufacturer_id;	/* manufacturer id			*/
+	ushort	device_id;		/* device id				*/
+	ushort	device_id2;		/* extended device id			*/
+	ushort	ext_addr;		/* extended query table address		*/
+	ushort	cfi_version;		/* cfi version				*/
 #endif
 } flash_info_t;
 
@@ -209,6 +214,9 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
 #define AMD_ID_GL064M_3 0x22012201	/* 3rd ID word for S29GL064M-R6 */
 #define AMD_ID_GL064MT_2 0x22102210	/* 2nd ID word for S29GL064M-R3 (top boot sector) */
 #define AMD_ID_GL064MT_3 0x22012201	/* 3rd ID word for S29GL064M-R3 (top boot sector) */
+#define AMD_ID_GL128N_2	0x22212221	/* 2nd ID word for S29GL128N */
+#define AMD_ID_GL128N_3	0x22012201	/* 3rd ID word for S29GL128N */
+
 
 #define AMD_ID_LV320B_2 0x221A221A	/* 2d ID word for AM29LV320MB at 0x38 */
 #define AMD_ID_LV320B_3 0x22002200	/* 3d ID word for AM29LV320MB at 0x3c */
@@ -417,6 +425,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
 #define FLASH_FUJLV650	0x00D0		/* Fujitsu MBM 29LV650UE/651UE		*/
 #define FLASH_MT28S4M16LC 0x00E1	/* Micron MT28S4M16LC			*/
 #define FLASH_S29GL064M 0x00F0		/* Spansion S29GL064M-R6		*/
+#define FLASH_S29GL128N 0x00F1		/* Spansion S29GL128N			*/
 
 #define FLASH_UNKNOWN	0xFFFF		/* unknown flash type			*/
 
@@ -435,6 +444,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
 #define FLASH_MAN_MT	0x00400000
 #define FLASH_MAN_SHARP 0x00500000
 #define FLASH_MAN_ATM	0x00600000
+#define FLASH_MAN_CFI	0x01000000
 
 
 #define FLASH_TYPEMASK	0x0000FFFF	/* extract FLASH type	information	*/
diff --git a/include/ft_build.h b/include/ft_build.h
index 47ca575d9f..89c689c084 100644
--- a/include/ft_build.h
+++ b/include/ft_build.h
@@ -36,19 +36,18 @@ struct boot_param_header {
 
 struct ft_cxt {
 	struct boot_param_header *bph;
-	int max_size;		/* maximum size of tree */
-	int overflow;		/* set when this happens */
-	u8 *p, *pstr, *pres;	/* running pointers */
-	u8 *p_begin, *pstr_begin, *pres_begin;	/* starting pointers */
-	u8 *p_anchor;		/* start of constructed area */
-	int struct_size, strings_size, res_size;
+	u8 *p_rsvmap;
+	u8 *p_start;  /* pointer to beginning of dt_struct */
+	u8 *p_end; /* pointer to end of dt_strings */
+	u8 *p; /* pointer to end of dt_struct and beginning of dt_strings */
 };
 
 void ft_begin_node(struct ft_cxt *cxt, const char *name);
+void ft_init_cxt(struct ft_cxt *cxt, void *blob);
 void ft_end_node(struct ft_cxt *cxt);
 
-void ft_begin_tree(struct ft_cxt *cxt);
-int ft_end_tree(struct ft_cxt *cxt);
+void ft_end_tree(struct ft_cxt *cxt);
+void ft_finalize_tree(struct ft_cxt *cxt);
 
 void ft_nop(struct ft_cxt *cxt);
 void ft_prop(struct ft_cxt *cxt, const char *name, const void *data, int sz);
@@ -57,12 +56,16 @@ void ft_prop_int(struct ft_cxt *cxt, const char *name, int val);
 void ft_begin(struct ft_cxt *cxt, void *blob, int max_size);
 void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size);
 
-void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_end);
+void ft_setup(void *blob, bd_t * bd, ulong initrd_start, ulong initrd_end);
 
 void ft_dump_blob(const void *bphp);
 void ft_merge_blob(struct ft_cxt *cxt, void *blob);
 void *ft_get_prop(void *bphp, const char *propname, int *szp);
 
+#ifdef CONFIG_OF_BOARD_SETUP
 void ft_board_setup(void *blob, bd_t *bd);
+void ft_cpu_setup(void *blob, bd_t *bd);
+void ft_pci_setup(void *blob, bd_t *bd);
+#endif
 
 #endif
diff --git a/include/image.h b/include/image.h
index 139df0b2d1..2f575fd2d7 100644
--- a/include/image.h
+++ b/include/image.h
@@ -76,6 +76,7 @@
 #define IH_CPU_MICROBLAZE	14	/* MicroBlaze   */
 #define IH_CPU_NIOS2		15	/* Nios-II	*/
 #define IH_CPU_BLACKFIN		16	/* Blackfin	*/
+#define IH_CPU_AVR32		17	/* AVR32	*/
 
 /*
  * Image Types
@@ -124,6 +125,7 @@
 #define IH_TYPE_FIRMWARE	5	/* Firmware Image		*/
 #define IH_TYPE_SCRIPT		6	/* Script file			*/
 #define IH_TYPE_FILESYSTEM	7	/* Filesystem Image (any type)	*/
+#define IH_TYPE_FLATDT		8	/* Binary Flat Device Tree Blob	*/
 
 /*
  * Compression Types
diff --git a/include/lcd.h b/include/lcd.h
index 7e23736bca..b688583828 100644
--- a/include/lcd.h
+++ b/include/lcd.h
@@ -148,7 +148,14 @@ typedef struct vidinfo {
 
 extern vidinfo_t panel_info;
 
-#endif /* CONFIG_MPC823 or CONFIG_PXA250 */
+#elif defined(CONFIG_MCC200)
+typedef struct vidinfo {
+	ushort	vl_col;		/* Number of columns (i.e. 160) */
+	ushort	vl_row;		/* Number of rows (i.e. 100) */
+
+	u_char	vl_bpix;	/* Bits per pixel, 0 = 1 */
+} vidinfo_t;
+#endif /* CONFIG_MPC823, CONFIG_PXA250 or CONFIG_MCC200 */
 
 /* Video functions */
 
diff --git a/include/linux/mtd/compat.h b/include/linux/mtd/compat.h
index 460cd45c80..fe55087ea9 100644
--- a/include/linux/mtd/compat.h
+++ b/include/linux/mtd/compat.h
@@ -31,11 +31,13 @@
 #define max_t(type,x,y) \
 	({ type __x = (x); type __y = (y); __x > __y ? __x: __y; })
 
+#ifndef BUG
 #define BUG() do { \
 	printf("U-Boot BUG at %s:%d!\n", __FILE__, __LINE__); \
 } while (0)
 
 #define BUG_ON(condition) do { if (condition) BUG(); } while(0)
+#endif /* BUG */
 
 #define likely(x)	__builtin_expect(!!(x), 1)
 #define unlikely(x)	__builtin_expect(!!(x), 0)
diff --git a/include/linux/mtd/ndfc.h b/include/linux/mtd/ndfc.h
new file mode 100644
index 0000000000..d0558a9826
--- /dev/null
+++ b/include/linux/mtd/ndfc.h
@@ -0,0 +1,67 @@
+/*
+ *  linux/include/linux/mtd/ndfc.h
+ *
+ *  Copyright (c) 2006 Thomas Gleixner <tglx@linutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Info:
+ *   Contains defines, datastructures for ndfc nand controller
+ *
+ */
+#ifndef __LINUX_MTD_NDFC_H
+#define __LINUX_MTD_NDFC_H
+
+/* NDFC Register definitions */
+#define NDFC_CMD		0x00
+#define NDFC_ALE		0x04
+#define NDFC_DATA		0x08
+#define NDFC_ECC		0x10
+#define NDFC_BCFG0		0x30
+#define NDFC_BCFG1		0x34
+#define NDFC_BCFG2		0x38
+#define NDFC_BCFG3		0x3c
+#define NDFC_CCR		0x40
+#define NDFC_STAT		0x44
+#define NDFC_HWCTL		0x48
+#define NDFC_REVID		0x50
+
+#define NDFC_STAT_IS_READY	0x01000000
+
+#define NDFC_CCR_RESET_CE	0x80000000 /* CE Reset */
+#define NDFC_CCR_RESET_ECC	0x40000000 /* ECC Reset */
+#define NDFC_CCR_RIE		0x20000000 /* Interrupt Enable on Device Rdy */
+#define NDFC_CCR_REN		0x10000000 /* Enable wait for Rdy in LinearR */
+#define NDFC_CCR_ROMEN		0x08000000 /* Enable ROM In LinearR */
+#define NDFC_CCR_ARE		0x04000000 /* Auto-Read Enable */
+#define NDFC_CCR_BS(x)		(((x) & 0x3) << 24) /* Select Bank on CE[x] */
+#define NDFC_CCR_BS_MASK	0x03000000 /* Select Bank */
+#define NDFC_CCR_ARAC0		0x00000000 /* 3 Addr, 1 Col 2 Row 512b page */
+#define NDFC_CCR_ARAC1		0x00001000 /* 4 Addr, 1 Col 3 Row 512b page */
+#define NDFC_CCR_ARAC2		0x00002000 /* 4 Addr, 2 Col 2 Row 2K page */
+#define NDFC_CCR_ARAC3		0x00003000 /* 5 Addr, 2 Col 3 Row 2K page */
+#define NDFC_CCR_ARAC_MASK	0x00003000 /* Auto-Read mode Addr Cycles */
+#define NDFC_CCR_RPG		0x0000C000 /* Auto-Read Page */
+#define NDFC_CCR_EBCC		0x00000004 /* EBC Configuration Completed */
+#define NDFC_CCR_DHC		0x00000002 /* Direct Hardware Control Enable */
+
+#define NDFC_BxCFG_EN		0x80000000 /* Bank Enable */
+#define NDFC_BxCFG_CED		0x40000000 /* nCE Style */
+#define NDFC_BxCFG_SZ_MASK	0x08000000 /* Bank Size */
+#define NDFC_BxCFG_SZ_8BIT	0x00000000 /* 8bit */
+#define NDFC_BxCFG_SZ_16BIT	0x08000000 /* 16bit */
+
+#define NDFC_MAX_BANKS		4
+
+struct ndfc_controller_settings {
+	uint32_t	ccr_settings;
+	uint64_t	ndfc_erpn;
+};
+
+struct ndfc_chip_settings {
+	uint32_t	bank_settings;
+};
+
+#endif
diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h
index 50a6ac1e98..089aa1322b 100644
--- a/include/mpc5xxx.h
+++ b/include/mpc5xxx.h
@@ -188,7 +188,14 @@
 #define MPC5XXX_WU_GPIO_ENABLE  (MPC5XXX_WU_GPIO + 0x0000)
 #define MPC5XXX_WU_GPIO_ODE     (MPC5XXX_WU_GPIO + 0x0004)
 #define MPC5XXX_WU_GPIO_DIR     (MPC5XXX_WU_GPIO + 0x0008)
-#define MPC5XXX_WU_GPIO_DATA    (MPC5XXX_WU_GPIO + 0x000c)
+#define MPC5XXX_WU_GPIO_DATA_O  (MPC5XXX_WU_GPIO + 0x000c)
+#define MPC5XXX_WU_GPIO_DATA_I  (MPC5XXX_WU_GPIO + 0x0020)
+
+/* GPIO pins */
+#define GPIO_WKUP_7		0x80000000UL
+#define GPIO_PSC6_0		0x10000000UL
+#define GPIO_PSC3_9		0x04000000UL
+#define GPIO_PSC1_4		0x01000000UL
 
 /* PCI registers */
 #define MPC5XXX_PCI_CMD		(MPC5XXX_PCI + 0x04)
@@ -232,23 +239,92 @@
 #define MPC5XXX_ICTL_PER_STS	(MPC5XXX_ICTL + 0x0030)
 #define MPC5XXX_ICTL_BUS_STS	(MPC5XXX_ICTL + 0x0038)
 
+#define NR_IRQS			64
+
+/* IRQ mapping - these are our logical IRQ numbers */
+#define MPC5XXX_CRIT_IRQ_NUM	4
+#define MPC5XXX_MAIN_IRQ_NUM	17
+#define MPC5XXX_SDMA_IRQ_NUM	17
+#define MPC5XXX_PERP_IRQ_NUM	23
+
+#define MPC5XXX_CRIT_IRQ_BASE	1
+#define MPC5XXX_MAIN_IRQ_BASE	(MPC5XXX_CRIT_IRQ_BASE + MPC5XXX_CRIT_IRQ_NUM)
+#define MPC5XXX_SDMA_IRQ_BASE	(MPC5XXX_MAIN_IRQ_BASE + MPC5XXX_MAIN_IRQ_NUM)
+#define MPC5XXX_PERP_IRQ_BASE	(MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM)
+
+#define MPC5XXX_IRQ0			(MPC5XXX_CRIT_IRQ_BASE + 0)
+#define MPC5XXX_SLICE_TIMER_0_IRQ	(MPC5XXX_CRIT_IRQ_BASE + 1)
+#define MPC5XXX_HI_INT_IRQ		(MPC5XXX_CRIT_IRQ_BASE + 2)
+#define MPC5XXX_CCS_IRQ			(MPC5XXX_CRIT_IRQ_BASE + 3)
+
+#define MPC5XXX_IRQ1			(MPC5XXX_MAIN_IRQ_BASE + 1)
+#define MPC5XXX_IRQ2			(MPC5XXX_MAIN_IRQ_BASE + 2)
+#define MPC5XXX_IRQ3			(MPC5XXX_MAIN_IRQ_BASE + 3)
+#define MPC5XXX_RTC_PINT_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 5)
+#define MPC5XXX_RTC_SINT_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 6)
+#define MPC5XXX_RTC_GPIO_STD_IRQ	(MPC5XXX_MAIN_IRQ_BASE + 7)
+#define MPC5XXX_RTC_GPIO_WKUP_IRQ	(MPC5XXX_MAIN_IRQ_BASE + 8)
+#define MPC5XXX_TMR0_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 9)
+#define MPC5XXX_TMR1_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 10)
+#define MPC5XXX_TMR2_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 11)
+#define MPC5XXX_TMR3_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 12)
+#define MPC5XXX_TMR4_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 13)
+#define MPC5XXX_TMR5_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 14)
+#define MPC5XXX_TMR6_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 15)
+#define MPC5XXX_TMR7_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 16)
+
+#define MPC5XXX_SDMA_IRQ		(MPC5XXX_PERP_IRQ_BASE + 0)
+#define MPC5XXX_PSC1_IRQ		(MPC5XXX_PERP_IRQ_BASE + 1)
+#define MPC5XXX_PSC2_IRQ		(MPC5XXX_PERP_IRQ_BASE + 2)
+#define MPC5XXX_PSC3_IRQ		(MPC5XXX_PERP_IRQ_BASE + 3)
+#define MPC5XXX_PSC6_IRQ		(MPC5XXX_PERP_IRQ_BASE + 4)
+#define MPC5XXX_IRDA_IRQ		(MPC5XXX_PERP_IRQ_BASE + 4)
+#define MPC5XXX_FEC_IRQ			(MPC5XXX_PERP_IRQ_BASE + 5)
+#define MPC5XXX_USB_IRQ			(MPC5XXX_PERP_IRQ_BASE + 6)
+#define MPC5XXX_ATA_IRQ			(MPC5XXX_PERP_IRQ_BASE + 7)
+#define MPC5XXX_PCI_CNTRL_IRQ		(MPC5XXX_PERP_IRQ_BASE + 8)
+#define MPC5XXX_PCI_SCIRX_IRQ		(MPC5XXX_PERP_IRQ_BASE + 9)
+#define MPC5XXX_PCI_SCITX_IRQ		(MPC5XXX_PERP_IRQ_BASE + 10)
+#define MPC5XXX_PSC4_IRQ		(MPC5XXX_PERP_IRQ_BASE + 11)
+#define MPC5XXX_PSC5_IRQ		(MPC5XXX_PERP_IRQ_BASE + 12)
+#define MPC5XXX_SPI_MODF_IRQ		(MPC5XXX_PERP_IRQ_BASE + 13)
+#define MPC5XXX_SPI_SPIF_IRQ		(MPC5XXX_PERP_IRQ_BASE + 14)
+#define MPC5XXX_I2C1_IRQ		(MPC5XXX_PERP_IRQ_BASE + 15)
+#define MPC5XXX_I2C2_IRQ		(MPC5XXX_PERP_IRQ_BASE + 16)
+#define MPC5XXX_MSCAN1_IRQ		(MPC5XXX_PERP_IRQ_BASE + 17)
+#define MPC5XXX_MSCAN2_IRQ		(MPC5XXX_PERP_IRQ_BASE + 18)
+#define MPC5XXX_IR_RX_IRQ		(MPC5XXX_PERP_IRQ_BASE + 19)
+#define MPC5XXX_IR_TX_IRQ		(MPC5XXX_PERP_IRQ_BASE + 20)
+#define MPC5XXX_XLB_ARB_IRQ		(MPC5XXX_PERP_IRQ_BASE + 21)
+#define MPC5XXX_BDLC_IRQ		(MPC5XXX_PERP_IRQ_BASE + 22)
+
 /* General Purpose Timers registers */
 #define MPC5XXX_GPT0_ENABLE		(MPC5XXX_GPT + 0x0)
 #define MPC5XXX_GPT0_COUNTER		(MPC5XXX_GPT + 0x4)
+#define MPC5XXX_GPT0_STATUS		(MPC5XXX_GPT + 0x0C)
 #define MPC5XXX_GPT1_ENABLE		(MPC5XXX_GPT + 0x10)
 #define MPC5XXX_GPT1_COUNTER		(MPC5XXX_GPT + 0x14)
+#define MPC5XXX_GPT1_STATUS		(MPC5XXX_GPT + 0x1C)
 #define MPC5XXX_GPT2_ENABLE		(MPC5XXX_GPT + 0x20)
 #define MPC5XXX_GPT2_COUNTER		(MPC5XXX_GPT + 0x24)
+#define MPC5XXX_GPT2_STATUS		(MPC5XXX_GPT + 0x2C)
 #define MPC5XXX_GPT3_ENABLE		(MPC5XXX_GPT + 0x30)
 #define MPC5XXX_GPT3_COUNTER		(MPC5XXX_GPT + 0x34)
+#define MPC5XXX_GPT3_STATUS		(MPC5XXX_GPT + 0x3C)
 #define MPC5XXX_GPT4_ENABLE		(MPC5XXX_GPT + 0x40)
 #define MPC5XXX_GPT4_COUNTER		(MPC5XXX_GPT + 0x44)
+#define MPC5XXX_GPT4_STATUS		(MPC5XXX_GPT + 0x4C)
 #define MPC5XXX_GPT5_ENABLE		(MPC5XXX_GPT + 0x50)
+#define MPC5XXX_GPT5_STATUS		(MPC5XXX_GPT + 0x5C)
 #define MPC5XXX_GPT5_COUNTER		(MPC5XXX_GPT + 0x54)
 #define MPC5XXX_GPT6_ENABLE		(MPC5XXX_GPT + 0x60)
 #define MPC5XXX_GPT6_COUNTER		(MPC5XXX_GPT + 0x64)
+#define MPC5XXX_GPT6_STATUS		(MPC5XXX_GPT + 0x6C)
 #define MPC5XXX_GPT7_ENABLE		(MPC5XXX_GPT + 0x70)
 #define MPC5XXX_GPT7_COUNTER		(MPC5XXX_GPT + 0x74)
+#define MPC5XXX_GPT7_STATUS		(MPC5XXX_GPT + 0x7C)
+
+#define MPC5XXX_GPT_GPIO_PIN(status)	((0x00000100 & (status)) >> 8)
 
 #define MPC5XXX_GPT7_PWMCFG		(MPC5XXX_GPT + 0x78)
 
diff --git a/include/mpc86xx.h b/include/mpc86xx.h
new file mode 100644
index 0000000000..bc8ba3f2da
--- /dev/null
+++ b/include/mpc86xx.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright 2006 Freescale Semiconductor.
+ * Jeffrey Brown
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ */
+
+#ifndef	__MPC86xx_H__
+#define __MPC86xx_H__
+
+#define EXC_OFF_SYS_RESET	0x0100	/* System reset	offset */
+
+/*
+ * l2cr values.  Look in config_<BOARD>.h for the actual setup
+ */
+#define l2cr		 1017
+
+#define L2CR_L2E         0x80000000 /* bit 0 - enable */
+#define L2CR_L2PE        0x40000000 /* bit 1 - data parity */
+#define L2CR_L2I         0x00200000 /* bit 10 - global invalidate bit */
+#define L2CR_L2CTL       0x00100000 /* bit 11 - l2 ram control */
+#define L2CR_L2DO        0x00010000 /* bit 15 - data-only mode */
+#define L2CR_REP         0x00001000 /* bit 19 - l2 replacement alg */
+#define L2CR_HWF         0x00000800 /* bit 20 - hardware flush */
+#define L2CR_L2IP        0x00000001 /* global invalidate in progress */
+
+/*
+ * BAT settings.  Look in config_<BOARD>.h for the actual setup
+ */
+
+#define BATU_BL_128K            0x00000000
+#define BATU_BL_256K            0x00000004
+#define BATU_BL_512K            0x0000000c
+#define BATU_BL_1M              0x0000001c
+#define BATU_BL_2M              0x0000003c
+#define BATU_BL_4M              0x0000007c
+#define BATU_BL_8M              0x000000fc
+#define BATU_BL_16M             0x000001fc
+#define BATU_BL_32M             0x000003fc
+#define BATU_BL_64M             0x000007fc
+#define BATU_BL_128M            0x00000ffc
+#define BATU_BL_256M            0x00001ffc
+#define BATU_BL_512M            0x00003ffc
+#define BATU_BL_1G              0x00007ffc
+#define BATU_BL_2G              0x0000fffc
+#define BATU_BL_4G              0x0001fffc
+
+#define BATU_VS                 0x00000002
+#define BATU_VP                 0x00000001
+#define BATU_INVALID            0x00000000
+
+#define BATL_WRITETHROUGH       0x00000040
+#define BATL_CACHEINHIBIT       0x00000020
+#define BATL_MEMCOHERENCE	0x00000010
+#define BATL_GUARDEDSTORAGE     0x00000008
+#define BATL_NO_ACCESS		0x00000000
+
+#define BATL_PP_MSK		0x00000003
+#define BATL_PP_00		0x00000000 /* No access */
+#define BATL_PP_01		0x00000001 /* Read-only */
+#define BATL_PP_10		0x00000002 /* Read-write */
+#define BATL_PP_11		0x00000003
+
+#define BATL_PP_NO_ACCESS	BATL_PP_00
+#define BATL_PP_RO		BATL_PP_01
+#define BATL_PP_RW		BATL_PP_10
+
+#define HID0_XBSEN              0x00000100
+#define HID0_HIGH_BAT_EN        0x00800000
+#define HID0_XAEN               0x00020000
+
+#ifndef __ASSEMBLY__
+
+typedef struct {
+	unsigned long freqProcessor;
+	unsigned long freqSystemBus;
+} MPC86xx_SYS_INFO;
+
+#define l1icache_enable	icache_enable
+
+void l2cache_enable(void);
+void l1dcache_enable(void);
+
+static __inline__ unsigned long get_hid0 (void)
+{
+	unsigned long hid0;
+	asm volatile("mfspr %0, 1008" : "=r" (hid0) :);
+	return hid0;
+}
+
+static __inline__ unsigned long get_hid1 (void)
+{
+	unsigned long hid1;
+	asm volatile("mfspr %0, 1009" : "=r" (hid1) :);
+	return hid1;
+}
+
+static __inline__ void set_hid0 (unsigned long hid0)
+{
+	asm volatile("mtspr 1008, %0" : : "r" (hid0));
+}
+
+static __inline__ void set_hid1 (unsigned long hid1)
+{
+	asm volatile("mtspr 1009, %0" : : "r" (hid1));
+}
+
+
+static __inline__ unsigned long get_l2cr (void)
+{
+   unsigned long l2cr_val;
+   asm volatile("mfspr %0, 1017" : "=r" (l2cr_val) :);
+   return l2cr_val;
+}
+
+#endif  /* _ASMLANGUAGE */
+#endif	/* __MPC86xx_H__ */
diff --git a/include/nand.h b/include/nand.h
index 905115b3da..23493f7e98 100644
--- a/include/nand.h
+++ b/include/nand.h
@@ -60,4 +60,65 @@ static inline int nand_erase(nand_info_t *info, ulong off, ulong size)
 	return info->erase(info, &instr);
 }
 
+
+/*****************************************************************************
+ * declarations from nand_util.c
+ ****************************************************************************/
+
+struct nand_write_options {
+	u_char *buffer;		/* memory block containing image to write */
+	ulong length;		/* number of bytes to write */
+	ulong offset;		/* start address in NAND */
+	int quiet;		/* don't display progress messages */
+	int autoplace;		/* if true use auto oob layout */
+	int forcejffs2;		/* force jffs2 oob layout */
+	int forceyaffs;		/* force yaffs oob layout */
+	int noecc;		/* write without ecc */
+	int writeoob;		/* image contains oob data */
+	int pad;		/* pad to page size */
+	int blockalign;		/* 1|2|4 set multiple of eraseblocks
+				 * to align to */
+};
+
+typedef struct nand_write_options nand_write_options_t;
+
+struct nand_read_options {
+	u_char *buffer;		/* memory block in which read image is written*/
+	ulong length;		/* number of bytes to read */
+	ulong offset;		/* start address in NAND */
+	int quiet;		/* don't display progress messages */
+	int readoob;		/* put oob data in image */
+};
+
+typedef struct nand_read_options nand_read_options_t;
+
+struct nand_erase_options {
+	ulong length;		/* number of bytes to erase */
+	ulong offset;		/* first address in NAND to erase */
+	int quiet;		/* don't display progress messages */
+	int jffs2;		/* if true: format for jffs2 usage
+				 * (write appropriate cleanmarker blocks) */
+	int scrub;		/* if true, really clean NAND by erasing
+				 * bad blocks (UNSAFE) */
+};
+
+typedef struct nand_erase_options nand_erase_options_t;
+
+int nand_write_opts(nand_info_t *meminfo, const nand_write_options_t *opts);
+
+int nand_read_opts(nand_info_t *meminfo, const nand_read_options_t *opts);
+int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts);
+
+#define NAND_LOCK_STATUS_TIGHT	0x01
+#define NAND_LOCK_STATUS_LOCK	0x02
+#define NAND_LOCK_STATUS_UNLOCK 0x04
+
+int nand_lock( nand_info_t *meminfo, int tight );
+int nand_unlock( nand_info_t *meminfo, ulong start, ulong length );
+int nand_get_lock_status(nand_info_t *meminfo, ulong offset);
+
+#ifdef CFG_NAND_SELECT_DEVICE
+void board_nand_select_device(struct nand_chip *nand, int chip);
+#endif
+
 #endif
diff --git a/include/pci.h b/include/pci.h
index 0fc00e4276..7c9a0e3441 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -270,6 +270,15 @@
 #define  PCI_AGP_COMMAND_RATE1	0x0001	/* Use 4x rate */
 #define PCI_AGP_SIZEOF		12
 
+/* PCI-X registers */
+
+#define  PCI_X_CMD_DPERR_E      0x0001  /* Data Parity Error Recovery Enable */
+#define  PCI_X_CMD_ERO          0x0002  /* Enable Relaxed Ordering */
+#define  PCI_X_CMD_MAX_READ     0x0000  /* Max Memory Read Byte Count */
+#define  PCI_X_CMD_MAX_SPLIT    0x0030  /* Max Outstanding Split Transactions */
+#define  PCI_X_CMD_VERSION(x)   (((x) >> 12) & 3) /* Version */
+
+
 /* Slot Identification */
 
 #define PCI_SID_ESR		2	/* Expansion Slot Register */
@@ -492,4 +501,7 @@ extern int pci_hose_config_device(struct pci_controller *hose,
 extern void pci_mpc824x_init (struct pci_controller *hose);
 #endif
 
+#ifdef CONFIG_MPC85xx
+extern void pci_mpc85xx_init (struct pci_controller *hose);
+#endif
 #endif	/* _PCI_H */
diff --git a/include/pci_ids.h b/include/pci_ids.h
index 8cc3ec0a23..3b10452416 100644
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -1045,6 +1045,9 @@
 #define PCI_DEVICE_ID_REALTEK_8139	0x8139
 #define PCI_DEVICE_ID_REALTEK_8169	0x8169
 
+#define PCI_VENDOR_ID_DLINK		0x1186
+#define PCI_DEVICE_ID_DLINK_8139	0x1300
+
 #define PCI_VENDOR_ID_XILINX		0x10ee
 #define PCI_DEVICE_ID_TURBOPAM		0x4020
 
diff --git a/include/ppc440.h b/include/ppc440.h
index d5a9f66a41..e407320a9e 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -82,7 +82,10 @@
 #define	 ivor13 0x19d	/* interrupt vector offset register 13 */
 #define	 ivor14 0x19e	/* interrupt vector offset register 14 */
 #define	 ivor15 0x19f	/* interrupt vector offset register 15 */
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 #define	 mcsrr0 0x23a	/* machine check save/restore register 0 */
 #define	 mcsrr1 0x23b	/* mahcine check save/restore register 1 */
 #define	 mcsr	0x23c	/* machine check status register */
@@ -151,7 +154,18 @@
 #define sdr_ecid1	0x0081
 #define sdr_ecid2	0x0082
 #define sdr_jtag	0x00c0
+#if !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
 #define sdr_ddrdl	0x00e0
+#else
+#define sdr_cfg		0x00e0
+#define SDR_CFG_LT2_MASK          0x01000000 /* Leakage test 2*/
+#define SDR_CFG_64_32BITS_MASK    0x01000000 /* Switch DDR 64 bits or 32 bits */
+#define SDR_CFG_32BITS            0x00000000  /* 32 bits */
+#define SDR_CFG_64BITS            0x01000000  /* 64 bits */
+#define SDR_CFG_MC_V2518_MASK     0x02000000 /* Low VDD2518 (2.5 or 1.8V) */
+#define SDR_CFG_MC_V25            0x00000000  /* 2.5 V */
+#define SDR_CFG_MC_V18            0x02000000  /* 1.8 V */
+#endif /* !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) */
 #define sdr_ebc		0x0100
 #define sdr_uart0	0x0120	/* UART0 Config */
 #define sdr_uart1	0x0121	/* UART1 Config */
@@ -180,6 +194,54 @@
 #define sdr_plbtr	0x4200
 #define sdr_mfr		0x4300	/* SDR0_MFR reg */
 
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* test-only!!!! */
+#define DDR0_00	0x00
+#define DDR0_01	0x01
+#define DDR0_02	0x02
+#define DDR0_03	0x03
+#define DDR0_04	0x04
+#define DDR0_05	0x05
+#define DDR0_06	0x06
+#define DDR0_07	0x07
+#define DDR0_08	0x08
+#define DDR0_09	0x09
+#define DDR0_10	0x0A
+#define DDR0_11	0x0B
+#define DDR0_12	0x0C
+#define DDR0_13	0x0D
+#define DDR0_14	0x0E
+#define DDR0_15	0x0F
+#define DDR0_16	0x10
+#define DDR0_17	0x11
+#define DDR0_18	0x12
+#define DDR0_19	0x13
+#define DDR0_20	0x14
+#define DDR0_21	0x15
+#define DDR0_22	0x16
+#define DDR0_23	0x17
+#define DDR0_24	0x18
+#define DDR0_25	0x19
+#define DDR0_26	0x1A
+#define DDR0_27	0x1B
+#define DDR0_28	0x1C
+#define DDR0_29	0x1D
+#define DDR0_30	0x1E
+#define DDR0_31	0x1F
+#define DDR0_32	0x20
+#define DDR0_33	0x21
+#define DDR0_34	0x22
+#define DDR0_35	0x23
+#define DDR0_36	0x24
+#define DDR0_37	0x25
+#define DDR0_38	0x26
+#define DDR0_39	0x27
+#define DDR0_40	0x28
+#define DDR0_41	0x29
+#define DDR0_42	0x2A
+#define DDR0_43	0x2B
+#define DDR0_44	0x2C
+#endif /*CONFIG_440EPX*/
+
 /*-----------------------------------------------------------------------------
  | SDRAM Controller
  +----------------------------------------------------------------------------*/
@@ -787,7 +849,8 @@
 #define xbcfg		0x23	/* external bus configuration reg	*/
 #define xbcid		0x24	/* external bus core id reg		*/
 
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 
 /* PLB4 to PLB3 Bridge OUT */
 #define P4P3_DCR_BASE           0x020
@@ -877,6 +940,7 @@
 #define plb1_bearl                (PLB_ARBITER_BASE+ 0x0C)
 #define plb1_bearh                (PLB_ARBITER_BASE+ 0x0D)
 
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
 /* Pin Function Control Register 1 */
 #define SDR0_PFC1                    0x4101
 #define   SDR0_PFC1_U1ME_MASK         0x02000000    /* UART1 Mode Enable */
@@ -918,6 +982,178 @@
 #define   SDR0_USB0_LEEN_DISABLE      0x00000000      /* Little Endian Disable */
 #define   SDR0_USB0_LEEN_ENABLE       0x00000001      /* Little Endian Enable */
 
+/* Miscealleneaous Function Reg. */
+#define SDR0_MFR                     0x4300
+#define   SDR0_MFR_ETH0_CLK_SEL_MASK   0x08000000   /* Ethernet0 Clock Select */
+#define   SDR0_MFR_ETH0_CLK_SEL_EXT    0x00000000
+#define   SDR0_MFR_ETH1_CLK_SEL_MASK   0x04000000   /* Ethernet1 Clock Select */
+#define   SDR0_MFR_ETH1_CLK_SEL_EXT    0x00000000
+#define   SDR0_MFR_ZMII_MODE_MASK      0x03000000   /* ZMII Mode Mask */
+#define   SDR0_MFR_ZMII_MODE_MII       0x00000000     /* ZMII Mode MII */
+#define   SDR0_MFR_ZMII_MODE_SMII      0x01000000     /* ZMII Mode SMII */
+#define   SDR0_MFR_ZMII_MODE_RMII_10M  0x02000000     /* ZMII Mode RMII - 10 Mbs */
+#define   SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000     /* ZMII Mode RMII - 100 Mbs */
+#define   SDR0_MFR_ZMII_MODE_BIT0      0x02000000     /* ZMII Mode Bit0 */
+#define   SDR0_MFR_ZMII_MODE_BIT1      0x01000000     /* ZMII Mode Bit1 */
+#define   SDR0_MFR_ZM_ENCODE(n)        ((((unsigned long)(n))&0x3)<<24)
+#define   SDR0_MFR_ZM_DECODE(n)        ((((unsigned long)(n))<<24)&0x3)
+
+#define   SDR0_MFR_ERRATA3_EN0         0x00800000
+#define   SDR0_MFR_ERRATA3_EN1         0x00400000
+#define   SDR0_MFR_PKT_REJ_MASK        0x00180000   /* Pkt Rej. Enable Mask */
+#define   SDR0_MFR_PKT_REJ_EN          0x00180000   /* Pkt Rej. Enable on both EMAC3 0-1 */
+#define   SDR0_MFR_PKT_REJ_EN0         0x00100000   /* Pkt Rej. Enable on EMAC3(0) */
+#define   SDR0_MFR_PKT_REJ_EN1         0x00080000   /* Pkt Rej. Enable on EMAC3(1) */
+#define   SDR0_MFR_PKT_REJ_POL         0x00200000   /* Packet Reject Polarity */
+
+#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
+
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define SDR_USB2D0CR                 0x0320
+#define   SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK   0x00000004    /* USB 2.0 Device/EBC Master Selection */
+#define   SDR0_USB2D0CR_USB2DEV_SELECTION      0x00000004    /* USB 2.0 Device Selection */
+#define   SDR0_USB2D0CR_EBC_SELECTION          0x00000000    /* EBC Selection */
+
+#define   SDR0_USB2D0CR_USB_DEV_INT_SEL_MASK   0x00000002    /* USB Device Interface Selection */
+#define   SDR0_USB2D0CR_USB20D_DEVSEL          0x00000000      /* USB2.0 Device Selected */
+#define   SDR0_USB2D0CR_USB11D_DEVSEL          0x00000002      /* USB1.1 Device Selected */
+
+#define   SDR0_USB2D0CR_LEEN_MASK              0x00000001    /* Little Endian selection */
+#define   SDR0_USB2D0CR_LEEN_DISABLE           0x00000000      /* Little Endian Disable */
+#define   SDR0_USB2D0CR_LEEN_ENABLE            0x00000001      /* Little Endian Enable */
+
+/* USB2 Host Control Register */
+#define SDR0_USB2H0CR                0x0340
+#define   SDR0_USB2H0CR_WDINT_MASK             0x00000001 /* Host UTMI Word Interface */
+#define   SDR0_USB2H0CR_WDINT_8BIT_60MHZ       0x00000000  /* 8-bit/60MHz */
+#define   SDR0_USB2H0CR_WDINT_16BIT_30MHZ      0x00000001  /* 16-bit/30MHz */
+#define   SDR0_USB2H0CR_EFLADJ_MASK            0x0000007e /* EHCI Frame Length Adjustment */
+
+/* Pin Function Control Register 1 */
+#define SDR0_PFC1                    0x4101
+#define   SDR0_PFC1_U1ME_MASK                  0x02000000    /* UART1 Mode Enable */
+#define   SDR0_PFC1_U1ME_DSR_DTR               0x00000000      /* UART1 in DSR/DTR Mode */
+#define   SDR0_PFC1_U1ME_CTS_RTS               0x02000000      /* UART1 in CTS/RTS Mode */
+
+#define   SDR0_PFC1_SELECT_MASK                0x01C00000 /* Ethernet Pin Select EMAC 0 */
+#define   SDR0_PFC1_SELECT_CONFIG_1_1          0x00C00000   /* 1xMII   using RGMII bridge */
+#define   SDR0_PFC1_SELECT_CONFIG_1_2          0x00000000   /* 1xMII   using  ZMII bridge */
+#define   SDR0_PFC1_SELECT_CONFIG_2            0x00C00000   /* 1xGMII  using RGMII bridge */
+#define   SDR0_PFC1_SELECT_CONFIG_3            0x01000000   /* 1xTBI   using RGMII bridge */
+#define   SDR0_PFC1_SELECT_CONFIG_4            0x01400000   /* 2xRGMII using RGMII bridge */
+#define   SDR0_PFC1_SELECT_CONFIG_5            0x01800000   /* 2xRTBI  using RGMII bridge */
+#define   SDR0_PFC1_SELECT_CONFIG_6            0x00800000   /* 2xSMII  using  ZMII bridge */
+
+#define   SDR0_PFC1_U0ME_MASK                  0x00080000    /* UART0 Mode Enable */
+#define   SDR0_PFC1_U0ME_DSR_DTR               0x00000000      /* UART0 in DSR/DTR Mode */
+#define   SDR0_PFC1_U0ME_CTS_RTS               0x00080000      /* UART0 in CTS/RTS Mode */
+#define   SDR0_PFC1_U0IM_MASK                  0x00040000    /* UART0 Interface Mode */
+#define   SDR0_PFC1_U0IM_8PINS                 0x00000000      /* UART0 Interface Mode 8 pins */
+#define   SDR0_PFC1_U0IM_4PINS                 0x00040000      /* UART0 Interface Mode 4 pins */
+#define   SDR0_PFC1_SIS_MASK                   0x00020000    /* SCP or IIC1 Selection */
+#define   SDR0_PFC1_SIS_SCP_SEL                0x00000000      /* SCP Selected */
+#define   SDR0_PFC1_SIS_IIC1_SEL               0x00020000      /* IIC1 Selected */
+#define   SDR0_PFC1_UES_MASK                   0x00010000    /* USB2D_RX_Active / EBC_Hold Req Selection */
+#define   SDR0_PFC1_UES_USB2D_SEL              0x00000000      /* USB2D_RX_Active Selected */
+#define   SDR0_PFC1_UES_EBCHR_SEL              0x00010000      /* EBC_Hold Req Selected */
+#define   SDR0_PFC1_DIS_MASK                   0x00008000    /* DMA_Req(1) / UIC_IRQ(5) Selection */
+#define   SDR0_PFC1_DIS_DMAR_SEL               0x00000000      /* DMA_Req(1) Selected */
+#define   SDR0_PFC1_DIS_UICIRQ5_SEL            0x00008000      /* UIC_IRQ(5) Selected */
+#define   SDR0_PFC1_ERE_MASK                   0x00004000    /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
+#define   SDR0_PFC1_ERE_EXTR_SEL               0x00000000      /* EBC Mast.Ext.Req.En. Selected */
+#define   SDR0_PFC1_ERE_GPIO0_27_SEL           0x00004000      /* GPIO0(27) Selected */
+#define   SDR0_PFC1_UPR_MASK                   0x00002000    /* USB2 Device Packet Reject Selection */
+#define   SDR0_PFC1_UPR_DISABLE                0x00000000      /* USB2 Device Packet Reject Disable */
+#define   SDR0_PFC1_UPR_ENABLE                 0x00002000      /* USB2 Device Packet Reject Enable */
+
+#define   SDR0_PFC1_PLB_PME_MASK               0x00001000    /* PLB3/PLB4 Perf. Monitor En. Selection */
+#define   SDR0_PFC1_PLB_PME_PLB3_SEL           0x00000000      /* PLB3 Performance Monitor Enable */
+#define   SDR0_PFC1_PLB_PME_PLB4_SEL           0x00001000      /* PLB3 Performance Monitor Enable */
+#define   SDR0_PFC1_GFGGI_MASK                 0x0000000F    /* GPT Frequency Generation Gated In */
+
+/* Ethernet PLL Configuration Register */
+#define SDR0_PFC2                    0x4102
+#define   SDR0_PFC2_TUNE_MASK                  0x01FF8000  /* Loop stability tuning bits */
+#define   SDR0_PFC2_MULTI_MASK                 0x00007C00  /* Frequency multiplication selector */
+#define   SDR0_PFC2_RANGEB_MASK                0x00000380  /* PLLOUTB/C frequency selector */
+#define   SDR0_PFC2_RANGEA_MASK                0x00000071  /* PLLOUTA frequency selector */
+
+#define   SDR0_PFC2_SELECT_MASK                0xE0000000  /* Ethernet Pin select EMAC1 */
+#define   SDR0_PFC2_SELECT_CONFIG_1_1          0x60000000   /* 1xMII   using RGMII bridge */
+#define   SDR0_PFC2_SELECT_CONFIG_1_2          0x00000000   /* 1xMII   using  ZMII bridge */
+#define   SDR0_PFC2_SELECT_CONFIG_2            0x60000000   /* 1xGMII  using RGMII bridge */
+#define   SDR0_PFC2_SELECT_CONFIG_3            0x80000000   /* 1xTBI   using RGMII bridge */
+#define   SDR0_PFC2_SELECT_CONFIG_4            0xA0000000   /* 2xRGMII using RGMII bridge */
+#define   SDR0_PFC2_SELECT_CONFIG_5            0xC0000000   /* 2xRTBI  using RGMII bridge */
+#define   SDR0_PFC2_SELECT_CONFIG_6            0x40000000   /* 2xSMII  using  ZMII bridge */
+
+/* USB2PHY0 Control Register */
+#define SDR0_USB2PHY0CR               0x4103
+#define   SDR0_USB2PHY0CR_UTMICN_MASK          0x00100000 /*  PHY UTMI interface connection */
+#define   SDR0_USB2PHY0CR_UTMICN_DEV           0x00000000  /* Device support */
+#define   SDR0_USB2PHY0CR_UTMICN_HOST          0x00100000  /* Host support */
+
+#define   SDR0_USB2PHY0CR_DWNSTR_MASK          0x00400000 /* Select downstream port mode */
+#define   SDR0_USB2PHY0CR_DWNSTR_DEV           0x00000000  /* Device */
+#define   SDR0_USB2PHY0CR_DWNSTR_HOST          0x00400000  /* Host   */
+
+#define   SDR0_USB2PHY0CR_DVBUS_MASK           0x00800000 /* VBus detect (Device mode only)  */
+#define   SDR0_USB2PHY0CR_DVBUS_PURDIS         0x00000000  /* Pull-up resistance on D+ is disabled */
+#define   SDR0_USB2PHY0CR_DVBUS_PUREN          0x00800000  /* Pull-up resistance on D+ is enabled */
+
+#define   SDR0_USB2PHY0CR_WDINT_MASK           0x01000000 /* PHY UTMI data width and clock select  */
+#define   SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ     0x00000000  /* 8-bit data/60MHz */
+#define   SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ    0x01000000  /* 16-bit data/30MHz */
+
+#define   SDR0_USB2PHY0CR_LOOPEN_MASK          0x02000000 /* Loop back test enable  */
+#define   SDR0_USB2PHY0CR_LOOP_ENABLE          0x00000000  /* Loop back disabled */
+#define   SDR0_USB2PHY0CR_LOOP_DISABLE         0x02000000  /* Loop back enabled (only test purposes) */
+
+#define   SDR0_USB2PHY0CR_XOON_MASK            0x04000000 /* Force XO block on during a suspend  */
+#define   SDR0_USB2PHY0CR_XO_ON                0x00000000  /* PHY XO block is powered-on */
+#define   SDR0_USB2PHY0CR_XO_OFF               0x04000000  /* PHY XO block is powered-off when all ports are suspended */
+
+#define   SDR0_USB2PHY0CR_PWRSAV_MASK          0x08000000 /* Select PHY power-save mode  */
+#define   SDR0_USB2PHY0CR_PWRSAV_OFF           0x00000000  /* Non-power-save mode */
+#define   SDR0_USB2PHY0CR_PWRSAV_ON            0x08000000  /* Power-save mode. Valid only for full-speed operation */
+
+#define   SDR0_USB2PHY0CR_XOREF_MASK           0x10000000 /* Select reference clock source  */
+#define   SDR0_USB2PHY0CR_XOREF_INTERNAL       0x00000000  /* PHY PLL uses chip internal 48M clock as a reference */
+#define   SDR0_USB2PHY0CR_XOREF_XO             0x10000000  /* PHY PLL uses internal XO block output as a reference */
+
+#define   SDR0_USB2PHY0CR_XOCLK_MASK           0x20000000 /* Select clock for XO block  */
+#define   SDR0_USB2PHY0CR_XOCLK_EXTERNAL       0x00000000  /* PHY macro used an external clock */
+#define   SDR0_USB2PHY0CR_XOCLK_CRYSTAL        0x20000000  /* PHY macro uses the clock from a crystal */
+
+#define   SDR0_USB2PHY0CR_CLKSEL_MASK          0xc0000000 /* Select ref clk freq */
+#define   SDR0_USB2PHY0CR_CLKSEL_12MHZ         0x00000000 /* Select ref clk freq = 12 MHz*/
+#define   SDR0_USB2PHY0CR_CLKSEL_48MHZ         0x40000000 /* Select ref clk freq = 48 MHz*/
+#define   SDR0_USB2PHY0CR_CLKSEL_24MHZ         0x80000000 /* Select ref clk freq = 24 MHz*/
+
+/* Miscealleneaous Function Reg. */
+#define SDR0_MFR                     0x4300
+#define   SDR0_MFR_ETH0_CLK_SEL_MASK   0x08000000   /* Ethernet0 Clock Select */
+#define   SDR0_MFR_ETH0_CLK_SEL_EXT    0x00000000
+#define   SDR0_MFR_ETH1_CLK_SEL_MASK   0x04000000   /* Ethernet1 Clock Select */
+#define   SDR0_MFR_ETH1_CLK_SEL_EXT    0x00000000
+#define   SDR0_MFR_ZMII_MODE_MASK      0x03000000   /* ZMII Mode Mask */
+#define   SDR0_MFR_ZMII_MODE_MII       0x00000000     /* ZMII Mode MII */
+#define   SDR0_MFR_ZMII_MODE_SMII      0x01000000     /* ZMII Mode SMII */
+#define   SDR0_MFR_ZMII_MODE_BIT0      0x02000000     /* ZMII Mode Bit0 */
+#define   SDR0_MFR_ZMII_MODE_BIT1      0x01000000     /* ZMII Mode Bit1 */
+#define   SDR0_MFR_ZM_ENCODE(n)        ((((unsigned long)(n))&0x3)<<24)
+#define   SDR0_MFR_ZM_DECODE(n)        ((((unsigned long)(n))<<24)&0x3)
+
+#define   SDR0_MFR_ERRATA3_EN0         0x00800000
+#define   SDR0_MFR_ERRATA3_EN1         0x00400000
+#define   SDR0_MFR_PKT_REJ_MASK        0x00180000   /* Pkt Rej. Enable Mask */
+#define   SDR0_MFR_PKT_REJ_EN          0x00180000   /* Pkt Rej. Enable on both EMAC3 0-1 */
+#define   SDR0_MFR_PKT_REJ_EN0         0x00100000   /* Pkt Rej. Enable on EMAC3(0) */
+#define   SDR0_MFR_PKT_REJ_EN1         0x00080000   /* Pkt Rej. Enable on EMAC3(1) */
+#define   SDR0_MFR_PKT_REJ_POL         0x00200000   /* Packet Reject Polarity */
+
+#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */
+
 /* CUST0 Customer Configuration Register0 */
 #define SDR0_CUST0                   0x4000
 #define   SDR0_CUST0_MUX_E_N_G_MASK   0xC0000000     /* Mux_Emac_NDFC_GPIO */
@@ -1007,27 +1243,18 @@
 #define   SDR0_PFC1_PLB_PME_PLB4_SEL  0x00001000      /* PLB3 Performance Monitor Enable */
 #define   SDR0_PFC1_GFGGI_MASK        0x0000000F    /* GPT Frequency Generation Gated In */
 
-/* Miscealleneaous Function Reg. */
-#define SDR0_MFR                     0x4300
-#define   SDR0_MFR_ETH0_CLK_SEL        0x08000000   /* Ethernet0 Clock Select */
-#define   SDR0_MFR_ETH1_CLK_SEL        0x04000000   /* Ethernet1 Clock Select */
-#define   SDR0_MFR_ZMII_MODE_MASK      0x03000000   /* ZMII Mode Mask */
-#define   SDR0_MFR_ZMII_MODE_MII       0x00000000     /* ZMII Mode MII */
-#define   SDR0_MFR_ZMII_MODE_SMII      0x01000000     /* ZMII Mode SMII */
-#define   SDR0_MFR_ZMII_MODE_RMII_10M  0x02000000     /* ZMII Mode RMII - 10 Mbs */
-#define   SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000     /* ZMII Mode RMII - 100 Mbs */
-#define   SDR0_MFR_ZMII_MODE_BIT0      0x02000000     /* ZMII Mode Bit0 */
-#define   SDR0_MFR_ZMII_MODE_BIT1      0x01000000     /* ZMII Mode Bit1 */
-#define   SDR0_MFR_ZM_ENCODE(n)        ((((unsigned long)(n))&0x3)<<24)
-#define   SDR0_MFR_ZM_DECODE(n)        ((((unsigned long)(n))<<24)&0x3)
-
-#define   SDR0_MFR_ERRATA3_EN0         0x00800000
-#define   SDR0_MFR_ERRATA3_EN1         0x00400000
-#define   SDR0_MFR_PKT_REJ_MASK        0x00300000   /* Pkt Rej. Enable Mask */
-#define   SDR0_MFR_PKT_REJ_EN          0x00300000   /* Pkt Rej. Enable on both EMAC3 0-1 */
-#define   SDR0_MFR_PKT_REJ_EN0         0x00200000   /* Pkt Rej. Enable on EMAC3(0) */
-#define   SDR0_MFR_PKT_REJ_EN1         0x00100000   /* Pkt Rej. Enable on EMAC3(1) */
-#define   SDR0_MFR_PKT_REJ_POL         0x00080000   /* Packet Reject Polarity */
+/*-----------------------------------------------------------------------------
+ | Internal SRAM
+ +----------------------------------------------------------------------------*/
+#define ISRAM0_DCR_BASE 0x380
+#define isram0_sb0cr	(ISRAM0_DCR_BASE+0x00)	/* SRAM bank config 0*/
+#define isram0_bear	(ISRAM0_DCR_BASE+0x04)	/* SRAM bus error addr reg */
+#define isram0_besr0	(ISRAM0_DCR_BASE+0x05)	/* SRAM bus error status reg 0 */
+#define isram0_besr1	(ISRAM0_DCR_BASE+0x06)	/* SRAM bus error status reg 1 */
+#define isram0_pmeg	(ISRAM0_DCR_BASE+0x07)	/* SRAM power management */
+#define isram0_cid	(ISRAM0_DCR_BASE+0x08)	/* SRAM bus core id reg */
+#define isram0_revid	(ISRAM0_DCR_BASE+0x09)	/* SRAM bus revision id reg */
+#define isram0_dpc	(ISRAM0_DCR_BASE+0x0a)	/* SRAM data parity check reg */
 
 #else
 
@@ -1121,7 +1348,7 @@
 #define uic1vr	(UIC1_DCR_BASE+0x7)   /* UIC1 vector			   */
 #define uic1vcr (UIC1_DCR_BASE+0x8)   /* UIC1 vector configuration	   */
 
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define UIC2_DCR_BASE 0xe0
 #define uic2sr	(UIC0_DCR_BASE+0x0)   /* UIC2 status-Read Clear		*/
 #define uic2srs	(UIC0_DCR_BASE+0x1)   /* UIC2 status-Read Set */
@@ -1343,8 +1570,8 @@
 #define malrxctp0r  (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg   */
 #define malrxctp1r  (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg   */
 #if defined(CONFIG_440GX)
-#define malrxctp2r  (MAL_DCR_BASE+0x42) /* RX 0 Channel table pointer reg   */
-#define malrxctp3r  (MAL_DCR_BASE+0x43) /* RX 1 Channel table pointer reg   */
+#define malrxctp2r  (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg   */
+#define malrxctp3r  (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg   */
 #endif /* CONFIG_440GX */
 #define malrcbs0    (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg	    */
 #define malrcbs1    (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg	    */
@@ -1423,6 +1650,46 @@
 #define UIC_EIR6	0x00000004	/* External interrupt 6		    */
 #define UIC_UIC1NC	0x00000002	/* UIC1 non-critical interrupt	    */
 #define UIC_UIC1C	0x00000001	/* UIC1 critical interrupt	    */
+
+#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+
+#define UIC_U0        0x80000000  /* UART 0                             */
+#define UIC_U1        0x40000000  /* UART 1                             */
+#define UIC_IIC0      0x20000000  /* IIC                                */
+#define UIC_KRD       0x10000000  /* Kasumi Ready for data              */
+#define UIC_KDA       0x08000000  /* Kasumi Data Available              */
+#define UIC_PCRW      0x04000000  /* PCI command register write         */
+#define UIC_PPM       0x02000000  /* PCI power management               */
+#define UIC_IIC1      0x01000000  /* IIC                                */
+#define UIC_SPI       0x00800000  /* SPI                                */
+#define UIC_EPCISER   0x00400000  /* External PCI SERR                  */
+#define UIC_MTE       0x00200000  /* MAL TXEOB                          */
+#define UIC_MRE       0x00100000  /* MAL RXEOB                          */
+#define UIC_D0        0x00080000  /* DMA channel 0                      */
+#define UIC_D1        0x00040000  /* DMA channel 1                      */
+#define UIC_D2        0x00020000  /* DMA channel 2                      */
+#define UIC_D3        0x00010000  /* DMA channel 3                      */
+#define UIC_UD0       0x00008000  /* UDMA irq 0                         */
+#define UIC_UD1       0x00004000  /* UDMA irq 1                         */
+#define UIC_UD2       0x00002000  /* UDMA irq 2                         */
+#define UIC_UD3       0x00001000  /* UDMA irq 3                         */
+#define UIC_HSB2D     0x00000800  /* USB2.0 Device                      */
+#define UIC_OHCI1     0x00000400  /* USB2.0 Host OHCI irq 1             */
+#define UIC_OHCI2     0x00000200  /* USB2.0 Host OHCI irq 2             */
+#define UIC_EIP94     0x00000100  /* Security EIP94                     */
+#define UIC_ETH0      0x00000080  /* Emac 0                             */
+#define UIC_ETH1      0x00000040  /* Emac 1                             */
+#define UIC_EHCI      0x00000020  /* USB2.0 Host EHCI                   */
+#define UIC_EIR4      0x00000010  /* External interrupt 4               */
+#define UIC_UIC2NC    0x00000008  /* UIC2 non-critical interrupt        */
+#define UIC_UIC2C     0x00000004  /* UIC2 critical interrupt            */
+#define UIC_UIC1NC    0x00000002  /* UIC1 non-critical interrupt        */
+#define UIC_UIC1C     0x00000001  /* UIC1 critical interrupt            */
+
+/* For compatibility with 405 code */
+#define UIC_MAL_TXEOB	UIC_MTE
+#define UIC_MAL_RXEOB	UIC_MRE
+
 #elif !defined(CONFIG_440SPE)
 #define UIC_U0		0x80000000	/* UART 0			    */
 #define UIC_U1		0x40000000	/* UART 1			    */
@@ -1531,6 +1798,48 @@
 #define UIC_EWU0	0x00000004	/* Ethernet 0 wakeup		    */
 #define UIC_ETH1	0x00000002	/* Ethernet 1			    */
 #define UIC_EWU1	0x00000001	/* Ethernet 1 wakeup		    */
+
+#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+
+#define UIC_MS        0x80000000  /* MAL SERR                           */
+#define UIC_MTDE      0x40000000  /* MAL TXDE                           */
+#define UIC_MRDE      0x20000000  /* MAL RXDE                           */
+#define UIC_U2        0x10000000  /* UART 2                             */
+#define UIC_U3        0x08000000  /* UART 3                             */
+#define UIC_EBCO      0x04000000  /* EBCO interrupt status              */
+#define UIC_NDFC      0x02000000  /* NDFC                               */
+#define UIC_KSLE      0x01000000  /* KASUMI slave error                 */
+#define UIC_CT5       0x00800000  /* GPT compare timer 5                */
+#define UIC_CT6       0x00400000  /* GPT compare timer 6                */
+#define UIC_PLB34I0   0x00200000  /* PLB3X4X MIRQ0                      */
+#define UIC_PLB34I1   0x00100000  /* PLB3X4X MIRQ1                      */
+#define UIC_PLB34I2   0x00080000  /* PLB3X4X MIRQ2                      */
+#define UIC_PLB34I3   0x00040000  /* PLB3X4X MIRQ3                      */
+#define UIC_PLB34I4   0x00020000  /* PLB3X4X MIRQ4                      */
+#define UIC_PLB34I5   0x00010000  /* PLB3X4X MIRQ5                      */
+#define UIC_CT0       0x00008000  /* GPT compare timer 0                */
+#define UIC_CT1       0x00004000  /* GPT compare timer 1                */
+#define UIC_EIR7      0x00002000  /* External interrupt 7               */
+#define UIC_EIR8      0x00001000  /* External interrupt 8               */
+#define UIC_EIR9      0x00000800  /* External interrupt 9               */
+#define UIC_CT2       0x00000400  /* GPT compare timer 2                */
+#define UIC_CT3       0x00000200  /* GPT compare timer 3                */
+#define UIC_CT4       0x00000100  /* GPT compare timer 4                */
+#define UIC_SRE       0x00000080  /* Serial ROM error                   */
+#define UIC_GPTDC     0x00000040  /* GPT decrementer pulse              */
+#define UIC_RSVD0     0x00000020  /* Reserved                           */
+#define UIC_EPCIPER   0x00000010  /* External PCI PERR                  */
+#define UIC_EIR0      0x00000008  /* External interrupt 0               */
+#define UIC_EWU0      0x00000004  /* Ethernet 0 wakeup                  */
+#define UIC_EIR1      0x00000002  /* External interrupt 1               */
+#define UIC_EWU1      0x00000001  /* Ethernet 1 wakeup                  */
+
+/* For compatibility with 405 code */
+#define UIC_MAL_SERR	UIC_MS
+#define UIC_MAL_TXDE	UIC_MTDE
+#define UIC_MAL_RXDE	UIC_MRDE
+#define UIC_ENET	UIC_ETH0
+
 #elif !defined(CONFIG_440SPE)
 #define UIC_MS		0x80000000	/* MAL SERR			    */
 #define UIC_MTDE	0x40000000	/* MAL TXDE			    */
@@ -1608,6 +1917,20 @@
 #define UIC_RSVD29	0x00000004	/* Reserved			    */
 #define UIC_RSVD30	0x00000002	/* Reserved			    */
 #define UIC_RSVD31	0x00000001	/* Reserved			    */
+
+#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* UIC2 */
+
+#define UIC_EIR5    0x80000000  /* External interrupt 5                 */
+#define UIC_EIR6    0x40000000  /* External interrupt 6                 */
+#define UIC_OPB     0x20000000  /* OPB to PLB bridge interrupt stat     */
+#define UIC_EIR2    0x10000000  /* External interrupt 2                 */
+#define UIC_EIR3    0x08000000  /* External interrupt 3                 */
+#define UIC_DDR2    0x04000000  /* DDR2 sdram                           */
+#define UIC_MCTX0   0x02000000  /* MAl intp coalescence TX0             */
+#define UIC_MCTX1   0x01000000  /* MAl intp coalescence TX1             */
+#define UIC_MCTR0   0x00800000  /* MAl intp coalescence TR0             */
+#define UIC_MCTR1   0x00400000  /* MAl intp coalescence TR1             */
+
 #endif	/* CONFIG_440GX */
 
 /*---------------------------------------------------------------------------+
@@ -1623,6 +1946,17 @@
 
 #define UICB0_ALL		(UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \
 						 UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI)
+
+#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+
+#define UICB0_UIC1CI	0x00000000	/* UIC1 Critical Interrupt	    */
+#define UICB0_UIC1NCI	0x00000000	/* UIC1 Noncritical Interrupt	    */
+#define UICB0_UIC2CI	0x00000000	/* UIC2 Critical Interrupt	    */
+#define UICB0_UIC2NCI	0x00000000	/* UIC2 Noncritical Interrupt	    */
+
+#define UICB0_ALL		(UICB0_UIC1CI | UICB0_UIC1NCI | \
+						 UICB0_UIC1CI | UICB0_UIC2NCI)
+
 #endif /* CONFIG_440GX */
 /*---------------------------------------------------------------------------+
 |  Universal interrupt controller interrupts
@@ -2262,7 +2596,8 @@
 #define SDR0_SDSTP1_PAE_MASK		(0x80000000 >> 13)
 #define SDR0_SDSTP1_PISE_MASK		(0x80000000 >> 15)
 #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define SDR0_SDSTP1_PAE_MASK		(0x80000000 >> 21)
 #define SDR0_SDSTP1_PAME_MASK		(0x80000000 >> 27)
 #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
@@ -2390,11 +2725,81 @@
 #define SDR0_MFR_ZMII_MODE_BIT1      0x01000000     /* ZMII Mode Bit1 */
 #define SDR0_MFR_ERRATA3_EN0         0x00800000
 #define SDR0_MFR_ERRATA3_EN1         0x00400000
+#if defined(CONFIG_440GX) /* test-only: only 440GX or 440SPE??? */
 #define SDR0_MFR_PKT_REJ_MASK        0x00300000   /* Pkt Rej. Enable Mask */
 #define SDR0_MFR_PKT_REJ_EN          0x00300000   /* Pkt Rej. Enable on both EMAC3 0-1 */
 #define SDR0_MFR_PKT_REJ_EN0         0x00200000   /* Pkt Rej. Enable on EMAC3(0) */
 #define SDR0_MFR_PKT_REJ_EN1         0x00100000   /* Pkt Rej. Enable on EMAC3(1) */
 #define SDR0_MFR_PKT_REJ_POL         0x00080000   /* Packet Reject Polarity      */
+#endif
+
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define SDR0_PFC1_EPS_ENCODE(n)		((((unsigned long)(n))&0x07)<<22)
+#define SDR0_PFC1_EPS_DECODE(n)		((((unsigned long)(n))>>22)&0x07)
+#define SDR0_PFC2_EPS_ENCODE(n)		((((unsigned long)(n))&0x07)<<29)
+#define SDR0_PFC2_EPS_DECODE(n)		((((unsigned long)(n))>>29)&0x07)
+#endif
+
+#define SDR0_MFR_ECS_MASK		0x10000000
+#define SDR0_MFR_ECS_INTERNAL		0x10000000
+
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define SDR0_SRST0        0x200
+#define SDR0_SRST0_BGO          0x80000000 /* PLB to OPB bridge */
+#define SDR0_SRST0_PLB4         0x40000000 /* PLB4 arbiter */
+#define SDR0_SRST0_EBC          0x20000000 /* External bus controller */
+#define SDR0_SRST0_OPB          0x10000000 /* OPB arbiter */
+#define SDR0_SRST0_UART0        0x08000000 /* Universal asynchronous receiver/transmitter 0 */
+#define SDR0_SRST0_UART1        0x04000000 /* Universal asynchronous receiver/transmitter 1 */
+#define SDR0_SRST0_IIC0         0x02000000 /* Inter integrated circuit 0 */
+#define SDR0_SRST0_USB2H        0x01000000 /* USB2.0 Host */
+#define SDR0_SRST0_GPIO         0x00800000 /* General purpose I/O */
+#define SDR0_SRST0_GPT          0x00400000 /* General purpose timer */
+#define SDR0_SRST0_DMC          0x00200000 /* DDR SDRAM memory controller */
+#define SDR0_SRST0_PCI          0x00100000 /* PCI */
+#define SDR0_SRST0_EMAC0        0x00080000 /* Ethernet media access controller 0 */
+#define SDR0_SRST0_EMAC1        0x00040000 /* Ethernet media access controller 1 */
+#define SDR0_SRST0_CPM0         0x00020000 /* Clock and power management */
+#define SDR0_SRST0_ZMII         0x00010000 /* ZMII bridge */
+#define SDR0_SRST0_UIC0         0x00008000 /* Universal interrupt controller 0 */
+#define SDR0_SRST0_UIC1         0x00004000 /* Universal interrupt controller 1 */
+#define SDR0_SRST0_IIC1         0x00002000 /* Inter integrated circuit 1 */
+#define SDR0_SRST0_SCP          0x00001000 /* Serial communications port */
+#define SDR0_SRST0_BGI          0x00000800 /* OPB to PLB bridge */
+#define SDR0_SRST0_DMA          0x00000400 /* Direct memory access controller */
+#define SDR0_SRST0_DMAC         0x00000200 /* DMA channel */
+#define SDR0_SRST0_MAL          0x00000100 /* Media access layer */
+#define SDR0_SRST0_USB2D        0x00000080 /* USB2.0 device */
+#define SDR0_SRST0_GPTR         0x00000040 /* General purpose timer */
+#define SDR0_SRST0_P4P3         0x00000010 /* PLB4 to PLB3 bridge */
+#define SDR0_SRST0_P3P4         0x00000008 /* PLB3 to PLB4 bridge */
+#define SDR0_SRST0_PLB3         0x00000004 /* PLB3 arbiter */
+#define SDR0_SRST0_UART2        0x00000002 /* Universal asynchronous receiver/transmitter 2 */
+#define SDR0_SRST0_UART3        0x00000001 /* Universal asynchronous receiver/transmitter 3 */
+
+#define SDR0_SRST1        0x201
+#define SDR0_SRST1_NDFC         0x80000000 /* Nand flash controller */
+#define SDR0_SRST1_OPBA1        0x40000000 /* OPB Arbiter attached to PLB4 */
+#define SDR0_SRST1_P4OPB0       0x20000000 /* PLB4 to OPB Bridge0 */
+#define SDR0_SRST1_PLB42OPB0    SDR0_SRST1_P4OPB0
+#define SDR0_SRST1_DMA4         0x10000000 /* DMA to PLB4 */
+#define SDR0_SRST1_DMA4CH       0x08000000 /* DMA Channel to PLB4 */
+#define SDR0_SRST1_OPBA2        0x04000000 /* OPB Arbiter attached to PLB4 USB 2.0 Host */
+#define SDR0_SRST1_OPB2PLB40    0x02000000 /* OPB to PLB4 Bridge attached to USB 2.0 Host */
+#define SDR0_SRST1_PLB42OPB1    0x01000000 /* PLB4 to OPB Bridge attached to USB 2.0 Host */
+#define SDR0_SRST1_CPM1         0x00800000 /* Clock and Power management 1 */
+#define SDR0_SRST1_UIC2         0x00400000 /* Universal Interrupt Controller 2 */
+#define SDR0_SRST1_CRYP0        0x00200000 /* Security Engine */
+#define SDR0_SRST1_USB20PHY     0x00100000 /* USB 2.0 Phy */
+#define SDR0_SRST1_USB2HUTMI    0x00080000 /* USB 2.0 Host UTMI Interface */
+#define SDR0_SRST1_USB2HPHY     0x00040000 /* USB 2.0 Host Phy Interface */
+#define SDR0_SRST1_SRAM0        0x00020000 /* Internal SRAM Controller */
+#define SDR0_SRST1_RGMII0       0x00010000 /* RGMII Bridge */
+#define SDR0_SRST1_ETHPLL       0x00008000 /* Ethernet PLL */
+#define SDR0_SRST1_FPU          0x00004000 /* Floating Point Unit */
+#define SDR0_SRST1_KASU0        0x00002000 /* Kasumi Engine */
+
+#else
 
 #define SDR0_SRST_BGO			0x80000000
 #define SDR0_SRST_PLB			0x40000000
@@ -2427,10 +2832,15 @@
 #define SDR0_SRST_EMAC3			0x00000008
 #define SDR0_SRST_RGMII			0x00000001
 
+#endif
+
 /*-----------------------------------------------------------------------------+
 |  Clocking
 +-----------------------------------------------------------------------------*/
-#if !defined (CONFIG_440GX) && !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
+#if !defined (CONFIG_440GX) && \
+    !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
+    !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
+    !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
 #define PLLSYS0_TUNE_MASK	0xffc00000	/* PLL TUNE bits	    */
 #define PLLSYS0_FB_DIV_MASK	0x003c0000	/* Feedback divisor	    */
 #define PLLSYS0_FWD_DIV_A_MASK	0x00038000	/* Forward divisor A	    */
@@ -2498,6 +2908,120 @@
 #define PLLSYS1_NTO1_MASK	0x00000001	/* CPU:PLB N-to-1 ratio */
 #endif /* CONFIG_440GX */
 
+#if defined (CONFIG_440EPX) || defined (CONFIG_440GRX)
+/*--------------------------------------*/
+#define CPR0_PLLC                   0x40
+#define   CPR0_PLLC_RST_MASK           0x80000000
+#define   CPR0_PLLC_RST_PLLLOCKED      0x00000000
+#define   CPR0_PLLC_RST_PLLRESET       0x80000000
+#define   CPR0_PLLC_ENG_MASK           0x40000000
+#define   CPR0_PLLC_ENG_DISABLE        0x00000000
+#define   CPR0_PLLC_ENG_ENABLE         0x40000000
+#define   CPR0_PLLC_ENG_ENCODE(n)      ((((unsigned long)(n))&0x01)<<30)
+#define   CPR0_PLLC_ENG_DECODE(n)      ((((unsigned long)(n))>>30)&0x01)
+#define   CPR0_PLLC_SRC_MASK           0x20000000
+#define   CPR0_PLLC_SRC_PLLOUTA        0x00000000
+#define   CPR0_PLLC_SRC_PLLOUTB        0x20000000
+#define   CPR0_PLLC_SRC_ENCODE(n)      ((((unsigned long)(n))&0x01)<<29)
+#define   CPR0_PLLC_SRC_DECODE(n)      ((((unsigned long)(n))>>29)&0x01)
+#define   CPR0_PLLC_SEL_MASK           0x07000000
+#define   CPR0_PLLC_SEL_PLL            0x00000000
+#define   CPR0_PLLC_SEL_CPU            0x01000000
+#define   CPR0_PLLC_SEL_PER            0x05000000
+#define   CPR0_PLLC_SEL_ENCODE(n)      ((((unsigned long)(n))&0x07)<<24)
+#define   CPR0_PLLC_SEL_DECODE(n)      ((((unsigned long)(n))>>24)&0x07)
+#define   CPR0_PLLC_TUNE_MASK          0x000003FF
+#define   CPR0_PLLC_TUNE_ENCODE(n)     ((((unsigned long)(n))&0x3FF)<<0)
+#define   CPR0_PLLC_TUNE_DECODE(n)     ((((unsigned long)(n))>>0)&0x3FF)
+/*--------------------------------------*/
+#define CPR0_PLLD                   0x60
+#define   CPR0_PLLD_FBDV_MASK          0x1F000000
+#define   CPR0_PLLD_FBDV_ENCODE(n)     ((((unsigned long)(n))&0x1F)<<24)
+#define   CPR0_PLLD_FBDV_DECODE(n)     ((((((unsigned long)(n))>>24)-1)&0x1F)+1)
+#define   CPR0_PLLD_FWDVA_MASK         0x000F0000
+#define   CPR0_PLLD_FWDVA_ENCODE(n)    ((((unsigned long)(n))&0x0F)<<16)
+#define   CPR0_PLLD_FWDVA_DECODE(n)    ((((((unsigned long)(n))>>16)-1)&0x0F)+1)
+#define   CPR0_PLLD_FWDVB_MASK         0x00000700
+#define   CPR0_PLLD_FWDVB_ENCODE(n)    ((((unsigned long)(n))&0x07)<<8)
+#define   CPR0_PLLD_FWDVB_DECODE(n)    ((((((unsigned long)(n))>>8)-1)&0x07)+1)
+#define   CPR0_PLLD_LFBDV_MASK         0x0000003F
+#define   CPR0_PLLD_LFBDV_ENCODE(n)    ((((unsigned long)(n))&0x3F)<<0)
+#define   CPR0_PLLD_LFBDV_DECODE(n)    ((((((unsigned long)(n))>>0)-1)&0x3F)+1)
+/*--------------------------------------*/
+#define CPR0_PRIMAD                 0x80
+#define   CPR0_PRIMAD_PRADV0_MASK      0x07000000
+#define   CPR0_PRIMAD_PRADV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
+#define   CPR0_PRIMAD_PRADV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
+/*--------------------------------------*/
+#define CPR0_PRIMBD                 0xA0
+#define   CPR0_PRIMBD_PRBDV0_MASK      0x07000000
+#define   CPR0_PRIMBD_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
+#define   CPR0_PRIMBD_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
+/*--------------------------------------*/
+#if 0
+#define CPR0_CPM0_ER                0xB0    /* CPM Enable Register */
+#define CPR0_CPM0_FR                0xB1    /* CPM Force Register */
+#define CPR0_CPM0_SR                0xB2    /* CPM Status Register */
+#define CPR0_CPM0_IIC0               0x80000000    /* Inter-Intergrated Circuit0 */
+#define CPR0_CPM0_IIC1               0x40000000    /* Inter-Intergrated Circuit1 */
+#define CPR0_CPM0_PCI                0x20000000    /* Peripheral Component Interconnect */
+#define CPR0_CPM0_USB1H              0x08000000    /* USB1.1 Host */
+#define CPR0_CPM0_FPU                0x04000000    /* PPC440 FPU */
+#define CPR0_CPM0_CPU                0x02000000    /* PPC440x5 Processor Core */
+#define CPR0_CPM0_DMA                0x01000000    /* Direct Memory Access Controller */
+#define CPR0_CPM0_BGO                0x00800000    /* PLB to OPB Bridge */
+#define CPR0_CPM0_BGI                0x00400000    /* OPB to PLB Bridge */
+#define CPR0_CPM0_EBC                0x00200000    /* External Bus Controller */
+#define CPR0_CPM0_NDFC               0x00100000    /* Nand Flash Controller */
+#define CPR0_CPM0_MADMAL             0x00080000    /* DDR SDRAM Controller or MADMAL ??? */
+#define CPR0_CPM0_DMC                0x00080000    /* DDR SDRAM Controller or MADMAL ??? */
+#define CPR0_CPM0_PLB4               0x00040000    /* PLB4 Arbiter */
+#define CPR0_CPM0_PLB4x3x            0x00020000    /* PLB4 to PLB3 */
+#define CPR0_CPM0_PLB3x4x            0x00010000    /* PLB3 to PLB4 */
+#define CPR0_CPM0_PLB3               0x00008000    /* PLB3 Arbiter */
+#define CPR0_CPM0_PPM                0x00002000    /* PLB Performance Monitor */
+#define CPR0_CPM0_UIC1               0x00001000    /* Universal Interrupt Controller 1 */
+#define CPR0_CPM0_GPIO               0x00000800    /* General Purpose IO */
+#define CPR0_CPM0_GPT                0x00000400    /* General Purpose Timer */
+#define CPR0_CPM0_UART0              0x00000200    /* Universal Asynchronous Rcver/Xmitter 0 */
+#define CPR0_CPM0_UART1              0x00000100    /* Universal Asynchronous Rcver/Xmitter 1 */
+#define CPR0_CPM0_UIC0               0x00000080    /* Universal Interrupt Controller 0 */
+#define CPR0_CPM0_TMRCLK             0x00000040    /* CPU Timer */
+#define CPR0_CPM0_EMC0               0x00000020    /* Ethernet 0 */
+#define CPR0_CPM0_EMC1               0x00000010    /* Ethernet 1 */
+#define CPR0_CPM0_UART2              0x00000008    /* Universal Asynchronous Rcver/Xmitter 2 */
+#define CPR0_CPM0_UART3              0x00000004    /* Universal Asynchronous Rcver/Xmitter 3 */
+#define CPR0_CPM0_USB2D              0x00000002    /* USB2.0 Device */
+#define CPR0_CPM0_USB2H              0x00000001    /* USB2.0 Host */
+#endif
+/*--------------------------------------*/
+#define CPR0_OPBD                   0xC0
+#define   CPR0_OPBD_OPBDV0_MASK        0x03000000
+#define   CPR0_OPBD_OPBDV0_ENCODE(n)   ((((unsigned long)(n))&0x03)<<24)
+#define   CPR0_OPBD_OPBDV0_DECODE(n)   ((((((unsigned long)(n))>>24)-1)&0x03)+1)
+/*--------------------------------------*/
+#define CPR0_PERD                   0xE0
+#define   CPR0_PERD_PERDV0_MASK        0x07000000
+#define   CPR0_PERD_PERDV0_ENCODE(n)   ((((unsigned long)(n))&0x07)<<24)
+#define   CPR0_PERD_PERDV0_DECODE(n)   ((((((unsigned long)(n))>>24)-1)&0x07)+1)
+/*--------------------------------------*/
+#define CPR0_MALD                  0x100
+#define   CPR0_MALD_MALDV0_MASK        0x03000000
+#define   CPR0_MALD_MALDV0_ENCODE(n)   ((((unsigned long)(n))&0x03)<<24)
+#define   CPR0_MALD_MALDV0_DECODE(n)   ((((((unsigned long)(n))>>24)-1)&0x03)+1)
+/*--------------------------------------*/
+#define CPR0_SPCID                 0x120
+#define   CPR0_SPCID_SPCIDV0_MASK      0x03000000
+#define   CPR0_SPCID_SPCIDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
+#define   CPR0_SPCID_SPCIDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
+/*--------------------------------------*/
+#define CPR0_ICFG                  0x140
+#define   CPR0_ICFG_RLI_MASK           0x80000000
+#define   CPR0_ICFG_RLI_RESETCPR       0x00000000
+#define   CPR0_ICFG_RLI_PRESERVECPR    0x80000000
+#define   CPR0_ICFG_ICS_MASK           0x00000007
+#endif /* defined (CONFIG_440EPX) || defined (CONFIG_440GRX) */
+
 /*-----------------------------------------------------------------------------
 | IIC Register Offsets
 '----------------------------------------------------------------------------*/
@@ -2539,7 +3063,8 @@
 #define PCIX0_CFGBASE		(CFG_PCI_BASE + 0x0ec80000)
 #define PCIX0_IOBASE		(CFG_PCI_BASE + 0x08000000)
 
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 
 /* PCI Local Configuration Registers
    --------------------------------- */
@@ -2625,6 +3150,33 @@
 
 #endif /* !defined(CONFIG_440EP) !defined(CONFIG_440GR) */
 
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+
+/* USB2.0 Device */
+#define USB2D0_BASE         CFG_USB2D0_BASE
+
+#define USB2D0_INTRIN       (USB2D0_BASE + 0x00000000)
+
+#define USB2D0_INTRIN       (USB2D0_BASE + 0x00000000) /* Interrupt register for Endpoint 0 plus IN Endpoints 1 to 3 */
+#define USB2D0_POWER        (USB2D0_BASE + 0x00000000) /* Power management register */
+#define USB2D0_FADDR        (USB2D0_BASE + 0x00000000) /* Function address register */
+#define USB2D0_INTRINE      (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRIN */
+#define USB2D0_INTROUT      (USB2D0_BASE + 0x00000000) /* Interrupt register for OUT Endpoints 1 to 3 */
+#define USB2D0_INTRUSBE     (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRUSB */
+#define USB2D0_INTRUSB      (USB2D0_BASE + 0x00000000) /* Interrupt register for common USB interrupts */
+#define USB2D0_INTROUTE     (USB2D0_BASE + 0x00000000) /* Interrupt enable register for IntrOut */
+#define USB2D0_TSTMODE      (USB2D0_BASE + 0x00000000) /* Enables the USB 2.0 test modes */
+#define USB2D0_INDEX        (USB2D0_BASE + 0x00000000) /* Index register for selecting the Endpoint status/control registers */
+#define USB2D0_FRAME        (USB2D0_BASE + 0x00000000) /* Frame number */
+#define USB2D0_INCSR0       (USB2D0_BASE + 0x00000000) /* Control Status register for Endpoint 0. (Index register set to select Endpoint 0) */
+#define USB2D0_INCSR        (USB2D0_BASE + 0x00000000) /* Control Status register for IN Endpoint. (Index register set to select Endpoints 13) */
+#define USB2D0_INMAXP       (USB2D0_BASE + 0x00000000) /* Maximum packet size for IN Endpoint. (Index register set to select Endpoints 13) */
+#define USB2D0_OUTCSR       (USB2D0_BASE + 0x00000000) /* Control Status register for OUT Endpoint. (Index register set to select Endpoints 13) */
+#define USB2D0_OUTMAXP      (USB2D0_BASE + 0x00000000) /* Maximum packet size for OUT Endpoint. (Index register set to select Endpoints 13) */
+#define USB2D0_OUTCOUNT0    (USB2D0_BASE + 0x00000000) /* Number of received bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) */
+#define USB2D0_OUTCOUNT     (USB2D0_BASE + 0x00000000) /* Number of bytes in OUT Endpoint FIFO. (Index register set to select Endpoints 13) */
+#endif
+
 /******************************************************************************
  * GPIO macro register defines
  ******************************************************************************/
@@ -2640,7 +3192,8 @@
 #define GPIO0_IR               (GPIO0_BASE+0x1C)
 #endif /* CONFIG_440GP */
 
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define GPIO0_BASE             (CFG_PERIPHERAL_BASE+0x00000B00)
 #define GPIO1_BASE             (CFG_PERIPHERAL_BASE+0x00000C00)
 
diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h
index ec2e3629bb..43c5ca451e 100644
--- a/include/ppc4xx_enet.h
+++ b/include/ppc4xx_enet.h
@@ -145,12 +145,14 @@ typedef struct emac_4xx_hw_st {
 #define EMAC_STACR_OC_MASK	(0x00000000)
 #endif
 
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define SDR0_PFC1_EM_1000	(0x00200000)
 #endif
 
 /*ZMII Bridge Register addresses */
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define ZMII_BASE			(CFG_PERIPHERAL_BASE + 0x0D00)
 #else
 #define ZMII_BASE			(CFG_PERIPHERAL_BASE + 0x0780)
@@ -163,6 +165,7 @@ typedef struct emac_4xx_hw_st {
 #define ZMII_MDI0			0x80000000
 
 /* ZMII FER Register Bit Definitions */
+#define ZMII_FER_DIS		(0x0)
 #define ZMII_FER_MDI		(0x8)
 #define ZMII_FER_SMII		(0x4)
 #define ZMII_FER_RMII		(0x2)
@@ -197,7 +200,11 @@ typedef struct emac_4xx_hw_st {
 #define ZMII_SMIISR_V(__x)	((3 - __x) * 8)
 
 /* RGMII Register Addresses */
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define RGMII_BASE		(CFG_PERIPHERAL_BASE + 0x1000)
+#else
 #define RGMII_BASE		(CFG_PERIPHERAL_BASE + 0x0790)
+#endif
 #define RGMII_FER		(RGMII_BASE + 0x00)
 #define RGMII_SSR		(RGMII_BASE + 0x04)
 
@@ -216,7 +223,11 @@ typedef struct emac_4xx_hw_st {
 #define RGMII_SSR_SP_100MBPS	(0x02)
 #define RGMII_SSR_SP_1000MBPS	(0x04)
 
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define RGMII_SSR_V(__x)	((__x) * 8)
+#else
 #define RGMII_SSR_V(__x)	((__x -2) * 8)
+#endif
 
 
 /*---------------------------------------------------------------------------+
@@ -286,7 +297,8 @@ typedef struct emac_4xx_hw_st {
 
 /* Ethernet MAC Regsiter Addresses */
 #if defined(CONFIG_440)
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define EMAC_BASE			    (CFG_PERIPHERAL_BASE + 0x0E00)
 #else
 #define EMAC_BASE			    (CFG_PERIPHERAL_BASE + 0x0800)
@@ -332,7 +344,9 @@ typedef struct emac_4xx_hw_st {
 #define EMAC_M0_WKE			    (0x04000000)
 
 /* on 440GX EMAC_MR1 has a different layout! */
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 /* MODE Reg 1 */
 #define EMAC_M1_FDE		(0x80000000)
 #define EMAC_M1_ILE		(0x40000000)
diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl
index 72d690ef0f..3e47e82aba 100644
--- a/include/ppc_asm.tmpl
+++ b/include/ppc_asm.tmpl
@@ -312,7 +312,7 @@ label:                                                  \
 	lwz     r3,GOT(transfer_to_handler);            \
 	mtlr    r3;                                     \
 	addi    r3,r1,STACK_FRAME_OVERHEAD;             \
-	li      r20,MSR_KERNEL;                         \
+	li      r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \
 	rlwimi  r20,r23,0,25,25;                        \
 	blrl    ;                                       \
 .L_ ## label :                                          \
diff --git a/include/serial.h b/include/serial.h
index 8c7b1c26c1..48800595d7 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -26,6 +26,13 @@ extern struct serial_device * default_serial_console (void);
    || defined(CONFIG_405EP) || defined(CONFIG_MPC5xxx)
 extern struct serial_device serial0_device;
 extern struct serial_device serial1_device;
+#if defined(CFG_NS16550_SERIAL)
+extern struct serial_device eserial1_device;
+extern struct serial_device eserial2_device;
+extern struct serial_device eserial3_device;
+extern struct serial_device eserial4_device;
+#endif /* CFG_NS16550_SERIAL */
+
 #endif
 
 
diff --git a/include/status_led.h b/include/status_led.h
index a56883b9a5..db4c60fe3f 100644
--- a/include/status_led.h
+++ b/include/status_led.h
@@ -346,6 +346,15 @@ void status_led_set  (int led, int state);
 #elif defined(CONFIG_NIOS2)
 /* XXX empty just to avoid the error */
 /************************************************************************/
+#elif defined(CONFIG_V38B)
+
+# define STATUS_LED_BIT		0x0010			/* Timer7 GPIO */
+# define STATUS_LED_PERIOD	(CFG_HZ / 2)
+# define STATUS_LED_STATE	STATUS_LED_BLINKING
+
+# define STATUS_LED_ACTIVE	0		/* LED on for bit == 0 */
+# define STATUS_LED_BOOT	0		/* LED 0 used for boot status */
+
 #else
 # error Status LED configuration missing
 #endif