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| author | Stefan Roese <sr@denx.de> | 2007-07-04 10:06:30 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-07-04 10:06:30 +0200 |
| commit | 04e6c38b766eaa2f3287561563c9e215e0c3a0d4 (patch) | |
| tree | fe6add157fff96f242e74810b3b79aff07625d73 /include | |
| parent | 98c440bee623ecdd5322852732b883e696fb2140 (diff) | |
| download | u-boot-04e6c38b766eaa2f3287561563c9e215e0c3a0d4.tar.gz u-boot-04e6c38b766eaa2f3287561563c9e215e0c3a0d4.tar.xz u-boot-04e6c38b766eaa2f3287561563c9e215e0c3a0d4.zip | |
ppc4xx: Update lwmon5 board
- Add optional ECC generation routine to preserve existing
RAM values. This is needed for the Linux log-buffer support
- Add optional DDR2 setup with CL=4
- GPIO50 not used anymore
- Lime register setup added
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/lwmon5.h | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index c6f67fee44..1d87c73c71 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -327,12 +327,24 @@ #define CFG_EBC_CFG 0xb8400000 /*----------------------------------------------------------------------- + * Graphics (Fujitsu Lime) + *----------------------------------------------------------------------*/ +/* SDRAM Clock frequency adjustment register */ +#define CFG_LIME_SDRAM_CLOCK 0xC1FC0000 +/* Lime Clock frequency is to set 133MHz */ +#define CFG_LIME_CLOCK_133MHZ 0x10000 + +/* SDRAM Parameter register */ +#define CFG_LIME_MMR 0xC1FCFFFC +/* SDRAM parameter value */ +#define CFG_LIME_MMR_VALUE 0x414FB7F2 + +/*----------------------------------------------------------------------- * GPIO Setup *----------------------------------------------------------------------*/ #define CFG_GPIO_PHY1_RST 12 #define CFG_GPIO_FLASH_WP 14 #define CFG_GPIO_PHY0_RST 22 -#define CFG_GPIO_HUB_RST 50 #define CFG_GPIO_WATCHDOG 58 #define CFG_GPIO_LIME_S 59 #define CFG_GPIO_LIME_RST 60 @@ -396,7 +408,7 @@ {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \ {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \ {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \ {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \ {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \ {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO53 Unselect via TraceSelect Bit */ \ |