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| author | Stefan Roese <sr@denx.de> | 2005-11-22 13:20:42 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2005-11-22 13:20:42 +0100 |
| commit | 5568e613ee38d4bb5dd601cdb2f74ed0d7de9902 (patch) | |
| tree | c89680cfc4931d8e0e3173c27959d678c3cbb44e /include/ppc440.h | |
| parent | fe126d8b34d2e7c3c2dc1d4e61086018e016768c (diff) | |
| download | u-boot-5568e613ee38d4bb5dd601cdb2f74ed0d7de9902.tar.gz u-boot-5568e613ee38d4bb5dd601cdb2f74ed0d7de9902.tar.xz u-boot-5568e613ee38d4bb5dd601cdb2f74ed0d7de9902.zip | |
Add support for Prodrive P3P440 board:
- Added onboard PPC440 DDR autodetection in cpu/ppc/sdram.c
- CFG_FLASH_QUIET_TEST added to use the common CFI driver
for bank autodetection
Patch by Stefan Roese, 22 Nov 2005
Diffstat (limited to 'include/ppc440.h')
| -rw-r--r-- | include/ppc440.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/include/ppc440.h b/include/ppc440.h index c66e059e34..41db16ff2f 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -547,6 +547,8 @@ #define cpc0_strp2 (CNTRL_DCR_BASE+0x36) /* Power-on config reg 2 (RO) */ #define cpc0_strp3 (CNTRL_DCR_BASE+0x37) /* Power-on config reg 3 (RO) */ +#define cpc0_gpio (CNTRL_DCR_BASE+0x38) /* GPIO config reg (440GP) */ + #define cntrl0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */ #define cntrl1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */ @@ -1392,6 +1394,15 @@ /****************************************************************************** * GPIO macro register defines ******************************************************************************/ +#if defined(CONFIG_440GP) +#define GPIO_BASE0 (CFG_PERIPHERAL_BASE+0x00000700) + +#define GPIO0_OR (GPIO_BASE0+0x0) +#define GPIO0_TCR (GPIO_BASE0+0x4) +#define GPIO0_ODR (GPIO_BASE0+0x18) +#define GPIO0_IR (GPIO_BASE0+0x1C) +#endif /* CONFIG_440GP */ + #if defined(CONFIG_440EP) || defined(CONFIG_440GR) #define GPIO_BASE0 (CFG_PERIPHERAL_BASE+0x00000B00) #define GPIO_BASE1 (CFG_PERIPHERAL_BASE+0x00000C00) |