* The PS/2 mux on the BMS2003 board needs 450 ms after power on

before we can access it; add delay in case we are faster (with no CF card inserted) * Cleanup of some init functions * Make sure SCC Ethernet is always stopped by the time we boot Linux to avoid Linux crashes by early packets coming in. * Accelerate flash accesses on LWMON board by using buffered writes
author: wdenk <wdenk> 2004-01-20 23:12:12 +0000
committer: wdenk <wdenk> 2004-01-20 23:12:12 +0000
commit: c837dcb1a316745092567bfe4fb266d0941884ff (patch)
tree: 8b275e8c982d1b0a411ff33c08c86cd3d343eed6 /include/configs
parent: b0aef11c9f1f98d018adaa484f1e048fa626801e (diff)
download: u-boot-c837dcb1a316745092567bfe4fb266d0941884ff.tar.gz
u-boot-c837dcb1a316745092567bfe4fb266d0941884ff.tar.xz
u-boot-c837dcb1a316745092567bfe4fb266d0941884ff.zip
61 files changed, 2165 insertions, 2148 deletions
diff --git a/include/configs/ADCIOP.h b/include/configs/ADCIOP.h
index 255942aabd..5a62139f9f 100644
--- a/include/configs/ADCIOP.h
+++ b/include/configs/ADCIOP.h
@@ -12,7 +12,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -34,27 +34,27 @@
  */
 
 #define CONFIG_IOP480		1	/* This is a IOP480 CPU		*/
-#define CONFIG_ADCIOP		1	/* ...on a ADCIOP board 	*/
+#define CONFIG_ADCIOP		1	/* ...on a ADCIOP board		*/
 
-#define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
 
-#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+#define CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
 
-#define CONFIG_CPUCLOCK	        66
-#define CONFIG_BUSCLOCK	        (CONFIG_CPUCLOCK)
+#define CONFIG_CPUCLOCK		66
+#define CONFIG_BUSCLOCK		(CONFIG_CPUCLOCK)
 
-#define CONFIG_BAUDRATE	        9600
+#define CONFIG_BAUDRATE		9600
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
 #define CONFIG_BOOTCOMMAND	"bootm ffc00000" /* autoboot command	*/
 
-#undef  CONFIG_BOOTARGS
+#undef	CONFIG_BOOTARGS
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #undef CONFIG_WATCHDOG			/* watchdog disabled		*/
 
-#define	CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
 
 #define CONFIG_IPADDR		10.0.18.222
 #define CONFIG_SERVERIP		10.0.18.190
@@ -62,7 +62,7 @@
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_DHCP	| \
 				CFG_CMD_IRQ	| \
-				CFG_CMD_ELF     | \
+				CFG_CMD_ELF	| \
 				CFG_CMD_ASKENV	)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
@@ -74,33 +74,33 @@
 #define CFG_LONGHELP			/* undef to save memory		*/
 #define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 #define CFG_MAXARGS	16		/* max number of command args	*/
 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
 #define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE      \
+#define CFG_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 }
 
-#define CFG_LOAD_ADDR	0x100000	/* default load address	*/
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	0x00df0000 /* inside of SDRAM                   */
+#define CFG_INIT_RAM_ADDR	0x00df0000 /* inside of SDRAM			*/
 #define CFG_INIT_RAM_END	0x0f00	/* End of used area in RAM	       */
 #define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
@@ -122,28 +122,28 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 #define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256     /* max number of sectors on one chip	*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE     unsigned char   /* flash word size (width)      */
-#define CFG_FLASH_ADDR0         0x0AA9  /* 1st address for flash config cycles  */
-#define CFG_FLASH_ADDR1         0x0556  /* 2nd address for flash config cycles  */
+#define CFG_FLASH_WORD_SIZE	unsigned char	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x0AA9	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x0556	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0         0x0002  /* 0 is standard                        */
-#define CFG_FLASH_READ1         0x0000  /* 1 is standard                        */
-#define CFG_FLASH_READ2         0x0004  /* 2 is standard                        */
+#define CFG_FLASH_READ0		0x0002	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0000	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0004	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #if 1 /* Use NVRAM for environment variables */
 /*-----------------------------------------------------------------------
@@ -159,8 +159,8 @@
 
 #else /* Use FLASH for environment variables */
 
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_OFFSET		0x00010000	/* Offset of Environment Sector	*/
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET		0x00010000	/* Offset of Environment Sector */
 #define CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
 
 #define CFG_ENV_SECT_SIZE	0x8000	/* see README - env sector total size	*/
@@ -173,12 +173,12 @@
 #define CONFIG_PCI			/* include pci support			*/
 #undef CONFIG_PCI_PNP
 
-#define CONFIG_NET_MULTI		/* Multi ethernet cards support 	*/
+#define CONFIG_NET_MULTI		/* Multi ethernet cards support		*/
 
 #define CONFIG_TULIP
 
-#define CFG_ETH_DEV_FN       0x0000
-#define CFG_ETH_IOBASE       0x0fff0000
+#define CFG_ETH_DEV_FN	     0x0000
+#define CFG_ETH_IOBASE	     0x0fff0000
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
diff --git a/include/configs/AR405.h b/include/configs/AR405.h
index 847edbc623..1fae9163d1 100644
--- a/include/configs/AR405.h
+++ b/include/configs/AR405.h
@@ -34,12 +34,12 @@
  */
 
 #define CONFIG_405GP		1	/* This is a PPC405GP CPU	*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
-#define CONFIG_AR405		1	/* ...on a AR405 board	        */
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_AR405		1	/* ...on a AR405 board		*/
 
-#define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
 
-#define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
+#define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll	*/
 
 #define CONFIG_BAUDRATE		9600
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
@@ -51,8 +51,8 @@
 #endif
 
 #if 0
-#define CONFIG_BOOTARGS		"root=/dev/nfs "                        \
-    "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 "        \
+#define CONFIG_BOOTARGS		"root=/dev/nfs "			\
+    "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 "	\
     "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4"
 #else
 #define CONFIG_BOOTARGS		"root=/dev/hda1 "			\
@@ -64,7 +64,7 @@
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_MII		1	/* MII PHY management		*/
-#define	CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
 
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_PCI	| \
@@ -76,7 +76,7 @@
 
 #undef CONFIG_WATCHDOG			/* watchdog disabled		*/
 
-#define	CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 
 /*
  * Miscellaneous configurable options
@@ -84,30 +84,30 @@
 #define CFG_LONGHELP			/* undef to save memory		*/
 #define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 #define CFG_MAXARGS	16		/* max number of command args	*/
 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
 #define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define CFG_EXT_SERIAL_CLOCK    14745600 /* use external serial clock   */
+#define CFG_EXT_SERIAL_CLOCK	14745600 /* use external serial clock	*/
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE      \
+#define CFG_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
 #define CFG_LOAD_ADDR	0x100000	/* default load address */
 #define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
@@ -115,27 +115,27 @@
  * PCI stuff
  *-----------------------------------------------------------------------
  */
-#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
 
-#define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function     */
-#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-					/* resource configuration       */
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
 
-#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
 
-#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
+#define CONFIG_PCI_BOOTDELAY	0	/* enable pci bootdelay variable*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0403  /* PCI Device ID: ARISTO405     */
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0xfff00000      /* point to flash               */
-#define CFG_PCI_PTM2MS  0xfff00001      /* 1MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0403	/* PCI Device ID: ARISTO405	*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0xfff00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xfff00001	/* 1MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
@@ -163,24 +163,24 @@
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
-#define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
-#define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
-#define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
-#define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_OFFSET		0x00010000	/* Offset of Environment Sector	*/
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET		0x00010000	/* Offset of Environment Sector */
 #define CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
 
-#define CFG_ENV_SECT_SIZE	0x10000	/* see README - env sector total size	*/
+#define CFG_ENV_SECT_SIZE	0x10000 /* see README - env sector total size	*/
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
@@ -204,40 +204,40 @@
  * External Bus Controller (EBC) Setup
  */
 
-/* Memory Bank 0 (Flash Bank 0) initialization                                  */
-#define CFG_EBC_PB0AP           0x92015480
-#define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CFG_EBC_PB0AP		0x92015480
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
-/* Memory Bank 1 (CAN0, 1, 2, 3) initialization                                 */
-#define CFG_EBC_PB1AP           0x01000380  /* enable Ready, BEM=0              */
-#define CFG_EBC_PB1CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+/* Memory Bank 1 (CAN0, 1, 2, 3) initialization					*/
+#define CFG_EBC_PB1AP		0x01000380  /* enable Ready, BEM=0		*/
+#define CFG_EBC_PB1CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 2 (Expension Bus) initialization                                 */
-#define CFG_EBC_PB2AP           0x01000280  /* disable Ready, BEM=0             */
-#define CFG_EBC_PB2CR           0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit  */
+/* Memory Bank 2 (Expension Bus) initialization					*/
+#define CFG_EBC_PB2AP		0x01000280  /* disable Ready, BEM=0		*/
+#define CFG_EBC_PB2CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 3 (16552) initialization                                         */
-#define CFG_EBC_PB3AP           0x01000380  /* enable Ready, BEM=0              */
-#define CFG_EBC_PB3CR           0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit  */
+/* Memory Bank 3 (16552) initialization						*/
+#define CFG_EBC_PB3AP		0x01000380  /* enable Ready, BEM=0		*/
+#define CFG_EBC_PB3CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 4 (FPGA regs) initialization                                     */
-#define CFG_EBC_PB4AP           0x01005380  /* enable Ready, BEM=0              */
-#define CFG_EBC_PB4CR           0xF031C000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=32bit */
+/* Memory Bank 4 (FPGA regs) initialization					*/
+#define CFG_EBC_PB4AP		0x01005380  /* enable Ready, BEM=0		*/
+#define CFG_EBC_PB4CR		0xF031C000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=32bit */
 
-/* Memory Bank 5 (Flash Bank 1/DUMMY) initialization                            */
-#define CFG_EBC_PB5AP           0x92015480
-#define CFG_EBC_PB5CR           0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+/* Memory Bank 5 (Flash Bank 1/DUMMY) initialization				*/
+#define CFG_EBC_PB5AP		0x92015480
+#define CFG_EBC_PB5CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
-#define CFG_INIT_DCACHE_CS      7       /* use cs # 7 for data cache memory    */
+#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
 
-#define CFG_INIT_RAM_ADDR       0x40000000  /* use data cache                  */
-#define CFG_INIT_RAM_END        0x2000  /* End of used area in RAM             */
+#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
+#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
 /*
  * Internal Definitions
diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h
index 3868997208..7ed01d16de 100644
--- a/include/configs/ASH405.h
+++ b/include/configs/ASH405.h
@@ -34,13 +34,13 @@
  */
 
 #define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
-#define CONFIG_ASH405		1	/* ...on a ASH405 board 	*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_ASH405		1	/* ...on a ASH405 board		*/
 
-#define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */
-#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
 
-#define CONFIG_SYS_CLK_FREQ     33333334 /* external frequency to pll   */
+#define CONFIG_SYS_CLK_FREQ	33333334 /* external frequency to pll	*/
 
 #define CONFIG_BAUDRATE		9600
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
@@ -60,7 +60,7 @@
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_MII		1	/* MII PHY management		*/
-#define	CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
 
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_DHCP	| \
@@ -71,17 +71,17 @@
 				CFG_CMD_I2C	| \
 				CFG_CMD_MII	| \
 				CFG_CMD_PING	| \
-				CFG_CMD_EEPROM  )
+				CFG_CMD_EEPROM	)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
-#undef  CONFIG_WATCHDOG			/* watchdog disabled		*/
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
-#define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible*/
-#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address         */
+#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
+#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
 
-#define	CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 
 /*
  * Miscellaneous configurable options
@@ -91,45 +91,45 @@
 
 #undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
 #ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CFG_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 #define CFG_MAXARGS	16		/* max number of command args	*/
 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
 
-#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
 #define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
-#define CFG_BASE_BAUD       691200
-#undef  CONFIG_UART1_CONSOLE            /* define for uart1 as console  */
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD	    691200
+#undef	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE      \
+#define CFG_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
 #define CFG_LOAD_ADDR	0x100000	/* default load address */
 #define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
-#define CONFIG_VERSION_VARIABLE	1       /* include version env variable */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
-#define CFG_RX_ETH_BUFFER	16      /* use 16 rx buffer on 405 emac */
+#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
 
 /*-----------------------------------------------------------------------
  * NAND-FLASH stuff
@@ -142,14 +142,14 @@
 #define ADDR_PAGE 2
 #define ADDR_COLUMN_PAGE 3
 
-#define NAND_ChipID_UNKNOWN 	0x00
+#define NAND_ChipID_UNKNOWN	0x00
 #define NAND_MAX_FLOORS 1
 #define NAND_MAX_CHIPS 1
 
-#define CFG_NAND_CE  (0x80000000 >> 1)  /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2)  /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3)  /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4)  /* our RDY is GPIO4 */
+#define CFG_NAND_CE  (0x80000000 >> 1)	/* our CE is GPIO1 */
+#define CFG_NAND_CLE (0x80000000 >> 2)	/* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3)	/* our ALE is GPIO3 */
+#define CFG_NAND_RDY (0x80000000 >> 4)	/* our RDY is GPIO4 */
 
 #define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
 #define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
@@ -168,26 +168,26 @@
  * PCI stuff
  *-----------------------------------------------------------------------
  */
-#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
-
-#define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_HOST	PCI_HOST_HOST   /* select pci host function     */
-#undef  CONFIG_PCI_PNP			/* do pci plug-and-play         */
-					/* resource configuration       */
-
-#undef  CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
-#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_HOST	/* select pci host function	*/
+#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
+#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
@@ -215,34 +215,34 @@
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
-#define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
-#define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
-#define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
-#define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS     1           /* ! second bank contains U-Boot */
+#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
 #endif
 
 /*-----------------------------------------------------------------------
  * Environment Variable setup
  */
-#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET          0x100   /* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE            0x700   /* 2048 bytes may be used for env vars*/
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
 				   /* total size of a CAT24WC16 is 2048 bytes */
 
 #define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		242		        /* NVRAM size		*/
+#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
 
 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC16) for environment
@@ -252,20 +252,20 @@
 #define CFG_I2C_SLAVE		0x7F
 
 #define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
 #define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
 #define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
-					/* last	4 bits of the address	*/
+					/* last 4 bits of the address	*/
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's    */
-					/* have only 8kB, 16kB is save here     */
+#define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's	*/
+					/* have only 8kB, 16kB is save here	*/
 #define CFG_CACHELINE_SIZE	32	/* ...			*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
@@ -283,49 +283,49 @@
  * External Bus Controller (EBC) Setup
  */
 
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
-#define CFG_EBC_PB0AP           0x92015480
-/*#define CFG_EBC_PB0AP           0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
-#define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CFG_EBC_PB0AP		0x92015480
+/*#define CFG_EBC_PB0AP		  0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
-/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization                      */
-#define CFG_EBC_PB1AP           0x92015480
-#define CFG_EBC_PB1CR           0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit  */
+/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
+#define CFG_EBC_PB1AP		0x92015480
+#define CFG_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization              */
-#define CFG_EBC_PB2AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
+#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization     */
-#define CFG_EBC_PB3AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR           0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization	*/
+#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 
-#define CAN_BA          0xF0000000          /* CAN Base Address                 */
-#define DUART0_BA       0xF0000400          /* DUART Base Address               */
-#define DUART1_BA       0xF0000408          /* DUART Base Address               */
-#define DUART2_BA       0xF0000410          /* DUART Base Address               */
-#define DUART3_BA       0xF0000418          /* DUART Base Address               */
-#define RTC_BA          0xF0000500          /* RTC Base Address                 */
-#define CFG_NAND_BASE   0xF4000000
+#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
+#define DUART0_BA	0xF0000400	    /* DUART Base Address		*/
+#define DUART1_BA	0xF0000408	    /* DUART Base Address		*/
+#define DUART2_BA	0xF0000410	    /* DUART Base Address		*/
+#define DUART3_BA	0xF0000418	    /* DUART Base Address		*/
+#define RTC_BA		0xF0000500	    /* RTC Base Address			*/
+#define CFG_NAND_BASE	0xF4000000
 
 /*-----------------------------------------------------------------------
  * FPGA stuff
  */
-#define CFG_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
-#define CFG_FPGA_MAX_SIZE       128*1024    /* 128kByte is enough for XC2S50E*/
+#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CFG_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/
 
 /* FPGA program pin configuration */
-#define CFG_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */
+#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
+#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM        1
+#define CFG_TEMP_STACK_OCM	  1
 
 /* On Chip Memory location */
 #define CFG_OCM_DATA_ADDR	0xF8000000
@@ -335,13 +335,13 @@
 
 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Definitions for GPIO setup (PPC405EP specific)
  *
- * GPIO0[0]     - External Bus Controller BLAST output
- * GPIO0[1-9]   - Instruction trace outputs -> GPIO
+ * GPIO0[0]	- External Bus Controller BLAST output
+ * GPIO0[1-9]	- Instruction trace outputs -> GPIO
  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
@@ -349,15 +349,15 @@
  * GPIO0[28-29] - UART1 data signal input/output
  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
  */
-#define CFG_GPIO0_OSRH          0x40000550
-#define CFG_GPIO0_OSRL          0x00000110
-#define CFG_GPIO0_ISR1H         0x00000000
-#define CFG_GPIO0_ISR1L         0x15555445
-#define CFG_GPIO0_TSRH          0x00000000
-#define CFG_GPIO0_TSRL          0x00000000
-#define CFG_GPIO0_TCR           0xF7FE0014
+#define CFG_GPIO0_OSRH		0x40000550
+#define CFG_GPIO0_OSRL		0x00000110
+#define CFG_GPIO0_ISR1H		0x00000000
+#define CFG_GPIO0_ISR1L		0x15555445
+#define CFG_GPIO0_TSRH		0x00000000
+#define CFG_GPIO0_TSRL		0x00000000
+#define CFG_GPIO0_TCR		0xF7FE0014
 
-#define CFG_DUART_RST           (0x80000000 >> 14)
+#define CFG_DUART_RST		(0x80000000 >> 14)
 
 /*
  * Internal Definitions
@@ -372,16 +372,16 @@
  * This value will be set if iic boot eprom is disabled.
  */
 #if 0
-#define PLLMR0_DEFAULT   PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT   PLLMR1_266_133_66_33
+#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
 #endif
 #if 1
-#define PLLMR0_DEFAULT   PLLMR0_200_100_50_33
-#define PLLMR1_DEFAULT   PLLMR1_200_100_50_33
+#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
+#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
 #endif
 #if 0
-#define PLLMR0_DEFAULT   PLLMR0_133_66_66_33
-#define PLLMR1_DEFAULT   PLLMR1_133_66_66_33
+#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
 #endif
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/AmigaOneG3SE.h b/include/configs/AmigaOneG3SE.h
index 99b42e9a6d..ea50f41504 100644
--- a/include/configs/AmigaOneG3SE.h
+++ b/include/configs/AmigaOneG3SE.h
@@ -43,7 +43,7 @@
 
 #define CONFIG_AMIGAONEG3SE	1
 
-#define CONFIG_BOARD_PRE_INIT	1
+#define CONFIG_BOARD_EARLY_INIT_F 1
 #define CONFIG_MISC_INIT_R	1
 
 #define CONFIG_VERY_BIG_RAM	1
diff --git a/include/configs/BMW.h b/include/configs/BMW.h
index edfd68fcff..050054d274 100644
--- a/include/configs/BMW.h
+++ b/include/configs/BMW.h
@@ -45,7 +45,9 @@
 #define CONFIG_MPC8245		1
 #define CONFIG_BMW		1
 
-#define CONFIG_BCM570x		1 /* Use Broadcom BCM570x Ethernet Driver */
+#define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()			*/
+
+#define CONFIG_BCM570x		1	/* Use Broadcom BCM570x Ethernet Driver */
 #define	CONFIG_TIGON3		1
 
 #define CONFIG_CONS_INDEX	1
diff --git a/include/configs/BUBINGA405EP.h b/include/configs/BUBINGA405EP.h
index a485e4e80f..507cb75948 100644
--- a/include/configs/BUBINGA405EP.h
+++ b/include/configs/BUBINGA405EP.h
@@ -42,7 +42,7 @@
 #define CONFIG_4xx		1	/* ...member of PPC4xx family   */
 #define CONFIG_BUBINGA405EP	1	/* ...on a BUBINGA405EP board	*/
 
-#define CONFIG_BOARD_PRE_INIT	1	/* Call board_pre_init	*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
 
 #define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
 
diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h
index 7aceb582b8..21bc4410c1 100644
--- a/include/configs/CANBT.h
+++ b/include/configs/CANBT.h
@@ -34,12 +34,12 @@
  */
 
 #define CONFIG_405CR		1	/* This is a PPC405CR CPU	*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
-#define CONFIG_CANBT		1	/* ...on a CANBT board	        */
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_CANBT		1	/* ...on a CANBT board		*/
 
-#define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
 
-#define CONFIG_SYS_CLK_FREQ     25000000 /* external frequency to pll   */
+#define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll	*/
 
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_BOOTDELAY	1	/* autoboot after 1 seconds	*/
@@ -52,13 +52,13 @@
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
-#undef  CONFIG_PCI_PNP			/* no pci plug-and-play		*/
+#undef	CONFIG_PCI_PNP			/* no pci plug-and-play		*/
 
-#define	CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
 
-#define CONFIG_COMMANDS	     (( CONFIG_CMD_DFL	|       \
-				CFG_CMD_IRQ	|       \
-				CFG_CMD_EEPROM      ) & \
+#define CONFIG_COMMANDS	     (( CONFIG_CMD_DFL	|	\
+				CFG_CMD_IRQ	|	\
+				CFG_CMD_EEPROM	    ) & \
 			       ~CFG_CMD_NET)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
@@ -66,7 +66,7 @@
 
 #undef CONFIG_WATCHDOG			/* watchdog disabled		*/
 
-#define	CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 
 /*
  * Miscellaneous configurable options
@@ -74,30 +74,30 @@
 #define CFG_LONGHELP			/* undef to save memory		*/
 #define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 #define CFG_MAXARGS	16		/* max number of command args	*/
 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
 #define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define CFG_EXT_SERIAL_CLOCK    14745600 /* use external serial clock   */
+#define CFG_EXT_SERIAL_CLOCK	14745600 /* use external serial clock	*/
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE      \
+#define CFG_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
 #define CFG_LOAD_ADDR	0x100000	/* default load address */
 #define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
@@ -127,44 +127,44 @@
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
-#define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
-#define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
-#define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
-#define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #if 0 /* Use FLASH for environment variables */
 
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_OFFSET		0x00010000	/* Offset of Environment Sector	*/
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET		0x00010000	/* Offset of Environment Sector */
 #define CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
 
-#define CFG_ENV_SECT_SIZE	0x10000	/* see README - env sector total size	*/
+#define CFG_ENV_SECT_SIZE	0x10000 /* see README - env sector total size	*/
 
 #else /* Use EEPROM for environment variables */
 
-#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE            0x400   /* 1024 bytes may be used for env vars */
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x400	/* 1024 bytes may be used for env vars */
 				   /* total size of a CAT24WC08 is 1024 bytes */
 #endif
 
 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC08) for environment
  */
-#define CONFIG_HARD_I2C                 /* I2C with hardware support */
+#define CONFIG_HARD_I2C			/* I2C with hardware support */
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CFG_I2C_SLAVE		0x7F
 
 #define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1	/* bytes of address		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
 #define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
 
@@ -190,26 +190,26 @@
  * External Bus Controller (EBC) Setup
  */
 
-/* Memory Bank 0 (Flash Bank 0) initialization                                  */
-#define CFG_EBC_PB0AP           0x92015480
-#define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CFG_EBC_PB0AP		0x92015480
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
-/* Memory Bank 1 (CAN/USB) initialization                                       */
-#define CFG_EBC_PB1AP           0x010053C0  /* enable Ready, BEM=1              */
-#define CFG_EBC_PB1CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+/* Memory Bank 1 (CAN/USB) initialization					*/
+#define CFG_EBC_PB1AP		0x010053C0  /* enable Ready, BEM=1		*/
+#define CFG_EBC_PB1CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 2 (Misc-IO/LEDs) initialization                                  */
-#define CFG_EBC_PB2AP           0x000004c0  /* no Ready, BEM=1                  */
-#define CFG_EBC_PB2CR           0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit  */
+/* Memory Bank 2 (Misc-IO/LEDs) initialization					*/
+#define CFG_EBC_PB2AP		0x000004c0  /* no Ready, BEM=1			*/
+#define CFG_EBC_PB2CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 3 (CAN Features) initialization                                  */
-#define CFG_EBC_PB3AP           0x80000040  /* no Ready, BEM=1                  */
-#define CFG_EBC_PB3CR           0xF021C000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=32bit */
+/* Memory Bank 3 (CAN Features) initialization					*/
+#define CFG_EBC_PB3AP		0x80000040  /* no Ready, BEM=1			*/
+#define CFG_EBC_PB3CR		0xF021C000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=32bit */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in RAM)
  */
-#define CFG_INIT_RAM_ADDR	0x00ef0000 /* inside of SDRAM                   */
+#define CFG_INIT_RAM_ADDR	0x00ef0000 /* inside of SDRAM			*/
 #define CFG_INIT_RAM_END	0x0f00	/* End of used area in RAM	       */
 #define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h
index b877043712..7c600d92ed 100644
--- a/include/configs/CPCI405.h
+++ b/include/configs/CPCI405.h
@@ -34,21 +34,21 @@
  */
 
 #define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_CPCI405		1	/* ...on a CPCI405 board	*/
 
-#define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
 
-#define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
+#define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll	*/
 
 #define CONFIG_BAUDRATE		9600
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
 
 #if 0
-#define CONFIG_PREBOOT                                                          \
-	"crc32 f0207004 ffc 0;"                                                 \
-	"if cmp 0 f0207000 1;"                                                  \
-	"then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;"             \
+#define CONFIG_PREBOOT								\
+	"crc32 f0207004 ffc 0;"							\
+	"if cmp 0 f0207000 1;"							\
+	"then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;"		\
 	"else;echo Old CRC is bad;fi"
 #endif
 
@@ -67,9 +67,9 @@
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_MII		1	/* MII PHY management		*/
-#define	CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
 
-#define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | \
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
 				 CONFIG_BOOTP_DNS | \
 				 CONFIG_BOOTP_DNS2 | \
 				 CONFIG_BOOTP_SEND_HOSTNAME )
@@ -81,7 +81,7 @@
 				CFG_CMD_IDE	| \
 				CFG_CMD_ELF	| \
 				CFG_CMD_MII	| \
-				CFG_CMD_EEPROM  )
+				CFG_CMD_EEPROM	)
 
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
@@ -89,9 +89,9 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
-#undef  CONFIG_WATCHDOG			/* watchdog disabled		*/
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
-#define	CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 
 /*
  * Miscellaneous configurable options
@@ -101,38 +101,38 @@
 
 #undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
 #ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CFG_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 #define CFG_MAXARGS	16		/* max number of command args	*/
 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
 
-#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
 #define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
-#define CFG_BASE_BAUD       691200
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD	    691200
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE      \
+#define CFG_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
 #define CFG_LOAD_ADDR	0x100000	/* default load address */
 #define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
@@ -140,46 +140,46 @@
  * PCI stuff
  *-----------------------------------------------------------------------
  */
-#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
-
-#define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
-#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-					/* resource configuration       */
-
-#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
-
-#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
-#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
-#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_AUTO	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CONFIG_PCI_BOOTDELAY	0	/* enable pci bootdelay variable*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
+#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A	*/
+#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff
  *-----------------------------------------------------------------------
  */
-#undef  CONFIG_IDE_8xx_DIRECT               /* no pcmcia interface required */
-#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
-#undef  CONFIG_IDE_RESET                /* no reset for ide supported   */
+#undef	CONFIG_IDE_8xx_DIRECT		    /* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+#undef	CONFIG_IDE_RESET		/* no reset for ide supported	*/
 
-#define	CFG_IDE_MAXBUS	        1		/* max. 1 IDE busses	*/
-#define	CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+#define CFG_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
+#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
 
-#define	CFG_ATA_BASE_ADDR	0xF0100000
-#define	CFG_ATA_IDE0_OFFSET	0x0000
+#define CFG_ATA_BASE_ADDR	0xF0100000
+#define CFG_ATA_IDE0_OFFSET	0x0000
 
 #define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
-#define	CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
 #define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
 
 /*-----------------------------------------------------------------------
@@ -208,18 +208,18 @@
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
-#define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
-#define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
-#define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
-#define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #if 1 /* Use NVRAM for environment variables */
 /*-----------------------------------------------------------------------
@@ -235,9 +235,9 @@
 
 #else /* Use EEPROM for environment variables */
 
-#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE            0x200   /* 512 bytes may be used for env vars */
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x200	/* 512 bytes may be used for env vars */
 				   /* total size of a CAT24WC08 is 1024 bytes */
 #endif
 
@@ -249,12 +249,12 @@
 #define CFG_I2C_SLAVE		0x7F
 
 #define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
 #define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
 #define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
-					/* last	4 bits of the address	*/
+					/* last 4 bits of the address	*/
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 
@@ -280,55 +280,55 @@
  * External Bus Controller (EBC) Setup
  */
 
-/* Memory Bank 0 (Flash Bank 0) initialization                                  */
-#define CFG_EBC_PB0AP           0x92015480
-#define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CFG_EBC_PB0AP		0x92015480
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
-/* Memory Bank 1 (Flash Bank 1) initialization                                  */
-#define CFG_EBC_PB1AP           0x92015480
-#define CFG_EBC_PB1CR           0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+/* Memory Bank 1 (Flash Bank 1) initialization					*/
+#define CFG_EBC_PB1AP		0x92015480
+#define CFG_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
 
-/* Memory Bank 2 (CAN0, 1, 2, Codeswitch) initialization                        */
-#define CFG_EBC_PB2AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+/* Memory Bank 2 (CAN0, 1, 2, Codeswitch) initialization			*/
+#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 3 (CompactFlash IDE) initialization                              */
-#define CFG_EBC_PB3AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR           0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+/* Memory Bank 3 (CompactFlash IDE) initialization				*/
+#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 
-/* Memory Bank 4 (NVRAM) initialization                                         */
-#define CFG_EBC_PB4AP           0x01005280  /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1     */
-#define CFG_EBC_PB4CR           0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit  */
+/* Memory Bank 4 (NVRAM) initialization						*/
+#define CFG_EBC_PB4AP		0x01005280  /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1	*/
+#define CFG_EBC_PB4CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 5 (Quart) initialization                                         */
-#define CFG_EBC_PB5AP           0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
-#define CFG_EBC_PB5CR           0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit  */
+/* Memory Bank 5 (Quart) initialization						*/
+#define CFG_EBC_PB5AP		0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
+#define CFG_EBC_PB5CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
 
 /*-----------------------------------------------------------------------
  * FPGA stuff
  */
 
 /* FPGA program pin configuration */
-#define CFG_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT           0x00400000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE           0x00800000  /* FPGA done pin (ppc input)     */
+#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CFG_FPGA_INIT		0x00400000  /* FPGA init pin (ppc input)     */
+#define CFG_FPGA_DONE		0x00800000  /* FPGA done pin (ppc input)     */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
 #if 1 /* test-only */
-#define CFG_INIT_DCACHE_CS      7       /* use cs # 7 for data cache memory    */
+#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
 
-#define CFG_INIT_RAM_ADDR       0x40000000  /* use data cache                  */
+#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
 #else
-#define CFG_INIT_RAM_ADDR	0x00df0000 /* inside of SDRAM                   */
+#define CFG_INIT_RAM_ADDR	0x00df0000 /* inside of SDRAM			*/
 #endif
-#define CFG_INIT_RAM_END        0x2000  /* End of used area in RAM             */
+#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
 
 /*
diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h
index dd2fa7ffea..6ee5698a18 100644
--- a/include/configs/CPCI4052.h
+++ b/include/configs/CPCI4052.h
@@ -34,22 +34,22 @@
  */
 
 #define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_CPCI405		1	/* ...on a CPCI405 board	*/
-#define CONFIG_CPCI405_VER2     1       /* ...version 2                 */
+#define CONFIG_CPCI405_VER2	1	/* ...version 2			*/
 
-#define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
 
-#define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
+#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll	*/
 
 #define CONFIG_BAUDRATE		9600
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
 
 #if 0
-#define CONFIG_PREBOOT                                                          \
-	"crc32 f0207004 ffc 0;"                                                 \
-	"if cmp 0 f0207000 1;"                                                  \
-	"then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;"             \
+#define CONFIG_PREBOOT								\
+	"crc32 f0207004 ffc 0;"							\
+	"if cmp 0 f0207000 1;"							\
+	"then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;"		\
 	"else;echo Old CRC is bad;fi"
 #endif
 
@@ -68,11 +68,11 @@
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_MII		1	/* MII PHY management		*/
-#define	CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
 
 #define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
 
-#define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | \
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
 				 CONFIG_BOOTP_DNS | \
 				 CONFIG_BOOTP_DNS2 | \
 				 CONFIG_BOOTP_SEND_HOSTNAME )
@@ -88,7 +88,7 @@
 				CFG_CMD_I2C	| \
 				CFG_CMD_MII	| \
 				CFG_CMD_PING	| \
-				CFG_CMD_EEPROM  )
+				CFG_CMD_EEPROM	)
 
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
@@ -96,9 +96,9 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
-#undef  CONFIG_WATCHDOG			/* watchdog disabled		*/
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
-#define	CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 
 /*
  * Miscellaneous configurable options
@@ -108,89 +108,89 @@
 
 #undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
 #ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CFG_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 #define CFG_MAXARGS	16		/* max number of command args	*/
 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
 
-#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
 #define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
-#define CFG_BASE_BAUD       691200
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD	    691200
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE      \
+#define CFG_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
 #define CFG_LOAD_ADDR	0x100000	/* default load address */
 #define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
-#define CONFIG_VERSION_VARIABLE	1       /* include version env variable */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
-#define CFG_RX_ETH_BUFFER	16      /* use 16 rx buffer on 405 emac */
+#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
  */
-#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
-
-#define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
-#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-					/* resource configuration       */
-
-#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
-
-#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
-#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
-#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_AUTO	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CONFIG_PCI_BOOTDELAY	0	/* enable pci bootdelay variable*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
+#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A	*/
+#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff
  *-----------------------------------------------------------------------
  */
-#undef  CONFIG_IDE_8xx_DIRECT               /* no pcmcia interface required */
-#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
+#undef	CONFIG_IDE_8xx_DIRECT		    /* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
 #define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
 
-#define	CFG_IDE_MAXBUS	        1		/* max. 1 IDE busses	*/
-#define	CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+#define CFG_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
+#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
 
-#define	CFG_ATA_BASE_ADDR	0xF0100000
-#define	CFG_ATA_IDE0_OFFSET	0x0000
+#define CFG_ATA_BASE_ADDR	0xF0100000
+#define CFG_ATA_IDE0_OFFSET	0x0000
 
 #define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
-#define	CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
 #define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
 
 /*-----------------------------------------------------------------------
@@ -219,21 +219,21 @@
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
-#define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
-#define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
-#define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
-#define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
-#define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS     1           /* ! second bank contains U-Boot */
+#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
 
 #if 0 /* Use NVRAM for environment variables */
 /*-----------------------------------------------------------------------
@@ -246,9 +246,9 @@
 
 #else /* Use EEPROM for environment variables */
 
-#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE            0x800   /* 2048 bytes may be used for env vars*/
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x800	/* 2048 bytes may be used for env vars*/
 				   /* total size of a CAT24WC16 is 2048 bytes */
 #endif
 
@@ -264,20 +264,20 @@
 #define CFG_I2C_SLAVE		0x7F
 
 #define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
 #define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
 #define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
-					/* last	4 bits of the address	*/
+					/* last 4 bits of the address	*/
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's    */
-					/* have only 8kB, 16kB is save here     */
+#define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's	*/
+					/* have only 8kB, 16kB is save here	*/
 #define CFG_CACHELINE_SIZE	32	/* ...			*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
@@ -296,89 +296,89 @@
  * External Bus Controller (EBC) Setup
  */
 
-/* Memory Bank 0 (Flash Bank 0) initialization                                  */
-#define CFG_EBC_PB0AP           0x92015480
-#define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CFG_EBC_PB0AP		0x92015480
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
-/* Memory Bank 1 (Flash Bank 1) initialization                                  */
-#define CFG_EBC_PB1AP           0x92015480
-#define CFG_EBC_PB1CR           0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+/* Memory Bank 1 (Flash Bank 1) initialization					*/
+#define CFG_EBC_PB1AP		0x92015480
+#define CFG_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
 
-/* Memory Bank 2 (CAN0, 1) initialization                                       */
-#define CFG_EBC_PB2AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
-#define CFG_LED_ADDR            0xF0000380
+/* Memory Bank 2 (CAN0, 1) initialization					*/
+#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#define CFG_LED_ADDR		0xF0000380
 
-/* Memory Bank 3 (CompactFlash IDE) initialization                              */
-#define CFG_EBC_PB3AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR           0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+/* Memory Bank 3 (CompactFlash IDE) initialization				*/
+#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 
-/* Memory Bank 4 (NVRAM/RTC) initialization                                     */
-/*#define CFG_EBC_PB4AP           0x01805280  / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1     */
-#define CFG_EBC_PB4AP           0x01805680  /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1     */
-#define CFG_EBC_PB4CR           0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit  */
+/* Memory Bank 4 (NVRAM/RTC) initialization					*/
+/*#define CFG_EBC_PB4AP		  0x01805280  / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1	   */
+#define CFG_EBC_PB4AP		0x01805680  /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1	*/
+#define CFG_EBC_PB4CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 5 (optional Quart) initialization                                */
-#define CFG_EBC_PB5AP           0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
-#define CFG_EBC_PB5CR           0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit  */
+/* Memory Bank 5 (optional Quart) initialization				*/
+#define CFG_EBC_PB5AP		0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
+#define CFG_EBC_PB5CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 6 (FPGA internal) initialization                                 */
-#define CFG_EBC_PB6AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB6CR           0xF041A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-#define CFG_FPGA_BASE_ADDR      0xF0400000
+/* Memory Bank 6 (FPGA internal) initialization					*/
+#define CFG_EBC_PB6AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB6CR		0xF041A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+#define CFG_FPGA_BASE_ADDR	0xF0400000
 
 /*-----------------------------------------------------------------------
  * FPGA stuff
  */
 /* FPGA internal regs */
-#define CFG_FPGA_MODE           0x00
-#define CFG_FPGA_STATUS         0x02
-#define CFG_FPGA_TS             0x04
-#define CFG_FPGA_TS_LOW         0x06
-#define CFG_FPGA_TS_CAP0        0x10
-#define CFG_FPGA_TS_CAP0_LOW    0x12
-#define CFG_FPGA_TS_CAP1        0x14
-#define CFG_FPGA_TS_CAP1_LOW    0x16
-#define CFG_FPGA_TS_CAP2        0x18
-#define CFG_FPGA_TS_CAP2_LOW    0x1a
-#define CFG_FPGA_TS_CAP3        0x1c
-#define CFG_FPGA_TS_CAP3_LOW    0x1e
+#define CFG_FPGA_MODE		0x00
+#define CFG_FPGA_STATUS		0x02
+#define CFG_FPGA_TS		0x04
+#define CFG_FPGA_TS_LOW		0x06
+#define CFG_FPGA_TS_CAP0	0x10
+#define CFG_FPGA_TS_CAP0_LOW	0x12
+#define CFG_FPGA_TS_CAP1	0x14
+#define CFG_FPGA_TS_CAP1_LOW	0x16
+#define CFG_FPGA_TS_CAP2	0x18
+#define CFG_FPGA_TS_CAP2_LOW	0x1a
+#define CFG_FPGA_TS_CAP3	0x1c
+#define CFG_FPGA_TS_CAP3_LOW	0x1e
 
 /* FPGA Mode Reg */
-#define CFG_FPGA_MODE_CF_RESET      0x0001
+#define CFG_FPGA_MODE_CF_RESET	    0x0001
 #define CFG_FPGA_MODE_DUART_RESET   0x0002
 #define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004     /* only set on CPCI-405 Ver 3 */
 #define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
 #define CFG_FPGA_MODE_TS_IRQ_CLEAR  0x1000
-#define CFG_FPGA_MODE_TS_CLEAR      0x2000
+#define CFG_FPGA_MODE_TS_CLEAR	    0x2000
 
 /* FPGA Status Reg */
-#define CFG_FPGA_STATUS_DIP0    0x0001
-#define CFG_FPGA_STATUS_DIP1    0x0002
-#define CFG_FPGA_STATUS_DIP2    0x0004
-#define CFG_FPGA_STATUS_FLASH   0x0008
-#define CFG_FPGA_STATUS_TS_IRQ  0x1000
+#define CFG_FPGA_STATUS_DIP0	0x0001
+#define CFG_FPGA_STATUS_DIP1	0x0002
+#define CFG_FPGA_STATUS_DIP2	0x0004
+#define CFG_FPGA_STATUS_FLASH	0x0008
+#define CFG_FPGA_STATUS_TS_IRQ	0x1000
 
-#define CFG_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
-#define CFG_FPGA_MAX_SIZE       32*1024     /* 32kByte is enough for XC2S15  */
+#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CFG_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for XC2S15  */
 
 /* FPGA program pin configuration */
-#define CFG_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */
+#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
+#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
-#define CFG_INIT_DCACHE_CS      7       /* use cs # 7 for data cache memory    */
+#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
 
-#define CFG_INIT_RAM_ADDR       0x40000000  /* use data cache                  */
-#define CFG_INIT_RAM_END        0x2000  /* End of used area in RAM             */
+#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
+#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
 
 /*
diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h
index 492fe49424..3c94ebc349 100644
--- a/include/configs/CPCI405AB.h
+++ b/include/configs/CPCI405AB.h
@@ -34,38 +34,38 @@
  */
 
 #define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_CPCI405		1	/* ...on a CPCI405 board	*/
-#define CONFIG_CPCI405_VER2     1       /* ...version 2                 */
-#define CONFIG_CPCI405AB        1       /* ...and special AB version    */
+#define CONFIG_CPCI405_VER2	1	/* ...version 2			*/
+#define CONFIG_CPCI405AB	1	/* ...and special AB version	*/
 
-#define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
 
-#define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
+#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll	*/
 
 #define CONFIG_BAUDRATE		9600
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
 
 #if 0
-#define CONFIG_PREBOOT                                                          \
-	"crc32 f0207004 ffc 0;"                                                 \
-	"if cmp 0 f0207000 1;"                                                  \
-	"then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;"             \
+#define CONFIG_PREBOOT								\
+	"crc32 f0207004 ffc 0;"							\
+	"if cmp 0 f0207000 1;"							\
+	"then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;"		\
 	"else;echo Old CRC is bad;fi"
 #endif
 
 #undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND	"bootm 100000"	/* default boot command	*/
+#define CONFIG_BOOTCOMMAND	"bootm 100000"	/* default boot command */
 
-#undef  CONFIG_LOADS_ECHO		/* echo on for serial download	*/
+#undef	CONFIG_LOADS_ECHO		/* echo on for serial download	*/
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_MII		1	/* MII PHY management		*/
-#define	CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
 
 #define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
 
-#define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | \
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
 				 CONFIG_BOOTP_DNS | \
 				 CONFIG_BOOTP_DNS2 | \
 				 CONFIG_BOOTP_SEND_HOSTNAME )
@@ -81,7 +81,7 @@
 				CFG_CMD_I2C	| \
 				CFG_CMD_MII	| \
 				CFG_CMD_PING	| \
-				CFG_CMD_EEPROM  )
+				CFG_CMD_EEPROM	)
 
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
@@ -89,9 +89,9 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
-#undef  CONFIG_WATCHDOG			/* watchdog disabled		*/
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
-#define	CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 
 /*
  * Miscellaneous configurable options
@@ -101,89 +101,89 @@
 
 #undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
 #ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CFG_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 #define CFG_MAXARGS	16		/* max number of command args	*/
 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
 
-#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
 #define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
-#define CFG_BASE_BAUD       691200
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD	    691200
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE      \
+#define CFG_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
 #define CFG_LOAD_ADDR	0x100000	/* default load address */
 #define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
-#define CONFIG_VERSION_VARIABLE	1       /* include version env variable */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
-#define CFG_RX_ETH_BUFFER	16      /* use 16 rx buffer on 405 emac */
+#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
  */
-#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
-
-#define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
-#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-					/* resource configuration       */
-
-#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
-
-#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
-#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
-#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_AUTO	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CONFIG_PCI_BOOTDELAY	0	/* enable pci bootdelay variable*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
+#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A	*/
+#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff
  *-----------------------------------------------------------------------
  */
-#undef  CONFIG_IDE_8xx_DIRECT               /* no pcmcia interface required */
-#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
+#undef	CONFIG_IDE_8xx_DIRECT		    /* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
 #define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
 
-#define	CFG_IDE_MAXBUS	        1		/* max. 1 IDE busses	*/
-#define	CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+#define CFG_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
+#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
 
-#define	CFG_ATA_BASE_ADDR	0xF0100000
-#define	CFG_ATA_IDE0_OFFSET	0x0000
+#define CFG_ATA_BASE_ADDR	0xF0100000
+#define CFG_ATA_IDE0_OFFSET	0x0000
 
 #define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
-#define	CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
 #define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
 
 /*-----------------------------------------------------------------------
@@ -212,21 +212,21 @@
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
-#define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
-#define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
-#define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
-#define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
-#define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS     1           /* ! second bank contains U-Boot */
+#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
 
 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC32) for environment
@@ -236,20 +236,20 @@
 #define CFG_I2C_SLAVE		0x7F
 
 #define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC32		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CFG_I2C_EEPROM_ADDR_LEN 2	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
 #define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x01
 #define CFG_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
 					/* 32 byte page write mode using*/
-					/* last	5 bits of the address	*/
+					/* last 5 bits of the address	*/
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 
 /* Use EEPROM for environment variables */
 
-#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE            0x800   /* 2048 bytes may be used for env vars*/
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x800	/* 2048 bytes may be used for env vars*/
 				   /* total size of a CAT24WC32 is 4096 bytes */
 
 #define CFG_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
@@ -259,8 +259,8 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's    */
-					/* have only 8kB, 16kB is save here     */
+#define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's	*/
+					/* have only 8kB, 16kB is save here	*/
 #define CFG_CACHELINE_SIZE	32	/* ...			*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
@@ -279,89 +279,89 @@
  * External Bus Controller (EBC) Setup
  */
 
-/* Memory Bank 0 (Flash Bank 0) initialization                                  */
-#define CFG_EBC_PB0AP           0x92015480
-#define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CFG_EBC_PB0AP		0x92015480
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
-/* Memory Bank 1 (Flash Bank 1) initialization                                  */
-#define CFG_EBC_PB1AP           0x92015480
-#define CFG_EBC_PB1CR           0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+/* Memory Bank 1 (Flash Bank 1) initialization					*/
+#define CFG_EBC_PB1AP		0x92015480
+#define CFG_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
 
-/* Memory Bank 2 (CAN0, 1) initialization                                       */
-#define CFG_EBC_PB2AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
-#define CFG_LED_ADDR            0xF0000380
+/* Memory Bank 2 (CAN0, 1) initialization					*/
+#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#define CFG_LED_ADDR		0xF0000380
 
-/* Memory Bank 3 (CompactFlash IDE) initialization                              */
-#define CFG_EBC_PB3AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR           0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+/* Memory Bank 3 (CompactFlash IDE) initialization				*/
+#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 
-/* Memory Bank 4 (NVRAM/RTC) initialization                                     */
-/*#define CFG_EBC_PB4AP           0x01805280  / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1     */
-#define CFG_EBC_PB4AP           0x01805680  /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1     */
-#define CFG_EBC_PB4CR           0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit  */
+/* Memory Bank 4 (NVRAM/RTC) initialization					*/
+/*#define CFG_EBC_PB4AP		  0x01805280  / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1	   */
+#define CFG_EBC_PB4AP		0x01805680  /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1	*/
+#define CFG_EBC_PB4CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 5 (optional Quart) initialization                                */
-#define CFG_EBC_PB5AP           0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
-#define CFG_EBC_PB5CR           0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit  */
+/* Memory Bank 5 (optional Quart) initialization				*/
+#define CFG_EBC_PB5AP		0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
+#define CFG_EBC_PB5CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 6 (FPGA internal) initialization                                 */
-#define CFG_EBC_PB6AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB6CR           0xF041A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-#define CFG_FPGA_BASE_ADDR      0xF0400000
+/* Memory Bank 6 (FPGA internal) initialization					*/
+#define CFG_EBC_PB6AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB6CR		0xF041A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+#define CFG_FPGA_BASE_ADDR	0xF0400000
 
 /*-----------------------------------------------------------------------
  * FPGA stuff
  */
 /* FPGA internal regs */
-#define CFG_FPGA_MODE           0x00
-#define CFG_FPGA_STATUS         0x02
-#define CFG_FPGA_TS             0x04
-#define CFG_FPGA_TS_LOW         0x06
-#define CFG_FPGA_TS_CAP0        0x10
-#define CFG_FPGA_TS_CAP0_LOW    0x12
-#define CFG_FPGA_TS_CAP1        0x14
-#define CFG_FPGA_TS_CAP1_LOW    0x16
-#define CFG_FPGA_TS_CAP2        0x18
-#define CFG_FPGA_TS_CAP2_LOW    0x1a
-#define CFG_FPGA_TS_CAP3        0x1c
-#define CFG_FPGA_TS_CAP3_LOW    0x1e
+#define CFG_FPGA_MODE		0x00
+#define CFG_FPGA_STATUS		0x02
+#define CFG_FPGA_TS		0x04
+#define CFG_FPGA_TS_LOW		0x06
+#define CFG_FPGA_TS_CAP0	0x10
+#define CFG_FPGA_TS_CAP0_LOW	0x12
+#define CFG_FPGA_TS_CAP1	0x14
+#define CFG_FPGA_TS_CAP1_LOW	0x16
+#define CFG_FPGA_TS_CAP2	0x18
+#define CFG_FPGA_TS_CAP2_LOW	0x1a
+#define CFG_FPGA_TS_CAP3	0x1c
+#define CFG_FPGA_TS_CAP3_LOW	0x1e
 
 /* FPGA Mode Reg */
-#define CFG_FPGA_MODE_CF_RESET      0x0001
+#define CFG_FPGA_MODE_CF_RESET	    0x0001
 #define CFG_FPGA_MODE_DUART_RESET   0x0002
 #define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004     /* only set on CPCI-405 Ver 3 */
 #define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
 #define CFG_FPGA_MODE_TS_IRQ_CLEAR  0x1000
-#define CFG_FPGA_MODE_TS_CLEAR      0x2000
+#define CFG_FPGA_MODE_TS_CLEAR	    0x2000
 
 /* FPGA Status Reg */
-#define CFG_FPGA_STATUS_DIP0    0x0001
-#define CFG_FPGA_STATUS_DIP1    0x0002
-#define CFG_FPGA_STATUS_DIP2    0x0004
-#define CFG_FPGA_STATUS_FLASH   0x0008
-#define CFG_FPGA_STATUS_TS_IRQ  0x1000
+#define CFG_FPGA_STATUS_DIP0	0x0001
+#define CFG_FPGA_STATUS_DIP1	0x0002
+#define CFG_FPGA_STATUS_DIP2	0x0004
+#define CFG_FPGA_STATUS_FLASH	0x0008
+#define CFG_FPGA_STATUS_TS_IRQ	0x1000
 
-#define CFG_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
-#define CFG_FPGA_MAX_SIZE       128*1024    /* 128kByte is enough for XC2S30 */
+#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CFG_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S30 */
 
 /* FPGA program pin configuration */
-#define CFG_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */
+#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
+#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
-#define CFG_INIT_DCACHE_CS      7       /* use cs # 7 for data cache memory    */
+#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
 
-#define CFG_INIT_RAM_ADDR       0x40000000  /* use data cache                  */
-#define CFG_INIT_RAM_END        0x2000  /* End of used area in RAM             */
+#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
+#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
 
 /*
diff --git a/include/configs/CPCI440.h b/include/configs/CPCI440.h
index 55bb1ec673..3e0cee4025 100644
--- a/include/configs/CPCI440.h
+++ b/include/configs/CPCI440.h
@@ -33,7 +33,7 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_EBONY		1	    /* Board is ebony		*/
 #define CONFIG_4xx		1	    /* ... PPC4xx family	*/
-#define CONFIG_BOARD_PRE_INIT	1	    /* Call board_pre_init	*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
 #undef	CFG_DRAM_TEST			    /* Disable-takes long time! */
 #define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
 
diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h
index bcda6998cc..1aff9e47ce 100644
--- a/include/configs/CPCIISER4.h
+++ b/include/configs/CPCIISER4.h
@@ -34,12 +34,12 @@
  */
 
 #define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_CPCIISER4	1	/* ...on a CPCIISER4 board	*/
 
-#define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
 
-#define CONFIG_SYS_CLK_FREQ     25000000 /* external frequency to pll   */
+#define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll	*/
 
 #define CONFIG_BAUDRATE		9600
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
@@ -51,21 +51,21 @@
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_MII		1	/* MII PHY management		*/
-#define	CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
 
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_PCI	| \
 				CFG_CMD_IRQ	| \
 				CFG_CMD_MII	| \
 				CFG_CMD_ELF	| \
-				CFG_CMD_EEPROM  )
+				CFG_CMD_EEPROM	)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
 #undef CONFIG_WATCHDOG			/* watchdog disabled		*/
 
-#define	CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 
 /*
  * Miscellaneous configurable options
@@ -73,30 +73,30 @@
 #define CFG_LONGHELP			/* undef to save memory		*/
 #define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 #define CFG_MAXARGS	16		/* max number of command args	*/
 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
 #define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define CFG_EXT_SERIAL_CLOCK    1843200  /* use external serial clock   */
+#define CFG_EXT_SERIAL_CLOCK	1843200	 /* use external serial clock	*/
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE      \
+#define CFG_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
 #define CFG_LOAD_ADDR	0x100000	/* default load address */
 #define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
@@ -104,23 +104,23 @@
  * PCI stuff
  *-----------------------------------------------------------------------
  */
-#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
-
-#define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
-#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-					/* resource configuration       */
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0404  /* PCI Device ID: CPCI-ISER4    */
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xff000001      /* 16MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0xffe00000      /* point to flash               */
-#define CFG_PCI_PTM2MS  0xffe00001      /* 2MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_AUTO	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0404	/* PCI Device ID: CPCI-ISER4	*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0xff000001	/* 16MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0xffe00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xffe00001	/* 2MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
@@ -148,18 +148,18 @@
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
-#define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
-#define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
-#define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
-#define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC08) for environment
@@ -169,18 +169,18 @@
 #define CFG_I2C_SLAVE		0x7F
 
 #define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
 #define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
 #define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
-					/* last	4 bits of the address	*/
+					/* last 4 bits of the address	*/
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 
-#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE            0x300   /* 768 bytes may be used for env vars */
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x300	/* 768 bytes may be used for env vars */
 				   /* total size of a CAT24WC08 is 1024 bytes */
 
 /*-----------------------------------------------------------------------
@@ -205,31 +205,31 @@
  * External Bus Controller (EBC) Setup
  */
 
-/* Memory Bank 0 (Flash Bank 0) initialization                                  */
-#define CFG_EBC_PB0AP           0x92015480
-#define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CFG_EBC_PB0AP		0x92015480
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
-/* Memory Bank 1 (Uart 8bit) initialization                                     */
-#define CFG_EBC_PB1AP           0x01000480  /* TWT=2,TH=2,no Ready,BEM=0,SOR=1  */
-#define CFG_EBC_PB1CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+/* Memory Bank 1 (Uart 8bit) initialization					*/
+#define CFG_EBC_PB1AP		0x01000480  /* TWT=2,TH=2,no Ready,BEM=0,SOR=1	*/
+#define CFG_EBC_PB1CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 2 (Uart 32bit) initialization                                    */
-#define CFG_EBC_PB2AP           0x000004c0  /* no Ready, BEM=1                  */
-#define CFG_EBC_PB2CR           0xF011C000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
+/* Memory Bank 2 (Uart 32bit) initialization					*/
+#define CFG_EBC_PB2AP		0x000004c0  /* no Ready, BEM=1			*/
+#define CFG_EBC_PB2CR		0xF011C000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
 
-/* Memory Bank 3 (FPGA Reset) initialization                                    */
-#define CFG_EBC_PB3AP           0x010004C0  /* no Ready, BEM=1                  */
-#define CFG_EBC_PB3CR           0xF021A000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */
+/* Memory Bank 3 (FPGA Reset) initialization					*/
+#define CFG_EBC_PB3AP		0x010004C0  /* no Ready, BEM=1			*/
+#define CFG_EBC_PB3CR		0xF021A000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_DCACHE_CS      7       /* use cs # 7 for data cache memory    */
-#define CFG_INIT_RAM_ADDR       0x40000000  /* use data cache                  */
-#define CFG_INIT_RAM_END        0x2000  /* End of used area in RAM             */
+#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
+#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
+#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
 /*
  * Internal Definitions
diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h
index fd8594493b..63d7a92404 100644
--- a/include/configs/CRAYL1.h
+++ b/include/configs/CRAYL1.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000, 2001
+ * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  * David Updegraff, Cray, Inc.  dave@cray.com: our 405 is walnut-lite..
  *
@@ -41,7 +41,7 @@
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 #define CONFIG_MII		    1	/* MII PHY management */
 #define	CONFIG_PHY_ADDR		1	/* PHY address; handling of ENET */
-#define CONFIG_BOARD_PRE_INIT 1 /* early setup for 405gp */
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* early setup for 405gp */
 #define CONFIG_MISC_INIT_R	1	/* so that a misc_init_r() is called */
 
 /* set PRAM to keep U-Boot out, mem= to keep linux out, and initrd_hi to
diff --git a/include/configs/DASA_SIM.h b/include/configs/DASA_SIM.h
index 30e978cdaa..5ff9b9ecfc 100644
--- a/include/configs/DASA_SIM.h
+++ b/include/configs/DASA_SIM.h
@@ -12,7 +12,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -34,20 +34,20 @@
  */
 
 #define CONFIG_IOP480		1	/* This is a IOP480 CPU		*/
-#define CONFIG_DASA_SIM		1	/* ...on a DASA_SIM board 	*/
+#define CONFIG_DASA_SIM		1	/* ...on a DASA_SIM board	*/
 
-#define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
 
-#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+#define CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
 
-#define CONFIG_CPUCLOCK	        66
-#define CONFIG_BUSCLOCK	        (CONFIG_CPUCLOCK)
+#define CONFIG_CPUCLOCK		66
+#define CONFIG_BUSCLOCK		(CONFIG_CPUCLOCK)
 
-#define CONFIG_BAUDRATE	        9600
+#define CONFIG_BAUDRATE		9600
 #define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds	*/
 #define CONFIG_BOOTCOMMAND	"bootm ffe00000" /* autoboot command	*/
 
-#undef  CONFIG_BOOTARGS
+#undef	CONFIG_BOOTARGS
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
@@ -63,16 +63,16 @@
 				CFG_CMD_IRQ	| \
 				CFG_CMD_BSP	| \
 				CFG_CMD_ASKENV	| \
-				CFG_CMD_ELF     )
+				CFG_CMD_ELF	)
 #else
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_BSP     )
+				CFG_CMD_BSP	)
 #endif
 
 #if 0 /* Does not appear to be used?!  If it is used, needs to be fixed */
 #define CONFIG_SOFT_I2C			/* Software I2C support enabled */
 #endif
-#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
@@ -83,33 +83,33 @@
 #define CFG_LONGHELP			/* undef to save memory		*/
 #define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 #define CFG_MAXARGS	16		/* max number of command args	*/
 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
 #define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE      \
+#define CFG_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 }
 
-#define CFG_LOAD_ADDR	0x100000	/* default load address	*/
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	0x00df0000 /* inside of SDRAM                   */
+#define CFG_INIT_RAM_ADDR	0x00df0000 /* inside of SDRAM			*/
 #define CFG_INIT_RAM_END	0x0f00	/* End of used area in RAM	       */
 #define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
@@ -131,37 +131,37 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 #define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256     /* max number of sectors on one chip	*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE     unsigned char   /* flash word size (width)      */
-#define CFG_FLASH_ADDR0         0x0AA9  /* 1st address for flash config cycles  */
-#define CFG_FLASH_ADDR1         0x0556  /* 2nd address for flash config cycles  */
+#define CFG_FLASH_WORD_SIZE	unsigned char	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x0AA9	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x0556	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0         0x0002  /* 0 is standard                        */
-#define CFG_FLASH_READ1         0x0000  /* 1 is standard                        */
-#define CFG_FLASH_READ2         0x0004  /* 2 is standard                        */
+#define CFG_FLASH_READ0		0x0002	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0000	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0004	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_OFFSET		0x00010000	/* Offset of Environment Sector	*/
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET		0x00010000	/* Offset of Environment Sector */
 #define CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
 
 #if 0
 #define CFG_ENV_SECT_SIZE	0x8000	/* see README - env sector total size	*/
 #else
-#define CFG_ENV_SECT_SIZE	0x10000	/* see README - env sector total size	*/
+#define CFG_ENV_SECT_SIZE	0x10000 /* see README - env sector total size	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -170,12 +170,12 @@
 #define CONFIG_PCI			/* include pci support			*/
 #undef CONFIG_PCI_PNP
 
-#define CONFIG_NET_MULTI		/* Multi ethernet cards support 	*/
+#define CONFIG_NET_MULTI		/* Multi ethernet cards support		*/
 
 #define CONFIG_TULIP
 
-#define CFG_ETH_DEV_FN       0x0000
-#define CFG_ETH_IOBASE       0x0fff0000
+#define CFG_ETH_DEV_FN	     0x0000
+#define CFG_ETH_IOBASE	     0x0fff0000
 #define CFG_PCI9054_DEV_FN   0x0800
 #define CFG_PCI9054_IOBASE   0x0eff0000
 
diff --git a/include/configs/DB64360.h b/include/configs/DB64360.h
index 25614b080c..e318b274a7 100644
--- a/include/configs/DB64360.h
+++ b/include/configs/DB64360.h
@@ -131,7 +131,7 @@ if we use PCI it has its own MAC addr */
 
 /* which initialization functions to call for this board */
 #define CONFIG_MISC_INIT_R     /* initialize the icache L1 */
-#define CONFIG_BOARD_PRE_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
 
 #define CFG_BOARD_NAME		"DB64360"
 #define CONFIG_IDENT_STRING	"Marvell DB64360 (1.1)"
diff --git a/include/configs/DB64460.h b/include/configs/DB64460.h
index acf2becb4f..e58b63a458 100644
--- a/include/configs/DB64460.h
+++ b/include/configs/DB64460.h
@@ -68,7 +68,7 @@
 
 /* which initialization functions to call for this board */
 #define CONFIG_MISC_INIT_R     /* initialize the icache L1 */
-#define CONFIG_BOARD_PRE_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
 
 #define CFG_BOARD_NAME		"DB64460"
 #define CONFIG_IDENT_STRING	"Marvell DB64460 (1.0)"
diff --git a/include/configs/DK1C20.h b/include/configs/DK1C20.h
index 0d8e4631b3..92c8e517eb 100644
--- a/include/configs/DK1C20.h
+++ b/include/configs/DK1C20.h
@@ -295,7 +295,7 @@
 #define CONFIG_SYS_CLK_FREQ	CFG_NIOS_CPU_CLK/* 50 MHz core clock	*/
 #define	CFG_HZ			1000		/* 1 msec time tick	*/
 #undef  CFG_CLKS_IN_HZ
-#define	CONFIG_BOARD_PRE_INIT	1	/* enable early board-spec. init*/
+#define	CONFIG_BOARD_EARLY_INIT_F 1	/* enable early board-spec. init*/
 
 /*------------------------------------------------------------------------
  * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM)
diff --git a/include/configs/DK1S10.h b/include/configs/DK1S10.h
index c54ac58c3a..bd7ded52b9 100644
--- a/include/configs/DK1S10.h
+++ b/include/configs/DK1S10.h
@@ -294,7 +294,7 @@
 #define CONFIG_SYS_CLK_FREQ	CFG_NIOS_CPU_CLK/* 50 MHz core clock	*/
 #define	CFG_HZ			1000		/* 1 msec time tick	*/
 #undef  CFG_CLKS_IN_HZ
-#define	CONFIG_BOARD_PRE_INIT	1	/* enable early board-spec. init*/
+#define	CONFIG_BOARD_EARLY_INIT_F 1	/* enable early board-spec. init*/
 
 /*------------------------------------------------------------------------
  * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM)
diff --git a/include/configs/DP405.h b/include/configs/DP405.h
index 03bd0805a6..666a0d0ff8 100644
--- a/include/configs/DP405.h
+++ b/include/configs/DP405.h
@@ -34,13 +34,13 @@
  */
 
 #define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
-#define CONFIG_DP405		1	/* ...on a DP405 board 	        */
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_DP405		1	/* ...on a DP405 board		*/
 
-#define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */
-#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
 
-#define CONFIG_SYS_CLK_FREQ     33333334 /* external frequency to pll   */
+#define CONFIG_SYS_CLK_FREQ	33333334 /* external frequency to pll	*/
 
 #define CONFIG_BAUDRATE		9600
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
@@ -60,7 +60,7 @@
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_MII		1	/* MII PHY management		*/
-#define	CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
 
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_BSP	| \
@@ -69,17 +69,17 @@
 				CFG_CMD_ELF	| \
 				CFG_CMD_DATE	| \
 				CFG_CMD_I2C	| \
-				CFG_CMD_EEPROM  )
+				CFG_CMD_EEPROM	)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
-#undef  CONFIG_WATCHDOG			/* watchdog disabled		*/
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
-#define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible*/
-#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address         */
+#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
+#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
 
-#define	CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 
 /*
  * Miscellaneous configurable options
@@ -89,70 +89,70 @@
 
 #undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
 #ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CFG_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 #define CFG_MAXARGS	16		/* max number of command args	*/
 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
 
-#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
 #define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
-#define CFG_BASE_BAUD       691200
-#undef  CONFIG_UART1_CONSOLE            /* define for uart1 as console  */
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD	    691200
+#undef	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE      \
+#define CFG_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
 #define CFG_LOAD_ADDR	0x100000	/* default load address */
 #define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
-#define CONFIG_VERSION_VARIABLE	1       /* include version env variable */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
-#define CFG_RX_ETH_BUFFER	16      /* use 16 rx buffer on 405 emac */
+#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
  */
-#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
-
-#define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_HOST	PCI_HOST_HOST   /* select pci host function     */
-#undef  CONFIG_PCI_PNP			/* do pci plug-and-play         */
-					/* resource configuration       */
-
-#undef  CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
-#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_HOST	/* select pci host function	*/
+#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
+#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 
 /*
  * For booting Linux, the board info and command line data
@@ -171,22 +171,22 @@
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
-#define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
-#define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
-#define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
-#define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS     1           /* ! second bank contains U-Boot */
+#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -209,13 +209,13 @@
 /*-----------------------------------------------------------------------
  * Environment Variable setup
  */
-#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET          0x100   /* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE            0x700   /* 2048 bytes may be used for env vars*/
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
 				   /* total size of a CAT24WC16 is 2048 bytes */
 
 #define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		242		        /* NVRAM size		*/
+#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
 
 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC16) for environment
@@ -225,20 +225,20 @@
 #define CFG_I2C_SLAVE		0x7F
 
 #define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
 #define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
 #define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
-					/* last	4 bits of the address	*/
+					/* last 4 bits of the address	*/
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's    */
-					/* have only 8kB, 16kB is save here     */
+#define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's	*/
+					/* have only 8kB, 16kB is save here	*/
 #define CFG_CACHELINE_SIZE	32	/* ...			*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
@@ -248,41 +248,41 @@
  * External Bus Controller (EBC) Setup
  */
 
-#define CAN_BA          0xF0000000          /* CAN Base Address                 */
-#define RTC_BA          0xF0000500          /* RTC Base Address                 */
+#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
+#define RTC_BA		0xF0000500	    /* RTC Base Address			*/
 
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
-#define CFG_EBC_PB0AP           0x92015480
-#define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CFG_EBC_PB0AP		0x92015480
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
 #if 0 /* test-only */
-/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization                      */
-#define CFG_EBC_PB1AP           0x92015480
-#define CFG_EBC_PB1CR           0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit  */
+/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
+#define CFG_EBC_PB1AP		0x92015480
+#define CFG_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
 #endif
 
-/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization              */
-#define CFG_EBC_PB2AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
+#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 
 /*-----------------------------------------------------------------------
  * FPGA stuff
  */
-#define CFG_FPGA_XC95XL         1           /* using Xilinx XC95XL CPLD      */
-#define CFG_FPGA_MAX_SIZE       32*1024     /* 32kByte is enough for CPLD    */
+#define CFG_FPGA_XC95XL		1	    /* using Xilinx XC95XL CPLD	     */
+#define CFG_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for CPLD    */
 
 /* FPGA program pin configuration */
-#define CFG_FPGA_PRG            0x04000000  /* JTAG TMS pin (ppc output)     */
-#define CFG_FPGA_CLK            0x02000000  /* JTAG TCK pin (ppc output)     */
-#define CFG_FPGA_DATA           0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
-#define CFG_FPGA_INIT           0x00010000  /* unused (ppc input)            */
-#define CFG_FPGA_DONE           0x00008000  /* JTAG TDI->TDO pin (ppc input) */
+#define CFG_FPGA_PRG		0x04000000  /* JTAG TMS pin (ppc output)     */
+#define CFG_FPGA_CLK		0x02000000  /* JTAG TCK pin (ppc output)     */
+#define CFG_FPGA_DATA		0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
+#define CFG_FPGA_INIT		0x00010000  /* unused (ppc input)	     */
+#define CFG_FPGA_DONE		0x00008000  /* JTAG TDI->TDO pin (ppc input) */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM        1
+#define CFG_TEMP_STACK_OCM	  1
 
 /* On Chip Memory location */
 #define CFG_OCM_DATA_ADDR	0xF8000000
@@ -292,13 +292,13 @@
 
 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Definitions for GPIO setup (PPC405EP specific)
  *
- * GPIO0[0]     - External Bus Controller BLAST output
- * GPIO0[1-9]   - Instruction trace outputs -> GPIO
+ * GPIO0[0]	- External Bus Controller BLAST output
+ * GPIO0[1-9]	- Instruction trace outputs -> GPIO
  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
@@ -306,17 +306,17 @@
  * GPIO0[28-29] - UART1 data signal input/output
  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
  */
-/* GPIO Input:          OSR=00, ISR=00, TSR=00, TCR=0 */
-/* GPIO Output:         OSR=00, ISR=00, TSR=00, TCR=1 */
-/* Alt. Funtion Input:  OSR=00, ISR=01, TSR=00, TCR=0 */
+/* GPIO Input:		OSR=00, ISR=00, TSR=00, TCR=0 */
+/* GPIO Output:		OSR=00, ISR=00, TSR=00, TCR=1 */
+/* Alt. Funtion Input:	OSR=00, ISR=01, TSR=00, TCR=0 */
 /* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
-#define CFG_GPIO0_OSRH          0x40000540  /*  0 ... 15 */
-#define CFG_GPIO0_OSRL          0x00000110  /* 16 ... 31 */
-#define CFG_GPIO0_ISR1H         0x00000000  /*  0 ... 15 */
-#define CFG_GPIO0_ISR1L         0x14000045  /* 16 ... 31 */
-#define CFG_GPIO0_TSRH          0x00000000  /*  0 ... 15 */
-#define CFG_GPIO0_TSRL          0x00000000  /* 16 ... 31 */
-#define CFG_GPIO0_TCR           0xF7FE0014  /*  0 ... 31 */
+#define CFG_GPIO0_OSRH		0x40000540  /*	0 ... 15 */
+#define CFG_GPIO0_OSRL		0x00000110  /* 16 ... 31 */
+#define CFG_GPIO0_ISR1H		0x00000000  /*	0 ... 15 */
+#define CFG_GPIO0_ISR1L		0x14000045  /* 16 ... 31 */
+#define CFG_GPIO0_TSRH		0x00000000  /*	0 ... 15 */
+#define CFG_GPIO0_TSRL		0x00000000  /* 16 ... 31 */
+#define CFG_GPIO0_TCR		0xF7FE0014  /*	0 ... 31 */
 
 /*
  * Internal Definitions
@@ -331,16 +331,16 @@
  * This value will be set if iic boot eprom is disabled.
  */
 #if 0
-#define PLLMR0_DEFAULT   PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT   PLLMR1_266_133_66_33
+#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
 #endif
 #if 0
-#define PLLMR0_DEFAULT   PLLMR0_200_100_50_33
-#define PLLMR1_DEFAULT   PLLMR1_200_100_50_33
+#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
+#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
 #endif
 #if 1
-#define PLLMR0_DEFAULT   PLLMR0_133_66_66_33
-#define PLLMR1_DEFAULT   PLLMR1_133_66_66_33
+#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
 #endif
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/DU405.h b/include/configs/DU405.h
index 3e5fc3fd44..5a5415a13e 100644
--- a/include/configs/DU405.h
+++ b/include/configs/DU405.h
@@ -34,12 +34,12 @@
  */
 
 #define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
-#define CONFIG_DU405	        1	/* ...on a DU405 board	        */
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_DU405		1	/* ...on a DU405 board		*/
 
-#define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
 
-#define CONFIG_SYS_CLK_FREQ     25000000 /* external frequency to pll   */
+#define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll	*/
 
 #define CONFIG_BAUDRATE		9600
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
@@ -51,7 +51,7 @@
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_MII		1	/* MII PHY management		*/
-#define	CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
 
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_PCI	| \
@@ -59,7 +59,7 @@
 				CFG_CMD_IDE	| \
 				CFG_CMD_ELF	| \
 				CFG_CMD_DATE	| \
-				CFG_CMD_EEPROM  )
+				CFG_CMD_EEPROM	)
 
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
@@ -69,10 +69,10 @@
 
 #undef CONFIG_WATCHDOG			/* watchdog disabled		*/
 
-#define CONFIG_RTC_MC146818             /* BQ3285 is MC146818 compatible*/
-#define CFG_RTC_REG_BASE_ADDR	 0xF0000080 /* RTC Base Address         */
+#define CONFIG_RTC_MC146818		/* BQ3285 is MC146818 compatible*/
+#define CFG_RTC_REG_BASE_ADDR	 0xF0000080 /* RTC Base Address		*/
 
-#define	CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 
 /*
  * Miscellaneous configurable options
@@ -80,30 +80,30 @@
 #define CFG_LONGHELP			/* undef to save memory		*/
 #define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 #define CFG_MAXARGS	16		/* max number of command args	*/
 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
 #define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define CFG_EXT_SERIAL_CLOCK    11059200  /* use external serial clock  */
+#define CFG_EXT_SERIAL_CLOCK	11059200  /* use external serial clock	*/
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE      \
+#define CFG_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
 #define CFG_LOAD_ADDR	0x100000	/* default load address */
 #define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
@@ -111,44 +111,44 @@
  * PCI stuff
  *-----------------------------------------------------------------------
  */
-#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
 
-#define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
-#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-					/* resource configuration       */
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_AUTO	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
 
-#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
 
-#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
+#define CONFIG_PCI_BOOTDELAY	0	/* enable pci bootdelay variable*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0404  /* PCI Device ID: CPCI-ISER4    */
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xff000001      /* 16MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0xffe00000      /* point to flash               */
-#define CFG_PCI_PTM2MS  0xffe00001      /* 2MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0404	/* PCI Device ID: CPCI-ISER4	*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0xff000001	/* 16MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0xffe00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xffe00001	/* 2MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff
  *-----------------------------------------------------------------------
  */
-#undef  CONFIG_IDE_8xx_DIRECT           /* no pcmcia interface required */
-#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
-#undef  CONFIG_IDE_RESET                /* no reset for ide supported   */
+#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+#undef	CONFIG_IDE_RESET		/* no reset for ide supported	*/
 
-#define	CFG_IDE_MAXBUS	        1		/* max. 1 IDE busses	*/
-#define	CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+#define CFG_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
+#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
 
-#define	CFG_ATA_BASE_ADDR	0xF0100000
-#define	CFG_ATA_IDE0_OFFSET	0x0000
+#define CFG_ATA_BASE_ADDR	0xF0100000
+#define CFG_ATA_IDE0_OFFSET	0x0000
 
 #define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
-#define	CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
 #define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
 
 /*-----------------------------------------------------------------------
@@ -177,18 +177,18 @@
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
-#define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
-#define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
-#define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
-#define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC08) for environment
@@ -198,18 +198,18 @@
 #define CFG_I2C_SLAVE		0x7F
 
 #define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
 #define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
 #define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
-					/* last	4 bits of the address	*/
+					/* last 4 bits of the address	*/
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 
-#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE            0x400   /* 1024 bytes may be used for env vars */
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x400	/* 1024 bytes may be used for env vars */
 				   /* total size of a CAT24WC08 is 1024 bytes */
 
 /*-----------------------------------------------------------------------
@@ -234,48 +234,48 @@
  * External Bus Controller (EBC) Setup
  */
 
-#define FLASH0_BA       0xFFC00000          /* FLASH 0 Base Address             */
-#define FLASH1_BA       0xFF800000          /* FLASH 1 Base Address             */
-#define CAN_BA          0xF0000000          /* CAN Base Address                 */
-#define DUART_BA        0xF0300000          /* DUART Base Address               */
-#define CF_BA           0xF0100000          /* CompactFlash Base Address        */
-#define SRAM_BA         0xF0200000          /* SRAM Base Address                */
-#define DURAG_IO_BA     0xF0400000          /* DURAG Bus IO Base Address        */
-#define DURAG_MEM_BA    0xF0500000          /* DURAG Bus Mem Base Address       */
+#define FLASH0_BA	0xFFC00000	    /* FLASH 0 Base Address		*/
+#define FLASH1_BA	0xFF800000	    /* FLASH 1 Base Address		*/
+#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
+#define DUART_BA	0xF0300000	    /* DUART Base Address		*/
+#define CF_BA		0xF0100000	    /* CompactFlash Base Address	*/
+#define SRAM_BA		0xF0200000	    /* SRAM Base Address		*/
+#define DURAG_IO_BA	0xF0400000	    /* DURAG Bus IO Base Address	*/
+#define DURAG_MEM_BA	0xF0500000	    /* DURAG Bus Mem Base Address	*/
 
-#define FPGA_MODE_REG   (DUART_BA+0x80)     /* FPGA Mode Register               */
+#define FPGA_MODE_REG	(DUART_BA+0x80)	    /* FPGA Mode Register		*/
 
-/* Memory Bank 0 (Flash Bank 0) initialization                                  */
-#define CFG_EBC_PB0AP   0x92015480
-#define CFG_EBC_PB0CR   FLASH0_BA | 0x5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CFG_EBC_PB0AP	0x92015480
+#define CFG_EBC_PB0CR	FLASH0_BA | 0x5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
-/* Memory Bank 1 (Flash Bank 1) initialization                                  */
-#define CFG_EBC_PB1AP   0x92015480
-#define CFG_EBC_PB1CR   FLASH1_BA | 0x5A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+/* Memory Bank 1 (Flash Bank 1) initialization					*/
+#define CFG_EBC_PB1AP	0x92015480
+#define CFG_EBC_PB1CR	FLASH1_BA | 0x5A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
 
-/* Memory Bank 2 (CAN0) initialization                                          */
-#define CFG_EBC_PB2AP   0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR   CAN_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+/* Memory Bank 2 (CAN0) initialization						*/
+#define CFG_EBC_PB2AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR	CAN_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 3 (DUART) initialization                                         */
-#define CFG_EBC_PB3AP   0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR   DUART_BA | 0x18000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit  */
+/* Memory Bank 3 (DUART) initialization						*/
+#define CFG_EBC_PB3AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR	DUART_BA | 0x18000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 4 (CompactFlash IDE) initialization                              */
-#define CFG_EBC_PB4AP   0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB4CR   CF_BA | 0x1A000     /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+/* Memory Bank 4 (CompactFlash IDE) initialization				*/
+#define CFG_EBC_PB4AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB4CR	CF_BA | 0x1A000	    /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 
-/* Memory Bank 5 (SRAM) initialization                                          */
-#define CFG_EBC_PB5AP   0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB5CR   SRAM_BA | 0x1A000   /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */
+/* Memory Bank 5 (SRAM) initialization						*/
+#define CFG_EBC_PB5AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB5CR	SRAM_BA | 0x1A000   /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */
 
-/* Memory Bank 6 (DURAG Bus IO Space) initialization                            */
-#define CFG_EBC_PB6AP   0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB6CR   DURAG_IO_BA | 0x18000 /* BAS=0xF04,BS=1MB,BU=R/W,BW=8bit*/
+/* Memory Bank 6 (DURAG Bus IO Space) initialization				*/
+#define CFG_EBC_PB6AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB6CR	DURAG_IO_BA | 0x18000 /* BAS=0xF04,BS=1MB,BU=R/W,BW=8bit*/
 
-/* Memory Bank 7 (DURAG Bus Mem Space) initialization                           */
-#define CFG_EBC_PB7AP   0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB7CR   DURAG_MEM_BA | 0x18000 /* BAS=0xF05,BS=1MB,BU=R/W,BW=8bit */
+/* Memory Bank 7 (DURAG Bus Mem Space) initialization				*/
+#define CFG_EBC_PB7AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB7CR	DURAG_MEM_BA | 0x18000 /* BAS=0xF05,BS=1MB,BU=R/W,BW=8bit */
 
 
 /*-----------------------------------------------------------------------
@@ -283,7 +283,7 @@
  */
 
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM        1
+#define CFG_TEMP_STACK_OCM	  1
 
 /* On Chip Memory location */
 #define CFG_OCM_DATA_ADDR	0xF8000000
@@ -293,7 +293,7 @@
 #define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
 
 /*
diff --git a/include/configs/EBONY.h b/include/configs/EBONY.h
index aecb3c2996..46e729f15d 100644
--- a/include/configs/EBONY.h
+++ b/include/configs/EBONY.h
@@ -32,7 +32,7 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_EBONY		1	    /* Board is ebony		*/
 #define CONFIG_4xx		1	    /* ... PPC4xx family	*/
-#define CONFIG_BOARD_PRE_INIT	1	    /* Call board_pre_init	*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
 #undef	CFG_DRAM_TEST			    /* Disable-takes long time! */
 #define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
 
diff --git a/include/configs/ELPT860.h b/include/configs/ELPT860.h
index 2f253b9787..5bfdc9be12 100644
--- a/include/configs/ELPT860.h
+++ b/include/configs/ELPT860.h
@@ -19,7 +19,7 @@
 **
 ** This program is distributed in the hope that it will be useful,
 ** but WITHOUT ANY WARRANTY; without even the implied warranty of
-** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 ** GNU General Public License for more details.
 **
 ** You should have received a copy of the GNU General Public License
@@ -47,26 +47,26 @@
 #define CONFIG_MPC860T		1
 #define CONFIG_ELPT860		1	/* ...on a LEOX's ELPT860 CPU board */
 
-#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		    */
+#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		    */
 #undef	  CONFIG_8xx_CONS_SMC2
 #undef	  CONFIG_8xx_CONS_NONE
 
-#define CONFIG_CLOCKS_IN_MHZ    1  /* Clock passed to Linux (<2.4.5) in MHz */
-#define CONFIG_8xx_GCLK_FREQ    50000000       /* MPC860T runs at 50MHz */
+#define CONFIG_CLOCKS_IN_MHZ	1  /* Clock passed to Linux (<2.4.5) in MHz */
+#define CONFIG_8xx_GCLK_FREQ	50000000       /* MPC860T runs at 50MHz */
 
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
-#define CONFIG_BOARD_PRE_INIT   1       /* Call board_pre_init          */
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
 
 /* BOOT arguments */
-#define CONFIG_PREBOOT                                                     \
-     "echo;"	                                                           \
-     "echo Type \"run nfsboot\" to mount root filesystem over NFS;"        \
+#define CONFIG_PREBOOT							   \
+     "echo;"								   \
+     "echo Type \"run nfsboot\" to mount root filesystem over NFS;"	   \
      "echo"
 
 #undef	  CONFIG_BOOTARGS
 
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
+#define CONFIG_EXTRA_ENV_SETTINGS					\
     "ramargs=setenv bootargs root=/dev/ram rw\0"			\
     "rootargs=setenv rootpath /tftp/$(ipaddr)\0"			\
     "nfsargs=setenv bootargs root=/dev/nfs rw "				\
@@ -86,14 +86,14 @@
 #undef	  CONFIG_WATCHDOG		/* watchdog disabled		*/
 #undef	  CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
 #undef	  CONFIG_RTC_MPC8xx		/* internal RTC MPC8xx unused	*/
-#define CONFIG_RTC_DS164x       1       /* RTC is a Dallas DS1646       */
+#define CONFIG_RTC_DS164x	1	/* RTC is a Dallas DS1646	*/
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #undef	  CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
-#define CONFIG_COMMANDS	        ( CONFIG_CMD_DFL | \
+#define CONFIG_COMMANDS		( CONFIG_CMD_DFL | \
 				  CFG_CMD_ASKENV | \
-				  CFG_CMD_DATE   )
+				  CFG_CMD_DATE	 )
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
@@ -101,8 +101,8 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT     "LEOX_elpt860: "	/* Monitor Command Prompt	*/
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT     "LEOX_elpt860: " /* Monitor Command Prompt	*/
 
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #  define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
@@ -110,35 +110,35 @@
 #  define CFG_CBSIZE	 256		/* Console I/O Buffer Size	*/
 #endif
 
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	  16		/* max number of command args	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	  16		/* max number of command args	*/
 #define CFG_BARGSIZE	  CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 
 #define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x00C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x00100000	/* default load address	*/
+#define CFG_LOAD_ADDR		0x00100000	/* default load address */
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 /*
  * Environment Variables and Storages
  */
-#define CONFIG_ENV_OVERWRITE    1  /* Allow Overwrite of serial# & ethaddr */
+#define CONFIG_ENV_OVERWRITE	1  /* Allow Overwrite of serial# & ethaddr */
 
-#undef    CFG_ENV_IS_IN_NVRAM          /* Environment is in NVRAM       */
-#undef    CFG_ENV_IS_IN_EEPROM         /* Environment is in I2C EEPROM  */
-#define CFG_ENV_IS_IN_FLASH     1      /* Environment is in FLASH       */
+#undef	  CFG_ENV_IS_IN_NVRAM	       /* Environment is in NVRAM	*/
+#undef	  CFG_ENV_IS_IN_EEPROM	       /* Environment is in I2C EEPROM	*/
+#define CFG_ENV_IS_IN_FLASH	1      /* Environment is in FLASH	*/
 
-#define CONFIG_BAUDRATE		9600   /* console baudrate = 9600 bps   */
+#define CONFIG_BAUDRATE		9600   /* console baudrate = 9600 bps	*/
 #define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
-#define CONFIG_ETHADDR          00:01:77:00:60:40
-#define CONFIG_IPADDR           192.168.0.30
-#define CONFIG_NETMASK          255.255.255.0
+#define CONFIG_ETHADDR		00:01:77:00:60:40
+#define CONFIG_IPADDR		192.168.0.30
+#define CONFIG_NETMASK		255.255.255.0
 
-#define CONFIG_SERVERIP         192.168.0.1
-#define CONFIG_GATEWAYIP        192.168.0.1
+#define CONFIG_SERVERIP		192.168.0.1
+#define CONFIG_GATEWAYIP	192.168.0.1
 
 /*
  * Low Level Configuration Settings
@@ -155,19 +155,19 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
  * Please note that CFG_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_SDRAM_BASE		0x00000000
 #define CFG_FLASH_BASE		0x02000000
-#define CFG_NVRAM_BASE          0x03000000
+#define CFG_NVRAM_BASE		0x03000000
 
 #if defined(CFG_ENV_IS_IN_FLASH)
 #  if defined(DEBUG)
@@ -184,48 +184,48 @@
 #endif
 
 #define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)  /* Reserve 128 kB for malloc() */
+#define CFG_MALLOC_LEN		(128 << 10)  /* Reserve 128 kB for malloc() */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)    /* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ		(8 << 20)    /* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks        */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks	     */
 #define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip */
 
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)   */
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)   */
 
 #if defined(CFG_ENV_IS_IN_FLASH)
-#  define CFG_ENV_OFFSET        0x10000	/* Offset   of Environment Sector    */
-#  define CFG_ENV_SIZE          0x10000 /* Total Size of Environment Sector  */
+#  define CFG_ENV_OFFSET	0x10000 /* Offset   of Environment Sector    */
+#  define CFG_ENV_SIZE		0x10000 /* Total Size of Environment Sector  */
 #endif
 
 /*-----------------------------------------------------------------------
  * NVRAM organization
  */
-#define CFG_NVRAM_BASE_ADDR     CFG_NVRAM_BASE /* Base address of NVRAM area */
-#define CFG_NVRAM_SIZE          ((128*1024)-8) /* clock regs resident in the */
+#define CFG_NVRAM_BASE_ADDR	CFG_NVRAM_BASE /* Base address of NVRAM area */
+#define CFG_NVRAM_SIZE		((128*1024)-8) /* clock regs resident in the */
 					       /*   8 top NVRAM locations    */
 
 #if defined(CFG_ENV_IS_IN_NVRAM)
-#  define CFG_ENV_ADDR          CFG_NVRAM_BASE /* Base address of NVRAM area */
-#  define CFG_ENV_SIZE          0x4000	/* Total Size of Environment Sector  */
+#  define CFG_ENV_ADDR		CFG_NVRAM_BASE /* Base address of NVRAM area */
+#  define CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector  */
 #endif
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs               */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs		     */
 
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	 4      /* log base 2 of the above value     */
+#  define CFG_CACHELINE_SHIFT	 4	/* log base 2 of the above value     */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -235,10 +235,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#  define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT  | SYPCR_BME | SYPCR_SWF | \
+#  define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT	 | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI | SYPCR_SWP)
 #else
-#  define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT  | SYPCR_BME | SYPCR_SWF | \
+#  define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT	 | SYPCR_BME | SYPCR_SWF | \
 						   SYPCR_SWP)
 #endif
 
@@ -309,7 +309,7 @@
  * BR0 and OR0 (FLASH)
  */
 
-#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0          */
+#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0	  */
 
 /* used to re-map FLASH both when starting from SRAM or FLASH:
  * restrict access enough to keep SRAM working (if any)
@@ -327,10 +327,10 @@
  * BR1 and OR1 (SDRAM)
  *
  */
-#define SDRAM_BASE1_PRELIM	CFG_SDRAM_BASE	/* SDRAM bank #0        */
-#define	SDRAM_MAX_SIZE		0x02000000	/* 32 MB MAX for CS1    */
+#define SDRAM_BASE1_PRELIM	CFG_SDRAM_BASE	/* SDRAM bank #0	*/
+#define SDRAM_MAX_SIZE		0x02000000	/* 32 MB MAX for CS1	*/
 
-/* SDRAM timing:                                                        */
+/* SDRAM timing:							*/
 #define CFG_OR_TIMING_SDRAM	0x00000000
 
 #define CFG_OR1_PRELIM	((2 * CFG_PRELIM_OR_AM) | CFG_OR_TIMING_SDRAM )
@@ -340,10 +340,10 @@
  * BR2 and OR2 (NVRAM)
  *
  */
-#define NVRAM_BASE1_PRELIM	CFG_NVRAM_BASE	/* NVRAM bank #0        */
-#define	NVRAM_MAX_SIZE		0x00020000	/* 128 KB MAX for CS2   */
+#define NVRAM_BASE1_PRELIM	CFG_NVRAM_BASE	/* NVRAM bank #0	*/
+#define NVRAM_MAX_SIZE		0x00020000	/* 128 KB MAX for CS2	*/
 
-#define CFG_OR2_PRELIM	        0xFFF80160
+#define CFG_OR2_PRELIM		0xFFF80160
 #define CFG_BR2_PRELIM	((NVRAM_BASE1_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
 
 /*
@@ -351,15 +351,15 @@
  */
 
 /* periodic timer for refresh */
-#define CFG_MAMR_PTA	        97     /* start with divider for 100 MHz */
+#define CFG_MAMR_PTA		97     /* start with divider for 100 MHz */
 
 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
 #define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16	  /* setting for 2 banks */
-#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32	  /* setting for 1 bank  */
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32	  /* setting for 1 bank	 */
 
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit  */
-#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8    /* setting for 2 banks */
-#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16   /* setting for 1 bank  */
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit	 */
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8	  /* setting for 2 banks */
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16	  /* setting for 1 bank	 */
 
 /*
  * MAMR settings for SDRAM
@@ -383,8 +383,8 @@
 /*
  * Boot Flags
  */
-#define	BOOTFLAG_COLD	0x01             /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM	0x02             /* Software reboot                  */
+#define BOOTFLAG_COLD	0x01		 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		 /* Software reboot		     */
 
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/ERIC.h b/include/configs/ERIC.h
index 539716f2c5..1643dee4c9 100644
--- a/include/configs/ERIC.h
+++ b/include/configs/ERIC.h
@@ -37,7 +37,7 @@
 #define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_ERIC		1	/* ...on a ERIC board	*/
 
-#define	CONFIG_BOARD_PRE_INIT	1	/* run board_pre_init() */
+#define	CONFIG_BOARD_EARLY_INIT_F 1	/* run board_early_init_f() */
 
 #define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll	*/
 
diff --git a/include/configs/EVB64260.h b/include/configs/EVB64260.h
index af5122f6f0..9baf252f61 100644
--- a/include/configs/EVB64260.h
+++ b/include/configs/EVB64260.h
@@ -51,7 +51,7 @@
 
 /* which initialization functions to call for this board */
 #define CONFIG_MISC_INIT_R	1
-#define CONFIG_BOARD_PRE_INIT	1
+#define CONFIG_BOARD_EARLY_INIT_F 1
 
 #ifndef CONFIG_EVB64260_750CX
 #define CFG_BOARD_NAME		"EVB64260"
diff --git a/include/configs/EXBITGEN.h b/include/configs/EXBITGEN.h
index 4e7051947c..d85be424a2 100644
--- a/include/configs/EXBITGEN.h
+++ b/include/configs/EXBITGEN.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -37,7 +37,7 @@
 #define CONFIG_4xx		1	/* ...member of PPC4xx family   */
 #define CONFIG_EXBITGEN		1	/* on a Exbit Generic board     */
 
-#define CONFIG_BOARD_PRE_INIT	1	/* Call board_pre_init		*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
 
 #define CONFIG_SYS_CLK_FREQ     25000000 /* external frequency to pll   */
 
diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h
index e4dbc7abfb..ff0d8d08c1 100644
--- a/include/configs/HUB405.h
+++ b/include/configs/HUB405.h
@@ -34,13 +34,13 @@
  */
 
 #define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
-#define CONFIG_HUB405		1	/* ...on a ASH405 board 	*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_HUB405		1	/* ...on a ASH405 board		*/
 
-#define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */
-#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
 
-#define CONFIG_SYS_CLK_FREQ     33333334 /* external frequency to pll   */
+#define CONFIG_SYS_CLK_FREQ	33333334 /* external frequency to pll	*/
 
 #define CONFIG_BAUDRATE		9600
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
@@ -60,7 +60,7 @@
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_MII		1	/* MII PHY management		*/
-#define	CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
 
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_DHCP	| \
@@ -70,14 +70,14 @@
 				CFG_CMD_I2C	| \
 				CFG_CMD_MII	| \
 				CFG_CMD_PING	| \
-				CFG_CMD_EEPROM  )
+				CFG_CMD_EEPROM	)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
-#undef  CONFIG_WATCHDOG			/* watchdog disabled		*/
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
-#define	CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 
 /*
  * Miscellaneous configurable options
@@ -87,45 +87,45 @@
 
 #undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
 #ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CFG_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 #define CFG_MAXARGS	16		/* max number of command args	*/
 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
 
-#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
 #define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
-#define CFG_BASE_BAUD       691200
-#undef  CONFIG_UART1_CONSOLE            /* define for uart1 as console  */
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD	    691200
+#undef	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE      \
+#define CFG_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
 #define CFG_LOAD_ADDR	0x100000	/* default load address */
 #define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
-#define CONFIG_VERSION_VARIABLE	1       /* include version env variable */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
-#define CFG_RX_ETH_BUFFER	16      /* use 16 rx buffer on 405 emac */
+#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
 
 /*-----------------------------------------------------------------------
  * NAND-FLASH stuff
@@ -138,14 +138,14 @@
 #define ADDR_PAGE 2
 #define ADDR_COLUMN_PAGE 3
 
-#define NAND_ChipID_UNKNOWN 	0x00
+#define NAND_ChipID_UNKNOWN	0x00
 #define NAND_MAX_FLOORS 1
 #define NAND_MAX_CHIPS 1
 
-#define CFG_NAND_CE  (0x80000000 >> 1)  /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2)  /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3)  /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4)  /* our RDY is GPIO4 */
+#define CFG_NAND_CE  (0x80000000 >> 1)	/* our CE is GPIO1 */
+#define CFG_NAND_CLE (0x80000000 >> 2)	/* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3)	/* our ALE is GPIO3 */
+#define CFG_NAND_RDY (0x80000000 >> 4)	/* our RDY is GPIO4 */
 
 #define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
 #define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
@@ -164,26 +164,26 @@
  * PCI stuff
  *-----------------------------------------------------------------------
  */
-#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
-
-#undef  CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_HOST	PCI_HOST_HOST   /* select pci host function     */
-#undef  CONFIG_PCI_PNP			/* do pci plug-and-play         */
-					/* resource configuration       */
-
-#undef  CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
-#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#undef	CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_HOST	/* select pci host function	*/
+#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
+#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
@@ -211,34 +211,34 @@
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
-#define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
-#define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
-#define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
-#define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS     1           /* ! second bank contains U-Boot */
+#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
 #endif
 
 /*-----------------------------------------------------------------------
  * Environment Variable setup
  */
-#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET          0x100   /* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE            0x700   /* 2048 bytes may be used for env vars*/
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
 				   /* total size of a CAT24WC16 is 2048 bytes */
 
 #define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		242		        /* NVRAM size		*/
+#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
 
 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC16) for environment
@@ -248,20 +248,20 @@
 #define CFG_I2C_SLAVE		0x7F
 
 #define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
 #define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
 #define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
-					/* last	4 bits of the address	*/
+					/* last 4 bits of the address	*/
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's    */
-					/* have only 8kB, 16kB is save here     */
+#define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's	*/
+					/* have only 8kB, 16kB is save here	*/
 #define CFG_CACHELINE_SIZE	32	/* ...			*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
@@ -279,48 +279,48 @@
  * External Bus Controller (EBC) Setup
  */
 
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
-#define CFG_EBC_PB0AP           0x92015480
-/*#define CFG_EBC_PB0AP           0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
-#define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CFG_EBC_PB0AP		0x92015480
+/*#define CFG_EBC_PB0AP		  0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
-/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization                      */
-#define CFG_EBC_PB1AP           0x92015480
-#define CFG_EBC_PB1CR           0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit  */
+/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
+#define CFG_EBC_PB1AP		0x92015480
+#define CFG_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 2 (8 Bit Peripheral: UART) initialization                        */
+/* Memory Bank 2 (8 Bit Peripheral: UART) initialization			*/
 #if 0
-#define CFG_EBC_PB2AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 #else
-#define CFG_EBC_PB2AP           0x92015480
-#define CFG_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+#define CFG_EBC_PB2AP		0x92015480
+#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 #endif
 
-#define DUART0_BA       0xF0000000          /* DUART Base Address               */
-#define DUART1_BA       0xF0000008          /* DUART Base Address               */
-#define DUART2_BA       0xF0000010          /* DUART Base Address               */
-#define DUART3_BA       0xF0000018          /* DUART Base Address               */
-#define CFG_NAND_BASE   0xF4000000
+#define DUART0_BA	0xF0000000	    /* DUART Base Address		*/
+#define DUART1_BA	0xF0000008	    /* DUART Base Address		*/
+#define DUART2_BA	0xF0000010	    /* DUART Base Address		*/
+#define DUART3_BA	0xF0000018	    /* DUART Base Address		*/
+#define CFG_NAND_BASE	0xF4000000
 
 /*-----------------------------------------------------------------------
  * FPGA stuff
  */
-#define CFG_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
-#define CFG_FPGA_MAX_SIZE       128*1024    /* 128kByte is enough for XC2S50E*/
+#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CFG_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/
 
 /* FPGA program pin configuration */
-#define CFG_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */
+#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
+#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM        1
+#define CFG_TEMP_STACK_OCM	  1
 
 /* On Chip Memory location */
 #define CFG_OCM_DATA_ADDR	0xF8000000
@@ -330,13 +330,13 @@
 
 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Definitions for GPIO setup (PPC405EP specific)
  *
- * GPIO0[0]     - External Bus Controller BLAST output
- * GPIO0[1-9]   - Instruction trace outputs -> GPIO
+ * GPIO0[0]	- External Bus Controller BLAST output
+ * GPIO0[1-9]	- Instruction trace outputs -> GPIO
  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
@@ -344,15 +344,15 @@
  * GPIO0[28-29] - UART1 data signal input/output
  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
  */
-#define CFG_GPIO0_OSRH          0x40000550
-#define CFG_GPIO0_OSRL          0x00000110
-#define CFG_GPIO0_ISR1H         0x00000000
-#define CFG_GPIO0_ISR1L         0x15555445
-#define CFG_GPIO0_TSRH          0x00000000
-#define CFG_GPIO0_TSRL          0x00000000
-#define CFG_GPIO0_TCR           0xF7FE0014
+#define CFG_GPIO0_OSRH		0x40000550
+#define CFG_GPIO0_OSRL		0x00000110
+#define CFG_GPIO0_ISR1H		0x00000000
+#define CFG_GPIO0_ISR1L		0x15555445
+#define CFG_GPIO0_TSRH		0x00000000
+#define CFG_GPIO0_TSRL		0x00000000
+#define CFG_GPIO0_TCR		0xF7FE0014
 
-#define CFG_DUART_RST           (0x80000000 >> 14)
+#define CFG_DUART_RST		(0x80000000 >> 14)
 
 /*
  * Internal Definitions
@@ -367,16 +367,16 @@
  * This value will be set if iic boot eprom is disabled.
  */
 #if 0
-#define PLLMR0_DEFAULT   PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT   PLLMR1_266_133_66_33
+#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
 #endif
 #if 0
-#define PLLMR0_DEFAULT   PLLMR0_200_100_50_33
-#define PLLMR1_DEFAULT   PLLMR1_200_100_50_33
+#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
+#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
 #endif
 #if 1
-#define PLLMR0_DEFAULT   PLLMR0_133_66_66_33
-#define PLLMR1_DEFAULT   PLLMR1_133_66_66_33
+#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
 #endif
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/IAD210.h b/include/configs/IAD210.h
index 6dedbd7770..fd15b85c22 100644
--- a/include/configs/IAD210.h
+++ b/include/configs/IAD210.h
@@ -66,7 +66,7 @@
 #define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
 
 /* using this define saves us updating another source file */
-#define CONFIG_BOARD_PRE_INIT  1
+#define CONFIG_BOARD_EARLY_INIT_F 1
 
 #undef	CONFIG_BOOTARGS
 /* #define CONFIG_BOOTCOMMAND							\
diff --git a/include/configs/IP860.h b/include/configs/IP860.h
index 649096274f..47f69a248d 100644
--- a/include/configs/IP860.h
+++ b/include/configs/IP860.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -35,7 +35,7 @@
 
 #define CONFIG_MPC860		1	/* This is a MPC860 CPU		*/
 #define CONFIG_IP860		1	/* ...on a IP860 board		*/
-#define CONFIG_BOARD_PRE_INIT	1	    /* Call board_pre_init	*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
 
 #define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
 #define CONFIG_BAUDRATE		9600
diff --git a/include/configs/MHPC.h b/include/configs/MHPC.h
index e36341fd1e..f942e95549 100644
--- a/include/configs/MHPC.h
+++ b/include/configs/MHPC.h
@@ -18,7 +18,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -39,23 +39,23 @@
  * (easy to change)
  */
 #define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
-#define CONFIG_MHPC 		1	/* on a miniHiPerCam	        */
-#define CONFIG_BOARD_PRE_INIT   1       /* do special hardware init.    */
-#define CONFIG_MISC_INIT_R      1
+#define CONFIG_MHPC		1	/* on a miniHiPerCam		*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* do special hardware init.	*/
+#define CONFIG_MISC_INIT_R	1
 
 #define CONFIG_8xx_GCLK_FREQ	MPC8XX_SPEED
 #undef	CONFIG_8xx_CONS_SMC1
-#define	CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
+#define CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
 #undef	CONFIG_8xx_CONS_NONE
 #define CONFIG_BAUDRATE		9600
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
-#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+#define CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
 
-#define CONFIG_ENV_OVERWRITE    1
-#define CONFIG_ETHADDR          00:00:5b:ee:de:ad
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_ETHADDR		00:00:5b:ee:de:ad
 
-#undef  CONFIG_BOOTARGS
+#undef	CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND	\
 	"bootp;"								\
 	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "	\
@@ -66,12 +66,12 @@
 #undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+#define CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
 
-#undef  CONFIG_UCODE_PATCH
+#undef	CONFIG_UCODE_PATCH
 
 /* enable I2C and select the hardware/software driver */
-#undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
 #define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
 /*
  * Software (bit-bang) I2C driver configuration
@@ -84,36 +84,36 @@
 #define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
 #define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 #define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
-			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+			else	immr->im_cpm.cp_pbdat &= ~PB_SDA
 #define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
-			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+			else	immr->im_cpm.cp_pbdat &= ~PB_SCL
 #define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
 
-#define CFG_I2C_SPEED                   50000
-#define CFG_I2C_SLAVE                   0xFE
-#define CFG_I2C_EEPROM_ADDR             0x50    /* EEPROM X24C04		*/
-#define CFG_I2C_EEPROM_ADDR_LEN         1       /* bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"    */
-#define CFG_I2C_EEPROM_ADDR_OVERFLOW    0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS      3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10
-
-#define LCD_VIDEO_ADDR          (SDRAM_MAX_SIZE-SDRAM_RES_SIZE)
-#define LCD_VIDEO_SIZE          SDRAM_RES_SIZE  /* 2MB */
-#define LCD_VIDEO_COLS          640
-#define LCD_VIDEO_ROWS          480
-#define LCD_VIDEO_FG            255
-#define LCD_VIDEO_BG            0
-
-#undef  CONFIG_VIDEO                            /* test only ! s.a devices.c and 8xx */
-#define CONFIG_CFB_CONSOLE                      /* framebuffer console with std input */
+#define CFG_I2C_SPEED			50000
+#define CFG_I2C_SLAVE			0xFE
+#define CFG_I2C_EEPROM_ADDR		0x50	/* EEPROM X24C04		*/
+#define CFG_I2C_EEPROM_ADDR_LEN		1	/* bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS	3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+#define LCD_VIDEO_ADDR		(SDRAM_MAX_SIZE-SDRAM_RES_SIZE)
+#define LCD_VIDEO_SIZE		SDRAM_RES_SIZE	/* 2MB */
+#define LCD_VIDEO_COLS		640
+#define LCD_VIDEO_ROWS		480
+#define LCD_VIDEO_FG		255
+#define LCD_VIDEO_BG		0
+
+#undef	CONFIG_VIDEO				/* test only ! s.a devices.c and 8xx */
+#define CONFIG_CFB_CONSOLE			/* framebuffer console with std input */
 #define CONFIG_VIDEO_LOGO
 
-#define VIDEO_KBD_INIT_FCT      0               /* no KBD dev on MHPC - use serial */
-#define VIDEO_TSTC_FCT          serial_tstc
-#define VIDEO_GETC_FCT          serial_getc
+#define VIDEO_KBD_INIT_FCT	0		/* no KBD dev on MHPC - use serial */
+#define VIDEO_TSTC_FCT		serial_tstc
+#define VIDEO_GETC_FCT		serial_getc
 
-#define CONFIG_BR0_WORKAROUND   1
+#define CONFIG_BR0_WORKAROUND	1
 
 #define CONFIG_COMMANDS	     ( CONFIG_CMD_DFL  | \
 			       CFG_CMD_DATE    | \
@@ -131,23 +131,23 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 
 #define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x300000	/* default load address	*/
+#define CFG_LOAD_ADDR		0x300000	/* default load address */
 
-#define	CFG_HZ                  1000		/* decrementer freq: 1 ms ticks	*/
+#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
 
 #define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
@@ -166,33 +166,33 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
  * Please note that CFG_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_SDRAM_BASE		0x00000000
 #define CFG_FLASH_BASE		0xfe000000
 
-#define	CFG_MONITOR_LEN		0x40000 	/* Reserve 256 kB for Monitor	*/
-#undef  CFG_MONITOR_BASE	            /* to run U-Boot from RAM */
+#define CFG_MONITOR_LEN		0x40000		/* Reserve 256 kB for Monitor	*/
+#undef	CFG_MONITOR_BASE		    /* to run U-Boot from RAM */
 #define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
-#define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS     1           /* one flash only */
+#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS	1	    /* one flash only */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map- for Linux	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map- for Linux	*/
 
 /*-----------------------------------------------------------------------
  * FLASH organization
@@ -202,9 +202,9 @@
 
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_OFFSET		CFG_MONITOR_LEN	/* Offset of Environment */
-#define	CFG_ENV_SIZE		0x20000	/* Total Size of Environment 	*/
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET		CFG_MONITOR_LEN /* Offset of Environment */
+#define CFG_ENV_SIZE		0x20000 /* Total Size of Environment	*/
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
@@ -262,7 +262,7 @@
  * interrupt status bit - leave PLL multiplication factor unchanged !
  */
 #define MPC8XX_SPEED	50000000L
-#define MPC8XX_XIN   	5000000L      /* ref clk */
+#define MPC8XX_XIN	5000000L      /* ref clk */
 #define MPC8XX_FACT	(MPC8XX_SPEED/MPC8XX_XIN)
 #define CFG_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
 			PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
@@ -307,8 +307,8 @@
  * BR1 and OR1 (SDRAM)
  */
 #define SDRAM_BASE1_PRELIM	0x00000000	/* SDRAM bank #0	*/
-#define SDRAM_MAX_SIZE		0x01000000	/* max 16 MB    	*/
-#define SDRAM_RES_SIZE          0x00200000      /* 2 MB for framebuffer */
+#define SDRAM_MAX_SIZE		0x01000000	/* max 16 MB		*/
+#define SDRAM_RES_SIZE		0x00200000	/* 2 MB for framebuffer */
 
 /* SDRAM timing: drive GPL5 high on first cycle */
 #define CFG_OR_TIMING_SDRAM	(OR_G5LS)
@@ -358,14 +358,14 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_DER	0
+#define CFG_DER 0
 
 /*
  * Internal Definitions
  *
  * Boot Flags
  */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
 #define BOOTFLAG_WARM	0x02		/* Software reboot			*/
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
index 9c21745c49..cfe74e1b6f 100644
--- a/include/configs/MIP405.h
+++ b/include/configs/MIP405.h
@@ -252,7 +252,7 @@
 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
 #define FLASH_SIZE_PRELIM	 3  /* maximal flash FLASH size bank #0	*/
 
-#define CONFIG_BOARD_PRE_INIT
+#define CONFIG_BOARD_EARLY_INIT_F 1
 
 /* Peripheral Bus Mapping */
 #define PER_PLD_ADDR		0xF4000000 /* smallest window is 1MByte 0x10 0000*/
diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h
index 9625cdf176..f4ccdafba5 100644
--- a/include/configs/MPC8260ADS.h
+++ b/include/configs/MPC8260ADS.h
@@ -51,7 +51,7 @@
 #define CONFIG_ADSTYPE		CFG_8260ADS
 #endif /* CONFIG_ADSTYPE */
 
-#define CONFIG_BOARD_PRE_INIT	1	/* Call board_pre_init	*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
 
 /* allow serial and ethaddr to be overwritten */
 #define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h
index 26c13068ef..c62f942d51 100644
--- a/include/configs/MPC8266ADS.h
+++ b/include/configs/MPC8266ADS.h
@@ -49,10 +49,10 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU   */
-#define CONFIG_MPC8266ADS	1	/* ...on motorola ads board */
+#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU	*/
+#define CONFIG_MPC8266ADS	1	/* ...on motorola ADS board	*/
 
-#define CONFIG_BOARD_PRE_INIT	1	/* Call board_pre_init	*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
 
 /* allow serial and ethaddr to be overwritten */
 #define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 951d1fefb0..2f1bb487f8 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -31,21 +31,21 @@
 #define __CONFIG_H
 
 /* High Level Configuration Options */
-#define CONFIG_BOOKE		1	    /* BOOKE 			*/
+#define CONFIG_BOOKE		1	    /* BOOKE			*/
 #define CONFIG_E500		1	    /* BOOKE e500 family	*/
 #define CONFIG_MPC85xx		1	    /* MPC8540/MPC8560		*/
-#define CONFIG_MPC85xx_REV1	1	    /* MPC85xx Rev 1 Chip       */
-#define CONFIG_MPC8540		1	    /* MPC8540 specific	        */
+#define CONFIG_MPC85xx_REV1	1	    /* MPC85xx Rev 1 Chip	*/
+#define CONFIG_MPC8540		1	    /* MPC8540 specific		*/
 #define CONFIG_MPC8540ADS	1	    /* MPC8540ADS board specific*/
 
-#undef  CONFIG_PCI	         	    /* pci ethernet support	*/
-#define CONFIG_TSEC_ENET 		    /* tsec ethernet support  */
+#undef	CONFIG_PCI			    /* pci ethernet support	*/
+#define CONFIG_TSEC_ENET		    /* tsec ethernet support  */
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM                   /* Use SPD EEPROM for DDR setup */
-#undef  CONFIG_DDR_ECC			    /* only for ECC DDR module */
+#define CONFIG_SPD_EEPROM		    /* Use SPD EEPROM for DDR setup */
+#undef	CONFIG_DDR_ECC			    /* only for ECC DDR module */
 
 #if defined(CONFIG_MPC85xx_REV1)
-#define CONFIG_DDR_DLL                      /* possible DLL fix needed */
+#define CONFIG_DDR_DLL			    /* possible DLL fix needed */
 #endif
 
 /* Using Localbus SDRAM to emulate flash before we can program the flash,
@@ -53,24 +53,24 @@
  */
 #undef CONFIG_RAM_AS_FLASH
 
-#if !defined(CONFIG_PCI) 		    /* some PCI card is 33Mhz only */
+#if !defined(CONFIG_PCI)		    /* some PCI card is 33Mhz only */
 #define CONFIG_SYS_CLK_FREQ	66000000    /* sysclk for MPC85xx	*/
 #else
 #define CONFIG_SYS_CLK_FREQ	33000000    /* most pci cards are 33Mhz */
 #endif
 
-#if !defined(CONFIG_SPD_EEPROM)             /* manually set up DDR parameters */
+#if !defined(CONFIG_SPD_EEPROM)		    /* manually set up DDR parameters */
 #define CONFIG_DDR_SETTING
 #endif
 
 /* below can be toggled for performance analysis. otherwise use default */
-#define CONFIG_L2_CACHE		    	    /* toggle L2 cache 	*/
-#undef  CONFIG_BTB			    /* toggle branch predition */
-#undef  CONFIG_ADDR_STREAMING		    /* toggle addr streaming   */
+#define CONFIG_L2_CACHE			    /* toggle L2 cache	*/
+#undef	CONFIG_BTB			    /* toggle branch predition	*/
+#undef	CONFIG_ADDR_STREAMING		    /* toggle addr streaming	*/
 
-#define CONFIG_BOARD_PRE_INIT	1	    /* Call board_pre_init	*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
 
-#undef	CFG_DRAM_TEST			    /* memory test, takes time  */
+#undef	CFG_DRAM_TEST			    /* memory test, takes time	*/
 #define CFG_MEMTEST_START	0x00200000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x00400000
 
@@ -82,13 +82,13 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default	*/
-#define CFG_CCSRBAR		0xfdf00000	/* relocated CCSRBAR 	*/
+#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default	*/
+#define CFG_CCSRBAR		0xfdf00000	/* relocated CCSRBAR	*/
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory  */
+#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory	 */
 #define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
-#define CFG_SDRAM_SIZE		128             /* DDR is now 128MB     */
+#define CFG_SDRAM_SIZE		128		/* DDR is now 128MB	*/
 
 #if defined(CONFIG_RAM_AS_FLASH)
 #define CFG_LBC_SDRAM_BASE	0xfc000000	/* Localbus SDRAM */
@@ -98,44 +98,44 @@
 #define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB	*/
 
 #if defined(CONFIG_RAM_AS_FLASH)
-#define CFG_FLASH_BASE    	0xf8000000	/* start of FLASH  16M	*/
+#define CFG_FLASH_BASE		0xf8000000	/* start of FLASH  16M	*/
 #define CFG_BR0_PRELIM		0xf8001801	/* port size 32bit */
 #else /* Boot from real Flash */
-#define CFG_FLASH_BASE		0xff000000	/* start of FLASH 16M    */
+#define CFG_FLASH_BASE		0xff000000	/* start of FLASH 16M	 */
 #define CFG_BR0_PRELIM		0xff001801	/* port size 32bit	*/
 #endif
 
-#define	CFG_OR0_PRELIM		0xff006ff7	/* 16MB Flash		*/
+#define CFG_OR0_PRELIM		0xff006ff7	/* 16MB Flash		*/
 #define CFG_MAX_FLASH_BANKS	1		/* number of banks	*/
-#define CFG_MAX_FLASH_SECT	64		/* sectors per device   */
+#define CFG_MAX_FLASH_SECT	64		/* sectors per device	*/
 #undef	CFG_FLASH_CHECKSUM
 #define CFG_FLASH_ERASE_TOUT	60000	/* Timeout for Flash Erase (in ms)*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)*/
 
-#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 #define CFG_RAMBOOT
 #else
-#undef  CFG_RAMBOOT
+#undef	CFG_RAMBOOT
 #endif
 
 #define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
 
 #if defined(CONFIG_DDR_SETTING)
-#define CFG_DDR_CS0_BNDS        0x00000007      /* 0-128MB              */
-#define CFG_DDR_CS0_CONFIG      0x80000002
-#define CFG_DDR_TIMING_1        0x37344321
-#define CFG_DDR_TIMING_2        0x00000800      /* P9-45,may need tuning*/
-#define CFG_DDR_CONTROL         0xc2000000      /* unbuffered,no DYN_PWR*/
-#define CFG_DDR_MODE            0x00000062      /* DLL,normal,seq,4/2.5 */
-#define CFG_DDR_INTERVAL        0x05200100      /* autocharge,no open page*/
+#define CFG_DDR_CS0_BNDS	0x00000007	/* 0-128MB		*/
+#define CFG_DDR_CS0_CONFIG	0x80000002
+#define CFG_DDR_TIMING_1	0x37344321
+#define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning*/
+#define CFG_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR*/
+#define CFG_DDR_MODE		0x00000062	/* DLL,normal,seq,4/2.5 */
+#define CFG_DDR_INTERVAL	0x05200100	/* autocharge,no open page*/
 #endif
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
 /* local bus definitions */
-#define CFG_BR2_PRELIM		0xf8001861	/* 64MB localbus SDRAM  */
+#define CFG_BR2_PRELIM		0xf8001861	/* 64MB localbus SDRAM	*/
 #define CFG_OR2_PRELIM		0xfc006901
 #define CFG_LBC_LCRR		0x00030004	/* local bus freq divider*/
 #define CFG_LBC_LBCR		0x00000000
@@ -148,52 +148,52 @@
 #define CFG_LBC_LSDMR_5		0x4061b723
 
 #if defined(CONFIG_RAM_AS_FLASH)
-#define CFG_BR4_PRELIM          0xf8000801      /* 32KB, 8-bit wide for ADS config reg */
+#define CFG_BR4_PRELIM		0xf8000801	/* 32KB, 8-bit wide for ADS config reg */
 #else
-#define CFG_BR4_PRELIM          0xfc000801      /* 32KB, 8-bit wide for ADS config reg */
+#define CFG_BR4_PRELIM		0xfc000801	/* 32KB, 8-bit wide for ADS config reg */
 #endif
-#define CFG_OR4_PRELIM          0xffffe1f1
-#define CFG_BCSR                (CFG_BR4_PRELIM & 0xffff8000)
+#define CFG_OR4_PRELIM		0xffffe1f1
+#define CFG_BCSR		(CFG_BR4_PRELIM & 0xffff8000)
 
 #define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 	1
-#define CFG_INIT_RAM_ADDR   	0x40000000 	/* Initial RAM address	*/
-#define CFG_INIT_RAM_END    	0x4000	    	/* End of used area in RAM */
+#define CFG_INIT_RAM_LOCK	1
+#define CFG_INIT_RAM_ADDR	0x40000000	/* Initial RAM address	*/
+#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */
 
-#define CFG_GBL_DATA_SIZE  	128		/* num bytes initial data */
+#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN	    	(256 * 1024)    /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN	    	(128 * 1024)    /* Reserved for malloc */
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX     1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
 #define CFG_NS16550
 #define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE    1
+#define CFG_NS16550_REG_SIZE	1
 #define CFG_NS16550_CLK		get_bus_freq(0)
-#define CONFIG_BAUDRATE	 	115200
+#define CONFIG_BAUDRATE		115200
 
 #define CFG_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
-#define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
+#define CFG_NS16550_COM1	(CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2	(CFG_CCSRBAR+0x4600)
 
 /* Use the HUSH parser */
 #define CFG_HUSH_PARSER
-#ifdef  CFG_HUSH_PARSER
+#ifdef	CFG_HUSH_PARSER
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
 /* I2C */
-#define  CONFIG_HARD_I2C		/* I2C with hardware support*/
+#define	 CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
 #define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
 
 /* General PCI */
 #define CFG_PCI_MEM_BASE	0xe0000000
@@ -203,22 +203,22 @@
 #define CONFIG_NET_MULTI
 #undef CONFIG_EEPRO100
 #define CONFIG_TULIP
-#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
   #if !defined(CONFIG_PCI_PNP)
-  #define PCI_ENET0_IOADDR      0xe0000000
-  #define PCI_ENET0_MEMADDR     0xe0000000
-  #define PCI_IDSEL_NUMBER      0x0c 	/*slot0->3(IDSEL)=12->15*/
+  #define PCI_ENET0_IOADDR	0xe0000000
+  #define PCI_ENET0_MEMADDR	0xe0000000
+  #define PCI_IDSEL_NUMBER	0x0c	/*slot0->3(IDSEL)=12->15*/
   #endif
-#define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
-#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup	*/
+#define CFG_PCI_SUBSYS_VENDORID 0x1057	/* Motorola */
 #if defined(CONFIG_MPC85xx_REV1)	/* Errata PCI 8 */
   #define CFG_PCI_SUBSYS_DEVICEID 0x0003
 #else
   #define CFG_PCI_SUBSYS_DEVICEID 0x0008
 #endif
 #elif defined(CONFIG_TSEC_ENET)
-#define CONFIG_NET_MULTI 	1
-#define CONFIG_PHY_M88E1011      1       /* GigaBit Ether PHY    */
+#define CONFIG_NET_MULTI	1
+#define CONFIG_PHY_M88E1011	 1	 /* GigaBit Ether PHY	 */
 #define CONFIG_MII		1	/* MII PHY management	*/
 #define CONFIG_PHY_ADDR		8	/* PHY address	*/
 #endif
@@ -232,7 +232,7 @@
   #else
   #define CFG_ENV_IS_IN_FLASH	1
   #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
-  #define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+  #define CFG_ENV_SECT_SIZE	0x40000 /* 256K(one sector) for env */
   #endif
   #define CFG_ENV_SIZE		0x2000
 #else
@@ -242,10 +242,10 @@
 #define CFG_ENV_SIZE		0x2000
 #endif
 
-#define CONFIG_BOOTARGS	"root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8540ads-003:eth0:off console=ttyS0,115200"
+#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8540ads-003:eth0:off console=ttyS0,115200"
 /*#define CONFIG_BOOTARGS	"root=/dev/ram rw console=ttyS0,115200"*/
 #define CONFIG_BOOTCOMMAND	"bootm 0xff300000 0xff700000"
-#define CONFIG_BOOTDELAY	3 	/* -1 disable autoboot */
+#define CONFIG_BOOTDELAY	3	/* -1 disable autoboot */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
@@ -274,7 +274,7 @@
  * Miscellaneous configurable options
  */
 #define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"MPC8540ADS=> "	/* Monitor Command Prompt	*/
+#define CFG_PROMPT	"MPC8540ADS=> " /* Monitor Command Prompt	*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -291,10 +291,10 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20) 	/* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux */
 
 /* Cache Configuration */
-#define CFG_DCACHE_SIZE	32768
+#define CFG_DCACHE_SIZE 32768
 #define CFG_CACHELINE_SIZE	32
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
@@ -315,17 +315,17 @@
 
 /* NOTE: change below for your network setting!!! */
 #if defined(CONFIG_TSEC_ENET)
-#define CONFIG_ETHADDR  00:01:af:07:9b:8a
-#define CONFIG_ETH1ADDR  00:01:af:07:9b:8b
-#define CONFIG_ETH2ADDR  00:01:af:07:9b:8c
+#define CONFIG_ETHADDR	00:01:af:07:9b:8a
+#define CONFIG_ETH1ADDR	 00:01:af:07:9b:8b
+#define CONFIG_ETH2ADDR	 00:01:af:07:9b:8c
 #endif
 
-#define CONFIG_SERVERIP         163.12.64.52
-#define CONFIG_IPADDR           10.82.0.105
-#define CONFIG_GATEWAYIP        10.82.1.254
-#define CONFIG_NETMASK          255.255.254.0
-#define CONFIG_HOSTNAME         MPC8560ADS_PILOT_003
-#define CONFIG_ROOTPATH         /home/r6aads/mpclinux/eldk-2.0.2/ppc_82xx
-#define CONFIG_BOOTFILE         pImage
+#define CONFIG_SERVERIP		163.12.64.52
+#define CONFIG_IPADDR		10.82.0.105
+#define CONFIG_GATEWAYIP	10.82.1.254
+#define CONFIG_NETMASK		255.255.254.0
+#define CONFIG_HOSTNAME		MPC8560ADS_PILOT_003
+#define CONFIG_ROOTPATH		/home/r6aads/mpclinux/eldk-2.0.2/ppc_82xx
+#define CONFIG_BOOTFILE		pImage
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 0d844d1c0b..44b128fd6b 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -31,22 +31,22 @@
 #define __CONFIG_H
 
 /* High Level Configuration Options */
-#define CONFIG_BOOKE		1	/* BOOKE		*/
-#define CONFIG_E500		1	/* BOOKE e500 family	*/
-#define CONFIG_MPC85xx		1	/* MPC8540/MPC8560	*/
-#define CONFIG_MPC85xx_REV1	1	/* MPC85xx Rev 1.0 chip */
-#define CONFIG_MPC8560		1	/* MPC8560 specific	*/
-#define CONFIG_MPC8560ADS	1	/* MPC8560ADS board specific*/
-
-#undef  CONFIG_PCI	         	/* pci ethernet support	*/
-#define CONFIG_TSEC_ENET 		/* tsec ethernet support*/
-#undef  CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
+#define CONFIG_BOOKE		1	/* BOOKE			*/
+#define CONFIG_E500		1	/* BOOKE e500 family		*/
+#define CONFIG_MPC85xx		1	/* MPC8540/MPC8560		*/
+#define CONFIG_MPC85xx_REV1	1	/* MPC85xx Rev 1.0 chip		*/
+#define CONFIG_MPC8560		1	/* MPC8560 specific		*/
+#define CONFIG_MPC8560ADS	1	/* MPC8560ADS board specific	*/
+
+#undef	CONFIG_PCI			/* pci ethernet support		*/
+#define CONFIG_TSEC_ENET		/* tsec ethernet support	*/
+#undef	CONFIG_ETHER_ON_FCC		/* cpm FCC ethernet support	*/
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
-#undef  CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#undef	CONFIG_DDR_ECC			/* only for ECC DDR module	*/
 
 #if defined(CONFIG_MPC85xx_REV1)
-#define CONFIG_DDR_DLL                  /* possible DLL fix needed */
+#define CONFIG_DDR_DLL			/* possible DLL fix needed	*/
 #endif
 
 /* Using Localbus SDRAM to emulate flash before we can program the flash,
@@ -54,10 +54,10 @@
  */
 #undef CONFIG_RAM_AS_FLASH
 
-#if !defined(CONFIG_PCI)		/* some PCI card is 33Mhz only */
-#define CONFIG_SYS_CLK_FREQ	66000000/* sysclk for MPC85xx */
+#if !defined(CONFIG_PCI)		/* some PCI card is 33Mhz only	*/
+#define CONFIG_SYS_CLK_FREQ	66000000/* sysclk for MPC85xx		*/
 #else
-#define CONFIG_SYS_CLK_FREQ     33000000/* most pci cards are 33Mhz */
+#define CONFIG_SYS_CLK_FREQ	33000000/* most pci cards are 33Mhz	*/
 #endif
 
 #if !defined(CONFIG_SPD_EEPROM)		/* manually set up DDR parameters */
@@ -65,15 +65,15 @@
 #endif
 
 /* below can be toggled for performance analysis. otherwise use default */
-#define CONFIG_L2_CACHE                     /* toggle L2 cache         */
-#undef  CONFIG_BTB                          /* toggle branch predition */
-#undef  CONFIG_ADDR_STREAMING               /* toggle addr streaming   */
+#define CONFIG_L2_CACHE			    /* toggle L2 cache		*/
+#undef	CONFIG_BTB			    /* toggle branch predition	*/
+#undef	CONFIG_ADDR_STREAMING		    /* toggle addr streaming	*/
 
-#define CONFIG_BOARD_PRE_INIT   1           /* Call board_pre_init      */
+#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
 
-#undef  CFG_DRAM_TEST                       /* memory test, takes time  */
-#define CFG_MEMTEST_START       0x00200000  /* memtest region */
-#define CFG_MEMTEST_END         0x00400000
+#undef	CFG_DRAM_TEST			    /* memory test, takes time	*/
+#define CFG_MEMTEST_START	0x00200000  /* memtest region */
+#define CFG_MEMTEST_END		0x00400000
 
 #if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
      defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
@@ -85,48 +85,48 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default	*/
-#define CFG_CCSRBAR             0xfdf00000      /* relocated CCSRBAR    */
+#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default	*/
+#define CFG_CCSRBAR		0xfdf00000	/* relocated CCSRBAR	*/
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory  */
+#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory	 */
 #define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
-#define CFG_SDRAM_SIZE		128		/* DDR is 128MB	*/
+#define CFG_SDRAM_SIZE		128		/* DDR is 128MB */
 
 #if defined(CONFIG_RAM_AS_FLASH)
-#define CFG_LBC_SDRAM_BASE      0xfc000000      /* Localbus SDRAM */
+#define CFG_LBC_SDRAM_BASE	0xfc000000	/* Localbus SDRAM */
 #else
-#define CFG_LBC_SDRAM_BASE      0xf8000000      /* Localbus SDRAM */
+#define CFG_LBC_SDRAM_BASE	0xf8000000	/* Localbus SDRAM */
 #endif
 #define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB	*/
 
 #if defined(CONFIG_RAM_AS_FLASH)
-#define CFG_FLASH_BASE        0xf8000000      /* start of FLASH  16M  */
-#define CFG_BR0_PRELIM        0xf8001801      /* port size 32bit */
+#define CFG_FLASH_BASE	      0xf8000000      /* start of FLASH	 16M  */
+#define CFG_BR0_PRELIM	      0xf8001801      /* port size 32bit */
 #else /* Boot from real Flash */
-#define CFG_FLASH_BASE        0xff000000      /* start of FLASH 16M    */
-#define CFG_BR0_PRELIM        0xff001801      /* port size 32bit      */
+#define CFG_FLASH_BASE	      0xff000000      /* start of FLASH 16M    */
+#define CFG_BR0_PRELIM	      0xff001801      /* port size 32bit      */
 #endif
 
-#define CFG_OR0_PRELIM          0xff006ff7      /* 16MB Flash           */
+#define CFG_OR0_PRELIM		0xff006ff7	/* 16MB Flash		*/
 #define CFG_MAX_FLASH_BANKS	1		/* number of banks	*/
-#define CFG_MAX_FLASH_SECT	64		/* sectors per device   */
+#define CFG_MAX_FLASH_SECT	64		/* sectors per device	*/
 #undef	CFG_FLASH_CHECKSUM
 #define CFG_FLASH_ERASE_TOUT	60000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor	*/
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor	*/
 
 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 #define CFG_RAMBOOT
 #else
-#undef  CFG_RAMBOOT
+#undef	CFG_RAMBOOT
 #endif
 
-#define SPD_EEPROM_ADDRESS 	0x51     	/*  DDR DIMM */
+#define SPD_EEPROM_ADDRESS	0x51		/*  DDR DIMM */
 
 #if defined(CONFIG_DDR_SETTING)
-#define	CFG_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
+#define CFG_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
 #define CFG_DDR_CS0_CONFIG	0x80000002
 #define CFG_DDR_TIMING_1	0x37344321
 #define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning*/
@@ -138,9 +138,9 @@
 #undef CONFIG_CLOCKS_IN_MHZ
 
 /* local bus definitions */
-#define CFG_BR2_PRELIM		0xf8001861	/* 64MB localbus SDRAM  */
+#define CFG_BR2_PRELIM		0xf8001861	/* 64MB localbus SDRAM	*/
 #define CFG_OR2_PRELIM		0xfc006901
-#define CFG_LBC_LCRR		0x00030004	/* local bus freq 	*/
+#define CFG_LBC_LCRR		0x00030004	/* local bus freq	*/
 #define CFG_LBC_LBCR		0x00000000
 #define CFG_LBC_LSRT		0x20000000
 #define CFG_LBC_MRTPR		0x20000000
@@ -151,78 +151,78 @@
 #define CFG_LBC_LSDMR_5		0x4061b723
 
 #if defined(CONFIG_RAM_AS_FLASH)
-#define CFG_BR4_PRELIM          0xf8000801      /* 32KB, 8-bit wide for ADS config reg */
+#define CFG_BR4_PRELIM		0xf8000801	/* 32KB, 8-bit wide for ADS config reg */
 #else
-#define CFG_BR4_PRELIM          0xfc000801      /* 32KB, 8-bit wide for ADS config reg */
+#define CFG_BR4_PRELIM		0xfc000801	/* 32KB, 8-bit wide for ADS config reg */
 #endif
 #define CFG_OR4_PRELIM		0xffffe1f1
 #define CFG_BCSR		(CFG_BR4_PRELIM & 0xffff8000)
 
 #define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 	1
-#define CFG_INIT_RAM_ADDR       0x40000000      /* Initial RAM address  */
-#define CFG_INIT_RAM_END    	0x4000	    	/* End of used area in RAM */
+#define CFG_INIT_RAM_LOCK	1
+#define CFG_INIT_RAM_ADDR	0x40000000	/* Initial RAM address	*/
+#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */
 
-#define CFG_GBL_DATA_SIZE  	128		/* num bytes initial data */
+#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN	    	(256 * 1024)    /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN	    	(128 * 1024)    /* Reserved for malloc */
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
 
 /* Serial Port */
-#define CONFIG_CONS_ON_SCC              	/* define if console on SCC */
-#undef  CONFIG_CONS_NONE                	/* define if console on something else */
-#define CONFIG_CONS_INDEX       1       	/* which serial channel for console */
+#define CONFIG_CONS_ON_SCC			/* define if console on SCC */
+#undef	CONFIG_CONS_NONE			/* define if console on something else */
+#define CONFIG_CONS_INDEX	1		/* which serial channel for console */
 
-#define CONFIG_BAUDRATE	 	115200
+#define CONFIG_BAUDRATE		115200
 
 #define CFG_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
 /* Use the HUSH parser */
 #define CFG_HUSH_PARSER
-#ifdef  CFG_HUSH_PARSER
+#ifdef	CFG_HUSH_PARSER
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
 /* I2C */
-#define  CONFIG_HARD_I2C    		/* I2C with hardware support*/
+#define	 CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
 #define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES        {0x69}  /* Don't probe these addrs */
+#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
 
 #define CFG_PCI_MEM_BASE	0xe0000000
 #define CFG_PCI_MEM_PHYS	0xe0000000
 #define CFG_PCI_MEM_SIZE	0x10000000
 
-#if defined(CONFIG_PCI) 		/* PCI Ethernet card */
+#if defined(CONFIG_PCI)			/* PCI Ethernet card */
 #define CONFIG_NET_MULTI
 #define CONFIG_EEPRO100
 #undef CONFIG_TULIP
-#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
   #if !defined(CONFIG_PCI_PNP)
-  #define PCI_ENET0_IOADDR    	0xe0000000
-  #define PCI_ENET0_MEMADDR     0xe0000000
-  #define PCI_IDSEL_NUMBER      0x0c 	/* slot0->3(IDSEL)=12->15 */
+  #define PCI_ENET0_IOADDR	0xe0000000
+  #define PCI_ENET0_MEMADDR	0xe0000000
+  #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
   #endif
-#define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
-#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
-#if defined(CONFIG_MPC85xx_REV1) 	/* Errata PCI 7 */
+#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup	*/
+#define CFG_PCI_SUBSYS_VENDORID 0x1057	/* Motorola */
+#if defined(CONFIG_MPC85xx_REV1)	/* Errata PCI 7 */
   #define CFG_PCI_SUBSYS_DEVICEID 0x0003
 #else
   #define CFG_PCI_SUBSYS_DEVICEID 0x0009
 #endif
-#elif defined(CONFIG_TSEC_ENET) 	/* TSEC Ethernet port */
-#define CONFIG_NET_MULTI 	1
-#define CONFIG_PHY_M88E1011      1       /* GigaBit Ether PHY        */
+#elif defined(CONFIG_TSEC_ENET)		/* TSEC Ethernet port */
+#define CONFIG_NET_MULTI	1
+#define CONFIG_PHY_M88E1011	 1	 /* GigaBit Ether PHY	     */
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		8	/* PHY address			*/
 #elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */
-#define CONFIG_ETHER_ON_FCC             /* define if ether on FCC   */
-#undef  CONFIG_ETHER_NONE               /* define if ether on something else */
-#define CONFIG_ETHER_INDEX      2       /* which channel for ether  */
+#define CONFIG_ETHER_ON_FCC		/* define if ether on FCC   */
+#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
+#define CONFIG_ETHER_INDEX	2	/* which channel for ether  */
   #if (CONFIG_ETHER_INDEX == 2)
   /*
    * - Rx-CLK is CLK13
@@ -230,15 +230,15 @@
    * - Select bus for bd/buffers
    * - Full duplex
    */
-  #define CFG_CMXFCR_MASK       (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-  #define CFG_CMXFCR_VALUE      (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
-  #define CFG_CPMFCR_RAMTYPE    0
-  #define CFG_FCC_PSMR          (FCC_PSMR_FDE)
+  #define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+  #define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+  #define CFG_CPMFCR_RAMTYPE	0
+  #define CFG_FCC_PSMR		(FCC_PSMR_FDE)
   #define FETH2_RST		0x01
   #elif (CONFIG_ETHER_INDEX == 3)
   /* need more definitions here for FE3 */
   #define FETH3_RST		0x80
-  #endif  				/* CONFIG_ETHER_INDEX */
+  #endif				/* CONFIG_ETHER_INDEX */
 #define CONFIG_MII			/* MII PHY management */
 #define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
 /*
@@ -267,7 +267,7 @@
   #else
   #define CFG_ENV_IS_IN_FLASH	1
   #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
-  #define CFG_ENV_SECT_SIZE	0x40000	/* 128K(one sector) for env */
+  #define CFG_ENV_SECT_SIZE	0x40000 /* 128K(one sector) for env */
   #endif
   #define CFG_ENV_SIZE		0x2000
 #else
@@ -320,7 +320,7 @@
  * Miscellaneous configurable options
  */
 #define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"MPC8560ADS=> "	/* Monitor Command Prompt	*/
+#define CFG_PROMPT	"MPC8560ADS=> " /* Monitor Command Prompt	*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -361,17 +361,17 @@
 
 /*Note: change below for your network setting!!! */
 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
-#define CONFIG_ETHADDR  00:01:af:07:9b:8a
-#define CONFIG_ETH1ADDR  00:01:af:07:9b:8b
-#define CONFIG_ETH2ADDR  00:01:af:07:9b:8c
+#define CONFIG_ETHADDR	00:01:af:07:9b:8a
+#define CONFIG_ETH1ADDR	 00:01:af:07:9b:8b
+#define CONFIG_ETH2ADDR	 00:01:af:07:9b:8c
 #endif
 
-#define CONFIG_SERVERIP 	163.12.64.52
-#define CONFIG_IPADDR  		10.82.0.105
+#define CONFIG_SERVERIP		163.12.64.52
+#define CONFIG_IPADDR		10.82.0.105
 #define CONFIG_GATEWAYIP	10.82.1.254
 #define CONFIG_NETMASK		255.255.254.0
-#define CONFIG_HOSTNAME 	MPC8560ADS_PILOT_003
-#define CONFIG_ROOTPATH 	/home/r6aads/mpclinux/eldk-2.0.2/ppc_82xx
-#define CONFIG_BOOTFILE 	pImage
+#define CONFIG_HOSTNAME		MPC8560ADS_PILOT_003
+#define CONFIG_ROOTPATH		/home/r6aads/mpclinux/eldk-2.0.2/ppc_82xx
+#define CONFIG_BOOTFILE		pImage
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h
index 8221a198e8..46505b6fd3 100644
--- a/include/configs/NETVIA.h
+++ b/include/configs/NETVIA.h
@@ -105,7 +105,7 @@
 #define CONFIG_COMMANDS		CONFIG_COMMANDS_BASE
 #endif
 
-#define CONFIG_BOARD_PRE_INIT
+#define CONFIG_BOARD_EARLY_INIT_F 1
 #define CONFIG_MISC_INIT_R
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h
index 698b89c008..c88d882e0b 100644
--- a/include/configs/OCRTC.h
+++ b/include/configs/OCRTC.h
@@ -34,12 +34,12 @@
  */
 
 #define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
-#define CONFIG_OCRTC   		1	/* ...on a OCRTC board	        */
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_OCRTC		1	/* ...on a OCRTC board		*/
 
-#define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
 
-#define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
+#define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll	*/
 
 #define CONFIG_BAUDRATE		9600
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
@@ -51,7 +51,7 @@
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_MII		1	/* MII PHY management		*/
-#define	CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
 
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_PCI	| \
@@ -59,7 +59,7 @@
 				CFG_CMD_ASKENV	| \
 				CFG_CMD_ELF	| \
 				CFG_CMD_BSP	| \
-				CFG_CMD_EEPROM  )
+				CFG_CMD_EEPROM	)
 
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
@@ -67,9 +67,9 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
-#undef  CONFIG_WATCHDOG			/* watchdog disabled		*/
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
-#define	CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 
 /*
  * Miscellaneous configurable options
@@ -77,32 +77,32 @@
 #define CFG_LONGHELP			/* undef to save memory		*/
 #define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 #define CFG_MAXARGS	16		/* max number of command args	*/
 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
 #define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
-#define CFG_BASE_BAUD       691200
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD	    691200
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE      \
+#define CFG_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
 #define CFG_LOAD_ADDR	0x100000	/* default load address */
 #define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
@@ -110,28 +110,28 @@
  * PCI stuff
  *-----------------------------------------------------------------------
  */
-#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
 
-#define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
-#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-					/* resource configuration       */
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_AUTO	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
 
-#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
 
-#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
+#define CONFIG_PCI_BOOTDELAY	0	/* enable pci bootdelay variable*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0410  /* PCI Device ID: OCRTC         */
-#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0410	/* PCI Device ID: OCRTC		*/
+#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
@@ -159,18 +159,18 @@
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
-#define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
-#define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
-#define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
-#define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #if 0 /* Use NVRAM for environment variables */
 /*-----------------------------------------------------------------------
@@ -186,9 +186,9 @@
 
 #else /* Use EEPROM for environment variables */
 
-#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE            0x300   /* 768 bytes may be used for env vars */
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x300	/* 768 bytes may be used for env vars */
 				   /* total size of a CAT24WC08 is 1024 bytes */
 #endif
 
@@ -200,12 +200,12 @@
 #define CFG_I2C_SLAVE		0x7F
 
 #define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
 #define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
 #define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
-					/* last	4 bits of the address	*/
+					/* last 4 bits of the address	*/
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 
@@ -231,53 +231,53 @@
  * External Bus Controller (EBC) Setup
  */
 
-/* Memory Bank 0 (Flash Bank 0) initialization                                  */
-#define CFG_EBC_PB0AP           0x92015480
-#define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CFG_EBC_PB0AP		0x92015480
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
-/* Memory Bank 1 (Flash Bank 1) initialization                                  */
-#define CFG_EBC_PB1AP           0x92015480
-#define CFG_EBC_PB1CR           0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+/* Memory Bank 1 (Flash Bank 1) initialization					*/
+#define CFG_EBC_PB1AP		0x92015480
+#define CFG_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
 
-/* Memory Bank 2 (PLD - FPGA-boot) initialization                               */
-#define CFG_EBC_PB2AP           0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+/* Memory Bank 2 (PLD - FPGA-boot) initialization				*/
+#define CFG_EBC_PB2AP		0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
 					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CFG_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 3 (PLD - OSL) initialization                                     */
-#define CFG_EBC_PB3AP           0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+/* Memory Bank 3 (PLD - OSL) initialization					*/
+#define CFG_EBC_PB3AP		0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
 					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CFG_EBC_PB3CR           0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit  */
+#define CFG_EBC_PB3CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 4 (Spartan2 1) initialization                                    */
-#define CFG_EBC_PB4AP           0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+/* Memory Bank 4 (Spartan2 1) initialization					*/
+#define CFG_EBC_PB4AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
 					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CFG_EBC_PB4CR           0xF209C000  /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/
+#define CFG_EBC_PB4CR		0xF209C000  /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/
 
-/* Memory Bank 5 (Spartan2 2) initialization                                    */
-#define CFG_EBC_PB5AP           0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+/* Memory Bank 5 (Spartan2 2) initialization					*/
+#define CFG_EBC_PB5AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
 					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CFG_EBC_PB5CR           0xF309C000  /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/
+#define CFG_EBC_PB5CR		0xF309C000  /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/
 
-/* Memory Bank 6 (Virtex 1) initialization                                      */
-#define CFG_EBC_PB6AP           0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+/* Memory Bank 6 (Virtex 1) initialization					*/
+#define CFG_EBC_PB6AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
 					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CFG_EBC_PB6CR           0xF409A000  /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/
+#define CFG_EBC_PB6CR		0xF409A000  /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/
 
-/* Memory Bank 7 (Virtex 2) initialization                                      */
-#define CFG_EBC_PB7AP           0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+/* Memory Bank 7 (Virtex 2) initialization					*/
+#define CFG_EBC_PB7AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
 					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CFG_EBC_PB7CR           0xF509A000  /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/
+#define CFG_EBC_PB7CR		0xF509A000  /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/
 
 
-#define CFG_ETHERNET_MAC_ADDR   0x00000000      /* Pass Ethernet MAC to VxWorks */
+#define CFG_ETHERNET_MAC_ADDR	0x00000000	/* Pass Ethernet MAC to VxWorks */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM        1
+#define CFG_TEMP_STACK_OCM	  1
 
 /* On Chip Memory location */
 #define CFG_OCM_DATA_ADDR	0xF8000000
@@ -287,7 +287,7 @@
 #define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
 
 /*
diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h
index cb4c5eee95..3dcb514fa9 100644
--- a/include/configs/ORSG.h
+++ b/include/configs/ORSG.h
@@ -34,12 +34,12 @@
  */
 
 #define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
-#define CONFIG_ORSG   		1	/* ...on a ORSG board	        */
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_ORSG		1	/* ...on a ORSG board		*/
 
-#define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
 
-#define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
+#define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll	*/
 
 #define CONFIG_BAUDRATE		9600
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
@@ -51,7 +51,7 @@
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_MII		1	/* MII PHY management		*/
-#define	CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
 
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_PCI	| \
@@ -59,7 +59,7 @@
 				CFG_CMD_ASKENV	| \
 				CFG_CMD_ELF	| \
 				CFG_CMD_BSP	| \
-				CFG_CMD_EEPROM  )
+				CFG_CMD_EEPROM	)
 
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
@@ -67,9 +67,9 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
-#undef  CONFIG_WATCHDOG			/* watchdog disabled		*/
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
-#define	CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 
 /*
  * Miscellaneous configurable options
@@ -77,32 +77,32 @@
 #define CFG_LONGHELP			/* undef to save memory		*/
 #define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 #define CFG_MAXARGS	16		/* max number of command args	*/
 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
 #define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
-#define CFG_BASE_BAUD       691200
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD	    691200
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE      \
+#define CFG_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
 #define CFG_LOAD_ADDR	0x100000	/* default load address */
 #define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
@@ -110,26 +110,26 @@
  * PCI stuff
  *-----------------------------------------------------------------------
  */
-#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
-
-#define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_HOST	PCI_HOST_ADAPTER /* select pci adapter          */
-#undef  CONFIG_PCI_PNP			/* no pci plug-and-play         */
-					/* resource configuration       */
-
-#undef  CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0411  /* PCI Device ID: ORSG          */
-#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci adapter		*/
+#undef	CONFIG_PCI_PNP			/* no pci plug-and-play		*/
+					/* resource configuration	*/
+
+#undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0411	/* PCI Device ID: ORSG		*/
+#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
@@ -157,18 +157,18 @@
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
-#define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
-#define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
-#define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
-#define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #if 0 /* Use NVRAM for environment variables */
 /*-----------------------------------------------------------------------
@@ -184,9 +184,9 @@
 
 #else /* Use EEPROM for environment variables */
 
-#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE            0x300   /* 768 bytes may be used for env vars */
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x300	/* 768 bytes may be used for env vars */
 				   /* total size of a CAT24WC08 is 1024 bytes */
 #endif
 
@@ -198,12 +198,12 @@
 #define CFG_I2C_SLAVE		0x7F
 
 #define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
 #define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
 #define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
-					/* last	4 bits of the address	*/
+					/* last 4 bits of the address	*/
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 
@@ -229,53 +229,53 @@
  * External Bus Controller (EBC) Setup
  */
 
-/* Memory Bank 0 (Flash Bank 0) initialization                                  */
-#define CFG_EBC_PB0AP           0x92015480
-#define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CFG_EBC_PB0AP		0x92015480
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
-/* Memory Bank 1 (Flash Bank 1) initialization                                  */
-#define CFG_EBC_PB1AP           0x92015480
-#define CFG_EBC_PB1CR           0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+/* Memory Bank 1 (Flash Bank 1) initialization					*/
+#define CFG_EBC_PB1AP		0x92015480
+#define CFG_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
 
-/* Memory Bank 2 (PLD - FPGA-boot) initialization                               */
-#define CFG_EBC_PB2AP           0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+/* Memory Bank 2 (PLD - FPGA-boot) initialization				*/
+#define CFG_EBC_PB2AP		0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
 					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CFG_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 3 (PLD - OSL) initialization                                     */
-#define CFG_EBC_PB3AP           0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+/* Memory Bank 3 (PLD - OSL) initialization					*/
+#define CFG_EBC_PB3AP		0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
 					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CFG_EBC_PB3CR           0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit  */
+#define CFG_EBC_PB3CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 4 (Spartan2 1) initialization                                    */
-#define CFG_EBC_PB4AP           0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+/* Memory Bank 4 (Spartan2 1) initialization					*/
+#define CFG_EBC_PB4AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
 					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CFG_EBC_PB4CR           0xF209C000  /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/
+#define CFG_EBC_PB4CR		0xF209C000  /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/
 
-/* Memory Bank 5 (Spartan2 2) initialization                                    */
-#define CFG_EBC_PB5AP           0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+/* Memory Bank 5 (Spartan2 2) initialization					*/
+#define CFG_EBC_PB5AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
 					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CFG_EBC_PB5CR           0xF309C000  /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/
+#define CFG_EBC_PB5CR		0xF309C000  /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/
 
-/* Memory Bank 6 (Virtex 1) initialization                                      */
-#define CFG_EBC_PB6AP           0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+/* Memory Bank 6 (Virtex 1) initialization					*/
+#define CFG_EBC_PB6AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
 					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CFG_EBC_PB6CR           0xF409A000  /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/
+#define CFG_EBC_PB6CR		0xF409A000  /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/
 
-/* Memory Bank 7 (Virtex 2) initialization                                      */
-#define CFG_EBC_PB7AP           0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+/* Memory Bank 7 (Virtex 2) initialization					*/
+#define CFG_EBC_PB7AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
 					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CFG_EBC_PB7CR           0xF509A000  /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/
+#define CFG_EBC_PB7CR		0xF509A000  /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/
 
 
-#define CFG_ETHERNET_MAC_ADDR   0x00000000      /* Pass Ethernet MAC to VxWorks */
+#define CFG_ETHERNET_MAC_ADDR	0x00000000	/* Pass Ethernet MAC to VxWorks */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM        1
+#define CFG_TEMP_STACK_OCM	  1
 
 /* On Chip Memory location */
 #define CFG_OCM_DATA_ADDR	0xF8000000
@@ -285,7 +285,7 @@
 #define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
 
 /*
diff --git a/include/configs/OXC.h b/include/configs/OXC.h
index 57f577d2bb..586b19f82c 100644
--- a/include/configs/OXC.h
+++ b/include/configs/OXC.h
@@ -39,7 +39,7 @@
 #define CONFIG_MPC8240		1
 #define CONFIG_OXC		1
 
-#define CONFIG_BOARD_PRE_INIT	1	/* Call board_pre_init	*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
 
 #define CONFIG_IDENT_STRING     " [oxc] "
 
diff --git a/include/configs/P3G4.h b/include/configs/P3G4.h
index b6ebc5fde9..c56ad11b9f 100644
--- a/include/configs/P3G4.h
+++ b/include/configs/P3G4.h
@@ -51,7 +51,7 @@
 
 /* which initialization functions to call for this board */
 #define CONFIG_MISC_INIT_R	1
-#define CONFIG_BOARD_PRE_INIT	1
+#define CONFIG_BOARD_EARLY_INIT_F 1
 
 #define CFG_BOARD_NAME		"P3G4"
 
diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h
index 9cd8f5a32d..49fdfdddae 100644
--- a/include/configs/PCI405.h
+++ b/include/configs/PCI405.h
@@ -34,22 +34,22 @@
  */
 
 #define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
-#define CONFIG_PCI405		1	/* ...on a PCI405 board	        */
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_PCI405		1	/* ...on a PCI405 board		*/
 
-#define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
 #define CONFIG_MISC_INIT_R	1	/* call misc_init_r() on init	*/
 
-#define CONFIG_SYS_CLK_FREQ     25000000 /* external frequency to pll   */
+#define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll	*/
 
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
 
 #if 0
-#define CONFIG_PREBOOT                                                          \
-	"crc32 f0207004 ffc 0;"                                                 \
-	"if cmp 0 f0207000 1;"                                                  \
-	"then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;"             \
+#define CONFIG_PREBOOT								\
+	"crc32 f0207004 ffc 0;"							\
+	"if cmp 0 f0207000 1;"							\
+	"then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;"		\
 	"else;echo Old CRC is bad;fi"
 #endif
 
@@ -59,8 +59,8 @@
 	"bootm fffc0000"
 #else
 #define CONFIG_BOOTCOMMAND							\
-	"mw.l 0 ffffffff; mw.l 4 ffffffff;"                                     \
-	"while cmp 0 4 1; do echo Waiting for Host...;done;"                    \
+	"mw.l 0 ffffffff; mw.l 4 ffffffff;"					\
+	"while cmp 0 4 1; do echo Waiting for Host...;done;"			\
 	"bootm 400000"
 #endif
 
@@ -68,7 +68,7 @@
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_MII		1	/* MII PHY management		*/
-#define	CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
 
 #define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
 
@@ -79,16 +79,16 @@
 				CFG_CMD_DATE	| \
 				CFG_CMD_I2C	| \
 				CFG_CMD_BSP	| \
-				CFG_CMD_EEPROM  )
+				CFG_CMD_EEPROM	)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
-#undef  CONFIG_WATCHDOG			/* watchdog disabled		*/
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
-#define	CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 
-#define	CONFIG_PRAM		2048	/* reserve 2 MB "protected RAM"	*/
+#define CONFIG_PRAM		2048	/* reserve 2 MB "protected RAM" */
 
 /*
  * Miscellaneous configurable options
@@ -96,75 +96,75 @@
 #define CFG_LONGHELP			/* undef to save memory		*/
 #define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
-#define	CFG_HUSH_PARSER			/* use "hush" command parser	*/
+#define CFG_HUSH_PARSER			/* use "hush" command parser	*/
 #ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CFG_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 #define CFG_MAXARGS	16		/* max number of command args	*/
 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
 
-#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
 #define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
-#define CFG_BASE_BAUD       691200
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD	    691200
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE      \
+#define CFG_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
 #define CFG_LOAD_ADDR	0x100000	/* default load address */
 #define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #undef CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
-#define CONFIG_VERSION_VARIABLE	1       /* include version env variable */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
  */
-#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
 
-#define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_HOST	PCI_HOST_ADAPTER /* select pci host function    */
-#undef  CONFIG_PCI_PNP			/* no pci plug-and-play         */
-					/* resource configuration       */
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci host function	*/
+#undef	CONFIG_PCI_PNP			/* no pci plug-and-play		*/
+					/* resource configuration	*/
 
-#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0407  /* PCI Device ID: PCI-405       */
-#define CFG_PCI_CLASSCODE       0x0280  /* PCI Class Code: Network/Other*/
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xff000001      /* 16MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0407	/* PCI Device ID: PCI-405	*/
+#define CFG_PCI_CLASSCODE	0x0280	/* PCI Class Code: Network/Other*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0xff000001	/* 16MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
 
 #if 0 /* test-only */
-#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 #else
-#define CFG_PCI_PTM2LA  0xef600000      /* point to internal regs       */
-#define CFG_PCI_PTM2MS  0xffe00001      /* 2MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA	0xef600000	/* point to internal regs	*/
+#define CFG_PCI_PTM2MS	0xffe00001	/* 2MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x00000000	/* Host: use this pci address	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -193,18 +193,18 @@
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
-#define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
-#define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
-#define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
-#define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #if 0 /* Use NVRAM for environment variables */
 /*-----------------------------------------------------------------------
@@ -217,9 +217,9 @@
 
 #else /* Use EEPROM for environment variables */
 
-#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE            0x400   /* 1024 bytes may be used for env vars*/
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x400	/* 1024 bytes may be used for env vars*/
 				   /* total size of a CAT24WC08 is 1024 bytes */
 #endif
 
@@ -234,12 +234,12 @@
 #define CFG_I2C_SLAVE		0x7F
 
 #define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
 #define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
 #define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
-					/* last	4 bits of the address	*/
+					/* last 4 bits of the address	*/
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 
@@ -264,73 +264,73 @@
  * External Bus Controller (EBC) Setup
  */
 
-/* Memory Bank 0 (Flash Bank 0) initialization                                  */
-#define CFG_EBC_PB0AP           0x92015480
-#define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CFG_EBC_PB0AP		0x92015480
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
-/* Memory Bank 1 (NVRAM/RTC) initialization                                     */
-#define CFG_EBC_PB1AP           0x01005280  /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1     */
-#define CFG_EBC_PB1CR           0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit  */
+/* Memory Bank 1 (NVRAM/RTC) initialization					*/
+#define CFG_EBC_PB1AP		0x01005280  /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1	*/
+#define CFG_EBC_PB1CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 2 (CAN0, 1) initialization                                       */
-#define CFG_EBC_PB2AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-/*#define CFG_EBC_PB2AP           0x038056C0  / * BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+/* Memory Bank 2 (CAN0, 1) initialization					*/
+#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+/*#define CFG_EBC_PB2AP		  0x038056C0  / * BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 3 (FPGA internal) initialization                                 */
-#define CFG_EBC_PB3AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR           0xF041C000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
-#define CFG_FPGA_BASE_ADDR      0xF0400000
+/* Memory Bank 3 (FPGA internal) initialization					*/
+#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR		0xF041C000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
+#define CFG_FPGA_BASE_ADDR	0xF0400000
 
 /*-----------------------------------------------------------------------
  * FPGA stuff
  */
 /* FPGA internal regs */
-#define CFG_FPGA_MODE           0x00
-#define CFG_FPGA_STATUS         0x02
-#define CFG_FPGA_TS             0x04
-#define CFG_FPGA_TS_LOW         0x06
-#define CFG_FPGA_TS_CAP0        0x10
-#define CFG_FPGA_TS_CAP0_LOW    0x12
-#define CFG_FPGA_TS_CAP1        0x14
-#define CFG_FPGA_TS_CAP1_LOW    0x16
-#define CFG_FPGA_TS_CAP2        0x18
-#define CFG_FPGA_TS_CAP2_LOW    0x1a
-#define CFG_FPGA_TS_CAP3        0x1c
-#define CFG_FPGA_TS_CAP3_LOW    0x1e
+#define CFG_FPGA_MODE		0x00
+#define CFG_FPGA_STATUS		0x02
+#define CFG_FPGA_TS		0x04
+#define CFG_FPGA_TS_LOW		0x06
+#define CFG_FPGA_TS_CAP0	0x10
+#define CFG_FPGA_TS_CAP0_LOW	0x12
+#define CFG_FPGA_TS_CAP1	0x14
+#define CFG_FPGA_TS_CAP1_LOW	0x16
+#define CFG_FPGA_TS_CAP2	0x18
+#define CFG_FPGA_TS_CAP2_LOW	0x1a
+#define CFG_FPGA_TS_CAP3	0x1c
+#define CFG_FPGA_TS_CAP3_LOW	0x1e
 
 /* FPGA Mode Reg */
-#define CFG_FPGA_MODE_CF_RESET  0x0001
+#define CFG_FPGA_MODE_CF_RESET	0x0001
 #define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
 #define CFG_FPGA_MODE_TS_IRQ_CLEAR  0x1000
-#define CFG_FPGA_MODE_TS_CLEAR  0x2000
+#define CFG_FPGA_MODE_TS_CLEAR	0x2000
 
 /* FPGA Status Reg */
-#define CFG_FPGA_STATUS_DIP0    0x0001
-#define CFG_FPGA_STATUS_DIP1    0x0002
-#define CFG_FPGA_STATUS_DIP2    0x0004
-#define CFG_FPGA_STATUS_FLASH   0x0008
-#define CFG_FPGA_STATUS_TS_IRQ  0x1000
+#define CFG_FPGA_STATUS_DIP0	0x0001
+#define CFG_FPGA_STATUS_DIP1	0x0002
+#define CFG_FPGA_STATUS_DIP2	0x0004
+#define CFG_FPGA_STATUS_FLASH	0x0008
+#define CFG_FPGA_STATUS_TS_IRQ	0x1000
 
-#define CFG_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
-#define CFG_FPGA_MAX_SIZE       32*1024     /* 32kByte is enough for XC2S15  */
+#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CFG_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for XC2S15  */
 
 /* FPGA program pin configuration */
-#define CFG_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT           0x00400000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE           0x00800000  /* FPGA done pin (ppc input)     */
+#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CFG_FPGA_INIT		0x00400000  /* FPGA init pin (ppc input)     */
+#define CFG_FPGA_DONE		0x00800000  /* FPGA done pin (ppc input)     */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
-#define CFG_INIT_DCACHE_CS      7       /* use cs # 7 for data cache memory    */
-#define CFG_INIT_RAM_ADDR       0x40000000  /* use data cache                  */
-#define CFG_INIT_RAM_END        0x2000  /* End of used area in RAM             */
+#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
+#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
+#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
 /*
  * Internal Definitions
diff --git a/include/configs/PCIPPC2.h b/include/configs/PCIPPC2.h
index 645cdc59d2..f90c52e269 100644
--- a/include/configs/PCIPPC2.h
+++ b/include/configs/PCIPPC2.h
@@ -43,7 +43,7 @@
 
 #define CONFIG_PCIPPC2		1	/* this is a PCIPPC2 board	*/
 
-#define CONFIG_BOARD_PRE_INIT	1
+#define CONFIG_BOARD_EARLY_INIT_F 1
 #define CONFIG_MISC_INIT_R	1
 
 #define CONFIG_CONS_INDEX	1
diff --git a/include/configs/PCIPPC6.h b/include/configs/PCIPPC6.h
index 4953458d40..f4a5dd875e 100644
--- a/include/configs/PCIPPC6.h
+++ b/include/configs/PCIPPC6.h
@@ -43,7 +43,7 @@
 
 #define CONFIG_PCIPPC2		1	/* this is a PCIPPC2 board	*/
 
-#define CONFIG_BOARD_PRE_INIT	1
+#define CONFIG_BOARD_EARLY_INIT_F 1
 #define CONFIG_MISC_INIT_R	1
 
 #define CONFIG_CONS_INDEX	1
diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h
index 2cd5726b95..dbec242d6c 100644
--- a/include/configs/PIP405.h
+++ b/include/configs/PIP405.h
@@ -103,7 +103,7 @@
  ***************************************************************/
 #define SPD_EEPROM_ADDRESS      0x50
 
-#define CONFIG_BOARD_PRE_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
 /**************************************************************
  * Environment definitions
  **************************************************************/
@@ -238,7 +238,7 @@
 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
 #define FLASH_SIZE_PRELIM	 3  /* maximal flash FLASH size bank #0	*/
 
-#define CONFIG_BOARD_PRE_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
 
 /* Configuration Port location */
 #define CONFIG_PORT_ADDR	0xF4000000
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index d93deff7ed..0798af4d04 100644
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -34,13 +34,13 @@
  */
 
 #define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
-#define CONFIG_PLU405		1	/* ...on a PLU405 board 	*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_PLU405		1	/* ...on a PLU405 board		*/
 
-#define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */
-#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
 
-#define CONFIG_SYS_CLK_FREQ     33333334 /* external frequency to pll   */
+#define CONFIG_SYS_CLK_FREQ	33333334 /* external frequency to pll	*/
 
 #define CONFIG_BAUDRATE		9600
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
@@ -60,7 +60,7 @@
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_MII		1	/* MII PHY management		*/
-#define	CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
 
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_DHCP	| \
@@ -73,7 +73,7 @@
 				CFG_CMD_I2C	| \
 				CFG_CMD_MII	| \
 				CFG_CMD_PING	| \
-				CFG_CMD_EEPROM  )
+				CFG_CMD_EEPROM	)
 
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
@@ -81,12 +81,12 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
-#undef  CONFIG_WATCHDOG			/* watchdog disabled		*/
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
-#define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible*/
-#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address         */
+#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
+#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
 
-#define	CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 
 /*
  * Miscellaneous configurable options
@@ -96,45 +96,45 @@
 
 #undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
 #ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CFG_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 #define CFG_MAXARGS	16		/* max number of command args	*/
 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
 
-#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
 #define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
-#define CFG_BASE_BAUD       691200
-#undef  CONFIG_UART1_CONSOLE            /* define for uart1 as console  */
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD	    691200
+#undef	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE      \
+#define CFG_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
 #define CFG_LOAD_ADDR	0x100000	/* default load address */
 #define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
-#define CONFIG_VERSION_VARIABLE	1       /* include version env variable */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
-#define CFG_RX_ETH_BUFFER	16      /* use 16 rx buffer on 405 emac */
+#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
 
 /*-----------------------------------------------------------------------
  * NAND-FLASH stuff
@@ -147,14 +147,14 @@
 #define ADDR_PAGE 2
 #define ADDR_COLUMN_PAGE 3
 
-#define NAND_ChipID_UNKNOWN 	0x00
+#define NAND_ChipID_UNKNOWN	0x00
 #define NAND_MAX_FLOORS 1
 #define NAND_MAX_CHIPS 1
 
-#define CFG_NAND_CE  (0x80000000 >> 1)  /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2)  /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3)  /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4)  /* our RDY is GPIO4 */
+#define CFG_NAND_CE  (0x80000000 >> 1)	/* our CE is GPIO1 */
+#define CFG_NAND_CLE (0x80000000 >> 2)	/* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3)	/* our ALE is GPIO3 */
+#define CFG_NAND_RDY (0x80000000 >> 4)	/* our RDY is GPIO4 */
 
 #define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
 #define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
@@ -173,43 +173,43 @@
  * PCI stuff
  *-----------------------------------------------------------------------
  */
-#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
-
-#define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_HOST	PCI_HOST_HOST   /* select pci host function     */
-#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-					/* resource configuration       */
-
-#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
-#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_HOST	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
+#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff
  *-----------------------------------------------------------------------
  */
-#undef  CONFIG_IDE_8xx_DIRECT               /* no pcmcia interface required */
-#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
+#undef	CONFIG_IDE_8xx_DIRECT		    /* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
 #define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
 
-#define	CFG_IDE_MAXBUS	        1		/* max. 1 IDE busses	*/
-#define	CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+#define CFG_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
+#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
 
-#define	CFG_ATA_BASE_ADDR	0xF0100000
-#define	CFG_ATA_IDE0_OFFSET	0x0000
+#define CFG_ATA_BASE_ADDR	0xF0100000
+#define CFG_ATA_IDE0_OFFSET	0x0000
 
 #define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
-#define	CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
 #define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
 
 /*
@@ -229,22 +229,22 @@
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
-#define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
-#define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
-#define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
-#define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS     1           /* ! second bank contains U-Boot */
+#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -267,13 +267,13 @@
 /*-----------------------------------------------------------------------
  * Environment Variable setup
  */
-#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET          0x100   /* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE            0x700   /* 2048 bytes may be used for env vars*/
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
 				   /* total size of a CAT24WC16 is 2048 bytes */
 
 #define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		242		        /* NVRAM size		*/
+#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
 
 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC16) for environment
@@ -285,20 +285,20 @@
 #define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT24WC08		*/
 #if 1 /* test-only */
 /* CAT24WC08/16... */
-#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
 #define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
 #define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
-					/* last	4 bits of the address	*/
+					/* last 4 bits of the address	*/
 #else
 /* CAT24WC32/64... */
-#define CFG_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CFG_I2C_EEPROM_ADDR_LEN 2	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
 #define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x01
 #define CFG_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
 					/* 32 byte page write mode using*/
-					/* last	5 bits of the address	*/
+					/* last 5 bits of the address	*/
 #endif
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 #define CFG_EEPROM_PAGE_WRITE_ENABLE
@@ -306,8 +306,8 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's    */
-					/* have only 8kB, 16kB is save here     */
+#define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's	*/
+					/* have only 8kB, 16kB is save here	*/
 #define CFG_CACHELINE_SIZE	32	/* ...			*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
@@ -317,59 +317,59 @@
  * External Bus Controller (EBC) Setup
  */
 
-#define CAN_BA          0xF0000000          /* CAN Base Address                 */
-#define DUART0_BA       0xF0000400          /* DUART Base Address               */
-#define DUART1_BA       0xF0000408          /* DUART Base Address               */
-#define RTC_BA          0xF0000500          /* RTC Base Address                 */
-#define VGA_BA          0xF1000000          /* Epson VGA Base Address           */
-#define CFG_NAND_BASE   0xF4000000          /* NAND FLASH Base Address          */
+#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
+#define DUART0_BA	0xF0000400	    /* DUART Base Address		*/
+#define DUART1_BA	0xF0000408	    /* DUART Base Address		*/
+#define RTC_BA		0xF0000500	    /* RTC Base Address			*/
+#define VGA_BA		0xF1000000	    /* Epson VGA Base Address		*/
+#define CFG_NAND_BASE	0xF4000000	    /* NAND FLASH Base Address		*/
 
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
-#define CFG_EBC_PB0AP           0x92015480
-/*#define CFG_EBC_PB0AP           0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
-#define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CFG_EBC_PB0AP		0x92015480
+/*#define CFG_EBC_PB0AP		  0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
-/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization                      */
-#define CFG_EBC_PB1AP           0x92015480
-#define CFG_EBC_PB1CR           0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit  */
+/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
+#define CFG_EBC_PB1AP		0x92015480
+#define CFG_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization              */
-#define CFG_EBC_PB2AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
+#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization     */
-#define CFG_EBC_PB3AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR           0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization	*/
+#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 
 /*-----------------------------------------------------------------------
  * FPGA stuff
  */
 
-#define CFG_FPGA_BASE_ADDR 0xF0100100       /* FPGA internal Base Address       */
+#define CFG_FPGA_BASE_ADDR 0xF0100100	    /* FPGA internal Base Address	*/
 
 /* FPGA internal regs */
-#define CFG_FPGA_CTRL           0x000
+#define CFG_FPGA_CTRL		0x000
 
 /* FPGA Control Reg */
-#define CFG_FPGA_CTRL_CF_RESET  0x0001
-#define CFG_FPGA_CTRL_WDI       0x0002
+#define CFG_FPGA_CTRL_CF_RESET	0x0001
+#define CFG_FPGA_CTRL_WDI	0x0002
 #define CFG_FPGA_CTRL_PS2_RESET 0x0020
 
-#define CFG_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
-#define CFG_FPGA_MAX_SIZE       128*1024    /* 128kByte is enough for XC2S50E*/
+#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CFG_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/
 
 /* FPGA program pin configuration */
-#define CFG_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */
+#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
+#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM        1
+#define CFG_TEMP_STACK_OCM	  1
 
 /* On Chip Memory location */
 #define CFG_OCM_DATA_ADDR	0xF8000000
@@ -379,13 +379,13 @@
 
 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Definitions for GPIO setup (PPC405EP specific)
  *
- * GPIO0[0]     - External Bus Controller BLAST output
- * GPIO0[1-9]   - Instruction trace outputs -> GPIO
+ * GPIO0[0]	- External Bus Controller BLAST output
+ * GPIO0[1-9]	- Instruction trace outputs -> GPIO
  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
@@ -393,15 +393,15 @@
  * GPIO0[28-29] - UART1 data signal input/output
  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
  */
-#define CFG_GPIO0_OSRH          0x40000550
-#define CFG_GPIO0_OSRL          0x00000110
-#define CFG_GPIO0_ISR1H         0x00000000
-#define CFG_GPIO0_ISR1L         0x15555445
-#define CFG_GPIO0_TSRH          0x00000000
-#define CFG_GPIO0_TSRL          0x00000000
-#define CFG_GPIO0_TCR           0xF7FE0014
+#define CFG_GPIO0_OSRH		0x40000550
+#define CFG_GPIO0_OSRL		0x00000110
+#define CFG_GPIO0_ISR1H		0x00000000
+#define CFG_GPIO0_ISR1L		0x15555445
+#define CFG_GPIO0_TSRH		0x00000000
+#define CFG_GPIO0_TSRL		0x00000000
+#define CFG_GPIO0_TCR		0xF7FE0014
 
-#define CFG_DUART_RST           (0x80000000 >> 14)
+#define CFG_DUART_RST		(0x80000000 >> 14)
 
 /*
  * Internal Definitions
@@ -416,16 +416,16 @@
  * This value will be set if iic boot eprom is disabled.
  */
 #if 0
-#define PLLMR0_DEFAULT   PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT   PLLMR1_266_133_66_33
+#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
 #endif
 #if 0
-#define PLLMR0_DEFAULT   PLLMR0_200_100_50_33
-#define PLLMR1_DEFAULT   PLLMR1_200_100_50_33
+#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
+#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
 #endif
 #if 1
-#define PLLMR0_DEFAULT   PLLMR0_133_66_66_33
-#define PLLMR1_DEFAULT   PLLMR1_133_66_66_33
+#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
 #endif
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h
index 35d49fcec8..49414bb29d 100644
--- a/include/configs/PMC405.h
+++ b/include/configs/PMC405.h
@@ -34,13 +34,13 @@
  */
 
 #define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
-#define CONFIG_PMC405		1	/* ...on a PMC405 board 	*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_PMC405		1	/* ...on a PMC405 board		*/
 
-#define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */
-#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
 
-#define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
+#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll	*/
 
 #define CONFIG_BAUDRATE		9600
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
@@ -60,7 +60,7 @@
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_MII		1	/* MII PHY management		*/
-#define	CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
 
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_BSP	| \
@@ -72,7 +72,7 @@
 				CFG_CMD_MII	| \
 				CFG_CMD_I2C	| \
 				CFG_CMD_PING	| \
-				CFG_CMD_EEPROM  )
+				CFG_CMD_EEPROM	)
 
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
@@ -80,12 +80,12 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
-#undef  CONFIG_WATCHDOG			/* watchdog disabled		*/
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
-#define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible*/
-#define CFG_RTC_REG_BASE_ADDR	 0xF0000300 /* RTC Base Address         */
+#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
+#define CFG_RTC_REG_BASE_ADDR	 0xF0000300 /* RTC Base Address		*/
 
-#define	CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 
 /*
  * Miscellaneous configurable options
@@ -95,69 +95,69 @@
 
 #undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
 #ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CFG_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 #define CFG_MAXARGS	16		/* max number of command args	*/
 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
 
-#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
 #define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
-#define CFG_BASE_BAUD       691200
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD	    691200
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE      \
+#define CFG_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
 #define CFG_LOAD_ADDR	0x100000	/* default load address */
 #define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
-#define CONFIG_VERSION_VARIABLE	1       /* include version env variable */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
-#define CFG_RX_ETH_BUFFER	16      /* use 16 rx buffer on 405 emac */
+#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
  */
-#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
-
-#define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function     */
-#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-					/* resource configuration       */
-
-#undef CONFIG_PCI_SCAN_SHOW             /* print pci devices @ startup  */
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0408  /* PCI Device ID: PMC-405       */
-#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#undef CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0408	/* PCI Device ID: PMC-405	*/
+#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
@@ -187,21 +187,21 @@
 #define CFG_FLASH_BASE		0xFE000000
 #define CFG_FLASH_INCREMENT	0x01000000
 
-#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
-#define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS     1           /* ! second bank contains u-boot    */
+#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains u-boot	*/
 
 /*-----------------------------------------------------------------------
  * Environment Variable setup
  */
-#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE            0x800   /* 2048 bytes may be used for env vars*/
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x800	/* 2048 bytes may be used for env vars*/
 				   /* total size of a CAT24WC16 is 2048 bytes */
 
 #define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		242		        /* NVRAM size		*/
+#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
 
 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC16) for environment
@@ -211,20 +211,20 @@
 #define CFG_I2C_SLAVE		0x7F
 
 #define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
 #define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
 #define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
-					/* last	4 bits of the address	*/
+					/* last 4 bits of the address	*/
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's    */
-					/* have only 8kB, 16kB is save here     */
+#define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's	*/
+					/* have only 8kB, 16kB is save here	*/
 #define CFG_CACHELINE_SIZE	32	/* ...			*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
@@ -233,47 +233,47 @@
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  */
-#define FLASH0_BA       0xFF000000          /* FLASH 0 Base Address             */
-#define FLASH1_BA       0xFE000000          /* FLASH 1 Base Address             */
-#define CAN_BA          0xF0000000          /* CAN Base Address                 */
-#define RTC_BA          0xF0000500          /* RTC Base Address                 */
-#define CF_BA           0xF0100000          /* CompactFlash Base Address        */
+#define FLASH0_BA	0xFF000000	    /* FLASH 0 Base Address		*/
+#define FLASH1_BA	0xFE000000	    /* FLASH 1 Base Address		*/
+#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
+#define RTC_BA		0xF0000500	    /* RTC Base Address			*/
+#define CF_BA		0xF0100000	    /* CompactFlash Base Address	*/
 
-/* Memory Bank 0 (Flash Bank 0) initialization                                  */
-#define CFG_EBC_PB0AP   0x92015480
-#define CFG_EBC_PB0CR   FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CFG_EBC_PB0AP	0x92015480
+#define CFG_EBC_PB0CR	FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/
 
-/* Memory Bank 1 (Flash Bank 1) initialization                                  */
-#define CFG_EBC_PB1AP   0x92015480
-#define CFG_EBC_PB1CR   FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
+/* Memory Bank 1 (Flash Bank 1) initialization					*/
+#define CFG_EBC_PB1AP	0x92015480
+#define CFG_EBC_PB1CR	FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
 
-/* Memory Bank 2 (CAN0, 1, RTC) initialization                                  */
-#define CFG_EBC_PB2AP   0x03000040   /* TWT=6,TH=0,CSN=0,OEN=0,WBN=0,WBF=0      */
-#define CFG_EBC_PB2CR   CAN_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+/* Memory Bank 2 (CAN0, 1, RTC) initialization					*/
+#define CFG_EBC_PB2AP	0x03000040   /* TWT=6,TH=0,CSN=0,OEN=0,WBN=0,WBF=0	*/
+#define CFG_EBC_PB2CR	CAN_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization               */
-#define CFG_EBC_PB3AP   0x010059C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR   CF_BA | 0x1A000     /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+/* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization		*/
+#define CFG_EBC_PB3AP	0x010059C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR	CF_BA | 0x1A000	    /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 
 /*-----------------------------------------------------------------------
  * FPGA stuff
  */
-#define CFG_FPGA_XC95XL         1           /* using Xilinx XC95XL CPLD      */
-#define CFG_FPGA_MAX_SIZE       32*1024     /* 32kByte is enough for CPLD    */
+#define CFG_FPGA_XC95XL		1	    /* using Xilinx XC95XL CPLD	     */
+#define CFG_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for CPLD    */
 
 /* FPGA program pin configuration */
-#define CFG_FPGA_PRG            0x04000000  /* JTAG TMS pin (ppc output)     */
-#define CFG_FPGA_CLK            0x02000000  /* JTAG TCK pin (ppc output)     */
-#define CFG_FPGA_DATA           0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
-#define CFG_FPGA_INIT           0x00010000  /* unused (ppc input)            */
-#define CFG_FPGA_DONE           0x00008000  /* JTAG TDI->TDO pin (ppc input) */
+#define CFG_FPGA_PRG		0x04000000  /* JTAG TMS pin (ppc output)     */
+#define CFG_FPGA_CLK		0x02000000  /* JTAG TCK pin (ppc output)     */
+#define CFG_FPGA_DATA		0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
+#define CFG_FPGA_INIT		0x00010000  /* unused (ppc input)	     */
+#define CFG_FPGA_DONE		0x00008000  /* JTAG TDI->TDO pin (ppc input) */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
 
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM      1
+#define CFG_TEMP_STACK_OCM	1
 
 /* On Chip Memory location */
 #define CFG_OCM_DATA_ADDR	0xF8000000
@@ -283,7 +283,7 @@
 #define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
 /*
  * Internal Definitions
diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h
index 50e8a15b8d..cb76e3cf3b 100644
--- a/include/configs/PPChameleonEVB.h
+++ b/include/configs/PPChameleonEVB.h
@@ -34,14 +34,14 @@
 #define CONFIG_PPCHAMELEON_MODULE_BA	0	/* Basic    Model */
 #define CONFIG_PPCHAMELEON_MODULE_ME	1	/* Medium   Model */
 #define CONFIG_PPCHAMELEON_MODULE_HI	2	/* High-End Model */
-#ifndef	CONFIG_PPCHAMELEON_MODULE_MODEL
-#define	CONFIG_PPCHAMELEON_MODULE_MODEL	CONFIG_PPCHAMELEON_MODULE_BA
+#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
+#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
 #endif
 
 /*
  * Debug stuff
  */
-#undef  __DEBUG_START_FROM_SRAM__
+#undef	__DEBUG_START_FROM_SRAM__
 #define __DISABLE_MACHINE_EXCEPTION__
 
 #ifdef __DEBUG_START_FROM_SRAM__
@@ -54,13 +54,13 @@
  */
 
 #define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
-#define CONFIG_PPCHAMELEONEVB	1	/* ...on a PPChameleonEVB board 	*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_PPCHAMELEONEVB	1	/* ...on a PPChameleonEVB board */
 
-#define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */
-#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
 
-#define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
+#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll	*/
 
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
@@ -70,7 +70,7 @@
 /* Ethernet stuff */
 #define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
 #define CONFIG_ETHADDR	00:50:c2:1e:af:fe
-#define CONFIG_ETH1ADDR	00:50:c2:1e:af:fd
+#define CONFIG_ETH1ADDR 00:50:c2:1e:af:fd
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
@@ -79,12 +79,12 @@
 #undef CONFIG_EXT_PHY
 
 #define CONFIG_MII		1	/* MII PHY management		*/
-#ifndef  CONFIG_EXT_PHY
-#define	CONFIG_PHY_ADDR		1	/* PHY address			*/
+#ifndef	 CONFIG_EXT_PHY
+#define CONFIG_PHY_ADDR		1	/* PHY address			*/
 #else
-#define	CONFIG_PHY_ADDR		2	/* PHY address			*/
+#define CONFIG_PHY_ADDR		2	/* PHY address			*/
 #endif
-#define	CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ
+#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ
 
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_DATE	| \
@@ -101,12 +101,12 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
-#undef  CONFIG_WATCHDOG			/* watchdog disabled		*/
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
-#define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible*/
-#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address         */
+#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
+#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
 
-#define	CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 
 /*
  * Miscellaneous configurable options
@@ -116,38 +116,38 @@
 
 #undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
 #ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CFG_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 #define CFG_MAXARGS	16		/* max number of command args	*/
 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
 
-#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
 #define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
-#define CFG_BASE_BAUD       691200
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD	    691200
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE      \
+#define CFG_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
 #define CFG_LOAD_ADDR	0x100000	/* default load address */
 #define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
@@ -166,14 +166,14 @@
 #define ADDR_PAGE 2
 #define ADDR_COLUMN_PAGE 3
 
-#define NAND_ChipID_UNKNOWN 	0x00
+#define NAND_ChipID_UNKNOWN	0x00
 #define NAND_MAX_FLOORS 1
 #define NAND_MAX_CHIPS 1
 
-#define CFG_NAND0_CE  (0x80000000 >> 1)  /* our CE is GPIO1 */
-#define CFG_NAND0_CLE (0x80000000 >> 2)  /* our CLE is GPIO2 */
-#define CFG_NAND0_ALE (0x80000000 >> 3)  /* our ALE is GPIO3 */
-#define CFG_NAND0_RDY (0x80000000 >> 4)  /* our RDY is GPIO4 */
+#define CFG_NAND0_CE  (0x80000000 >> 1)	 /* our CE is GPIO1 */
+#define CFG_NAND0_CLE (0x80000000 >> 2)	 /* our CLE is GPIO2 */
+#define CFG_NAND0_ALE (0x80000000 >> 3)	 /* our ALE is GPIO3 */
+#define CFG_NAND0_RDY (0x80000000 >> 4)	 /* our RDY is GPIO4 */
 
 #define CFG_NAND1_CE  (0x80000000 >> 14)  /* our CE is GPIO14 */
 #define CFG_NAND1_CLE (0x80000000 >> 15)  /* our CLE is GPIO15 */
@@ -277,26 +277,26 @@
  * PCI stuff
  *-----------------------------------------------------------------------
  */
-#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
-
-#define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_HOST	PCI_HOST_FORCE   /* select pci host function     */
-#undef  CONFIG_PCI_PNP			/* do pci plug-and-play         */
-					/* resource configuration       */
-
-#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
-#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_FORCE	 /* select pci host function	 */
+#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
+#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
@@ -324,34 +324,34 @@
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
-#define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
-#define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
-#define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
-#define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS     1           /* ! second bank contains U-Boot */
+#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
 #endif
 
 /*-----------------------------------------------------------------------
  * Environment Variable setup
  */
-#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET          0x100   /* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE            0x700   /* 2048 bytes may be used for env vars*/
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
 				   /* total size of a CAT24WC16 is 2048 bytes */
 
 #define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		242		        /* NVRAM size		*/
+#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
 
 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC16) for environment
@@ -361,20 +361,20 @@
 #define CFG_I2C_SLAVE		0x7F
 
 #define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
 /*#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07*/
 #define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
-					/* last	4 bits of the address	*/
+					/* last 4 bits of the address	*/
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's    */
-					/* have only 8kB, 16kB is save here     */
+#define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's	*/
+					/* have only 8kB, 16kB is save here	*/
 #define CFG_CACHELINE_SIZE	32	/* ...			*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
@@ -392,93 +392,93 @@
  * External Bus Controller (EBC) Setup
  */
 
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
-#define CFG_EBC_PB0AP           0x92015480
-#define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CFG_EBC_PB0AP		0x92015480
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
-/* Memory Bank 1 (External SRAM) initialization                      		*/
+/* Memory Bank 1 (External SRAM) initialization					*/
 /* Since this must replace NOR Flash, we use the same settings for CS0		*/
-#define CFG_EBC_PB1AP           0x92015480
-#define CFG_EBC_PB1CR           0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit  */
+#define CFG_EBC_PB1AP		0x92015480
+#define CFG_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization                      */
-#define CFG_EBC_PB2AP           0x92015480
-#define CFG_EBC_PB2CR           0xFF458000  /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit  */
+/* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization			*/
+#define CFG_EBC_PB2AP		0x92015480
+#define CFG_EBC_PB2CR		0xFF458000  /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization                      */
-#define CFG_EBC_PB3AP           0x92015480
-#define CFG_EBC_PB3CR           0xFF058000  /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit  */
+/* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization			*/
+#define CFG_EBC_PB3AP		0x92015480
+#define CFG_EBC_PB3CR		0xFF058000  /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit	*/
 
 
 #if 0 /* Roese */
-/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization                      */
-#define CFG_EBC_PB1AP           0x92015480
-#define CFG_EBC_PB1CR           0xFF858000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit  */
+/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
+#define CFG_EBC_PB1AP		0x92015480
+#define CFG_EBC_PB1CR		0xFF858000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 2 (CAN0, 1) initialization                                       */
-#define CFG_EBC_PB2AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+/* Memory Bank 2 (CAN0, 1) initialization					*/
+#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 3 (CompactFlash IDE) initialization                              */
-#define CFG_EBC_PB3AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR           0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+/* Memory Bank 3 (CompactFlash IDE) initialization				*/
+#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 
-/* Memory Bank 4 (NVRAM/RTC) initialization                                     */
-#define CFG_EBC_PB4AP           0x01005280  /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1     */
-#define CFG_EBC_PB4CR           0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit  */
+/* Memory Bank 4 (NVRAM/RTC) initialization					*/
+#define CFG_EBC_PB4AP		0x01005280  /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1	*/
+#define CFG_EBC_PB4CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
 #endif
 
 /*-----------------------------------------------------------------------
  * FPGA stuff
  */
 /* FPGA internal regs */
-#define CFG_FPGA_MODE           0x00
-#define CFG_FPGA_STATUS         0x02
-#define CFG_FPGA_TS             0x04
-#define CFG_FPGA_TS_LOW         0x06
-#define CFG_FPGA_TS_CAP0        0x10
-#define CFG_FPGA_TS_CAP0_LOW    0x12
-#define CFG_FPGA_TS_CAP1        0x14
-#define CFG_FPGA_TS_CAP1_LOW    0x16
-#define CFG_FPGA_TS_CAP2        0x18
-#define CFG_FPGA_TS_CAP2_LOW    0x1a
-#define CFG_FPGA_TS_CAP3        0x1c
-#define CFG_FPGA_TS_CAP3_LOW    0x1e
+#define CFG_FPGA_MODE		0x00
+#define CFG_FPGA_STATUS		0x02
+#define CFG_FPGA_TS		0x04
+#define CFG_FPGA_TS_LOW		0x06
+#define CFG_FPGA_TS_CAP0	0x10
+#define CFG_FPGA_TS_CAP0_LOW	0x12
+#define CFG_FPGA_TS_CAP1	0x14
+#define CFG_FPGA_TS_CAP1_LOW	0x16
+#define CFG_FPGA_TS_CAP2	0x18
+#define CFG_FPGA_TS_CAP2_LOW	0x1a
+#define CFG_FPGA_TS_CAP3	0x1c
+#define CFG_FPGA_TS_CAP3_LOW	0x1e
 
 /* FPGA Mode Reg */
-#define CFG_FPGA_MODE_CF_RESET  0x0001
+#define CFG_FPGA_MODE_CF_RESET	0x0001
 #define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
 #define CFG_FPGA_MODE_TS_IRQ_CLEAR  0x1000
-#define CFG_FPGA_MODE_TS_CLEAR  0x2000
+#define CFG_FPGA_MODE_TS_CLEAR	0x2000
 
 /* FPGA Status Reg */
-#define CFG_FPGA_STATUS_DIP0    0x0001
-#define CFG_FPGA_STATUS_DIP1    0x0002
-#define CFG_FPGA_STATUS_DIP2    0x0004
-#define CFG_FPGA_STATUS_FLASH   0x0008
-#define CFG_FPGA_STATUS_TS_IRQ  0x1000
+#define CFG_FPGA_STATUS_DIP0	0x0001
+#define CFG_FPGA_STATUS_DIP1	0x0002
+#define CFG_FPGA_STATUS_DIP2	0x0004
+#define CFG_FPGA_STATUS_FLASH	0x0008
+#define CFG_FPGA_STATUS_TS_IRQ	0x1000
 
-#define CFG_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
-#define CFG_FPGA_MAX_SIZE       128*1024    /* 128kByte is enough for XC2S50E*/
+#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CFG_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/
 
 /* FPGA program pin configuration */
-#define CFG_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */
+#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
+#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
 #if 0 /* test-only */
-#define CFG_INIT_DCACHE_CS      4       /* use cs # 4 for data cache memory    */
+#define CFG_INIT_DCACHE_CS	4	/* use cs # 4 for data cache memory    */
 
-#define CFG_INIT_RAM_ADDR       0x40000000  /* use data cache                  */
-#define CFG_INIT_RAM_END        0x2000  /* End of used area in RAM             */
+#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
+#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
 #else
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM        1
+#define CFG_TEMP_STACK_OCM	  1
 
 /* On Chip Memory location */
 #define CFG_OCM_DATA_ADDR	0xF8000000
@@ -489,29 +489,29 @@
 
 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Definitions for GPIO setup (PPC405EP specific)
  *
- * GPIO0[0]     - External Bus Controller BLAST output
- * GPIO0[1-9]   - Instruction trace outputs -> GPIO
+ * GPIO0[0]	- External Bus Controller BLAST output
+ * GPIO0[1-9]	- Instruction trace outputs -> GPIO
  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
  * GPIO0[24-27] - UART0 control signal inputs/outputs
  * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30]    - EMAC0 input
- * GPIO0[31]    - EMAC1 reject packet as output
+ * GPIO0[30]	- EMAC0 input
+ * GPIO0[31]	- EMAC1 reject packet as output
  */
-#define CFG_GPIO0_OSRH          0x40000550
-#define CFG_GPIO0_OSRL          0x00000110
-#define CFG_GPIO0_ISR1H         0x00000000
-/*#define CFG_GPIO0_ISR1L         0x15555445*/
-#define CFG_GPIO0_ISR1L         0x15555444
-#define CFG_GPIO0_TSRH          0x00000000
-#define CFG_GPIO0_TSRL          0x00000000
-#define CFG_GPIO0_TCR           0xF7FF8014
+#define CFG_GPIO0_OSRH		0x40000550
+#define CFG_GPIO0_OSRL		0x00000110
+#define CFG_GPIO0_ISR1H		0x00000000
+/*#define CFG_GPIO0_ISR1L	  0x15555445*/
+#define CFG_GPIO0_ISR1L		0x15555444
+#define CFG_GPIO0_TSRH		0x00000000
+#define CFG_GPIO0_TSRL		0x00000000
+#define CFG_GPIO0_TCR		0xF7FF8014
 
 /*
  * Internal Definitions
@@ -532,163 +532,163 @@
 !-----------------------------------------------------------------------
 ! Defines for entry options.
 ! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
-!       are plugged in the board will be utilized as non-ECC DIMMs.
+!	are plugged in the board will be utilized as non-ECC DIMMs.
 !-----------------------------------------------------------------------
 */
-#undef        AUTO_MEMORY_CONFIG
-#define        DIMM_READ_ADDR 0xAB
-#define        DIMM_WRITE_ADDR 0xAA
+#undef	      AUTO_MEMORY_CONFIG
+#define	       DIMM_READ_ADDR 0xAB
+#define	       DIMM_WRITE_ADDR 0xAA
 
 
-#define CPC0_PLLMR0  (CNTRL_DCR_BASE+0x0)  /* PLL mode 0 register          */
+#define CPC0_PLLMR0  (CNTRL_DCR_BASE+0x0)  /* PLL mode 0 register	   */
 #define CPC0_BOOT    (CNTRL_DCR_BASE+0x1)  /* Chip Clock Status register   */
-#define CPC0_CR1     (CNTRL_DCR_BASE+0x2)  /* Chip Control 1 register      */
+#define CPC0_CR1     (CNTRL_DCR_BASE+0x2)  /* Chip Control 1 register	   */
 #define CPC0_EPRCSR  (CNTRL_DCR_BASE+0x3)  /* EMAC PHY Rcv Clk Src register*/
-#define CPC0_PLLMR1  (CNTRL_DCR_BASE+0x4)  /* PLL mode 1 register          */
-#define CPC0_UCR     (CNTRL_DCR_BASE+0x5)  /* UART Control register        */
-#define CPC0_SRR     (CNTRL_DCR_BASE+0x6)  /* Soft Reset register          */
-#define CPC0_JTAGID  (CNTRL_DCR_BASE+0x7)  /* JTAG ID register             */
-#define CPC0_SPARE   (CNTRL_DCR_BASE+0x8)  /* Spare DCR                    */
-#define CPC0_PCI     (CNTRL_DCR_BASE+0x9)  /* PCI Control register         */
+#define CPC0_PLLMR1  (CNTRL_DCR_BASE+0x4)  /* PLL mode 1 register	   */
+#define CPC0_UCR     (CNTRL_DCR_BASE+0x5)  /* UART Control register	   */
+#define CPC0_SRR     (CNTRL_DCR_BASE+0x6)  /* Soft Reset register	   */
+#define CPC0_JTAGID  (CNTRL_DCR_BASE+0x7)  /* JTAG ID register		   */
+#define CPC0_SPARE   (CNTRL_DCR_BASE+0x8)  /* Spare DCR			   */
+#define CPC0_PCI     (CNTRL_DCR_BASE+0x9)  /* PCI Control register	   */
 
 /* Defines for CPC0_PLLMR1 Register fields */
-#define PLL_ACTIVE                 0x80000000
-#define CPC0_PLLMR1_SSCS           0x80000000
-#define PLL_RESET                  0x40000000
-#define CPC0_PLLMR1_PLLR           0x40000000
+#define PLL_ACTIVE		   0x80000000
+#define CPC0_PLLMR1_SSCS	   0x80000000
+#define PLL_RESET		   0x40000000
+#define CPC0_PLLMR1_PLLR	   0x40000000
     /* Feedback multiplier */
-#define PLL_FBKDIV                 0x00F00000
-#define CPC0_PLLMR1_FBDV           0x00F00000
-#define PLL_FBKDIV_16              0x00000000
-#define PLL_FBKDIV_1               0x00100000
-#define PLL_FBKDIV_2               0x00200000
-#define PLL_FBKDIV_3               0x00300000
-#define PLL_FBKDIV_4               0x00400000
-#define PLL_FBKDIV_5               0x00500000
-#define PLL_FBKDIV_6               0x00600000
-#define PLL_FBKDIV_7               0x00700000
-#define PLL_FBKDIV_8               0x00800000
-#define PLL_FBKDIV_9               0x00900000
-#define PLL_FBKDIV_10              0x00A00000
-#define PLL_FBKDIV_11              0x00B00000
-#define PLL_FBKDIV_12              0x00C00000
-#define PLL_FBKDIV_13              0x00D00000
-#define PLL_FBKDIV_14              0x00E00000
-#define PLL_FBKDIV_15              0x00F00000
+#define PLL_FBKDIV		   0x00F00000
+#define CPC0_PLLMR1_FBDV	   0x00F00000
+#define PLL_FBKDIV_16		   0x00000000
+#define PLL_FBKDIV_1		   0x00100000
+#define PLL_FBKDIV_2		   0x00200000
+#define PLL_FBKDIV_3		   0x00300000
+#define PLL_FBKDIV_4		   0x00400000
+#define PLL_FBKDIV_5		   0x00500000
+#define PLL_FBKDIV_6		   0x00600000
+#define PLL_FBKDIV_7		   0x00700000
+#define PLL_FBKDIV_8		   0x00800000
+#define PLL_FBKDIV_9		   0x00900000
+#define PLL_FBKDIV_10		   0x00A00000
+#define PLL_FBKDIV_11		   0x00B00000
+#define PLL_FBKDIV_12		   0x00C00000
+#define PLL_FBKDIV_13		   0x00D00000
+#define PLL_FBKDIV_14		   0x00E00000
+#define PLL_FBKDIV_15		   0x00F00000
     /* Forward A divisor */
-#define PLL_FWDDIVA                0x00070000
-#define CPC0_PLLMR1_FWDVA          0x00070000
-#define PLL_FWDDIVA_8              0x00000000
-#define PLL_FWDDIVA_7              0x00010000
-#define PLL_FWDDIVA_6              0x00020000
-#define PLL_FWDDIVA_5              0x00030000
-#define PLL_FWDDIVA_4              0x00040000
-#define PLL_FWDDIVA_3              0x00050000
-#define PLL_FWDDIVA_2              0x00060000
-#define PLL_FWDDIVA_1              0x00070000
+#define PLL_FWDDIVA		   0x00070000
+#define CPC0_PLLMR1_FWDVA	   0x00070000
+#define PLL_FWDDIVA_8		   0x00000000
+#define PLL_FWDDIVA_7		   0x00010000
+#define PLL_FWDDIVA_6		   0x00020000
+#define PLL_FWDDIVA_5		   0x00030000
+#define PLL_FWDDIVA_4		   0x00040000
+#define PLL_FWDDIVA_3		   0x00050000
+#define PLL_FWDDIVA_2		   0x00060000
+#define PLL_FWDDIVA_1		   0x00070000
     /* Forward B divisor */
-#define PLL_FWDDIVB                0x00007000
-#define CPC0_PLLMR1_FWDVB          0x00007000
-#define PLL_FWDDIVB_8              0x00000000
-#define PLL_FWDDIVB_7              0x00001000
-#define PLL_FWDDIVB_6              0x00002000
-#define PLL_FWDDIVB_5              0x00003000
-#define PLL_FWDDIVB_4              0x00004000
-#define PLL_FWDDIVB_3              0x00005000
-#define PLL_FWDDIVB_2              0x00006000
-#define PLL_FWDDIVB_1              0x00007000
+#define PLL_FWDDIVB		   0x00007000
+#define CPC0_PLLMR1_FWDVB	   0x00007000
+#define PLL_FWDDIVB_8		   0x00000000
+#define PLL_FWDDIVB_7		   0x00001000
+#define PLL_FWDDIVB_6		   0x00002000
+#define PLL_FWDDIVB_5		   0x00003000
+#define PLL_FWDDIVB_4		   0x00004000
+#define PLL_FWDDIVB_3		   0x00005000
+#define PLL_FWDDIVB_2		   0x00006000
+#define PLL_FWDDIVB_1		   0x00007000
     /* PLL tune bits */
-#define PLL_TUNE_MASK            0x000003FF
-#define PLL_TUNE_2_M_3           0x00000133     /*  2 <= M <= 3               */
-#define PLL_TUNE_4_M_6           0x00000134     /*  3 <  M <= 6               */
-#define PLL_TUNE_7_M_10          0x00000138     /*  6 <  M <= 10              */
-#define PLL_TUNE_11_M_14         0x0000013C     /* 10 <  M <= 14              */
-#define PLL_TUNE_15_M_40         0x0000023E     /* 14 <  M <= 40              */
-#define PLL_TUNE_VCO_LOW         0x00000000     /* 500MHz <= VCO <=  800MHz   */
-#define PLL_TUNE_VCO_HI          0x00000080     /* 800MHz <  VCO <= 1000MHz   */
+#define PLL_TUNE_MASK		 0x000003FF
+#define PLL_TUNE_2_M_3		 0x00000133	/*  2 <= M <= 3		      */
+#define PLL_TUNE_4_M_6		 0x00000134	/*  3 <	 M <= 6		      */
+#define PLL_TUNE_7_M_10		 0x00000138	/*  6 <	 M <= 10	      */
+#define PLL_TUNE_11_M_14	 0x0000013C	/* 10 <	 M <= 14	      */
+#define PLL_TUNE_15_M_40	 0x0000023E	/* 14 <	 M <= 40	      */
+#define PLL_TUNE_VCO_LOW	 0x00000000	/* 500MHz <= VCO <=  800MHz   */
+#define PLL_TUNE_VCO_HI		 0x00000080	/* 800MHz <  VCO <= 1000MHz   */
 
 /* Defines for CPC0_PLLMR0 Register fields */
     /* CPU divisor */
-#define PLL_CPUDIV                 0x00300000
-#define CPC0_PLLMR0_CCDV           0x00300000
-#define PLL_CPUDIV_1               0x00000000
-#define PLL_CPUDIV_2               0x00100000
-#define PLL_CPUDIV_3               0x00200000
-#define PLL_CPUDIV_4               0x00300000
+#define PLL_CPUDIV		   0x00300000
+#define CPC0_PLLMR0_CCDV	   0x00300000
+#define PLL_CPUDIV_1		   0x00000000
+#define PLL_CPUDIV_2		   0x00100000
+#define PLL_CPUDIV_3		   0x00200000
+#define PLL_CPUDIV_4		   0x00300000
     /* PLB divisor */
-#define PLL_PLBDIV                 0x00030000
-#define CPC0_PLLMR0_CBDV           0x00030000
-#define PLL_PLBDIV_1               0x00000000
-#define PLL_PLBDIV_2               0x00010000
-#define PLL_PLBDIV_3               0x00020000
-#define PLL_PLBDIV_4               0x00030000
+#define PLL_PLBDIV		   0x00030000
+#define CPC0_PLLMR0_CBDV	   0x00030000
+#define PLL_PLBDIV_1		   0x00000000
+#define PLL_PLBDIV_2		   0x00010000
+#define PLL_PLBDIV_3		   0x00020000
+#define PLL_PLBDIV_4		   0x00030000
     /* OPB divisor */
-#define PLL_OPBDIV                 0x00003000
-#define CPC0_PLLMR0_OPDV           0x00003000
-#define PLL_OPBDIV_1               0x00000000
-#define PLL_OPBDIV_2               0x00001000
-#define PLL_OPBDIV_3               0x00002000
-#define PLL_OPBDIV_4               0x00003000
+#define PLL_OPBDIV		   0x00003000
+#define CPC0_PLLMR0_OPDV	   0x00003000
+#define PLL_OPBDIV_1		   0x00000000
+#define PLL_OPBDIV_2		   0x00001000
+#define PLL_OPBDIV_3		   0x00002000
+#define PLL_OPBDIV_4		   0x00003000
     /* EBC divisor */
-#define PLL_EXTBUSDIV              0x00000300
-#define CPC0_PLLMR0_EPDV           0x00000300
-#define PLL_EXTBUSDIV_2            0x00000000
-#define PLL_EXTBUSDIV_3            0x00000100
-#define PLL_EXTBUSDIV_4            0x00000200
-#define PLL_EXTBUSDIV_5            0x00000300
+#define PLL_EXTBUSDIV		   0x00000300
+#define CPC0_PLLMR0_EPDV	   0x00000300
+#define PLL_EXTBUSDIV_2		   0x00000000
+#define PLL_EXTBUSDIV_3		   0x00000100
+#define PLL_EXTBUSDIV_4		   0x00000200
+#define PLL_EXTBUSDIV_5		   0x00000300
     /* MAL divisor */
-#define PLL_MALDIV                 0x00000030
-#define CPC0_PLLMR0_MPDV           0x00000030
-#define PLL_MALDIV_1               0x00000000
-#define PLL_MALDIV_2               0x00000010
-#define PLL_MALDIV_3               0x00000020
-#define PLL_MALDIV_4               0x00000030
+#define PLL_MALDIV		   0x00000030
+#define CPC0_PLLMR0_MPDV	   0x00000030
+#define PLL_MALDIV_1		   0x00000000
+#define PLL_MALDIV_2		   0x00000010
+#define PLL_MALDIV_3		   0x00000020
+#define PLL_MALDIV_4		   0x00000030
     /* PCI divisor */
-#define PLL_PCIDIV                 0x00000003
-#define CPC0_PLLMR0_PPFD           0x00000003
-#define PLL_PCIDIV_1               0x00000000
-#define PLL_PCIDIV_2               0x00000001
-#define PLL_PCIDIV_3               0x00000002
-#define PLL_PCIDIV_4               0x00000003
+#define PLL_PCIDIV		   0x00000003
+#define CPC0_PLLMR0_PPFD	   0x00000003
+#define PLL_PCIDIV_1		   0x00000000
+#define PLL_PCIDIV_2		   0x00000001
+#define PLL_PCIDIV_3		   0x00000002
+#define PLL_PCIDIV_4		   0x00000003
 
 /* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
-#define PLLMR0_133_133_33_66_33  (PLL_CPUDIV_1 | PLL_PLBDIV_1 |  \
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |  \
+#define PLLMR0_133_133_33_66_33	 (PLL_CPUDIV_1 | PLL_PLBDIV_1 |	 \
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
 			      PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PLLMR1_133_133_33_66_33  (PLL_FBKDIV_4  |  \
+#define PLLMR1_133_133_33_66_33	 (PLL_FBKDIV_4	|  \
 			      PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |  \
 			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 #define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |  \
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
 			      PLL_MALDIV_1 | PLL_PCIDIV_4)
 #define PLLMR1_200_100_50_33 (PLL_FBKDIV_6  |  \
 			      PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
 			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-#define PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |  \
+#define PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |	\
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
 			      PLL_MALDIV_1 | PLL_PCIDIV_4)
 #define PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8  |  \
 			      PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
 			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-#define PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |  \
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |  \
+#define PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |	\
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
 			      PLL_MALDIV_1 | PLL_PCIDIV_2)
-#define PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10  |  \
+#define PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10	|  \
 			      PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
 			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
 
 #if   (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
 /* Model HI */
-#define PLLMR0_DEFAULT   PLLMR0_333_111_37_55_55
-#define PLLMR1_DEFAULT   PLLMR1_333_111_37_55_55
+#define PLLMR0_DEFAULT	 PLLMR0_333_111_37_55_55
+#define PLLMR1_DEFAULT	 PLLMR1_333_111_37_55_55
 /* Model ME */
 #elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
-#define PLLMR0_DEFAULT   PLLMR0_266_133_33_66_33
-#define PLLMR1_DEFAULT   PLLMR1_266_133_33_66_33
+#define PLLMR0_DEFAULT	 PLLMR0_266_133_33_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_266_133_33_66_33
 #else
 /* Model BA (default) */
-#define PLLMR0_DEFAULT   PLLMR0_133_133_33_66_33
-#define PLLMR1_DEFAULT   PLLMR1_133_133_33_66_33
+#define PLLMR0_DEFAULT	 PLLMR0_133_133_33_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_133_133_33_66_33
 
 #endif
 
diff --git a/include/configs/RPXsuper.h b/include/configs/RPXsuper.h
index 0abff11e3b..cdf716cb24 100644
--- a/include/configs/RPXsuper.h
+++ b/include/configs/RPXsuper.h
@@ -174,7 +174,7 @@
 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU   */
 #define CONFIG_RPXSUPER         1       /* on an Embedded Planet RPX Super Board  */
 
-#define CONFIG_BOARD_PRE_INIT	1	/* Call board_pre_init	*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h
index 13a0105b07..b64611bb89 100644
--- a/include/configs/VOH405.h
+++ b/include/configs/VOH405.h
@@ -34,13 +34,13 @@
  */
 
 #define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
-#define CONFIG_VOH405		1	/* ...on a VOH405 board 	*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_VOH405		1	/* ...on a VOH405 board		*/
 
-#define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */
-#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
 
-#define CONFIG_SYS_CLK_FREQ     33333334 /* external frequency to pll   */
+#define CONFIG_SYS_CLK_FREQ	33333334 /* external frequency to pll	*/
 
 #define CONFIG_BAUDRATE		9600
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
@@ -60,7 +60,7 @@
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_MII		1	/* MII PHY management		*/
-#define	CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
 
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_DHCP	| \
@@ -73,7 +73,7 @@
 				CFG_CMD_I2C	| \
 				CFG_CMD_MII	| \
 				CFG_CMD_PING	| \
-				CFG_CMD_EEPROM  )
+				CFG_CMD_EEPROM	)
 
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
@@ -81,12 +81,12 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
-#undef  CONFIG_WATCHDOG			/* watchdog disabled		*/
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
-#define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible*/
-#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address         */
+#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
+#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
 
-#define	CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 
 /*
  * Miscellaneous configurable options
@@ -96,45 +96,45 @@
 
 #undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
 #ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CFG_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 #define CFG_MAXARGS	16		/* max number of command args	*/
 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
 
-#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
 #define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
-#define CFG_BASE_BAUD       691200
-#undef CONFIG_UART1_CONSOLE            /* define for uart1 as console  */
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD	    691200
+#undef CONFIG_UART1_CONSOLE	       /* define for uart1 as console  */
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE      \
+#define CFG_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
 #define CFG_LOAD_ADDR	0x100000	/* default load address */
 #define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
-#define CONFIG_VERSION_VARIABLE	1       /* include version env variable */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
-#define CFG_RX_ETH_BUFFER	16      /* use 16 rx buffer on 405 emac */
+#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
 
 /*-----------------------------------------------------------------------
  * NAND-FLASH stuff
@@ -147,14 +147,14 @@
 #define ADDR_PAGE 2
 #define ADDR_COLUMN_PAGE 3
 
-#define NAND_ChipID_UNKNOWN 	0x00
+#define NAND_ChipID_UNKNOWN	0x00
 #define NAND_MAX_FLOORS 1
 #define NAND_MAX_CHIPS 1
 
-#define CFG_NAND_CE  (0x80000000 >> 1)  /* our CE is GPIO1 */
-#define CFG_NAND_CLE (0x80000000 >> 2)  /* our CLE is GPIO2 */
-#define CFG_NAND_ALE (0x80000000 >> 3)  /* our ALE is GPIO3 */
-#define CFG_NAND_RDY (0x80000000 >> 4)  /* our RDY is GPIO4 */
+#define CFG_NAND_CE  (0x80000000 >> 1)	/* our CE is GPIO1 */
+#define CFG_NAND_CLE (0x80000000 >> 2)	/* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3)	/* our ALE is GPIO3 */
+#define CFG_NAND_RDY (0x80000000 >> 4)	/* our RDY is GPIO4 */
 
 #define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
 #define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
@@ -173,46 +173,46 @@
  * PCI stuff
  *-----------------------------------------------------------------------
  */
-#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
-
-#define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_HOST	PCI_HOST_HOST   /* select pci host function     */
-#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-					/* resource configuration       */
-
-#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
-#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_HOST	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
+#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff
  *-----------------------------------------------------------------------
  */
-#undef  CONFIG_IDE_8xx_DIRECT               /* no pcmcia interface required */
-#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
+#undef	CONFIG_IDE_8xx_DIRECT		    /* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
 #define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
 
-#define	CFG_IDE_MAXBUS	        2		/* max. 2 IDE busses	*/
-#define	CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
+#define CFG_IDE_MAXBUS		2		/* max. 2 IDE busses	*/
+#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
 
-#define CONFIG_ATAPI	        1	/* ATAPI for Travelstar         */
+#define CONFIG_ATAPI		1	/* ATAPI for Travelstar		*/
 
-#define	CFG_ATA_BASE_ADDR	0xF0100000
-#define	CFG_ATA_IDE0_OFFSET	0x0000
-#define	CFG_ATA_IDE1_OFFSET	0x0010
+#define CFG_ATA_BASE_ADDR	0xF0100000
+#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CFG_ATA_IDE1_OFFSET	0x0010
 
 #define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
-#define	CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
 #define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
 
 /*
@@ -232,22 +232,22 @@
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
-#define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
-#define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
-#define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
-#define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS     1           /* ! second bank contains U-Boot */
+#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -270,13 +270,13 @@
 /*-----------------------------------------------------------------------
  * Environment Variable setup
  */
-#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET          0x100   /* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE            0x700   /* 2048 bytes may be used for env vars*/
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
 				   /* total size of a CAT24WC16 is 2048 bytes */
 
 #define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		242		        /* NVRAM size		*/
+#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
 
 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC16) for environment
@@ -288,20 +288,20 @@
 #define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT24WC08		*/
 #if 0 /* test-only */
 /* CAT24WC08/16... */
-#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
 #define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
 #define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
-					/* last	4 bits of the address	*/
+					/* last 4 bits of the address	*/
 #else
 /* CAT24WC32/64... */
-#define CFG_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CFG_I2C_EEPROM_ADDR_LEN 2	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
 #define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x01
 #define CFG_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
 					/* 32 byte page write mode using*/
-					/* last	5 bits of the address	*/
+					/* last 5 bits of the address	*/
 #endif
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 #define CFG_EEPROM_PAGE_WRITE_ENABLE
@@ -309,8 +309,8 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's    */
-					/* have only 8kB, 16kB is save here     */
+#define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's	*/
+					/* have only 8kB, 16kB is save here	*/
 #define CFG_CACHELINE_SIZE	32	/* ...			*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
@@ -320,63 +320,63 @@
  * External Bus Controller (EBC) Setup
  */
 
-#define CAN_BA          0xF0000000          /* CAN Base Address                 */
-#define DUART0_BA       0xF0000400          /* DUART Base Address               */
-#define DUART1_BA       0xF0000408          /* DUART Base Address               */
-#define RTC_BA          0xF0000500          /* RTC Base Address                 */
-#define VGA_BA          0xF1000000          /* Epson VGA Base Address           */
-#define CFG_NAND_BASE   0xF4000000          /* NAND FLASH Base Address          */
+#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
+#define DUART0_BA	0xF0000400	    /* DUART Base Address		*/
+#define DUART1_BA	0xF0000408	    /* DUART Base Address		*/
+#define RTC_BA		0xF0000500	    /* RTC Base Address			*/
+#define VGA_BA		0xF1000000	    /* Epson VGA Base Address		*/
+#define CFG_NAND_BASE	0xF4000000	    /* NAND FLASH Base Address		*/
 
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
-#define CFG_EBC_PB0AP           0x92015480
-/*#define CFG_EBC_PB0AP           0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
-#define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CFG_EBC_PB0AP		0x92015480
+/*#define CFG_EBC_PB0AP		  0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
-/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization                      */
-#define CFG_EBC_PB1AP           0x92015480
-#define CFG_EBC_PB1CR           0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit  */
+/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
+#define CFG_EBC_PB1AP		0x92015480
+#define CFG_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization              */
-#define CFG_EBC_PB2AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
+#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization     */
-#define CFG_EBC_PB3AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR           0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization	*/
+#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 
-/* Memory Bank 4 (Epson VGA) initialization                                     */
-#define CFG_EBC_PB4AP   0x03805380   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
-#define CFG_EBC_PB4CR   VGA_BA | 0x7A000    /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */
+/* Memory Bank 4 (Epson VGA) initialization					*/
+#define CFG_EBC_PB4AP	0x03805380   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
+#define CFG_EBC_PB4CR	VGA_BA | 0x7A000    /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */
 
 /*-----------------------------------------------------------------------
  * FPGA stuff
  */
 
-#define CFG_FPGA_BASE_ADDR 0xF0100100       /* FPGA internal Base Address       */
+#define CFG_FPGA_BASE_ADDR 0xF0100100	    /* FPGA internal Base Address	*/
 
 /* FPGA internal regs */
-#define CFG_FPGA_CTRL           0x000
+#define CFG_FPGA_CTRL		0x000
 
 /* FPGA Control Reg */
-#define CFG_FPGA_CTRL_CF_RESET  0x0001
-#define CFG_FPGA_CTRL_WDI       0x0002
+#define CFG_FPGA_CTRL_CF_RESET	0x0001
+#define CFG_FPGA_CTRL_WDI	0x0002
 #define CFG_FPGA_CTRL_PS2_RESET 0x0020
 
-#define CFG_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
-#define CFG_FPGA_MAX_SIZE       128*1024    /* 128kByte is enough for XC2S50E*/
+#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CFG_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/
 
 /* FPGA program pin configuration */
-#define CFG_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */
+#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
+#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM        1
+#define CFG_TEMP_STACK_OCM	  1
 
 /* On Chip Memory location */
 #define CFG_OCM_DATA_ADDR	0xF8000000
@@ -386,13 +386,13 @@
 
 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Definitions for GPIO setup (PPC405EP specific)
  *
- * GPIO0[0]     - External Bus Controller BLAST output
- * GPIO0[1-9]   - Instruction trace outputs -> GPIO
+ * GPIO0[0]	- External Bus Controller BLAST output
+ * GPIO0[1-9]	- Instruction trace outputs -> GPIO
  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
@@ -400,15 +400,15 @@
  * GPIO0[28-29] - UART1 data signal input/output
  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
  */
-#define CFG_GPIO0_OSRH          0x40000550
-#define CFG_GPIO0_OSRL          0x00000110
-#define CFG_GPIO0_ISR1H         0x00000000
-#define CFG_GPIO0_ISR1L         0x15555445
-#define CFG_GPIO0_TSRH          0x00000000
-#define CFG_GPIO0_TSRL          0x00000000
-#define CFG_GPIO0_TCR           0xF7FE0014
+#define CFG_GPIO0_OSRH		0x40000550
+#define CFG_GPIO0_OSRL		0x00000110
+#define CFG_GPIO0_ISR1H		0x00000000
+#define CFG_GPIO0_ISR1L		0x15555445
+#define CFG_GPIO0_TSRH		0x00000000
+#define CFG_GPIO0_TSRL		0x00000000
+#define CFG_GPIO0_TCR		0xF7FE0014
 
-#define CFG_DUART_RST           (0x80000000 >> 14)
+#define CFG_DUART_RST		(0x80000000 >> 14)
 
 /*
  * Internal Definitions
@@ -423,16 +423,16 @@
  * This value will be set if iic boot eprom is disabled.
  */
 #if 1
-#define PLLMR0_DEFAULT   PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT   PLLMR1_266_133_66_33
+#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
 #endif
 #if 0
-#define PLLMR0_DEFAULT   PLLMR0_200_100_50_33
-#define PLLMR1_DEFAULT   PLLMR1_200_100_50_33
+#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
+#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
 #endif
 #if 0
-#define PLLMR0_DEFAULT   PLLMR0_133_66_66_33
-#define PLLMR1_DEFAULT   PLLMR1_133_66_66_33
+#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
 #endif
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h
index 7ae1c7059c..ae3f1f43ae 100644
--- a/include/configs/W7OLMC.h
+++ b/include/configs/W7OLMC.h
@@ -38,7 +38,8 @@
 #define CONFIG_W7O		1		/* ...on a Wave 7 Optics board	*/
 #define CONFIG_W7OLMC		1		/* ...specifically an LMC	*/
 
-#define CONFIG_BOARD_PRE_INIT	1		/* Call board_pre_init	*/
+#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f	*/
+#define	CONFIG_MISC_INIT_F	1		/* and misc_init_f()		*/
 
 #define CONFIG_SYS_CLK_FREQ	33333333	/* external frequency to pll	*/
 
diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h
index 89373b9040..2a78082fe2 100644
--- a/include/configs/W7OLMG.h
+++ b/include/configs/W7OLMG.h
@@ -38,7 +38,8 @@
 #define CONFIG_W7O		1		/* ...on a Wave 7 Optics board	*/
 #define CONFIG_W7OLMG		1		/* ...specifically an LMG	*/
 
-#define CONFIG_BOARD_PRE_INIT	1		/* Call board_pre_init	*/
+#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f	*/
+#define	CONFIG_MISC_INIT_F	1		/* and misc_init_f()		*/
 
 #define CONFIG_SYS_CLK_FREQ	33333333	/* external frequency to pll	*/
 
diff --git a/include/configs/WALNUT405.h b/include/configs/WALNUT405.h
index cdc9a3cc21..9155ce84e0 100644
--- a/include/configs/WALNUT405.h
+++ b/include/configs/WALNUT405.h
@@ -37,7 +37,7 @@
 #define CONFIG_4xx		1	/* ...member of PPC4xx family   */
 #define CONFIG_WALNUT405	1	/* ...on a WALNUT405 board	*/
 
-#define CONFIG_BOARD_PRE_INIT	1	/* Call board_pre_init	*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
 
 #define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
 
diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h
index a46b9fa2a8..673d9e5b5a 100644
--- a/include/configs/ZPC1900.h
+++ b/include/configs/ZPC1900.h
@@ -33,7 +33,7 @@
 
 #undef DEBUG
 
-#undef CONFIG_BOARD_PRE_INIT		/* Don't call board_pre_init   */
+#undef CONFIG_BOARD_EARLY_INIT_F	/* Don't call board_early_init_f   */
 
 /* Allow serial number (serial) and MAC address (ethaddr) to be overwritten */
 #define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/ZUMA.h b/include/configs/ZUMA.h
index 3fde23838f..578f152fde 100644
--- a/include/configs/ZUMA.h
+++ b/include/configs/ZUMA.h
@@ -53,7 +53,7 @@
 
 /* which initialization functions to call for this board */
 #define CONFIG_MISC_INIT_R
-#define CONFIG_BOARD_PRE_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
 #define CFG_BOARD_ASM_INIT
 
 #define CFG_BOARD_NAME		"Zuma APv2"
diff --git a/include/configs/bms2003.h b/include/configs/bms2003.h
index 810a5387e9..40baad0fd3 100644
--- a/include/configs/bms2003.h
+++ b/include/configs/bms2003.h
@@ -50,8 +50,9 @@
 #define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
 
 #define CONFIG_PS2KBD			/* AT-PS/2 Keyboard		*/
-#define CONFIG_PS2MULT			/* .. on PS/2 Multiplexer		*/
+#define CONFIG_PS2MULT			/* .. on PS/2 Multiplexer	*/
 #define CONFIG_PS2SERIAL	2	/* .. on COM3			*/
+#define CONFIG_PS2MULT_DELAY	(CFG_HZ/2)	/* Initial delay	*/
 
 #define CONFIG_BOOTCOUNT_LIMIT
 
@@ -83,7 +84,8 @@
 	""
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
-#define CONFIG_MISC_INIT_R  1
+#define	CONFIG_BOARD_EARLY_INIT_R 1
+#define CONFIG_MISC_INIT_R	  1
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
diff --git a/include/configs/cogent_mpc8260.h b/include/configs/cogent_mpc8260.h
index d7305272d2..b3ec89b05b 100644
--- a/include/configs/cogent_mpc8260.h
+++ b/include/configs/cogent_mpc8260.h
@@ -36,6 +36,8 @@
 #define CONFIG_MPC8260		1	/* This is an MPC8260 CPU	*/
 #define CONFIG_COGENT		1	/* using Cogent Modular Architecture */
 
+#define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/
+
 /* Cogent Modular Architecture options */
 #define CONFIG_CMA282		1	/* ...on a CMA282 CPU module	*/
 #define CONFIG_CMA111		1	/* ...on a CMA111 motherboard	*/
diff --git a/include/configs/cogent_mpc8xx.h b/include/configs/cogent_mpc8xx.h
index 51d4a7a7f0..80962d35fd 100644
--- a/include/configs/cogent_mpc8xx.h
+++ b/include/configs/cogent_mpc8xx.h
@@ -36,6 +36,8 @@
 #define CONFIG_MPC860		1	/* This is an MPC860 CPU	*/
 #define CONFIG_COGENT		1	/* using Cogent Modular Architecture */
 
+#define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/
+
 /* Cogent Modular Architecture options */
 #define CONFIG_CMA286_60_OLD	1	/* ...on an old CMA286-60 CPU module */
 #define CONFIG_CMA102		1	/* ...on a CMA102 motherboard	*/
diff --git a/include/configs/ep8260.h b/include/configs/ep8260.h
index f1b2cc14f9..8af139b887 100644
--- a/include/configs/ep8260.h
+++ b/include/configs/ep8260.h
@@ -309,7 +309,7 @@
 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU   */
 #define CONFIG_EP8260           11      /* on an Embedded Planet EP8260 Board, Rev. 11 */
 
-#define CONFIG_BOARD_PRE_INIT	1	    /* Call board_pre_init	*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
diff --git a/include/configs/hymod.h b/include/configs/hymod.h
index 62b025cdf7..e5680a5d87 100644
--- a/include/configs/hymod.h
+++ b/include/configs/hymod.h
@@ -36,6 +36,8 @@
 #define CONFIG_MPC8260		1	/* This is an MPC8260 CPU	*/
 #define CONFIG_HYMOD		1	/* ...on a Hymod board		*/
 
+#define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/
+
 #define CONFIG_BOARD_POSTCLK_INIT	/* have board_postclk_init() function */
 
 /*
diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h
index bfced4420b..8645a974bc 100644
--- a/include/configs/lubbock.h
+++ b/include/configs/lubbock.h
@@ -44,7 +44,7 @@
 #define CONFIG_LUBBOCK		1	/* on an LUBBOCK Board	    */
 #define CONFIG_LCD		1
 #define CONFIG_MMC		1
-#define BOARD_POST_INIT		1
+#define BOARD_LATE_INIT		1
 
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
 
diff --git a/include/configs/lwmon.h b/include/configs/lwmon.h
index 04215a60ec..4917258ba3 100644
--- a/include/configs/lwmon.h
+++ b/include/configs/lwmon.h
@@ -39,7 +39,7 @@
 #define CONFIG_MPC823		1	/* This is a MPC823E CPU	*/
 #define CONFIG_LWMON		1	/* ...on a LWMON board		*/
 
-#define CONFIG_BOARD_PRE_INIT	1	/* Call board_pre_init		*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
 #define CONFIG_BOARD_POSTCLK_INIT 1	/* Call board_postclk_init	*/
 
 #define CONFIG_LCD		1	/* use LCD controller ...	*/
@@ -282,6 +282,9 @@
 
 #define CFG_FLASH_ERASE_TOUT	180000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	600	/* Timeout for Flash Write (in ms)	*/
+#define CFG_FLASH_USE_BUFFER_WRITE
+#define CFG_FLASH_BUFFER_WRITE_TOUT	2048	/* Timeout for Flash Buffer Write (in ms)	*/
+#define CFG_FLASH_BUFFER_SIZE	32   /* Buffer size */
 
 #if 1
 /* Put environment in flash which is much faster to boot */
diff --git a/include/configs/rsdproto.h b/include/configs/rsdproto.h
index d71b3e9f24..b1f6cb20ea 100644
--- a/include/configs/rsdproto.h
+++ b/include/configs/rsdproto.h
@@ -38,6 +38,8 @@
 #define CONFIG_MPC8260		1	/* This is an MPC8260 CPU	*/
 #define CONFIG_RSD_PROTO	1	/* on a R&S Protocol Board      */
 
+#define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/
+
 /*
  * select serial console configuration
  *
author	wdenk <wdenk>	2004-01-20 23:12:12 +0000
committer	wdenk <wdenk>	2004-01-20 23:12:12 +0000
commit	c837dcb1a316745092567bfe4fb266d0941884ff (patch)
tree	8b275e8c982d1b0a411ff33c08c86cd3d343eed6 /include/configs
parent	b0aef11c9f1f98d018adaa484f1e048fa626801e (diff)
download	u-boot-c837dcb1a316745092567bfe4fb266d0941884ff.tar.gz u-boot-c837dcb1a316745092567bfe4fb266d0941884ff.tar.xz u-boot-c837dcb1a316745092567bfe4fb266d0941884ff.zip