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| author | Jon Loeliger <jdl@freescale.com> | 2005-07-25 14:05:07 -0500 |
|---|---|---|
| committer | Jon Loeliger <jdl@freescale.com> | 2005-07-25 14:05:07 -0500 |
| commit | d9b94f28a442b0013caef99de084d7b72e2d4607 (patch) | |
| tree | 1b293a551e021a4a696717231ec03206d9f172de /include/configs/stxgp3.h | |
| parent | 288693abe1f7c23e69479fd85c2c0d8d7fdbf8f2 (diff) | |
| download | u-boot-d9b94f28a442b0013caef99de084d7b72e2d4607.tar.gz u-boot-d9b94f28a442b0013caef99de084d7b72e2d4607.tar.xz u-boot-d9b94f28a442b0013caef99de084d7b72e2d4607.zip | |
* Patch by Jon Loeliger, 2005-05-05
Implemented support for MPC8548CDS board.
Added DDR II support based on SPD values for MPC85xx boards.
This roll-up patch also includes bugfies for the previously
published patches:
DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
Diffstat (limited to 'include/configs/stxgp3.h')
| -rw-r--r-- | include/configs/stxgp3.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index b5684d334b..e218597db0 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -227,14 +227,16 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_MPC85XX_TSEC1 1 +#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" #define CONFIG_MPC85XX_TSEC2 1 +#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" #undef CONFIG_MPS85XX_FEC #define TSEC1_PHY_ADDR 2 #define TSEC2_PHY_ADDR 4 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 -#define CONFIG_ETHPRIME "MOTO ENET0" +#define CONFIG_ETHPRIME "TSEC0" #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ |