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| author | Markus Klotzbücher <Markus Klotzbümk@pollux.(none)> | 2006-02-22 14:05:44 +0100 |
|---|---|---|
| committer | Markus Klotzbücher <mk@pollux.(none)> | 2006-02-22 14:05:44 +0100 |
| commit | ff3c2a947889a9d60fc1c869565aa88b2e44b37b (patch) | |
| tree | 6e2a6b6a04f76312393b378fcab5e8a225385e75 /include/configs/delta.h | |
| parent | 48b6242aa1a5c8ef5f08abf30ebf9a49e3d95bd7 (diff) | |
| download | u-boot-ff3c2a947889a9d60fc1c869565aa88b2e44b37b.tar.gz u-boot-ff3c2a947889a9d60fc1c869565aa88b2e44b37b.tar.xz u-boot-ff3c2a947889a9d60fc1c869565aa88b2e44b37b.zip | |
SDRAM now working for delta board, but there are still aliasing problems,
we only see 64MB.
Diffstat (limited to 'include/configs/delta.h')
| -rw-r--r-- | include/configs/delta.h | 22 |
1 files changed, 12 insertions, 10 deletions
diff --git a/include/configs/delta.h b/include/configs/delta.h index 7b923c22e9..786ed9a815 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -143,14 +143,14 @@ * Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ -#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_1 0x80000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x8000000 /* 128 MB */ +#define PHYS_SDRAM_2 0x88000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x8000000 /* 128 MB */ +#define PHYS_SDRAM_3 0x90000000 /* SDRAM Bank #3 */ +#define PHYS_SDRAM_3_SIZE 0x8000000 /* 128 MB */ +#define PHYS_SDRAM_4 0x98000000 /* SDRAM Bank #4 */ +#define PHYS_SDRAM_4_SIZE 0x8000000 /* 128 MB */ #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ #define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ @@ -158,8 +158,10 @@ #define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ #define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ -#define CFG_DRAM_BASE 0xa0000000 -#define CFG_DRAM_SIZE 0x04000000 +#define CFG_DRAM_BASE 0x80000000 /* at CS0 */ +#define CFG_DRAM_SIZE 0x20000000 /* 512 MB Ram */ + +#define CFG_SKIP_DRAM_SCRUB 1 #define CFG_FLASH_BASE PHYS_FLASH_1 |