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| author | Markus Klotzbuecher <mk@denx.de> | 2006-03-24 12:23:27 +0100 |
|---|---|---|
| committer | Markus Klotzbücher <mk@pollux.denx.de> | 2006-03-24 12:23:27 +0100 |
| commit | ba70d6a4170ebbec5513f01ceae66a200102ba9a (patch) | |
| tree | 2a3031d73fc67445a3792c870720fe6ce3cffff3 /include/configs/delta.h | |
| parent | 552fc624f28d5db7b25f38c4e104fb7255d7df6b (diff) | |
| download | u-boot-ba70d6a4170ebbec5513f01ceae66a200102ba9a.tar.gz u-boot-ba70d6a4170ebbec5513f01ceae66a200102ba9a.tar.xz u-boot-ba70d6a4170ebbec5513f01ceae66a200102ba9a.zip | |
delta board: DA9030 initialization and i2c support. Some minor changes to
make the pxa i2c driver work with the monahans cpu.
Diffstat (limited to 'include/configs/delta.h')
| -rw-r--r-- | include/configs/delta.h | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/include/configs/delta.h b/include/configs/delta.h index cb002f7263..eaa4c432b8 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -49,7 +49,6 @@ /* * Hardware drivers */ - #undef TURN_ON_ETHERNET #ifdef TURN_ON_ETHERNET # define CONFIG_DRIVER_SMC91111 1 @@ -59,6 +58,12 @@ # undef CONFIG_SMC_USE_IOFUNCS /* just for use with the kernel */ #endif +#define CONFIG_HARD_I2C 1 /* required for DA9030 access */ +#define CFG_I2C_SPEED 400000 /* I2C speed */ +#define CFG_I2C_SLAVE 1 /* I2C controllers address */ +#define DA9030_I2C_ADDR 0x49 /* I2C address of DA9030 */ +/* #define CONFIG_HW_WATCHDOG 1 /\* Required for hitting the DA9030 WD *\/ */ + /* * select serial console configuration */ @@ -73,8 +78,13 @@ #ifdef TURN_ON_ETHERNET # define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING) #else -# define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_ENV | CFG_CMD_NAND) \ - & ~(CFG_CMD_NET | CFG_CMD_FLASH | CFG_CMD_IMLS)) +# define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_ENV \ + | CFG_CMD_NAND \ + | CFG_CMD_I2C) \ + & ~(CFG_CMD_NET \ + | CFG_CMD_FLASH \ + | CFG_CMD_IMLS)) #endif @@ -121,7 +131,7 @@ #define CFG_LOAD_ADDR (CFG_DRAM_BASE + 0x8000) /* default load address */ -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_HZ 3250000 /* incrementer freq: 3.25 MHz */ #define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ /* valid baudrates */ |