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authorJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2008-12-14 10:29:39 +0100
committerWolfgang Denk <wd@denx.de>2008-12-14 10:55:30 +0100
commit3aed3aa2c128ce9fb39ca3f4e9385a7499e93dbf (patch)
treebde84327c29fa423337f5ee73c0ebdbf8cac27a3 /include/configs/PMC440.h
parent0e0c862efe7279e9609db74d758cd1b84c6c7209 (diff)
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Fix new found CFG_
Also fix some minor typos. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'include/configs/PMC440.h')
-rw-r--r--include/configs/PMC440.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h
index 7219bb8ae1..d0e3cda6c1 100644
--- a/include/configs/PMC440.h
+++ b/include/configs/PMC440.h
@@ -219,8 +219,8 @@
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
#endif
-#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
- /* 440EPx errata CHIP 11 */
+#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
+ /* 440EPx errata CHIP 11 */
/*-----------------------------------------------------------------------
* I2C
@@ -490,8 +490,8 @@
#endif
/* Memory Bank 1 (RESET) initialization */
-#define CFG_EBC_PB1AP 0x7f817200 //0x03017200
-#define CFG_EBC_PB1CR (CFG_RESET_BASE | 0x1c000)
+#define CONFIG_SYS_EBC_PB1AP 0x7f817200 //0x03017200
+#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_RESET_BASE | 0x1c000)
/* Memory Bank 4 (FPGA / 32Bit) initialization */
#define CONFIG_SYS_EBC_PB4AP 0x03840f40 /* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */