* The PS/2 mux on the BMS2003 board needs 450 ms after power on

  before we can access it; add delay in case we are faster (with no
  CF card inserted)

* Cleanup of some init functions

* Make sure SCC Ethernet is always stopped by the time we boot Linux
  to avoid Linux crashes by early packets coming in.

* Accelerate flash accesses on LWMON board by using buffered writes

1 files changed, 88 insertions, 88 deletions

diff --git a/include/configs/DU405.h b/include/configs/DU405.h
index 3e5fc3fd44..5a5415a13e 100644
--- a/include/configs/DU405.h
+++ b/include/configs/DU405.h
@@ -34,12 +34,12 @@
  */
 
 #define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
-#define CONFIG_DU405	        1	/* ...on a DU405 board	        */
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_DU405		1	/* ...on a DU405 board		*/
 
-#define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
 
-#define CONFIG_SYS_CLK_FREQ     25000000 /* external frequency to pll   */
+#define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll	*/
 
 #define CONFIG_BAUDRATE		9600
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
@@ -51,7 +51,7 @@
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_MII		1	/* MII PHY management		*/
-#define	CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
 
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_PCI	| \
@@ -59,7 +59,7 @@
 				CFG_CMD_IDE	| \
 				CFG_CMD_ELF	| \
 				CFG_CMD_DATE	| \
-				CFG_CMD_EEPROM  )
+				CFG_CMD_EEPROM	)
 
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
@@ -69,10 +69,10 @@
 
 #undef CONFIG_WATCHDOG			/* watchdog disabled		*/
 
-#define CONFIG_RTC_MC146818             /* BQ3285 is MC146818 compatible*/
-#define CFG_RTC_REG_BASE_ADDR	 0xF0000080 /* RTC Base Address         */
+#define CONFIG_RTC_MC146818		/* BQ3285 is MC146818 compatible*/
+#define CFG_RTC_REG_BASE_ADDR	 0xF0000080 /* RTC Base Address		*/
 
-#define	CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 
 /*
  * Miscellaneous configurable options
@@ -80,30 +80,30 @@
 #define CFG_LONGHELP			/* undef to save memory		*/
 #define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 #define CFG_MAXARGS	16		/* max number of command args	*/
 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
 #define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define CFG_EXT_SERIAL_CLOCK    11059200  /* use external serial clock  */
+#define CFG_EXT_SERIAL_CLOCK	11059200  /* use external serial clock	*/
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE      \
+#define CFG_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
 #define CFG_LOAD_ADDR	0x100000	/* default load address */
 #define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
@@ -111,44 +111,44 @@
  * PCI stuff
  *-----------------------------------------------------------------------
  */
-#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
 
-#define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
-#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-					/* resource configuration       */
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_AUTO	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
 
-#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
 
-#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
+#define CONFIG_PCI_BOOTDELAY	0	/* enable pci bootdelay variable*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0404  /* PCI Device ID: CPCI-ISER4    */
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xff000001      /* 16MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CFG_PCI_PTM2LA  0xffe00000      /* point to flash               */
-#define CFG_PCI_PTM2MS  0xffe00001      /* 2MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0404	/* PCI Device ID: CPCI-ISER4	*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0xff000001	/* 16MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0xffe00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xffe00001	/* 2MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff
  *-----------------------------------------------------------------------
  */
-#undef  CONFIG_IDE_8xx_DIRECT           /* no pcmcia interface required */
-#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
-#undef  CONFIG_IDE_RESET                /* no reset for ide supported   */
+#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+#undef	CONFIG_IDE_RESET		/* no reset for ide supported	*/
 
-#define	CFG_IDE_MAXBUS	        1		/* max. 1 IDE busses	*/
-#define	CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+#define CFG_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
+#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
 
-#define	CFG_ATA_BASE_ADDR	0xF0100000
-#define	CFG_ATA_IDE0_OFFSET	0x0000
+#define CFG_ATA_BASE_ADDR	0xF0100000
+#define CFG_ATA_IDE0_OFFSET	0x0000
 
 #define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
-#define	CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
 #define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
 
 /*-----------------------------------------------------------------------
@@ -177,18 +177,18 @@
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
-#define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
-#define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
-#define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
-#define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC08) for environment
@@ -198,18 +198,18 @@
 #define CFG_I2C_SLAVE		0x7F
 
 #define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
 #define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
 #define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
-					/* last	4 bits of the address	*/
+					/* last 4 bits of the address	*/
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 
-#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE            0x400   /* 1024 bytes may be used for env vars */
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x400	/* 1024 bytes may be used for env vars */
 				   /* total size of a CAT24WC08 is 1024 bytes */
 
 /*-----------------------------------------------------------------------
@@ -234,48 +234,48 @@
  * External Bus Controller (EBC) Setup
  */
 
-#define FLASH0_BA       0xFFC00000          /* FLASH 0 Base Address             */
-#define FLASH1_BA       0xFF800000          /* FLASH 1 Base Address             */
-#define CAN_BA          0xF0000000          /* CAN Base Address                 */
-#define DUART_BA        0xF0300000          /* DUART Base Address               */
-#define CF_BA           0xF0100000          /* CompactFlash Base Address        */
-#define SRAM_BA         0xF0200000          /* SRAM Base Address                */
-#define DURAG_IO_BA     0xF0400000          /* DURAG Bus IO Base Address        */
-#define DURAG_MEM_BA    0xF0500000          /* DURAG Bus Mem Base Address       */
+#define FLASH0_BA	0xFFC00000	    /* FLASH 0 Base Address		*/
+#define FLASH1_BA	0xFF800000	    /* FLASH 1 Base Address		*/
+#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
+#define DUART_BA	0xF0300000	    /* DUART Base Address		*/
+#define CF_BA		0xF0100000	    /* CompactFlash Base Address	*/
+#define SRAM_BA		0xF0200000	    /* SRAM Base Address		*/
+#define DURAG_IO_BA	0xF0400000	    /* DURAG Bus IO Base Address	*/
+#define DURAG_MEM_BA	0xF0500000	    /* DURAG Bus Mem Base Address	*/
 
-#define FPGA_MODE_REG   (DUART_BA+0x80)     /* FPGA Mode Register               */
+#define FPGA_MODE_REG	(DUART_BA+0x80)	    /* FPGA Mode Register		*/
 
-/* Memory Bank 0 (Flash Bank 0) initialization                                  */
-#define CFG_EBC_PB0AP   0x92015480
-#define CFG_EBC_PB0CR   FLASH0_BA | 0x5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CFG_EBC_PB0AP	0x92015480
+#define CFG_EBC_PB0CR	FLASH0_BA | 0x5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
-/* Memory Bank 1 (Flash Bank 1) initialization                                  */
-#define CFG_EBC_PB1AP   0x92015480
-#define CFG_EBC_PB1CR   FLASH1_BA | 0x5A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+/* Memory Bank 1 (Flash Bank 1) initialization					*/
+#define CFG_EBC_PB1AP	0x92015480
+#define CFG_EBC_PB1CR	FLASH1_BA | 0x5A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
 
-/* Memory Bank 2 (CAN0) initialization                                          */
-#define CFG_EBC_PB2AP   0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR   CAN_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+/* Memory Bank 2 (CAN0) initialization						*/
+#define CFG_EBC_PB2AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR	CAN_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 3 (DUART) initialization                                         */
-#define CFG_EBC_PB3AP   0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR   DUART_BA | 0x18000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit  */
+/* Memory Bank 3 (DUART) initialization						*/
+#define CFG_EBC_PB3AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR	DUART_BA | 0x18000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 4 (CompactFlash IDE) initialization                              */
-#define CFG_EBC_PB4AP   0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB4CR   CF_BA | 0x1A000     /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+/* Memory Bank 4 (CompactFlash IDE) initialization				*/
+#define CFG_EBC_PB4AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB4CR	CF_BA | 0x1A000	    /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 
-/* Memory Bank 5 (SRAM) initialization                                          */
-#define CFG_EBC_PB5AP   0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB5CR   SRAM_BA | 0x1A000   /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */
+/* Memory Bank 5 (SRAM) initialization						*/
+#define CFG_EBC_PB5AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB5CR	SRAM_BA | 0x1A000   /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */
 
-/* Memory Bank 6 (DURAG Bus IO Space) initialization                            */
-#define CFG_EBC_PB6AP   0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB6CR   DURAG_IO_BA | 0x18000 /* BAS=0xF04,BS=1MB,BU=R/W,BW=8bit*/
+/* Memory Bank 6 (DURAG Bus IO Space) initialization				*/
+#define CFG_EBC_PB6AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB6CR	DURAG_IO_BA | 0x18000 /* BAS=0xF04,BS=1MB,BU=R/W,BW=8bit*/
 
-/* Memory Bank 7 (DURAG Bus Mem Space) initialization                           */
-#define CFG_EBC_PB7AP   0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB7CR   DURAG_MEM_BA | 0x18000 /* BAS=0xF05,BS=1MB,BU=R/W,BW=8bit */
+/* Memory Bank 7 (DURAG Bus Mem Space) initialization				*/
+#define CFG_EBC_PB7AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB7CR	DURAG_MEM_BA | 0x18000 /* BAS=0xF05,BS=1MB,BU=R/W,BW=8bit */
 
 
 /*-----------------------------------------------------------------------
@@ -283,7 +283,7 @@
  */
 
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM        1
+#define CFG_TEMP_STACK_OCM	  1
 
 /* On Chip Memory location */
 #define CFG_OCM_DATA_ADDR	0xF8000000
@@ -293,7 +293,7 @@
 #define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
 
 /*