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| author | Kumar Gala <galak@kernel.crashing.org> | 2008-01-08 01:22:21 -0600 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2008-01-09 16:25:04 -0600 |
| commit | b009f3eca99bb7b9e6ba6639a8909a138dd5e9fe (patch) | |
| tree | 4346cd75759fe027b7d6871e54965871efd80f94 /include/asm-ppc | |
| parent | b964e9368f45372aaf1da0c13fe56f6d81ae8e96 (diff) | |
| download | u-boot-b009f3eca99bb7b9e6ba6639a8909a138dd5e9fe.tar.gz u-boot-b009f3eca99bb7b9e6ba6639a8909a138dd5e9fe.tar.xz u-boot-b009f3eca99bb7b9e6ba6639a8909a138dd5e9fe.zip | |
85xx: Remove cache config from configs.h
Either use the standard defines in asm/cache.h or grab the information
at runtime from the L1CFG SPR.
Also, minor cleanup in cache.h to make the code a bit more readable.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/asm-ppc')
| -rw-r--r-- | include/asm-ppc/cache.h | 10 | ||||
| -rw-r--r-- | include/asm-ppc/processor.h | 4 |
2 files changed, 8 insertions, 6 deletions
diff --git a/include/asm-ppc/cache.h b/include/asm-ppc/cache.h index e29bfc2a7b..9d9b9717dd 100644 --- a/include/asm-ppc/cache.h +++ b/include/asm-ppc/cache.h @@ -8,15 +8,13 @@ #include <asm/processor.h> /* bytes per L1 cache line */ -#if !(defined(CONFIG_8xx) || defined(CONFIG_IOP480)) -#if defined(CONFIG_PPC64BRIDGE) +#if defined(CONFIG_8xx) || defined(CONFIG_IOP480) +#define L1_CACHE_SHIFT 4 +#elif defined(CONFIG_PPC64BRIDGE) #define L1_CACHE_SHIFT 7 #else #define L1_CACHE_SHIFT 5 -#endif /* PPC64 */ -#else -#define L1_CACHE_SHIFT 4 -#endif /* !(8xx || IOP480) */ +#endif #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 9fbbdf8c56..86c5df2dba 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -424,6 +424,8 @@ #define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */ /* e500 definitions */ +#define SPRN_L1CFG0 0x203 /* L1 Cache Configuration Register 0 */ +#define SPRN_L1CFG1 0x204 /* L1 Cache Configuration Register 1 */ #define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */ #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ @@ -621,6 +623,8 @@ #define MCSRR1 SPRN_MCSRR1 #define L1CSR0 SPRN_L1CSR0 #define L1CSR1 SPRN_L1CSR1 +#define L1CFG0 SPRN_L1CFG0 +#define L1CFG1 SPRN_L1CFG1 #define MCSR SPRN_MCSR #define MMUCSR0 SPRN_MMUCSR0 #define BUCSR SPRN_BUCSR |