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| author | richardretanubun <richardretanubun@ruggedcom.com> | 2008-09-29 18:28:23 -0400 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-10-18 21:54:00 +0200 |
| commit | c68a05feeb88de9fcf158e67ff6423c4cc988f88 (patch) | |
| tree | f970fa26b563081ab5a61196d696c6d2bd069018 /drivers/qe | |
| parent | 41410eee472b0f42e03a77f961bbc55ef58f3c01 (diff) | |
| download | u-boot-c68a05feeb88de9fcf158e67ff6423c4cc988f88.tar.gz u-boot-c68a05feeb88de9fcf158e67ff6423c4cc988f88.tar.xz u-boot-c68a05feeb88de9fcf158e67ff6423c4cc988f88.zip | |
Adds two more ethernet interface to 83xx
Added as a convenience for other platforms that uses MPC8360 (has 8 UCC).
Six eth interface is chosen because the platform I am using combines
UCC1&2 and UCC3&4 as 1000 Eth and the other four UCCs as 10/100 Eth.
Signed-off-by: Richard Retanubun <RichardRetanubun@RugggedCom.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Diffstat (limited to 'drivers/qe')
| -rw-r--r-- | drivers/qe/uec.c | 48 |
1 files changed, 47 insertions, 1 deletions
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index 85e2ad3587..0d48360a2d 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -123,8 +123,54 @@ static uec_info_t eth4_uec_info = { .enet_interface = CFG_UEC4_INTERFACE_MODE, }; #endif +#ifdef CONFIG_UEC_ETH5 +static uec_info_t eth5_uec_info = { + .uf_info = { + .ucc_num = CFG_UEC5_UCC_NUM, + .rx_clock = CFG_UEC5_RX_CLK, + .tx_clock = CFG_UEC5_TX_CLK, + .eth_type = CFG_UEC5_ETH_TYPE, + }, +#if (CFG_UEC5_ETH_TYPE == FAST_ETH) + .num_threads_tx = UEC_NUM_OF_THREADS_1, + .num_threads_rx = UEC_NUM_OF_THREADS_1, +#else + .num_threads_tx = UEC_NUM_OF_THREADS_4, + .num_threads_rx = UEC_NUM_OF_THREADS_4, +#endif + .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, + .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, + .tx_bd_ring_len = 16, + .rx_bd_ring_len = 16, + .phy_address = CFG_UEC5_PHY_ADDR, + .enet_interface = CFG_UEC5_INTERFACE_MODE, +}; +#endif +#ifdef CONFIG_UEC_ETH6 +static uec_info_t eth6_uec_info = { + .uf_info = { + .ucc_num = CFG_UEC6_UCC_NUM, + .rx_clock = CFG_UEC6_RX_CLK, + .tx_clock = CFG_UEC6_TX_CLK, + .eth_type = CFG_UEC6_ETH_TYPE, + }, +#if (CFG_UEC6_ETH_TYPE == FAST_ETH) + .num_threads_tx = UEC_NUM_OF_THREADS_1, + .num_threads_rx = UEC_NUM_OF_THREADS_1, +#else + .num_threads_tx = UEC_NUM_OF_THREADS_4, + .num_threads_rx = UEC_NUM_OF_THREADS_4, +#endif + .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, + .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, + .tx_bd_ring_len = 16, + .rx_bd_ring_len = 16, + .phy_address = CFG_UEC6_PHY_ADDR, + .enet_interface = CFG_UEC6_INTERFACE_MODE, +}; +#endif -#define MAXCONTROLLERS (4) +#define MAXCONTROLLERS (6) static struct eth_device *devlist[MAXCONTROLLERS]; |